1// This file is generated from a similarly-named Perl script in the BoringSSL 2// source tree. Do not edit by hand. 3 4#include <ring-core/asm_base.h> 5 6#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_ARM) && defined(__ELF__) 7.syntax unified 8 9.arch armv7-a 10.fpu neon 11 12#if defined(__thumb2__) 13.thumb 14#else 15.code 32 16#endif 17 18.text 19 20.type _vpaes_consts,%object 21.align 7 @ totally strategic alignment 22_vpaes_consts: 23.Lk_mc_forward:@ mc_forward 24.quad 0x0407060500030201, 0x0C0F0E0D080B0A09 25.quad 0x080B0A0904070605, 0x000302010C0F0E0D 26.quad 0x0C0F0E0D080B0A09, 0x0407060500030201 27.quad 0x000302010C0F0E0D, 0x080B0A0904070605 28.Lk_mc_backward:@ mc_backward 29.quad 0x0605040702010003, 0x0E0D0C0F0A09080B 30.quad 0x020100030E0D0C0F, 0x0A09080B06050407 31.quad 0x0E0D0C0F0A09080B, 0x0605040702010003 32.quad 0x0A09080B06050407, 0x020100030E0D0C0F 33.Lk_sr:@ sr 34.quad 0x0706050403020100, 0x0F0E0D0C0B0A0908 35.quad 0x030E09040F0A0500, 0x0B06010C07020D08 36.quad 0x0F060D040B020900, 0x070E050C030A0108 37.quad 0x0B0E0104070A0D00, 0x0306090C0F020508 38 39@ 40@ "Hot" constants 41@ 42.Lk_inv:@ inv, inva 43.quad 0x0E05060F0D080180, 0x040703090A0B0C02 44.quad 0x01040A060F0B0780, 0x030D0E0C02050809 45.Lk_ipt:@ input transform (lo, hi) 46.quad 0xC2B2E8985A2A7000, 0xCABAE09052227808 47.quad 0x4C01307D317C4D00, 0xCD80B1FCB0FDCC81 48.Lk_sbo:@ sbou, sbot 49.quad 0xD0D26D176FBDC700, 0x15AABF7AC502A878 50.quad 0xCFE474A55FBB6A00, 0x8E1E90D1412B35FA 51.Lk_sb1:@ sb1u, sb1t 52.quad 0x3618D415FAE22300, 0x3BF7CCC10D2ED9EF 53.quad 0xB19BE18FCB503E00, 0xA5DF7A6E142AF544 54.Lk_sb2:@ sb2u, sb2t 55.quad 0x69EB88400AE12900, 0xC2A163C8AB82234A 56.quad 0xE27A93C60B712400, 0x5EB7E955BC982FCD 57 58.byte 86,101,99,116,111,114,32,80,101,114,109,117,116,97,116,105,111,110,32,65,69,83,32,102,111,114,32,65,82,77,118,55,32,78,69,79,78,44,32,77,105,107,101,32,72,97,109,98,117,114,103,32,40,83,116,97,110,102,111,114,100,32,85,110,105,118,101,114,115,105,116,121,41,0 59.align 2 60.size _vpaes_consts,.-_vpaes_consts 61.align 6 62@@ 63@@ _aes_preheat 64@@ 65@@ Fills q9-q15 as specified below. 66@@ 67.type _vpaes_preheat,%function 68.align 4 69_vpaes_preheat: 70 adr r10, .Lk_inv 71 vmov.i8 q9, #0x0f @ .Lk_s0F 72 vld1.64 {q10,q11}, [r10]! @ .Lk_inv 73 add r10, r10, #64 @ Skip .Lk_ipt, .Lk_sbo 74 vld1.64 {q12,q13}, [r10]! @ .Lk_sb1 75 vld1.64 {q14,q15}, [r10] @ .Lk_sb2 76 bx lr 77 78@@ 79@@ _aes_encrypt_core 80@@ 81@@ AES-encrypt q0. 82@@ 83@@ Inputs: 84@@ q0 = input 85@@ q9-q15 as in _vpaes_preheat 86@@ [r2] = scheduled keys 87@@ 88@@ Output in q0 89@@ Clobbers q1-q5, r8-r11 90@@ Preserves q6-q8 so you get some local vectors 91@@ 92@@ 93.type _vpaes_encrypt_core,%function 94.align 4 95_vpaes_encrypt_core: 96 mov r9, r2 97 ldr r8, [r2,#240] @ pull rounds 98 adr r11, .Lk_ipt 99 @ vmovdqa .Lk_ipt(%rip), %xmm2 # iptlo 100 @ vmovdqa .Lk_ipt+16(%rip), %xmm3 # ipthi 101 vld1.64 {q2, q3}, [r11] 102 adr r11, .Lk_mc_forward+16 103 vld1.64 {q5}, [r9]! @ vmovdqu (%r9), %xmm5 # round0 key 104 vand q1, q0, q9 @ vpand %xmm9, %xmm0, %xmm1 105 vshr.u8 q0, q0, #4 @ vpsrlb $4, %xmm0, %xmm0 106 vtbl.8 d2, {q2}, d2 @ vpshufb %xmm1, %xmm2, %xmm1 107 vtbl.8 d3, {q2}, d3 108 vtbl.8 d4, {q3}, d0 @ vpshufb %xmm0, %xmm3, %xmm2 109 vtbl.8 d5, {q3}, d1 110 veor q0, q1, q5 @ vpxor %xmm5, %xmm1, %xmm0 111 veor q0, q0, q2 @ vpxor %xmm2, %xmm0, %xmm0 112 113 @ .Lenc_entry ends with a bnz instruction which is normally paired with 114 @ subs in .Lenc_loop. 115 tst r8, r8 116 b .Lenc_entry 117 118.align 4 119.Lenc_loop: 120 @ middle of middle round 121 add r10, r11, #0x40 122 vtbl.8 d8, {q13}, d4 @ vpshufb %xmm2, %xmm13, %xmm4 # 4 = sb1u 123 vtbl.8 d9, {q13}, d5 124 vld1.64 {q1}, [r11]! @ vmovdqa -0x40(%r11,%r10), %xmm1 # .Lk_mc_forward[] 125 vtbl.8 d0, {q12}, d6 @ vpshufb %xmm3, %xmm12, %xmm0 # 0 = sb1t 126 vtbl.8 d1, {q12}, d7 127 veor q4, q4, q5 @ vpxor %xmm5, %xmm4, %xmm4 # 4 = sb1u + k 128 vtbl.8 d10, {q15}, d4 @ vpshufb %xmm2, %xmm15, %xmm5 # 4 = sb2u 129 vtbl.8 d11, {q15}, d5 130 veor q0, q0, q4 @ vpxor %xmm4, %xmm0, %xmm0 # 0 = A 131 vtbl.8 d4, {q14}, d6 @ vpshufb %xmm3, %xmm14, %xmm2 # 2 = sb2t 132 vtbl.8 d5, {q14}, d7 133 vld1.64 {q4}, [r10] @ vmovdqa (%r11,%r10), %xmm4 # .Lk_mc_backward[] 134 vtbl.8 d6, {q0}, d2 @ vpshufb %xmm1, %xmm0, %xmm3 # 0 = B 135 vtbl.8 d7, {q0}, d3 136 veor q2, q2, q5 @ vpxor %xmm5, %xmm2, %xmm2 # 2 = 2A 137 @ Write to q5 instead of q0, so the table and destination registers do 138 @ not overlap. 139 vtbl.8 d10, {q0}, d8 @ vpshufb %xmm4, %xmm0, %xmm0 # 3 = D 140 vtbl.8 d11, {q0}, d9 141 veor q3, q3, q2 @ vpxor %xmm2, %xmm3, %xmm3 # 0 = 2A+B 142 vtbl.8 d8, {q3}, d2 @ vpshufb %xmm1, %xmm3, %xmm4 # 0 = 2B+C 143 vtbl.8 d9, {q3}, d3 144 @ Here we restore the original q0/q5 usage. 145 veor q0, q5, q3 @ vpxor %xmm3, %xmm0, %xmm0 # 3 = 2A+B+D 146 and r11, r11, #~(1<<6) @ and $0x30, %r11 # ... mod 4 147 veor q0, q0, q4 @ vpxor %xmm4, %xmm0, %xmm0 # 0 = 2A+3B+C+D 148 subs r8, r8, #1 @ nr-- 149 150.Lenc_entry: 151 @ top of round 152 vand q1, q0, q9 @ vpand %xmm0, %xmm9, %xmm1 # 0 = k 153 vshr.u8 q0, q0, #4 @ vpsrlb $4, %xmm0, %xmm0 # 1 = i 154 vtbl.8 d10, {q11}, d2 @ vpshufb %xmm1, %xmm11, %xmm5 # 2 = a/k 155 vtbl.8 d11, {q11}, d3 156 veor q1, q1, q0 @ vpxor %xmm0, %xmm1, %xmm1 # 0 = j 157 vtbl.8 d6, {q10}, d0 @ vpshufb %xmm0, %xmm10, %xmm3 # 3 = 1/i 158 vtbl.8 d7, {q10}, d1 159 vtbl.8 d8, {q10}, d2 @ vpshufb %xmm1, %xmm10, %xmm4 # 4 = 1/j 160 vtbl.8 d9, {q10}, d3 161 veor q3, q3, q5 @ vpxor %xmm5, %xmm3, %xmm3 # 3 = iak = 1/i + a/k 162 veor q4, q4, q5 @ vpxor %xmm5, %xmm4, %xmm4 # 4 = jak = 1/j + a/k 163 vtbl.8 d4, {q10}, d6 @ vpshufb %xmm3, %xmm10, %xmm2 # 2 = 1/iak 164 vtbl.8 d5, {q10}, d7 165 vtbl.8 d6, {q10}, d8 @ vpshufb %xmm4, %xmm10, %xmm3 # 3 = 1/jak 166 vtbl.8 d7, {q10}, d9 167 veor q2, q2, q1 @ vpxor %xmm1, %xmm2, %xmm2 # 2 = io 168 veor q3, q3, q0 @ vpxor %xmm0, %xmm3, %xmm3 # 3 = jo 169 vld1.64 {q5}, [r9]! @ vmovdqu (%r9), %xmm5 170 bne .Lenc_loop 171 172 @ middle of last round 173 add r10, r11, #0x80 174 175 adr r11, .Lk_sbo 176 @ Read to q1 instead of q4, so the vtbl.8 instruction below does not 177 @ overlap table and destination registers. 178 vld1.64 {q1}, [r11]! @ vmovdqa -0x60(%r10), %xmm4 # 3 : sbou 179 vld1.64 {q0}, [r11] @ vmovdqa -0x50(%r10), %xmm0 # 0 : sbot .Lk_sbo+16 180 vtbl.8 d8, {q1}, d4 @ vpshufb %xmm2, %xmm4, %xmm4 # 4 = sbou 181 vtbl.8 d9, {q1}, d5 182 vld1.64 {q1}, [r10] @ vmovdqa 0x40(%r11,%r10), %xmm1 # .Lk_sr[] 183 @ Write to q2 instead of q0 below, to avoid overlapping table and 184 @ destination registers. 185 vtbl.8 d4, {q0}, d6 @ vpshufb %xmm3, %xmm0, %xmm0 # 0 = sb1t 186 vtbl.8 d5, {q0}, d7 187 veor q4, q4, q5 @ vpxor %xmm5, %xmm4, %xmm4 # 4 = sb1u + k 188 veor q2, q2, q4 @ vpxor %xmm4, %xmm0, %xmm0 # 0 = A 189 @ Here we restore the original q0/q2 usage. 190 vtbl.8 d0, {q2}, d2 @ vpshufb %xmm1, %xmm0, %xmm0 191 vtbl.8 d1, {q2}, d3 192 bx lr 193.size _vpaes_encrypt_core,.-_vpaes_encrypt_core 194 195.globl vpaes_encrypt 196.hidden vpaes_encrypt 197.type vpaes_encrypt,%function 198.align 4 199vpaes_encrypt: 200 @ _vpaes_encrypt_core uses r8-r11. Round up to r7-r11 to maintain stack 201 @ alignment. 202 stmdb sp!, {r7,r8,r9,r10,r11,lr} 203 @ _vpaes_encrypt_core uses q4-q5 (d8-d11), which are callee-saved. 204 vstmdb sp!, {d8,d9,d10,d11} 205 206 vld1.64 {q0}, [r0] 207 bl _vpaes_preheat 208 bl _vpaes_encrypt_core 209 vst1.64 {q0}, [r1] 210 211 vldmia sp!, {d8,d9,d10,d11} 212 ldmia sp!, {r7,r8,r9,r10,r11, pc} @ return 213.size vpaes_encrypt,.-vpaes_encrypt 214@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 215@@ @@ 216@@ AES key schedule @@ 217@@ @@ 218@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 219 220@ This function diverges from both x86_64 and armv7 in which constants are 221@ pinned. x86_64 has a common preheat function for all operations. aarch64 222@ separates them because it has enough registers to pin nearly all constants. 223@ armv7 does not have enough registers, but needing explicit loads and stores 224@ also complicates using x86_64's register allocation directly. 225@ 226@ We pin some constants for convenience and leave q14 and q15 free to load 227@ others on demand. 228 229@ 230@ Key schedule constants 231@ 232.type _vpaes_key_consts,%object 233.align 4 234_vpaes_key_consts: 235.Lk_rcon:@ rcon 236.quad 0x1F8391B9AF9DEEB6, 0x702A98084D7C7D81 237 238.Lk_opt:@ output transform 239.quad 0xFF9F4929D6B66000, 0xF7974121DEBE6808 240.quad 0x01EDBD5150BCEC00, 0xE10D5DB1B05C0CE0 241.Lk_deskew:@ deskew tables: inverts the sbox's "skew" 242.quad 0x07E4A34047A4E300, 0x1DFEB95A5DBEF91A 243.quad 0x5F36B5DC83EA6900, 0x2841C2ABF49D1E77 244.size _vpaes_key_consts,.-_vpaes_key_consts 245 246.type _vpaes_key_preheat,%function 247.align 4 248_vpaes_key_preheat: 249 adr r11, .Lk_rcon 250 vmov.i8 q12, #0x5b @ .Lk_s63 251 adr r10, .Lk_inv @ Must be aligned to 8 mod 16. 252 vmov.i8 q9, #0x0f @ .Lk_s0F 253 vld1.64 {q10,q11}, [r10] @ .Lk_inv 254 vld1.64 {q8}, [r11] @ .Lk_rcon 255 bx lr 256.size _vpaes_key_preheat,.-_vpaes_key_preheat 257 258.type _vpaes_schedule_core,%function 259.align 4 260_vpaes_schedule_core: 261 @ We only need to save lr, but ARM requires an 8-byte stack alignment, 262 @ so save an extra register. 263 stmdb sp!, {r3,lr} 264 265 bl _vpaes_key_preheat @ load the tables 266 267 adr r11, .Lk_ipt @ Must be aligned to 8 mod 16. 268 vld1.64 {q0}, [r0]! @ vmovdqu (%rdi), %xmm0 # load key (unaligned) 269 270 @ input transform 271 @ Use q4 here rather than q3 so .Lschedule_am_decrypting does not 272 @ overlap table and destination. 273 vmov q4, q0 @ vmovdqa %xmm0, %xmm3 274 bl _vpaes_schedule_transform 275 adr r10, .Lk_sr @ Must be aligned to 8 mod 16. 276 vmov q7, q0 @ vmovdqa %xmm0, %xmm7 277 278 add r8, r8, r10 279 280 @ encrypting, output zeroth round key after transform 281 vst1.64 {q0}, [r2] @ vmovdqu %xmm0, (%rdx) 282 283 @ *ring*: Decryption removed. 284 285.Lschedule_go: 286 cmp r1, #192 @ cmp $192, %esi 287 bhi .Lschedule_256 288 @ 128: fall though 289 290@@ 291@@ .schedule_128 292@@ 293@@ 128-bit specific part of key schedule. 294@@ 295@@ This schedule is really simple, because all its parts 296@@ are accomplished by the subroutines. 297@@ 298.Lschedule_128: 299 mov r0, #10 @ mov $10, %esi 300 301.Loop_schedule_128: 302 bl _vpaes_schedule_round 303 subs r0, r0, #1 @ dec %esi 304 beq .Lschedule_mangle_last 305 bl _vpaes_schedule_mangle @ write output 306 b .Loop_schedule_128 307 308@@ 309@@ .aes_schedule_256 310@@ 311@@ 256-bit specific part of key schedule. 312@@ 313@@ The structure here is very similar to the 128-bit 314@@ schedule, but with an additional "low side" in 315@@ q6. The low side's rounds are the same as the 316@@ high side's, except no rcon and no rotation. 317@@ 318.align 4 319.Lschedule_256: 320 vld1.64 {q0}, [r0] @ vmovdqu 16(%rdi),%xmm0 # load key part 2 (unaligned) 321 bl _vpaes_schedule_transform @ input transform 322 mov r0, #7 @ mov $7, %esi 323 324.Loop_schedule_256: 325 bl _vpaes_schedule_mangle @ output low result 326 vmov q6, q0 @ vmovdqa %xmm0, %xmm6 # save cur_lo in xmm6 327 328 @ high round 329 bl _vpaes_schedule_round 330 subs r0, r0, #1 @ dec %esi 331 beq .Lschedule_mangle_last 332 bl _vpaes_schedule_mangle 333 334 @ low round. swap xmm7 and xmm6 335 vdup.32 q0, d1[1] @ vpshufd $0xFF, %xmm0, %xmm0 336 vmov.i8 q4, #0 337 vmov q5, q7 @ vmovdqa %xmm7, %xmm5 338 vmov q7, q6 @ vmovdqa %xmm6, %xmm7 339 bl _vpaes_schedule_low_round 340 vmov q7, q5 @ vmovdqa %xmm5, %xmm7 341 342 b .Loop_schedule_256 343 344@@ 345@@ .aes_schedule_mangle_last 346@@ 347@@ Mangler for last round of key schedule 348@@ Mangles q0 349@@ when encrypting, outputs out(q0) ^ 63 350@@ when decrypting, outputs unskew(q0) 351@@ 352@@ Always called right before return... jumps to cleanup and exits 353@@ 354.align 4 355.Lschedule_mangle_last: 356 @ schedule last round key from xmm0 357 adr r11, .Lk_deskew @ lea .Lk_deskew(%rip),%r11 # prepare to deskew 358 359 @ encrypting 360 vld1.64 {q1}, [r8] @ vmovdqa (%r8,%r10),%xmm1 361 adr r11, .Lk_opt @ lea .Lk_opt(%rip), %r11 # prepare to output transform 362 add r2, r2, #32 @ add $32, %rdx 363 vmov q2, q0 364 vtbl.8 d0, {q2}, d2 @ vpshufb %xmm1, %xmm0, %xmm0 # output permute 365 vtbl.8 d1, {q2}, d3 366 367.Lschedule_mangle_last_dec: 368 sub r2, r2, #16 @ add $-16, %rdx 369 veor q0, q0, q12 @ vpxor .Lk_s63(%rip), %xmm0, %xmm0 370 bl _vpaes_schedule_transform @ output transform 371 vst1.64 {q0}, [r2] @ vmovdqu %xmm0, (%rdx) # save last key 372 373 @ cleanup 374 veor q0, q0, q0 @ vpxor %xmm0, %xmm0, %xmm0 375 veor q1, q1, q1 @ vpxor %xmm1, %xmm1, %xmm1 376 veor q2, q2, q2 @ vpxor %xmm2, %xmm2, %xmm2 377 veor q3, q3, q3 @ vpxor %xmm3, %xmm3, %xmm3 378 veor q4, q4, q4 @ vpxor %xmm4, %xmm4, %xmm4 379 veor q5, q5, q5 @ vpxor %xmm5, %xmm5, %xmm5 380 veor q6, q6, q6 @ vpxor %xmm6, %xmm6, %xmm6 381 veor q7, q7, q7 @ vpxor %xmm7, %xmm7, %xmm7 382 ldmia sp!, {r3,pc} @ return 383.size _vpaes_schedule_core,.-_vpaes_schedule_core 384 385@@ 386@@ .aes_schedule_round 387@@ 388@@ Runs one main round of the key schedule on q0, q7 389@@ 390@@ Specifically, runs subbytes on the high dword of q0 391@@ then rotates it by one byte and xors into the low dword of 392@@ q7. 393@@ 394@@ Adds rcon from low byte of q8, then rotates q8 for 395@@ next rcon. 396@@ 397@@ Smears the dwords of q7 by xoring the low into the 398@@ second low, result into third, result into highest. 399@@ 400@@ Returns results in q7 = q0. 401@@ Clobbers q1-q4, r11. 402@@ 403.type _vpaes_schedule_round,%function 404.align 4 405_vpaes_schedule_round: 406 @ extract rcon from xmm8 407 vmov.i8 q4, #0 @ vpxor %xmm4, %xmm4, %xmm4 408 vext.8 q1, q8, q4, #15 @ vpalignr $15, %xmm8, %xmm4, %xmm1 409 vext.8 q8, q8, q8, #15 @ vpalignr $15, %xmm8, %xmm8, %xmm8 410 veor q7, q7, q1 @ vpxor %xmm1, %xmm7, %xmm7 411 412 @ rotate 413 vdup.32 q0, d1[1] @ vpshufd $0xFF, %xmm0, %xmm0 414 vext.8 q0, q0, q0, #1 @ vpalignr $1, %xmm0, %xmm0, %xmm0 415 416 @ fall through... 417 418 @ low round: same as high round, but no rotation and no rcon. 419_vpaes_schedule_low_round: 420 @ The x86_64 version pins .Lk_sb1 in %xmm13 and .Lk_sb1+16 in %xmm12. 421 @ We pin other values in _vpaes_key_preheat, so load them now. 422 adr r11, .Lk_sb1 423 vld1.64 {q14,q15}, [r11] 424 425 @ smear xmm7 426 vext.8 q1, q4, q7, #12 @ vpslldq $4, %xmm7, %xmm1 427 veor q7, q7, q1 @ vpxor %xmm1, %xmm7, %xmm7 428 vext.8 q4, q4, q7, #8 @ vpslldq $8, %xmm7, %xmm4 429 430 @ subbytes 431 vand q1, q0, q9 @ vpand %xmm9, %xmm0, %xmm1 # 0 = k 432 vshr.u8 q0, q0, #4 @ vpsrlb $4, %xmm0, %xmm0 # 1 = i 433 veor q7, q7, q4 @ vpxor %xmm4, %xmm7, %xmm7 434 vtbl.8 d4, {q11}, d2 @ vpshufb %xmm1, %xmm11, %xmm2 # 2 = a/k 435 vtbl.8 d5, {q11}, d3 436 veor q1, q1, q0 @ vpxor %xmm0, %xmm1, %xmm1 # 0 = j 437 vtbl.8 d6, {q10}, d0 @ vpshufb %xmm0, %xmm10, %xmm3 # 3 = 1/i 438 vtbl.8 d7, {q10}, d1 439 veor q3, q3, q2 @ vpxor %xmm2, %xmm3, %xmm3 # 3 = iak = 1/i + a/k 440 vtbl.8 d8, {q10}, d2 @ vpshufb %xmm1, %xmm10, %xmm4 # 4 = 1/j 441 vtbl.8 d9, {q10}, d3 442 veor q7, q7, q12 @ vpxor .Lk_s63(%rip), %xmm7, %xmm7 443 vtbl.8 d6, {q10}, d6 @ vpshufb %xmm3, %xmm10, %xmm3 # 2 = 1/iak 444 vtbl.8 d7, {q10}, d7 445 veor q4, q4, q2 @ vpxor %xmm2, %xmm4, %xmm4 # 4 = jak = 1/j + a/k 446 vtbl.8 d4, {q10}, d8 @ vpshufb %xmm4, %xmm10, %xmm2 # 3 = 1/jak 447 vtbl.8 d5, {q10}, d9 448 veor q3, q3, q1 @ vpxor %xmm1, %xmm3, %xmm3 # 2 = io 449 veor q2, q2, q0 @ vpxor %xmm0, %xmm2, %xmm2 # 3 = jo 450 vtbl.8 d8, {q15}, d6 @ vpshufb %xmm3, %xmm13, %xmm4 # 4 = sbou 451 vtbl.8 d9, {q15}, d7 452 vtbl.8 d2, {q14}, d4 @ vpshufb %xmm2, %xmm12, %xmm1 # 0 = sb1t 453 vtbl.8 d3, {q14}, d5 454 veor q1, q1, q4 @ vpxor %xmm4, %xmm1, %xmm1 # 0 = sbox output 455 456 @ add in smeared stuff 457 veor q0, q1, q7 @ vpxor %xmm7, %xmm1, %xmm0 458 veor q7, q1, q7 @ vmovdqa %xmm0, %xmm7 459 bx lr 460.size _vpaes_schedule_round,.-_vpaes_schedule_round 461 462@@ 463@@ .aes_schedule_transform 464@@ 465@@ Linear-transform q0 according to tables at [r11] 466@@ 467@@ Requires that q9 = 0x0F0F... as in preheat 468@@ Output in q0 469@@ Clobbers q1, q2, q14, q15 470@@ 471.type _vpaes_schedule_transform,%function 472.align 4 473_vpaes_schedule_transform: 474 vld1.64 {q14,q15}, [r11] @ vmovdqa (%r11), %xmm2 # lo 475 @ vmovdqa 16(%r11), %xmm1 # hi 476 vand q1, q0, q9 @ vpand %xmm9, %xmm0, %xmm1 477 vshr.u8 q0, q0, #4 @ vpsrlb $4, %xmm0, %xmm0 478 vtbl.8 d4, {q14}, d2 @ vpshufb %xmm1, %xmm2, %xmm2 479 vtbl.8 d5, {q14}, d3 480 vtbl.8 d0, {q15}, d0 @ vpshufb %xmm0, %xmm1, %xmm0 481 vtbl.8 d1, {q15}, d1 482 veor q0, q0, q2 @ vpxor %xmm2, %xmm0, %xmm0 483 bx lr 484.size _vpaes_schedule_transform,.-_vpaes_schedule_transform 485 486@@ 487@@ .aes_schedule_mangle 488@@ 489@@ Mangles q0 from (basis-transformed) standard version 490@@ to our version. 491@@ 492@@ On encrypt, 493@@ xor with 0x63 494@@ multiply by circulant 0,1,1,1 495@@ apply shiftrows transform 496@@ 497@@ On decrypt, 498@@ xor with 0x63 499@@ multiply by "inverse mixcolumns" circulant E,B,D,9 500@@ deskew 501@@ apply shiftrows transform 502@@ 503@@ 504@@ Writes out to [r2], and increments or decrements it 505@@ Keeps track of round number mod 4 in r8 506@@ Preserves q0 507@@ Clobbers q1-q5 508@@ 509.type _vpaes_schedule_mangle,%function 510.align 4 511_vpaes_schedule_mangle: 512 tst r3, r3 513 vmov q4, q0 @ vmovdqa %xmm0, %xmm4 # save xmm0 for later 514 adr r11, .Lk_mc_forward @ Must be aligned to 8 mod 16. 515 vld1.64 {q5}, [r11] @ vmovdqa .Lk_mc_forward(%rip),%xmm5 516 517 @ encrypting 518 @ Write to q2 so we do not overlap table and destination below. 519 veor q2, q0, q12 @ vpxor .Lk_s63(%rip), %xmm0, %xmm4 520 add r2, r2, #16 @ add $16, %rdx 521 vtbl.8 d8, {q2}, d10 @ vpshufb %xmm5, %xmm4, %xmm4 522 vtbl.8 d9, {q2}, d11 523 vtbl.8 d2, {q4}, d10 @ vpshufb %xmm5, %xmm4, %xmm1 524 vtbl.8 d3, {q4}, d11 525 vtbl.8 d6, {q1}, d10 @ vpshufb %xmm5, %xmm1, %xmm3 526 vtbl.8 d7, {q1}, d11 527 veor q4, q4, q1 @ vpxor %xmm1, %xmm4, %xmm4 528 vld1.64 {q1}, [r8] @ vmovdqa (%r8,%r10), %xmm1 529 veor q3, q3, q4 @ vpxor %xmm4, %xmm3, %xmm3 530 531.Lschedule_mangle_both: 532 @ Write to q2 so table and destination do not overlap. 533 vtbl.8 d4, {q3}, d2 @ vpshufb %xmm1, %xmm3, %xmm3 534 vtbl.8 d5, {q3}, d3 535 add r8, r8, #64-16 @ add $-16, %r8 536 and r8, r8, #~(1<<6) @ and $0x30, %r8 537 vst1.64 {q2}, [r2] @ vmovdqu %xmm3, (%rdx) 538 bx lr 539.size _vpaes_schedule_mangle,.-_vpaes_schedule_mangle 540 541.globl vpaes_set_encrypt_key 542.hidden vpaes_set_encrypt_key 543.type vpaes_set_encrypt_key,%function 544.align 4 545vpaes_set_encrypt_key: 546 stmdb sp!, {r7,r8,r9,r10,r11, lr} 547 vstmdb sp!, {d8,d9,d10,d11,d12,d13,d14,d15} 548 549 lsr r9, r1, #5 @ shr $5,%eax 550 add r9, r9, #5 @ $5,%eax 551 str r9, [r2,#240] @ mov %eax,240(%rdx) # AES_KEY->rounds = nbits/32+5; 552 553 mov r3, #0 @ mov $0,%ecx 554 mov r8, #0x30 @ mov $0x30,%r8d 555 bl _vpaes_schedule_core 556 eor r0, r0, r0 557 558 vldmia sp!, {d8,d9,d10,d11,d12,d13,d14,d15} 559 ldmia sp!, {r7,r8,r9,r10,r11, pc} @ return 560.size vpaes_set_encrypt_key,.-vpaes_set_encrypt_key 561 562@ Additional constants for converting to bsaes. 563.type _vpaes_convert_consts,%object 564.align 4 565_vpaes_convert_consts: 566@ .Lk_opt_then_skew applies skew(opt(x)) XOR 0x63, where skew is the linear 567@ transform in the AES S-box. 0x63 is incorporated into the low half of the 568@ table. This was computed with the following script: 569@ 570@ def u64s_to_u128(x, y): 571@ return x | (y << 64) 572@ def u128_to_u64s(w): 573@ return w & ((1<<64)-1), w >> 64 574@ def get_byte(w, i): 575@ return (w >> (i*8)) & 0xff 576@ def apply_table(table, b): 577@ lo = b & 0xf 578@ hi = b >> 4 579@ return get_byte(table[0], lo) ^ get_byte(table[1], hi) 580@ def opt(b): 581@ table = [ 582@ u64s_to_u128(0xFF9F4929D6B66000, 0xF7974121DEBE6808), 583@ u64s_to_u128(0x01EDBD5150BCEC00, 0xE10D5DB1B05C0CE0), 584@ ] 585@ return apply_table(table, b) 586@ def rot_byte(b, n): 587@ return 0xff & ((b << n) | (b >> (8-n))) 588@ def skew(x): 589@ return (x ^ rot_byte(x, 1) ^ rot_byte(x, 2) ^ rot_byte(x, 3) ^ 590@ rot_byte(x, 4)) 591@ table = [0, 0] 592@ for i in range(16): 593@ table[0] |= (skew(opt(i)) ^ 0x63) << (i*8) 594@ table[1] |= skew(opt(i<<4)) << (i*8) 595@ print(" .quad 0x%016x, 0x%016x" % u128_to_u64s(table[0])) 596@ print(" .quad 0x%016x, 0x%016x" % u128_to_u64s(table[1])) 597.Lk_opt_then_skew: 598.quad 0x9cb8436798bc4763, 0x6440bb9f6044bf9b 599.quad 0x1f30062936192f00, 0xb49bad829db284ab 600 601@ void vpaes_encrypt_key_to_bsaes(AES_KEY *bsaes, const AES_KEY *vpaes); 602.globl vpaes_encrypt_key_to_bsaes 603.hidden vpaes_encrypt_key_to_bsaes 604.type vpaes_encrypt_key_to_bsaes,%function 605.align 4 606vpaes_encrypt_key_to_bsaes: 607 stmdb sp!, {r11, lr} 608 609 @ See _vpaes_schedule_core for the key schedule logic. In particular, 610 @ _vpaes_schedule_transform(.Lk_ipt) (section 2.2 of the paper), 611 @ _vpaes_schedule_mangle (section 4.3), and .Lschedule_mangle_last 612 @ contain the transformations not in the bsaes representation. This 613 @ function inverts those transforms. 614 @ 615 @ Note also that bsaes-armv7.pl expects aes-armv4.pl's key 616 @ representation, which does not match the other aes_nohw_* 617 @ implementations. The ARM aes_nohw_* stores each 32-bit word 618 @ byteswapped, as a convenience for (unsupported) big-endian ARM, at the 619 @ cost of extra REV and VREV32 operations in little-endian ARM. 620 621 vmov.i8 q9, #0x0f @ Required by _vpaes_schedule_transform 622 adr r2, .Lk_mc_forward @ Must be aligned to 8 mod 16. 623 add r3, r2, 0x90 @ .Lk_sr+0x10-.Lk_mc_forward = 0x90 (Apple's toolchain doesn't support the expression) 624 625 vld1.64 {q12}, [r2] 626 vmov.i8 q10, #0x5b @ .Lk_s63 from vpaes-x86_64 627 adr r11, .Lk_opt @ Must be aligned to 8 mod 16. 628 vmov.i8 q11, #0x63 @ .LK_s63 without .Lk_ipt applied 629 630 @ vpaes stores one fewer round count than bsaes, but the number of keys 631 @ is the same. 632 ldr r2, [r1,#240] 633 add r2, r2, #1 634 str r2, [r0,#240] 635 636 @ The first key is transformed with _vpaes_schedule_transform(.Lk_ipt). 637 @ Invert this with .Lk_opt. 638 vld1.64 {q0}, [r1]! 639 bl _vpaes_schedule_transform 640 vrev32.8 q0, q0 641 vst1.64 {q0}, [r0]! 642 643 @ The middle keys have _vpaes_schedule_transform(.Lk_ipt) applied, 644 @ followed by _vpaes_schedule_mangle. _vpaes_schedule_mangle XORs 0x63, 645 @ multiplies by the circulant 0,1,1,1, then applies ShiftRows. 646.Loop_enc_key_to_bsaes: 647 vld1.64 {q0}, [r1]! 648 649 @ Invert the ShiftRows step (see .Lschedule_mangle_both). Note we cycle 650 @ r3 in the opposite direction and start at .Lk_sr+0x10 instead of 0x30. 651 @ We use r3 rather than r8 to avoid a callee-saved register. 652 vld1.64 {q1}, [r3] 653 vtbl.8 d4, {q0}, d2 654 vtbl.8 d5, {q0}, d3 655 add r3, r3, #16 656 and r3, r3, #~(1<<6) 657 vmov q0, q2 658 659 @ Handle the last key differently. 660 subs r2, r2, #1 661 beq .Loop_enc_key_to_bsaes_last 662 663 @ Multiply by the circulant. This is its own inverse. 664 vtbl.8 d2, {q0}, d24 665 vtbl.8 d3, {q0}, d25 666 vmov q0, q1 667 vtbl.8 d4, {q1}, d24 668 vtbl.8 d5, {q1}, d25 669 veor q0, q0, q2 670 vtbl.8 d2, {q2}, d24 671 vtbl.8 d3, {q2}, d25 672 veor q0, q0, q1 673 674 @ XOR and finish. 675 veor q0, q0, q10 676 bl _vpaes_schedule_transform 677 vrev32.8 q0, q0 678 vst1.64 {q0}, [r0]! 679 b .Loop_enc_key_to_bsaes 680 681.Loop_enc_key_to_bsaes_last: 682 @ The final key does not have a basis transform (note 683 @ .Lschedule_mangle_last inverts the original transform). It only XORs 684 @ 0x63 and applies ShiftRows. The latter was already inverted in the 685 @ loop. Note that, because we act on the original representation, we use 686 @ q11, not q10. 687 veor q0, q0, q11 688 vrev32.8 q0, q0 689 vst1.64 {q0}, [r0] 690 691 @ Wipe registers which contained key material. 692 veor q0, q0, q0 693 veor q1, q1, q1 694 veor q2, q2, q2 695 696 ldmia sp!, {r11, pc} @ return 697.size vpaes_encrypt_key_to_bsaes,.-vpaes_encrypt_key_to_bsaes 698.globl vpaes_ctr32_encrypt_blocks 699.hidden vpaes_ctr32_encrypt_blocks 700.type vpaes_ctr32_encrypt_blocks,%function 701.align 4 702vpaes_ctr32_encrypt_blocks: 703 mov ip, sp 704 stmdb sp!, {r7,r8,r9,r10,r11, lr} 705 @ This function uses q4-q7 (d8-d15), which are callee-saved. 706 vstmdb sp!, {d8,d9,d10,d11,d12,d13,d14,d15} 707 708 cmp r2, #0 709 @ r8 is passed on the stack. 710 ldr r8, [ip] 711 beq .Lctr32_done 712 713 @ _vpaes_encrypt_core expects the key in r2, so swap r2 and r3. 714 mov r9, r3 715 mov r3, r2 716 mov r2, r9 717 718 @ Load the IV and counter portion. 719 ldr r7, [r8, #12] 720 vld1.8 {q7}, [r8] 721 722 bl _vpaes_preheat 723 rev r7, r7 @ The counter is big-endian. 724 725.Lctr32_loop: 726 vmov q0, q7 727 vld1.8 {q6}, [r0]! @ .Load input ahead of time 728 bl _vpaes_encrypt_core 729 veor q0, q0, q6 @ XOR input and result 730 vst1.8 {q0}, [r1]! 731 subs r3, r3, #1 732 @ Update the counter. 733 add r7, r7, #1 734 rev r9, r7 735 vmov.32 d15[1], r9 736 bne .Lctr32_loop 737 738.Lctr32_done: 739 vldmia sp!, {d8,d9,d10,d11,d12,d13,d14,d15} 740 ldmia sp!, {r7,r8,r9,r10,r11, pc} @ return 741.size vpaes_ctr32_encrypt_blocks,.-vpaes_ctr32_encrypt_blocks 742#endif // !OPENSSL_NO_ASM && defined(OPENSSL_ARM) && defined(__ELF__) 743