1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Global Combiner *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9#ifdef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS 10#include "llvm/ADT/SparseBitVector.h" 11namespace llvm { 12extern cl::OptionCategory GICombinerOptionCategory; 13} // end namespace llvm 14#endif // ifdef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS 15 16#ifdef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H 17class AArch64GenPreLegalizerCombinerHelper { 18 SparseBitVector<> DisabledRules; 19 20public: 21 bool parseCommandLineOption(); 22 bool isRuleDisabled(unsigned ID) const; 23 bool setRuleDisabled(StringRef RuleIdentifier); 24 25 bool tryCombineAll( 26 GISelChangeObserver &Observer, 27 MachineInstr &MI, 28 MachineIRBuilder &B, 29 CombinerHelper &Helper) const; 30}; 31 32static Optional<uint64_t> getRuleIdxForIdentifier(StringRef RuleIdentifier) { 33 uint64_t I; 34 // getAtInteger(...) returns false on success 35 bool Parsed = !RuleIdentifier.getAsInteger(0, I); 36 if (Parsed) 37 return I; 38 39#ifndef NDEBUG 40 switch (RuleIdentifier.size()) { 41 default: break; 42 case 9: // 1 string to match. 43 if (memcmp(RuleIdentifier.data()+0, "copy_prop", 9) != 0) 44 break; 45 return 0; // "copy_prop" 46 case 15: // 1 string to match. 47 if (memcmp(RuleIdentifier.data()+0, "extending_loads", 15) != 0) 48 break; 49 return 2; // "extending_loads" 50 case 19: // 1 string to match. 51 if (memcmp(RuleIdentifier.data()+0, "ptr_add_immed_chain", 19) != 0) 52 break; 53 return 1; // "ptr_add_immed_chain" 54 case 26: // 2 strings to match. 55 switch (RuleIdentifier[0]) { 56 default: break; 57 case 'c': // 1 string to match. 58 if (memcmp(RuleIdentifier.data()+1, "ombine_indexed_load_store", 25) != 0) 59 break; 60 return 3; // "combine_indexed_load_store" 61 case 'e': // 1 string to match. 62 if (memcmp(RuleIdentifier.data()+1, "lide_br_by_inverting_cond", 25) != 0) 63 break; 64 return 4; // "elide_br_by_inverting_cond" 65 } 66 break; 67 } 68#endif // ifndef NDEBUG 69 70 return None; 71} 72bool AArch64GenPreLegalizerCombinerHelper::setRuleDisabled(StringRef RuleIdentifier) { 73 std::pair<StringRef, StringRef> RangePair = RuleIdentifier.split('-'); 74 if (!RangePair.second.empty()) { 75 const auto First = getRuleIdxForIdentifier(RangePair.first); 76 const auto Last = getRuleIdxForIdentifier(RangePair.second); 77 if (!First.hasValue() || !Last.hasValue()) 78 return false; 79 if (First >= Last) 80 report_fatal_error("Beginning of range should be before end of range"); 81 for (auto I = First.getValue(); I < Last.getValue(); ++I) 82 DisabledRules.set(I); 83 return true; 84 } else { 85 const auto I = getRuleIdxForIdentifier(RangePair.first); 86 if (!I.hasValue()) 87 return false; 88 DisabledRules.set(I.getValue()); 89 return true; 90 } 91 return false; 92} 93bool AArch64GenPreLegalizerCombinerHelper::isRuleDisabled(unsigned RuleID) const { 94 return DisabledRules.test(RuleID); 95} 96#endif // ifdef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H 97 98#ifdef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP 99 100cl::list<std::string> AArch64PreLegalizerCombinerHelperOption( 101 "aarch64prelegalizercombinerhelper-disable-rule", 102 cl::desc("Disable one or more combiner rules temporarily in the AArch64PreLegalizerCombinerHelper pass"), 103 cl::CommaSeparated, 104 cl::Hidden, 105 cl::cat(GICombinerOptionCategory)); 106 107bool AArch64GenPreLegalizerCombinerHelper::parseCommandLineOption() { 108 for (const auto &Identifier : AArch64PreLegalizerCombinerHelperOption) 109 if (!setRuleDisabled(Identifier)) 110 return false; 111 return true; 112} 113 114bool AArch64GenPreLegalizerCombinerHelper::tryCombineAll( 115 GISelChangeObserver &Observer, 116 MachineInstr &MI, 117 MachineIRBuilder &B, 118 CombinerHelper &Helper) const { 119 MachineBasicBlock *MBB = MI.getParent(); 120 MachineFunction *MF = MBB->getParent(); 121 MachineRegisterInfo &MRI = MF->getRegInfo(); 122 SmallVector<MachineInstr *, 8> MIs = { &MI }; 123 124 (void)MBB; (void)MF; (void)MRI; 125 126 // Match data 127 PtrAddChain MatchData1; 128 PreferredTuple MatchData2; 129 IndexedLoadStoreMatchInfo MatchData3; 130 131 int Partition = -1; 132 Partition = -1; 133 switch (MIs[0]->getOpcode()) { 134 case TargetOpcode::COPY: Partition = 0; break; 135 case TargetOpcode::G_PTR_ADD: Partition = 1; break; 136 case TargetOpcode::G_LOAD: Partition = 2; break; 137 case TargetOpcode::G_SEXTLOAD: Partition = 3; break; 138 case TargetOpcode::G_ZEXTLOAD: Partition = 4; break; 139 case TargetOpcode::G_STORE: Partition = 5; break; 140 case TargetOpcode::G_BR: Partition = 6; break; 141 } 142 // Default case but without conflicting with potential default case in selection. 143 if (Partition == -1) return false; 144 if (Partition == 0 /* TargetOpcode::COPY */) { 145 // Leaf name: copy_prop 146 // Rule: copy_prop 147 if (!isRuleDisabled(0)) { 148 if (1 149 && [&]() { 150 return Helper.matchCombineCopy(*MIs[0]); 151 return true; 152 }()) { 153 Helper.applyCombineCopy(*MIs[0]); 154 return true; 155 } 156 } 157 return false; 158 } 159 if (Partition == 1 /* TargetOpcode::G_PTR_ADD */) { 160 // Leaf name: ptr_add_immed_chain 161 // Rule: ptr_add_immed_chain 162 if (!isRuleDisabled(1)) { 163 if (1 164 && [&]() { 165 return Helper.matchPtrAddImmedChain(*MIs[0], MatchData1); 166 return true; 167 }()) { 168 Helper.applyPtrAddImmedChain(*MIs[0], MatchData1); 169 return true; 170 } 171 } 172 return false; 173 } 174 if (Partition == 2 /* TargetOpcode::G_LOAD */) { 175 // Leaf name: extending_loads 176 // Rule: extending_loads 177 if (!isRuleDisabled(2)) { 178 if (1 179 && [&]() { 180 return Helper.matchCombineExtendingLoads(*MIs[0], MatchData2); 181 return true; 182 }()) { 183 Helper.applyCombineExtendingLoads(*MIs[0], MatchData2); 184 return true; 185 } 186 } 187 // Leaf name: combine_indexed_load_store 188 // Rule: combine_indexed_load_store 189 if (!isRuleDisabled(3)) { 190 if (1 191 && [&]() { 192 return Helper.matchCombineIndexedLoadStore(*MIs[0], MatchData3); 193 return true; 194 }()) { 195 Helper.applyCombineIndexedLoadStore(*MIs[0], MatchData3); 196 return true; 197 } 198 } 199 return false; 200 } 201 if (Partition == 3 /* TargetOpcode::G_SEXTLOAD */) { 202 // Leaf name: extending_loads 203 // Rule: extending_loads 204 if (!isRuleDisabled(2)) { 205 if (1 206 && [&]() { 207 return Helper.matchCombineExtendingLoads(*MIs[0], MatchData2); 208 return true; 209 }()) { 210 Helper.applyCombineExtendingLoads(*MIs[0], MatchData2); 211 return true; 212 } 213 } 214 // Leaf name: combine_indexed_load_store 215 // Rule: combine_indexed_load_store 216 if (!isRuleDisabled(3)) { 217 if (1 218 && [&]() { 219 return Helper.matchCombineIndexedLoadStore(*MIs[0], MatchData3); 220 return true; 221 }()) { 222 Helper.applyCombineIndexedLoadStore(*MIs[0], MatchData3); 223 return true; 224 } 225 } 226 return false; 227 } 228 if (Partition == 4 /* TargetOpcode::G_ZEXTLOAD */) { 229 // Leaf name: extending_loads 230 // Rule: extending_loads 231 if (!isRuleDisabled(2)) { 232 if (1 233 && [&]() { 234 return Helper.matchCombineExtendingLoads(*MIs[0], MatchData2); 235 return true; 236 }()) { 237 Helper.applyCombineExtendingLoads(*MIs[0], MatchData2); 238 return true; 239 } 240 } 241 // Leaf name: combine_indexed_load_store 242 // Rule: combine_indexed_load_store 243 if (!isRuleDisabled(3)) { 244 if (1 245 && [&]() { 246 return Helper.matchCombineIndexedLoadStore(*MIs[0], MatchData3); 247 return true; 248 }()) { 249 Helper.applyCombineIndexedLoadStore(*MIs[0], MatchData3); 250 return true; 251 } 252 } 253 return false; 254 } 255 if (Partition == 5 /* TargetOpcode::G_STORE */) { 256 // Leaf name: combine_indexed_load_store 257 // Rule: combine_indexed_load_store 258 if (!isRuleDisabled(3)) { 259 if (1 260 && [&]() { 261 return Helper.matchCombineIndexedLoadStore(*MIs[0], MatchData3); 262 return true; 263 }()) { 264 Helper.applyCombineIndexedLoadStore(*MIs[0], MatchData3); 265 return true; 266 } 267 } 268 return false; 269 } 270 if (Partition == 6 /* TargetOpcode::G_BR */) { 271 // Leaf name: elide_br_by_inverting_cond 272 // Rule: elide_br_by_inverting_cond 273 if (!isRuleDisabled(4)) { 274 if (1 275 && [&]() { 276 return Helper.matchElideBrByInvertingCond(*MIs[0]); 277 return true; 278 }()) { 279 Helper.applyElideBrByInvertingCond(*MIs[0]); 280 return true; 281 } 282 } 283 return false; 284 } 285 286 return false; 287} 288#endif // ifdef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP 289