1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Target Register Enum Values *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10#ifdef GET_REGINFO_ENUM 11#undef GET_REGINFO_ENUM 12 13namespace llvm { 14 15class MCRegisterClass; 16extern const MCRegisterClass ARMMCRegisterClasses[]; 17 18namespace ARM { 19enum { 20 NoRegister, 21 APSR = 1, 22 APSR_NZCV = 2, 23 CPSR = 3, 24 FPCXTNS = 4, 25 FPCXTS = 5, 26 FPEXC = 6, 27 FPINST = 7, 28 FPSCR = 8, 29 FPSCR_NZCV = 9, 30 FPSCR_NZCVQC = 10, 31 FPSID = 11, 32 ITSTATE = 12, 33 LR = 13, 34 PC = 14, 35 SP = 15, 36 SPSR = 16, 37 VPR = 17, 38 ZR = 18, 39 D0 = 19, 40 D1 = 20, 41 D2 = 21, 42 D3 = 22, 43 D4 = 23, 44 D5 = 24, 45 D6 = 25, 46 D7 = 26, 47 D8 = 27, 48 D9 = 28, 49 D10 = 29, 50 D11 = 30, 51 D12 = 31, 52 D13 = 32, 53 D14 = 33, 54 D15 = 34, 55 D16 = 35, 56 D17 = 36, 57 D18 = 37, 58 D19 = 38, 59 D20 = 39, 60 D21 = 40, 61 D22 = 41, 62 D23 = 42, 63 D24 = 43, 64 D25 = 44, 65 D26 = 45, 66 D27 = 46, 67 D28 = 47, 68 D29 = 48, 69 D30 = 49, 70 D31 = 50, 71 FPINST2 = 51, 72 MVFR0 = 52, 73 MVFR1 = 53, 74 MVFR2 = 54, 75 P0 = 55, 76 Q0 = 56, 77 Q1 = 57, 78 Q2 = 58, 79 Q3 = 59, 80 Q4 = 60, 81 Q5 = 61, 82 Q6 = 62, 83 Q7 = 63, 84 Q8 = 64, 85 Q9 = 65, 86 Q10 = 66, 87 Q11 = 67, 88 Q12 = 68, 89 Q13 = 69, 90 Q14 = 70, 91 Q15 = 71, 92 R0 = 72, 93 R1 = 73, 94 R2 = 74, 95 R3 = 75, 96 R4 = 76, 97 R5 = 77, 98 R6 = 78, 99 R7 = 79, 100 R8 = 80, 101 R9 = 81, 102 R10 = 82, 103 R11 = 83, 104 R12 = 84, 105 S0 = 85, 106 S1 = 86, 107 S2 = 87, 108 S3 = 88, 109 S4 = 89, 110 S5 = 90, 111 S6 = 91, 112 S7 = 92, 113 S8 = 93, 114 S9 = 94, 115 S10 = 95, 116 S11 = 96, 117 S12 = 97, 118 S13 = 98, 119 S14 = 99, 120 S15 = 100, 121 S16 = 101, 122 S17 = 102, 123 S18 = 103, 124 S19 = 104, 125 S20 = 105, 126 S21 = 106, 127 S22 = 107, 128 S23 = 108, 129 S24 = 109, 130 S25 = 110, 131 S26 = 111, 132 S27 = 112, 133 S28 = 113, 134 S29 = 114, 135 S30 = 115, 136 S31 = 116, 137 D0_D2 = 117, 138 D1_D3 = 118, 139 D2_D4 = 119, 140 D3_D5 = 120, 141 D4_D6 = 121, 142 D5_D7 = 122, 143 D6_D8 = 123, 144 D7_D9 = 124, 145 D8_D10 = 125, 146 D9_D11 = 126, 147 D10_D12 = 127, 148 D11_D13 = 128, 149 D12_D14 = 129, 150 D13_D15 = 130, 151 D14_D16 = 131, 152 D15_D17 = 132, 153 D16_D18 = 133, 154 D17_D19 = 134, 155 D18_D20 = 135, 156 D19_D21 = 136, 157 D20_D22 = 137, 158 D21_D23 = 138, 159 D22_D24 = 139, 160 D23_D25 = 140, 161 D24_D26 = 141, 162 D25_D27 = 142, 163 D26_D28 = 143, 164 D27_D29 = 144, 165 D28_D30 = 145, 166 D29_D31 = 146, 167 Q0_Q1 = 147, 168 Q1_Q2 = 148, 169 Q2_Q3 = 149, 170 Q3_Q4 = 150, 171 Q4_Q5 = 151, 172 Q5_Q6 = 152, 173 Q6_Q7 = 153, 174 Q7_Q8 = 154, 175 Q8_Q9 = 155, 176 Q9_Q10 = 156, 177 Q10_Q11 = 157, 178 Q11_Q12 = 158, 179 Q12_Q13 = 159, 180 Q13_Q14 = 160, 181 Q14_Q15 = 161, 182 Q0_Q1_Q2_Q3 = 162, 183 Q1_Q2_Q3_Q4 = 163, 184 Q2_Q3_Q4_Q5 = 164, 185 Q3_Q4_Q5_Q6 = 165, 186 Q4_Q5_Q6_Q7 = 166, 187 Q5_Q6_Q7_Q8 = 167, 188 Q6_Q7_Q8_Q9 = 168, 189 Q7_Q8_Q9_Q10 = 169, 190 Q8_Q9_Q10_Q11 = 170, 191 Q9_Q10_Q11_Q12 = 171, 192 Q10_Q11_Q12_Q13 = 172, 193 Q11_Q12_Q13_Q14 = 173, 194 Q12_Q13_Q14_Q15 = 174, 195 R0_R1 = 175, 196 R2_R3 = 176, 197 R4_R5 = 177, 198 R6_R7 = 178, 199 R8_R9 = 179, 200 R10_R11 = 180, 201 R12_SP = 181, 202 D0_D1_D2 = 182, 203 D1_D2_D3 = 183, 204 D2_D3_D4 = 184, 205 D3_D4_D5 = 185, 206 D4_D5_D6 = 186, 207 D5_D6_D7 = 187, 208 D6_D7_D8 = 188, 209 D7_D8_D9 = 189, 210 D8_D9_D10 = 190, 211 D9_D10_D11 = 191, 212 D10_D11_D12 = 192, 213 D11_D12_D13 = 193, 214 D12_D13_D14 = 194, 215 D13_D14_D15 = 195, 216 D14_D15_D16 = 196, 217 D15_D16_D17 = 197, 218 D16_D17_D18 = 198, 219 D17_D18_D19 = 199, 220 D18_D19_D20 = 200, 221 D19_D20_D21 = 201, 222 D20_D21_D22 = 202, 223 D21_D22_D23 = 203, 224 D22_D23_D24 = 204, 225 D23_D24_D25 = 205, 226 D24_D25_D26 = 206, 227 D25_D26_D27 = 207, 228 D26_D27_D28 = 208, 229 D27_D28_D29 = 209, 230 D28_D29_D30 = 210, 231 D29_D30_D31 = 211, 232 D0_D2_D4 = 212, 233 D1_D3_D5 = 213, 234 D2_D4_D6 = 214, 235 D3_D5_D7 = 215, 236 D4_D6_D8 = 216, 237 D5_D7_D9 = 217, 238 D6_D8_D10 = 218, 239 D7_D9_D11 = 219, 240 D8_D10_D12 = 220, 241 D9_D11_D13 = 221, 242 D10_D12_D14 = 222, 243 D11_D13_D15 = 223, 244 D12_D14_D16 = 224, 245 D13_D15_D17 = 225, 246 D14_D16_D18 = 226, 247 D15_D17_D19 = 227, 248 D16_D18_D20 = 228, 249 D17_D19_D21 = 229, 250 D18_D20_D22 = 230, 251 D19_D21_D23 = 231, 252 D20_D22_D24 = 232, 253 D21_D23_D25 = 233, 254 D22_D24_D26 = 234, 255 D23_D25_D27 = 235, 256 D24_D26_D28 = 236, 257 D25_D27_D29 = 237, 258 D26_D28_D30 = 238, 259 D27_D29_D31 = 239, 260 D0_D2_D4_D6 = 240, 261 D1_D3_D5_D7 = 241, 262 D2_D4_D6_D8 = 242, 263 D3_D5_D7_D9 = 243, 264 D4_D6_D8_D10 = 244, 265 D5_D7_D9_D11 = 245, 266 D6_D8_D10_D12 = 246, 267 D7_D9_D11_D13 = 247, 268 D8_D10_D12_D14 = 248, 269 D9_D11_D13_D15 = 249, 270 D10_D12_D14_D16 = 250, 271 D11_D13_D15_D17 = 251, 272 D12_D14_D16_D18 = 252, 273 D13_D15_D17_D19 = 253, 274 D14_D16_D18_D20 = 254, 275 D15_D17_D19_D21 = 255, 276 D16_D18_D20_D22 = 256, 277 D17_D19_D21_D23 = 257, 278 D18_D20_D22_D24 = 258, 279 D19_D21_D23_D25 = 259, 280 D20_D22_D24_D26 = 260, 281 D21_D23_D25_D27 = 261, 282 D22_D24_D26_D28 = 262, 283 D23_D25_D27_D29 = 263, 284 D24_D26_D28_D30 = 264, 285 D25_D27_D29_D31 = 265, 286 D1_D2 = 266, 287 D3_D4 = 267, 288 D5_D6 = 268, 289 D7_D8 = 269, 290 D9_D10 = 270, 291 D11_D12 = 271, 292 D13_D14 = 272, 293 D15_D16 = 273, 294 D17_D18 = 274, 295 D19_D20 = 275, 296 D21_D22 = 276, 297 D23_D24 = 277, 298 D25_D26 = 278, 299 D27_D28 = 279, 300 D29_D30 = 280, 301 D1_D2_D3_D4 = 281, 302 D3_D4_D5_D6 = 282, 303 D5_D6_D7_D8 = 283, 304 D7_D8_D9_D10 = 284, 305 D9_D10_D11_D12 = 285, 306 D11_D12_D13_D14 = 286, 307 D13_D14_D15_D16 = 287, 308 D15_D16_D17_D18 = 288, 309 D17_D18_D19_D20 = 289, 310 D19_D20_D21_D22 = 290, 311 D21_D22_D23_D24 = 291, 312 D23_D24_D25_D26 = 292, 313 D25_D26_D27_D28 = 293, 314 D27_D28_D29_D30 = 294, 315 NUM_TARGET_REGS // 295 316}; 317} // end namespace ARM 318 319// Register classes 320 321namespace ARM { 322enum { 323 HPRRegClassID = 0, 324 FPWithVPRRegClassID = 1, 325 SPRRegClassID = 2, 326 FPWithVPR_with_ssub_0RegClassID = 3, 327 GPRRegClassID = 4, 328 GPRwithAPSRRegClassID = 5, 329 GPRwithZRRegClassID = 6, 330 SPR_8RegClassID = 7, 331 GPRnopcRegClassID = 8, 332 GPRwithAPSRnospRegClassID = 9, 333 GPRwithZRnospRegClassID = 10, 334 rGPRRegClassID = 11, 335 tGPRwithpcRegClassID = 12, 336 FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID = 13, 337 hGPRRegClassID = 14, 338 tGPRRegClassID = 15, 339 tGPREvenRegClassID = 16, 340 GPRnopc_and_hGPRRegClassID = 17, 341 GPRwithAPSRnosp_and_hGPRRegClassID = 18, 342 tGPROddRegClassID = 19, 343 tcGPRRegClassID = 20, 344 hGPR_and_tGPREvenRegClassID = 21, 345 tGPR_and_tGPREvenRegClassID = 22, 346 tGPR_and_tGPROddRegClassID = 23, 347 tGPR_and_tcGPRRegClassID = 24, 348 tGPREven_and_tcGPRRegClassID = 25, 349 hGPR_and_tGPROddRegClassID = 26, 350 tGPREven_and_tGPR_and_tcGPRRegClassID = 27, 351 tGPROdd_and_tcGPRRegClassID = 28, 352 CCRRegClassID = 29, 353 GPRlrRegClassID = 30, 354 GPRspRegClassID = 31, 355 VCCRRegClassID = 32, 356 cl_FPSCR_NZCVRegClassID = 33, 357 hGPR_and_tGPRwithpcRegClassID = 34, 358 hGPR_and_tcGPRRegClassID = 35, 359 DPRRegClassID = 36, 360 DPR_VFP2RegClassID = 37, 361 DPR_8RegClassID = 38, 362 GPRPairRegClassID = 39, 363 GPRPairnospRegClassID = 40, 364 GPRPair_with_gsub_0_in_tGPRRegClassID = 41, 365 GPRPair_with_gsub_0_in_hGPRRegClassID = 42, 366 GPRPair_with_gsub_0_in_tcGPRRegClassID = 43, 367 GPRPair_with_gsub_1_in_tcGPRRegClassID = 44, 368 GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClassID = 45, 369 GPRPair_with_gsub_1_in_GPRspRegClassID = 46, 370 DPairSpcRegClassID = 47, 371 DPairSpc_with_ssub_0RegClassID = 48, 372 DPairSpc_with_ssub_4RegClassID = 49, 373 DPairSpc_with_dsub_0_in_DPR_8RegClassID = 50, 374 DPairSpc_with_dsub_2_in_DPR_8RegClassID = 51, 375 DPairRegClassID = 52, 376 DPair_with_ssub_0RegClassID = 53, 377 QPRRegClassID = 54, 378 DPair_with_ssub_2RegClassID = 55, 379 DPair_with_dsub_0_in_DPR_8RegClassID = 56, 380 MQPRRegClassID = 57, 381 QPR_VFP2RegClassID = 58, 382 DPair_with_dsub_1_in_DPR_8RegClassID = 59, 383 QPR_8RegClassID = 60, 384 DTripleRegClassID = 61, 385 DTripleSpcRegClassID = 62, 386 DTripleSpc_with_ssub_0RegClassID = 63, 387 DTriple_with_ssub_0RegClassID = 64, 388 DTriple_with_qsub_0_in_QPRRegClassID = 65, 389 DTriple_with_ssub_2RegClassID = 66, 390 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 67, 391 DTripleSpc_with_ssub_4RegClassID = 68, 392 DTriple_with_ssub_4RegClassID = 69, 393 DTripleSpc_with_ssub_8RegClassID = 70, 394 DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 71, 395 DTriple_with_dsub_0_in_DPR_8RegClassID = 72, 396 DTriple_with_qsub_0_in_MQPRRegClassID = 73, 397 DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 74, 398 DTriple_with_dsub_1_in_DPR_8RegClassID = 75, 399 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 76, 400 DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClassID = 77, 401 DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 78, 402 DTriple_with_dsub_2_in_DPR_8RegClassID = 79, 403 DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 80, 404 DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 81, 405 DTriple_with_qsub_0_in_QPR_8RegClassID = 82, 406 DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRRegClassID = 83, 407 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 84, 408 DQuadSpcRegClassID = 85, 409 DQuadSpc_with_ssub_0RegClassID = 86, 410 DQuadSpc_with_ssub_4RegClassID = 87, 411 DQuadSpc_with_ssub_8RegClassID = 88, 412 DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 89, 413 DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 90, 414 DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 91, 415 DQuadRegClassID = 92, 416 DQuad_with_ssub_0RegClassID = 93, 417 DQuad_with_ssub_2RegClassID = 94, 418 QQPRRegClassID = 95, 419 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 96, 420 DQuad_with_ssub_4RegClassID = 97, 421 DQuad_with_ssub_6RegClassID = 98, 422 DQuad_with_dsub_0_in_DPR_8RegClassID = 99, 423 DQuad_with_qsub_0_in_MQPRRegClassID = 100, 424 DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 101, 425 DQuad_with_dsub_1_in_DPR_8RegClassID = 102, 426 DQuad_with_qsub_1_in_MQPRRegClassID = 103, 427 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 104, 428 DQuad_with_dsub_2_in_DPR_8RegClassID = 105, 429 DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 106, 430 DQuad_with_dsub_3_in_DPR_8RegClassID = 107, 431 DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 108, 432 DQuad_with_qsub_0_in_QPR_8RegClassID = 109, 433 DQuad_with_qsub_1_in_QPR_8RegClassID = 110, 434 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 111, 435 DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 112, 436 QQQQPRRegClassID = 113, 437 QQQQPR_with_ssub_0RegClassID = 114, 438 QQQQPR_with_ssub_4RegClassID = 115, 439 QQQQPR_with_ssub_8RegClassID = 116, 440 QQQQPR_with_ssub_12RegClassID = 117, 441 QQQQPR_with_dsub_0_in_DPR_8RegClassID = 118, 442 QQQQPR_with_dsub_2_in_DPR_8RegClassID = 119, 443 QQQQPR_with_dsub_4_in_DPR_8RegClassID = 120, 444 QQQQPR_with_dsub_6_in_DPR_8RegClassID = 121, 445 446 }; 447} // end namespace ARM 448 449 450// Register alternate name indices 451 452namespace ARM { 453enum { 454 NoRegAltName, // 0 455 RegNamesRaw, // 1 456 NUM_TARGET_REG_ALT_NAMES = 2 457}; 458} // end namespace ARM 459 460 461// Subregister indices 462 463namespace ARM { 464enum { 465 NoSubRegister, 466 dsub_0, // 1 467 dsub_1, // 2 468 dsub_2, // 3 469 dsub_3, // 4 470 dsub_4, // 5 471 dsub_5, // 6 472 dsub_6, // 7 473 dsub_7, // 8 474 gsub_0, // 9 475 gsub_1, // 10 476 qqsub_0, // 11 477 qqsub_1, // 12 478 qsub_0, // 13 479 qsub_1, // 14 480 qsub_2, // 15 481 qsub_3, // 16 482 ssub_0, // 17 483 ssub_1, // 18 484 ssub_2, // 19 485 ssub_3, // 20 486 ssub_4, // 21 487 ssub_5, // 22 488 ssub_6, // 23 489 ssub_7, // 24 490 ssub_8, // 25 491 ssub_9, // 26 492 ssub_10, // 27 493 ssub_11, // 28 494 ssub_12, // 29 495 ssub_13, // 30 496 dsub_7_then_ssub_0, // 31 497 dsub_7_then_ssub_1, // 32 498 ssub_0_ssub_1_ssub_4_ssub_5, // 33 499 ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5, // 34 500 ssub_2_ssub_3_ssub_6_ssub_7, // 35 501 ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, // 36 502 ssub_2_ssub_3_ssub_4_ssub_5, // 37 503 ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9, // 38 504 ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, // 39 505 ssub_2_ssub_3_ssub_6_ssub_7_dsub_5, // 40 506 ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7, // 41 507 ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, // 42 508 ssub_4_ssub_5_ssub_8_ssub_9, // 43 509 ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, // 44 510 ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, // 45 511 ssub_6_ssub_7_dsub_5, // 46 512 ssub_6_ssub_7_ssub_8_ssub_9_dsub_5, // 47 513 ssub_6_ssub_7_dsub_5_dsub_7, // 48 514 ssub_6_ssub_7_ssub_8_ssub_9, // 49 515 ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 50 516 ssub_8_ssub_9_ssub_12_ssub_13, // 51 517 ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 52 518 dsub_5_dsub_7, // 53 519 dsub_5_ssub_12_ssub_13_dsub_7, // 54 520 dsub_5_ssub_12_ssub_13, // 55 521 ssub_4_ssub_5_ssub_6_ssub_7_qsub_2, // 56 522 NUM_TARGET_SUBREGS 523}; 524} // end namespace ARM 525 526} // end namespace llvm 527 528#endif // GET_REGINFO_ENUM 529 530/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 531|* *| 532|* MC Register Information *| 533|* *| 534|* Automatically generated file, do not edit! *| 535|* *| 536\*===----------------------------------------------------------------------===*/ 537 538 539#ifdef GET_REGINFO_MC_DESC 540#undef GET_REGINFO_MC_DESC 541 542namespace llvm { 543 544extern const MCPhysReg ARMRegDiffLists[] = { 545 /* 0 */ 64905, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 546 /* 17 */ 37, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 547 /* 32 */ 41, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 548 /* 45 */ 45, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 549 /* 56 */ 64431, 1, 1, 1, 1, 1, 1, 1, 0, 550 /* 65 */ 64965, 1, 1, 1, 1, 1, 1, 1, 0, 551 /* 74 */ 65245, 1, 1, 1, 1, 1, 1, 1, 0, 552 /* 83 */ 43, 1, 1, 1, 1, 1, 1, 0, 553 /* 91 */ 45, 1, 1, 1, 1, 1, 0, 554 /* 98 */ 65189, 1, 1, 1, 1, 1, 0, 555 /* 105 */ 45, 1, 1, 1, 1, 0, 556 /* 111 */ 47, 1, 1, 1, 1, 0, 557 /* 117 */ 47, 1, 1, 1, 0, 558 /* 122 */ 64491, 1, 1, 1, 0, 559 /* 127 */ 65008, 1, 1, 1, 0, 560 /* 132 */ 65275, 1, 1, 1, 0, 561 /* 137 */ 65329, 1, 1, 1, 0, 562 /* 142 */ 13, 1, 1, 0, 563 /* 146 */ 47, 1, 1, 0, 564 /* 150 */ 65387, 1, 1, 0, 565 /* 154 */ 137, 65489, 48, 65489, 12, 121, 65416, 1, 1, 0, 566 /* 164 */ 136, 65490, 47, 65490, 12, 121, 65416, 1, 1, 0, 567 /* 174 */ 135, 65491, 46, 65491, 12, 121, 65416, 1, 1, 0, 568 /* 184 */ 134, 65492, 45, 65492, 12, 121, 65416, 1, 1, 0, 569 /* 194 */ 133, 65493, 44, 65493, 12, 121, 65416, 1, 1, 0, 570 /* 204 */ 132, 65494, 43, 65494, 12, 121, 65416, 1, 1, 0, 571 /* 214 */ 131, 65495, 42, 65495, 12, 121, 65416, 1, 1, 0, 572 /* 224 */ 130, 65496, 41, 65496, 12, 121, 65416, 1, 1, 0, 573 /* 234 */ 129, 65497, 40, 65497, 12, 121, 65416, 1, 1, 0, 574 /* 244 */ 128, 65498, 39, 65498, 12, 121, 65416, 1, 1, 0, 575 /* 254 */ 65489, 133, 65416, 1, 1, 0, 576 /* 260 */ 65490, 133, 65416, 1, 1, 0, 577 /* 266 */ 65491, 133, 65416, 1, 1, 0, 578 /* 272 */ 65492, 133, 65416, 1, 1, 0, 579 /* 278 */ 65493, 133, 65416, 1, 1, 0, 580 /* 284 */ 65494, 133, 65416, 1, 1, 0, 581 /* 290 */ 65495, 133, 65416, 1, 1, 0, 582 /* 296 */ 65496, 133, 65416, 1, 1, 0, 583 /* 302 */ 65497, 133, 65416, 1, 1, 0, 584 /* 308 */ 65498, 133, 65416, 1, 1, 0, 585 /* 314 */ 127, 65499, 38, 65499, 133, 65416, 1, 1, 0, 586 /* 323 */ 65073, 1, 3, 1, 3, 1, 3, 1, 0, 587 /* 332 */ 65129, 1, 3, 1, 3, 1, 0, 588 /* 339 */ 65319, 1, 3, 1, 0, 589 /* 344 */ 13, 1, 0, 590 /* 347 */ 14, 1, 0, 591 /* 350 */ 66, 1, 0, 592 /* 353 */ 65499, 66, 1, 65470, 67, 1, 0, 593 /* 360 */ 65290, 67, 1, 65469, 68, 1, 0, 594 /* 367 */ 65438, 66, 1, 65471, 68, 1, 0, 595 /* 374 */ 65500, 68, 1, 65468, 69, 1, 0, 596 /* 381 */ 65438, 67, 1, 65470, 69, 1, 0, 597 /* 388 */ 65291, 69, 1, 65467, 70, 1, 0, 598 /* 395 */ 65438, 68, 1, 65469, 70, 1, 0, 599 /* 402 */ 65501, 70, 1, 65466, 71, 1, 0, 600 /* 409 */ 65438, 69, 1, 65468, 71, 1, 0, 601 /* 416 */ 65292, 71, 1, 65465, 72, 1, 0, 602 /* 423 */ 65438, 70, 1, 65467, 72, 1, 0, 603 /* 430 */ 65502, 72, 1, 65464, 73, 1, 0, 604 /* 437 */ 65438, 71, 1, 65466, 73, 1, 0, 605 /* 444 */ 65293, 73, 1, 65463, 74, 1, 0, 606 /* 451 */ 65438, 72, 1, 65465, 74, 1, 0, 607 /* 458 */ 65503, 74, 1, 65462, 75, 1, 0, 608 /* 465 */ 65438, 73, 1, 65464, 75, 1, 0, 609 /* 472 */ 65294, 75, 1, 65461, 76, 1, 0, 610 /* 479 */ 65438, 74, 1, 65463, 76, 1, 0, 611 /* 486 */ 65504, 76, 1, 65460, 77, 1, 0, 612 /* 493 */ 65438, 75, 1, 65462, 77, 1, 0, 613 /* 500 */ 65295, 77, 1, 65459, 78, 1, 0, 614 /* 507 */ 65438, 76, 1, 65461, 78, 1, 0, 615 /* 514 */ 65505, 78, 1, 65458, 79, 1, 0, 616 /* 521 */ 65438, 77, 1, 65460, 79, 1, 0, 617 /* 528 */ 65296, 79, 1, 65457, 80, 1, 0, 618 /* 535 */ 65438, 78, 1, 65459, 80, 1, 0, 619 /* 542 */ 65506, 80, 1, 65456, 81, 1, 0, 620 /* 549 */ 65438, 79, 1, 65458, 81, 1, 0, 621 /* 556 */ 65038, 1, 0, 622 /* 559 */ 65256, 1, 0, 623 /* 562 */ 65298, 1, 0, 624 /* 565 */ 65299, 1, 0, 625 /* 568 */ 65300, 1, 0, 626 /* 571 */ 65301, 1, 0, 627 /* 574 */ 65302, 1, 0, 628 /* 577 */ 65303, 1, 0, 629 /* 580 */ 65304, 1, 0, 630 /* 583 */ 65453, 1, 65499, 133, 1, 65416, 1, 0, 631 /* 591 */ 138, 65488, 49, 65488, 12, 121, 65416, 1, 0, 632 /* 600 */ 65488, 13, 121, 65416, 1, 0, 633 /* 606 */ 65489, 13, 121, 65416, 1, 0, 634 /* 612 */ 65490, 13, 121, 65416, 1, 0, 635 /* 618 */ 65491, 13, 121, 65416, 1, 0, 636 /* 624 */ 65492, 13, 121, 65416, 1, 0, 637 /* 630 */ 65493, 13, 121, 65416, 1, 0, 638 /* 636 */ 65494, 13, 121, 65416, 1, 0, 639 /* 642 */ 65495, 13, 121, 65416, 1, 0, 640 /* 648 */ 65496, 13, 121, 65416, 1, 0, 641 /* 654 */ 65497, 13, 121, 65416, 1, 0, 642 /* 660 */ 65498, 13, 121, 65416, 1, 0, 643 /* 666 */ 65464, 1, 65488, 133, 65416, 121, 65416, 1, 0, 644 /* 675 */ 65463, 1, 65489, 133, 65416, 121, 65416, 1, 0, 645 /* 684 */ 65462, 1, 65490, 133, 65416, 121, 65416, 1, 0, 646 /* 693 */ 65461, 1, 65491, 133, 65416, 121, 65416, 1, 0, 647 /* 702 */ 65460, 1, 65492, 133, 65416, 121, 65416, 1, 0, 648 /* 711 */ 65459, 1, 65493, 133, 65416, 121, 65416, 1, 0, 649 /* 720 */ 65458, 1, 65494, 133, 65416, 121, 65416, 1, 0, 650 /* 729 */ 65457, 1, 65495, 133, 65416, 121, 65416, 1, 0, 651 /* 738 */ 65456, 1, 65496, 133, 65416, 121, 65416, 1, 0, 652 /* 747 */ 65455, 1, 65497, 133, 65416, 121, 65416, 1, 0, 653 /* 756 */ 65454, 1, 65498, 133, 65416, 121, 65416, 1, 0, 654 /* 765 */ 65488, 133, 65416, 1, 0, 655 /* 770 */ 65499, 134, 65416, 1, 0, 656 /* 775 */ 126, 65500, 37, 65500, 133, 65417, 1, 0, 657 /* 783 */ 65433, 1, 0, 658 /* 786 */ 65434, 1, 0, 659 /* 789 */ 65435, 1, 0, 660 /* 792 */ 65436, 1, 0, 661 /* 795 */ 65437, 1, 0, 662 /* 798 */ 65438, 1, 0, 663 /* 801 */ 65457, 1, 0, 664 /* 804 */ 65507, 1, 0, 665 /* 807 */ 65508, 1, 0, 666 /* 810 */ 65509, 1, 0, 667 /* 813 */ 65510, 1, 0, 668 /* 816 */ 65511, 1, 0, 669 /* 819 */ 65512, 1, 0, 670 /* 822 */ 65513, 1, 0, 671 /* 825 */ 65514, 1, 0, 672 /* 828 */ 65515, 1, 0, 673 /* 831 */ 65073, 1, 3, 1, 3, 1, 2, 0, 674 /* 839 */ 65129, 1, 3, 1, 2, 0, 675 /* 845 */ 65319, 1, 2, 0, 676 /* 849 */ 65073, 1, 3, 1, 2, 2, 0, 677 /* 856 */ 65129, 1, 2, 2, 0, 678 /* 861 */ 65073, 1, 2, 2, 2, 0, 679 /* 867 */ 65329, 2, 2, 2, 0, 680 /* 872 */ 65073, 1, 3, 2, 2, 0, 681 /* 878 */ 65357, 2, 2, 0, 682 /* 882 */ 65073, 1, 3, 1, 3, 2, 0, 683 /* 889 */ 65129, 1, 3, 2, 0, 684 /* 894 */ 65343, 77, 1, 65460, 79, 1, 65458, 81, 1, 12, 2, 0, 685 /* 906 */ 65343, 76, 1, 65461, 78, 1, 65459, 80, 1, 13, 2, 0, 686 /* 918 */ 65343, 75, 1, 65462, 77, 1, 65460, 79, 1, 14, 2, 0, 687 /* 930 */ 65343, 74, 1, 65463, 76, 1, 65461, 78, 1, 15, 2, 0, 688 /* 942 */ 65343, 73, 1, 65464, 75, 1, 65462, 77, 1, 16, 2, 0, 689 /* 954 */ 65343, 72, 1, 65465, 74, 1, 65463, 76, 1, 17, 2, 0, 690 /* 966 */ 65343, 71, 1, 65466, 73, 1, 65464, 75, 1, 18, 2, 0, 691 /* 978 */ 65343, 70, 1, 65467, 72, 1, 65465, 74, 1, 19, 2, 0, 692 /* 990 */ 65343, 69, 1, 65468, 71, 1, 65466, 73, 1, 20, 2, 0, 693 /* 1002 */ 65343, 68, 1, 65469, 70, 1, 65467, 72, 1, 21, 2, 0, 694 /* 1014 */ 65343, 67, 1, 65470, 69, 1, 65468, 71, 1, 22, 2, 0, 695 /* 1026 */ 65343, 66, 1, 65471, 68, 1, 65469, 70, 1, 23, 2, 0, 696 /* 1038 */ 65343, 2, 2, 94, 2, 0, 697 /* 1044 */ 65343, 81, 1, 65456, 2, 94, 2, 0, 698 /* 1052 */ 65343, 80, 1, 65457, 2, 94, 2, 0, 699 /* 1060 */ 65343, 79, 1, 65458, 81, 1, 65456, 94, 2, 0, 700 /* 1070 */ 65343, 78, 1, 65459, 80, 1, 65457, 94, 2, 0, 701 /* 1080 */ 65438, 2, 0, 702 /* 1083 */ 65452, 2, 0, 703 /* 1086 */ 65073, 1, 3, 1, 3, 1, 3, 0, 704 /* 1094 */ 65129, 1, 3, 1, 3, 0, 705 /* 1100 */ 65319, 1, 3, 0, 706 /* 1104 */ 7, 0, 707 /* 1106 */ 140, 65486, 13, 0, 708 /* 1110 */ 14, 0, 709 /* 1112 */ 126, 65501, 15, 0, 710 /* 1116 */ 13, 69, 0, 711 /* 1119 */ 65445, 65513, 1, 23, 65514, 1, 95, 65, 65472, 65, 69, 0, 712 /* 1131 */ 65445, 65512, 1, 24, 65513, 1, 95, 65, 65472, 65, 70, 0, 713 /* 1143 */ 65445, 65511, 1, 25, 65512, 1, 95, 65, 65472, 65, 71, 0, 714 /* 1155 */ 65445, 65510, 1, 26, 65511, 1, 95, 65, 65472, 65, 72, 0, 715 /* 1167 */ 65445, 65509, 1, 27, 65510, 1, 95, 65, 65472, 65, 73, 0, 716 /* 1179 */ 65445, 65508, 1, 28, 65509, 1, 95, 65, 65472, 65, 74, 0, 717 /* 1191 */ 65445, 65507, 1, 29, 65508, 1, 95, 65, 65472, 65, 75, 0, 718 /* 1203 */ 65445, 65506, 80, 1, 65456, 81, 1, 65484, 65507, 1, 95, 65, 65472, 65, 76, 0, 719 /* 1219 */ 65445, 65505, 78, 1, 65458, 79, 1, 65487, 65506, 80, 1, 65456, 81, 1, 13, 65, 65472, 65, 77, 0, 720 /* 1239 */ 65445, 65504, 76, 1, 65460, 77, 1, 65490, 65505, 78, 1, 65458, 79, 1, 15, 65, 65472, 65, 78, 0, 721 /* 1259 */ 65445, 65503, 74, 1, 65462, 75, 1, 65493, 65504, 76, 1, 65460, 77, 1, 17, 65, 65472, 65, 79, 0, 722 /* 1279 */ 65445, 65502, 72, 1, 65464, 73, 1, 65496, 65503, 74, 1, 65462, 75, 1, 19, 65, 65472, 65, 80, 0, 723 /* 1299 */ 65445, 65501, 70, 1, 65466, 71, 1, 65499, 65502, 72, 1, 65464, 73, 1, 21, 65, 65472, 65, 81, 0, 724 /* 1319 */ 65445, 65500, 68, 1, 65468, 69, 1, 65502, 65501, 70, 1, 65466, 71, 1, 23, 65, 65472, 65, 82, 0, 725 /* 1339 */ 65445, 65499, 66, 1, 65470, 67, 1, 65505, 65500, 68, 1, 65468, 69, 1, 25, 65, 65472, 65, 83, 0, 726 /* 1359 */ 97, 0, 727 /* 1361 */ 98, 0, 728 /* 1363 */ 99, 0, 729 /* 1365 */ 100, 0, 730 /* 1367 */ 101, 0, 731 /* 1369 */ 102, 0, 732 /* 1371 */ 103, 0, 733 /* 1373 */ 65373, 1, 1, 21, 75, 135, 0, 734 /* 1380 */ 65373, 1, 1, 22, 74, 136, 0, 735 /* 1387 */ 65373, 1, 1, 23, 73, 137, 0, 736 /* 1394 */ 65373, 1, 1, 24, 72, 138, 0, 737 /* 1401 */ 65373, 1, 1, 25, 71, 139, 0, 738 /* 1408 */ 65373, 1, 1, 26, 70, 140, 0, 739 /* 1415 */ 65373, 1, 1, 27, 69, 141, 0, 740 /* 1422 */ 65373, 80, 1, 65456, 81, 1, 65455, 28, 68, 142, 0, 741 /* 1433 */ 65373, 78, 1, 65458, 79, 1, 65457, 80, 1, 65484, 67, 143, 0, 742 /* 1446 */ 65373, 76, 1, 65460, 77, 1, 65459, 78, 1, 65487, 66, 144, 0, 743 /* 1459 */ 65373, 74, 1, 65462, 75, 1, 65461, 76, 1, 65490, 65, 145, 0, 744 /* 1472 */ 65373, 72, 1, 65464, 73, 1, 65463, 74, 1, 65493, 64, 146, 0, 745 /* 1485 */ 65373, 70, 1, 65466, 71, 1, 65465, 72, 1, 65496, 63, 147, 0, 746 /* 1498 */ 65373, 68, 1, 65468, 69, 1, 65467, 70, 1, 65499, 62, 148, 0, 747 /* 1511 */ 65373, 66, 1, 65470, 67, 1, 65469, 68, 1, 65502, 61, 149, 0, 748 /* 1524 */ 166, 0, 749 /* 1526 */ 65288, 1, 1, 1, 230, 1, 65400, 65, 65472, 65, 65396, 0, 750 /* 1538 */ 65287, 1, 1, 1, 231, 1, 65399, 65, 65472, 65, 65397, 0, 751 /* 1550 */ 65286, 1, 1, 1, 232, 1, 65398, 65, 65472, 65, 65398, 0, 752 /* 1562 */ 65285, 1, 1, 1, 233, 1, 65397, 65, 65472, 65, 65399, 0, 753 /* 1574 */ 65284, 1, 1, 1, 234, 1, 65396, 65, 65472, 65, 65400, 0, 754 /* 1586 */ 65283, 1, 1, 1, 235, 1, 65395, 65, 65472, 65, 65401, 0, 755 /* 1598 */ 65521, 65445, 65511, 1, 25, 65512, 1, 95, 65, 65472, 65, 71, 65419, 65445, 65513, 1, 23, 65514, 1, 95, 65, 65472, 65, 69, 65492, 28, 65509, 28, 28, 65386, 65, 30, 65442, 65, 30, 40, 15, 65402, 0, 756 /* 1637 */ 65521, 65445, 65510, 1, 26, 65511, 1, 95, 65, 65472, 65, 72, 65419, 65445, 65512, 1, 24, 65513, 1, 95, 65, 65472, 65, 70, 65491, 28, 65509, 28, 29, 65385, 65, 30, 65442, 65, 30, 41, 15, 65402, 0, 757 /* 1676 */ 65521, 65445, 65509, 1, 27, 65510, 1, 95, 65, 65472, 65, 73, 65419, 65445, 65511, 1, 25, 65512, 1, 95, 65, 65472, 65, 71, 65490, 28, 65509, 28, 30, 65384, 65, 30, 65442, 65, 30, 42, 15, 65402, 0, 758 /* 1715 */ 65521, 65445, 65508, 1, 28, 65509, 1, 95, 65, 65472, 65, 74, 65419, 65445, 65510, 1, 26, 65511, 1, 95, 65, 65472, 65, 72, 65489, 28, 65509, 28, 31, 65383, 65, 30, 65442, 65, 30, 43, 15, 65402, 0, 759 /* 1754 */ 65521, 65445, 65507, 1, 29, 65508, 1, 95, 65, 65472, 65, 75, 65419, 65445, 65509, 1, 27, 65510, 1, 95, 65, 65472, 65, 73, 65488, 28, 65509, 28, 32, 65382, 65, 30, 65442, 65, 30, 44, 15, 65402, 0, 760 /* 1793 */ 65521, 65445, 65506, 80, 1, 65456, 81, 1, 65484, 65507, 1, 95, 65, 65472, 65, 76, 65419, 65445, 65508, 1, 28, 65509, 1, 95, 65, 65472, 65, 74, 65487, 28, 65509, 28, 33, 65381, 65, 30, 65442, 65, 30, 45, 15, 65402, 0, 761 /* 1836 */ 65521, 65445, 65505, 78, 1, 65458, 79, 1, 65487, 65506, 80, 1, 65456, 81, 1, 13, 65, 65472, 65, 77, 65419, 65445, 65507, 1, 29, 65508, 1, 95, 65, 65472, 65, 75, 65486, 28, 65509, 28, 34, 65380, 65, 30, 65442, 65, 30, 46, 15, 65402, 0, 762 /* 1883 */ 65521, 65445, 65504, 76, 1, 65460, 77, 1, 65490, 65505, 78, 1, 65458, 79, 1, 15, 65, 65472, 65, 78, 65419, 65445, 65506, 80, 1, 65456, 81, 1, 65484, 65507, 1, 95, 65, 65472, 65, 76, 65485, 28, 65509, 28, 35, 65379, 65, 30, 65442, 65, 30, 47, 15, 65402, 0, 763 /* 1934 */ 65521, 65445, 65503, 74, 1, 65462, 75, 1, 65493, 65504, 76, 1, 65460, 77, 1, 17, 65, 65472, 65, 79, 65419, 65445, 65505, 78, 1, 65458, 79, 1, 65487, 65506, 80, 1, 65456, 81, 1, 13, 65, 65472, 65, 77, 65484, 28, 65509, 28, 36, 65378, 65, 30, 65442, 65, 30, 48, 15, 65402, 0, 764 /* 1989 */ 65521, 65445, 65502, 72, 1, 65464, 73, 1, 65496, 65503, 74, 1, 65462, 75, 1, 19, 65, 65472, 65, 80, 65419, 65445, 65504, 76, 1, 65460, 77, 1, 65490, 65505, 78, 1, 65458, 79, 1, 15, 65, 65472, 65, 78, 65483, 28, 65509, 28, 37, 65377, 65, 30, 65442, 65, 30, 49, 15, 65402, 0, 765 /* 2044 */ 65521, 65445, 65501, 70, 1, 65466, 71, 1, 65499, 65502, 72, 1, 65464, 73, 1, 21, 65, 65472, 65, 81, 65419, 65445, 65503, 74, 1, 65462, 75, 1, 65493, 65504, 76, 1, 65460, 77, 1, 17, 65, 65472, 65, 79, 65482, 28, 65509, 28, 38, 65376, 65, 30, 65442, 65, 30, 50, 15, 65402, 0, 766 /* 2099 */ 65521, 65445, 65500, 68, 1, 65468, 69, 1, 65502, 65501, 70, 1, 65466, 71, 1, 23, 65, 65472, 65, 82, 65419, 65445, 65502, 72, 1, 65464, 73, 1, 65496, 65503, 74, 1, 65462, 75, 1, 19, 65, 65472, 65, 80, 65481, 28, 65509, 28, 39, 65375, 65, 30, 65442, 65, 30, 51, 15, 65402, 0, 767 /* 2154 */ 65521, 65445, 65499, 66, 1, 65470, 67, 1, 65505, 65500, 68, 1, 65468, 69, 1, 25, 65, 65472, 65, 83, 65419, 65445, 65501, 70, 1, 65466, 71, 1, 65499, 65502, 72, 1, 65464, 73, 1, 21, 65, 65472, 65, 81, 65480, 28, 65509, 28, 40, 65374, 65, 30, 65442, 65, 30, 52, 15, 65402, 0, 768 /* 2209 */ 65282, 81, 1, 65455, 1, 1, 236, 1, 65394, 65, 65472, 65, 65402, 0, 769 /* 2223 */ 65281, 79, 1, 65457, 80, 1, 65456, 81, 1, 65455, 237, 1, 65393, 65, 65472, 65, 65403, 0, 770 /* 2241 */ 65280, 77, 1, 65459, 78, 1, 65458, 79, 1, 65457, 80, 1, 157, 1, 65392, 65, 65472, 65, 65404, 0, 771 /* 2261 */ 65279, 75, 1, 65461, 76, 1, 65460, 77, 1, 65459, 78, 1, 160, 1, 65391, 65, 65472, 65, 65405, 0, 772 /* 2281 */ 65278, 73, 1, 65463, 74, 1, 65462, 75, 1, 65461, 76, 1, 163, 1, 65390, 65, 65472, 65, 65406, 0, 773 /* 2301 */ 65277, 71, 1, 65465, 72, 1, 65464, 73, 1, 65463, 74, 1, 166, 1, 65389, 65, 65472, 65, 65407, 0, 774 /* 2321 */ 65276, 69, 1, 65467, 70, 1, 65466, 71, 1, 65465, 72, 1, 169, 1, 65388, 65, 65472, 65, 65408, 0, 775 /* 2341 */ 65275, 67, 1, 65469, 68, 1, 65468, 69, 1, 65467, 70, 1, 172, 1, 65387, 65, 65472, 65, 65409, 0, 776 /* 2361 */ 23, 73, 2, 63, 65488, 120, 65465, 1, 65487, 75, 26, 65447, 65, 26, 30, 65416, 66, 26, 29, 65416, 0, 777 /* 2382 */ 22, 74, 2, 63, 65487, 120, 65466, 1, 65486, 76, 26, 65446, 66, 26, 29, 65416, 0, 778 /* 2399 */ 65, 65487, 77, 26, 65446, 66, 26, 29, 65416, 0, 779 /* 2409 */ 23, 73, 2, 134, 65465, 1, 65487, 50, 65487, 75, 26, 31, 65416, 65, 26, 30, 65416, 0, 780 /* 2427 */ 22, 74, 135, 65466, 1, 65486, 77, 26, 30, 65416, 0, 781 /* 2438 */ 65, 65487, 77, 26, 30, 65416, 0, 782 /* 2445 */ 139, 65487, 50, 65487, 12, 121, 65416, 0, 783 /* 2453 */ 65487, 13, 121, 65416, 0, 784 /* 2458 */ 65465, 1, 65487, 133, 65416, 121, 65416, 0, 785 /* 2466 */ 65466, 1, 65486, 133, 65416, 0, 786 /* 2472 */ 65487, 133, 65416, 0, 787 /* 2476 */ 65468, 36, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0, 788 /* 2488 */ 65469, 36, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0, 789 /* 2500 */ 65, 65500, 66, 28, 40, 65417, 0, 790 /* 2507 */ 65452, 1, 65500, 134, 65417, 0, 791 /* 2513 */ 65315, 75, 1, 65462, 77, 1, 65460, 79, 1, 65458, 81, 1, 10, 95, 65443, 95, 65443, 0, 792 /* 2531 */ 65315, 74, 1, 65463, 76, 1, 65461, 78, 1, 65459, 80, 1, 11, 95, 65443, 95, 65443, 0, 793 /* 2549 */ 65315, 73, 1, 65464, 75, 1, 65462, 77, 1, 65460, 79, 1, 12, 95, 65443, 95, 65443, 0, 794 /* 2567 */ 65315, 72, 1, 65465, 74, 1, 65463, 76, 1, 65461, 78, 1, 13, 95, 65443, 95, 65443, 0, 795 /* 2585 */ 65315, 71, 1, 65466, 73, 1, 65464, 75, 1, 65462, 77, 1, 14, 95, 65443, 95, 65443, 0, 796 /* 2603 */ 65315, 70, 1, 65467, 72, 1, 65465, 74, 1, 65463, 76, 1, 15, 95, 65443, 95, 65443, 0, 797 /* 2621 */ 65315, 69, 1, 65468, 71, 1, 65466, 73, 1, 65464, 75, 1, 16, 95, 65443, 95, 65443, 0, 798 /* 2639 */ 65315, 68, 1, 65469, 70, 1, 65467, 72, 1, 65465, 74, 1, 17, 95, 65443, 95, 65443, 0, 799 /* 2657 */ 65315, 67, 1, 65470, 69, 1, 65468, 71, 1, 65466, 73, 1, 18, 95, 65443, 95, 65443, 0, 800 /* 2675 */ 65315, 66, 1, 65471, 68, 1, 65469, 70, 1, 65467, 72, 1, 19, 95, 65443, 95, 65443, 0, 801 /* 2693 */ 65315, 2, 2, 2, 92, 95, 65443, 95, 65443, 0, 802 /* 2703 */ 65315, 81, 1, 65456, 2, 2, 92, 95, 65443, 95, 65443, 0, 803 /* 2715 */ 65315, 80, 1, 65457, 2, 2, 92, 95, 65443, 95, 65443, 0, 804 /* 2727 */ 65315, 79, 1, 65458, 81, 1, 65456, 2, 92, 95, 65443, 95, 65443, 0, 805 /* 2741 */ 65315, 78, 1, 65459, 80, 1, 65457, 2, 92, 95, 65443, 95, 65443, 0, 806 /* 2755 */ 65315, 77, 1, 65460, 79, 1, 65458, 81, 1, 65456, 92, 95, 65443, 95, 65443, 0, 807 /* 2771 */ 65315, 76, 1, 65461, 78, 1, 65459, 80, 1, 65457, 92, 95, 65443, 95, 65443, 0, 808 /* 2787 */ 21, 75, 65, 65486, 78, 26, 65445, 0, 809 /* 2795 */ 24, 72, 2, 63, 65489, 120, 65464, 1, 65488, 74, 26, 65448, 64, 26, 31, 65416, 65, 26, 30, 65416, 92, 65445, 0, 810 /* 2818 */ 65, 65488, 76, 26, 65447, 65, 26, 30, 65416, 92, 65445, 0, 811 /* 2830 */ 26, 65446, 92, 65445, 0, 812 /* 2835 */ 24, 72, 2, 135, 65464, 1, 65488, 49, 65488, 74, 26, 32, 65416, 64, 26, 31, 65416, 65, 26, 65446, 0, 813 /* 2856 */ 65, 65488, 76, 26, 31, 65416, 65, 26, 65446, 0, 814 /* 2866 */ 25, 71, 2, 63, 65490, 120, 65463, 1, 65489, 73, 26, 65449, 63, 26, 32, 65416, 64, 26, 31, 65416, 91, 65446, 0, 815 /* 2889 */ 65, 65489, 75, 26, 65448, 64, 26, 31, 65416, 91, 65446, 0, 816 /* 2901 */ 25, 71, 2, 136, 65463, 1, 65489, 48, 65489, 73, 26, 33, 65416, 63, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0, 817 /* 2924 */ 65, 65489, 75, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0, 818 /* 2936 */ 26, 70, 2, 63, 65491, 120, 65462, 1, 65490, 72, 26, 65450, 62, 26, 33, 65416, 63, 26, 32, 65416, 90, 65447, 0, 819 /* 2959 */ 65, 65490, 74, 26, 65449, 63, 26, 32, 65416, 90, 65447, 0, 820 /* 2971 */ 26, 70, 2, 137, 65462, 1, 65490, 47, 65490, 72, 26, 34, 65416, 62, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0, 821 /* 2994 */ 65, 65490, 74, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0, 822 /* 3006 */ 27, 69, 2, 63, 65492, 120, 65461, 1, 65491, 71, 26, 65451, 61, 26, 34, 65416, 62, 26, 33, 65416, 89, 65448, 0, 823 /* 3029 */ 65, 65491, 73, 26, 65450, 62, 26, 33, 65416, 89, 65448, 0, 824 /* 3041 */ 27, 69, 2, 138, 65461, 1, 65491, 46, 65491, 71, 26, 35, 65416, 61, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0, 825 /* 3064 */ 65, 65491, 73, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0, 826 /* 3076 */ 28, 68, 2, 63, 65493, 120, 65460, 1, 65492, 70, 26, 65452, 60, 26, 35, 65416, 61, 26, 34, 65416, 88, 65449, 0, 827 /* 3099 */ 65, 65492, 72, 26, 65451, 61, 26, 34, 65416, 88, 65449, 0, 828 /* 3111 */ 28, 68, 2, 139, 65460, 1, 65492, 45, 65492, 70, 26, 36, 65416, 60, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0, 829 /* 3134 */ 65, 65492, 72, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0, 830 /* 3146 */ 65454, 29, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0, 831 /* 3170 */ 65455, 29, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0, 832 /* 3194 */ 65, 65493, 71, 26, 65452, 60, 26, 35, 65416, 87, 65450, 0, 833 /* 3206 */ 29, 67, 2, 140, 65459, 1, 65493, 44, 65493, 69, 26, 37, 65416, 59, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0, 834 /* 3229 */ 65, 65493, 71, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0, 835 /* 3241 */ 65456, 30, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0, 836 /* 3265 */ 65457, 30, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0, 837 /* 3289 */ 65, 65494, 70, 26, 65453, 59, 26, 36, 65416, 86, 65451, 0, 838 /* 3301 */ 65455, 30, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0, 839 /* 3325 */ 65456, 30, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0, 840 /* 3349 */ 65, 65494, 70, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0, 841 /* 3361 */ 65458, 31, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0, 842 /* 3385 */ 65459, 31, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0, 843 /* 3409 */ 65, 65495, 69, 26, 65454, 58, 26, 37, 65416, 85, 65452, 0, 844 /* 3421 */ 65457, 31, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0, 845 /* 3445 */ 65458, 31, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0, 846 /* 3469 */ 65, 65495, 69, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0, 847 /* 3481 */ 65460, 32, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0, 848 /* 3505 */ 65461, 32, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0, 849 /* 3529 */ 65, 65496, 68, 26, 65455, 57, 26, 38, 65416, 84, 65453, 0, 850 /* 3541 */ 65459, 32, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0, 851 /* 3565 */ 65460, 32, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0, 852 /* 3589 */ 65, 65496, 68, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0, 853 /* 3601 */ 65462, 33, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0, 854 /* 3625 */ 65463, 33, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0, 855 /* 3649 */ 65, 65497, 67, 26, 65456, 56, 26, 39, 65416, 83, 65454, 0, 856 /* 3661 */ 65461, 33, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0, 857 /* 3685 */ 65462, 33, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0, 858 /* 3709 */ 65, 65497, 67, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0, 859 /* 3721 */ 65297, 81, 1, 65455, 0, 860 /* 3726 */ 65464, 34, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0, 861 /* 3748 */ 65465, 34, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0, 862 /* 3770 */ 65, 65498, 66, 26, 65457, 55, 26, 40, 65416, 82, 65455, 0, 863 /* 3782 */ 65463, 34, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0, 864 /* 3806 */ 65464, 34, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0, 865 /* 3830 */ 65, 65498, 66, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0, 866 /* 3842 */ 65438, 81, 1, 65456, 0, 867 /* 3847 */ 65466, 35, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0, 868 /* 3866 */ 65467, 35, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0, 869 /* 3885 */ 65, 65499, 65, 2, 26, 41, 65416, 81, 65456, 0, 870 /* 3895 */ 65465, 35, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0, 871 /* 3917 */ 65466, 35, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0, 872 /* 3939 */ 65, 65499, 65, 26, 42, 65416, 54, 26, 65457, 81, 65456, 0, 873 /* 3951 */ 65438, 80, 1, 65457, 0, 874 /* 3956 */ 28, 65457, 0, 875 /* 3959 */ 65467, 36, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0, 876 /* 3977 */ 65468, 36, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0, 877 /* 3995 */ 65, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0, 878 /* 4005 */ 26, 65458, 80, 65457, 0, 879 /* 4010 */ 65469, 37, 61, 65, 65501, 65, 28, 65458, 0, 880 /* 4019 */ 65470, 37, 61, 65, 65501, 65, 28, 65458, 0, 881 /* 4028 */ 65373, 1, 1, 230, 65402, 65461, 0, 882 /* 4035 */ 65373, 1, 1, 231, 65401, 65462, 0, 883 /* 4042 */ 65373, 1, 1, 232, 65400, 65463, 0, 884 /* 4049 */ 65373, 1, 1, 233, 65399, 65464, 0, 885 /* 4056 */ 65373, 1, 1, 234, 65398, 65465, 0, 886 /* 4063 */ 65373, 1, 1, 235, 65397, 65466, 0, 887 /* 4070 */ 65373, 1, 1, 236, 65396, 65467, 0, 888 /* 4077 */ 65439, 65467, 0, 889 /* 4080 */ 65373, 81, 1, 65455, 1, 237, 65395, 65468, 0, 890 /* 4089 */ 65373, 79, 1, 65457, 80, 1, 65456, 81, 1, 156, 65394, 65469, 0, 891 /* 4102 */ 65373, 77, 1, 65459, 78, 1, 65458, 79, 1, 159, 65393, 65470, 0, 892 /* 4115 */ 65373, 75, 1, 65461, 76, 1, 65460, 77, 1, 162, 65392, 65471, 0, 893 /* 4128 */ 65373, 73, 1, 65463, 74, 1, 65462, 75, 1, 165, 65391, 65472, 0, 894 /* 4141 */ 65373, 71, 1, 65465, 72, 1, 65464, 73, 1, 168, 65390, 65473, 0, 895 /* 4154 */ 65373, 69, 1, 65467, 70, 1, 65466, 71, 1, 171, 65389, 65474, 0, 896 /* 4167 */ 65373, 67, 1, 65469, 68, 1, 65468, 69, 1, 174, 65388, 65475, 0, 897 /* 4180 */ 65534, 0, 898 /* 4182 */ 65535, 0, 899}; 900 901extern const LaneBitmask ARMLaneMaskLists[] = { 902 /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(), 903 /* 2 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask::getAll(), 904 /* 5 */ LaneBitmask(0x00000001), LaneBitmask(0x00000002), LaneBitmask::getAll(), 905 /* 8 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask::getAll(), 906 /* 11 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(), 907 /* 16 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask::getAll(), 908 /* 20 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask::getAll(), 909 /* 23 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask::getAll(), 910 /* 28 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask::getAll(), 911 /* 35 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask::getAll(), 912 /* 39 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask::getAll(), 913 /* 42 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask::getAll(), 914 /* 48 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask::getAll(), 915 /* 53 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask::getAll(), 916 /* 57 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask::getAll(), 917 /* 66 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000300), LaneBitmask::getAll(), 918 /* 74 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(), 919 /* 81 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(), 920 /* 87 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(), 921 /* 92 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask::getAll(), 922 /* 99 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000C00), LaneBitmask::getAll(), 923 /* 105 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask::getAll(), 924 /* 110 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask::getAll(), 925 /* 114 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00004000), LaneBitmask(0x00008000), LaneBitmask::getAll(), 926 /* 123 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x0000C000), LaneBitmask::getAll(), 927 /* 131 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(), 928 /* 138 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(), 929 /* 144 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(), 930 /* 149 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00001000), LaneBitmask(0x00002000), LaneBitmask(0x00004000), LaneBitmask(0x00008000), LaneBitmask(0x00010000), LaneBitmask(0x00020000), LaneBitmask::getAll(), 931 /* 166 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00001000), LaneBitmask(0x00002000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(), 932 /* 181 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(), 933 /* 194 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(), 934 /* 205 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(), 935}; 936 937extern const uint16_t ARMSubRegIdxLists[] = { 938 /* 0 */ 1, 2, 0, 939 /* 3 */ 1, 17, 18, 2, 0, 940 /* 8 */ 1, 3, 0, 941 /* 11 */ 1, 17, 18, 3, 0, 942 /* 16 */ 9, 10, 0, 943 /* 19 */ 17, 18, 0, 944 /* 22 */ 1, 17, 18, 2, 19, 20, 0, 945 /* 29 */ 1, 17, 18, 3, 21, 22, 0, 946 /* 36 */ 1, 2, 3, 13, 33, 37, 0, 947 /* 43 */ 1, 17, 18, 2, 3, 13, 33, 37, 0, 948 /* 52 */ 1, 17, 18, 2, 19, 20, 3, 13, 33, 37, 0, 949 /* 63 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 13, 33, 37, 0, 950 /* 76 */ 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 0, 951 /* 88 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 0, 952 /* 104 */ 1, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0, 953 /* 116 */ 1, 17, 18, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0, 954 /* 130 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 13, 14, 33, 34, 35, 36, 37, 0, 955 /* 148 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 23, 24, 13, 14, 33, 34, 35, 36, 37, 0, 956 /* 168 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 0, 957 /* 188 */ 1, 3, 5, 33, 43, 0, 958 /* 194 */ 1, 17, 18, 3, 5, 33, 43, 0, 959 /* 202 */ 1, 17, 18, 3, 21, 22, 5, 33, 43, 0, 960 /* 212 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 33, 43, 0, 961 /* 224 */ 1, 3, 5, 7, 33, 38, 43, 45, 51, 0, 962 /* 234 */ 1, 17, 18, 3, 5, 7, 33, 38, 43, 45, 51, 0, 963 /* 246 */ 1, 17, 18, 3, 21, 22, 5, 7, 33, 38, 43, 45, 51, 0, 964 /* 260 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 33, 38, 43, 45, 51, 0, 965 /* 276 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 29, 30, 33, 38, 43, 45, 51, 0, 966 /* 294 */ 11, 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, 967 /* 333 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, 968 /* 376 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, 969 /* 423 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, 970 /* 474 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 29, 30, 8, 31, 32, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, 971}; 972 973extern const MCRegisterInfo::SubRegCoveredBits ARMSubRegIdxRanges[] = { 974 { 65535, 65535 }, 975 { 0, 64 }, // dsub_0 976 { 64, 64 }, // dsub_1 977 { 128, 64 }, // dsub_2 978 { 192, 64 }, // dsub_3 979 { 256, 64 }, // dsub_4 980 { 320, 64 }, // dsub_5 981 { 384, 64 }, // dsub_6 982 { 448, 64 }, // dsub_7 983 { 0, 32 }, // gsub_0 984 { 32, 32 }, // gsub_1 985 { 0, 256 }, // qqsub_0 986 { 256, 256 }, // qqsub_1 987 { 0, 128 }, // qsub_0 988 { 128, 128 }, // qsub_1 989 { 256, 128 }, // qsub_2 990 { 384, 128 }, // qsub_3 991 { 0, 32 }, // ssub_0 992 { 32, 32 }, // ssub_1 993 { 64, 32 }, // ssub_2 994 { 96, 32 }, // ssub_3 995 { 128, 32 }, // ssub_4 996 { 160, 32 }, // ssub_5 997 { 192, 32 }, // ssub_6 998 { 224, 32 }, // ssub_7 999 { 256, 32 }, // ssub_8 1000 { 288, 32 }, // ssub_9 1001 { 320, 32 }, // ssub_10 1002 { 352, 32 }, // ssub_11 1003 { 384, 32 }, // ssub_12 1004 { 416, 32 }, // ssub_13 1005 { 448, 32 }, // dsub_7_then_ssub_0 1006 { 480, 32 }, // dsub_7_then_ssub_1 1007 { 65535, 128 }, // ssub_0_ssub_1_ssub_4_ssub_5 1008 { 0, 192 }, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 1009 { 65535, 128 }, // ssub_2_ssub_3_ssub_6_ssub_7 1010 { 64, 192 }, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 1011 { 64, 128 }, // ssub_2_ssub_3_ssub_4_ssub_5 1012 { 65535, 192 }, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 1013 { 65535, 256 }, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 1014 { 65535, 192 }, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 1015 { 65535, 256 }, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 1016 { 64, 256 }, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 1017 { 65535, 128 }, // ssub_4_ssub_5_ssub_8_ssub_9 1018 { 128, 192 }, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 1019 { 65535, 192 }, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 1020 { 65535, 128 }, // ssub_6_ssub_7_dsub_5 1021 { 192, 192 }, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 1022 { 65535, 192 }, // ssub_6_ssub_7_dsub_5_dsub_7 1023 { 192, 128 }, // ssub_6_ssub_7_ssub_8_ssub_9 1024 { 192, 256 }, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 1025 { 65535, 128 }, // ssub_8_ssub_9_ssub_12_ssub_13 1026 { 256, 192 }, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 1027 { 65535, 128 }, // dsub_5_dsub_7 1028 { 320, 192 }, // dsub_5_ssub_12_ssub_13_dsub_7 1029 { 320, 128 }, // dsub_5_ssub_12_ssub_13 1030 { 128, 256 }, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 1031}; 1032 1033extern const char ARMRegStrings[] = { 1034 /* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0, 1035 /* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0, 1036 /* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0, 1037 /* 39 */ 'R', '1', '0', 0, 1038 /* 43 */ 'S', '1', '0', 0, 1039 /* 47 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0, 1040 /* 63 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0, 1041 /* 79 */ 'S', '2', '0', 0, 1042 /* 83 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0, 1043 /* 99 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0, 1044 /* 115 */ 'S', '3', '0', 0, 1045 /* 119 */ 'D', '0', 0, 1046 /* 122 */ 'P', '0', 0, 1047 /* 125 */ 'Q', '0', 0, 1048 /* 128 */ 'M', 'V', 'F', 'R', '0', 0, 1049 /* 134 */ 'S', '0', 0, 1050 /* 137 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0, 1051 /* 148 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0, 1052 /* 161 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0, 1053 /* 175 */ 'R', '1', '0', '_', 'R', '1', '1', 0, 1054 /* 183 */ 'S', '1', '1', 0, 1055 /* 187 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0, 1056 /* 199 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0, 1057 /* 215 */ 'S', '2', '1', 0, 1058 /* 219 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0, 1059 /* 231 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0, 1060 /* 247 */ 'S', '3', '1', 0, 1061 /* 251 */ 'D', '1', 0, 1062 /* 254 */ 'Q', '0', '_', 'Q', '1', 0, 1063 /* 260 */ 'M', 'V', 'F', 'R', '1', 0, 1064 /* 266 */ 'R', '0', '_', 'R', '1', 0, 1065 /* 272 */ 'S', '1', 0, 1066 /* 275 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0, 1067 /* 289 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0, 1068 /* 304 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0, 1069 /* 319 */ 'R', '1', '2', 0, 1070 /* 323 */ 'S', '1', '2', 0, 1071 /* 327 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0, 1072 /* 343 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0, 1073 /* 359 */ 'S', '2', '2', 0, 1074 /* 363 */ 'D', '0', '_', 'D', '2', 0, 1075 /* 369 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0, 1076 /* 378 */ 'Q', '1', '_', 'Q', '2', 0, 1077 /* 384 */ 'M', 'V', 'F', 'R', '2', 0, 1078 /* 390 */ 'S', '2', 0, 1079 /* 393 */ 'F', 'P', 'I', 'N', 'S', 'T', '2', 0, 1080 /* 401 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0, 1081 /* 415 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0, 1082 /* 427 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0, 1083 /* 443 */ 'S', '1', '3', 0, 1084 /* 447 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0, 1085 /* 463 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0, 1086 /* 475 */ 'S', '2', '3', 0, 1087 /* 479 */ 'D', '1', '_', 'D', '3', 0, 1088 /* 485 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0, 1089 /* 494 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0, 1090 /* 506 */ 'R', '2', '_', 'R', '3', 0, 1091 /* 512 */ 'S', '3', 0, 1092 /* 515 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0, 1093 /* 530 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0, 1094 /* 546 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0, 1095 /* 562 */ 'S', '1', '4', 0, 1096 /* 566 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0, 1097 /* 582 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0, 1098 /* 598 */ 'S', '2', '4', 0, 1099 /* 602 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0, 1100 /* 611 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0, 1101 /* 623 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0, 1102 /* 635 */ 'R', '4', 0, 1103 /* 638 */ 'S', '4', 0, 1104 /* 641 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0, 1105 /* 656 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0, 1106 /* 668 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0, 1107 /* 684 */ 'S', '1', '5', 0, 1108 /* 688 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0, 1109 /* 704 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0, 1110 /* 716 */ 'S', '2', '5', 0, 1111 /* 720 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0, 1112 /* 729 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0, 1113 /* 738 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0, 1114 /* 750 */ 'R', '4', '_', 'R', '5', 0, 1115 /* 756 */ 'S', '5', 0, 1116 /* 759 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0, 1117 /* 775 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0, 1118 /* 791 */ 'S', '1', '6', 0, 1119 /* 795 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0, 1120 /* 811 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0, 1121 /* 827 */ 'S', '2', '6', 0, 1122 /* 831 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0, 1123 /* 843 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0, 1124 /* 855 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0, 1125 /* 867 */ 'R', '6', 0, 1126 /* 870 */ 'S', '6', 0, 1127 /* 873 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0, 1128 /* 889 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0, 1129 /* 901 */ 'S', '1', '7', 0, 1130 /* 905 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0, 1131 /* 921 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0, 1132 /* 933 */ 'S', '2', '7', 0, 1133 /* 937 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0, 1134 /* 949 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0, 1135 /* 958 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0, 1136 /* 970 */ 'R', '6', '_', 'R', '7', 0, 1137 /* 976 */ 'S', '7', 0, 1138 /* 979 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0, 1139 /* 995 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0, 1140 /* 1011 */ 'S', '1', '8', 0, 1141 /* 1015 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0, 1142 /* 1031 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0, 1143 /* 1047 */ 'S', '2', '8', 0, 1144 /* 1051 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0, 1145 /* 1063 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0, 1146 /* 1075 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0, 1147 /* 1087 */ 'R', '8', 0, 1148 /* 1090 */ 'S', '8', 0, 1149 /* 1093 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0, 1150 /* 1109 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0, 1151 /* 1121 */ 'S', '1', '9', 0, 1152 /* 1125 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0, 1153 /* 1141 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0, 1154 /* 1153 */ 'S', '2', '9', 0, 1155 /* 1157 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0, 1156 /* 1169 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0, 1157 /* 1178 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0, 1158 /* 1190 */ 'R', '8', '_', 'R', '9', 0, 1159 /* 1196 */ 'S', '9', 0, 1160 /* 1199 */ 'P', 'C', 0, 1161 /* 1202 */ 'F', 'P', 'S', 'C', 'R', '_', 'N', 'Z', 'C', 'V', 'Q', 'C', 0, 1162 /* 1215 */ 'F', 'P', 'E', 'X', 'C', 0, 1163 /* 1221 */ 'F', 'P', 'S', 'I', 'D', 0, 1164 /* 1227 */ 'I', 'T', 'S', 'T', 'A', 'T', 'E', 0, 1165 /* 1235 */ 'R', '1', '2', '_', 'S', 'P', 0, 1166 /* 1242 */ 'F', 'P', 'S', 'C', 'R', 0, 1167 /* 1248 */ 'L', 'R', 0, 1168 /* 1251 */ 'V', 'P', 'R', 0, 1169 /* 1255 */ 'A', 'P', 'S', 'R', 0, 1170 /* 1260 */ 'C', 'P', 'S', 'R', 0, 1171 /* 1265 */ 'S', 'P', 'S', 'R', 0, 1172 /* 1270 */ 'Z', 'R', 0, 1173 /* 1273 */ 'F', 'P', 'C', 'X', 'T', 'N', 'S', 0, 1174 /* 1281 */ 'F', 'P', 'C', 'X', 'T', 'S', 0, 1175 /* 1288 */ 'F', 'P', 'I', 'N', 'S', 'T', 0, 1176 /* 1295 */ 'F', 'P', 'S', 'C', 'R', '_', 'N', 'Z', 'C', 'V', 0, 1177 /* 1306 */ 'A', 'P', 'S', 'R', '_', 'N', 'Z', 'C', 'V', 0, 1178}; 1179 1180extern const MCRegisterDesc ARMRegDesc[] = { // Descriptors 1181 { 12, 0, 0, 0, 0, 0 }, 1182 { 1255, 16, 16, 2, 66913, 0 }, 1183 { 1306, 16, 16, 2, 66913, 0 }, 1184 { 1260, 16, 16, 2, 66913, 0 }, 1185 { 1273, 16, 16, 2, 66913, 0 }, 1186 { 1281, 16, 16, 2, 66913, 0 }, 1187 { 1215, 16, 16, 2, 66913, 0 }, 1188 { 1288, 16, 16, 2, 66913, 0 }, 1189 { 1242, 16, 16, 2, 17664, 0 }, 1190 { 1295, 16, 16, 2, 17664, 0 }, 1191 { 1202, 16, 16, 2, 66881, 0 }, 1192 { 1221, 16, 16, 2, 66881, 0 }, 1193 { 1227, 16, 16, 2, 66881, 0 }, 1194 { 1248, 16, 16, 2, 66881, 0 }, 1195 { 1199, 16, 16, 2, 66881, 0 }, 1196 { 1239, 16, 1524, 2, 66881, 0 }, 1197 { 1265, 16, 16, 2, 66881, 0 }, 1198 { 1251, 16, 16, 2, 66881, 0 }, 1199 { 1270, 16, 16, 2, 66881, 0 }, 1200 { 119, 350, 4011, 19, 13250, 8 }, 1201 { 251, 357, 2477, 19, 13250, 8 }, 1202 { 366, 364, 3960, 19, 13250, 8 }, 1203 { 482, 378, 3848, 19, 13250, 8 }, 1204 { 608, 392, 3896, 19, 13250, 8 }, 1205 { 726, 406, 3727, 19, 13250, 8 }, 1206 { 840, 420, 3783, 19, 13250, 8 }, 1207 { 946, 434, 3602, 19, 13250, 8 }, 1208 { 1060, 448, 3662, 19, 13250, 8 }, 1209 { 1166, 462, 3482, 19, 13250, 8 }, 1210 { 9, 476, 3542, 19, 13250, 8 }, 1211 { 144, 490, 3362, 19, 13250, 8 }, 1212 { 285, 504, 3422, 19, 13250, 8 }, 1213 { 411, 518, 3242, 19, 13250, 8 }, 1214 { 526, 532, 3302, 19, 13250, 8 }, 1215 { 652, 546, 3147, 19, 13250, 8 }, 1216 { 771, 16, 3206, 2, 17761, 0 }, 1217 { 885, 16, 3076, 2, 17761, 0 }, 1218 { 991, 16, 3111, 2, 17761, 0 }, 1219 { 1105, 16, 3006, 2, 17761, 0 }, 1220 { 59, 16, 3041, 2, 17761, 0 }, 1221 { 195, 16, 2936, 2, 17761, 0 }, 1222 { 339, 16, 2971, 2, 17761, 0 }, 1223 { 459, 16, 2866, 2, 17761, 0 }, 1224 { 578, 16, 2901, 2, 17761, 0 }, 1225 { 700, 16, 2795, 2, 17761, 0 }, 1226 { 807, 16, 2835, 2, 17761, 0 }, 1227 { 917, 16, 2361, 2, 17761, 0 }, 1228 { 1027, 16, 2409, 2, 17761, 0 }, 1229 { 1137, 16, 2382, 2, 17761, 0 }, 1230 { 95, 16, 2427, 2, 17761, 0 }, 1231 { 227, 16, 2787, 2, 17761, 0 }, 1232 { 393, 16, 16, 2, 17761, 0 }, 1233 { 128, 16, 16, 2, 17761, 0 }, 1234 { 260, 16, 16, 2, 17761, 0 }, 1235 { 384, 16, 16, 2, 17761, 0 }, 1236 { 122, 16, 16, 2, 17761, 0 }, 1237 { 125, 353, 1112, 22, 2196, 11 }, 1238 { 257, 374, 775, 22, 2196, 11 }, 1239 { 381, 402, 314, 22, 2196, 11 }, 1240 { 503, 430, 244, 22, 2196, 11 }, 1241 { 632, 458, 234, 22, 2196, 11 }, 1242 { 747, 486, 224, 22, 2196, 11 }, 1243 { 864, 514, 214, 22, 2196, 11 }, 1244 { 967, 542, 204, 22, 2196, 11 }, 1245 { 1084, 804, 194, 0, 12818, 20 }, 1246 { 1187, 807, 184, 0, 12818, 20 }, 1247 { 35, 810, 174, 0, 12818, 20 }, 1248 { 171, 813, 164, 0, 12818, 20 }, 1249 { 315, 816, 154, 0, 12818, 20 }, 1250 { 439, 819, 591, 0, 12818, 20 }, 1251 { 558, 822, 2445, 0, 12818, 20 }, 1252 { 680, 825, 1106, 0, 12818, 20 }, 1253 { 131, 16, 1371, 2, 66881, 0 }, 1254 { 263, 16, 1369, 2, 66881, 0 }, 1255 { 387, 16, 1369, 2, 66881, 0 }, 1256 { 509, 16, 1367, 2, 66881, 0 }, 1257 { 635, 16, 1367, 2, 66881, 0 }, 1258 { 753, 16, 1365, 2, 66881, 0 }, 1259 { 867, 16, 1365, 2, 66881, 0 }, 1260 { 973, 16, 1363, 2, 66881, 0 }, 1261 { 1087, 16, 1363, 2, 66881, 0 }, 1262 { 1193, 16, 1361, 2, 66881, 0 }, 1263 { 39, 16, 1361, 2, 66881, 0 }, 1264 { 179, 16, 1359, 2, 66881, 0 }, 1265 { 319, 16, 1359, 2, 66881, 0 }, 1266 { 134, 16, 4019, 2, 65393, 0 }, 1267 { 272, 16, 4010, 2, 65393, 0 }, 1268 { 390, 16, 2488, 2, 65393, 0 }, 1269 { 512, 16, 2476, 2, 65393, 0 }, 1270 { 638, 16, 3977, 2, 65393, 0 }, 1271 { 756, 16, 3959, 2, 65393, 0 }, 1272 { 870, 16, 3866, 2, 65393, 0 }, 1273 { 976, 16, 3847, 2, 65393, 0 }, 1274 { 1090, 16, 3917, 2, 65393, 0 }, 1275 { 1196, 16, 3895, 2, 65393, 0 }, 1276 { 43, 16, 3748, 2, 65393, 0 }, 1277 { 183, 16, 3726, 2, 65393, 0 }, 1278 { 323, 16, 3806, 2, 65393, 0 }, 1279 { 443, 16, 3782, 2, 65393, 0 }, 1280 { 562, 16, 3625, 2, 65393, 0 }, 1281 { 684, 16, 3601, 2, 65393, 0 }, 1282 { 791, 16, 3685, 2, 65393, 0 }, 1283 { 901, 16, 3661, 2, 65393, 0 }, 1284 { 1011, 16, 3505, 2, 65393, 0 }, 1285 { 1121, 16, 3481, 2, 65393, 0 }, 1286 { 79, 16, 3565, 2, 65393, 0 }, 1287 { 215, 16, 3541, 2, 65393, 0 }, 1288 { 359, 16, 3385, 2, 65393, 0 }, 1289 { 475, 16, 3361, 2, 65393, 0 }, 1290 { 598, 16, 3445, 2, 65393, 0 }, 1291 { 716, 16, 3421, 2, 65393, 0 }, 1292 { 827, 16, 3265, 2, 65393, 0 }, 1293 { 933, 16, 3241, 2, 65393, 0 }, 1294 { 1047, 16, 3325, 2, 65393, 0 }, 1295 { 1153, 16, 3301, 2, 65393, 0 }, 1296 { 115, 16, 3170, 2, 65393, 0 }, 1297 { 247, 16, 3146, 2, 65393, 0 }, 1298 { 363, 367, 4013, 29, 5426, 23 }, 1299 { 479, 381, 2500, 29, 5426, 23 }, 1300 { 605, 395, 3995, 29, 5426, 23 }, 1301 { 723, 409, 3885, 29, 5426, 23 }, 1302 { 837, 423, 3939, 29, 5426, 23 }, 1303 { 943, 437, 3770, 29, 5426, 23 }, 1304 { 1057, 451, 3830, 29, 5426, 23 }, 1305 { 1163, 465, 3649, 29, 5426, 23 }, 1306 { 6, 479, 3709, 29, 5426, 23 }, 1307 { 154, 493, 3529, 29, 5426, 23 }, 1308 { 281, 507, 3589, 29, 5426, 23 }, 1309 { 407, 521, 3409, 29, 5426, 23 }, 1310 { 522, 535, 3469, 29, 5426, 23 }, 1311 { 648, 549, 3289, 29, 5426, 23 }, 1312 { 767, 3951, 3349, 11, 17602, 35 }, 1313 { 881, 3842, 3194, 11, 13522, 35 }, 1314 { 987, 1080, 3229, 8, 17329, 39 }, 1315 { 1101, 1080, 3099, 8, 17329, 39 }, 1316 { 55, 1080, 3134, 8, 17329, 39 }, 1317 { 207, 1080, 3029, 8, 17329, 39 }, 1318 { 335, 1080, 3064, 8, 17329, 39 }, 1319 { 455, 1080, 2959, 8, 17329, 39 }, 1320 { 574, 1080, 2994, 8, 17329, 39 }, 1321 { 696, 1080, 2889, 8, 17329, 39 }, 1322 { 803, 1080, 2924, 8, 17329, 39 }, 1323 { 913, 1080, 2818, 8, 17329, 39 }, 1324 { 1023, 1080, 2856, 8, 17329, 39 }, 1325 { 1133, 1080, 2399, 8, 17329, 39 }, 1326 { 91, 1080, 2438, 8, 17329, 39 }, 1327 { 239, 1080, 2789, 8, 17329, 39 }, 1328 { 254, 1339, 1114, 168, 1044, 57 }, 1329 { 378, 1319, 347, 168, 1044, 57 }, 1330 { 500, 1299, 142, 168, 1044, 57 }, 1331 { 629, 1279, 142, 168, 1044, 57 }, 1332 { 744, 1259, 142, 168, 1044, 57 }, 1333 { 861, 1239, 142, 168, 1044, 57 }, 1334 { 964, 1219, 142, 168, 1044, 57 }, 1335 { 1081, 1203, 142, 88, 1456, 74 }, 1336 { 1184, 1191, 142, 76, 2114, 87 }, 1337 { 32, 1179, 142, 76, 2114, 87 }, 1338 { 167, 1167, 142, 76, 2114, 87 }, 1339 { 311, 1155, 142, 76, 2114, 87 }, 1340 { 435, 1143, 142, 76, 2114, 87 }, 1341 { 554, 1131, 344, 76, 2114, 87 }, 1342 { 676, 1119, 1108, 76, 2114, 87 }, 1343 { 494, 2154, 16, 474, 4, 149 }, 1344 { 623, 2099, 16, 474, 4, 149 }, 1345 { 738, 2044, 16, 474, 4, 149 }, 1346 { 855, 1989, 16, 474, 4, 149 }, 1347 { 958, 1934, 16, 474, 4, 149 }, 1348 { 1075, 1883, 16, 423, 272, 166 }, 1349 { 1178, 1836, 16, 376, 512, 181 }, 1350 { 26, 1793, 16, 333, 720, 194 }, 1351 { 161, 1754, 16, 294, 1186, 205 }, 1352 { 304, 1715, 16, 294, 1186, 205 }, 1353 { 427, 1676, 16, 294, 1186, 205 }, 1354 { 546, 1637, 16, 294, 1186, 205 }, 1355 { 668, 1598, 16, 294, 1186, 205 }, 1356 { 266, 783, 16, 16, 8946, 5 }, 1357 { 506, 786, 16, 16, 8946, 5 }, 1358 { 750, 789, 16, 16, 8946, 5 }, 1359 { 970, 792, 16, 16, 8946, 5 }, 1360 { 1190, 795, 16, 16, 8946, 5 }, 1361 { 175, 798, 16, 16, 8946, 5 }, 1362 { 1235, 4077, 16, 16, 17856, 2 }, 1363 { 369, 1511, 1113, 63, 1570, 28 }, 1364 { 485, 4167, 2509, 63, 1570, 28 }, 1365 { 614, 1498, 778, 63, 1570, 28 }, 1366 { 729, 4154, 770, 63, 1570, 28 }, 1367 { 846, 1485, 317, 63, 1570, 28 }, 1368 { 949, 4141, 660, 63, 1570, 28 }, 1369 { 1066, 1472, 308, 63, 1570, 28 }, 1370 { 1169, 4128, 654, 63, 1570, 28 }, 1371 { 16, 1459, 302, 63, 1570, 28 }, 1372 { 137, 4115, 648, 63, 1570, 28 }, 1373 { 292, 1446, 296, 63, 1570, 28 }, 1374 { 415, 4102, 642, 63, 1570, 28 }, 1375 { 534, 1433, 290, 63, 1570, 28 }, 1376 { 656, 4089, 636, 63, 1570, 28 }, 1377 { 779, 1422, 284, 52, 1680, 42 }, 1378 { 889, 4080, 630, 43, 1872, 48 }, 1379 { 999, 1415, 278, 36, 2401, 53 }, 1380 { 1109, 4070, 624, 36, 2401, 53 }, 1381 { 67, 1408, 272, 36, 2401, 53 }, 1382 { 187, 4063, 618, 36, 2401, 53 }, 1383 { 347, 1401, 266, 36, 2401, 53 }, 1384 { 463, 4056, 612, 36, 2401, 53 }, 1385 { 586, 1394, 260, 36, 2401, 53 }, 1386 { 704, 4049, 606, 36, 2401, 53 }, 1387 { 815, 1387, 254, 36, 2401, 53 }, 1388 { 921, 4042, 600, 36, 2401, 53 }, 1389 { 1035, 1380, 765, 36, 2401, 53 }, 1390 { 1141, 4035, 2453, 36, 2401, 53 }, 1391 { 103, 1373, 2472, 36, 2401, 53 }, 1392 { 219, 4028, 1107, 36, 2401, 53 }, 1393 { 602, 1026, 4016, 212, 5314, 92 }, 1394 { 720, 1014, 3956, 212, 5314, 92 }, 1395 { 834, 1002, 4005, 212, 5314, 92 }, 1396 { 940, 990, 3912, 212, 5314, 92 }, 1397 { 1054, 978, 3912, 212, 5314, 92 }, 1398 { 1160, 966, 3801, 212, 5314, 92 }, 1399 { 3, 954, 3801, 212, 5314, 92 }, 1400 { 151, 942, 3680, 212, 5314, 92 }, 1401 { 278, 930, 3680, 212, 5314, 92 }, 1402 { 404, 918, 3560, 212, 5314, 92 }, 1403 { 518, 906, 3560, 212, 5314, 92 }, 1404 { 644, 894, 3440, 212, 5314, 92 }, 1405 { 763, 1070, 3440, 202, 17506, 99 }, 1406 { 877, 1060, 3320, 202, 13426, 99 }, 1407 { 983, 1052, 3320, 194, 14226, 105 }, 1408 { 1097, 1044, 3224, 194, 13698, 105 }, 1409 { 51, 1038, 3224, 188, 14049, 110 }, 1410 { 203, 1038, 3129, 188, 14049, 110 }, 1411 { 331, 1038, 3129, 188, 14049, 110 }, 1412 { 451, 1038, 3059, 188, 14049, 110 }, 1413 { 570, 1038, 3059, 188, 14049, 110 }, 1414 { 692, 1038, 2989, 188, 14049, 110 }, 1415 { 799, 1038, 2989, 188, 14049, 110 }, 1416 { 909, 1038, 2919, 188, 14049, 110 }, 1417 { 1019, 1038, 2919, 188, 14049, 110 }, 1418 { 1129, 1038, 2830, 188, 14049, 110 }, 1419 { 87, 1038, 2853, 188, 14049, 110 }, 1420 { 235, 1038, 2792, 188, 14049, 110 }, 1421 { 831, 2675, 4017, 276, 5170, 114 }, 1422 { 937, 2657, 3954, 276, 5170, 114 }, 1423 { 1051, 2639, 3954, 276, 5170, 114 }, 1424 { 1157, 2621, 3845, 276, 5170, 114 }, 1425 { 0, 2603, 3845, 276, 5170, 114 }, 1426 { 148, 2585, 3724, 276, 5170, 114 }, 1427 { 275, 2567, 3724, 276, 5170, 114 }, 1428 { 401, 2549, 3623, 276, 5170, 114 }, 1429 { 515, 2531, 3623, 276, 5170, 114 }, 1430 { 641, 2513, 3503, 276, 5170, 114 }, 1431 { 759, 2771, 3503, 260, 17378, 123 }, 1432 { 873, 2755, 3383, 260, 13298, 123 }, 1433 { 979, 2741, 3383, 246, 14114, 131 }, 1434 { 1093, 2727, 3263, 246, 13586, 131 }, 1435 { 47, 2715, 3263, 234, 13954, 138 }, 1436 { 199, 2703, 3168, 234, 13778, 138 }, 1437 { 327, 2693, 3168, 224, 13873, 144 }, 1438 { 447, 2693, 3097, 224, 13873, 144 }, 1439 { 566, 2693, 3097, 224, 13873, 144 }, 1440 { 688, 2693, 3027, 224, 13873, 144 }, 1441 { 795, 2693, 3027, 224, 13873, 144 }, 1442 { 905, 2693, 2957, 224, 13873, 144 }, 1443 { 1015, 2693, 2957, 224, 13873, 144 }, 1444 { 1125, 2693, 2854, 224, 13873, 144 }, 1445 { 83, 2693, 2854, 224, 13873, 144 }, 1446 { 231, 2693, 2793, 224, 13873, 144 }, 1447 { 372, 360, 2507, 22, 1956, 11 }, 1448 { 617, 388, 583, 22, 1956, 11 }, 1449 { 849, 416, 756, 22, 1956, 11 }, 1450 { 1069, 444, 747, 22, 1956, 11 }, 1451 { 19, 472, 738, 22, 1956, 11 }, 1452 { 296, 500, 729, 22, 1956, 11 }, 1453 { 538, 528, 720, 22, 1956, 11 }, 1454 { 783, 3721, 711, 3, 2336, 16 }, 1455 { 1003, 562, 702, 0, 8898, 20 }, 1456 { 71, 565, 693, 0, 8898, 20 }, 1457 { 351, 568, 684, 0, 8898, 20 }, 1458 { 590, 571, 675, 0, 8898, 20 }, 1459 { 819, 574, 666, 0, 8898, 20 }, 1460 { 1039, 577, 2458, 0, 8898, 20 }, 1461 { 107, 580, 2466, 0, 8898, 20 }, 1462 { 611, 2341, 2486, 148, 900, 57 }, 1463 { 843, 2321, 588, 148, 900, 57 }, 1464 { 1063, 2301, 588, 148, 900, 57 }, 1465 { 13, 2281, 588, 148, 900, 57 }, 1466 { 289, 2261, 588, 148, 900, 57 }, 1467 { 530, 2241, 588, 148, 900, 57 }, 1468 { 775, 2223, 588, 130, 1328, 66 }, 1469 { 995, 2209, 588, 116, 1776, 81 }, 1470 { 63, 1586, 588, 104, 2034, 87 }, 1471 { 343, 1574, 588, 104, 2034, 87 }, 1472 { 582, 1562, 588, 104, 2034, 87 }, 1473 { 811, 1550, 588, 104, 2034, 87 }, 1474 { 1031, 1538, 588, 104, 2034, 87 }, 1475 { 99, 1526, 2380, 104, 2034, 87 }, 1476}; 1477 1478extern const MCPhysReg ARMRegUnitRoots[][2] = { 1479 { ARM::APSR }, 1480 { ARM::APSR_NZCV }, 1481 { ARM::CPSR }, 1482 { ARM::FPCXTNS }, 1483 { ARM::FPCXTS }, 1484 { ARM::FPEXC }, 1485 { ARM::FPINST }, 1486 { ARM::FPSCR, ARM::FPSCR_NZCV }, 1487 { ARM::FPSCR_NZCVQC }, 1488 { ARM::FPSID }, 1489 { ARM::ITSTATE }, 1490 { ARM::LR }, 1491 { ARM::PC }, 1492 { ARM::SP }, 1493 { ARM::SPSR }, 1494 { ARM::VPR }, 1495 { ARM::ZR }, 1496 { ARM::S0 }, 1497 { ARM::S1 }, 1498 { ARM::S2 }, 1499 { ARM::S3 }, 1500 { ARM::S4 }, 1501 { ARM::S5 }, 1502 { ARM::S6 }, 1503 { ARM::S7 }, 1504 { ARM::S8 }, 1505 { ARM::S9 }, 1506 { ARM::S10 }, 1507 { ARM::S11 }, 1508 { ARM::S12 }, 1509 { ARM::S13 }, 1510 { ARM::S14 }, 1511 { ARM::S15 }, 1512 { ARM::S16 }, 1513 { ARM::S17 }, 1514 { ARM::S18 }, 1515 { ARM::S19 }, 1516 { ARM::S20 }, 1517 { ARM::S21 }, 1518 { ARM::S22 }, 1519 { ARM::S23 }, 1520 { ARM::S24 }, 1521 { ARM::S25 }, 1522 { ARM::S26 }, 1523 { ARM::S27 }, 1524 { ARM::S28 }, 1525 { ARM::S29 }, 1526 { ARM::S30 }, 1527 { ARM::S31 }, 1528 { ARM::D16 }, 1529 { ARM::D17 }, 1530 { ARM::D18 }, 1531 { ARM::D19 }, 1532 { ARM::D20 }, 1533 { ARM::D21 }, 1534 { ARM::D22 }, 1535 { ARM::D23 }, 1536 { ARM::D24 }, 1537 { ARM::D25 }, 1538 { ARM::D26 }, 1539 { ARM::D27 }, 1540 { ARM::D28 }, 1541 { ARM::D29 }, 1542 { ARM::D30 }, 1543 { ARM::D31 }, 1544 { ARM::FPINST2 }, 1545 { ARM::MVFR0 }, 1546 { ARM::MVFR1 }, 1547 { ARM::MVFR2 }, 1548 { ARM::P0 }, 1549 { ARM::R0 }, 1550 { ARM::R1 }, 1551 { ARM::R2 }, 1552 { ARM::R3 }, 1553 { ARM::R4 }, 1554 { ARM::R5 }, 1555 { ARM::R6 }, 1556 { ARM::R7 }, 1557 { ARM::R8 }, 1558 { ARM::R9 }, 1559 { ARM::R10 }, 1560 { ARM::R11 }, 1561 { ARM::R12 }, 1562}; 1563 1564namespace { // Register classes... 1565 // HPR Register Class... 1566 const MCPhysReg HPR[] = { 1567 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31, 1568 }; 1569 1570 // HPR Bit set. 1571 const uint8_t HPRBits[] = { 1572 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 1573 }; 1574 1575 // FPWithVPR Register Class... 1576 const MCPhysReg FPWithVPR[] = { 1577 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::VPR, 1578 }; 1579 1580 // FPWithVPR Bit set. 1581 const uint8_t FPWithVPRBits[] = { 1582 0x00, 0x00, 0xfa, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 1583 }; 1584 1585 // SPR Register Class... 1586 const MCPhysReg SPR[] = { 1587 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31, 1588 }; 1589 1590 // SPR Bit set. 1591 const uint8_t SPRBits[] = { 1592 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 1593 }; 1594 1595 // FPWithVPR_with_ssub_0 Register Class... 1596 const MCPhysReg FPWithVPR_with_ssub_0[] = { 1597 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1598 }; 1599 1600 // FPWithVPR_with_ssub_0 Bit set. 1601 const uint8_t FPWithVPR_with_ssub_0Bits[] = { 1602 0x00, 0x00, 0xf8, 0xff, 0x07, 1603 }; 1604 1605 // GPR Register Class... 1606 const MCPhysReg GPR[] = { 1607 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC, 1608 }; 1609 1610 // GPR Bit set. 1611 const uint8_t GPRBits[] = { 1612 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, 1613 }; 1614 1615 // GPRwithAPSR Register Class... 1616 const MCPhysReg GPRwithAPSR[] = { 1617 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::APSR_NZCV, 1618 }; 1619 1620 // GPRwithAPSR Bit set. 1621 const uint8_t GPRwithAPSRBits[] = { 1622 0x04, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, 1623 }; 1624 1625 // GPRwithZR Register Class... 1626 const MCPhysReg GPRwithZR[] = { 1627 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::ZR, 1628 }; 1629 1630 // GPRwithZR Bit set. 1631 const uint8_t GPRwithZRBits[] = { 1632 0x00, 0xa0, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, 1633 }; 1634 1635 // SPR_8 Register Class... 1636 const MCPhysReg SPR_8[] = { 1637 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1638 }; 1639 1640 // SPR_8 Bit set. 1641 const uint8_t SPR_8Bits[] = { 1642 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 1643 }; 1644 1645 // GPRnopc Register Class... 1646 const MCPhysReg GPRnopc[] = { 1647 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, 1648 }; 1649 1650 // GPRnopc Bit set. 1651 const uint8_t GPRnopcBits[] = { 1652 0x00, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, 1653 }; 1654 1655 // GPRwithAPSRnosp Register Class... 1656 const MCPhysReg GPRwithAPSRnosp[] = { 1657 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::APSR, 1658 }; 1659 1660 // GPRwithAPSRnosp Bit set. 1661 const uint8_t GPRwithAPSRnospBits[] = { 1662 0x02, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, 1663 }; 1664 1665 // GPRwithZRnosp Register Class... 1666 const MCPhysReg GPRwithZRnosp[] = { 1667 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::ZR, 1668 }; 1669 1670 // GPRwithZRnosp Bit set. 1671 const uint8_t GPRwithZRnospBits[] = { 1672 0x00, 0x20, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, 1673 }; 1674 1675 // rGPR Register Class... 1676 const MCPhysReg rGPR[] = { 1677 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, 1678 }; 1679 1680 // rGPR Bit set. 1681 const uint8_t rGPRBits[] = { 1682 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, 1683 }; 1684 1685 // tGPRwithpc Register Class... 1686 const MCPhysReg tGPRwithpc[] = { 1687 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::PC, 1688 }; 1689 1690 // tGPRwithpc Bit set. 1691 const uint8_t tGPRwithpcBits[] = { 1692 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 1693 }; 1694 1695 // FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 Register Class... 1696 const MCPhysReg FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8[] = { 1697 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1698 }; 1699 1700 // FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 Bit set. 1701 const uint8_t FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits[] = { 1702 0x00, 0x00, 0xf8, 0x07, 1703 }; 1704 1705 // hGPR Register Class... 1706 const MCPhysReg hGPR[] = { 1707 ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC, 1708 }; 1709 1710 // hGPR Bit set. 1711 const uint8_t hGPRBits[] = { 1712 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 1713 }; 1714 1715 // tGPR Register Class... 1716 const MCPhysReg tGPR[] = { 1717 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1718 }; 1719 1720 // tGPR Bit set. 1721 const uint8_t tGPRBits[] = { 1722 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 1723 }; 1724 1725 // tGPREven Register Class... 1726 const MCPhysReg tGPREven[] = { 1727 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, ARM::R12, ARM::LR, 1728 }; 1729 1730 // tGPREven Bit set. 1731 const uint8_t tGPREvenBits[] = { 1732 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15, 1733 }; 1734 1735 // GPRnopc_and_hGPR Register Class... 1736 const MCPhysReg GPRnopc_and_hGPR[] = { 1737 ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, 1738 }; 1739 1740 // GPRnopc_and_hGPR Bit set. 1741 const uint8_t GPRnopc_and_hGPRBits[] = { 1742 0x00, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 1743 }; 1744 1745 // GPRwithAPSRnosp_and_hGPR Register Class... 1746 const MCPhysReg GPRwithAPSRnosp_and_hGPR[] = { 1747 ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, 1748 }; 1749 1750 // GPRwithAPSRnosp_and_hGPR Bit set. 1751 const uint8_t GPRwithAPSRnosp_and_hGPRBits[] = { 1752 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 1753 }; 1754 1755 // tGPROdd Register Class... 1756 const MCPhysReg tGPROdd[] = { 1757 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, 1758 }; 1759 1760 // tGPROdd Bit set. 1761 const uint8_t tGPROddBits[] = { 1762 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x0a, 1763 }; 1764 1765 // tcGPR Register Class... 1766 const MCPhysReg tcGPR[] = { 1767 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12, 1768 }; 1769 1770 // tcGPR Bit set. 1771 const uint8_t tcGPRBits[] = { 1772 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x10, 1773 }; 1774 1775 // hGPR_and_tGPREven Register Class... 1776 const MCPhysReg hGPR_and_tGPREven[] = { 1777 ARM::R8, ARM::R10, ARM::R12, ARM::LR, 1778 }; 1779 1780 // hGPR_and_tGPREven Bit set. 1781 const uint8_t hGPR_and_tGPREvenBits[] = { 1782 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 1783 }; 1784 1785 // tGPR_and_tGPREven Register Class... 1786 const MCPhysReg tGPR_and_tGPREven[] = { 1787 ARM::R0, ARM::R2, ARM::R4, ARM::R6, 1788 }; 1789 1790 // tGPR_and_tGPREven Bit set. 1791 const uint8_t tGPR_and_tGPREvenBits[] = { 1792 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 1793 }; 1794 1795 // tGPR_and_tGPROdd Register Class... 1796 const MCPhysReg tGPR_and_tGPROdd[] = { 1797 ARM::R1, ARM::R3, ARM::R5, ARM::R7, 1798 }; 1799 1800 // tGPR_and_tGPROdd Bit set. 1801 const uint8_t tGPR_and_tGPROddBits[] = { 1802 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 1803 }; 1804 1805 // tGPR_and_tcGPR Register Class... 1806 const MCPhysReg tGPR_and_tcGPR[] = { 1807 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1808 }; 1809 1810 // tGPR_and_tcGPR Bit set. 1811 const uint8_t tGPR_and_tcGPRBits[] = { 1812 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 1813 }; 1814 1815 // tGPREven_and_tcGPR Register Class... 1816 const MCPhysReg tGPREven_and_tcGPR[] = { 1817 ARM::R0, ARM::R2, ARM::R12, 1818 }; 1819 1820 // tGPREven_and_tcGPR Bit set. 1821 const uint8_t tGPREven_and_tcGPRBits[] = { 1822 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x10, 1823 }; 1824 1825 // hGPR_and_tGPROdd Register Class... 1826 const MCPhysReg hGPR_and_tGPROdd[] = { 1827 ARM::R9, ARM::R11, 1828 }; 1829 1830 // hGPR_and_tGPROdd Bit set. 1831 const uint8_t hGPR_and_tGPROddBits[] = { 1832 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 1833 }; 1834 1835 // tGPREven_and_tGPR_and_tcGPR Register Class... 1836 const MCPhysReg tGPREven_and_tGPR_and_tcGPR[] = { 1837 ARM::R0, ARM::R2, 1838 }; 1839 1840 // tGPREven_and_tGPR_and_tcGPR Bit set. 1841 const uint8_t tGPREven_and_tGPR_and_tcGPRBits[] = { 1842 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 1843 }; 1844 1845 // tGPROdd_and_tcGPR Register Class... 1846 const MCPhysReg tGPROdd_and_tcGPR[] = { 1847 ARM::R1, ARM::R3, 1848 }; 1849 1850 // tGPROdd_and_tcGPR Bit set. 1851 const uint8_t tGPROdd_and_tcGPRBits[] = { 1852 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 1853 }; 1854 1855 // CCR Register Class... 1856 const MCPhysReg CCR[] = { 1857 ARM::CPSR, 1858 }; 1859 1860 // CCR Bit set. 1861 const uint8_t CCRBits[] = { 1862 0x08, 1863 }; 1864 1865 // GPRlr Register Class... 1866 const MCPhysReg GPRlr[] = { 1867 ARM::LR, 1868 }; 1869 1870 // GPRlr Bit set. 1871 const uint8_t GPRlrBits[] = { 1872 0x00, 0x20, 1873 }; 1874 1875 // GPRsp Register Class... 1876 const MCPhysReg GPRsp[] = { 1877 ARM::SP, 1878 }; 1879 1880 // GPRsp Bit set. 1881 const uint8_t GPRspBits[] = { 1882 0x00, 0x80, 1883 }; 1884 1885 // VCCR Register Class... 1886 const MCPhysReg VCCR[] = { 1887 ARM::VPR, 1888 }; 1889 1890 // VCCR Bit set. 1891 const uint8_t VCCRBits[] = { 1892 0x00, 0x00, 0x02, 1893 }; 1894 1895 // cl_FPSCR_NZCV Register Class... 1896 const MCPhysReg cl_FPSCR_NZCV[] = { 1897 ARM::FPSCR_NZCV, 1898 }; 1899 1900 // cl_FPSCR_NZCV Bit set. 1901 const uint8_t cl_FPSCR_NZCVBits[] = { 1902 0x00, 0x02, 1903 }; 1904 1905 // hGPR_and_tGPRwithpc Register Class... 1906 const MCPhysReg hGPR_and_tGPRwithpc[] = { 1907 ARM::PC, 1908 }; 1909 1910 // hGPR_and_tGPRwithpc Bit set. 1911 const uint8_t hGPR_and_tGPRwithpcBits[] = { 1912 0x00, 0x40, 1913 }; 1914 1915 // hGPR_and_tcGPR Register Class... 1916 const MCPhysReg hGPR_and_tcGPR[] = { 1917 ARM::R12, 1918 }; 1919 1920 // hGPR_and_tcGPR Bit set. 1921 const uint8_t hGPR_and_tcGPRBits[] = { 1922 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 1923 }; 1924 1925 // DPR Register Class... 1926 const MCPhysReg DPR[] = { 1927 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, 1928 }; 1929 1930 // DPR Bit set. 1931 const uint8_t DPRBits[] = { 1932 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 1933 }; 1934 1935 // DPR_VFP2 Register Class... 1936 const MCPhysReg DPR_VFP2[] = { 1937 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1938 }; 1939 1940 // DPR_VFP2 Bit set. 1941 const uint8_t DPR_VFP2Bits[] = { 1942 0x00, 0x00, 0xf8, 0xff, 0x07, 1943 }; 1944 1945 // DPR_8 Register Class... 1946 const MCPhysReg DPR_8[] = { 1947 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1948 }; 1949 1950 // DPR_8 Bit set. 1951 const uint8_t DPR_8Bits[] = { 1952 0x00, 0x00, 0xf8, 0x07, 1953 }; 1954 1955 // GPRPair Register Class... 1956 const MCPhysReg GPRPair[] = { 1957 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11, ARM::R12_SP, 1958 }; 1959 1960 // GPRPair Bit set. 1961 const uint8_t GPRPairBits[] = { 1962 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 1963 }; 1964 1965 // GPRPairnosp Register Class... 1966 const MCPhysReg GPRPairnosp[] = { 1967 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11, 1968 }; 1969 1970 // GPRPairnosp Bit set. 1971 const uint8_t GPRPairnospBits[] = { 1972 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 1973 }; 1974 1975 // GPRPair_with_gsub_0_in_tGPR Register Class... 1976 const MCPhysReg GPRPair_with_gsub_0_in_tGPR[] = { 1977 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1978 }; 1979 1980 // GPRPair_with_gsub_0_in_tGPR Bit set. 1981 const uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = { 1982 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 1983 }; 1984 1985 // GPRPair_with_gsub_0_in_hGPR Register Class... 1986 const MCPhysReg GPRPair_with_gsub_0_in_hGPR[] = { 1987 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP, 1988 }; 1989 1990 // GPRPair_with_gsub_0_in_hGPR Bit set. 1991 const uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = { 1992 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 1993 }; 1994 1995 // GPRPair_with_gsub_0_in_tcGPR Register Class... 1996 const MCPhysReg GPRPair_with_gsub_0_in_tcGPR[] = { 1997 ARM::R0_R1, ARM::R2_R3, ARM::R12_SP, 1998 }; 1999 2000 // GPRPair_with_gsub_0_in_tcGPR Bit set. 2001 const uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = { 2002 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x21, 2003 }; 2004 2005 // GPRPair_with_gsub_1_in_tcGPR Register Class... 2006 const MCPhysReg GPRPair_with_gsub_1_in_tcGPR[] = { 2007 ARM::R0_R1, ARM::R2_R3, 2008 }; 2009 2010 // GPRPair_with_gsub_1_in_tcGPR Bit set. 2011 const uint8_t GPRPair_with_gsub_1_in_tcGPRBits[] = { 2012 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 2013 }; 2014 2015 // GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR Register Class... 2016 const MCPhysReg GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR[] = { 2017 ARM::R8_R9, ARM::R10_R11, 2018 }; 2019 2020 // GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR Bit set. 2021 const uint8_t GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits[] = { 2022 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 2023 }; 2024 2025 // GPRPair_with_gsub_1_in_GPRsp Register Class... 2026 const MCPhysReg GPRPair_with_gsub_1_in_GPRsp[] = { 2027 ARM::R12_SP, 2028 }; 2029 2030 // GPRPair_with_gsub_1_in_GPRsp Bit set. 2031 const uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = { 2032 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 2033 }; 2034 2035 // DPairSpc Register Class... 2036 const MCPhysReg DPairSpc[] = { 2037 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, ARM::D28_D30, ARM::D29_D31, 2038 }; 2039 2040 // DPairSpc Bit set. 2041 const uint8_t DPairSpcBits[] = { 2042 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x07, 2043 }; 2044 2045 // DPairSpc_with_ssub_0 Register Class... 2046 const MCPhysReg DPairSpc_with_ssub_0[] = { 2047 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 2048 }; 2049 2050 // DPairSpc_with_ssub_0 Bit set. 2051 const uint8_t DPairSpc_with_ssub_0Bits[] = { 2052 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 2053 }; 2054 2055 // DPairSpc_with_ssub_4 Register Class... 2056 const MCPhysReg DPairSpc_with_ssub_4[] = { 2057 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, 2058 }; 2059 2060 // DPairSpc_with_ssub_4 Bit set. 2061 const uint8_t DPairSpc_with_ssub_4Bits[] = { 2062 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 2063 }; 2064 2065 // DPairSpc_with_dsub_0_in_DPR_8 Register Class... 2066 const MCPhysReg DPairSpc_with_dsub_0_in_DPR_8[] = { 2067 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 2068 }; 2069 2070 // DPairSpc_with_dsub_0_in_DPR_8 Bit set. 2071 const uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = { 2072 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 2073 }; 2074 2075 // DPairSpc_with_dsub_2_in_DPR_8 Register Class... 2076 const MCPhysReg DPairSpc_with_dsub_2_in_DPR_8[] = { 2077 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, 2078 }; 2079 2080 // DPairSpc_with_dsub_2_in_DPR_8 Bit set. 2081 const uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = { 2082 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 2083 }; 2084 2085 // DPair Register Class... 2086 const MCPhysReg DPair[] = { 2087 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, ARM::Q15, 2088 }; 2089 2090 // DPair Bit set. 2091 const uint8_t DPairBits[] = { 2092 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x01, 2093 }; 2094 2095 // DPair_with_ssub_0 Register Class... 2096 const MCPhysReg DPair_with_ssub_0[] = { 2097 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, 2098 }; 2099 2100 // DPair_with_ssub_0 Bit set. 2101 const uint8_t DPair_with_ssub_0Bits[] = { 2102 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 2103 }; 2104 2105 // QPR Register Class... 2106 const MCPhysReg QPR[] = { 2107 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 2108 }; 2109 2110 // QPR Bit set. 2111 const uint8_t QPRBits[] = { 2112 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 2113 }; 2114 2115 // DPair_with_ssub_2 Register Class... 2116 const MCPhysReg DPair_with_ssub_2[] = { 2117 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, 2118 }; 2119 2120 // DPair_with_ssub_2 Bit set. 2121 const uint8_t DPair_with_ssub_2Bits[] = { 2122 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, 2123 }; 2124 2125 // DPair_with_dsub_0_in_DPR_8 Register Class... 2126 const MCPhysReg DPair_with_dsub_0_in_DPR_8[] = { 2127 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, 2128 }; 2129 2130 // DPair_with_dsub_0_in_DPR_8 Bit set. 2131 const uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = { 2132 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 2133 }; 2134 2135 // MQPR Register Class... 2136 const MCPhysReg MQPR[] = { 2137 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 2138 }; 2139 2140 // MQPR Bit set. 2141 const uint8_t MQPRBits[] = { 2142 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 2143 }; 2144 2145 // QPR_VFP2 Register Class... 2146 const MCPhysReg QPR_VFP2[] = { 2147 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 2148 }; 2149 2150 // QPR_VFP2 Bit set. 2151 const uint8_t QPR_VFP2Bits[] = { 2152 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 2153 }; 2154 2155 // DPair_with_dsub_1_in_DPR_8 Register Class... 2156 const MCPhysReg DPair_with_dsub_1_in_DPR_8[] = { 2157 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, 2158 }; 2159 2160 // DPair_with_dsub_1_in_DPR_8 Bit set. 2161 const uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = { 2162 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 2163 }; 2164 2165 // QPR_8 Register Class... 2166 const MCPhysReg QPR_8[] = { 2167 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 2168 }; 2169 2170 // QPR_8 Bit set. 2171 const uint8_t QPR_8Bits[] = { 2172 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 2173 }; 2174 2175 // DTriple Register Class... 2176 const MCPhysReg DTriple[] = { 2177 ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17, ARM::D16_D17_D18, ARM::D17_D18_D19, ARM::D18_D19_D20, ARM::D19_D20_D21, ARM::D20_D21_D22, ARM::D21_D22_D23, ARM::D22_D23_D24, ARM::D23_D24_D25, ARM::D24_D25_D26, ARM::D25_D26_D27, ARM::D26_D27_D28, ARM::D27_D28_D29, ARM::D28_D29_D30, ARM::D29_D30_D31, 2178 }; 2179 2180 // DTriple Bit set. 2181 const uint8_t DTripleBits[] = { 2182 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x0f, 2183 }; 2184 2185 // DTripleSpc Register Class... 2186 const MCPhysReg DTripleSpc[] = { 2187 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31, 2188 }; 2189 2190 // DTripleSpc Bit set. 2191 const uint8_t DTripleSpcBits[] = { 2192 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 2193 }; 2194 2195 // DTripleSpc_with_ssub_0 Register Class... 2196 const MCPhysReg DTripleSpc_with_ssub_0[] = { 2197 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, 2198 }; 2199 2200 // DTripleSpc_with_ssub_0 Bit set. 2201 const uint8_t DTripleSpc_with_ssub_0Bits[] = { 2202 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 2203 }; 2204 2205 // DTriple_with_ssub_0 Register Class... 2206 const MCPhysReg DTriple_with_ssub_0[] = { 2207 ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17, 2208 }; 2209 2210 // DTriple_with_ssub_0 Bit set. 2211 const uint8_t DTriple_with_ssub_0Bits[] = { 2212 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 2213 }; 2214 2215 // DTriple_with_qsub_0_in_QPR Register Class... 2216 const MCPhysReg DTriple_with_qsub_0_in_QPR[] = { 2217 ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16, ARM::D16_D17_D18, ARM::D18_D19_D20, ARM::D20_D21_D22, ARM::D22_D23_D24, ARM::D24_D25_D26, ARM::D26_D27_D28, ARM::D28_D29_D30, 2218 }; 2219 2220 // DTriple_with_qsub_0_in_QPR Bit set. 2221 const uint8_t DTriple_with_qsub_0_in_QPRBits[] = { 2222 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x55, 0x55, 0x55, 0x05, 2223 }; 2224 2225 // DTriple_with_ssub_2 Register Class... 2226 const MCPhysReg DTriple_with_ssub_2[] = { 2227 ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, 2228 }; 2229 2230 // DTriple_with_ssub_2 Bit set. 2231 const uint8_t DTriple_with_ssub_2Bits[] = { 2232 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, 2233 }; 2234 2235 // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... 2236 const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { 2237 ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17, ARM::D17_D18_D19, ARM::D19_D20_D21, ARM::D21_D22_D23, ARM::D23_D24_D25, ARM::D25_D26_D27, ARM::D27_D28_D29, ARM::D29_D30_D31, 2238 }; 2239 2240 // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. 2241 const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { 2242 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0x0a, 2243 }; 2244 2245 // DTripleSpc_with_ssub_4 Register Class... 2246 const MCPhysReg DTripleSpc_with_ssub_4[] = { 2247 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, 2248 }; 2249 2250 // DTripleSpc_with_ssub_4 Bit set. 2251 const uint8_t DTripleSpc_with_ssub_4Bits[] = { 2252 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 2253 }; 2254 2255 // DTriple_with_ssub_4 Register Class... 2256 const MCPhysReg DTriple_with_ssub_4[] = { 2257 ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, 2258 }; 2259 2260 // DTriple_with_ssub_4 Bit set. 2261 const uint8_t DTriple_with_ssub_4Bits[] = { 2262 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 2263 }; 2264 2265 // DTripleSpc_with_ssub_8 Register Class... 2266 const MCPhysReg DTripleSpc_with_ssub_8[] = { 2267 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, 2268 }; 2269 2270 // DTripleSpc_with_ssub_8 Bit set. 2271 const uint8_t DTripleSpc_with_ssub_8Bits[] = { 2272 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 2273 }; 2274 2275 // DTripleSpc_with_dsub_0_in_DPR_8 Register Class... 2276 const MCPhysReg DTripleSpc_with_dsub_0_in_DPR_8[] = { 2277 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, 2278 }; 2279 2280 // DTripleSpc_with_dsub_0_in_DPR_8 Bit set. 2281 const uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = { 2282 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 2283 }; 2284 2285 // DTriple_with_dsub_0_in_DPR_8 Register Class... 2286 const MCPhysReg DTriple_with_dsub_0_in_DPR_8[] = { 2287 ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, 2288 }; 2289 2290 // DTriple_with_dsub_0_in_DPR_8 Bit set. 2291 const uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = { 2292 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 2293 }; 2294 2295 // DTriple_with_qsub_0_in_MQPR Register Class... 2296 const MCPhysReg DTriple_with_qsub_0_in_MQPR[] = { 2297 ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16, 2298 }; 2299 2300 // DTriple_with_qsub_0_in_MQPR Bit set. 2301 const uint8_t DTriple_with_qsub_0_in_MQPRBits[] = { 2302 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x55, 0x15, 2303 }; 2304 2305 // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... 2306 const MCPhysReg DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { 2307 ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17, 2308 }; 2309 2310 // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. 2311 const uint8_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { 2312 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x2a, 2313 }; 2314 2315 // DTriple_with_dsub_1_in_DPR_8 Register Class... 2316 const MCPhysReg DTriple_with_dsub_1_in_DPR_8[] = { 2317 ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, 2318 }; 2319 2320 // DTriple_with_dsub_1_in_DPR_8 Bit set. 2321 const uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = { 2322 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 2323 }; 2324 2325 // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class... 2326 const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = { 2327 ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, 2328 }; 2329 2330 // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set. 2331 const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = { 2332 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x0a, 2333 }; 2334 2335 // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR Register Class... 2336 const MCPhysReg DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR[] = { 2337 ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, 2338 }; 2339 2340 // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR Bit set. 2341 const uint8_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits[] = { 2342 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x55, 0x05, 2343 }; 2344 2345 // DTripleSpc_with_dsub_2_in_DPR_8 Register Class... 2346 const MCPhysReg DTripleSpc_with_dsub_2_in_DPR_8[] = { 2347 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, 2348 }; 2349 2350 // DTripleSpc_with_dsub_2_in_DPR_8 Bit set. 2351 const uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = { 2352 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03, 2353 }; 2354 2355 // DTriple_with_dsub_2_in_DPR_8 Register Class... 2356 const MCPhysReg DTriple_with_dsub_2_in_DPR_8[] = { 2357 ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, 2358 }; 2359 2360 // DTriple_with_dsub_2_in_DPR_8 Bit set. 2361 const uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = { 2362 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 2363 }; 2364 2365 // DTripleSpc_with_dsub_4_in_DPR_8 Register Class... 2366 const MCPhysReg DTripleSpc_with_dsub_4_in_DPR_8[] = { 2367 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, 2368 }; 2369 2370 // DTripleSpc_with_dsub_4_in_DPR_8 Bit set. 2371 const uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = { 2372 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 2373 }; 2374 2375 // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class... 2376 const MCPhysReg DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = { 2377 ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, 2378 }; 2379 2380 // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set. 2381 const uint8_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = { 2382 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2a, 2383 }; 2384 2385 // DTriple_with_qsub_0_in_QPR_8 Register Class... 2386 const MCPhysReg DTriple_with_qsub_0_in_QPR_8[] = { 2387 ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, 2388 }; 2389 2390 // DTriple_with_qsub_0_in_QPR_8 Bit set. 2391 const uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = { 2392 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x15, 2393 }; 2394 2395 // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR Register Class... 2396 const MCPhysReg DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR[] = { 2397 ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, 2398 }; 2399 2400 // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR Bit set. 2401 const uint8_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRBits[] = { 2402 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 2403 }; 2404 2405 // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class... 2406 const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = { 2407 ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, 2408 }; 2409 2410 // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set. 2411 const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = { 2412 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0a, 2413 }; 2414 2415 // DQuadSpc Register Class... 2416 const MCPhysReg DQuadSpc[] = { 2417 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31, 2418 }; 2419 2420 // DQuadSpc Bit set. 2421 const uint8_t DQuadSpcBits[] = { 2422 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 2423 }; 2424 2425 // DQuadSpc_with_ssub_0 Register Class... 2426 const MCPhysReg DQuadSpc_with_ssub_0[] = { 2427 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, 2428 }; 2429 2430 // DQuadSpc_with_ssub_0 Bit set. 2431 const uint8_t DQuadSpc_with_ssub_0Bits[] = { 2432 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 2433 }; 2434 2435 // DQuadSpc_with_ssub_4 Register Class... 2436 const MCPhysReg DQuadSpc_with_ssub_4[] = { 2437 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, 2438 }; 2439 2440 // DQuadSpc_with_ssub_4 Bit set. 2441 const uint8_t DQuadSpc_with_ssub_4Bits[] = { 2442 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 2443 }; 2444 2445 // DQuadSpc_with_ssub_8 Register Class... 2446 const MCPhysReg DQuadSpc_with_ssub_8[] = { 2447 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, 2448 }; 2449 2450 // DQuadSpc_with_ssub_8 Bit set. 2451 const uint8_t DQuadSpc_with_ssub_8Bits[] = { 2452 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 2453 }; 2454 2455 // DQuadSpc_with_dsub_0_in_DPR_8 Register Class... 2456 const MCPhysReg DQuadSpc_with_dsub_0_in_DPR_8[] = { 2457 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, 2458 }; 2459 2460 // DQuadSpc_with_dsub_0_in_DPR_8 Bit set. 2461 const uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = { 2462 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 2463 }; 2464 2465 // DQuadSpc_with_dsub_2_in_DPR_8 Register Class... 2466 const MCPhysReg DQuadSpc_with_dsub_2_in_DPR_8[] = { 2467 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, 2468 }; 2469 2470 // DQuadSpc_with_dsub_2_in_DPR_8 Bit set. 2471 const uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = { 2472 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03, 2473 }; 2474 2475 // DQuadSpc_with_dsub_4_in_DPR_8 Register Class... 2476 const MCPhysReg DQuadSpc_with_dsub_4_in_DPR_8[] = { 2477 ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, 2478 }; 2479 2480 // DQuadSpc_with_dsub_4_in_DPR_8 Bit set. 2481 const uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = { 2482 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 2483 }; 2484 2485 // DQuad Register Class... 2486 const MCPhysReg DQuad[] = { 2487 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18, ARM::Q8_Q9, ARM::D17_D18_D19_D20, ARM::Q9_Q10, ARM::D19_D20_D21_D22, ARM::Q10_Q11, ARM::D21_D22_D23_D24, ARM::Q11_Q12, ARM::D23_D24_D25_D26, ARM::Q12_Q13, ARM::D25_D26_D27_D28, ARM::Q13_Q14, ARM::D27_D28_D29_D30, ARM::Q14_Q15, 2488 }; 2489 2490 // DQuad Bit set. 2491 const uint8_t DQuadBits[] = { 2492 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f, 2493 }; 2494 2495 // DQuad_with_ssub_0 Register Class... 2496 const MCPhysReg DQuad_with_ssub_0[] = { 2497 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18, 2498 }; 2499 2500 // DQuad_with_ssub_0 Bit set. 2501 const uint8_t DQuad_with_ssub_0Bits[] = { 2502 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 2503 }; 2504 2505 // DQuad_with_ssub_2 Register Class... 2506 const MCPhysReg DQuad_with_ssub_2[] = { 2507 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, 2508 }; 2509 2510 // DQuad_with_ssub_2 Bit set. 2511 const uint8_t DQuad_with_ssub_2Bits[] = { 2512 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 2513 }; 2514 2515 // QQPR Register Class... 2516 const MCPhysReg QQPR[] = { 2517 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8, ARM::Q8_Q9, ARM::Q9_Q10, ARM::Q10_Q11, ARM::Q11_Q12, ARM::Q12_Q13, ARM::Q13_Q14, ARM::Q14_Q15, 2518 }; 2519 2520 // QQPR Bit set. 2521 const uint8_t QQPRBits[] = { 2522 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, 2523 }; 2524 2525 // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... 2526 const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { 2527 ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18, ARM::D17_D18_D19_D20, ARM::D19_D20_D21_D22, ARM::D21_D22_D23_D24, ARM::D23_D24_D25_D26, ARM::D25_D26_D27_D28, ARM::D27_D28_D29_D30, 2528 }; 2529 2530 // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. 2531 const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { 2532 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f, 2533 }; 2534 2535 // DQuad_with_ssub_4 Register Class... 2536 const MCPhysReg DQuad_with_ssub_4[] = { 2537 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, 2538 }; 2539 2540 // DQuad_with_ssub_4 Bit set. 2541 const uint8_t DQuad_with_ssub_4Bits[] = { 2542 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 2543 }; 2544 2545 // DQuad_with_ssub_6 Register Class... 2546 const MCPhysReg DQuad_with_ssub_6[] = { 2547 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, 2548 }; 2549 2550 // DQuad_with_ssub_6 Bit set. 2551 const uint8_t DQuad_with_ssub_6Bits[] = { 2552 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 2553 }; 2554 2555 // DQuad_with_dsub_0_in_DPR_8 Register Class... 2556 const MCPhysReg DQuad_with_dsub_0_in_DPR_8[] = { 2557 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, 2558 }; 2559 2560 // DQuad_with_dsub_0_in_DPR_8 Bit set. 2561 const uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = { 2562 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 2563 }; 2564 2565 // DQuad_with_qsub_0_in_MQPR Register Class... 2566 const MCPhysReg DQuad_with_qsub_0_in_MQPR[] = { 2567 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8, 2568 }; 2569 2570 // DQuad_with_qsub_0_in_MQPR Bit set. 2571 const uint8_t DQuad_with_qsub_0_in_MQPRBits[] = { 2572 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 2573 }; 2574 2575 // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... 2576 const MCPhysReg DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { 2577 ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18, 2578 }; 2579 2580 // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. 2581 const uint8_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { 2582 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 2583 }; 2584 2585 // DQuad_with_dsub_1_in_DPR_8 Register Class... 2586 const MCPhysReg DQuad_with_dsub_1_in_DPR_8[] = { 2587 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, 2588 }; 2589 2590 // DQuad_with_dsub_1_in_DPR_8 Bit set. 2591 const uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = { 2592 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 2593 }; 2594 2595 // DQuad_with_qsub_1_in_MQPR Register Class... 2596 const MCPhysReg DQuad_with_qsub_1_in_MQPR[] = { 2597 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, 2598 }; 2599 2600 // DQuad_with_qsub_1_in_MQPR Bit set. 2601 const uint8_t DQuad_with_qsub_1_in_MQPRBits[] = { 2602 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 2603 }; 2604 2605 // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class... 2606 const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = { 2607 ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, 2608 }; 2609 2610 // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set. 2611 const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = { 2612 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 2613 }; 2614 2615 // DQuad_with_dsub_2_in_DPR_8 Register Class... 2616 const MCPhysReg DQuad_with_dsub_2_in_DPR_8[] = { 2617 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, 2618 }; 2619 2620 // DQuad_with_dsub_2_in_DPR_8 Bit set. 2621 const uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = { 2622 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 2623 }; 2624 2625 // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class... 2626 const MCPhysReg DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = { 2627 ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, 2628 }; 2629 2630 // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set. 2631 const uint8_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = { 2632 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 2633 }; 2634 2635 // DQuad_with_dsub_3_in_DPR_8 Register Class... 2636 const MCPhysReg DQuad_with_dsub_3_in_DPR_8[] = { 2637 ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, 2638 }; 2639 2640 // DQuad_with_dsub_3_in_DPR_8 Bit set. 2641 const uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = { 2642 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 2643 }; 2644 2645 // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class... 2646 const MCPhysReg DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = { 2647 ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, 2648 }; 2649 2650 // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set. 2651 const uint8_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = { 2652 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 2653 }; 2654 2655 // DQuad_with_qsub_0_in_QPR_8 Register Class... 2656 const MCPhysReg DQuad_with_qsub_0_in_QPR_8[] = { 2657 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 2658 }; 2659 2660 // DQuad_with_qsub_0_in_QPR_8 Bit set. 2661 const uint8_t DQuad_with_qsub_0_in_QPR_8Bits[] = { 2662 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 2663 }; 2664 2665 // DQuad_with_qsub_1_in_QPR_8 Register Class... 2666 const MCPhysReg DQuad_with_qsub_1_in_QPR_8[] = { 2667 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, 2668 }; 2669 2670 // DQuad_with_qsub_1_in_QPR_8 Bit set. 2671 const uint8_t DQuad_with_qsub_1_in_QPR_8Bits[] = { 2672 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 2673 }; 2674 2675 // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class... 2676 const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = { 2677 ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, 2678 }; 2679 2680 // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set. 2681 const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = { 2682 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 2683 }; 2684 2685 // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class... 2686 const MCPhysReg DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = { 2687 ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, 2688 }; 2689 2690 // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set. 2691 const uint8_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = { 2692 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 2693 }; 2694 2695 // QQQQPR Register Class... 2696 const MCPhysReg QQQQPR[] = { 2697 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10, ARM::Q8_Q9_Q10_Q11, ARM::Q9_Q10_Q11_Q12, ARM::Q10_Q11_Q12_Q13, ARM::Q11_Q12_Q13_Q14, ARM::Q12_Q13_Q14_Q15, 2698 }; 2699 2700 // QQQQPR Bit set. 2701 const uint8_t QQQQPRBits[] = { 2702 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 2703 }; 2704 2705 // QQQQPR_with_ssub_0 Register Class... 2706 const MCPhysReg QQQQPR_with_ssub_0[] = { 2707 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10, 2708 }; 2709 2710 // QQQQPR_with_ssub_0 Bit set. 2711 const uint8_t QQQQPR_with_ssub_0Bits[] = { 2712 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 2713 }; 2714 2715 // QQQQPR_with_ssub_4 Register Class... 2716 const MCPhysReg QQQQPR_with_ssub_4[] = { 2717 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, 2718 }; 2719 2720 // QQQQPR_with_ssub_4 Bit set. 2721 const uint8_t QQQQPR_with_ssub_4Bits[] = { 2722 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, 2723 }; 2724 2725 // QQQQPR_with_ssub_8 Register Class... 2726 const MCPhysReg QQQQPR_with_ssub_8[] = { 2727 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, 2728 }; 2729 2730 // QQQQPR_with_ssub_8 Bit set. 2731 const uint8_t QQQQPR_with_ssub_8Bits[] = { 2732 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 2733 }; 2734 2735 // QQQQPR_with_ssub_12 Register Class... 2736 const MCPhysReg QQQQPR_with_ssub_12[] = { 2737 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, 2738 }; 2739 2740 // QQQQPR_with_ssub_12 Bit set. 2741 const uint8_t QQQQPR_with_ssub_12Bits[] = { 2742 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 2743 }; 2744 2745 // QQQQPR_with_dsub_0_in_DPR_8 Register Class... 2746 const MCPhysReg QQQQPR_with_dsub_0_in_DPR_8[] = { 2747 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, 2748 }; 2749 2750 // QQQQPR_with_dsub_0_in_DPR_8 Bit set. 2751 const uint8_t QQQQPR_with_dsub_0_in_DPR_8Bits[] = { 2752 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 2753 }; 2754 2755 // QQQQPR_with_dsub_2_in_DPR_8 Register Class... 2756 const MCPhysReg QQQQPR_with_dsub_2_in_DPR_8[] = { 2757 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 2758 }; 2759 2760 // QQQQPR_with_dsub_2_in_DPR_8 Bit set. 2761 const uint8_t QQQQPR_with_dsub_2_in_DPR_8Bits[] = { 2762 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 2763 }; 2764 2765 // QQQQPR_with_dsub_4_in_DPR_8 Register Class... 2766 const MCPhysReg QQQQPR_with_dsub_4_in_DPR_8[] = { 2767 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, 2768 }; 2769 2770 // QQQQPR_with_dsub_4_in_DPR_8 Bit set. 2771 const uint8_t QQQQPR_with_dsub_4_in_DPR_8Bits[] = { 2772 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 2773 }; 2774 2775 // QQQQPR_with_dsub_6_in_DPR_8 Register Class... 2776 const MCPhysReg QQQQPR_with_dsub_6_in_DPR_8[] = { 2777 ARM::Q0_Q1_Q2_Q3, 2778 }; 2779 2780 // QQQQPR_with_dsub_6_in_DPR_8 Bit set. 2781 const uint8_t QQQQPR_with_dsub_6_in_DPR_8Bits[] = { 2782 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 2783 }; 2784 2785} // end anonymous namespace 2786 2787extern const char ARMRegClassStrings[] = { 2788 /* 0 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0, 2789 /* 19 */ 'F', 'P', 'W', 'i', 't', 'h', 'V', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0, 2790 /* 41 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0, 2791 /* 62 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0, 2792 /* 85 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0, 2793 /* 106 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0, 2794 /* 124 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0, 2795 /* 144 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0, 2796 /* 162 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '1', '2', 0, 2797 /* 182 */ 'D', 'P', 'R', '_', 'V', 'F', 'P', '2', 0, 2798 /* 191 */ 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0, 2799 /* 200 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0, 2800 /* 218 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0, 2801 /* 238 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0, 2802 /* 256 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0, 2803 /* 275 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0, 2804 /* 296 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0, 2805 /* 319 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0, 2806 /* 340 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0, 2807 /* 358 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0, 2808 /* 378 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '6', 0, 2809 /* 396 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, 2810 /* 424 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, 2811 /* 454 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, 2812 /* 486 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, 2813 /* 516 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, 2814 /* 543 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, 2815 /* 572 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, 2816 /* 599 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, 2817 /* 626 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, 2818 /* 655 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, 2819 /* 682 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, 2820 /* 710 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, 2821 /* 740 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, 2822 /* 772 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, 2823 /* 802 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, 2824 /* 829 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, 2825 /* 858 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '3', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, 2826 /* 885 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, 2827 /* 913 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, 2828 /* 943 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, 2829 /* 975 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '6', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, 2830 /* 1003 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0, 2831 /* 1030 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0, 2832 /* 1059 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0, 2833 /* 1086 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0, 2834 /* 1134 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0, 2835 /* 1184 */ 'F', 'P', 'W', 'i', 't', 'h', 'V', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'S', 'P', 'R', '_', '8', 0, 2836 /* 1227 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0, 2837 /* 1246 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0, 2838 /* 1267 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0, 2839 /* 1290 */ 'V', 'C', 'C', 'R', 0, 2840 /* 1295 */ 'D', 'P', 'R', 0, 2841 /* 1299 */ 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', 0, 2842 /* 1314 */ 't', 'G', 'P', 'R', 'E', 'v', 'e', 'n', '_', 'a', 'n', 'd', '_', 't', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', 0, 2843 /* 1342 */ 't', 'G', 'P', 'R', 'O', 'd', 'd', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', 0, 2844 /* 1360 */ 't', 'G', 'P', 'R', 'E', 'v', 'e', 'n', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', 0, 2845 /* 1379 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', 0, 2846 /* 1408 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', 0, 2847 /* 1437 */ 'G', 'P', 'R', 'n', 'o', 'p', 'c', '_', 'a', 'n', 'd', '_', 'h', 'G', 'P', 'R', 0, 2848 /* 1454 */ 'G', 'P', 'R', 'w', 'i', 't', 'h', 'A', 'P', 'S', 'R', 'n', 'o', 's', 'p', '_', 'a', 'n', 'd', '_', 'h', 'G', 'P', 'R', 0, 2849 /* 1479 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', 'n', 'o', 's', 'p', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'h', 'G', 'P', 'R', 0, 2850 /* 1523 */ 'r', 'G', 'P', 'R', 0, 2851 /* 1528 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 't', 'G', 'P', 'R', 0, 2852 /* 1556 */ 'H', 'P', 'R', 0, 2853 /* 1560 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'M', 'Q', 'P', 'R', 0, 2854 /* 1586 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'M', 'Q', 'P', 'R', 0, 2855 /* 1638 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'M', 'Q', 'P', 'R', 0, 2856 /* 1699 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'M', 'Q', 'P', 'R', 0, 2857 /* 1725 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '6', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'M', 'Q', 'P', 'R', 0, 2858 /* 1794 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'M', 'Q', 'P', 'R', 0, 2859 /* 1872 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '3', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'M', 'Q', 'P', 'R', 0, 2860 /* 1950 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'M', 'Q', 'P', 'R', 0, 2861 /* 2032 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', 0, 2862 /* 2039 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0, 2863 /* 2066 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0, 2864 /* 2134 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0, 2865 /* 2206 */ 'S', 'P', 'R', 0, 2866 /* 2210 */ 'F', 'P', 'W', 'i', 't', 'h', 'V', 'P', 'R', 0, 2867 /* 2220 */ 'G', 'P', 'R', 'w', 'i', 't', 'h', 'A', 'P', 'S', 'R', 0, 2868 /* 2232 */ 'G', 'P', 'R', 'w', 'i', 't', 'h', 'Z', 'R', 0, 2869 /* 2242 */ 'c', 'l', '_', 'F', 'P', 'S', 'C', 'R', '_', 'N', 'Z', 'C', 'V', 0, 2870 /* 2256 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', 0, 2871 /* 2265 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', 0, 2872 /* 2276 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', 0, 2873 /* 2285 */ 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'G', 'P', 'R', 'w', 'i', 't', 'h', 'p', 'c', 0, 2874 /* 2305 */ 'G', 'P', 'R', 'n', 'o', 'p', 'c', 0, 2875 /* 2313 */ 'D', 'Q', 'u', 'a', 'd', 0, 2876 /* 2319 */ 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'G', 'P', 'R', 'O', 'd', 'd', 0, 2877 /* 2336 */ 't', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'G', 'P', 'R', 'O', 'd', 'd', 0, 2878 /* 2353 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 0, 2879 /* 2361 */ 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'G', 'P', 'R', 'E', 'v', 'e', 'n', 0, 2880 /* 2379 */ 't', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'G', 'P', 'R', 'E', 'v', 'e', 'n', 0, 2881 /* 2397 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'G', 'P', 'R', 's', 'p', 0, 2882 /* 2426 */ 'G', 'P', 'R', 'w', 'i', 't', 'h', 'A', 'P', 'S', 'R', 'n', 'o', 's', 'p', 0, 2883 /* 2442 */ 'G', 'P', 'R', 'w', 'i', 't', 'h', 'Z', 'R', 'n', 'o', 's', 'p', 0, 2884 /* 2456 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', 'n', 'o', 's', 'p', 0, 2885 /* 2468 */ 'D', 'P', 'a', 'i', 'r', 0, 2886 /* 2474 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', 0, 2887 /* 2482 */ 'G', 'P', 'R', 'l', 'r', 0, 2888}; 2889 2890extern const MCRegisterClass ARMMCRegisterClasses[] = { 2891 { HPR, HPRBits, 1556, 32, sizeof(HPRBits), ARM::HPRRegClassID, 1, true }, 2892 { FPWithVPR, FPWithVPRBits, 2210, 65, sizeof(FPWithVPRBits), ARM::FPWithVPRRegClassID, 1, false }, 2893 { SPR, SPRBits, 2206, 32, sizeof(SPRBits), ARM::SPRRegClassID, 1, true }, 2894 { FPWithVPR_with_ssub_0, FPWithVPR_with_ssub_0Bits, 19, 16, sizeof(FPWithVPR_with_ssub_0Bits), ARM::FPWithVPR_with_ssub_0RegClassID, 1, false }, 2895 { GPR, GPRBits, 1310, 16, sizeof(GPRBits), ARM::GPRRegClassID, 1, true }, 2896 { GPRwithAPSR, GPRwithAPSRBits, 2220, 16, sizeof(GPRwithAPSRBits), ARM::GPRwithAPSRRegClassID, 1, true }, 2897 { GPRwithZR, GPRwithZRBits, 2232, 16, sizeof(GPRwithZRBits), ARM::GPRwithZRRegClassID, 1, true }, 2898 { SPR_8, SPR_8Bits, 1221, 16, sizeof(SPR_8Bits), ARM::SPR_8RegClassID, 1, true }, 2899 { GPRnopc, GPRnopcBits, 2305, 15, sizeof(GPRnopcBits), ARM::GPRnopcRegClassID, 1, true }, 2900 { GPRwithAPSRnosp, GPRwithAPSRnospBits, 2426, 15, sizeof(GPRwithAPSRnospBits), ARM::GPRwithAPSRnospRegClassID, 1, false }, 2901 { GPRwithZRnosp, GPRwithZRnospBits, 2442, 15, sizeof(GPRwithZRnospBits), ARM::GPRwithZRnospRegClassID, 1, true }, 2902 { rGPR, rGPRBits, 1523, 14, sizeof(rGPRBits), ARM::rGPRRegClassID, 1, true }, 2903 { tGPRwithpc, tGPRwithpcBits, 2294, 9, sizeof(tGPRwithpcBits), ARM::tGPRwithpcRegClassID, 1, true }, 2904 { FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8, FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits, 1184, 8, sizeof(FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits), ARM::FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID, 1, false }, 2905 { hGPR, hGPRBits, 1449, 8, sizeof(hGPRBits), ARM::hGPRRegClassID, 1, true }, 2906 { tGPR, tGPRBits, 1551, 8, sizeof(tGPRBits), ARM::tGPRRegClassID, 1, true }, 2907 { tGPREven, tGPREvenBits, 2370, 8, sizeof(tGPREvenBits), ARM::tGPREvenRegClassID, 1, true }, 2908 { GPRnopc_and_hGPR, GPRnopc_and_hGPRBits, 1437, 7, sizeof(GPRnopc_and_hGPRBits), ARM::GPRnopc_and_hGPRRegClassID, 1, true }, 2909 { GPRwithAPSRnosp_and_hGPR, GPRwithAPSRnosp_and_hGPRBits, 1454, 6, sizeof(GPRwithAPSRnosp_and_hGPRBits), ARM::GPRwithAPSRnosp_and_hGPRRegClassID, 1, true }, 2910 { tGPROdd, tGPROddBits, 2328, 6, sizeof(tGPROddBits), ARM::tGPROddRegClassID, 1, true }, 2911 { tcGPR, tcGPRBits, 1308, 5, sizeof(tcGPRBits), ARM::tcGPRRegClassID, 1, true }, 2912 { hGPR_and_tGPREven, hGPR_and_tGPREvenBits, 2361, 4, sizeof(hGPR_and_tGPREvenBits), ARM::hGPR_and_tGPREvenRegClassID, 1, true }, 2913 { tGPR_and_tGPREven, tGPR_and_tGPREvenBits, 2379, 4, sizeof(tGPR_and_tGPREvenBits), ARM::tGPR_and_tGPREvenRegClassID, 1, true }, 2914 { tGPR_and_tGPROdd, tGPR_and_tGPROddBits, 2336, 4, sizeof(tGPR_and_tGPROddBits), ARM::tGPR_and_tGPROddRegClassID, 1, true }, 2915 { tGPR_and_tcGPR, tGPR_and_tcGPRBits, 1327, 4, sizeof(tGPR_and_tcGPRBits), ARM::tGPR_and_tcGPRRegClassID, 1, true }, 2916 { tGPREven_and_tcGPR, tGPREven_and_tcGPRBits, 1360, 3, sizeof(tGPREven_and_tcGPRBits), ARM::tGPREven_and_tcGPRRegClassID, 1, true }, 2917 { hGPR_and_tGPROdd, hGPR_and_tGPROddBits, 2319, 2, sizeof(hGPR_and_tGPROddBits), ARM::hGPR_and_tGPROddRegClassID, 1, true }, 2918 { tGPREven_and_tGPR_and_tcGPR, tGPREven_and_tGPR_and_tcGPRBits, 1314, 2, sizeof(tGPREven_and_tGPR_and_tcGPRBits), ARM::tGPREven_and_tGPR_and_tcGPRRegClassID, 1, true }, 2919 { tGPROdd_and_tcGPR, tGPROdd_and_tcGPRBits, 1342, 2, sizeof(tGPROdd_and_tcGPRBits), ARM::tGPROdd_and_tcGPRRegClassID, 1, true }, 2920 { CCR, CCRBits, 1291, 1, sizeof(CCRBits), ARM::CCRRegClassID, -1, false }, 2921 { GPRlr, GPRlrBits, 2482, 1, sizeof(GPRlrBits), ARM::GPRlrRegClassID, 1, true }, 2922 { GPRsp, GPRspBits, 2420, 1, sizeof(GPRspBits), ARM::GPRspRegClassID, 1, true }, 2923 { VCCR, VCCRBits, 1290, 1, sizeof(VCCRBits), ARM::VCCRRegClassID, 1, true }, 2924 { cl_FPSCR_NZCV, cl_FPSCR_NZCVBits, 2242, 1, sizeof(cl_FPSCR_NZCVBits), ARM::cl_FPSCR_NZCVRegClassID, 1, true }, 2925 { hGPR_and_tGPRwithpc, hGPR_and_tGPRwithpcBits, 2285, 1, sizeof(hGPR_and_tGPRwithpcBits), ARM::hGPR_and_tGPRwithpcRegClassID, 1, true }, 2926 { hGPR_and_tcGPR, hGPR_and_tcGPRBits, 1299, 1, sizeof(hGPR_and_tcGPRBits), ARM::hGPR_and_tcGPRRegClassID, 1, true }, 2927 { DPR, DPRBits, 1295, 32, sizeof(DPRBits), ARM::DPRRegClassID, 1, true }, 2928 { DPR_VFP2, DPR_VFP2Bits, 182, 16, sizeof(DPR_VFP2Bits), ARM::DPR_VFP2RegClassID, 1, true }, 2929 { DPR_8, DPR_8Bits, 418, 8, sizeof(DPR_8Bits), ARM::DPR_8RegClassID, 1, true }, 2930 { GPRPair, GPRPairBits, 2474, 7, sizeof(GPRPairBits), ARM::GPRPairRegClassID, 1, true }, 2931 { GPRPairnosp, GPRPairnospBits, 2456, 6, sizeof(GPRPairnospBits), ARM::GPRPairnospRegClassID, 1, true }, 2932 { GPRPair_with_gsub_0_in_tGPR, GPRPair_with_gsub_0_in_tGPRBits, 1528, 4, sizeof(GPRPair_with_gsub_0_in_tGPRBits), ARM::GPRPair_with_gsub_0_in_tGPRRegClassID, 1, true }, 2933 { GPRPair_with_gsub_0_in_hGPR, GPRPair_with_gsub_0_in_hGPRBits, 1495, 3, sizeof(GPRPair_with_gsub_0_in_hGPRBits), ARM::GPRPair_with_gsub_0_in_hGPRRegClassID, 1, true }, 2934 { GPRPair_with_gsub_0_in_tcGPR, GPRPair_with_gsub_0_in_tcGPRBits, 1379, 3, sizeof(GPRPair_with_gsub_0_in_tcGPRBits), ARM::GPRPair_with_gsub_0_in_tcGPRRegClassID, 1, true }, 2935 { GPRPair_with_gsub_1_in_tcGPR, GPRPair_with_gsub_1_in_tcGPRBits, 1408, 2, sizeof(GPRPair_with_gsub_1_in_tcGPRBits), ARM::GPRPair_with_gsub_1_in_tcGPRRegClassID, 1, true }, 2936 { GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR, GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits, 1479, 2, sizeof(GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits), ARM::GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClassID, 1, true }, 2937 { GPRPair_with_gsub_1_in_GPRsp, GPRPair_with_gsub_1_in_GPRspBits, 2397, 1, sizeof(GPRPair_with_gsub_1_in_GPRspBits), ARM::GPRPair_with_gsub_1_in_GPRspRegClassID, 1, true }, 2938 { DPairSpc, DPairSpcBits, 2276, 30, sizeof(DPairSpcBits), ARM::DPairSpcRegClassID, 1, true }, 2939 { DPairSpc_with_ssub_0, DPairSpc_with_ssub_0Bits, 85, 16, sizeof(DPairSpc_with_ssub_0Bits), ARM::DPairSpc_with_ssub_0RegClassID, 1, true }, 2940 { DPairSpc_with_ssub_4, DPairSpc_with_ssub_4Bits, 319, 14, sizeof(DPairSpc_with_ssub_4Bits), ARM::DPairSpc_with_ssub_4RegClassID, 1, true }, 2941 { DPairSpc_with_dsub_0_in_DPR_8, DPairSpc_with_dsub_0_in_DPR_8Bits, 486, 8, sizeof(DPairSpc_with_dsub_0_in_DPR_8Bits), ARM::DPairSpc_with_dsub_0_in_DPR_8RegClassID, 1, true }, 2942 { DPairSpc_with_dsub_2_in_DPR_8, DPairSpc_with_dsub_2_in_DPR_8Bits, 772, 6, sizeof(DPairSpc_with_dsub_2_in_DPR_8Bits), ARM::DPairSpc_with_dsub_2_in_DPR_8RegClassID, 1, true }, 2943 { DPair, DPairBits, 2468, 31, sizeof(DPairBits), ARM::DPairRegClassID, 1, true }, 2944 { DPair_with_ssub_0, DPair_with_ssub_0Bits, 144, 16, sizeof(DPair_with_ssub_0Bits), ARM::DPair_with_ssub_0RegClassID, 1, true }, 2945 { QPR, QPRBits, 1582, 16, sizeof(QPRBits), ARM::QPRRegClassID, 1, true }, 2946 { DPair_with_ssub_2, DPair_with_ssub_2Bits, 238, 15, sizeof(DPair_with_ssub_2Bits), ARM::DPair_with_ssub_2RegClassID, 1, true }, 2947 { DPair_with_dsub_0_in_DPR_8, DPair_with_dsub_0_in_DPR_8Bits, 572, 8, sizeof(DPair_with_dsub_0_in_DPR_8Bits), ARM::DPair_with_dsub_0_in_DPR_8RegClassID, 1, true }, 2948 { MQPR, MQPRBits, 1581, 8, sizeof(MQPRBits), ARM::MQPRRegClassID, 1, true }, 2949 { QPR_VFP2, QPR_VFP2Bits, 191, 8, sizeof(QPR_VFP2Bits), ARM::QPR_VFP2RegClassID, 1, true }, 2950 { DPair_with_dsub_1_in_DPR_8, DPair_with_dsub_1_in_DPR_8Bits, 655, 7, sizeof(DPair_with_dsub_1_in_DPR_8Bits), ARM::DPair_with_dsub_1_in_DPR_8RegClassID, 1, true }, 2951 { QPR_8, QPR_8Bits, 1024, 4, sizeof(QPR_8Bits), ARM::QPR_8RegClassID, 1, true }, 2952 { DTriple, DTripleBits, 2353, 30, sizeof(DTripleBits), ARM::DTripleRegClassID, 1, true }, 2953 { DTripleSpc, DTripleSpcBits, 2265, 28, sizeof(DTripleSpcBits), ARM::DTripleSpcRegClassID, 1, true }, 2954 { DTripleSpc_with_ssub_0, DTripleSpc_with_ssub_0Bits, 62, 16, sizeof(DTripleSpc_with_ssub_0Bits), ARM::DTripleSpc_with_ssub_0RegClassID, 1, true }, 2955 { DTriple_with_ssub_0, DTriple_with_ssub_0Bits, 124, 16, sizeof(DTriple_with_ssub_0Bits), ARM::DTriple_with_ssub_0RegClassID, 1, true }, 2956 { DTriple_with_qsub_0_in_QPR, DTriple_with_qsub_0_in_QPRBits, 2039, 15, sizeof(DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_qsub_0_in_QPRRegClassID, 1, true }, 2957 { DTriple_with_ssub_2, DTriple_with_ssub_2Bits, 218, 15, sizeof(DTriple_with_ssub_2Bits), ARM::DTriple_with_ssub_2RegClassID, 1, true }, 2958 { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2158, 15, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true }, 2959 { DTripleSpc_with_ssub_4, DTripleSpc_with_ssub_4Bits, 296, 14, sizeof(DTripleSpc_with_ssub_4Bits), ARM::DTripleSpc_with_ssub_4RegClassID, 1, true }, 2960 { DTriple_with_ssub_4, DTriple_with_ssub_4Bits, 358, 14, sizeof(DTriple_with_ssub_4Bits), ARM::DTriple_with_ssub_4RegClassID, 1, true }, 2961 { DTripleSpc_with_ssub_8, DTripleSpc_with_ssub_8Bits, 1267, 12, sizeof(DTripleSpc_with_ssub_8Bits), ARM::DTripleSpc_with_ssub_8RegClassID, 1, true }, 2962 { DTripleSpc_with_dsub_0_in_DPR_8, DTripleSpc_with_dsub_0_in_DPR_8Bits, 454, 8, sizeof(DTripleSpc_with_dsub_0_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID, 1, true }, 2963 { DTriple_with_dsub_0_in_DPR_8, DTriple_with_dsub_0_in_DPR_8Bits, 543, 8, sizeof(DTriple_with_dsub_0_in_DPR_8Bits), ARM::DTriple_with_dsub_0_in_DPR_8RegClassID, 1, true }, 2964 { DTriple_with_qsub_0_in_MQPR, DTriple_with_qsub_0_in_MQPRBits, 1610, 8, sizeof(DTriple_with_qsub_0_in_MQPRBits), ARM::DTriple_with_qsub_0_in_MQPRRegClassID, 1, true }, 2965 { DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2134, 8, sizeof(DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true }, 2966 { DTriple_with_dsub_1_in_DPR_8, DTriple_with_dsub_1_in_DPR_8Bits, 626, 7, sizeof(DTriple_with_dsub_1_in_DPR_8Bits), ARM::DTriple_with_dsub_1_in_DPR_8RegClassID, 1, true }, 2967 { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, 1983, 7, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, 1, true }, 2968 { DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR, DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits, 1586, 7, sizeof(DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits), ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClassID, 1, true }, 2969 { DTripleSpc_with_dsub_2_in_DPR_8, DTripleSpc_with_dsub_2_in_DPR_8Bits, 740, 6, sizeof(DTripleSpc_with_dsub_2_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClassID, 1, true }, 2970 { DTriple_with_dsub_2_in_DPR_8, DTriple_with_dsub_2_in_DPR_8Bits, 829, 6, sizeof(DTriple_with_dsub_2_in_DPR_8Bits), ARM::DTriple_with_dsub_2_in_DPR_8RegClassID, 1, true }, 2971 { DTripleSpc_with_dsub_4_in_DPR_8, DTripleSpc_with_dsub_4_in_DPR_8Bits, 943, 4, sizeof(DTripleSpc_with_dsub_4_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClassID, 1, true }, 2972 { DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, 1950, 4, sizeof(DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits), ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, 1, true }, 2973 { DTriple_with_qsub_0_in_QPR_8, DTriple_with_qsub_0_in_QPR_8Bits, 1030, 4, sizeof(DTriple_with_qsub_0_in_QPR_8Bits), ARM::DTriple_with_qsub_0_in_QPR_8RegClassID, 1, true }, 2974 { DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR, DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRBits, 1638, 3, sizeof(DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRBits), ARM::DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRRegClassID, 1, true }, 2975 { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, 1134, 3, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID, 1, true }, 2976 { DQuadSpc, DQuadSpcBits, 2256, 28, sizeof(DQuadSpcBits), ARM::DQuadSpcRegClassID, 1, true }, 2977 { DQuadSpc_with_ssub_0, DQuadSpc_with_ssub_0Bits, 41, 16, sizeof(DQuadSpc_with_ssub_0Bits), ARM::DQuadSpc_with_ssub_0RegClassID, 1, true }, 2978 { DQuadSpc_with_ssub_4, DQuadSpc_with_ssub_4Bits, 275, 14, sizeof(DQuadSpc_with_ssub_4Bits), ARM::DQuadSpc_with_ssub_4RegClassID, 1, true }, 2979 { DQuadSpc_with_ssub_8, DQuadSpc_with_ssub_8Bits, 1246, 12, sizeof(DQuadSpc_with_ssub_8Bits), ARM::DQuadSpc_with_ssub_8RegClassID, 1, true }, 2980 { DQuadSpc_with_dsub_0_in_DPR_8, DQuadSpc_with_dsub_0_in_DPR_8Bits, 424, 8, sizeof(DQuadSpc_with_dsub_0_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClassID, 1, true }, 2981 { DQuadSpc_with_dsub_2_in_DPR_8, DQuadSpc_with_dsub_2_in_DPR_8Bits, 710, 6, sizeof(DQuadSpc_with_dsub_2_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClassID, 1, true }, 2982 { DQuadSpc_with_dsub_4_in_DPR_8, DQuadSpc_with_dsub_4_in_DPR_8Bits, 913, 4, sizeof(DQuadSpc_with_dsub_4_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_4_in_DPR_8RegClassID, 1, true }, 2983 { DQuad, DQuadBits, 2313, 29, sizeof(DQuadBits), ARM::DQuadRegClassID, 1, true }, 2984 { DQuad_with_ssub_0, DQuad_with_ssub_0Bits, 106, 16, sizeof(DQuad_with_ssub_0Bits), ARM::DQuad_with_ssub_0RegClassID, 1, true }, 2985 { DQuad_with_ssub_2, DQuad_with_ssub_2Bits, 200, 15, sizeof(DQuad_with_ssub_2Bits), ARM::DQuad_with_ssub_2RegClassID, 1, true }, 2986 { QQPR, QQPRBits, 2034, 15, sizeof(QQPRBits), ARM::QQPRRegClassID, 1, true }, 2987 { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2088, 14, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true }, 2988 { DQuad_with_ssub_4, DQuad_with_ssub_4Bits, 340, 14, sizeof(DQuad_with_ssub_4Bits), ARM::DQuad_with_ssub_4RegClassID, 1, true }, 2989 { DQuad_with_ssub_6, DQuad_with_ssub_6Bits, 378, 13, sizeof(DQuad_with_ssub_6Bits), ARM::DQuad_with_ssub_6RegClassID, 1, true }, 2990 { DQuad_with_dsub_0_in_DPR_8, DQuad_with_dsub_0_in_DPR_8Bits, 516, 8, sizeof(DQuad_with_dsub_0_in_DPR_8Bits), ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, 1, true }, 2991 { DQuad_with_qsub_0_in_MQPR, DQuad_with_qsub_0_in_MQPRBits, 1560, 8, sizeof(DQuad_with_qsub_0_in_MQPRBits), ARM::DQuad_with_qsub_0_in_MQPRRegClassID, 1, true }, 2992 { DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2066, 8, sizeof(DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true }, 2993 { DQuad_with_dsub_1_in_DPR_8, DQuad_with_dsub_1_in_DPR_8Bits, 599, 7, sizeof(DQuad_with_dsub_1_in_DPR_8Bits), ARM::DQuad_with_dsub_1_in_DPR_8RegClassID, 1, true }, 2994 { DQuad_with_qsub_1_in_MQPR, DQuad_with_qsub_1_in_MQPRBits, 1699, 7, sizeof(DQuad_with_qsub_1_in_MQPRBits), ARM::DQuad_with_qsub_1_in_MQPRRegClassID, 1, true }, 2995 { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, 1747, 7, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, 1, true }, 2996 { DQuad_with_dsub_2_in_DPR_8, DQuad_with_dsub_2_in_DPR_8Bits, 802, 6, sizeof(DQuad_with_dsub_2_in_DPR_8Bits), ARM::DQuad_with_dsub_2_in_DPR_8RegClassID, 1, true }, 2997 { DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, 1725, 6, sizeof(DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits), ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, 1, true }, 2998 { DQuad_with_dsub_3_in_DPR_8, DQuad_with_dsub_3_in_DPR_8Bits, 858, 5, sizeof(DQuad_with_dsub_3_in_DPR_8Bits), ARM::DQuad_with_dsub_3_in_DPR_8RegClassID, 1, true }, 2999 { DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, 1794, 4, sizeof(DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits), ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, 1, true }, 3000 { DQuad_with_qsub_0_in_QPR_8, DQuad_with_qsub_0_in_QPR_8Bits, 1003, 4, sizeof(DQuad_with_qsub_0_in_QPR_8Bits), ARM::DQuad_with_qsub_0_in_QPR_8RegClassID, 1, true }, 3001 { DQuad_with_qsub_1_in_QPR_8, DQuad_with_qsub_1_in_QPR_8Bits, 1059, 3, sizeof(DQuad_with_qsub_1_in_QPR_8Bits), ARM::DQuad_with_qsub_1_in_QPR_8RegClassID, 1, true }, 3002 { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, 1086, 3, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID, 1, true }, 3003 { DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, 1872, 2, sizeof(DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits), ARM::DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, 1, true }, 3004 { QQQQPR, QQQQPRBits, 2032, 13, sizeof(QQQQPRBits), ARM::QQQQPRRegClassID, 1, true }, 3005 { QQQQPR_with_ssub_0, QQQQPR_with_ssub_0Bits, 0, 8, sizeof(QQQQPR_with_ssub_0Bits), ARM::QQQQPR_with_ssub_0RegClassID, 1, true }, 3006 { QQQQPR_with_ssub_4, QQQQPR_with_ssub_4Bits, 256, 7, sizeof(QQQQPR_with_ssub_4Bits), ARM::QQQQPR_with_ssub_4RegClassID, 1, true }, 3007 { QQQQPR_with_ssub_8, QQQQPR_with_ssub_8Bits, 1227, 6, sizeof(QQQQPR_with_ssub_8Bits), ARM::QQQQPR_with_ssub_8RegClassID, 1, true }, 3008 { QQQQPR_with_ssub_12, QQQQPR_with_ssub_12Bits, 162, 5, sizeof(QQQQPR_with_ssub_12Bits), ARM::QQQQPR_with_ssub_12RegClassID, 1, true }, 3009 { QQQQPR_with_dsub_0_in_DPR_8, QQQQPR_with_dsub_0_in_DPR_8Bits, 396, 4, sizeof(QQQQPR_with_dsub_0_in_DPR_8Bits), ARM::QQQQPR_with_dsub_0_in_DPR_8RegClassID, 1, true }, 3010 { QQQQPR_with_dsub_2_in_DPR_8, QQQQPR_with_dsub_2_in_DPR_8Bits, 682, 3, sizeof(QQQQPR_with_dsub_2_in_DPR_8Bits), ARM::QQQQPR_with_dsub_2_in_DPR_8RegClassID, 1, true }, 3011 { QQQQPR_with_dsub_4_in_DPR_8, QQQQPR_with_dsub_4_in_DPR_8Bits, 885, 2, sizeof(QQQQPR_with_dsub_4_in_DPR_8Bits), ARM::QQQQPR_with_dsub_4_in_DPR_8RegClassID, 1, true }, 3012 { QQQQPR_with_dsub_6_in_DPR_8, QQQQPR_with_dsub_6_in_DPR_8Bits, 975, 1, sizeof(QQQQPR_with_dsub_6_in_DPR_8Bits), ARM::QQQQPR_with_dsub_6_in_DPR_8RegClassID, 1, true }, 3013}; 3014 3015// ARM Dwarf<->LLVM register mappings. 3016extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0Dwarf2L[] = { 3017 { 0U, ARM::R0 }, 3018 { 1U, ARM::R1 }, 3019 { 2U, ARM::R2 }, 3020 { 3U, ARM::R3 }, 3021 { 4U, ARM::R4 }, 3022 { 5U, ARM::R5 }, 3023 { 6U, ARM::R6 }, 3024 { 7U, ARM::R7 }, 3025 { 8U, ARM::R8 }, 3026 { 9U, ARM::R9 }, 3027 { 10U, ARM::R10 }, 3028 { 11U, ARM::R11 }, 3029 { 12U, ARM::R12 }, 3030 { 13U, ARM::SP }, 3031 { 14U, ARM::LR }, 3032 { 15U, ARM::ZR }, 3033 { 256U, ARM::D0 }, 3034 { 257U, ARM::D1 }, 3035 { 258U, ARM::D2 }, 3036 { 259U, ARM::D3 }, 3037 { 260U, ARM::D4 }, 3038 { 261U, ARM::D5 }, 3039 { 262U, ARM::D6 }, 3040 { 263U, ARM::D7 }, 3041 { 264U, ARM::D8 }, 3042 { 265U, ARM::D9 }, 3043 { 266U, ARM::D10 }, 3044 { 267U, ARM::D11 }, 3045 { 268U, ARM::D12 }, 3046 { 269U, ARM::D13 }, 3047 { 270U, ARM::D14 }, 3048 { 271U, ARM::D15 }, 3049 { 272U, ARM::D16 }, 3050 { 273U, ARM::D17 }, 3051 { 274U, ARM::D18 }, 3052 { 275U, ARM::D19 }, 3053 { 276U, ARM::D20 }, 3054 { 277U, ARM::D21 }, 3055 { 278U, ARM::D22 }, 3056 { 279U, ARM::D23 }, 3057 { 280U, ARM::D24 }, 3058 { 281U, ARM::D25 }, 3059 { 282U, ARM::D26 }, 3060 { 283U, ARM::D27 }, 3061 { 284U, ARM::D28 }, 3062 { 285U, ARM::D29 }, 3063 { 286U, ARM::D30 }, 3064 { 287U, ARM::D31 }, 3065}; 3066extern const unsigned ARMDwarfFlavour0Dwarf2LSize = array_lengthof(ARMDwarfFlavour0Dwarf2L); 3067 3068extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0Dwarf2L[] = { 3069 { 0U, ARM::R0 }, 3070 { 1U, ARM::R1 }, 3071 { 2U, ARM::R2 }, 3072 { 3U, ARM::R3 }, 3073 { 4U, ARM::R4 }, 3074 { 5U, ARM::R5 }, 3075 { 6U, ARM::R6 }, 3076 { 7U, ARM::R7 }, 3077 { 8U, ARM::R8 }, 3078 { 9U, ARM::R9 }, 3079 { 10U, ARM::R10 }, 3080 { 11U, ARM::R11 }, 3081 { 12U, ARM::R12 }, 3082 { 13U, ARM::SP }, 3083 { 14U, ARM::LR }, 3084 { 15U, ARM::ZR }, 3085 { 256U, ARM::D0 }, 3086 { 257U, ARM::D1 }, 3087 { 258U, ARM::D2 }, 3088 { 259U, ARM::D3 }, 3089 { 260U, ARM::D4 }, 3090 { 261U, ARM::D5 }, 3091 { 262U, ARM::D6 }, 3092 { 263U, ARM::D7 }, 3093 { 264U, ARM::D8 }, 3094 { 265U, ARM::D9 }, 3095 { 266U, ARM::D10 }, 3096 { 267U, ARM::D11 }, 3097 { 268U, ARM::D12 }, 3098 { 269U, ARM::D13 }, 3099 { 270U, ARM::D14 }, 3100 { 271U, ARM::D15 }, 3101 { 272U, ARM::D16 }, 3102 { 273U, ARM::D17 }, 3103 { 274U, ARM::D18 }, 3104 { 275U, ARM::D19 }, 3105 { 276U, ARM::D20 }, 3106 { 277U, ARM::D21 }, 3107 { 278U, ARM::D22 }, 3108 { 279U, ARM::D23 }, 3109 { 280U, ARM::D24 }, 3110 { 281U, ARM::D25 }, 3111 { 282U, ARM::D26 }, 3112 { 283U, ARM::D27 }, 3113 { 284U, ARM::D28 }, 3114 { 285U, ARM::D29 }, 3115 { 286U, ARM::D30 }, 3116 { 287U, ARM::D31 }, 3117}; 3118extern const unsigned ARMEHFlavour0Dwarf2LSize = array_lengthof(ARMEHFlavour0Dwarf2L); 3119 3120extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0L2Dwarf[] = { 3121 { ARM::LR, 14U }, 3122 { ARM::PC, 15U }, 3123 { ARM::SP, 13U }, 3124 { ARM::ZR, 15U }, 3125 { ARM::D0, 256U }, 3126 { ARM::D1, 257U }, 3127 { ARM::D2, 258U }, 3128 { ARM::D3, 259U }, 3129 { ARM::D4, 260U }, 3130 { ARM::D5, 261U }, 3131 { ARM::D6, 262U }, 3132 { ARM::D7, 263U }, 3133 { ARM::D8, 264U }, 3134 { ARM::D9, 265U }, 3135 { ARM::D10, 266U }, 3136 { ARM::D11, 267U }, 3137 { ARM::D12, 268U }, 3138 { ARM::D13, 269U }, 3139 { ARM::D14, 270U }, 3140 { ARM::D15, 271U }, 3141 { ARM::D16, 272U }, 3142 { ARM::D17, 273U }, 3143 { ARM::D18, 274U }, 3144 { ARM::D19, 275U }, 3145 { ARM::D20, 276U }, 3146 { ARM::D21, 277U }, 3147 { ARM::D22, 278U }, 3148 { ARM::D23, 279U }, 3149 { ARM::D24, 280U }, 3150 { ARM::D25, 281U }, 3151 { ARM::D26, 282U }, 3152 { ARM::D27, 283U }, 3153 { ARM::D28, 284U }, 3154 { ARM::D29, 285U }, 3155 { ARM::D30, 286U }, 3156 { ARM::D31, 287U }, 3157 { ARM::R0, 0U }, 3158 { ARM::R1, 1U }, 3159 { ARM::R2, 2U }, 3160 { ARM::R3, 3U }, 3161 { ARM::R4, 4U }, 3162 { ARM::R5, 5U }, 3163 { ARM::R6, 6U }, 3164 { ARM::R7, 7U }, 3165 { ARM::R8, 8U }, 3166 { ARM::R9, 9U }, 3167 { ARM::R10, 10U }, 3168 { ARM::R11, 11U }, 3169 { ARM::R12, 12U }, 3170}; 3171extern const unsigned ARMDwarfFlavour0L2DwarfSize = array_lengthof(ARMDwarfFlavour0L2Dwarf); 3172 3173extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0L2Dwarf[] = { 3174 { ARM::LR, 14U }, 3175 { ARM::PC, 15U }, 3176 { ARM::SP, 13U }, 3177 { ARM::ZR, 15U }, 3178 { ARM::D0, 256U }, 3179 { ARM::D1, 257U }, 3180 { ARM::D2, 258U }, 3181 { ARM::D3, 259U }, 3182 { ARM::D4, 260U }, 3183 { ARM::D5, 261U }, 3184 { ARM::D6, 262U }, 3185 { ARM::D7, 263U }, 3186 { ARM::D8, 264U }, 3187 { ARM::D9, 265U }, 3188 { ARM::D10, 266U }, 3189 { ARM::D11, 267U }, 3190 { ARM::D12, 268U }, 3191 { ARM::D13, 269U }, 3192 { ARM::D14, 270U }, 3193 { ARM::D15, 271U }, 3194 { ARM::D16, 272U }, 3195 { ARM::D17, 273U }, 3196 { ARM::D18, 274U }, 3197 { ARM::D19, 275U }, 3198 { ARM::D20, 276U }, 3199 { ARM::D21, 277U }, 3200 { ARM::D22, 278U }, 3201 { ARM::D23, 279U }, 3202 { ARM::D24, 280U }, 3203 { ARM::D25, 281U }, 3204 { ARM::D26, 282U }, 3205 { ARM::D27, 283U }, 3206 { ARM::D28, 284U }, 3207 { ARM::D29, 285U }, 3208 { ARM::D30, 286U }, 3209 { ARM::D31, 287U }, 3210 { ARM::R0, 0U }, 3211 { ARM::R1, 1U }, 3212 { ARM::R2, 2U }, 3213 { ARM::R3, 3U }, 3214 { ARM::R4, 4U }, 3215 { ARM::R5, 5U }, 3216 { ARM::R6, 6U }, 3217 { ARM::R7, 7U }, 3218 { ARM::R8, 8U }, 3219 { ARM::R9, 9U }, 3220 { ARM::R10, 10U }, 3221 { ARM::R11, 11U }, 3222 { ARM::R12, 12U }, 3223}; 3224extern const unsigned ARMEHFlavour0L2DwarfSize = array_lengthof(ARMEHFlavour0L2Dwarf); 3225 3226extern const uint16_t ARMRegEncodingTable[] = { 3227 0, 3228 15, 3229 15, 3230 0, 3231 14, 3232 15, 3233 8, 3234 9, 3235 3, 3236 3, 3237 2, 3238 0, 3239 4, 3240 14, 3241 15, 3242 13, 3243 2, 3244 32, 3245 15, 3246 0, 3247 1, 3248 2, 3249 3, 3250 4, 3251 5, 3252 6, 3253 7, 3254 8, 3255 9, 3256 10, 3257 11, 3258 12, 3259 13, 3260 14, 3261 15, 3262 16, 3263 17, 3264 18, 3265 19, 3266 20, 3267 21, 3268 22, 3269 23, 3270 24, 3271 25, 3272 26, 3273 27, 3274 28, 3275 29, 3276 30, 3277 31, 3278 10, 3279 7, 3280 6, 3281 5, 3282 13, 3283 0, 3284 1, 3285 2, 3286 3, 3287 4, 3288 5, 3289 6, 3290 7, 3291 8, 3292 9, 3293 10, 3294 11, 3295 12, 3296 13, 3297 14, 3298 15, 3299 0, 3300 1, 3301 2, 3302 3, 3303 4, 3304 5, 3305 6, 3306 7, 3307 8, 3308 9, 3309 10, 3310 11, 3311 12, 3312 0, 3313 1, 3314 2, 3315 3, 3316 4, 3317 5, 3318 6, 3319 7, 3320 8, 3321 9, 3322 10, 3323 11, 3324 12, 3325 13, 3326 14, 3327 15, 3328 16, 3329 17, 3330 18, 3331 19, 3332 20, 3333 21, 3334 22, 3335 23, 3336 24, 3337 25, 3338 26, 3339 27, 3340 28, 3341 29, 3342 30, 3343 31, 3344 0, 3345 1, 3346 2, 3347 3, 3348 4, 3349 5, 3350 6, 3351 7, 3352 8, 3353 9, 3354 10, 3355 11, 3356 12, 3357 13, 3358 14, 3359 15, 3360 16, 3361 17, 3362 18, 3363 19, 3364 20, 3365 21, 3366 22, 3367 23, 3368 24, 3369 25, 3370 26, 3371 27, 3372 28, 3373 29, 3374 0, 3375 1, 3376 2, 3377 3, 3378 4, 3379 5, 3380 6, 3381 7, 3382 8, 3383 9, 3384 10, 3385 11, 3386 12, 3387 13, 3388 14, 3389 0, 3390 1, 3391 2, 3392 3, 3393 4, 3394 5, 3395 6, 3396 7, 3397 8, 3398 9, 3399 10, 3400 11, 3401 12, 3402 0, 3403 2, 3404 4, 3405 6, 3406 8, 3407 10, 3408 12, 3409 0, 3410 1, 3411 2, 3412 3, 3413 4, 3414 5, 3415 6, 3416 7, 3417 8, 3418 9, 3419 10, 3420 11, 3421 12, 3422 13, 3423 14, 3424 15, 3425 16, 3426 17, 3427 18, 3428 19, 3429 20, 3430 21, 3431 22, 3432 23, 3433 24, 3434 25, 3435 26, 3436 27, 3437 28, 3438 29, 3439 0, 3440 1, 3441 2, 3442 3, 3443 4, 3444 5, 3445 6, 3446 7, 3447 8, 3448 9, 3449 10, 3450 11, 3451 12, 3452 13, 3453 14, 3454 15, 3455 16, 3456 17, 3457 18, 3458 19, 3459 20, 3460 21, 3461 22, 3462 23, 3463 24, 3464 25, 3465 26, 3466 27, 3467 0, 3468 1, 3469 2, 3470 3, 3471 4, 3472 5, 3473 6, 3474 7, 3475 8, 3476 9, 3477 10, 3478 11, 3479 12, 3480 13, 3481 14, 3482 15, 3483 16, 3484 17, 3485 18, 3486 19, 3487 20, 3488 21, 3489 22, 3490 23, 3491 24, 3492 25, 3493 1, 3494 3, 3495 5, 3496 7, 3497 9, 3498 11, 3499 13, 3500 15, 3501 17, 3502 19, 3503 21, 3504 23, 3505 25, 3506 27, 3507 29, 3508 1, 3509 3, 3510 5, 3511 7, 3512 9, 3513 11, 3514 13, 3515 15, 3516 17, 3517 19, 3518 21, 3519 23, 3520 25, 3521 27, 3522}; 3523static inline void InitARMMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) { 3524 RI->InitMCRegisterInfo(ARMRegDesc, 295, RA, PC, ARMMCRegisterClasses, 122, ARMRegUnitRoots, 83, ARMRegDiffLists, ARMLaneMaskLists, ARMRegStrings, ARMRegClassStrings, ARMSubRegIdxLists, 57, 3525ARMSubRegIdxRanges, ARMRegEncodingTable); 3526 3527 switch (DwarfFlavour) { 3528 default: 3529 llvm_unreachable("Unknown DWARF flavour"); 3530 case 0: 3531 RI->mapDwarfRegsToLLVMRegs(ARMDwarfFlavour0Dwarf2L, ARMDwarfFlavour0Dwarf2LSize, false); 3532 break; 3533 } 3534 switch (EHFlavour) { 3535 default: 3536 llvm_unreachable("Unknown DWARF flavour"); 3537 case 0: 3538 RI->mapDwarfRegsToLLVMRegs(ARMEHFlavour0Dwarf2L, ARMEHFlavour0Dwarf2LSize, true); 3539 break; 3540 } 3541 switch (DwarfFlavour) { 3542 default: 3543 llvm_unreachable("Unknown DWARF flavour"); 3544 case 0: 3545 RI->mapLLVMRegsToDwarfRegs(ARMDwarfFlavour0L2Dwarf, ARMDwarfFlavour0L2DwarfSize, false); 3546 break; 3547 } 3548 switch (EHFlavour) { 3549 default: 3550 llvm_unreachable("Unknown DWARF flavour"); 3551 case 0: 3552 RI->mapLLVMRegsToDwarfRegs(ARMEHFlavour0L2Dwarf, ARMEHFlavour0L2DwarfSize, true); 3553 break; 3554 } 3555} 3556 3557} // end namespace llvm 3558 3559#endif // GET_REGINFO_MC_DESC 3560 3561/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 3562|* *| 3563|* Register Information Header Fragment *| 3564|* *| 3565|* Automatically generated file, do not edit! *| 3566|* *| 3567\*===----------------------------------------------------------------------===*/ 3568 3569 3570#ifdef GET_REGINFO_HEADER 3571#undef GET_REGINFO_HEADER 3572 3573#include "llvm/CodeGen/TargetRegisterInfo.h" 3574 3575namespace llvm { 3576 3577class ARMFrameLowering; 3578 3579struct ARMGenRegisterInfo : public TargetRegisterInfo { 3580 explicit ARMGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0, 3581 unsigned PC = 0, unsigned HwMode = 0); 3582 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override; 3583 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; 3584 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; 3585 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override; 3586 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override; 3587 unsigned getRegUnitWeight(unsigned RegUnit) const override; 3588 unsigned getNumRegPressureSets() const override; 3589 const char *getRegPressureSetName(unsigned Idx) const override; 3590 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override; 3591 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override; 3592 const int *getRegUnitPressureSets(unsigned RegUnit) const override; 3593 ArrayRef<const char *> getRegMaskNames() const override; 3594 ArrayRef<const uint32_t *> getRegMasks() const override; 3595 /// Devirtualized TargetFrameLowering. 3596 static const ARMFrameLowering *getFrameLowering( 3597 const MachineFunction &MF); 3598}; 3599 3600namespace ARM { // Register classes 3601 extern const TargetRegisterClass HPRRegClass; 3602 extern const TargetRegisterClass FPWithVPRRegClass; 3603 extern const TargetRegisterClass SPRRegClass; 3604 extern const TargetRegisterClass FPWithVPR_with_ssub_0RegClass; 3605 extern const TargetRegisterClass GPRRegClass; 3606 extern const TargetRegisterClass GPRwithAPSRRegClass; 3607 extern const TargetRegisterClass GPRwithZRRegClass; 3608 extern const TargetRegisterClass SPR_8RegClass; 3609 extern const TargetRegisterClass GPRnopcRegClass; 3610 extern const TargetRegisterClass GPRwithAPSRnospRegClass; 3611 extern const TargetRegisterClass GPRwithZRnospRegClass; 3612 extern const TargetRegisterClass rGPRRegClass; 3613 extern const TargetRegisterClass tGPRwithpcRegClass; 3614 extern const TargetRegisterClass FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClass; 3615 extern const TargetRegisterClass hGPRRegClass; 3616 extern const TargetRegisterClass tGPRRegClass; 3617 extern const TargetRegisterClass tGPREvenRegClass; 3618 extern const TargetRegisterClass GPRnopc_and_hGPRRegClass; 3619 extern const TargetRegisterClass GPRwithAPSRnosp_and_hGPRRegClass; 3620 extern const TargetRegisterClass tGPROddRegClass; 3621 extern const TargetRegisterClass tcGPRRegClass; 3622 extern const TargetRegisterClass hGPR_and_tGPREvenRegClass; 3623 extern const TargetRegisterClass tGPR_and_tGPREvenRegClass; 3624 extern const TargetRegisterClass tGPR_and_tGPROddRegClass; 3625 extern const TargetRegisterClass tGPR_and_tcGPRRegClass; 3626 extern const TargetRegisterClass tGPREven_and_tcGPRRegClass; 3627 extern const TargetRegisterClass hGPR_and_tGPROddRegClass; 3628 extern const TargetRegisterClass tGPREven_and_tGPR_and_tcGPRRegClass; 3629 extern const TargetRegisterClass tGPROdd_and_tcGPRRegClass; 3630 extern const TargetRegisterClass CCRRegClass; 3631 extern const TargetRegisterClass GPRlrRegClass; 3632 extern const TargetRegisterClass GPRspRegClass; 3633 extern const TargetRegisterClass VCCRRegClass; 3634 extern const TargetRegisterClass cl_FPSCR_NZCVRegClass; 3635 extern const TargetRegisterClass hGPR_and_tGPRwithpcRegClass; 3636 extern const TargetRegisterClass hGPR_and_tcGPRRegClass; 3637 extern const TargetRegisterClass DPRRegClass; 3638 extern const TargetRegisterClass DPR_VFP2RegClass; 3639 extern const TargetRegisterClass DPR_8RegClass; 3640 extern const TargetRegisterClass GPRPairRegClass; 3641 extern const TargetRegisterClass GPRPairnospRegClass; 3642 extern const TargetRegisterClass GPRPair_with_gsub_0_in_tGPRRegClass; 3643 extern const TargetRegisterClass GPRPair_with_gsub_0_in_hGPRRegClass; 3644 extern const TargetRegisterClass GPRPair_with_gsub_0_in_tcGPRRegClass; 3645 extern const TargetRegisterClass GPRPair_with_gsub_1_in_tcGPRRegClass; 3646 extern const TargetRegisterClass GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClass; 3647 extern const TargetRegisterClass GPRPair_with_gsub_1_in_GPRspRegClass; 3648 extern const TargetRegisterClass DPairSpcRegClass; 3649 extern const TargetRegisterClass DPairSpc_with_ssub_0RegClass; 3650 extern const TargetRegisterClass DPairSpc_with_ssub_4RegClass; 3651 extern const TargetRegisterClass DPairSpc_with_dsub_0_in_DPR_8RegClass; 3652 extern const TargetRegisterClass DPairSpc_with_dsub_2_in_DPR_8RegClass; 3653 extern const TargetRegisterClass DPairRegClass; 3654 extern const TargetRegisterClass DPair_with_ssub_0RegClass; 3655 extern const TargetRegisterClass QPRRegClass; 3656 extern const TargetRegisterClass DPair_with_ssub_2RegClass; 3657 extern const TargetRegisterClass DPair_with_dsub_0_in_DPR_8RegClass; 3658 extern const TargetRegisterClass MQPRRegClass; 3659 extern const TargetRegisterClass QPR_VFP2RegClass; 3660 extern const TargetRegisterClass DPair_with_dsub_1_in_DPR_8RegClass; 3661 extern const TargetRegisterClass QPR_8RegClass; 3662 extern const TargetRegisterClass DTripleRegClass; 3663 extern const TargetRegisterClass DTripleSpcRegClass; 3664 extern const TargetRegisterClass DTripleSpc_with_ssub_0RegClass; 3665 extern const TargetRegisterClass DTriple_with_ssub_0RegClass; 3666 extern const TargetRegisterClass DTriple_with_qsub_0_in_QPRRegClass; 3667 extern const TargetRegisterClass DTriple_with_ssub_2RegClass; 3668 extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass; 3669 extern const TargetRegisterClass DTripleSpc_with_ssub_4RegClass; 3670 extern const TargetRegisterClass DTriple_with_ssub_4RegClass; 3671 extern const TargetRegisterClass DTripleSpc_with_ssub_8RegClass; 3672 extern const TargetRegisterClass DTripleSpc_with_dsub_0_in_DPR_8RegClass; 3673 extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8RegClass; 3674 extern const TargetRegisterClass DTriple_with_qsub_0_in_MQPRRegClass; 3675 extern const TargetRegisterClass DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass; 3676 extern const TargetRegisterClass DTriple_with_dsub_1_in_DPR_8RegClass; 3677 extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass; 3678 extern const TargetRegisterClass DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClass; 3679 extern const TargetRegisterClass DTripleSpc_with_dsub_2_in_DPR_8RegClass; 3680 extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8RegClass; 3681 extern const TargetRegisterClass DTripleSpc_with_dsub_4_in_DPR_8RegClass; 3682 extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass; 3683 extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_8RegClass; 3684 extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRRegClass; 3685 extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass; 3686 extern const TargetRegisterClass DQuadSpcRegClass; 3687 extern const TargetRegisterClass DQuadSpc_with_ssub_0RegClass; 3688 extern const TargetRegisterClass DQuadSpc_with_ssub_4RegClass; 3689 extern const TargetRegisterClass DQuadSpc_with_ssub_8RegClass; 3690 extern const TargetRegisterClass DQuadSpc_with_dsub_0_in_DPR_8RegClass; 3691 extern const TargetRegisterClass DQuadSpc_with_dsub_2_in_DPR_8RegClass; 3692 extern const TargetRegisterClass DQuadSpc_with_dsub_4_in_DPR_8RegClass; 3693 extern const TargetRegisterClass DQuadRegClass; 3694 extern const TargetRegisterClass DQuad_with_ssub_0RegClass; 3695 extern const TargetRegisterClass DQuad_with_ssub_2RegClass; 3696 extern const TargetRegisterClass QQPRRegClass; 3697 extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass; 3698 extern const TargetRegisterClass DQuad_with_ssub_4RegClass; 3699 extern const TargetRegisterClass DQuad_with_ssub_6RegClass; 3700 extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8RegClass; 3701 extern const TargetRegisterClass DQuad_with_qsub_0_in_MQPRRegClass; 3702 extern const TargetRegisterClass DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass; 3703 extern const TargetRegisterClass DQuad_with_dsub_1_in_DPR_8RegClass; 3704 extern const TargetRegisterClass DQuad_with_qsub_1_in_MQPRRegClass; 3705 extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass; 3706 extern const TargetRegisterClass DQuad_with_dsub_2_in_DPR_8RegClass; 3707 extern const TargetRegisterClass DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass; 3708 extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8RegClass; 3709 extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass; 3710 extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_8RegClass; 3711 extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_8RegClass; 3712 extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass; 3713 extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass; 3714 extern const TargetRegisterClass QQQQPRRegClass; 3715 extern const TargetRegisterClass QQQQPR_with_ssub_0RegClass; 3716 extern const TargetRegisterClass QQQQPR_with_ssub_4RegClass; 3717 extern const TargetRegisterClass QQQQPR_with_ssub_8RegClass; 3718 extern const TargetRegisterClass QQQQPR_with_ssub_12RegClass; 3719 extern const TargetRegisterClass QQQQPR_with_dsub_0_in_DPR_8RegClass; 3720 extern const TargetRegisterClass QQQQPR_with_dsub_2_in_DPR_8RegClass; 3721 extern const TargetRegisterClass QQQQPR_with_dsub_4_in_DPR_8RegClass; 3722 extern const TargetRegisterClass QQQQPR_with_dsub_6_in_DPR_8RegClass; 3723} // end namespace ARM 3724 3725} // end namespace llvm 3726 3727#endif // GET_REGINFO_HEADER 3728 3729/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 3730|* *| 3731|* Target Register and Register Classes Information *| 3732|* *| 3733|* Automatically generated file, do not edit! *| 3734|* *| 3735\*===----------------------------------------------------------------------===*/ 3736 3737 3738#ifdef GET_REGINFO_TARGET_DESC 3739#undef GET_REGINFO_TARGET_DESC 3740 3741namespace llvm { 3742 3743extern const MCRegisterClass ARMMCRegisterClasses[]; 3744 3745static const MVT::SimpleValueType VTLists[] = { 3746 /* 0 */ MVT::i32, MVT::Other, 3747 /* 2 */ MVT::f16, MVT::Other, 3748 /* 4 */ MVT::f32, MVT::Other, 3749 /* 6 */ MVT::i32, MVT::v16i1, MVT::v8i1, MVT::v4i1, MVT::Other, 3750 /* 11 */ MVT::v2i64, MVT::Other, 3751 /* 13 */ MVT::v4i64, MVT::Other, 3752 /* 15 */ MVT::v8i64, MVT::Other, 3753 /* 17 */ MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64, MVT::v2f32, MVT::v4f16, MVT::Other, 3754 /* 25 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::Other, 3755 /* 33 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::Other, 3756 /* 40 */ MVT::Untyped, MVT::Other, 3757}; 3758 3759static const char *const SubRegIndexNameTable[] = { "dsub_0", "dsub_1", "dsub_2", "dsub_3", "dsub_4", "dsub_5", "dsub_6", "dsub_7", "gsub_0", "gsub_1", "qqsub_0", "qqsub_1", "qsub_0", "qsub_1", "qsub_2", "qsub_3", "ssub_0", "ssub_1", "ssub_2", "ssub_3", "ssub_4", "ssub_5", "ssub_6", "ssub_7", "ssub_8", "ssub_9", "ssub_10", "ssub_11", "ssub_12", "ssub_13", "dsub_7_then_ssub_0", "dsub_7_then_ssub_1", "ssub_0_ssub_1_ssub_4_ssub_5", "ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5", "ssub_2_ssub_3_ssub_6_ssub_7", "ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7", "ssub_2_ssub_3_ssub_4_ssub_5", "ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9", "ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13", "ssub_2_ssub_3_ssub_6_ssub_7_dsub_5", "ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7", "ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13", "ssub_6_ssub_7_dsub_5", "ssub_6_ssub_7_ssub_8_ssub_9_dsub_5", "ssub_6_ssub_7_dsub_5_dsub_7", "ssub_6_ssub_7_ssub_8_ssub_9", "ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13", "ssub_8_ssub_9_ssub_12_ssub_13", "ssub_8_ssub_9_dsub_5_ssub_12_ssub_13", "dsub_5_dsub_7", "dsub_5_ssub_12_ssub_13_dsub_7", "dsub_5_ssub_12_ssub_13", "ssub_4_ssub_5_ssub_6_ssub_7_qsub_2", "" }; 3760 3761 3762static const LaneBitmask SubRegIndexLaneMaskTable[] = { 3763 LaneBitmask::getAll(), 3764 LaneBitmask(0x0000000C), // dsub_0 3765 LaneBitmask(0x00000030), // dsub_1 3766 LaneBitmask(0x000000C0), // dsub_2 3767 LaneBitmask(0x00000300), // dsub_3 3768 LaneBitmask(0x00000C00), // dsub_4 3769 LaneBitmask(0x00003000), // dsub_5 3770 LaneBitmask(0x0000C000), // dsub_6 3771 LaneBitmask(0x00030000), // dsub_7 3772 LaneBitmask(0x00000001), // gsub_0 3773 LaneBitmask(0x00000002), // gsub_1 3774 LaneBitmask(0x000003FC), // qqsub_0 3775 LaneBitmask(0x0003FC00), // qqsub_1 3776 LaneBitmask(0x0000003C), // qsub_0 3777 LaneBitmask(0x000003C0), // qsub_1 3778 LaneBitmask(0x00003C00), // qsub_2 3779 LaneBitmask(0x0003C000), // qsub_3 3780 LaneBitmask(0x00000004), // ssub_0 3781 LaneBitmask(0x00000008), // ssub_1 3782 LaneBitmask(0x00000010), // ssub_2 3783 LaneBitmask(0x00000020), // ssub_3 3784 LaneBitmask(0x00000040), // ssub_4 3785 LaneBitmask(0x00000080), // ssub_5 3786 LaneBitmask(0x00000100), // ssub_6 3787 LaneBitmask(0x00000200), // ssub_7 3788 LaneBitmask(0x00000400), // ssub_8 3789 LaneBitmask(0x00000800), // ssub_9 3790 LaneBitmask(0x00001000), // ssub_10 3791 LaneBitmask(0x00002000), // ssub_11 3792 LaneBitmask(0x00004000), // ssub_12 3793 LaneBitmask(0x00008000), // ssub_13 3794 LaneBitmask(0x00010000), // dsub_7_then_ssub_0 3795 LaneBitmask(0x00020000), // dsub_7_then_ssub_1 3796 LaneBitmask(0x000000CC), // ssub_0_ssub_1_ssub_4_ssub_5 3797 LaneBitmask(0x000000FC), // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 3798 LaneBitmask(0x00000330), // ssub_2_ssub_3_ssub_6_ssub_7 3799 LaneBitmask(0x000003F0), // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 3800 LaneBitmask(0x000000F0), // ssub_2_ssub_3_ssub_4_ssub_5 3801 LaneBitmask(0x00000CCC), // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 3802 LaneBitmask(0x0000CCCC), // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 3803 LaneBitmask(0x00003330), // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 3804 LaneBitmask(0x00033330), // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 3805 LaneBitmask(0x00000FF0), // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 3806 LaneBitmask(0x00000CC0), // ssub_4_ssub_5_ssub_8_ssub_9 3807 LaneBitmask(0x00000FC0), // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 3808 LaneBitmask(0x0000CCC0), // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 3809 LaneBitmask(0x00003300), // ssub_6_ssub_7_dsub_5 3810 LaneBitmask(0x00003F00), // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 3811 LaneBitmask(0x00033300), // ssub_6_ssub_7_dsub_5_dsub_7 3812 LaneBitmask(0x00000F00), // ssub_6_ssub_7_ssub_8_ssub_9 3813 LaneBitmask(0x0000FF00), // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 3814 LaneBitmask(0x0000CC00), // ssub_8_ssub_9_ssub_12_ssub_13 3815 LaneBitmask(0x0000FC00), // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 3816 LaneBitmask(0x00033000), // dsub_5_dsub_7 3817 LaneBitmask(0x0003F000), // dsub_5_ssub_12_ssub_13_dsub_7 3818 LaneBitmask(0x0000F000), // dsub_5_ssub_12_ssub_13 3819 LaneBitmask(0x00003FC0), // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 3820 }; 3821 3822 3823 3824static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = { 3825 // Mode = 0 (Default) 3826 { 16, 16, 32, VTLists+2 }, // HPR 3827 { 32, 32, 32, VTLists+4 }, // FPWithVPR 3828 { 32, 32, 32, VTLists+4 }, // SPR 3829 { 32, 32, 32, VTLists+4 }, // FPWithVPR_with_ssub_0 3830 { 32, 32, 32, VTLists+0 }, // GPR 3831 { 32, 32, 32, VTLists+0 }, // GPRwithAPSR 3832 { 32, 32, 32, VTLists+0 }, // GPRwithZR 3833 { 32, 32, 32, VTLists+4 }, // SPR_8 3834 { 32, 32, 32, VTLists+0 }, // GPRnopc 3835 { 32, 32, 32, VTLists+0 }, // GPRwithAPSRnosp 3836 { 32, 32, 32, VTLists+0 }, // GPRwithZRnosp 3837 { 32, 32, 32, VTLists+0 }, // rGPR 3838 { 32, 32, 32, VTLists+0 }, // tGPRwithpc 3839 { 32, 32, 32, VTLists+4 }, // FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 3840 { 32, 32, 32, VTLists+0 }, // hGPR 3841 { 32, 32, 32, VTLists+0 }, // tGPR 3842 { 32, 32, 32, VTLists+0 }, // tGPREven 3843 { 32, 32, 32, VTLists+0 }, // GPRnopc_and_hGPR 3844 { 32, 32, 32, VTLists+0 }, // GPRwithAPSRnosp_and_hGPR 3845 { 32, 32, 32, VTLists+0 }, // tGPROdd 3846 { 32, 32, 32, VTLists+0 }, // tcGPR 3847 { 32, 32, 32, VTLists+0 }, // hGPR_and_tGPREven 3848 { 32, 32, 32, VTLists+0 }, // tGPR_and_tGPREven 3849 { 32, 32, 32, VTLists+0 }, // tGPR_and_tGPROdd 3850 { 32, 32, 32, VTLists+0 }, // tGPR_and_tcGPR 3851 { 32, 32, 32, VTLists+0 }, // tGPREven_and_tcGPR 3852 { 32, 32, 32, VTLists+0 }, // hGPR_and_tGPROdd 3853 { 32, 32, 32, VTLists+0 }, // tGPREven_and_tGPR_and_tcGPR 3854 { 32, 32, 32, VTLists+0 }, // tGPROdd_and_tcGPR 3855 { 32, 32, 32, VTLists+0 }, // CCR 3856 { 32, 32, 32, VTLists+0 }, // GPRlr 3857 { 32, 32, 32, VTLists+0 }, // GPRsp 3858 { 32, 32, 32, VTLists+6 }, // VCCR 3859 { 32, 32, 32, VTLists+0 }, // cl_FPSCR_NZCV 3860 { 32, 32, 32, VTLists+0 }, // hGPR_and_tGPRwithpc 3861 { 32, 32, 32, VTLists+0 }, // hGPR_and_tcGPR 3862 { 64, 64, 64, VTLists+17 }, // DPR 3863 { 64, 64, 64, VTLists+17 }, // DPR_VFP2 3864 { 64, 64, 64, VTLists+17 }, // DPR_8 3865 { 64, 64, 64, VTLists+40 }, // GPRPair 3866 { 64, 64, 64, VTLists+40 }, // GPRPairnosp 3867 { 64, 64, 64, VTLists+40 }, // GPRPair_with_gsub_0_in_tGPR 3868 { 64, 64, 64, VTLists+40 }, // GPRPair_with_gsub_0_in_hGPR 3869 { 64, 64, 64, VTLists+40 }, // GPRPair_with_gsub_0_in_tcGPR 3870 { 64, 64, 64, VTLists+40 }, // GPRPair_with_gsub_1_in_tcGPR 3871 { 64, 64, 64, VTLists+40 }, // GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR 3872 { 64, 64, 64, VTLists+40 }, // GPRPair_with_gsub_1_in_GPRsp 3873 { 128, 128, 64, VTLists+11 }, // DPairSpc 3874 { 128, 128, 64, VTLists+11 }, // DPairSpc_with_ssub_0 3875 { 128, 128, 64, VTLists+11 }, // DPairSpc_with_ssub_4 3876 { 128, 128, 64, VTLists+11 }, // DPairSpc_with_dsub_0_in_DPR_8 3877 { 128, 128, 64, VTLists+11 }, // DPairSpc_with_dsub_2_in_DPR_8 3878 { 128, 128, 128, VTLists+33 }, // DPair 3879 { 128, 128, 128, VTLists+33 }, // DPair_with_ssub_0 3880 { 128, 128, 128, VTLists+25 }, // QPR 3881 { 128, 128, 128, VTLists+33 }, // DPair_with_ssub_2 3882 { 128, 128, 128, VTLists+33 }, // DPair_with_dsub_0_in_DPR_8 3883 { 128, 128, 128, VTLists+25 }, // MQPR 3884 { 128, 128, 128, VTLists+33 }, // QPR_VFP2 3885 { 128, 128, 128, VTLists+33 }, // DPair_with_dsub_1_in_DPR_8 3886 { 128, 128, 128, VTLists+33 }, // QPR_8 3887 { 192, 192, 64, VTLists+40 }, // DTriple 3888 { 192, 192, 64, VTLists+40 }, // DTripleSpc 3889 { 192, 192, 64, VTLists+40 }, // DTripleSpc_with_ssub_0 3890 { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_0 3891 { 192, 192, 64, VTLists+40 }, // DTriple_with_qsub_0_in_QPR 3892 { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_2 3893 { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 3894 { 192, 192, 64, VTLists+40 }, // DTripleSpc_with_ssub_4 3895 { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_4 3896 { 192, 192, 64, VTLists+40 }, // DTripleSpc_with_ssub_8 3897 { 192, 192, 64, VTLists+40 }, // DTripleSpc_with_dsub_0_in_DPR_8 3898 { 192, 192, 64, VTLists+40 }, // DTriple_with_dsub_0_in_DPR_8 3899 { 192, 192, 64, VTLists+40 }, // DTriple_with_qsub_0_in_MQPR 3900 { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 3901 { 192, 192, 64, VTLists+40 }, // DTriple_with_dsub_1_in_DPR_8 3902 { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 3903 { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR 3904 { 192, 192, 64, VTLists+40 }, // DTripleSpc_with_dsub_2_in_DPR_8 3905 { 192, 192, 64, VTLists+40 }, // DTriple_with_dsub_2_in_DPR_8 3906 { 192, 192, 64, VTLists+40 }, // DTripleSpc_with_dsub_4_in_DPR_8 3907 { 192, 192, 64, VTLists+40 }, // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 3908 { 192, 192, 64, VTLists+40 }, // DTriple_with_qsub_0_in_QPR_8 3909 { 192, 192, 64, VTLists+40 }, // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR 3910 { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 3911 { 256, 256, 64, VTLists+13 }, // DQuadSpc 3912 { 256, 256, 64, VTLists+13 }, // DQuadSpc_with_ssub_0 3913 { 256, 256, 64, VTLists+13 }, // DQuadSpc_with_ssub_4 3914 { 256, 256, 64, VTLists+13 }, // DQuadSpc_with_ssub_8 3915 { 256, 256, 64, VTLists+13 }, // DQuadSpc_with_dsub_0_in_DPR_8 3916 { 256, 256, 64, VTLists+13 }, // DQuadSpc_with_dsub_2_in_DPR_8 3917 { 256, 256, 64, VTLists+13 }, // DQuadSpc_with_dsub_4_in_DPR_8 3918 { 256, 256, 256, VTLists+13 }, // DQuad 3919 { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_0 3920 { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_2 3921 { 256, 256, 256, VTLists+13 }, // QQPR 3922 { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 3923 { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_4 3924 { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_6 3925 { 256, 256, 256, VTLists+13 }, // DQuad_with_dsub_0_in_DPR_8 3926 { 256, 256, 256, VTLists+13 }, // DQuad_with_qsub_0_in_MQPR 3927 { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 3928 { 256, 256, 256, VTLists+13 }, // DQuad_with_dsub_1_in_DPR_8 3929 { 256, 256, 256, VTLists+13 }, // DQuad_with_qsub_1_in_MQPR 3930 { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 3931 { 256, 256, 256, VTLists+13 }, // DQuad_with_dsub_2_in_DPR_8 3932 { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 3933 { 256, 256, 256, VTLists+13 }, // DQuad_with_dsub_3_in_DPR_8 3934 { 256, 256, 256, VTLists+13 }, // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 3935 { 256, 256, 256, VTLists+13 }, // DQuad_with_qsub_0_in_QPR_8 3936 { 256, 256, 256, VTLists+13 }, // DQuad_with_qsub_1_in_QPR_8 3937 { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 3938 { 256, 256, 256, VTLists+13 }, // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 3939 { 512, 512, 256, VTLists+15 }, // QQQQPR 3940 { 512, 512, 256, VTLists+15 }, // QQQQPR_with_ssub_0 3941 { 512, 512, 256, VTLists+15 }, // QQQQPR_with_ssub_4 3942 { 512, 512, 256, VTLists+15 }, // QQQQPR_with_ssub_8 3943 { 512, 512, 256, VTLists+15 }, // QQQQPR_with_ssub_12 3944 { 512, 512, 256, VTLists+15 }, // QQQQPR_with_dsub_0_in_DPR_8 3945 { 512, 512, 256, VTLists+15 }, // QQQQPR_with_dsub_2_in_DPR_8 3946 { 512, 512, 256, VTLists+15 }, // QQQQPR_with_dsub_4_in_DPR_8 3947 { 512, 512, 256, VTLists+15 }, // QQQQPR_with_dsub_6_in_DPR_8 3948}; 3949 3950static const TargetRegisterClass *const NullRegClasses[] = { nullptr }; 3951 3952static const uint32_t HPRSubClassMask[] = { 3953 0x00000085, 0x00000000, 0x00000000, 0x00000000, 3954 0x00002008, 0x9faf0060, 0x6fdffff5, 0x03fdfffe, // ssub_0 3955 0x00002008, 0x9faf0060, 0x6fdffff5, 0x03fdfffe, // ssub_1 3956 0x00000000, 0x1f800000, 0x401ebb24, 0x03fdffde, // ssub_2 3957 0x00000000, 0x1f800000, 0x401ebb24, 0x03fdffde, // ssub_3 3958 0x00000000, 0x000e0000, 0x0f9ff9f0, 0x03f9ffce, // ssub_4 3959 0x00000000, 0x000e0000, 0x0f9ff9f0, 0x03f9ffce, // ssub_5 3960 0x00000000, 0x00000000, 0x00000000, 0x03f9fecc, // ssub_6 3961 0x00000000, 0x00000000, 0x00000000, 0x03f9fecc, // ssub_7 3962 0x00000000, 0x00000000, 0x0f0140c0, 0x03f00000, // ssub_8 3963 0x00000000, 0x00000000, 0x0f0140c0, 0x03f00000, // ssub_9 3964 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_10 3965 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_11 3966 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_12 3967 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_13 3968 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_7_then_ssub_0 3969 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_7_then_ssub_1 3970}; 3971 3972static const uint32_t FPWithVPRSubClassMask[] = { 3973 0x0000208e, 0x00000071, 0x00000000, 0x00000000, 3974 0x00000000, 0xffff8000, 0xffffffff, 0x03ffffff, // dsub_0 3975 0x00000000, 0x3ff00000, 0xf01ebf2f, 0x03ffffff, // dsub_1 3976 0x00000000, 0xe00f8000, 0xffffffff, 0x03ffffff, // dsub_2 3977 0x00000000, 0x00000000, 0xf0000000, 0x03ffffff, // dsub_3 3978 0x00000000, 0xc0000000, 0x0fe140d0, 0x03fe0000, // dsub_4 3979 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // dsub_5 3980 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // dsub_6 3981 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // dsub_7 3982 0x00002008, 0x9faf0060, 0x6fdffff5, 0x03fdfffe, // ssub_0 3983 0x00002008, 0x9faf0060, 0x6fdffff5, 0x03fdfffe, // ssub_1 3984 0x00000000, 0x1f800000, 0x401ebb24, 0x03fdffde, // ssub_2 3985 0x00000000, 0x1f800000, 0x401ebb24, 0x03fdffde, // ssub_3 3986 0x00000000, 0x000e0000, 0x0f9ff9f0, 0x03f9ffce, // ssub_4 3987 0x00000000, 0x000e0000, 0x0f9ff9f0, 0x03f9ffce, // ssub_5 3988 0x00000000, 0x00000000, 0x00000000, 0x03f9fecc, // ssub_6 3989 0x00000000, 0x00000000, 0x00000000, 0x03f9fecc, // ssub_7 3990 0x00000000, 0x00000000, 0x0f0140c0, 0x03f00000, // ssub_8 3991 0x00000000, 0x00000000, 0x0f0140c0, 0x03f00000, // ssub_9 3992 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_10 3993 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_11 3994 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_12 3995 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_13 3996 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_7_then_ssub_0 3997 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_7_then_ssub_1 3998}; 3999 4000static const uint32_t SPRSubClassMask[] = { 4001 0x00000084, 0x00000000, 0x00000000, 0x00000000, 4002 0x00002008, 0x9faf0060, 0x6fdffff5, 0x03fdfffe, // ssub_0 4003 0x00002008, 0x9faf0060, 0x6fdffff5, 0x03fdfffe, // ssub_1 4004 0x00000000, 0x1f800000, 0x401ebb24, 0x03fdffde, // ssub_2 4005 0x00000000, 0x1f800000, 0x401ebb24, 0x03fdffde, // ssub_3 4006 0x00000000, 0x000e0000, 0x0f9ff9f0, 0x03f9ffce, // ssub_4 4007 0x00000000, 0x000e0000, 0x0f9ff9f0, 0x03f9ffce, // ssub_5 4008 0x00000000, 0x00000000, 0x00000000, 0x03f9fecc, // ssub_6 4009 0x00000000, 0x00000000, 0x00000000, 0x03f9fecc, // ssub_7 4010 0x00000000, 0x00000000, 0x0f0140c0, 0x03f00000, // ssub_8 4011 0x00000000, 0x00000000, 0x0f0140c0, 0x03f00000, // ssub_9 4012 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_10 4013 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_11 4014 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_12 4015 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_13 4016 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_7_then_ssub_0 4017 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_7_then_ssub_1 4018}; 4019 4020static const uint32_t FPWithVPR_with_ssub_0SubClassMask[] = { 4021 0x00002008, 0x00000060, 0x00000000, 0x00000000, 4022 0x00000000, 0x9faf0000, 0x6fdffff5, 0x03fdfffe, // dsub_0 4023 0x00000000, 0x1f800000, 0x401ebb24, 0x03fdffde, // dsub_1 4024 0x00000000, 0x000e0000, 0x0f9ff9f0, 0x03f9ffce, // dsub_2 4025 0x00000000, 0x00000000, 0x00000000, 0x03f9fecc, // dsub_3 4026 0x00000000, 0x00000000, 0x0f0140c0, 0x03f00000, // dsub_4 4027 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // dsub_5 4028 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_6 4029 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_7 4030}; 4031 4032static const uint32_t GPRSubClassMask[] = { 4033 0xdfffd910, 0x0000000c, 0x00000000, 0x00000000, 4034 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_0 4035 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_1 4036}; 4037 4038static const uint32_t GPRwithAPSRSubClassMask[] = { 4039 0xdfff8920, 0x00000008, 0x00000000, 0x00000000, 4040 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_0 4041 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_1 4042}; 4043 4044static const uint32_t GPRwithZRSubClassMask[] = { 4045 0xdfff8d40, 0x00000008, 0x00000000, 0x00000000, 4046 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_0 4047 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_1 4048}; 4049 4050static const uint32_t SPR_8SubClassMask[] = { 4051 0x00000080, 0x00000000, 0x00000000, 0x00000000, 4052 0x00002000, 0x190c0040, 0x0e1fc980, 0x03c1fa48, // ssub_0 4053 0x00002000, 0x190c0040, 0x0e1fc980, 0x03c1fa48, // ssub_1 4054 0x00000000, 0x18000000, 0x001c8800, 0x03c1ea40, // ssub_2 4055 0x00000000, 0x18000000, 0x001c8800, 0x03c1ea40, // ssub_3 4056 0x00000000, 0x00080000, 0x0c19c000, 0x0381ca00, // ssub_4 4057 0x00000000, 0x00080000, 0x0c19c000, 0x0381ca00, // ssub_5 4058 0x00000000, 0x00000000, 0x00000000, 0x03814800, // ssub_6 4059 0x00000000, 0x00000000, 0x00000000, 0x03814800, // ssub_7 4060 0x00000000, 0x00000000, 0x08010000, 0x03000000, // ssub_8 4061 0x00000000, 0x00000000, 0x08010000, 0x03000000, // ssub_9 4062 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_10 4063 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_11 4064 0x00000000, 0x00000000, 0x00000000, 0x02000000, // ssub_12 4065 0x00000000, 0x00000000, 0x00000000, 0x02000000, // ssub_13 4066 0x00000000, 0x00000000, 0x00000000, 0x02000000, // dsub_7_then_ssub_0 4067 0x00000000, 0x00000000, 0x00000000, 0x02000000, // dsub_7_then_ssub_1 4068}; 4069 4070static const uint32_t GPRnopcSubClassMask[] = { 4071 0xdfff8900, 0x00000008, 0x00000000, 0x00000000, 4072 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_0 4073 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_1 4074}; 4075 4076static const uint32_t GPRwithAPSRnospSubClassMask[] = { 4077 0x5ffd8a00, 0x00000008, 0x00000000, 0x00000000, 4078 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_0 4079 0x00000000, 0x00003300, 0x00000000, 0x00000000, // gsub_1 4080}; 4081 4082static const uint32_t GPRwithZRnospSubClassMask[] = { 4083 0x5ffd8c00, 0x00000008, 0x00000000, 0x00000000, 4084 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_0 4085 0x00000000, 0x00003300, 0x00000000, 0x00000000, // gsub_1 4086}; 4087 4088static const uint32_t rGPRSubClassMask[] = { 4089 0x5ffd8800, 0x00000008, 0x00000000, 0x00000000, 4090 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_0 4091 0x00000000, 0x00003300, 0x00000000, 0x00000000, // gsub_1 4092}; 4093 4094static const uint32_t tGPRwithpcSubClassMask[] = { 4095 0x19c09000, 0x00000004, 0x00000000, 0x00000000, 4096 0x00000000, 0x00001200, 0x00000000, 0x00000000, // gsub_0 4097 0x00000000, 0x00001200, 0x00000000, 0x00000000, // gsub_1 4098}; 4099 4100static const uint32_t FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8SubClassMask[] = { 4101 0x00002000, 0x00000040, 0x00000000, 0x00000000, 4102 0x00000000, 0x190c0000, 0x0e1fc980, 0x03c1fa48, // dsub_0 4103 0x00000000, 0x18000000, 0x001c8800, 0x03c1ea40, // dsub_1 4104 0x00000000, 0x00080000, 0x0c19c000, 0x0381ca00, // dsub_2 4105 0x00000000, 0x00000000, 0x00000000, 0x03814800, // dsub_3 4106 0x00000000, 0x00000000, 0x08010000, 0x03000000, // dsub_4 4107 0x00000000, 0x00000000, 0x00000000, 0x03000000, // dsub_5 4108 0x00000000, 0x00000000, 0x00000000, 0x02000000, // dsub_6 4109 0x00000000, 0x00000000, 0x00000000, 0x02000000, // dsub_7 4110}; 4111 4112static const uint32_t hGPRSubClassMask[] = { 4113 0xc4264000, 0x0000000c, 0x00000000, 0x00000000, 4114 0x00000000, 0x00006400, 0x00000000, 0x00000000, // gsub_0 4115 0x00000000, 0x00006400, 0x00000000, 0x00000000, // gsub_1 4116}; 4117 4118static const uint32_t tGPRSubClassMask[] = { 4119 0x19c08000, 0x00000000, 0x00000000, 0x00000000, 4120 0x00000000, 0x00001200, 0x00000000, 0x00000000, // gsub_0 4121 0x00000000, 0x00001200, 0x00000000, 0x00000000, // gsub_1 4122}; 4123 4124static const uint32_t tGPREvenSubClassMask[] = { 4125 0x4a610000, 0x00000008, 0x00000000, 0x00000000, 4126 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_0 4127}; 4128 4129static const uint32_t GPRnopc_and_hGPRSubClassMask[] = { 4130 0xc4260000, 0x00000008, 0x00000000, 0x00000000, 4131 0x00000000, 0x00006400, 0x00000000, 0x00000000, // gsub_0 4132 0x00000000, 0x00006400, 0x00000000, 0x00000000, // gsub_1 4133}; 4134 4135static const uint32_t GPRwithAPSRnosp_and_hGPRSubClassMask[] = { 4136 0x44240000, 0x00000008, 0x00000000, 0x00000000, 4137 0x00000000, 0x00006400, 0x00000000, 0x00000000, // gsub_0 4138 0x00000000, 0x00002000, 0x00000000, 0x00000000, // gsub_1 4139}; 4140 4141static const uint32_t tGPROddSubClassMask[] = { 4142 0x14880000, 0x00000000, 0x00000000, 0x00000000, 4143 0x00000000, 0x00003300, 0x00000000, 0x00000000, // gsub_1 4144}; 4145 4146static const uint32_t tcGPRSubClassMask[] = { 4147 0x1b100000, 0x00000008, 0x00000000, 0x00000000, 4148 0x00000000, 0x00005800, 0x00000000, 0x00000000, // gsub_0 4149 0x00000000, 0x00001000, 0x00000000, 0x00000000, // gsub_1 4150}; 4151 4152static const uint32_t hGPR_and_tGPREvenSubClassMask[] = { 4153 0x40200000, 0x00000008, 0x00000000, 0x00000000, 4154 0x00000000, 0x00006400, 0x00000000, 0x00000000, // gsub_0 4155}; 4156 4157static const uint32_t tGPR_and_tGPREvenSubClassMask[] = { 4158 0x08400000, 0x00000000, 0x00000000, 0x00000000, 4159 0x00000000, 0x00001200, 0x00000000, 0x00000000, // gsub_0 4160}; 4161 4162static const uint32_t tGPR_and_tGPROddSubClassMask[] = { 4163 0x10800000, 0x00000000, 0x00000000, 0x00000000, 4164 0x00000000, 0x00001200, 0x00000000, 0x00000000, // gsub_1 4165}; 4166 4167static const uint32_t tGPR_and_tcGPRSubClassMask[] = { 4168 0x19000000, 0x00000000, 0x00000000, 0x00000000, 4169 0x00000000, 0x00001000, 0x00000000, 0x00000000, // gsub_0 4170 0x00000000, 0x00001000, 0x00000000, 0x00000000, // gsub_1 4171}; 4172 4173static const uint32_t tGPREven_and_tcGPRSubClassMask[] = { 4174 0x0a000000, 0x00000008, 0x00000000, 0x00000000, 4175 0x00000000, 0x00005800, 0x00000000, 0x00000000, // gsub_0 4176}; 4177 4178static const uint32_t hGPR_and_tGPROddSubClassMask[] = { 4179 0x04000000, 0x00000000, 0x00000000, 0x00000000, 4180 0x00000000, 0x00002000, 0x00000000, 0x00000000, // gsub_1 4181}; 4182 4183static const uint32_t tGPREven_and_tGPR_and_tcGPRSubClassMask[] = { 4184 0x08000000, 0x00000000, 0x00000000, 0x00000000, 4185 0x00000000, 0x00001000, 0x00000000, 0x00000000, // gsub_0 4186}; 4187 4188static const uint32_t tGPROdd_and_tcGPRSubClassMask[] = { 4189 0x10000000, 0x00000000, 0x00000000, 0x00000000, 4190 0x00000000, 0x00001000, 0x00000000, 0x00000000, // gsub_1 4191}; 4192 4193static const uint32_t CCRSubClassMask[] = { 4194 0x20000000, 0x00000000, 0x00000000, 0x00000000, 4195}; 4196 4197static const uint32_t GPRlrSubClassMask[] = { 4198 0x40000000, 0x00000000, 0x00000000, 0x00000000, 4199}; 4200 4201static const uint32_t GPRspSubClassMask[] = { 4202 0x80000000, 0x00000000, 0x00000000, 0x00000000, 4203 0x00000000, 0x00004000, 0x00000000, 0x00000000, // gsub_1 4204}; 4205 4206static const uint32_t VCCRSubClassMask[] = { 4207 0x00000000, 0x00000001, 0x00000000, 0x00000000, 4208}; 4209 4210static const uint32_t cl_FPSCR_NZCVSubClassMask[] = { 4211 0x00000000, 0x00000002, 0x00000000, 0x00000000, 4212}; 4213 4214static const uint32_t hGPR_and_tGPRwithpcSubClassMask[] = { 4215 0x00000000, 0x00000004, 0x00000000, 0x00000000, 4216}; 4217 4218static const uint32_t hGPR_and_tcGPRSubClassMask[] = { 4219 0x00000000, 0x00000008, 0x00000000, 0x00000000, 4220 0x00000000, 0x00004000, 0x00000000, 0x00000000, // gsub_0 4221}; 4222 4223static const uint32_t DPRSubClassMask[] = { 4224 0x00000000, 0x00000070, 0x00000000, 0x00000000, 4225 0x00000000, 0xffff8000, 0xffffffff, 0x03ffffff, // dsub_0 4226 0x00000000, 0x3ff00000, 0xf01ebf2f, 0x03ffffff, // dsub_1 4227 0x00000000, 0xe00f8000, 0xffffffff, 0x03ffffff, // dsub_2 4228 0x00000000, 0x00000000, 0xf0000000, 0x03ffffff, // dsub_3 4229 0x00000000, 0xc0000000, 0x0fe140d0, 0x03fe0000, // dsub_4 4230 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // dsub_5 4231 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // dsub_6 4232 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // dsub_7 4233}; 4234 4235static const uint32_t DPR_VFP2SubClassMask[] = { 4236 0x00000000, 0x00000060, 0x00000000, 0x00000000, 4237 0x00000000, 0x9faf0000, 0x6fdffff5, 0x03fdfffe, // dsub_0 4238 0x00000000, 0x1f800000, 0x401ebb24, 0x03fdffde, // dsub_1 4239 0x00000000, 0x000e0000, 0x0f9ff9f0, 0x03f9ffce, // dsub_2 4240 0x00000000, 0x00000000, 0x00000000, 0x03f9fecc, // dsub_3 4241 0x00000000, 0x00000000, 0x0f0140c0, 0x03f00000, // dsub_4 4242 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // dsub_5 4243 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_6 4244 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_7 4245}; 4246 4247static const uint32_t DPR_8SubClassMask[] = { 4248 0x00000000, 0x00000040, 0x00000000, 0x00000000, 4249 0x00000000, 0x190c0000, 0x0e1fc980, 0x03c1fa48, // dsub_0 4250 0x00000000, 0x18000000, 0x001c8800, 0x03c1ea40, // dsub_1 4251 0x00000000, 0x00080000, 0x0c19c000, 0x0381ca00, // dsub_2 4252 0x00000000, 0x00000000, 0x00000000, 0x03814800, // dsub_3 4253 0x00000000, 0x00000000, 0x08010000, 0x03000000, // dsub_4 4254 0x00000000, 0x00000000, 0x00000000, 0x03000000, // dsub_5 4255 0x00000000, 0x00000000, 0x00000000, 0x02000000, // dsub_6 4256 0x00000000, 0x00000000, 0x00000000, 0x02000000, // dsub_7 4257}; 4258 4259static const uint32_t GPRPairSubClassMask[] = { 4260 0x00000000, 0x00007f80, 0x00000000, 0x00000000, 4261}; 4262 4263static const uint32_t GPRPairnospSubClassMask[] = { 4264 0x00000000, 0x00003300, 0x00000000, 0x00000000, 4265}; 4266 4267static const uint32_t GPRPair_with_gsub_0_in_tGPRSubClassMask[] = { 4268 0x00000000, 0x00001200, 0x00000000, 0x00000000, 4269}; 4270 4271static const uint32_t GPRPair_with_gsub_0_in_hGPRSubClassMask[] = { 4272 0x00000000, 0x00006400, 0x00000000, 0x00000000, 4273}; 4274 4275static const uint32_t GPRPair_with_gsub_0_in_tcGPRSubClassMask[] = { 4276 0x00000000, 0x00005800, 0x00000000, 0x00000000, 4277}; 4278 4279static const uint32_t GPRPair_with_gsub_1_in_tcGPRSubClassMask[] = { 4280 0x00000000, 0x00001000, 0x00000000, 0x00000000, 4281}; 4282 4283static const uint32_t GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRSubClassMask[] = { 4284 0x00000000, 0x00002000, 0x00000000, 0x00000000, 4285}; 4286 4287static const uint32_t GPRPair_with_gsub_1_in_GPRspSubClassMask[] = { 4288 0x00000000, 0x00004000, 0x00000000, 0x00000000, 4289}; 4290 4291static const uint32_t DPairSpcSubClassMask[] = { 4292 0x00000000, 0x000f8000, 0x00000000, 0x00000000, 4293 0x00000000, 0xe0000000, 0xffffffff, 0x03ffffff, // ssub_0_ssub_1_ssub_4_ssub_5 4294 0x00000000, 0x00000000, 0xf0000000, 0x03ffffff, // ssub_2_ssub_3_ssub_6_ssub_7 4295 0x00000000, 0xc0000000, 0x0fe140d0, 0x03fe0000, // ssub_4_ssub_5_ssub_8_ssub_9 4296 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_6_ssub_7_dsub_5 4297 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_8_ssub_9_ssub_12_ssub_13 4298 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // dsub_5_dsub_7 4299}; 4300 4301static const uint32_t DPairSpc_with_ssub_0SubClassMask[] = { 4302 0x00000000, 0x000f0000, 0x00000000, 0x00000000, 4303 0x00000000, 0x80000000, 0x6fdffff5, 0x03fdfffe, // ssub_0_ssub_1_ssub_4_ssub_5 4304 0x00000000, 0x00000000, 0x40000000, 0x03fdffde, // ssub_2_ssub_3_ssub_6_ssub_7 4305 0x00000000, 0x00000000, 0x0f8140d0, 0x03f80000, // ssub_4_ssub_5_ssub_8_ssub_9 4306 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_6_ssub_7_dsub_5 4307 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_8_ssub_9_ssub_12_ssub_13 4308 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // dsub_5_dsub_7 4309}; 4310 4311static const uint32_t DPairSpc_with_ssub_4SubClassMask[] = { 4312 0x00000000, 0x000e0000, 0x00000000, 0x00000000, 4313 0x00000000, 0x00000000, 0x0f9ff9f0, 0x03f9ffce, // ssub_0_ssub_1_ssub_4_ssub_5 4314 0x00000000, 0x00000000, 0x00000000, 0x03f9fecc, // ssub_2_ssub_3_ssub_6_ssub_7 4315 0x00000000, 0x00000000, 0x0f0140c0, 0x03f00000, // ssub_4_ssub_5_ssub_8_ssub_9 4316 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_6_ssub_7_dsub_5 4317 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_8_ssub_9_ssub_12_ssub_13 4318 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_5_dsub_7 4319}; 4320 4321static const uint32_t DPairSpc_with_dsub_0_in_DPR_8SubClassMask[] = { 4322 0x00000000, 0x000c0000, 0x00000000, 0x00000000, 4323 0x00000000, 0x00000000, 0x0e1fc980, 0x03c1fa48, // ssub_0_ssub_1_ssub_4_ssub_5 4324 0x00000000, 0x00000000, 0x00000000, 0x03c1ea40, // ssub_2_ssub_3_ssub_6_ssub_7 4325 0x00000000, 0x00000000, 0x0c014000, 0x03800000, // ssub_4_ssub_5_ssub_8_ssub_9 4326 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_6_ssub_7_dsub_5 4327 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_8_ssub_9_ssub_12_ssub_13 4328 0x00000000, 0x00000000, 0x00000000, 0x03000000, // dsub_5_dsub_7 4329}; 4330 4331static const uint32_t DPairSpc_with_dsub_2_in_DPR_8SubClassMask[] = { 4332 0x00000000, 0x00080000, 0x00000000, 0x00000000, 4333 0x00000000, 0x00000000, 0x0c19c000, 0x0381ca00, // ssub_0_ssub_1_ssub_4_ssub_5 4334 0x00000000, 0x00000000, 0x00000000, 0x03814800, // ssub_2_ssub_3_ssub_6_ssub_7 4335 0x00000000, 0x00000000, 0x08010000, 0x03000000, // ssub_4_ssub_5_ssub_8_ssub_9 4336 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_6_ssub_7_dsub_5 4337 0x00000000, 0x00000000, 0x00000000, 0x02000000, // ssub_8_ssub_9_ssub_12_ssub_13 4338 0x00000000, 0x00000000, 0x00000000, 0x02000000, // dsub_5_dsub_7 4339}; 4340 4341static const uint32_t DPairSubClassMask[] = { 4342 0x00000000, 0x1ff00000, 0x00000000, 0x00000000, 4343 0x00000000, 0x20000000, 0xf01ebf2f, 0x03ffffff, // qsub_0 4344 0x00000000, 0x00000000, 0xf0000000, 0x03ffffff, // qsub_1 4345 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // qsub_2 4346 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // qsub_3 4347 0x00000000, 0x20000000, 0xf01ebf2f, 0x03ffffff, // ssub_2_ssub_3_ssub_4_ssub_5 4348 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_6_ssub_7_ssub_8_ssub_9 4349 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // dsub_5_ssub_12_ssub_13 4350}; 4351 4352static const uint32_t DPair_with_ssub_0SubClassMask[] = { 4353 0x00000000, 0x1fa00000, 0x00000000, 0x00000000, 4354 0x00000000, 0x00000000, 0x601ebf25, 0x03fdfffe, // qsub_0 4355 0x00000000, 0x00000000, 0x00000000, 0x03f9ffce, // qsub_1 4356 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // qsub_2 4357 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // qsub_3 4358 0x00000000, 0x00000000, 0x401ebb24, 0x03fdffde, // ssub_2_ssub_3_ssub_4_ssub_5 4359 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_6_ssub_7_ssub_8_ssub_9 4360 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // dsub_5_ssub_12_ssub_13 4361}; 4362 4363static const uint32_t QPRSubClassMask[] = { 4364 0x00000000, 0x16400000, 0x00000000, 0x00000000, 4365 0x00000000, 0x00000000, 0x800c2202, 0x03fe6090, // qsub_0 4366 0x00000000, 0x00000000, 0x80000000, 0x03fe6090, // qsub_1 4367 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // qsub_2 4368 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // qsub_3 4369 0x00000000, 0x00000000, 0x00121408, 0x00019521, // ssub_2_ssub_3_ssub_4_ssub_5 4370}; 4371 4372static const uint32_t DPair_with_ssub_2SubClassMask[] = { 4373 0x00000000, 0x1f800000, 0x00000000, 0x00000000, 4374 0x00000000, 0x00000000, 0x401ebb24, 0x03fdffde, // qsub_0 4375 0x00000000, 0x00000000, 0x00000000, 0x03f9fecc, // qsub_1 4376 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // qsub_2 4377 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // qsub_3 4378 0x00000000, 0x00000000, 0x001eb920, 0x03f9ffce, // ssub_2_ssub_3_ssub_4_ssub_5 4379 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_6_ssub_7_ssub_8_ssub_9 4380 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_5_ssub_12_ssub_13 4381}; 4382 4383static const uint32_t DPair_with_dsub_0_in_DPR_8SubClassMask[] = { 4384 0x00000000, 0x19000000, 0x00000000, 0x00000000, 4385 0x00000000, 0x00000000, 0x001e8900, 0x03c1fa48, // qsub_0 4386 0x00000000, 0x00000000, 0x00000000, 0x0381ca00, // qsub_1 4387 0x00000000, 0x00000000, 0x00000000, 0x03000000, // qsub_2 4388 0x00000000, 0x00000000, 0x00000000, 0x02000000, // qsub_3 4389 0x00000000, 0x00000000, 0x001c8800, 0x03c1ea40, // ssub_2_ssub_3_ssub_4_ssub_5 4390 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_6_ssub_7_ssub_8_ssub_9 4391 0x00000000, 0x00000000, 0x00000000, 0x03000000, // dsub_5_ssub_12_ssub_13 4392}; 4393 4394static const uint32_t MQPRSubClassMask[] = { 4395 0x00000000, 0x16000000, 0x00000000, 0x00000000, 4396 0x00000000, 0x00000000, 0x000c2200, 0x03fc6090, // qsub_0 4397 0x00000000, 0x00000000, 0x00000000, 0x03f86080, // qsub_1 4398 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // qsub_2 4399 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // qsub_3 4400 0x00000000, 0x00000000, 0x00121000, 0x00019500, // ssub_2_ssub_3_ssub_4_ssub_5 4401}; 4402 4403static const uint32_t QPR_VFP2SubClassMask[] = { 4404 0x00000000, 0x16000000, 0x00000000, 0x00000000, 4405 0x00000000, 0x00000000, 0x000c2200, 0x03fc6090, // qsub_0 4406 0x00000000, 0x00000000, 0x00000000, 0x03f86080, // qsub_1 4407 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // qsub_2 4408 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // qsub_3 4409 0x00000000, 0x00000000, 0x00121000, 0x00019500, // ssub_2_ssub_3_ssub_4_ssub_5 4410}; 4411 4412static const uint32_t DPair_with_dsub_1_in_DPR_8SubClassMask[] = { 4413 0x00000000, 0x18000000, 0x00000000, 0x00000000, 4414 0x00000000, 0x00000000, 0x001c8800, 0x03c1ea40, // qsub_0 4415 0x00000000, 0x00000000, 0x00000000, 0x03814800, // qsub_1 4416 0x00000000, 0x00000000, 0x00000000, 0x03000000, // qsub_2 4417 0x00000000, 0x00000000, 0x00000000, 0x02000000, // qsub_3 4418 0x00000000, 0x00000000, 0x00188000, 0x0381ca00, // ssub_2_ssub_3_ssub_4_ssub_5 4419 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_6_ssub_7_ssub_8_ssub_9 4420 0x00000000, 0x00000000, 0x00000000, 0x02000000, // dsub_5_ssub_12_ssub_13 4421}; 4422 4423static const uint32_t QPR_8SubClassMask[] = { 4424 0x00000000, 0x10000000, 0x00000000, 0x00000000, 4425 0x00000000, 0x00000000, 0x000c0000, 0x03c06000, // qsub_0 4426 0x00000000, 0x00000000, 0x00000000, 0x03804000, // qsub_1 4427 0x00000000, 0x00000000, 0x00000000, 0x03000000, // qsub_2 4428 0x00000000, 0x00000000, 0x00000000, 0x02000000, // qsub_3 4429 0x00000000, 0x00000000, 0x00100000, 0x00018000, // ssub_2_ssub_3_ssub_4_ssub_5 4430}; 4431 4432static const uint32_t DTripleSubClassMask[] = { 4433 0x00000000, 0x20000000, 0x001ebf2f, 0x00000000, 4434 0x00000000, 0x00000000, 0xf0000000, 0x03ffffff, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 4435 0x00000000, 0x00000000, 0xf0000000, 0x03ffffff, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 4436 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4437 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 4438 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4439 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // dsub_5_ssub_12_ssub_13_dsub_7 4440}; 4441 4442static const uint32_t DTripleSpcSubClassMask[] = { 4443 0x00000000, 0xc0000000, 0x0fe140d0, 0x00000000, 4444 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 4445 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 4446 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 4447 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_6_ssub_7_dsub_5_dsub_7 4448}; 4449 4450static const uint32_t DTripleSpc_with_ssub_0SubClassMask[] = { 4451 0x00000000, 0x80000000, 0x0fc140d0, 0x00000000, 4452 0x00000000, 0x00000000, 0x00000000, 0x03fc0000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 4453 0x00000000, 0x00000000, 0x00000000, 0x03fc0000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 4454 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 4455 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_6_ssub_7_dsub_5_dsub_7 4456}; 4457 4458static const uint32_t DTriple_with_ssub_0SubClassMask[] = { 4459 0x00000000, 0x00000000, 0x001ebf25, 0x00000000, 4460 0x00000000, 0x00000000, 0x60000000, 0x03fdfffe, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 4461 0x00000000, 0x00000000, 0x40000000, 0x03fdffde, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 4462 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4463 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 4464 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4465 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // dsub_5_ssub_12_ssub_13_dsub_7 4466}; 4467 4468static const uint32_t DTriple_with_qsub_0_in_QPRSubClassMask[] = { 4469 0x00000000, 0x00000000, 0x000c2202, 0x00000000, 4470 0x00000000, 0x00000000, 0x80000000, 0x03fe6090, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 4471 0x00000000, 0x00000000, 0x00000000, 0x00019521, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 4472 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4473 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4474}; 4475 4476static const uint32_t DTriple_with_ssub_2SubClassMask[] = { 4477 0x00000000, 0x00000000, 0x001ebb24, 0x00000000, 4478 0x00000000, 0x00000000, 0x40000000, 0x03fdffde, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 4479 0x00000000, 0x00000000, 0x00000000, 0x03f9ffce, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 4480 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4481 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 4482 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4483 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_5_ssub_12_ssub_13_dsub_7 4484}; 4485 4486static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = { 4487 0x00000000, 0x00000000, 0x00121408, 0x00000000, 4488 0x00000000, 0x00000000, 0x00000000, 0x00019521, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 4489 0x00000000, 0x00000000, 0x80000000, 0x03fe6090, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 4490 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 4491 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // dsub_5_ssub_12_ssub_13_dsub_7 4492}; 4493 4494static const uint32_t DTripleSpc_with_ssub_4SubClassMask[] = { 4495 0x00000000, 0x00000000, 0x0f8140d0, 0x00000000, 4496 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 4497 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 4498 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 4499 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_6_ssub_7_dsub_5_dsub_7 4500}; 4501 4502static const uint32_t DTriple_with_ssub_4SubClassMask[] = { 4503 0x00000000, 0x00000000, 0x001eb920, 0x00000000, 4504 0x00000000, 0x00000000, 0x00000000, 0x03f9ffce, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 4505 0x00000000, 0x00000000, 0x00000000, 0x03f9fecc, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 4506 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4507 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 4508 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4509 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_5_ssub_12_ssub_13_dsub_7 4510}; 4511 4512static const uint32_t DTripleSpc_with_ssub_8SubClassMask[] = { 4513 0x00000000, 0x00000000, 0x0f0140c0, 0x00000000, 4514 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 4515 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 4516 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 4517 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_6_ssub_7_dsub_5_dsub_7 4518}; 4519 4520static const uint32_t DTripleSpc_with_dsub_0_in_DPR_8SubClassMask[] = { 4521 0x00000000, 0x00000000, 0x0e014080, 0x00000000, 4522 0x00000000, 0x00000000, 0x00000000, 0x03c00000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 4523 0x00000000, 0x00000000, 0x00000000, 0x03c00000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 4524 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 4525 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_6_ssub_7_dsub_5_dsub_7 4526}; 4527 4528static const uint32_t DTriple_with_dsub_0_in_DPR_8SubClassMask[] = { 4529 0x00000000, 0x00000000, 0x001e8900, 0x00000000, 4530 0x00000000, 0x00000000, 0x00000000, 0x03c1fa48, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 4531 0x00000000, 0x00000000, 0x00000000, 0x03c1ea40, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 4532 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4533 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 4534 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4535 0x00000000, 0x00000000, 0x00000000, 0x03000000, // dsub_5_ssub_12_ssub_13_dsub_7 4536}; 4537 4538static const uint32_t DTriple_with_qsub_0_in_MQPRSubClassMask[] = { 4539 0x00000000, 0x00000000, 0x000c2200, 0x00000000, 4540 0x00000000, 0x00000000, 0x00000000, 0x03fc6090, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 4541 0x00000000, 0x00000000, 0x00000000, 0x00019500, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 4542 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4543 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4544}; 4545 4546static const uint32_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = { 4547 0x00000000, 0x00000000, 0x00121400, 0x00000000, 4548 0x00000000, 0x00000000, 0x00000000, 0x00019520, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 4549 0x00000000, 0x00000000, 0x00000000, 0x03fc6090, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 4550 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 4551 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // dsub_5_ssub_12_ssub_13_dsub_7 4552}; 4553 4554static const uint32_t DTriple_with_dsub_1_in_DPR_8SubClassMask[] = { 4555 0x00000000, 0x00000000, 0x001c8800, 0x00000000, 4556 0x00000000, 0x00000000, 0x00000000, 0x03c1ea40, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 4557 0x00000000, 0x00000000, 0x00000000, 0x0381ca00, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 4558 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4559 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 4560 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4561 0x00000000, 0x00000000, 0x00000000, 0x02000000, // dsub_5_ssub_12_ssub_13_dsub_7 4562}; 4563 4564static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask[] = { 4565 0x00000000, 0x00000000, 0x00121000, 0x00000000, 4566 0x00000000, 0x00000000, 0x00000000, 0x00019500, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 4567 0x00000000, 0x00000000, 0x00000000, 0x03f86080, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 4568 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 4569 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_5_ssub_12_ssub_13_dsub_7 4570}; 4571 4572static const uint32_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRSubClassMask[] = { 4573 0x00000000, 0x00000000, 0x000c2000, 0x00000000, 4574 0x00000000, 0x00000000, 0x00000000, 0x03f86080, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 4575 0x00000000, 0x00000000, 0x00000000, 0x00019400, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 4576 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4577 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4578}; 4579 4580static const uint32_t DTripleSpc_with_dsub_2_in_DPR_8SubClassMask[] = { 4581 0x00000000, 0x00000000, 0x0c014000, 0x00000000, 4582 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 4583 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 4584 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 4585 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_6_ssub_7_dsub_5_dsub_7 4586}; 4587 4588static const uint32_t DTriple_with_dsub_2_in_DPR_8SubClassMask[] = { 4589 0x00000000, 0x00000000, 0x00188000, 0x00000000, 4590 0x00000000, 0x00000000, 0x00000000, 0x0381ca00, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 4591 0x00000000, 0x00000000, 0x00000000, 0x03814800, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 4592 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4593 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 4594 0x00000000, 0x00000000, 0x00000000, 0x02000000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4595 0x00000000, 0x00000000, 0x00000000, 0x02000000, // dsub_5_ssub_12_ssub_13_dsub_7 4596}; 4597 4598static const uint32_t DTripleSpc_with_dsub_4_in_DPR_8SubClassMask[] = { 4599 0x00000000, 0x00000000, 0x08010000, 0x00000000, 4600 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 4601 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 4602 0x00000000, 0x00000000, 0x00000000, 0x02000000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 4603 0x00000000, 0x00000000, 0x00000000, 0x02000000, // ssub_6_ssub_7_dsub_5_dsub_7 4604}; 4605 4606static const uint32_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask[] = { 4607 0x00000000, 0x00000000, 0x00120000, 0x00000000, 4608 0x00000000, 0x00000000, 0x00000000, 0x00019000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 4609 0x00000000, 0x00000000, 0x00000000, 0x03c06000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 4610 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 4611 0x00000000, 0x00000000, 0x00000000, 0x03000000, // dsub_5_ssub_12_ssub_13_dsub_7 4612}; 4613 4614static const uint32_t DTriple_with_qsub_0_in_QPR_8SubClassMask[] = { 4615 0x00000000, 0x00000000, 0x000c0000, 0x00000000, 4616 0x00000000, 0x00000000, 0x00000000, 0x03c06000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 4617 0x00000000, 0x00000000, 0x00000000, 0x00018000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 4618 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4619 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4620}; 4621 4622static const uint32_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRSubClassMask[] = { 4623 0x00000000, 0x00000000, 0x00080000, 0x00000000, 4624 0x00000000, 0x00000000, 0x00000000, 0x03804000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 4625 0x00000000, 0x00000000, 0x00000000, 0x00010000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 4626 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4627 0x00000000, 0x00000000, 0x00000000, 0x02000000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4628}; 4629 4630static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask[] = { 4631 0x00000000, 0x00000000, 0x00100000, 0x00000000, 4632 0x00000000, 0x00000000, 0x00000000, 0x00018000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 4633 0x00000000, 0x00000000, 0x00000000, 0x03804000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 4634 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 4635 0x00000000, 0x00000000, 0x00000000, 0x02000000, // dsub_5_ssub_12_ssub_13_dsub_7 4636}; 4637 4638static const uint32_t DQuadSpcSubClassMask[] = { 4639 0x00000000, 0x00000000, 0x0fe00000, 0x00000000, 4640 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 4641 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 4642 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 4643 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_6_ssub_7_dsub_5_dsub_7 4644}; 4645 4646static const uint32_t DQuadSpc_with_ssub_0SubClassMask[] = { 4647 0x00000000, 0x00000000, 0x0fc00000, 0x00000000, 4648 0x00000000, 0x00000000, 0x00000000, 0x03fc0000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 4649 0x00000000, 0x00000000, 0x00000000, 0x03fc0000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 4650 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 4651 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_6_ssub_7_dsub_5_dsub_7 4652}; 4653 4654static const uint32_t DQuadSpc_with_ssub_4SubClassMask[] = { 4655 0x00000000, 0x00000000, 0x0f800000, 0x00000000, 4656 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 4657 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 4658 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 4659 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_6_ssub_7_dsub_5_dsub_7 4660}; 4661 4662static const uint32_t DQuadSpc_with_ssub_8SubClassMask[] = { 4663 0x00000000, 0x00000000, 0x0f000000, 0x00000000, 4664 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 4665 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 4666 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 4667 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_6_ssub_7_dsub_5_dsub_7 4668}; 4669 4670static const uint32_t DQuadSpc_with_dsub_0_in_DPR_8SubClassMask[] = { 4671 0x00000000, 0x00000000, 0x0e000000, 0x00000000, 4672 0x00000000, 0x00000000, 0x00000000, 0x03c00000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 4673 0x00000000, 0x00000000, 0x00000000, 0x03c00000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 4674 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 4675 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_6_ssub_7_dsub_5_dsub_7 4676}; 4677 4678static const uint32_t DQuadSpc_with_dsub_2_in_DPR_8SubClassMask[] = { 4679 0x00000000, 0x00000000, 0x0c000000, 0x00000000, 4680 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 4681 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 4682 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 4683 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_6_ssub_7_dsub_5_dsub_7 4684}; 4685 4686static const uint32_t DQuadSpc_with_dsub_4_in_DPR_8SubClassMask[] = { 4687 0x00000000, 0x00000000, 0x08000000, 0x00000000, 4688 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 4689 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 4690 0x00000000, 0x00000000, 0x00000000, 0x02000000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 4691 0x00000000, 0x00000000, 0x00000000, 0x02000000, // ssub_6_ssub_7_dsub_5_dsub_7 4692}; 4693 4694static const uint32_t DQuadSubClassMask[] = { 4695 0x00000000, 0x00000000, 0xf0000000, 0x0001ffff, 4696 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // qqsub_0 4697 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // qqsub_1 4698 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4699 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4700 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 4701}; 4702 4703static const uint32_t DQuad_with_ssub_0SubClassMask[] = { 4704 0x00000000, 0x00000000, 0x60000000, 0x0001fffe, 4705 0x00000000, 0x00000000, 0x00000000, 0x03fc0000, // qqsub_0 4706 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // qqsub_1 4707 0x00000000, 0x00000000, 0x00000000, 0x03fc0000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4708 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4709 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 4710}; 4711 4712static const uint32_t DQuad_with_ssub_2SubClassMask[] = { 4713 0x00000000, 0x00000000, 0x40000000, 0x0001ffde, 4714 0x00000000, 0x00000000, 0x00000000, 0x03fc0000, // qqsub_0 4715 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // qqsub_1 4716 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4717 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4718 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 4719}; 4720 4721static const uint32_t QQPRSubClassMask[] = { 4722 0x00000000, 0x00000000, 0x80000000, 0x00006090, 4723 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // qqsub_0 4724 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // qqsub_1 4725 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 4726}; 4727 4728static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = { 4729 0x00000000, 0x00000000, 0x00000000, 0x00019521, 4730 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4731 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4732}; 4733 4734static const uint32_t DQuad_with_ssub_4SubClassMask[] = { 4735 0x00000000, 0x00000000, 0x00000000, 0x0001ffce, 4736 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // qqsub_0 4737 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // qqsub_1 4738 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4739 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4740 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 4741}; 4742 4743static const uint32_t DQuad_with_ssub_6SubClassMask[] = { 4744 0x00000000, 0x00000000, 0x00000000, 0x0001fecc, 4745 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // qqsub_0 4746 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // qqsub_1 4747 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4748 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4749 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 4750}; 4751 4752static const uint32_t DQuad_with_dsub_0_in_DPR_8SubClassMask[] = { 4753 0x00000000, 0x00000000, 0x00000000, 0x0001fa48, 4754 0x00000000, 0x00000000, 0x00000000, 0x03c00000, // qqsub_0 4755 0x00000000, 0x00000000, 0x00000000, 0x03000000, // qqsub_1 4756 0x00000000, 0x00000000, 0x00000000, 0x03c00000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4757 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4758 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 4759}; 4760 4761static const uint32_t DQuad_with_qsub_0_in_MQPRSubClassMask[] = { 4762 0x00000000, 0x00000000, 0x00000000, 0x00006090, 4763 0x00000000, 0x00000000, 0x00000000, 0x03fc0000, // qqsub_0 4764 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // qqsub_1 4765 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 4766}; 4767 4768static const uint32_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = { 4769 0x00000000, 0x00000000, 0x00000000, 0x00019520, 4770 0x00000000, 0x00000000, 0x00000000, 0x03fc0000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4771 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4772}; 4773 4774static const uint32_t DQuad_with_dsub_1_in_DPR_8SubClassMask[] = { 4775 0x00000000, 0x00000000, 0x00000000, 0x0001ea40, 4776 0x00000000, 0x00000000, 0x00000000, 0x03c00000, // qqsub_0 4777 0x00000000, 0x00000000, 0x00000000, 0x03000000, // qqsub_1 4778 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4779 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4780 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 4781}; 4782 4783static const uint32_t DQuad_with_qsub_1_in_MQPRSubClassMask[] = { 4784 0x00000000, 0x00000000, 0x00000000, 0x00006080, 4785 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // qqsub_0 4786 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // qqsub_1 4787 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 4788}; 4789 4790static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask[] = { 4791 0x00000000, 0x00000000, 0x00000000, 0x00019500, 4792 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4793 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4794}; 4795 4796static const uint32_t DQuad_with_dsub_2_in_DPR_8SubClassMask[] = { 4797 0x00000000, 0x00000000, 0x00000000, 0x0001ca00, 4798 0x00000000, 0x00000000, 0x00000000, 0x03800000, // qqsub_0 4799 0x00000000, 0x00000000, 0x00000000, 0x02000000, // qqsub_1 4800 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4801 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4802 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 4803}; 4804 4805static const uint32_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask[] = { 4806 0x00000000, 0x00000000, 0x00000000, 0x00019400, 4807 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4808 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4809}; 4810 4811static const uint32_t DQuad_with_dsub_3_in_DPR_8SubClassMask[] = { 4812 0x00000000, 0x00000000, 0x00000000, 0x00014800, 4813 0x00000000, 0x00000000, 0x00000000, 0x03800000, // qqsub_0 4814 0x00000000, 0x00000000, 0x00000000, 0x02000000, // qqsub_1 4815 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4816 0x00000000, 0x00000000, 0x00000000, 0x02000000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4817 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 4818}; 4819 4820static const uint32_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask[] = { 4821 0x00000000, 0x00000000, 0x00000000, 0x00019000, 4822 0x00000000, 0x00000000, 0x00000000, 0x03c00000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4823 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4824}; 4825 4826static const uint32_t DQuad_with_qsub_0_in_QPR_8SubClassMask[] = { 4827 0x00000000, 0x00000000, 0x00000000, 0x00006000, 4828 0x00000000, 0x00000000, 0x00000000, 0x03c00000, // qqsub_0 4829 0x00000000, 0x00000000, 0x00000000, 0x03000000, // qqsub_1 4830 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 4831}; 4832 4833static const uint32_t DQuad_with_qsub_1_in_QPR_8SubClassMask[] = { 4834 0x00000000, 0x00000000, 0x00000000, 0x00004000, 4835 0x00000000, 0x00000000, 0x00000000, 0x03800000, // qqsub_0 4836 0x00000000, 0x00000000, 0x00000000, 0x02000000, // qqsub_1 4837 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 4838}; 4839 4840static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask[] = { 4841 0x00000000, 0x00000000, 0x00000000, 0x00018000, 4842 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4843 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4844}; 4845 4846static const uint32_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask[] = { 4847 0x00000000, 0x00000000, 0x00000000, 0x00010000, 4848 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 4849 0x00000000, 0x00000000, 0x00000000, 0x02000000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 4850}; 4851 4852static const uint32_t QQQQPRSubClassMask[] = { 4853 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, 4854}; 4855 4856static const uint32_t QQQQPR_with_ssub_0SubClassMask[] = { 4857 0x00000000, 0x00000000, 0x00000000, 0x03fc0000, 4858}; 4859 4860static const uint32_t QQQQPR_with_ssub_4SubClassMask[] = { 4861 0x00000000, 0x00000000, 0x00000000, 0x03f80000, 4862}; 4863 4864static const uint32_t QQQQPR_with_ssub_8SubClassMask[] = { 4865 0x00000000, 0x00000000, 0x00000000, 0x03f00000, 4866}; 4867 4868static const uint32_t QQQQPR_with_ssub_12SubClassMask[] = { 4869 0x00000000, 0x00000000, 0x00000000, 0x03e00000, 4870}; 4871 4872static const uint32_t QQQQPR_with_dsub_0_in_DPR_8SubClassMask[] = { 4873 0x00000000, 0x00000000, 0x00000000, 0x03c00000, 4874}; 4875 4876static const uint32_t QQQQPR_with_dsub_2_in_DPR_8SubClassMask[] = { 4877 0x00000000, 0x00000000, 0x00000000, 0x03800000, 4878}; 4879 4880static const uint32_t QQQQPR_with_dsub_4_in_DPR_8SubClassMask[] = { 4881 0x00000000, 0x00000000, 0x00000000, 0x03000000, 4882}; 4883 4884static const uint32_t QQQQPR_with_dsub_6_in_DPR_8SubClassMask[] = { 4885 0x00000000, 0x00000000, 0x00000000, 0x02000000, 4886}; 4887 4888static const uint16_t SuperRegIdxSeqs[] = { 4889 /* 0 */ 1, 2, 3, 4, 5, 6, 7, 8, 0, 4890 /* 9 */ 9, 0, 4891 /* 11 */ 9, 10, 0, 4892 /* 14 */ 1, 2, 3, 4, 5, 6, 7, 8, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 0, 4893 /* 39 */ 13, 14, 15, 16, 37, 0, 4894 /* 45 */ 38, 40, 45, 48, 0, 4895 /* 50 */ 42, 50, 0, 4896 /* 53 */ 34, 36, 44, 52, 0, 4897 /* 58 */ 33, 35, 43, 46, 51, 53, 0, 4898 /* 65 */ 34, 36, 47, 54, 0, 4899 /* 70 */ 34, 36, 44, 47, 52, 54, 0, 4900 /* 77 */ 13, 14, 15, 16, 37, 49, 55, 0, 4901 /* 85 */ 11, 12, 56, 0, 4902 /* 89 */ 11, 12, 42, 50, 56, 0, 4903}; 4904 4905static const TargetRegisterClass *const SPRSuperclasses[] = { 4906 &ARM::HPRRegClass, 4907 &ARM::FPWithVPRRegClass, 4908 nullptr 4909}; 4910 4911static const TargetRegisterClass *const FPWithVPR_with_ssub_0Superclasses[] = { 4912 &ARM::FPWithVPRRegClass, 4913 nullptr 4914}; 4915 4916static const TargetRegisterClass *const SPR_8Superclasses[] = { 4917 &ARM::HPRRegClass, 4918 &ARM::FPWithVPRRegClass, 4919 &ARM::SPRRegClass, 4920 nullptr 4921}; 4922 4923static const TargetRegisterClass *const GPRnopcSuperclasses[] = { 4924 &ARM::GPRRegClass, 4925 &ARM::GPRwithAPSRRegClass, 4926 &ARM::GPRwithZRRegClass, 4927 nullptr 4928}; 4929 4930static const TargetRegisterClass *const GPRwithZRnospSuperclasses[] = { 4931 &ARM::GPRwithZRRegClass, 4932 nullptr 4933}; 4934 4935static const TargetRegisterClass *const rGPRSuperclasses[] = { 4936 &ARM::GPRRegClass, 4937 &ARM::GPRwithAPSRRegClass, 4938 &ARM::GPRwithZRRegClass, 4939 &ARM::GPRnopcRegClass, 4940 &ARM::GPRwithAPSRnospRegClass, 4941 &ARM::GPRwithZRnospRegClass, 4942 nullptr 4943}; 4944 4945static const TargetRegisterClass *const tGPRwithpcSuperclasses[] = { 4946 &ARM::GPRRegClass, 4947 nullptr 4948}; 4949 4950static const TargetRegisterClass *const FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Superclasses[] = { 4951 &ARM::FPWithVPRRegClass, 4952 &ARM::FPWithVPR_with_ssub_0RegClass, 4953 nullptr 4954}; 4955 4956static const TargetRegisterClass *const hGPRSuperclasses[] = { 4957 &ARM::GPRRegClass, 4958 nullptr 4959}; 4960 4961static const TargetRegisterClass *const tGPRSuperclasses[] = { 4962 &ARM::GPRRegClass, 4963 &ARM::GPRwithAPSRRegClass, 4964 &ARM::GPRwithZRRegClass, 4965 &ARM::GPRnopcRegClass, 4966 &ARM::GPRwithAPSRnospRegClass, 4967 &ARM::GPRwithZRnospRegClass, 4968 &ARM::rGPRRegClass, 4969 &ARM::tGPRwithpcRegClass, 4970 nullptr 4971}; 4972 4973static const TargetRegisterClass *const tGPREvenSuperclasses[] = { 4974 &ARM::GPRRegClass, 4975 &ARM::GPRwithAPSRRegClass, 4976 &ARM::GPRwithZRRegClass, 4977 &ARM::GPRnopcRegClass, 4978 &ARM::GPRwithAPSRnospRegClass, 4979 &ARM::GPRwithZRnospRegClass, 4980 &ARM::rGPRRegClass, 4981 nullptr 4982}; 4983 4984static const TargetRegisterClass *const GPRnopc_and_hGPRSuperclasses[] = { 4985 &ARM::GPRRegClass, 4986 &ARM::GPRwithAPSRRegClass, 4987 &ARM::GPRwithZRRegClass, 4988 &ARM::GPRnopcRegClass, 4989 &ARM::hGPRRegClass, 4990 nullptr 4991}; 4992 4993static const TargetRegisterClass *const GPRwithAPSRnosp_and_hGPRSuperclasses[] = { 4994 &ARM::GPRRegClass, 4995 &ARM::GPRwithAPSRRegClass, 4996 &ARM::GPRwithZRRegClass, 4997 &ARM::GPRnopcRegClass, 4998 &ARM::GPRwithAPSRnospRegClass, 4999 &ARM::GPRwithZRnospRegClass, 5000 &ARM::rGPRRegClass, 5001 &ARM::hGPRRegClass, 5002 &ARM::GPRnopc_and_hGPRRegClass, 5003 nullptr 5004}; 5005 5006static const TargetRegisterClass *const tGPROddSuperclasses[] = { 5007 &ARM::GPRRegClass, 5008 &ARM::GPRwithAPSRRegClass, 5009 &ARM::GPRwithZRRegClass, 5010 &ARM::GPRnopcRegClass, 5011 &ARM::GPRwithAPSRnospRegClass, 5012 &ARM::GPRwithZRnospRegClass, 5013 &ARM::rGPRRegClass, 5014 nullptr 5015}; 5016 5017static const TargetRegisterClass *const tcGPRSuperclasses[] = { 5018 &ARM::GPRRegClass, 5019 &ARM::GPRwithAPSRRegClass, 5020 &ARM::GPRwithZRRegClass, 5021 &ARM::GPRnopcRegClass, 5022 &ARM::GPRwithAPSRnospRegClass, 5023 &ARM::GPRwithZRnospRegClass, 5024 &ARM::rGPRRegClass, 5025 nullptr 5026}; 5027 5028static const TargetRegisterClass *const hGPR_and_tGPREvenSuperclasses[] = { 5029 &ARM::GPRRegClass, 5030 &ARM::GPRwithAPSRRegClass, 5031 &ARM::GPRwithZRRegClass, 5032 &ARM::GPRnopcRegClass, 5033 &ARM::GPRwithAPSRnospRegClass, 5034 &ARM::GPRwithZRnospRegClass, 5035 &ARM::rGPRRegClass, 5036 &ARM::hGPRRegClass, 5037 &ARM::tGPREvenRegClass, 5038 &ARM::GPRnopc_and_hGPRRegClass, 5039 &ARM::GPRwithAPSRnosp_and_hGPRRegClass, 5040 nullptr 5041}; 5042 5043static const TargetRegisterClass *const tGPR_and_tGPREvenSuperclasses[] = { 5044 &ARM::GPRRegClass, 5045 &ARM::GPRwithAPSRRegClass, 5046 &ARM::GPRwithZRRegClass, 5047 &ARM::GPRnopcRegClass, 5048 &ARM::GPRwithAPSRnospRegClass, 5049 &ARM::GPRwithZRnospRegClass, 5050 &ARM::rGPRRegClass, 5051 &ARM::tGPRwithpcRegClass, 5052 &ARM::tGPRRegClass, 5053 &ARM::tGPREvenRegClass, 5054 nullptr 5055}; 5056 5057static const TargetRegisterClass *const tGPR_and_tGPROddSuperclasses[] = { 5058 &ARM::GPRRegClass, 5059 &ARM::GPRwithAPSRRegClass, 5060 &ARM::GPRwithZRRegClass, 5061 &ARM::GPRnopcRegClass, 5062 &ARM::GPRwithAPSRnospRegClass, 5063 &ARM::GPRwithZRnospRegClass, 5064 &ARM::rGPRRegClass, 5065 &ARM::tGPRwithpcRegClass, 5066 &ARM::tGPRRegClass, 5067 &ARM::tGPROddRegClass, 5068 nullptr 5069}; 5070 5071static const TargetRegisterClass *const tGPR_and_tcGPRSuperclasses[] = { 5072 &ARM::GPRRegClass, 5073 &ARM::GPRwithAPSRRegClass, 5074 &ARM::GPRwithZRRegClass, 5075 &ARM::GPRnopcRegClass, 5076 &ARM::GPRwithAPSRnospRegClass, 5077 &ARM::GPRwithZRnospRegClass, 5078 &ARM::rGPRRegClass, 5079 &ARM::tGPRwithpcRegClass, 5080 &ARM::tGPRRegClass, 5081 &ARM::tcGPRRegClass, 5082 nullptr 5083}; 5084 5085static const TargetRegisterClass *const tGPREven_and_tcGPRSuperclasses[] = { 5086 &ARM::GPRRegClass, 5087 &ARM::GPRwithAPSRRegClass, 5088 &ARM::GPRwithZRRegClass, 5089 &ARM::GPRnopcRegClass, 5090 &ARM::GPRwithAPSRnospRegClass, 5091 &ARM::GPRwithZRnospRegClass, 5092 &ARM::rGPRRegClass, 5093 &ARM::tGPREvenRegClass, 5094 &ARM::tcGPRRegClass, 5095 nullptr 5096}; 5097 5098static const TargetRegisterClass *const hGPR_and_tGPROddSuperclasses[] = { 5099 &ARM::GPRRegClass, 5100 &ARM::GPRwithAPSRRegClass, 5101 &ARM::GPRwithZRRegClass, 5102 &ARM::GPRnopcRegClass, 5103 &ARM::GPRwithAPSRnospRegClass, 5104 &ARM::GPRwithZRnospRegClass, 5105 &ARM::rGPRRegClass, 5106 &ARM::hGPRRegClass, 5107 &ARM::GPRnopc_and_hGPRRegClass, 5108 &ARM::GPRwithAPSRnosp_and_hGPRRegClass, 5109 &ARM::tGPROddRegClass, 5110 nullptr 5111}; 5112 5113static const TargetRegisterClass *const tGPREven_and_tGPR_and_tcGPRSuperclasses[] = { 5114 &ARM::GPRRegClass, 5115 &ARM::GPRwithAPSRRegClass, 5116 &ARM::GPRwithZRRegClass, 5117 &ARM::GPRnopcRegClass, 5118 &ARM::GPRwithAPSRnospRegClass, 5119 &ARM::GPRwithZRnospRegClass, 5120 &ARM::rGPRRegClass, 5121 &ARM::tGPRwithpcRegClass, 5122 &ARM::tGPRRegClass, 5123 &ARM::tGPREvenRegClass, 5124 &ARM::tcGPRRegClass, 5125 &ARM::tGPR_and_tGPREvenRegClass, 5126 &ARM::tGPR_and_tcGPRRegClass, 5127 &ARM::tGPREven_and_tcGPRRegClass, 5128 nullptr 5129}; 5130 5131static const TargetRegisterClass *const tGPROdd_and_tcGPRSuperclasses[] = { 5132 &ARM::GPRRegClass, 5133 &ARM::GPRwithAPSRRegClass, 5134 &ARM::GPRwithZRRegClass, 5135 &ARM::GPRnopcRegClass, 5136 &ARM::GPRwithAPSRnospRegClass, 5137 &ARM::GPRwithZRnospRegClass, 5138 &ARM::rGPRRegClass, 5139 &ARM::tGPRwithpcRegClass, 5140 &ARM::tGPRRegClass, 5141 &ARM::tGPROddRegClass, 5142 &ARM::tcGPRRegClass, 5143 &ARM::tGPR_and_tGPROddRegClass, 5144 &ARM::tGPR_and_tcGPRRegClass, 5145 nullptr 5146}; 5147 5148static const TargetRegisterClass *const GPRlrSuperclasses[] = { 5149 &ARM::GPRRegClass, 5150 &ARM::GPRwithAPSRRegClass, 5151 &ARM::GPRwithZRRegClass, 5152 &ARM::GPRnopcRegClass, 5153 &ARM::GPRwithAPSRnospRegClass, 5154 &ARM::GPRwithZRnospRegClass, 5155 &ARM::rGPRRegClass, 5156 &ARM::hGPRRegClass, 5157 &ARM::tGPREvenRegClass, 5158 &ARM::GPRnopc_and_hGPRRegClass, 5159 &ARM::GPRwithAPSRnosp_and_hGPRRegClass, 5160 &ARM::hGPR_and_tGPREvenRegClass, 5161 nullptr 5162}; 5163 5164static const TargetRegisterClass *const GPRspSuperclasses[] = { 5165 &ARM::GPRRegClass, 5166 &ARM::GPRwithAPSRRegClass, 5167 &ARM::GPRwithZRRegClass, 5168 &ARM::GPRnopcRegClass, 5169 &ARM::hGPRRegClass, 5170 &ARM::GPRnopc_and_hGPRRegClass, 5171 nullptr 5172}; 5173 5174static const TargetRegisterClass *const VCCRSuperclasses[] = { 5175 &ARM::FPWithVPRRegClass, 5176 nullptr 5177}; 5178 5179static const TargetRegisterClass *const hGPR_and_tGPRwithpcSuperclasses[] = { 5180 &ARM::GPRRegClass, 5181 &ARM::tGPRwithpcRegClass, 5182 &ARM::hGPRRegClass, 5183 nullptr 5184}; 5185 5186static const TargetRegisterClass *const hGPR_and_tcGPRSuperclasses[] = { 5187 &ARM::GPRRegClass, 5188 &ARM::GPRwithAPSRRegClass, 5189 &ARM::GPRwithZRRegClass, 5190 &ARM::GPRnopcRegClass, 5191 &ARM::GPRwithAPSRnospRegClass, 5192 &ARM::GPRwithZRnospRegClass, 5193 &ARM::rGPRRegClass, 5194 &ARM::hGPRRegClass, 5195 &ARM::tGPREvenRegClass, 5196 &ARM::GPRnopc_and_hGPRRegClass, 5197 &ARM::GPRwithAPSRnosp_and_hGPRRegClass, 5198 &ARM::tcGPRRegClass, 5199 &ARM::hGPR_and_tGPREvenRegClass, 5200 &ARM::tGPREven_and_tcGPRRegClass, 5201 nullptr 5202}; 5203 5204static const TargetRegisterClass *const DPRSuperclasses[] = { 5205 &ARM::FPWithVPRRegClass, 5206 nullptr 5207}; 5208 5209static const TargetRegisterClass *const DPR_VFP2Superclasses[] = { 5210 &ARM::FPWithVPRRegClass, 5211 &ARM::FPWithVPR_with_ssub_0RegClass, 5212 &ARM::DPRRegClass, 5213 nullptr 5214}; 5215 5216static const TargetRegisterClass *const DPR_8Superclasses[] = { 5217 &ARM::FPWithVPRRegClass, 5218 &ARM::FPWithVPR_with_ssub_0RegClass, 5219 &ARM::FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClass, 5220 &ARM::DPRRegClass, 5221 &ARM::DPR_VFP2RegClass, 5222 nullptr 5223}; 5224 5225static const TargetRegisterClass *const GPRPairnospSuperclasses[] = { 5226 &ARM::GPRPairRegClass, 5227 nullptr 5228}; 5229 5230static const TargetRegisterClass *const GPRPair_with_gsub_0_in_tGPRSuperclasses[] = { 5231 &ARM::GPRPairRegClass, 5232 &ARM::GPRPairnospRegClass, 5233 nullptr 5234}; 5235 5236static const TargetRegisterClass *const GPRPair_with_gsub_0_in_hGPRSuperclasses[] = { 5237 &ARM::GPRPairRegClass, 5238 nullptr 5239}; 5240 5241static const TargetRegisterClass *const GPRPair_with_gsub_0_in_tcGPRSuperclasses[] = { 5242 &ARM::GPRPairRegClass, 5243 nullptr 5244}; 5245 5246static const TargetRegisterClass *const GPRPair_with_gsub_1_in_tcGPRSuperclasses[] = { 5247 &ARM::GPRPairRegClass, 5248 &ARM::GPRPairnospRegClass, 5249 &ARM::GPRPair_with_gsub_0_in_tGPRRegClass, 5250 &ARM::GPRPair_with_gsub_0_in_tcGPRRegClass, 5251 nullptr 5252}; 5253 5254static const TargetRegisterClass *const GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRSuperclasses[] = { 5255 &ARM::GPRPairRegClass, 5256 &ARM::GPRPairnospRegClass, 5257 &ARM::GPRPair_with_gsub_0_in_hGPRRegClass, 5258 nullptr 5259}; 5260 5261static const TargetRegisterClass *const GPRPair_with_gsub_1_in_GPRspSuperclasses[] = { 5262 &ARM::GPRPairRegClass, 5263 &ARM::GPRPair_with_gsub_0_in_hGPRRegClass, 5264 &ARM::GPRPair_with_gsub_0_in_tcGPRRegClass, 5265 nullptr 5266}; 5267 5268static const TargetRegisterClass *const DPairSpc_with_ssub_0Superclasses[] = { 5269 &ARM::DPairSpcRegClass, 5270 nullptr 5271}; 5272 5273static const TargetRegisterClass *const DPairSpc_with_ssub_4Superclasses[] = { 5274 &ARM::DPairSpcRegClass, 5275 &ARM::DPairSpc_with_ssub_0RegClass, 5276 nullptr 5277}; 5278 5279static const TargetRegisterClass *const DPairSpc_with_dsub_0_in_DPR_8Superclasses[] = { 5280 &ARM::DPairSpcRegClass, 5281 &ARM::DPairSpc_with_ssub_0RegClass, 5282 &ARM::DPairSpc_with_ssub_4RegClass, 5283 nullptr 5284}; 5285 5286static const TargetRegisterClass *const DPairSpc_with_dsub_2_in_DPR_8Superclasses[] = { 5287 &ARM::DPairSpcRegClass, 5288 &ARM::DPairSpc_with_ssub_0RegClass, 5289 &ARM::DPairSpc_with_ssub_4RegClass, 5290 &ARM::DPairSpc_with_dsub_0_in_DPR_8RegClass, 5291 nullptr 5292}; 5293 5294static const TargetRegisterClass *const DPair_with_ssub_0Superclasses[] = { 5295 &ARM::DPairRegClass, 5296 nullptr 5297}; 5298 5299static const TargetRegisterClass *const QPRSuperclasses[] = { 5300 &ARM::DPairRegClass, 5301 nullptr 5302}; 5303 5304static const TargetRegisterClass *const DPair_with_ssub_2Superclasses[] = { 5305 &ARM::DPairRegClass, 5306 &ARM::DPair_with_ssub_0RegClass, 5307 nullptr 5308}; 5309 5310static const TargetRegisterClass *const DPair_with_dsub_0_in_DPR_8Superclasses[] = { 5311 &ARM::DPairRegClass, 5312 &ARM::DPair_with_ssub_0RegClass, 5313 &ARM::DPair_with_ssub_2RegClass, 5314 nullptr 5315}; 5316 5317static const TargetRegisterClass *const MQPRSuperclasses[] = { 5318 &ARM::DPairRegClass, 5319 &ARM::DPair_with_ssub_0RegClass, 5320 &ARM::QPRRegClass, 5321 &ARM::DPair_with_ssub_2RegClass, 5322 &ARM::QPR_VFP2RegClass, 5323 nullptr 5324}; 5325 5326static const TargetRegisterClass *const QPR_VFP2Superclasses[] = { 5327 &ARM::DPairRegClass, 5328 &ARM::DPair_with_ssub_0RegClass, 5329 &ARM::QPRRegClass, 5330 &ARM::DPair_with_ssub_2RegClass, 5331 &ARM::MQPRRegClass, 5332 nullptr 5333}; 5334 5335static const TargetRegisterClass *const DPair_with_dsub_1_in_DPR_8Superclasses[] = { 5336 &ARM::DPairRegClass, 5337 &ARM::DPair_with_ssub_0RegClass, 5338 &ARM::DPair_with_ssub_2RegClass, 5339 &ARM::DPair_with_dsub_0_in_DPR_8RegClass, 5340 nullptr 5341}; 5342 5343static const TargetRegisterClass *const QPR_8Superclasses[] = { 5344 &ARM::DPairRegClass, 5345 &ARM::DPair_with_ssub_0RegClass, 5346 &ARM::QPRRegClass, 5347 &ARM::DPair_with_ssub_2RegClass, 5348 &ARM::DPair_with_dsub_0_in_DPR_8RegClass, 5349 &ARM::MQPRRegClass, 5350 &ARM::QPR_VFP2RegClass, 5351 &ARM::DPair_with_dsub_1_in_DPR_8RegClass, 5352 nullptr 5353}; 5354 5355static const TargetRegisterClass *const DTripleSpc_with_ssub_0Superclasses[] = { 5356 &ARM::DTripleSpcRegClass, 5357 nullptr 5358}; 5359 5360static const TargetRegisterClass *const DTriple_with_ssub_0Superclasses[] = { 5361 &ARM::DTripleRegClass, 5362 nullptr 5363}; 5364 5365static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPRSuperclasses[] = { 5366 &ARM::DTripleRegClass, 5367 nullptr 5368}; 5369 5370static const TargetRegisterClass *const DTriple_with_ssub_2Superclasses[] = { 5371 &ARM::DTripleRegClass, 5372 &ARM::DTriple_with_ssub_0RegClass, 5373 nullptr 5374}; 5375 5376static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = { 5377 &ARM::DTripleRegClass, 5378 nullptr 5379}; 5380 5381static const TargetRegisterClass *const DTripleSpc_with_ssub_4Superclasses[] = { 5382 &ARM::DTripleSpcRegClass, 5383 &ARM::DTripleSpc_with_ssub_0RegClass, 5384 nullptr 5385}; 5386 5387static const TargetRegisterClass *const DTriple_with_ssub_4Superclasses[] = { 5388 &ARM::DTripleRegClass, 5389 &ARM::DTriple_with_ssub_0RegClass, 5390 &ARM::DTriple_with_ssub_2RegClass, 5391 nullptr 5392}; 5393 5394static const TargetRegisterClass *const DTripleSpc_with_ssub_8Superclasses[] = { 5395 &ARM::DTripleSpcRegClass, 5396 &ARM::DTripleSpc_with_ssub_0RegClass, 5397 &ARM::DTripleSpc_with_ssub_4RegClass, 5398 nullptr 5399}; 5400 5401static const TargetRegisterClass *const DTripleSpc_with_dsub_0_in_DPR_8Superclasses[] = { 5402 &ARM::DTripleSpcRegClass, 5403 &ARM::DTripleSpc_with_ssub_0RegClass, 5404 &ARM::DTripleSpc_with_ssub_4RegClass, 5405 &ARM::DTripleSpc_with_ssub_8RegClass, 5406 nullptr 5407}; 5408 5409static const TargetRegisterClass *const DTriple_with_dsub_0_in_DPR_8Superclasses[] = { 5410 &ARM::DTripleRegClass, 5411 &ARM::DTriple_with_ssub_0RegClass, 5412 &ARM::DTriple_with_ssub_2RegClass, 5413 &ARM::DTriple_with_ssub_4RegClass, 5414 nullptr 5415}; 5416 5417static const TargetRegisterClass *const DTriple_with_qsub_0_in_MQPRSuperclasses[] = { 5418 &ARM::DTripleRegClass, 5419 &ARM::DTriple_with_ssub_0RegClass, 5420 &ARM::DTriple_with_qsub_0_in_QPRRegClass, 5421 &ARM::DTriple_with_ssub_2RegClass, 5422 nullptr 5423}; 5424 5425static const TargetRegisterClass *const DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = { 5426 &ARM::DTripleRegClass, 5427 &ARM::DTriple_with_ssub_0RegClass, 5428 &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, 5429 nullptr 5430}; 5431 5432static const TargetRegisterClass *const DTriple_with_dsub_1_in_DPR_8Superclasses[] = { 5433 &ARM::DTripleRegClass, 5434 &ARM::DTriple_with_ssub_0RegClass, 5435 &ARM::DTriple_with_ssub_2RegClass, 5436 &ARM::DTriple_with_ssub_4RegClass, 5437 &ARM::DTriple_with_dsub_0_in_DPR_8RegClass, 5438 nullptr 5439}; 5440 5441static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses[] = { 5442 &ARM::DTripleRegClass, 5443 &ARM::DTriple_with_ssub_0RegClass, 5444 &ARM::DTriple_with_ssub_2RegClass, 5445 &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, 5446 &ARM::DTriple_with_ssub_4RegClass, 5447 &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, 5448 nullptr 5449}; 5450 5451static const TargetRegisterClass *const DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRSuperclasses[] = { 5452 &ARM::DTripleRegClass, 5453 &ARM::DTriple_with_ssub_0RegClass, 5454 &ARM::DTriple_with_qsub_0_in_QPRRegClass, 5455 &ARM::DTriple_with_ssub_2RegClass, 5456 &ARM::DTriple_with_ssub_4RegClass, 5457 &ARM::DTriple_with_qsub_0_in_MQPRRegClass, 5458 nullptr 5459}; 5460 5461static const TargetRegisterClass *const DTripleSpc_with_dsub_2_in_DPR_8Superclasses[] = { 5462 &ARM::DTripleSpcRegClass, 5463 &ARM::DTripleSpc_with_ssub_0RegClass, 5464 &ARM::DTripleSpc_with_ssub_4RegClass, 5465 &ARM::DTripleSpc_with_ssub_8RegClass, 5466 &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass, 5467 nullptr 5468}; 5469 5470static const TargetRegisterClass *const DTriple_with_dsub_2_in_DPR_8Superclasses[] = { 5471 &ARM::DTripleRegClass, 5472 &ARM::DTriple_with_ssub_0RegClass, 5473 &ARM::DTriple_with_ssub_2RegClass, 5474 &ARM::DTriple_with_ssub_4RegClass, 5475 &ARM::DTriple_with_dsub_0_in_DPR_8RegClass, 5476 &ARM::DTriple_with_dsub_1_in_DPR_8RegClass, 5477 nullptr 5478}; 5479 5480static const TargetRegisterClass *const DTripleSpc_with_dsub_4_in_DPR_8Superclasses[] = { 5481 &ARM::DTripleSpcRegClass, 5482 &ARM::DTripleSpc_with_ssub_0RegClass, 5483 &ARM::DTripleSpc_with_ssub_4RegClass, 5484 &ARM::DTripleSpc_with_ssub_8RegClass, 5485 &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass, 5486 &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass, 5487 nullptr 5488}; 5489 5490static const TargetRegisterClass *const DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses[] = { 5491 &ARM::DTripleRegClass, 5492 &ARM::DTriple_with_ssub_0RegClass, 5493 &ARM::DTriple_with_ssub_2RegClass, 5494 &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, 5495 &ARM::DTriple_with_ssub_4RegClass, 5496 &ARM::DTriple_with_dsub_0_in_DPR_8RegClass, 5497 &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, 5498 &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, 5499 nullptr 5500}; 5501 5502static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPR_8Superclasses[] = { 5503 &ARM::DTripleRegClass, 5504 &ARM::DTriple_with_ssub_0RegClass, 5505 &ARM::DTriple_with_qsub_0_in_QPRRegClass, 5506 &ARM::DTriple_with_ssub_2RegClass, 5507 &ARM::DTriple_with_ssub_4RegClass, 5508 &ARM::DTriple_with_dsub_0_in_DPR_8RegClass, 5509 &ARM::DTriple_with_qsub_0_in_MQPRRegClass, 5510 &ARM::DTriple_with_dsub_1_in_DPR_8RegClass, 5511 &ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClass, 5512 nullptr 5513}; 5514 5515static const TargetRegisterClass *const DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRSuperclasses[] = { 5516 &ARM::DTripleRegClass, 5517 &ARM::DTriple_with_ssub_0RegClass, 5518 &ARM::DTriple_with_qsub_0_in_QPRRegClass, 5519 &ARM::DTriple_with_ssub_2RegClass, 5520 &ARM::DTriple_with_ssub_4RegClass, 5521 &ARM::DTriple_with_dsub_0_in_DPR_8RegClass, 5522 &ARM::DTriple_with_qsub_0_in_MQPRRegClass, 5523 &ARM::DTriple_with_dsub_1_in_DPR_8RegClass, 5524 &ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClass, 5525 &ARM::DTriple_with_dsub_2_in_DPR_8RegClass, 5526 &ARM::DTriple_with_qsub_0_in_QPR_8RegClass, 5527 nullptr 5528}; 5529 5530static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses[] = { 5531 &ARM::DTripleRegClass, 5532 &ARM::DTriple_with_ssub_0RegClass, 5533 &ARM::DTriple_with_ssub_2RegClass, 5534 &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, 5535 &ARM::DTriple_with_ssub_4RegClass, 5536 &ARM::DTriple_with_dsub_0_in_DPR_8RegClass, 5537 &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, 5538 &ARM::DTriple_with_dsub_1_in_DPR_8RegClass, 5539 &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, 5540 &ARM::DTriple_with_dsub_2_in_DPR_8RegClass, 5541 &ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, 5542 nullptr 5543}; 5544 5545static const TargetRegisterClass *const DQuadSpcSuperclasses[] = { 5546 &ARM::DTripleSpcRegClass, 5547 nullptr 5548}; 5549 5550static const TargetRegisterClass *const DQuadSpc_with_ssub_0Superclasses[] = { 5551 &ARM::DTripleSpcRegClass, 5552 &ARM::DTripleSpc_with_ssub_0RegClass, 5553 &ARM::DQuadSpcRegClass, 5554 nullptr 5555}; 5556 5557static const TargetRegisterClass *const DQuadSpc_with_ssub_4Superclasses[] = { 5558 &ARM::DTripleSpcRegClass, 5559 &ARM::DTripleSpc_with_ssub_0RegClass, 5560 &ARM::DTripleSpc_with_ssub_4RegClass, 5561 &ARM::DQuadSpcRegClass, 5562 &ARM::DQuadSpc_with_ssub_0RegClass, 5563 nullptr 5564}; 5565 5566static const TargetRegisterClass *const DQuadSpc_with_ssub_8Superclasses[] = { 5567 &ARM::DTripleSpcRegClass, 5568 &ARM::DTripleSpc_with_ssub_0RegClass, 5569 &ARM::DTripleSpc_with_ssub_4RegClass, 5570 &ARM::DTripleSpc_with_ssub_8RegClass, 5571 &ARM::DQuadSpcRegClass, 5572 &ARM::DQuadSpc_with_ssub_0RegClass, 5573 &ARM::DQuadSpc_with_ssub_4RegClass, 5574 nullptr 5575}; 5576 5577static const TargetRegisterClass *const DQuadSpc_with_dsub_0_in_DPR_8Superclasses[] = { 5578 &ARM::DTripleSpcRegClass, 5579 &ARM::DTripleSpc_with_ssub_0RegClass, 5580 &ARM::DTripleSpc_with_ssub_4RegClass, 5581 &ARM::DTripleSpc_with_ssub_8RegClass, 5582 &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass, 5583 &ARM::DQuadSpcRegClass, 5584 &ARM::DQuadSpc_with_ssub_0RegClass, 5585 &ARM::DQuadSpc_with_ssub_4RegClass, 5586 &ARM::DQuadSpc_with_ssub_8RegClass, 5587 nullptr 5588}; 5589 5590static const TargetRegisterClass *const DQuadSpc_with_dsub_2_in_DPR_8Superclasses[] = { 5591 &ARM::DTripleSpcRegClass, 5592 &ARM::DTripleSpc_with_ssub_0RegClass, 5593 &ARM::DTripleSpc_with_ssub_4RegClass, 5594 &ARM::DTripleSpc_with_ssub_8RegClass, 5595 &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass, 5596 &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass, 5597 &ARM::DQuadSpcRegClass, 5598 &ARM::DQuadSpc_with_ssub_0RegClass, 5599 &ARM::DQuadSpc_with_ssub_4RegClass, 5600 &ARM::DQuadSpc_with_ssub_8RegClass, 5601 &ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClass, 5602 nullptr 5603}; 5604 5605static const TargetRegisterClass *const DQuadSpc_with_dsub_4_in_DPR_8Superclasses[] = { 5606 &ARM::DTripleSpcRegClass, 5607 &ARM::DTripleSpc_with_ssub_0RegClass, 5608 &ARM::DTripleSpc_with_ssub_4RegClass, 5609 &ARM::DTripleSpc_with_ssub_8RegClass, 5610 &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass, 5611 &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass, 5612 &ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClass, 5613 &ARM::DQuadSpcRegClass, 5614 &ARM::DQuadSpc_with_ssub_0RegClass, 5615 &ARM::DQuadSpc_with_ssub_4RegClass, 5616 &ARM::DQuadSpc_with_ssub_8RegClass, 5617 &ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClass, 5618 &ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClass, 5619 nullptr 5620}; 5621 5622static const TargetRegisterClass *const DQuad_with_ssub_0Superclasses[] = { 5623 &ARM::DQuadRegClass, 5624 nullptr 5625}; 5626 5627static const TargetRegisterClass *const DQuad_with_ssub_2Superclasses[] = { 5628 &ARM::DQuadRegClass, 5629 &ARM::DQuad_with_ssub_0RegClass, 5630 nullptr 5631}; 5632 5633static const TargetRegisterClass *const QQPRSuperclasses[] = { 5634 &ARM::DQuadRegClass, 5635 nullptr 5636}; 5637 5638static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = { 5639 &ARM::DQuadRegClass, 5640 nullptr 5641}; 5642 5643static const TargetRegisterClass *const DQuad_with_ssub_4Superclasses[] = { 5644 &ARM::DQuadRegClass, 5645 &ARM::DQuad_with_ssub_0RegClass, 5646 &ARM::DQuad_with_ssub_2RegClass, 5647 nullptr 5648}; 5649 5650static const TargetRegisterClass *const DQuad_with_ssub_6Superclasses[] = { 5651 &ARM::DQuadRegClass, 5652 &ARM::DQuad_with_ssub_0RegClass, 5653 &ARM::DQuad_with_ssub_2RegClass, 5654 &ARM::DQuad_with_ssub_4RegClass, 5655 nullptr 5656}; 5657 5658static const TargetRegisterClass *const DQuad_with_dsub_0_in_DPR_8Superclasses[] = { 5659 &ARM::DQuadRegClass, 5660 &ARM::DQuad_with_ssub_0RegClass, 5661 &ARM::DQuad_with_ssub_2RegClass, 5662 &ARM::DQuad_with_ssub_4RegClass, 5663 &ARM::DQuad_with_ssub_6RegClass, 5664 nullptr 5665}; 5666 5667static const TargetRegisterClass *const DQuad_with_qsub_0_in_MQPRSuperclasses[] = { 5668 &ARM::DQuadRegClass, 5669 &ARM::DQuad_with_ssub_0RegClass, 5670 &ARM::DQuad_with_ssub_2RegClass, 5671 &ARM::QQPRRegClass, 5672 nullptr 5673}; 5674 5675static const TargetRegisterClass *const DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = { 5676 &ARM::DQuadRegClass, 5677 &ARM::DQuad_with_ssub_0RegClass, 5678 &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, 5679 nullptr 5680}; 5681 5682static const TargetRegisterClass *const DQuad_with_dsub_1_in_DPR_8Superclasses[] = { 5683 &ARM::DQuadRegClass, 5684 &ARM::DQuad_with_ssub_0RegClass, 5685 &ARM::DQuad_with_ssub_2RegClass, 5686 &ARM::DQuad_with_ssub_4RegClass, 5687 &ARM::DQuad_with_ssub_6RegClass, 5688 &ARM::DQuad_with_dsub_0_in_DPR_8RegClass, 5689 nullptr 5690}; 5691 5692static const TargetRegisterClass *const DQuad_with_qsub_1_in_MQPRSuperclasses[] = { 5693 &ARM::DQuadRegClass, 5694 &ARM::DQuad_with_ssub_0RegClass, 5695 &ARM::DQuad_with_ssub_2RegClass, 5696 &ARM::QQPRRegClass, 5697 &ARM::DQuad_with_ssub_4RegClass, 5698 &ARM::DQuad_with_ssub_6RegClass, 5699 &ARM::DQuad_with_qsub_0_in_MQPRRegClass, 5700 nullptr 5701}; 5702 5703static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses[] = { 5704 &ARM::DQuadRegClass, 5705 &ARM::DQuad_with_ssub_0RegClass, 5706 &ARM::DQuad_with_ssub_2RegClass, 5707 &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, 5708 &ARM::DQuad_with_ssub_4RegClass, 5709 &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, 5710 nullptr 5711}; 5712 5713static const TargetRegisterClass *const DQuad_with_dsub_2_in_DPR_8Superclasses[] = { 5714 &ARM::DQuadRegClass, 5715 &ARM::DQuad_with_ssub_0RegClass, 5716 &ARM::DQuad_with_ssub_2RegClass, 5717 &ARM::DQuad_with_ssub_4RegClass, 5718 &ARM::DQuad_with_ssub_6RegClass, 5719 &ARM::DQuad_with_dsub_0_in_DPR_8RegClass, 5720 &ARM::DQuad_with_dsub_1_in_DPR_8RegClass, 5721 nullptr 5722}; 5723 5724static const TargetRegisterClass *const DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses[] = { 5725 &ARM::DQuadRegClass, 5726 &ARM::DQuad_with_ssub_0RegClass, 5727 &ARM::DQuad_with_ssub_2RegClass, 5728 &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, 5729 &ARM::DQuad_with_ssub_4RegClass, 5730 &ARM::DQuad_with_ssub_6RegClass, 5731 &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, 5732 &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, 5733 nullptr 5734}; 5735 5736static const TargetRegisterClass *const DQuad_with_dsub_3_in_DPR_8Superclasses[] = { 5737 &ARM::DQuadRegClass, 5738 &ARM::DQuad_with_ssub_0RegClass, 5739 &ARM::DQuad_with_ssub_2RegClass, 5740 &ARM::DQuad_with_ssub_4RegClass, 5741 &ARM::DQuad_with_ssub_6RegClass, 5742 &ARM::DQuad_with_dsub_0_in_DPR_8RegClass, 5743 &ARM::DQuad_with_dsub_1_in_DPR_8RegClass, 5744 &ARM::DQuad_with_dsub_2_in_DPR_8RegClass, 5745 nullptr 5746}; 5747 5748static const TargetRegisterClass *const DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses[] = { 5749 &ARM::DQuadRegClass, 5750 &ARM::DQuad_with_ssub_0RegClass, 5751 &ARM::DQuad_with_ssub_2RegClass, 5752 &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, 5753 &ARM::DQuad_with_ssub_4RegClass, 5754 &ARM::DQuad_with_ssub_6RegClass, 5755 &ARM::DQuad_with_dsub_0_in_DPR_8RegClass, 5756 &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, 5757 &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, 5758 &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, 5759 nullptr 5760}; 5761 5762static const TargetRegisterClass *const DQuad_with_qsub_0_in_QPR_8Superclasses[] = { 5763 &ARM::DQuadRegClass, 5764 &ARM::DQuad_with_ssub_0RegClass, 5765 &ARM::DQuad_with_ssub_2RegClass, 5766 &ARM::QQPRRegClass, 5767 &ARM::DQuad_with_ssub_4RegClass, 5768 &ARM::DQuad_with_ssub_6RegClass, 5769 &ARM::DQuad_with_dsub_0_in_DPR_8RegClass, 5770 &ARM::DQuad_with_qsub_0_in_MQPRRegClass, 5771 &ARM::DQuad_with_dsub_1_in_DPR_8RegClass, 5772 &ARM::DQuad_with_qsub_1_in_MQPRRegClass, 5773 nullptr 5774}; 5775 5776static const TargetRegisterClass *const DQuad_with_qsub_1_in_QPR_8Superclasses[] = { 5777 &ARM::DQuadRegClass, 5778 &ARM::DQuad_with_ssub_0RegClass, 5779 &ARM::DQuad_with_ssub_2RegClass, 5780 &ARM::QQPRRegClass, 5781 &ARM::DQuad_with_ssub_4RegClass, 5782 &ARM::DQuad_with_ssub_6RegClass, 5783 &ARM::DQuad_with_dsub_0_in_DPR_8RegClass, 5784 &ARM::DQuad_with_qsub_0_in_MQPRRegClass, 5785 &ARM::DQuad_with_dsub_1_in_DPR_8RegClass, 5786 &ARM::DQuad_with_qsub_1_in_MQPRRegClass, 5787 &ARM::DQuad_with_dsub_2_in_DPR_8RegClass, 5788 &ARM::DQuad_with_dsub_3_in_DPR_8RegClass, 5789 &ARM::DQuad_with_qsub_0_in_QPR_8RegClass, 5790 nullptr 5791}; 5792 5793static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses[] = { 5794 &ARM::DQuadRegClass, 5795 &ARM::DQuad_with_ssub_0RegClass, 5796 &ARM::DQuad_with_ssub_2RegClass, 5797 &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, 5798 &ARM::DQuad_with_ssub_4RegClass, 5799 &ARM::DQuad_with_ssub_6RegClass, 5800 &ARM::DQuad_with_dsub_0_in_DPR_8RegClass, 5801 &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, 5802 &ARM::DQuad_with_dsub_1_in_DPR_8RegClass, 5803 &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, 5804 &ARM::DQuad_with_dsub_2_in_DPR_8RegClass, 5805 &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, 5806 &ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, 5807 nullptr 5808}; 5809 5810static const TargetRegisterClass *const DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses[] = { 5811 &ARM::DQuadRegClass, 5812 &ARM::DQuad_with_ssub_0RegClass, 5813 &ARM::DQuad_with_ssub_2RegClass, 5814 &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, 5815 &ARM::DQuad_with_ssub_4RegClass, 5816 &ARM::DQuad_with_ssub_6RegClass, 5817 &ARM::DQuad_with_dsub_0_in_DPR_8RegClass, 5818 &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, 5819 &ARM::DQuad_with_dsub_1_in_DPR_8RegClass, 5820 &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, 5821 &ARM::DQuad_with_dsub_2_in_DPR_8RegClass, 5822 &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, 5823 &ARM::DQuad_with_dsub_3_in_DPR_8RegClass, 5824 &ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, 5825 &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass, 5826 nullptr 5827}; 5828 5829static const TargetRegisterClass *const QQQQPR_with_ssub_0Superclasses[] = { 5830 &ARM::QQQQPRRegClass, 5831 nullptr 5832}; 5833 5834static const TargetRegisterClass *const QQQQPR_with_ssub_4Superclasses[] = { 5835 &ARM::QQQQPRRegClass, 5836 &ARM::QQQQPR_with_ssub_0RegClass, 5837 nullptr 5838}; 5839 5840static const TargetRegisterClass *const QQQQPR_with_ssub_8Superclasses[] = { 5841 &ARM::QQQQPRRegClass, 5842 &ARM::QQQQPR_with_ssub_0RegClass, 5843 &ARM::QQQQPR_with_ssub_4RegClass, 5844 nullptr 5845}; 5846 5847static const TargetRegisterClass *const QQQQPR_with_ssub_12Superclasses[] = { 5848 &ARM::QQQQPRRegClass, 5849 &ARM::QQQQPR_with_ssub_0RegClass, 5850 &ARM::QQQQPR_with_ssub_4RegClass, 5851 &ARM::QQQQPR_with_ssub_8RegClass, 5852 nullptr 5853}; 5854 5855static const TargetRegisterClass *const QQQQPR_with_dsub_0_in_DPR_8Superclasses[] = { 5856 &ARM::QQQQPRRegClass, 5857 &ARM::QQQQPR_with_ssub_0RegClass, 5858 &ARM::QQQQPR_with_ssub_4RegClass, 5859 &ARM::QQQQPR_with_ssub_8RegClass, 5860 &ARM::QQQQPR_with_ssub_12RegClass, 5861 nullptr 5862}; 5863 5864static const TargetRegisterClass *const QQQQPR_with_dsub_2_in_DPR_8Superclasses[] = { 5865 &ARM::QQQQPRRegClass, 5866 &ARM::QQQQPR_with_ssub_0RegClass, 5867 &ARM::QQQQPR_with_ssub_4RegClass, 5868 &ARM::QQQQPR_with_ssub_8RegClass, 5869 &ARM::QQQQPR_with_ssub_12RegClass, 5870 &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass, 5871 nullptr 5872}; 5873 5874static const TargetRegisterClass *const QQQQPR_with_dsub_4_in_DPR_8Superclasses[] = { 5875 &ARM::QQQQPRRegClass, 5876 &ARM::QQQQPR_with_ssub_0RegClass, 5877 &ARM::QQQQPR_with_ssub_4RegClass, 5878 &ARM::QQQQPR_with_ssub_8RegClass, 5879 &ARM::QQQQPR_with_ssub_12RegClass, 5880 &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass, 5881 &ARM::QQQQPR_with_dsub_2_in_DPR_8RegClass, 5882 nullptr 5883}; 5884 5885static const TargetRegisterClass *const QQQQPR_with_dsub_6_in_DPR_8Superclasses[] = { 5886 &ARM::QQQQPRRegClass, 5887 &ARM::QQQQPR_with_ssub_0RegClass, 5888 &ARM::QQQQPR_with_ssub_4RegClass, 5889 &ARM::QQQQPR_with_ssub_8RegClass, 5890 &ARM::QQQQPR_with_ssub_12RegClass, 5891 &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass, 5892 &ARM::QQQQPR_with_dsub_2_in_DPR_8RegClass, 5893 &ARM::QQQQPR_with_dsub_4_in_DPR_8RegClass, 5894 nullptr 5895}; 5896 5897 5898static inline unsigned HPRAltOrderSelect(const MachineFunction &MF) { 5899 return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(); 5900 } 5901 5902static ArrayRef<MCPhysReg> HPRGetRawAllocationOrder(const MachineFunction &MF) { 5903 static const MCPhysReg AltOrder1[] = { ARM::S0, ARM::S2, ARM::S4, ARM::S6, ARM::S8, ARM::S10, ARM::S12, ARM::S14, ARM::S16, ARM::S18, ARM::S20, ARM::S22, ARM::S24, ARM::S26, ARM::S28, ARM::S30, ARM::S1, ARM::S3, ARM::S5, ARM::S7, ARM::S9, ARM::S11, ARM::S13, ARM::S15, ARM::S17, ARM::S19, ARM::S21, ARM::S23, ARM::S25, ARM::S27, ARM::S29, ARM::S31 }; 5904 static const MCPhysReg AltOrder2[] = { ARM::S0, ARM::S4, ARM::S8, ARM::S12, ARM::S16, ARM::S20, ARM::S24, ARM::S28, ARM::S2, ARM::S6, ARM::S10, ARM::S14, ARM::S18, ARM::S22, ARM::S26, ARM::S30, ARM::S1, ARM::S5, ARM::S9, ARM::S13, ARM::S17, ARM::S21, ARM::S25, ARM::S29, ARM::S3, ARM::S7, ARM::S11, ARM::S15, ARM::S19, ARM::S23, ARM::S27, ARM::S31 }; 5905 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::HPRRegClassID]; 5906 const ArrayRef<MCPhysReg> Order[] = { 5907 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 5908 makeArrayRef(AltOrder1), 5909 makeArrayRef(AltOrder2) 5910 }; 5911 const unsigned Select = HPRAltOrderSelect(MF); 5912 assert(Select < 3); 5913 return Order[Select]; 5914} 5915 5916static inline unsigned SPRAltOrderSelect(const MachineFunction &MF) { 5917 return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(); 5918 } 5919 5920static ArrayRef<MCPhysReg> SPRGetRawAllocationOrder(const MachineFunction &MF) { 5921 static const MCPhysReg AltOrder1[] = { ARM::S0, ARM::S2, ARM::S4, ARM::S6, ARM::S8, ARM::S10, ARM::S12, ARM::S14, ARM::S16, ARM::S18, ARM::S20, ARM::S22, ARM::S24, ARM::S26, ARM::S28, ARM::S30, ARM::S1, ARM::S3, ARM::S5, ARM::S7, ARM::S9, ARM::S11, ARM::S13, ARM::S15, ARM::S17, ARM::S19, ARM::S21, ARM::S23, ARM::S25, ARM::S27, ARM::S29, ARM::S31 }; 5922 static const MCPhysReg AltOrder2[] = { ARM::S0, ARM::S4, ARM::S8, ARM::S12, ARM::S16, ARM::S20, ARM::S24, ARM::S28, ARM::S2, ARM::S6, ARM::S10, ARM::S14, ARM::S18, ARM::S22, ARM::S26, ARM::S30, ARM::S1, ARM::S5, ARM::S9, ARM::S13, ARM::S17, ARM::S21, ARM::S25, ARM::S29, ARM::S3, ARM::S7, ARM::S11, ARM::S15, ARM::S19, ARM::S23, ARM::S27, ARM::S31 }; 5923 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::SPRRegClassID]; 5924 const ArrayRef<MCPhysReg> Order[] = { 5925 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 5926 makeArrayRef(AltOrder1), 5927 makeArrayRef(AltOrder2) 5928 }; 5929 const unsigned Select = SPRAltOrderSelect(MF); 5930 assert(Select < 3); 5931 return Order[Select]; 5932} 5933 5934static inline unsigned GPRAltOrderSelect(const MachineFunction &MF) { 5935 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF); 5936 } 5937 5938static ArrayRef<MCPhysReg> GPRGetRawAllocationOrder(const MachineFunction &MF) { 5939 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::PC }; 5940 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 }; 5941 static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP, ARM::PC }; 5942 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRRegClassID]; 5943 const ArrayRef<MCPhysReg> Order[] = { 5944 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 5945 makeArrayRef(AltOrder1), 5946 makeArrayRef(AltOrder2), 5947 makeArrayRef(AltOrder3) 5948 }; 5949 const unsigned Select = GPRAltOrderSelect(MF); 5950 assert(Select < 4); 5951 return Order[Select]; 5952} 5953 5954static inline unsigned GPRwithAPSRAltOrderSelect(const MachineFunction &MF) { 5955 return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 5956 } 5957 5958static ArrayRef<MCPhysReg> GPRwithAPSRGetRawAllocationOrder(const MachineFunction &MF) { 5959 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP }; 5960 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 }; 5961 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRwithAPSRRegClassID]; 5962 const ArrayRef<MCPhysReg> Order[] = { 5963 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 5964 makeArrayRef(AltOrder1), 5965 makeArrayRef(AltOrder2) 5966 }; 5967 const unsigned Select = GPRwithAPSRAltOrderSelect(MF); 5968 assert(Select < 3); 5969 return Order[Select]; 5970} 5971 5972static inline unsigned GPRwithZRAltOrderSelect(const MachineFunction &MF) { 5973 return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 5974 } 5975 5976static ArrayRef<MCPhysReg> GPRwithZRGetRawAllocationOrder(const MachineFunction &MF) { 5977 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::ZR }; 5978 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 }; 5979 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRwithZRRegClassID]; 5980 const ArrayRef<MCPhysReg> Order[] = { 5981 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 5982 makeArrayRef(AltOrder1), 5983 makeArrayRef(AltOrder2) 5984 }; 5985 const unsigned Select = GPRwithZRAltOrderSelect(MF); 5986 assert(Select < 3); 5987 return Order[Select]; 5988} 5989 5990static inline unsigned GPRnopcAltOrderSelect(const MachineFunction &MF) { 5991 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF); 5992 } 5993 5994static ArrayRef<MCPhysReg> GPRnopcGetRawAllocationOrder(const MachineFunction &MF) { 5995 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP }; 5996 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 }; 5997 static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP }; 5998 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRnopcRegClassID]; 5999 const ArrayRef<MCPhysReg> Order[] = { 6000 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6001 makeArrayRef(AltOrder1), 6002 makeArrayRef(AltOrder2), 6003 makeArrayRef(AltOrder3) 6004 }; 6005 const unsigned Select = GPRnopcAltOrderSelect(MF); 6006 assert(Select < 4); 6007 return Order[Select]; 6008} 6009 6010static inline unsigned GPRwithZRnospAltOrderSelect(const MachineFunction &MF) { 6011 return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 6012 } 6013 6014static ArrayRef<MCPhysReg> GPRwithZRnospGetRawAllocationOrder(const MachineFunction &MF) { 6015 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::ZR }; 6016 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 }; 6017 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRwithZRnospRegClassID]; 6018 const ArrayRef<MCPhysReg> Order[] = { 6019 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6020 makeArrayRef(AltOrder1), 6021 makeArrayRef(AltOrder2) 6022 }; 6023 const unsigned Select = GPRwithZRnospAltOrderSelect(MF); 6024 assert(Select < 3); 6025 return Order[Select]; 6026} 6027 6028static inline unsigned rGPRAltOrderSelect(const MachineFunction &MF) { 6029 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF); 6030 } 6031 6032static ArrayRef<MCPhysReg> rGPRGetRawAllocationOrder(const MachineFunction &MF) { 6033 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12 }; 6034 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 }; 6035 static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11 }; 6036 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::rGPRRegClassID]; 6037 const ArrayRef<MCPhysReg> Order[] = { 6038 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6039 makeArrayRef(AltOrder1), 6040 makeArrayRef(AltOrder2), 6041 makeArrayRef(AltOrder3) 6042 }; 6043 const unsigned Select = rGPRAltOrderSelect(MF); 6044 assert(Select < 4); 6045 return Order[Select]; 6046} 6047 6048static inline unsigned tGPREvenAltOrderSelect(const MachineFunction &MF) { 6049 return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 6050 } 6051 6052static ArrayRef<MCPhysReg> tGPREvenGetRawAllocationOrder(const MachineFunction &MF) { 6053 static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R2, ARM::R4, ARM::R6 }; 6054 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPREvenRegClassID]; 6055 const ArrayRef<MCPhysReg> Order[] = { 6056 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6057 makeArrayRef(AltOrder1) 6058 }; 6059 const unsigned Select = tGPREvenAltOrderSelect(MF); 6060 assert(Select < 2); 6061 return Order[Select]; 6062} 6063 6064static inline unsigned tGPROddAltOrderSelect(const MachineFunction &MF) { 6065 return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 6066 } 6067 6068static ArrayRef<MCPhysReg> tGPROddGetRawAllocationOrder(const MachineFunction &MF) { 6069 static const MCPhysReg AltOrder1[] = { ARM::R1, ARM::R3, ARM::R5, ARM::R7 }; 6070 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPROddRegClassID]; 6071 const ArrayRef<MCPhysReg> Order[] = { 6072 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6073 makeArrayRef(AltOrder1) 6074 }; 6075 const unsigned Select = tGPROddAltOrderSelect(MF); 6076 assert(Select < 2); 6077 return Order[Select]; 6078} 6079 6080static inline unsigned tcGPRAltOrderSelect(const MachineFunction &MF) { 6081 return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 6082 } 6083 6084static ArrayRef<MCPhysReg> tcGPRGetRawAllocationOrder(const MachineFunction &MF) { 6085 static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; 6086 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tcGPRRegClassID]; 6087 const ArrayRef<MCPhysReg> Order[] = { 6088 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6089 makeArrayRef(AltOrder1) 6090 }; 6091 const unsigned Select = tcGPRAltOrderSelect(MF); 6092 assert(Select < 2); 6093 return Order[Select]; 6094} 6095 6096static inline unsigned tGPR_and_tGPREvenAltOrderSelect(const MachineFunction &MF) { 6097 return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 6098 } 6099 6100static ArrayRef<MCPhysReg> tGPR_and_tGPREvenGetRawAllocationOrder(const MachineFunction &MF) { 6101 static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R2, ARM::R4, ARM::R6 }; 6102 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPR_and_tGPREvenRegClassID]; 6103 const ArrayRef<MCPhysReg> Order[] = { 6104 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6105 makeArrayRef(AltOrder1) 6106 }; 6107 const unsigned Select = tGPR_and_tGPREvenAltOrderSelect(MF); 6108 assert(Select < 2); 6109 return Order[Select]; 6110} 6111 6112static inline unsigned tGPR_and_tGPROddAltOrderSelect(const MachineFunction &MF) { 6113 return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 6114 } 6115 6116static ArrayRef<MCPhysReg> tGPR_and_tGPROddGetRawAllocationOrder(const MachineFunction &MF) { 6117 static const MCPhysReg AltOrder1[] = { ARM::R1, ARM::R3, ARM::R5, ARM::R7 }; 6118 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPR_and_tGPROddRegClassID]; 6119 const ArrayRef<MCPhysReg> Order[] = { 6120 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6121 makeArrayRef(AltOrder1) 6122 }; 6123 const unsigned Select = tGPR_and_tGPROddAltOrderSelect(MF); 6124 assert(Select < 2); 6125 return Order[Select]; 6126} 6127 6128static inline unsigned tGPR_and_tcGPRAltOrderSelect(const MachineFunction &MF) { 6129 return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 6130 } 6131 6132static ArrayRef<MCPhysReg> tGPR_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) { 6133 static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; 6134 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPR_and_tcGPRRegClassID]; 6135 const ArrayRef<MCPhysReg> Order[] = { 6136 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6137 makeArrayRef(AltOrder1) 6138 }; 6139 const unsigned Select = tGPR_and_tcGPRAltOrderSelect(MF); 6140 assert(Select < 2); 6141 return Order[Select]; 6142} 6143 6144static inline unsigned tGPREven_and_tcGPRAltOrderSelect(const MachineFunction &MF) { 6145 return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 6146 } 6147 6148static ArrayRef<MCPhysReg> tGPREven_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) { 6149 static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R2 }; 6150 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPREven_and_tcGPRRegClassID]; 6151 const ArrayRef<MCPhysReg> Order[] = { 6152 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6153 makeArrayRef(AltOrder1) 6154 }; 6155 const unsigned Select = tGPREven_and_tcGPRAltOrderSelect(MF); 6156 assert(Select < 2); 6157 return Order[Select]; 6158} 6159 6160static inline unsigned hGPR_and_tGPROddAltOrderSelect(const MachineFunction &MF) { 6161 return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 6162 } 6163 6164static ArrayRef<MCPhysReg> hGPR_and_tGPROddGetRawAllocationOrder(const MachineFunction &MF) { 6165 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::hGPR_and_tGPROddRegClassID]; 6166 const ArrayRef<MCPhysReg> Order[] = { 6167 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6168 ArrayRef<MCPhysReg>() 6169 }; 6170 const unsigned Select = hGPR_and_tGPROddAltOrderSelect(MF); 6171 assert(Select < 2); 6172 return Order[Select]; 6173} 6174 6175static inline unsigned tGPREven_and_tGPR_and_tcGPRAltOrderSelect(const MachineFunction &MF) { 6176 return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 6177 } 6178 6179static ArrayRef<MCPhysReg> tGPREven_and_tGPR_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) { 6180 static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R2 }; 6181 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPREven_and_tGPR_and_tcGPRRegClassID]; 6182 const ArrayRef<MCPhysReg> Order[] = { 6183 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6184 makeArrayRef(AltOrder1) 6185 }; 6186 const unsigned Select = tGPREven_and_tGPR_and_tcGPRAltOrderSelect(MF); 6187 assert(Select < 2); 6188 return Order[Select]; 6189} 6190 6191static inline unsigned tGPROdd_and_tcGPRAltOrderSelect(const MachineFunction &MF) { 6192 return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 6193 } 6194 6195static ArrayRef<MCPhysReg> tGPROdd_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) { 6196 static const MCPhysReg AltOrder1[] = { ARM::R1, ARM::R3 }; 6197 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPROdd_and_tcGPRRegClassID]; 6198 const ArrayRef<MCPhysReg> Order[] = { 6199 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6200 makeArrayRef(AltOrder1) 6201 }; 6202 const unsigned Select = tGPROdd_and_tcGPRAltOrderSelect(MF); 6203 assert(Select < 2); 6204 return Order[Select]; 6205} 6206 6207static inline unsigned hGPR_and_tcGPRAltOrderSelect(const MachineFunction &MF) { 6208 return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 6209 } 6210 6211static ArrayRef<MCPhysReg> hGPR_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) { 6212 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::hGPR_and_tcGPRRegClassID]; 6213 const ArrayRef<MCPhysReg> Order[] = { 6214 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6215 ArrayRef<MCPhysReg>() 6216 }; 6217 const unsigned Select = hGPR_and_tcGPRAltOrderSelect(MF); 6218 assert(Select < 2); 6219 return Order[Select]; 6220} 6221 6222static inline unsigned DPRAltOrderSelect(const MachineFunction &MF) { 6223 return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(); 6224 } 6225 6226static ArrayRef<MCPhysReg> DPRGetRawAllocationOrder(const MachineFunction &MF) { 6227 static const MCPhysReg AltOrder1[] = { ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15 }; 6228 static const MCPhysReg AltOrder2[] = { ARM::D16, ARM::D18, ARM::D20, ARM::D22, ARM::D24, ARM::D26, ARM::D28, ARM::D30, ARM::D0, ARM::D2, ARM::D4, ARM::D6, ARM::D8, ARM::D10, ARM::D12, ARM::D14, ARM::D17, ARM::D19, ARM::D21, ARM::D23, ARM::D25, ARM::D27, ARM::D29, ARM::D31, ARM::D1, ARM::D3, ARM::D5, ARM::D7, ARM::D9, ARM::D11, ARM::D13, ARM::D15 }; 6229 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPRRegClassID]; 6230 const ArrayRef<MCPhysReg> Order[] = { 6231 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6232 makeArrayRef(AltOrder1), 6233 makeArrayRef(AltOrder2) 6234 }; 6235 const unsigned Select = DPRAltOrderSelect(MF); 6236 assert(Select < 3); 6237 return Order[Select]; 6238} 6239 6240static inline unsigned DPairAltOrderSelect(const MachineFunction &MF) { 6241 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps(); 6242 } 6243 6244static ArrayRef<MCPhysReg> DPairGetRawAllocationOrder(const MachineFunction &MF) { 6245 static const MCPhysReg AltOrder1[] = { ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D17_D18, ARM::D19_D20, ARM::D21_D22, ARM::D23_D24, ARM::D25_D26, ARM::D27_D28, ARM::D29_D30, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14, ARM::D15_D16 }; 6246 static const MCPhysReg AltOrder2[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14, ARM::D15_D16 }; 6247 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPairRegClassID]; 6248 const ArrayRef<MCPhysReg> Order[] = { 6249 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6250 makeArrayRef(AltOrder1), 6251 makeArrayRef(AltOrder2) 6252 }; 6253 const unsigned Select = DPairAltOrderSelect(MF); 6254 assert(Select < 3); 6255 return Order[Select]; 6256} 6257 6258static inline unsigned DPair_with_ssub_0AltOrderSelect(const MachineFunction &MF) { 6259 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps(); 6260 } 6261 6262static ArrayRef<MCPhysReg> DPair_with_ssub_0GetRawAllocationOrder(const MachineFunction &MF) { 6263 static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14, ARM::D15_D16 }; 6264 static const MCPhysReg AltOrder2[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14, ARM::D15_D16 }; 6265 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_ssub_0RegClassID]; 6266 const ArrayRef<MCPhysReg> Order[] = { 6267 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6268 makeArrayRef(AltOrder1), 6269 makeArrayRef(AltOrder2) 6270 }; 6271 const unsigned Select = DPair_with_ssub_0AltOrderSelect(MF); 6272 assert(Select < 3); 6273 return Order[Select]; 6274} 6275 6276static inline unsigned QPRAltOrderSelect(const MachineFunction &MF) { 6277 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps(); 6278 } 6279 6280static ArrayRef<MCPhysReg> QPRGetRawAllocationOrder(const MachineFunction &MF) { 6281 static const MCPhysReg AltOrder1[] = { ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7 }; 6282 static const MCPhysReg AltOrder2[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7 }; 6283 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QPRRegClassID]; 6284 const ArrayRef<MCPhysReg> Order[] = { 6285 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6286 makeArrayRef(AltOrder1), 6287 makeArrayRef(AltOrder2) 6288 }; 6289 const unsigned Select = QPRAltOrderSelect(MF); 6290 assert(Select < 3); 6291 return Order[Select]; 6292} 6293 6294static inline unsigned DPair_with_ssub_2AltOrderSelect(const MachineFunction &MF) { 6295 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps(); 6296 } 6297 6298static ArrayRef<MCPhysReg> DPair_with_ssub_2GetRawAllocationOrder(const MachineFunction &MF) { 6299 static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14 }; 6300 static const MCPhysReg AltOrder2[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14 }; 6301 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_ssub_2RegClassID]; 6302 const ArrayRef<MCPhysReg> Order[] = { 6303 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6304 makeArrayRef(AltOrder1), 6305 makeArrayRef(AltOrder2) 6306 }; 6307 const unsigned Select = DPair_with_ssub_2AltOrderSelect(MF); 6308 assert(Select < 3); 6309 return Order[Select]; 6310} 6311 6312static inline unsigned DPair_with_dsub_0_in_DPR_8AltOrderSelect(const MachineFunction &MF) { 6313 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps(); 6314 } 6315 6316static ArrayRef<MCPhysReg> DPair_with_dsub_0_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) { 6317 static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8 }; 6318 static const MCPhysReg AltOrder2[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8 }; 6319 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_dsub_0_in_DPR_8RegClassID]; 6320 const ArrayRef<MCPhysReg> Order[] = { 6321 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6322 makeArrayRef(AltOrder1), 6323 makeArrayRef(AltOrder2) 6324 }; 6325 const unsigned Select = DPair_with_dsub_0_in_DPR_8AltOrderSelect(MF); 6326 assert(Select < 3); 6327 return Order[Select]; 6328} 6329 6330static inline unsigned DPair_with_dsub_1_in_DPR_8AltOrderSelect(const MachineFunction &MF) { 6331 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps(); 6332 } 6333 6334static ArrayRef<MCPhysReg> DPair_with_dsub_1_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) { 6335 static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6 }; 6336 static const MCPhysReg AltOrder2[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6 }; 6337 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_dsub_1_in_DPR_8RegClassID]; 6338 const ArrayRef<MCPhysReg> Order[] = { 6339 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6340 makeArrayRef(AltOrder1), 6341 makeArrayRef(AltOrder2) 6342 }; 6343 const unsigned Select = DPair_with_dsub_1_in_DPR_8AltOrderSelect(MF); 6344 assert(Select < 3); 6345 return Order[Select]; 6346} 6347 6348static inline unsigned QQPRAltOrderSelect(const MachineFunction &MF) { return 1; } 6349 6350static ArrayRef<MCPhysReg> QQPRGetRawAllocationOrder(const MachineFunction &MF) { 6351 static const MCPhysReg AltOrder1[] = { ARM::Q8_Q9, ARM::Q9_Q10, ARM::Q10_Q11, ARM::Q11_Q12, ARM::Q12_Q13, ARM::Q13_Q14, ARM::Q14_Q15, ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8 }; 6352 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQPRRegClassID]; 6353 const ArrayRef<MCPhysReg> Order[] = { 6354 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6355 makeArrayRef(AltOrder1) 6356 }; 6357 const unsigned Select = QQPRAltOrderSelect(MF); 6358 assert(Select < 2); 6359 return Order[Select]; 6360} 6361 6362static inline unsigned DQuad_with_qsub_0_in_MQPRAltOrderSelect(const MachineFunction &MF) { return 1; } 6363 6364static ArrayRef<MCPhysReg> DQuad_with_qsub_0_in_MQPRGetRawAllocationOrder(const MachineFunction &MF) { 6365 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8 }; 6366 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_0_in_MQPRRegClassID]; 6367 const ArrayRef<MCPhysReg> Order[] = { 6368 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6369 makeArrayRef(AltOrder1) 6370 }; 6371 const unsigned Select = DQuad_with_qsub_0_in_MQPRAltOrderSelect(MF); 6372 assert(Select < 2); 6373 return Order[Select]; 6374} 6375 6376static inline unsigned DQuad_with_qsub_1_in_MQPRAltOrderSelect(const MachineFunction &MF) { return 1; } 6377 6378static ArrayRef<MCPhysReg> DQuad_with_qsub_1_in_MQPRGetRawAllocationOrder(const MachineFunction &MF) { 6379 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 }; 6380 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_1_in_MQPRRegClassID]; 6381 const ArrayRef<MCPhysReg> Order[] = { 6382 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6383 makeArrayRef(AltOrder1) 6384 }; 6385 const unsigned Select = DQuad_with_qsub_1_in_MQPRAltOrderSelect(MF); 6386 assert(Select < 2); 6387 return Order[Select]; 6388} 6389 6390static inline unsigned DQuad_with_qsub_0_in_QPR_8AltOrderSelect(const MachineFunction &MF) { return 1; } 6391 6392static ArrayRef<MCPhysReg> DQuad_with_qsub_0_in_QPR_8GetRawAllocationOrder(const MachineFunction &MF) { 6393 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4 }; 6394 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_0_in_QPR_8RegClassID]; 6395 const ArrayRef<MCPhysReg> Order[] = { 6396 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6397 makeArrayRef(AltOrder1) 6398 }; 6399 const unsigned Select = DQuad_with_qsub_0_in_QPR_8AltOrderSelect(MF); 6400 assert(Select < 2); 6401 return Order[Select]; 6402} 6403 6404static inline unsigned DQuad_with_qsub_1_in_QPR_8AltOrderSelect(const MachineFunction &MF) { return 1; } 6405 6406static ArrayRef<MCPhysReg> DQuad_with_qsub_1_in_QPR_8GetRawAllocationOrder(const MachineFunction &MF) { 6407 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3 }; 6408 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_1_in_QPR_8RegClassID]; 6409 const ArrayRef<MCPhysReg> Order[] = { 6410 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6411 makeArrayRef(AltOrder1) 6412 }; 6413 const unsigned Select = DQuad_with_qsub_1_in_QPR_8AltOrderSelect(MF); 6414 assert(Select < 2); 6415 return Order[Select]; 6416} 6417 6418static inline unsigned QQQQPRAltOrderSelect(const MachineFunction &MF) { return 1; } 6419 6420static ArrayRef<MCPhysReg> QQQQPRGetRawAllocationOrder(const MachineFunction &MF) { 6421 static const MCPhysReg AltOrder1[] = { ARM::Q8_Q9_Q10_Q11, ARM::Q9_Q10_Q11_Q12, ARM::Q10_Q11_Q12_Q13, ARM::Q11_Q12_Q13_Q14, ARM::Q12_Q13_Q14_Q15, ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10 }; 6422 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPRRegClassID]; 6423 const ArrayRef<MCPhysReg> Order[] = { 6424 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6425 makeArrayRef(AltOrder1) 6426 }; 6427 const unsigned Select = QQQQPRAltOrderSelect(MF); 6428 assert(Select < 2); 6429 return Order[Select]; 6430} 6431 6432static inline unsigned QQQQPR_with_ssub_0AltOrderSelect(const MachineFunction &MF) { return 1; } 6433 6434static ArrayRef<MCPhysReg> QQQQPR_with_ssub_0GetRawAllocationOrder(const MachineFunction &MF) { 6435 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10 }; 6436 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_0RegClassID]; 6437 const ArrayRef<MCPhysReg> Order[] = { 6438 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6439 makeArrayRef(AltOrder1) 6440 }; 6441 const unsigned Select = QQQQPR_with_ssub_0AltOrderSelect(MF); 6442 assert(Select < 2); 6443 return Order[Select]; 6444} 6445 6446static inline unsigned QQQQPR_with_ssub_4AltOrderSelect(const MachineFunction &MF) { return 1; } 6447 6448static ArrayRef<MCPhysReg> QQQQPR_with_ssub_4GetRawAllocationOrder(const MachineFunction &MF) { 6449 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9 }; 6450 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_4RegClassID]; 6451 const ArrayRef<MCPhysReg> Order[] = { 6452 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6453 makeArrayRef(AltOrder1) 6454 }; 6455 const unsigned Select = QQQQPR_with_ssub_4AltOrderSelect(MF); 6456 assert(Select < 2); 6457 return Order[Select]; 6458} 6459 6460static inline unsigned QQQQPR_with_ssub_8AltOrderSelect(const MachineFunction &MF) { return 1; } 6461 6462static ArrayRef<MCPhysReg> QQQQPR_with_ssub_8GetRawAllocationOrder(const MachineFunction &MF) { 6463 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8 }; 6464 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_8RegClassID]; 6465 const ArrayRef<MCPhysReg> Order[] = { 6466 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6467 makeArrayRef(AltOrder1) 6468 }; 6469 const unsigned Select = QQQQPR_with_ssub_8AltOrderSelect(MF); 6470 assert(Select < 2); 6471 return Order[Select]; 6472} 6473 6474static inline unsigned QQQQPR_with_ssub_12AltOrderSelect(const MachineFunction &MF) { return 1; } 6475 6476static ArrayRef<MCPhysReg> QQQQPR_with_ssub_12GetRawAllocationOrder(const MachineFunction &MF) { 6477 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 }; 6478 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_12RegClassID]; 6479 const ArrayRef<MCPhysReg> Order[] = { 6480 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6481 makeArrayRef(AltOrder1) 6482 }; 6483 const unsigned Select = QQQQPR_with_ssub_12AltOrderSelect(MF); 6484 assert(Select < 2); 6485 return Order[Select]; 6486} 6487 6488static inline unsigned QQQQPR_with_dsub_0_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; } 6489 6490static ArrayRef<MCPhysReg> QQQQPR_with_dsub_0_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) { 6491 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6 }; 6492 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_0_in_DPR_8RegClassID]; 6493 const ArrayRef<MCPhysReg> Order[] = { 6494 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6495 makeArrayRef(AltOrder1) 6496 }; 6497 const unsigned Select = QQQQPR_with_dsub_0_in_DPR_8AltOrderSelect(MF); 6498 assert(Select < 2); 6499 return Order[Select]; 6500} 6501 6502static inline unsigned QQQQPR_with_dsub_2_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; } 6503 6504static ArrayRef<MCPhysReg> QQQQPR_with_dsub_2_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) { 6505 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5 }; 6506 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_2_in_DPR_8RegClassID]; 6507 const ArrayRef<MCPhysReg> Order[] = { 6508 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6509 makeArrayRef(AltOrder1) 6510 }; 6511 const unsigned Select = QQQQPR_with_dsub_2_in_DPR_8AltOrderSelect(MF); 6512 assert(Select < 2); 6513 return Order[Select]; 6514} 6515 6516static inline unsigned QQQQPR_with_dsub_4_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; } 6517 6518static ArrayRef<MCPhysReg> QQQQPR_with_dsub_4_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) { 6519 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4 }; 6520 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_4_in_DPR_8RegClassID]; 6521 const ArrayRef<MCPhysReg> Order[] = { 6522 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6523 makeArrayRef(AltOrder1) 6524 }; 6525 const unsigned Select = QQQQPR_with_dsub_4_in_DPR_8AltOrderSelect(MF); 6526 assert(Select < 2); 6527 return Order[Select]; 6528} 6529 6530static inline unsigned QQQQPR_with_dsub_6_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; } 6531 6532static ArrayRef<MCPhysReg> QQQQPR_with_dsub_6_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) { 6533 static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3 }; 6534 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_6_in_DPR_8RegClassID]; 6535 const ArrayRef<MCPhysReg> Order[] = { 6536 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 6537 makeArrayRef(AltOrder1) 6538 }; 6539 const unsigned Select = QQQQPR_with_dsub_6_in_DPR_8AltOrderSelect(MF); 6540 assert(Select < 2); 6541 return Order[Select]; 6542} 6543 6544namespace ARM { // Register class instances 6545 extern const TargetRegisterClass HPRRegClass = { 6546 &ARMMCRegisterClasses[HPRRegClassID], 6547 HPRSubClassMask, 6548 SuperRegIdxSeqs + 22, 6549 LaneBitmask(0x00000001), 6550 0, 6551 false, /* HasDisjunctSubRegs */ 6552 false, /* CoveredBySubRegs */ 6553 NullRegClasses, 6554 HPRGetRawAllocationOrder 6555 }; 6556 6557 extern const TargetRegisterClass FPWithVPRRegClass = { 6558 &ARMMCRegisterClasses[FPWithVPRRegClassID], 6559 FPWithVPRSubClassMask, 6560 SuperRegIdxSeqs + 14, 6561 LaneBitmask(0x0000000C), 6562 0, 6563 true, /* HasDisjunctSubRegs */ 6564 false, /* CoveredBySubRegs */ 6565 NullRegClasses, 6566 nullptr 6567 }; 6568 6569 extern const TargetRegisterClass SPRRegClass = { 6570 &ARMMCRegisterClasses[SPRRegClassID], 6571 SPRSubClassMask, 6572 SuperRegIdxSeqs + 22, 6573 LaneBitmask(0x00000001), 6574 0, 6575 false, /* HasDisjunctSubRegs */ 6576 false, /* CoveredBySubRegs */ 6577 SPRSuperclasses, 6578 SPRGetRawAllocationOrder 6579 }; 6580 6581 extern const TargetRegisterClass FPWithVPR_with_ssub_0RegClass = { 6582 &ARMMCRegisterClasses[FPWithVPR_with_ssub_0RegClassID], 6583 FPWithVPR_with_ssub_0SubClassMask, 6584 SuperRegIdxSeqs + 0, 6585 LaneBitmask(0x0000000C), 6586 0, 6587 true, /* HasDisjunctSubRegs */ 6588 true, /* CoveredBySubRegs */ 6589 FPWithVPR_with_ssub_0Superclasses, 6590 nullptr 6591 }; 6592 6593 extern const TargetRegisterClass GPRRegClass = { 6594 &ARMMCRegisterClasses[GPRRegClassID], 6595 GPRSubClassMask, 6596 SuperRegIdxSeqs + 11, 6597 LaneBitmask(0x00000001), 6598 0, 6599 false, /* HasDisjunctSubRegs */ 6600 true, /* CoveredBySubRegs */ 6601 NullRegClasses, 6602 GPRGetRawAllocationOrder 6603 }; 6604 6605 extern const TargetRegisterClass GPRwithAPSRRegClass = { 6606 &ARMMCRegisterClasses[GPRwithAPSRRegClassID], 6607 GPRwithAPSRSubClassMask, 6608 SuperRegIdxSeqs + 11, 6609 LaneBitmask(0x00000001), 6610 0, 6611 false, /* HasDisjunctSubRegs */ 6612 true, /* CoveredBySubRegs */ 6613 NullRegClasses, 6614 GPRwithAPSRGetRawAllocationOrder 6615 }; 6616 6617 extern const TargetRegisterClass GPRwithZRRegClass = { 6618 &ARMMCRegisterClasses[GPRwithZRRegClassID], 6619 GPRwithZRSubClassMask, 6620 SuperRegIdxSeqs + 11, 6621 LaneBitmask(0x00000001), 6622 0, 6623 false, /* HasDisjunctSubRegs */ 6624 true, /* CoveredBySubRegs */ 6625 NullRegClasses, 6626 GPRwithZRGetRawAllocationOrder 6627 }; 6628 6629 extern const TargetRegisterClass SPR_8RegClass = { 6630 &ARMMCRegisterClasses[SPR_8RegClassID], 6631 SPR_8SubClassMask, 6632 SuperRegIdxSeqs + 22, 6633 LaneBitmask(0x00000001), 6634 0, 6635 false, /* HasDisjunctSubRegs */ 6636 false, /* CoveredBySubRegs */ 6637 SPR_8Superclasses, 6638 nullptr 6639 }; 6640 6641 extern const TargetRegisterClass GPRnopcRegClass = { 6642 &ARMMCRegisterClasses[GPRnopcRegClassID], 6643 GPRnopcSubClassMask, 6644 SuperRegIdxSeqs + 11, 6645 LaneBitmask(0x00000001), 6646 0, 6647 false, /* HasDisjunctSubRegs */ 6648 true, /* CoveredBySubRegs */ 6649 GPRnopcSuperclasses, 6650 GPRnopcGetRawAllocationOrder 6651 }; 6652 6653 extern const TargetRegisterClass GPRwithAPSRnospRegClass = { 6654 &ARMMCRegisterClasses[GPRwithAPSRnospRegClassID], 6655 GPRwithAPSRnospSubClassMask, 6656 SuperRegIdxSeqs + 11, 6657 LaneBitmask(0x00000001), 6658 0, 6659 false, /* HasDisjunctSubRegs */ 6660 true, /* CoveredBySubRegs */ 6661 NullRegClasses, 6662 nullptr 6663 }; 6664 6665 extern const TargetRegisterClass GPRwithZRnospRegClass = { 6666 &ARMMCRegisterClasses[GPRwithZRnospRegClassID], 6667 GPRwithZRnospSubClassMask, 6668 SuperRegIdxSeqs + 11, 6669 LaneBitmask(0x00000001), 6670 0, 6671 false, /* HasDisjunctSubRegs */ 6672 true, /* CoveredBySubRegs */ 6673 GPRwithZRnospSuperclasses, 6674 GPRwithZRnospGetRawAllocationOrder 6675 }; 6676 6677 extern const TargetRegisterClass rGPRRegClass = { 6678 &ARMMCRegisterClasses[rGPRRegClassID], 6679 rGPRSubClassMask, 6680 SuperRegIdxSeqs + 11, 6681 LaneBitmask(0x00000001), 6682 0, 6683 false, /* HasDisjunctSubRegs */ 6684 true, /* CoveredBySubRegs */ 6685 rGPRSuperclasses, 6686 rGPRGetRawAllocationOrder 6687 }; 6688 6689 extern const TargetRegisterClass tGPRwithpcRegClass = { 6690 &ARMMCRegisterClasses[tGPRwithpcRegClassID], 6691 tGPRwithpcSubClassMask, 6692 SuperRegIdxSeqs + 11, 6693 LaneBitmask(0x00000001), 6694 0, 6695 false, /* HasDisjunctSubRegs */ 6696 true, /* CoveredBySubRegs */ 6697 tGPRwithpcSuperclasses, 6698 nullptr 6699 }; 6700 6701 extern const TargetRegisterClass FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClass = { 6702 &ARMMCRegisterClasses[FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID], 6703 FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8SubClassMask, 6704 SuperRegIdxSeqs + 0, 6705 LaneBitmask(0x0000000C), 6706 0, 6707 true, /* HasDisjunctSubRegs */ 6708 true, /* CoveredBySubRegs */ 6709 FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Superclasses, 6710 nullptr 6711 }; 6712 6713 extern const TargetRegisterClass hGPRRegClass = { 6714 &ARMMCRegisterClasses[hGPRRegClassID], 6715 hGPRSubClassMask, 6716 SuperRegIdxSeqs + 11, 6717 LaneBitmask(0x00000001), 6718 0, 6719 false, /* HasDisjunctSubRegs */ 6720 true, /* CoveredBySubRegs */ 6721 hGPRSuperclasses, 6722 nullptr 6723 }; 6724 6725 extern const TargetRegisterClass tGPRRegClass = { 6726 &ARMMCRegisterClasses[tGPRRegClassID], 6727 tGPRSubClassMask, 6728 SuperRegIdxSeqs + 11, 6729 LaneBitmask(0x00000001), 6730 0, 6731 false, /* HasDisjunctSubRegs */ 6732 true, /* CoveredBySubRegs */ 6733 tGPRSuperclasses, 6734 nullptr 6735 }; 6736 6737 extern const TargetRegisterClass tGPREvenRegClass = { 6738 &ARMMCRegisterClasses[tGPREvenRegClassID], 6739 tGPREvenSubClassMask, 6740 SuperRegIdxSeqs + 9, 6741 LaneBitmask(0x00000001), 6742 0, 6743 false, /* HasDisjunctSubRegs */ 6744 true, /* CoveredBySubRegs */ 6745 tGPREvenSuperclasses, 6746 tGPREvenGetRawAllocationOrder 6747 }; 6748 6749 extern const TargetRegisterClass GPRnopc_and_hGPRRegClass = { 6750 &ARMMCRegisterClasses[GPRnopc_and_hGPRRegClassID], 6751 GPRnopc_and_hGPRSubClassMask, 6752 SuperRegIdxSeqs + 11, 6753 LaneBitmask(0x00000001), 6754 0, 6755 false, /* HasDisjunctSubRegs */ 6756 true, /* CoveredBySubRegs */ 6757 GPRnopc_and_hGPRSuperclasses, 6758 nullptr 6759 }; 6760 6761 extern const TargetRegisterClass GPRwithAPSRnosp_and_hGPRRegClass = { 6762 &ARMMCRegisterClasses[GPRwithAPSRnosp_and_hGPRRegClassID], 6763 GPRwithAPSRnosp_and_hGPRSubClassMask, 6764 SuperRegIdxSeqs + 11, 6765 LaneBitmask(0x00000001), 6766 0, 6767 false, /* HasDisjunctSubRegs */ 6768 true, /* CoveredBySubRegs */ 6769 GPRwithAPSRnosp_and_hGPRSuperclasses, 6770 nullptr 6771 }; 6772 6773 extern const TargetRegisterClass tGPROddRegClass = { 6774 &ARMMCRegisterClasses[tGPROddRegClassID], 6775 tGPROddSubClassMask, 6776 SuperRegIdxSeqs + 12, 6777 LaneBitmask(0x00000001), 6778 0, 6779 false, /* HasDisjunctSubRegs */ 6780 true, /* CoveredBySubRegs */ 6781 tGPROddSuperclasses, 6782 tGPROddGetRawAllocationOrder 6783 }; 6784 6785 extern const TargetRegisterClass tcGPRRegClass = { 6786 &ARMMCRegisterClasses[tcGPRRegClassID], 6787 tcGPRSubClassMask, 6788 SuperRegIdxSeqs + 11, 6789 LaneBitmask(0x00000001), 6790 0, 6791 false, /* HasDisjunctSubRegs */ 6792 true, /* CoveredBySubRegs */ 6793 tcGPRSuperclasses, 6794 tcGPRGetRawAllocationOrder 6795 }; 6796 6797 extern const TargetRegisterClass hGPR_and_tGPREvenRegClass = { 6798 &ARMMCRegisterClasses[hGPR_and_tGPREvenRegClassID], 6799 hGPR_and_tGPREvenSubClassMask, 6800 SuperRegIdxSeqs + 9, 6801 LaneBitmask(0x00000001), 6802 0, 6803 false, /* HasDisjunctSubRegs */ 6804 true, /* CoveredBySubRegs */ 6805 hGPR_and_tGPREvenSuperclasses, 6806 nullptr 6807 }; 6808 6809 extern const TargetRegisterClass tGPR_and_tGPREvenRegClass = { 6810 &ARMMCRegisterClasses[tGPR_and_tGPREvenRegClassID], 6811 tGPR_and_tGPREvenSubClassMask, 6812 SuperRegIdxSeqs + 9, 6813 LaneBitmask(0x00000001), 6814 0, 6815 false, /* HasDisjunctSubRegs */ 6816 true, /* CoveredBySubRegs */ 6817 tGPR_and_tGPREvenSuperclasses, 6818 tGPR_and_tGPREvenGetRawAllocationOrder 6819 }; 6820 6821 extern const TargetRegisterClass tGPR_and_tGPROddRegClass = { 6822 &ARMMCRegisterClasses[tGPR_and_tGPROddRegClassID], 6823 tGPR_and_tGPROddSubClassMask, 6824 SuperRegIdxSeqs + 12, 6825 LaneBitmask(0x00000001), 6826 0, 6827 false, /* HasDisjunctSubRegs */ 6828 true, /* CoveredBySubRegs */ 6829 tGPR_and_tGPROddSuperclasses, 6830 tGPR_and_tGPROddGetRawAllocationOrder 6831 }; 6832 6833 extern const TargetRegisterClass tGPR_and_tcGPRRegClass = { 6834 &ARMMCRegisterClasses[tGPR_and_tcGPRRegClassID], 6835 tGPR_and_tcGPRSubClassMask, 6836 SuperRegIdxSeqs + 11, 6837 LaneBitmask(0x00000001), 6838 0, 6839 false, /* HasDisjunctSubRegs */ 6840 true, /* CoveredBySubRegs */ 6841 tGPR_and_tcGPRSuperclasses, 6842 tGPR_and_tcGPRGetRawAllocationOrder 6843 }; 6844 6845 extern const TargetRegisterClass tGPREven_and_tcGPRRegClass = { 6846 &ARMMCRegisterClasses[tGPREven_and_tcGPRRegClassID], 6847 tGPREven_and_tcGPRSubClassMask, 6848 SuperRegIdxSeqs + 9, 6849 LaneBitmask(0x00000001), 6850 0, 6851 false, /* HasDisjunctSubRegs */ 6852 true, /* CoveredBySubRegs */ 6853 tGPREven_and_tcGPRSuperclasses, 6854 tGPREven_and_tcGPRGetRawAllocationOrder 6855 }; 6856 6857 extern const TargetRegisterClass hGPR_and_tGPROddRegClass = { 6858 &ARMMCRegisterClasses[hGPR_and_tGPROddRegClassID], 6859 hGPR_and_tGPROddSubClassMask, 6860 SuperRegIdxSeqs + 12, 6861 LaneBitmask(0x00000001), 6862 0, 6863 false, /* HasDisjunctSubRegs */ 6864 true, /* CoveredBySubRegs */ 6865 hGPR_and_tGPROddSuperclasses, 6866 hGPR_and_tGPROddGetRawAllocationOrder 6867 }; 6868 6869 extern const TargetRegisterClass tGPREven_and_tGPR_and_tcGPRRegClass = { 6870 &ARMMCRegisterClasses[tGPREven_and_tGPR_and_tcGPRRegClassID], 6871 tGPREven_and_tGPR_and_tcGPRSubClassMask, 6872 SuperRegIdxSeqs + 9, 6873 LaneBitmask(0x00000001), 6874 0, 6875 false, /* HasDisjunctSubRegs */ 6876 true, /* CoveredBySubRegs */ 6877 tGPREven_and_tGPR_and_tcGPRSuperclasses, 6878 tGPREven_and_tGPR_and_tcGPRGetRawAllocationOrder 6879 }; 6880 6881 extern const TargetRegisterClass tGPROdd_and_tcGPRRegClass = { 6882 &ARMMCRegisterClasses[tGPROdd_and_tcGPRRegClassID], 6883 tGPROdd_and_tcGPRSubClassMask, 6884 SuperRegIdxSeqs + 12, 6885 LaneBitmask(0x00000001), 6886 0, 6887 false, /* HasDisjunctSubRegs */ 6888 true, /* CoveredBySubRegs */ 6889 tGPROdd_and_tcGPRSuperclasses, 6890 tGPROdd_and_tcGPRGetRawAllocationOrder 6891 }; 6892 6893 extern const TargetRegisterClass CCRRegClass = { 6894 &ARMMCRegisterClasses[CCRRegClassID], 6895 CCRSubClassMask, 6896 SuperRegIdxSeqs + 8, 6897 LaneBitmask(0x00000001), 6898 0, 6899 false, /* HasDisjunctSubRegs */ 6900 true, /* CoveredBySubRegs */ 6901 NullRegClasses, 6902 nullptr 6903 }; 6904 6905 extern const TargetRegisterClass GPRlrRegClass = { 6906 &ARMMCRegisterClasses[GPRlrRegClassID], 6907 GPRlrSubClassMask, 6908 SuperRegIdxSeqs + 8, 6909 LaneBitmask(0x00000001), 6910 0, 6911 false, /* HasDisjunctSubRegs */ 6912 true, /* CoveredBySubRegs */ 6913 GPRlrSuperclasses, 6914 nullptr 6915 }; 6916 6917 extern const TargetRegisterClass GPRspRegClass = { 6918 &ARMMCRegisterClasses[GPRspRegClassID], 6919 GPRspSubClassMask, 6920 SuperRegIdxSeqs + 12, 6921 LaneBitmask(0x00000001), 6922 0, 6923 false, /* HasDisjunctSubRegs */ 6924 true, /* CoveredBySubRegs */ 6925 GPRspSuperclasses, 6926 nullptr 6927 }; 6928 6929 extern const TargetRegisterClass VCCRRegClass = { 6930 &ARMMCRegisterClasses[VCCRRegClassID], 6931 VCCRSubClassMask, 6932 SuperRegIdxSeqs + 8, 6933 LaneBitmask(0x00000001), 6934 0, 6935 false, /* HasDisjunctSubRegs */ 6936 true, /* CoveredBySubRegs */ 6937 VCCRSuperclasses, 6938 nullptr 6939 }; 6940 6941 extern const TargetRegisterClass cl_FPSCR_NZCVRegClass = { 6942 &ARMMCRegisterClasses[cl_FPSCR_NZCVRegClassID], 6943 cl_FPSCR_NZCVSubClassMask, 6944 SuperRegIdxSeqs + 8, 6945 LaneBitmask(0x00000001), 6946 0, 6947 false, /* HasDisjunctSubRegs */ 6948 true, /* CoveredBySubRegs */ 6949 NullRegClasses, 6950 nullptr 6951 }; 6952 6953 extern const TargetRegisterClass hGPR_and_tGPRwithpcRegClass = { 6954 &ARMMCRegisterClasses[hGPR_and_tGPRwithpcRegClassID], 6955 hGPR_and_tGPRwithpcSubClassMask, 6956 SuperRegIdxSeqs + 8, 6957 LaneBitmask(0x00000001), 6958 0, 6959 false, /* HasDisjunctSubRegs */ 6960 true, /* CoveredBySubRegs */ 6961 hGPR_and_tGPRwithpcSuperclasses, 6962 nullptr 6963 }; 6964 6965 extern const TargetRegisterClass hGPR_and_tcGPRRegClass = { 6966 &ARMMCRegisterClasses[hGPR_and_tcGPRRegClassID], 6967 hGPR_and_tcGPRSubClassMask, 6968 SuperRegIdxSeqs + 9, 6969 LaneBitmask(0x00000001), 6970 0, 6971 false, /* HasDisjunctSubRegs */ 6972 true, /* CoveredBySubRegs */ 6973 hGPR_and_tcGPRSuperclasses, 6974 hGPR_and_tcGPRGetRawAllocationOrder 6975 }; 6976 6977 extern const TargetRegisterClass DPRRegClass = { 6978 &ARMMCRegisterClasses[DPRRegClassID], 6979 DPRSubClassMask, 6980 SuperRegIdxSeqs + 0, 6981 LaneBitmask(0x0000000C), 6982 0, 6983 true, /* HasDisjunctSubRegs */ 6984 false, /* CoveredBySubRegs */ 6985 DPRSuperclasses, 6986 DPRGetRawAllocationOrder 6987 }; 6988 6989 extern const TargetRegisterClass DPR_VFP2RegClass = { 6990 &ARMMCRegisterClasses[DPR_VFP2RegClassID], 6991 DPR_VFP2SubClassMask, 6992 SuperRegIdxSeqs + 0, 6993 LaneBitmask(0x0000000C), 6994 0, 6995 true, /* HasDisjunctSubRegs */ 6996 true, /* CoveredBySubRegs */ 6997 DPR_VFP2Superclasses, 6998 nullptr 6999 }; 7000 7001 extern const TargetRegisterClass DPR_8RegClass = { 7002 &ARMMCRegisterClasses[DPR_8RegClassID], 7003 DPR_8SubClassMask, 7004 SuperRegIdxSeqs + 0, 7005 LaneBitmask(0x0000000C), 7006 0, 7007 true, /* HasDisjunctSubRegs */ 7008 true, /* CoveredBySubRegs */ 7009 DPR_8Superclasses, 7010 nullptr 7011 }; 7012 7013 extern const TargetRegisterClass GPRPairRegClass = { 7014 &ARMMCRegisterClasses[GPRPairRegClassID], 7015 GPRPairSubClassMask, 7016 SuperRegIdxSeqs + 8, 7017 LaneBitmask(0x00000003), 7018 0, 7019 true, /* HasDisjunctSubRegs */ 7020 true, /* CoveredBySubRegs */ 7021 NullRegClasses, 7022 nullptr 7023 }; 7024 7025 extern const TargetRegisterClass GPRPairnospRegClass = { 7026 &ARMMCRegisterClasses[GPRPairnospRegClassID], 7027 GPRPairnospSubClassMask, 7028 SuperRegIdxSeqs + 8, 7029 LaneBitmask(0x00000003), 7030 0, 7031 true, /* HasDisjunctSubRegs */ 7032 true, /* CoveredBySubRegs */ 7033 GPRPairnospSuperclasses, 7034 nullptr 7035 }; 7036 7037 extern const TargetRegisterClass GPRPair_with_gsub_0_in_tGPRRegClass = { 7038 &ARMMCRegisterClasses[GPRPair_with_gsub_0_in_tGPRRegClassID], 7039 GPRPair_with_gsub_0_in_tGPRSubClassMask, 7040 SuperRegIdxSeqs + 8, 7041 LaneBitmask(0x00000003), 7042 0, 7043 true, /* HasDisjunctSubRegs */ 7044 true, /* CoveredBySubRegs */ 7045 GPRPair_with_gsub_0_in_tGPRSuperclasses, 7046 nullptr 7047 }; 7048 7049 extern const TargetRegisterClass GPRPair_with_gsub_0_in_hGPRRegClass = { 7050 &ARMMCRegisterClasses[GPRPair_with_gsub_0_in_hGPRRegClassID], 7051 GPRPair_with_gsub_0_in_hGPRSubClassMask, 7052 SuperRegIdxSeqs + 8, 7053 LaneBitmask(0x00000003), 7054 0, 7055 true, /* HasDisjunctSubRegs */ 7056 true, /* CoveredBySubRegs */ 7057 GPRPair_with_gsub_0_in_hGPRSuperclasses, 7058 nullptr 7059 }; 7060 7061 extern const TargetRegisterClass GPRPair_with_gsub_0_in_tcGPRRegClass = { 7062 &ARMMCRegisterClasses[GPRPair_with_gsub_0_in_tcGPRRegClassID], 7063 GPRPair_with_gsub_0_in_tcGPRSubClassMask, 7064 SuperRegIdxSeqs + 8, 7065 LaneBitmask(0x00000003), 7066 0, 7067 true, /* HasDisjunctSubRegs */ 7068 true, /* CoveredBySubRegs */ 7069 GPRPair_with_gsub_0_in_tcGPRSuperclasses, 7070 nullptr 7071 }; 7072 7073 extern const TargetRegisterClass GPRPair_with_gsub_1_in_tcGPRRegClass = { 7074 &ARMMCRegisterClasses[GPRPair_with_gsub_1_in_tcGPRRegClassID], 7075 GPRPair_with_gsub_1_in_tcGPRSubClassMask, 7076 SuperRegIdxSeqs + 8, 7077 LaneBitmask(0x00000003), 7078 0, 7079 true, /* HasDisjunctSubRegs */ 7080 true, /* CoveredBySubRegs */ 7081 GPRPair_with_gsub_1_in_tcGPRSuperclasses, 7082 nullptr 7083 }; 7084 7085 extern const TargetRegisterClass GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClass = { 7086 &ARMMCRegisterClasses[GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClassID], 7087 GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRSubClassMask, 7088 SuperRegIdxSeqs + 8, 7089 LaneBitmask(0x00000003), 7090 0, 7091 true, /* HasDisjunctSubRegs */ 7092 true, /* CoveredBySubRegs */ 7093 GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRSuperclasses, 7094 nullptr 7095 }; 7096 7097 extern const TargetRegisterClass GPRPair_with_gsub_1_in_GPRspRegClass = { 7098 &ARMMCRegisterClasses[GPRPair_with_gsub_1_in_GPRspRegClassID], 7099 GPRPair_with_gsub_1_in_GPRspSubClassMask, 7100 SuperRegIdxSeqs + 8, 7101 LaneBitmask(0x00000003), 7102 0, 7103 true, /* HasDisjunctSubRegs */ 7104 true, /* CoveredBySubRegs */ 7105 GPRPair_with_gsub_1_in_GPRspSuperclasses, 7106 nullptr 7107 }; 7108 7109 extern const TargetRegisterClass DPairSpcRegClass = { 7110 &ARMMCRegisterClasses[DPairSpcRegClassID], 7111 DPairSpcSubClassMask, 7112 SuperRegIdxSeqs + 58, 7113 LaneBitmask(0x000000CC), 7114 0, 7115 true, /* HasDisjunctSubRegs */ 7116 true, /* CoveredBySubRegs */ 7117 NullRegClasses, 7118 nullptr 7119 }; 7120 7121 extern const TargetRegisterClass DPairSpc_with_ssub_0RegClass = { 7122 &ARMMCRegisterClasses[DPairSpc_with_ssub_0RegClassID], 7123 DPairSpc_with_ssub_0SubClassMask, 7124 SuperRegIdxSeqs + 58, 7125 LaneBitmask(0x000000CC), 7126 0, 7127 true, /* HasDisjunctSubRegs */ 7128 true, /* CoveredBySubRegs */ 7129 DPairSpc_with_ssub_0Superclasses, 7130 nullptr 7131 }; 7132 7133 extern const TargetRegisterClass DPairSpc_with_ssub_4RegClass = { 7134 &ARMMCRegisterClasses[DPairSpc_with_ssub_4RegClassID], 7135 DPairSpc_with_ssub_4SubClassMask, 7136 SuperRegIdxSeqs + 58, 7137 LaneBitmask(0x000000CC), 7138 0, 7139 true, /* HasDisjunctSubRegs */ 7140 true, /* CoveredBySubRegs */ 7141 DPairSpc_with_ssub_4Superclasses, 7142 nullptr 7143 }; 7144 7145 extern const TargetRegisterClass DPairSpc_with_dsub_0_in_DPR_8RegClass = { 7146 &ARMMCRegisterClasses[DPairSpc_with_dsub_0_in_DPR_8RegClassID], 7147 DPairSpc_with_dsub_0_in_DPR_8SubClassMask, 7148 SuperRegIdxSeqs + 58, 7149 LaneBitmask(0x000000CC), 7150 0, 7151 true, /* HasDisjunctSubRegs */ 7152 true, /* CoveredBySubRegs */ 7153 DPairSpc_with_dsub_0_in_DPR_8Superclasses, 7154 nullptr 7155 }; 7156 7157 extern const TargetRegisterClass DPairSpc_with_dsub_2_in_DPR_8RegClass = { 7158 &ARMMCRegisterClasses[DPairSpc_with_dsub_2_in_DPR_8RegClassID], 7159 DPairSpc_with_dsub_2_in_DPR_8SubClassMask, 7160 SuperRegIdxSeqs + 58, 7161 LaneBitmask(0x000000CC), 7162 0, 7163 true, /* HasDisjunctSubRegs */ 7164 true, /* CoveredBySubRegs */ 7165 DPairSpc_with_dsub_2_in_DPR_8Superclasses, 7166 nullptr 7167 }; 7168 7169 extern const TargetRegisterClass DPairRegClass = { 7170 &ARMMCRegisterClasses[DPairRegClassID], 7171 DPairSubClassMask, 7172 SuperRegIdxSeqs + 77, 7173 LaneBitmask(0x0000003C), 7174 0, 7175 true, /* HasDisjunctSubRegs */ 7176 true, /* CoveredBySubRegs */ 7177 NullRegClasses, 7178 DPairGetRawAllocationOrder 7179 }; 7180 7181 extern const TargetRegisterClass DPair_with_ssub_0RegClass = { 7182 &ARMMCRegisterClasses[DPair_with_ssub_0RegClassID], 7183 DPair_with_ssub_0SubClassMask, 7184 SuperRegIdxSeqs + 77, 7185 LaneBitmask(0x0000003C), 7186 0, 7187 true, /* HasDisjunctSubRegs */ 7188 true, /* CoveredBySubRegs */ 7189 DPair_with_ssub_0Superclasses, 7190 DPair_with_ssub_0GetRawAllocationOrder 7191 }; 7192 7193 extern const TargetRegisterClass QPRRegClass = { 7194 &ARMMCRegisterClasses[QPRRegClassID], 7195 QPRSubClassMask, 7196 SuperRegIdxSeqs + 39, 7197 LaneBitmask(0x0000003C), 7198 0, 7199 true, /* HasDisjunctSubRegs */ 7200 true, /* CoveredBySubRegs */ 7201 QPRSuperclasses, 7202 QPRGetRawAllocationOrder 7203 }; 7204 7205 extern const TargetRegisterClass DPair_with_ssub_2RegClass = { 7206 &ARMMCRegisterClasses[DPair_with_ssub_2RegClassID], 7207 DPair_with_ssub_2SubClassMask, 7208 SuperRegIdxSeqs + 77, 7209 LaneBitmask(0x0000003C), 7210 0, 7211 true, /* HasDisjunctSubRegs */ 7212 true, /* CoveredBySubRegs */ 7213 DPair_with_ssub_2Superclasses, 7214 DPair_with_ssub_2GetRawAllocationOrder 7215 }; 7216 7217 extern const TargetRegisterClass DPair_with_dsub_0_in_DPR_8RegClass = { 7218 &ARMMCRegisterClasses[DPair_with_dsub_0_in_DPR_8RegClassID], 7219 DPair_with_dsub_0_in_DPR_8SubClassMask, 7220 SuperRegIdxSeqs + 77, 7221 LaneBitmask(0x0000003C), 7222 0, 7223 true, /* HasDisjunctSubRegs */ 7224 true, /* CoveredBySubRegs */ 7225 DPair_with_dsub_0_in_DPR_8Superclasses, 7226 DPair_with_dsub_0_in_DPR_8GetRawAllocationOrder 7227 }; 7228 7229 extern const TargetRegisterClass MQPRRegClass = { 7230 &ARMMCRegisterClasses[MQPRRegClassID], 7231 MQPRSubClassMask, 7232 SuperRegIdxSeqs + 39, 7233 LaneBitmask(0x0000003C), 7234 0, 7235 true, /* HasDisjunctSubRegs */ 7236 true, /* CoveredBySubRegs */ 7237 MQPRSuperclasses, 7238 nullptr 7239 }; 7240 7241 extern const TargetRegisterClass QPR_VFP2RegClass = { 7242 &ARMMCRegisterClasses[QPR_VFP2RegClassID], 7243 QPR_VFP2SubClassMask, 7244 SuperRegIdxSeqs + 39, 7245 LaneBitmask(0x0000003C), 7246 0, 7247 true, /* HasDisjunctSubRegs */ 7248 true, /* CoveredBySubRegs */ 7249 QPR_VFP2Superclasses, 7250 nullptr 7251 }; 7252 7253 extern const TargetRegisterClass DPair_with_dsub_1_in_DPR_8RegClass = { 7254 &ARMMCRegisterClasses[DPair_with_dsub_1_in_DPR_8RegClassID], 7255 DPair_with_dsub_1_in_DPR_8SubClassMask, 7256 SuperRegIdxSeqs + 77, 7257 LaneBitmask(0x0000003C), 7258 0, 7259 true, /* HasDisjunctSubRegs */ 7260 true, /* CoveredBySubRegs */ 7261 DPair_with_dsub_1_in_DPR_8Superclasses, 7262 DPair_with_dsub_1_in_DPR_8GetRawAllocationOrder 7263 }; 7264 7265 extern const TargetRegisterClass QPR_8RegClass = { 7266 &ARMMCRegisterClasses[QPR_8RegClassID], 7267 QPR_8SubClassMask, 7268 SuperRegIdxSeqs + 39, 7269 LaneBitmask(0x0000003C), 7270 0, 7271 true, /* HasDisjunctSubRegs */ 7272 true, /* CoveredBySubRegs */ 7273 QPR_8Superclasses, 7274 nullptr 7275 }; 7276 7277 extern const TargetRegisterClass DTripleRegClass = { 7278 &ARMMCRegisterClasses[DTripleRegClassID], 7279 DTripleSubClassMask, 7280 SuperRegIdxSeqs + 70, 7281 LaneBitmask(0x000000FC), 7282 0, 7283 true, /* HasDisjunctSubRegs */ 7284 true, /* CoveredBySubRegs */ 7285 NullRegClasses, 7286 nullptr 7287 }; 7288 7289 extern const TargetRegisterClass DTripleSpcRegClass = { 7290 &ARMMCRegisterClasses[DTripleSpcRegClassID], 7291 DTripleSpcSubClassMask, 7292 SuperRegIdxSeqs + 45, 7293 LaneBitmask(0x00000CCC), 7294 0, 7295 true, /* HasDisjunctSubRegs */ 7296 true, /* CoveredBySubRegs */ 7297 NullRegClasses, 7298 nullptr 7299 }; 7300 7301 extern const TargetRegisterClass DTripleSpc_with_ssub_0RegClass = { 7302 &ARMMCRegisterClasses[DTripleSpc_with_ssub_0RegClassID], 7303 DTripleSpc_with_ssub_0SubClassMask, 7304 SuperRegIdxSeqs + 45, 7305 LaneBitmask(0x00000CCC), 7306 0, 7307 true, /* HasDisjunctSubRegs */ 7308 true, /* CoveredBySubRegs */ 7309 DTripleSpc_with_ssub_0Superclasses, 7310 nullptr 7311 }; 7312 7313 extern const TargetRegisterClass DTriple_with_ssub_0RegClass = { 7314 &ARMMCRegisterClasses[DTriple_with_ssub_0RegClassID], 7315 DTriple_with_ssub_0SubClassMask, 7316 SuperRegIdxSeqs + 70, 7317 LaneBitmask(0x000000FC), 7318 0, 7319 true, /* HasDisjunctSubRegs */ 7320 true, /* CoveredBySubRegs */ 7321 DTriple_with_ssub_0Superclasses, 7322 nullptr 7323 }; 7324 7325 extern const TargetRegisterClass DTriple_with_qsub_0_in_QPRRegClass = { 7326 &ARMMCRegisterClasses[DTriple_with_qsub_0_in_QPRRegClassID], 7327 DTriple_with_qsub_0_in_QPRSubClassMask, 7328 SuperRegIdxSeqs + 53, 7329 LaneBitmask(0x000000FC), 7330 0, 7331 true, /* HasDisjunctSubRegs */ 7332 true, /* CoveredBySubRegs */ 7333 DTriple_with_qsub_0_in_QPRSuperclasses, 7334 nullptr 7335 }; 7336 7337 extern const TargetRegisterClass DTriple_with_ssub_2RegClass = { 7338 &ARMMCRegisterClasses[DTriple_with_ssub_2RegClassID], 7339 DTriple_with_ssub_2SubClassMask, 7340 SuperRegIdxSeqs + 70, 7341 LaneBitmask(0x000000FC), 7342 0, 7343 true, /* HasDisjunctSubRegs */ 7344 true, /* CoveredBySubRegs */ 7345 DTriple_with_ssub_2Superclasses, 7346 nullptr 7347 }; 7348 7349 extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = { 7350 &ARMMCRegisterClasses[DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID], 7351 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask, 7352 SuperRegIdxSeqs + 65, 7353 LaneBitmask(0x000000FC), 7354 0, 7355 true, /* HasDisjunctSubRegs */ 7356 true, /* CoveredBySubRegs */ 7357 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses, 7358 nullptr 7359 }; 7360 7361 extern const TargetRegisterClass DTripleSpc_with_ssub_4RegClass = { 7362 &ARMMCRegisterClasses[DTripleSpc_with_ssub_4RegClassID], 7363 DTripleSpc_with_ssub_4SubClassMask, 7364 SuperRegIdxSeqs + 45, 7365 LaneBitmask(0x00000CCC), 7366 0, 7367 true, /* HasDisjunctSubRegs */ 7368 true, /* CoveredBySubRegs */ 7369 DTripleSpc_with_ssub_4Superclasses, 7370 nullptr 7371 }; 7372 7373 extern const TargetRegisterClass DTriple_with_ssub_4RegClass = { 7374 &ARMMCRegisterClasses[DTriple_with_ssub_4RegClassID], 7375 DTriple_with_ssub_4SubClassMask, 7376 SuperRegIdxSeqs + 70, 7377 LaneBitmask(0x000000FC), 7378 0, 7379 true, /* HasDisjunctSubRegs */ 7380 true, /* CoveredBySubRegs */ 7381 DTriple_with_ssub_4Superclasses, 7382 nullptr 7383 }; 7384 7385 extern const TargetRegisterClass DTripleSpc_with_ssub_8RegClass = { 7386 &ARMMCRegisterClasses[DTripleSpc_with_ssub_8RegClassID], 7387 DTripleSpc_with_ssub_8SubClassMask, 7388 SuperRegIdxSeqs + 45, 7389 LaneBitmask(0x00000CCC), 7390 0, 7391 true, /* HasDisjunctSubRegs */ 7392 true, /* CoveredBySubRegs */ 7393 DTripleSpc_with_ssub_8Superclasses, 7394 nullptr 7395 }; 7396 7397 extern const TargetRegisterClass DTripleSpc_with_dsub_0_in_DPR_8RegClass = { 7398 &ARMMCRegisterClasses[DTripleSpc_with_dsub_0_in_DPR_8RegClassID], 7399 DTripleSpc_with_dsub_0_in_DPR_8SubClassMask, 7400 SuperRegIdxSeqs + 45, 7401 LaneBitmask(0x00000CCC), 7402 0, 7403 true, /* HasDisjunctSubRegs */ 7404 true, /* CoveredBySubRegs */ 7405 DTripleSpc_with_dsub_0_in_DPR_8Superclasses, 7406 nullptr 7407 }; 7408 7409 extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8RegClass = { 7410 &ARMMCRegisterClasses[DTriple_with_dsub_0_in_DPR_8RegClassID], 7411 DTriple_with_dsub_0_in_DPR_8SubClassMask, 7412 SuperRegIdxSeqs + 70, 7413 LaneBitmask(0x000000FC), 7414 0, 7415 true, /* HasDisjunctSubRegs */ 7416 true, /* CoveredBySubRegs */ 7417 DTriple_with_dsub_0_in_DPR_8Superclasses, 7418 nullptr 7419 }; 7420 7421 extern const TargetRegisterClass DTriple_with_qsub_0_in_MQPRRegClass = { 7422 &ARMMCRegisterClasses[DTriple_with_qsub_0_in_MQPRRegClassID], 7423 DTriple_with_qsub_0_in_MQPRSubClassMask, 7424 SuperRegIdxSeqs + 53, 7425 LaneBitmask(0x000000FC), 7426 0, 7427 true, /* HasDisjunctSubRegs */ 7428 true, /* CoveredBySubRegs */ 7429 DTriple_with_qsub_0_in_MQPRSuperclasses, 7430 nullptr 7431 }; 7432 7433 extern const TargetRegisterClass DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = { 7434 &ARMMCRegisterClasses[DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID], 7435 DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask, 7436 SuperRegIdxSeqs + 65, 7437 LaneBitmask(0x000000FC), 7438 0, 7439 true, /* HasDisjunctSubRegs */ 7440 true, /* CoveredBySubRegs */ 7441 DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses, 7442 nullptr 7443 }; 7444 7445 extern const TargetRegisterClass DTriple_with_dsub_1_in_DPR_8RegClass = { 7446 &ARMMCRegisterClasses[DTriple_with_dsub_1_in_DPR_8RegClassID], 7447 DTriple_with_dsub_1_in_DPR_8SubClassMask, 7448 SuperRegIdxSeqs + 70, 7449 LaneBitmask(0x000000FC), 7450 0, 7451 true, /* HasDisjunctSubRegs */ 7452 true, /* CoveredBySubRegs */ 7453 DTriple_with_dsub_1_in_DPR_8Superclasses, 7454 nullptr 7455 }; 7456 7457 extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass = { 7458 &ARMMCRegisterClasses[DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID], 7459 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask, 7460 SuperRegIdxSeqs + 65, 7461 LaneBitmask(0x000000FC), 7462 0, 7463 true, /* HasDisjunctSubRegs */ 7464 true, /* CoveredBySubRegs */ 7465 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses, 7466 nullptr 7467 }; 7468 7469 extern const TargetRegisterClass DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClass = { 7470 &ARMMCRegisterClasses[DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClassID], 7471 DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRSubClassMask, 7472 SuperRegIdxSeqs + 53, 7473 LaneBitmask(0x000000FC), 7474 0, 7475 true, /* HasDisjunctSubRegs */ 7476 true, /* CoveredBySubRegs */ 7477 DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRSuperclasses, 7478 nullptr 7479 }; 7480 7481 extern const TargetRegisterClass DTripleSpc_with_dsub_2_in_DPR_8RegClass = { 7482 &ARMMCRegisterClasses[DTripleSpc_with_dsub_2_in_DPR_8RegClassID], 7483 DTripleSpc_with_dsub_2_in_DPR_8SubClassMask, 7484 SuperRegIdxSeqs + 45, 7485 LaneBitmask(0x00000CCC), 7486 0, 7487 true, /* HasDisjunctSubRegs */ 7488 true, /* CoveredBySubRegs */ 7489 DTripleSpc_with_dsub_2_in_DPR_8Superclasses, 7490 nullptr 7491 }; 7492 7493 extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8RegClass = { 7494 &ARMMCRegisterClasses[DTriple_with_dsub_2_in_DPR_8RegClassID], 7495 DTriple_with_dsub_2_in_DPR_8SubClassMask, 7496 SuperRegIdxSeqs + 70, 7497 LaneBitmask(0x000000FC), 7498 0, 7499 true, /* HasDisjunctSubRegs */ 7500 true, /* CoveredBySubRegs */ 7501 DTriple_with_dsub_2_in_DPR_8Superclasses, 7502 nullptr 7503 }; 7504 7505 extern const TargetRegisterClass DTripleSpc_with_dsub_4_in_DPR_8RegClass = { 7506 &ARMMCRegisterClasses[DTripleSpc_with_dsub_4_in_DPR_8RegClassID], 7507 DTripleSpc_with_dsub_4_in_DPR_8SubClassMask, 7508 SuperRegIdxSeqs + 45, 7509 LaneBitmask(0x00000CCC), 7510 0, 7511 true, /* HasDisjunctSubRegs */ 7512 true, /* CoveredBySubRegs */ 7513 DTripleSpc_with_dsub_4_in_DPR_8Superclasses, 7514 nullptr 7515 }; 7516 7517 extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass = { 7518 &ARMMCRegisterClasses[DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID], 7519 DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask, 7520 SuperRegIdxSeqs + 65, 7521 LaneBitmask(0x000000FC), 7522 0, 7523 true, /* HasDisjunctSubRegs */ 7524 true, /* CoveredBySubRegs */ 7525 DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses, 7526 nullptr 7527 }; 7528 7529 extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_8RegClass = { 7530 &ARMMCRegisterClasses[DTriple_with_qsub_0_in_QPR_8RegClassID], 7531 DTriple_with_qsub_0_in_QPR_8SubClassMask, 7532 SuperRegIdxSeqs + 53, 7533 LaneBitmask(0x000000FC), 7534 0, 7535 true, /* HasDisjunctSubRegs */ 7536 true, /* CoveredBySubRegs */ 7537 DTriple_with_qsub_0_in_QPR_8Superclasses, 7538 nullptr 7539 }; 7540 7541 extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRRegClass = { 7542 &ARMMCRegisterClasses[DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRRegClassID], 7543 DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRSubClassMask, 7544 SuperRegIdxSeqs + 53, 7545 LaneBitmask(0x000000FC), 7546 0, 7547 true, /* HasDisjunctSubRegs */ 7548 true, /* CoveredBySubRegs */ 7549 DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRSuperclasses, 7550 nullptr 7551 }; 7552 7553 extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass = { 7554 &ARMMCRegisterClasses[DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID], 7555 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask, 7556 SuperRegIdxSeqs + 65, 7557 LaneBitmask(0x000000FC), 7558 0, 7559 true, /* HasDisjunctSubRegs */ 7560 true, /* CoveredBySubRegs */ 7561 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses, 7562 nullptr 7563 }; 7564 7565 extern const TargetRegisterClass DQuadSpcRegClass = { 7566 &ARMMCRegisterClasses[DQuadSpcRegClassID], 7567 DQuadSpcSubClassMask, 7568 SuperRegIdxSeqs + 45, 7569 LaneBitmask(0x00000CCC), 7570 0, 7571 true, /* HasDisjunctSubRegs */ 7572 true, /* CoveredBySubRegs */ 7573 DQuadSpcSuperclasses, 7574 nullptr 7575 }; 7576 7577 extern const TargetRegisterClass DQuadSpc_with_ssub_0RegClass = { 7578 &ARMMCRegisterClasses[DQuadSpc_with_ssub_0RegClassID], 7579 DQuadSpc_with_ssub_0SubClassMask, 7580 SuperRegIdxSeqs + 45, 7581 LaneBitmask(0x00000CCC), 7582 0, 7583 true, /* HasDisjunctSubRegs */ 7584 true, /* CoveredBySubRegs */ 7585 DQuadSpc_with_ssub_0Superclasses, 7586 nullptr 7587 }; 7588 7589 extern const TargetRegisterClass DQuadSpc_with_ssub_4RegClass = { 7590 &ARMMCRegisterClasses[DQuadSpc_with_ssub_4RegClassID], 7591 DQuadSpc_with_ssub_4SubClassMask, 7592 SuperRegIdxSeqs + 45, 7593 LaneBitmask(0x00000CCC), 7594 0, 7595 true, /* HasDisjunctSubRegs */ 7596 true, /* CoveredBySubRegs */ 7597 DQuadSpc_with_ssub_4Superclasses, 7598 nullptr 7599 }; 7600 7601 extern const TargetRegisterClass DQuadSpc_with_ssub_8RegClass = { 7602 &ARMMCRegisterClasses[DQuadSpc_with_ssub_8RegClassID], 7603 DQuadSpc_with_ssub_8SubClassMask, 7604 SuperRegIdxSeqs + 45, 7605 LaneBitmask(0x00000CCC), 7606 0, 7607 true, /* HasDisjunctSubRegs */ 7608 true, /* CoveredBySubRegs */ 7609 DQuadSpc_with_ssub_8Superclasses, 7610 nullptr 7611 }; 7612 7613 extern const TargetRegisterClass DQuadSpc_with_dsub_0_in_DPR_8RegClass = { 7614 &ARMMCRegisterClasses[DQuadSpc_with_dsub_0_in_DPR_8RegClassID], 7615 DQuadSpc_with_dsub_0_in_DPR_8SubClassMask, 7616 SuperRegIdxSeqs + 45, 7617 LaneBitmask(0x00000CCC), 7618 0, 7619 true, /* HasDisjunctSubRegs */ 7620 true, /* CoveredBySubRegs */ 7621 DQuadSpc_with_dsub_0_in_DPR_8Superclasses, 7622 nullptr 7623 }; 7624 7625 extern const TargetRegisterClass DQuadSpc_with_dsub_2_in_DPR_8RegClass = { 7626 &ARMMCRegisterClasses[DQuadSpc_with_dsub_2_in_DPR_8RegClassID], 7627 DQuadSpc_with_dsub_2_in_DPR_8SubClassMask, 7628 SuperRegIdxSeqs + 45, 7629 LaneBitmask(0x00000CCC), 7630 0, 7631 true, /* HasDisjunctSubRegs */ 7632 true, /* CoveredBySubRegs */ 7633 DQuadSpc_with_dsub_2_in_DPR_8Superclasses, 7634 nullptr 7635 }; 7636 7637 extern const TargetRegisterClass DQuadSpc_with_dsub_4_in_DPR_8RegClass = { 7638 &ARMMCRegisterClasses[DQuadSpc_with_dsub_4_in_DPR_8RegClassID], 7639 DQuadSpc_with_dsub_4_in_DPR_8SubClassMask, 7640 SuperRegIdxSeqs + 45, 7641 LaneBitmask(0x00000CCC), 7642 0, 7643 true, /* HasDisjunctSubRegs */ 7644 true, /* CoveredBySubRegs */ 7645 DQuadSpc_with_dsub_4_in_DPR_8Superclasses, 7646 nullptr 7647 }; 7648 7649 extern const TargetRegisterClass DQuadRegClass = { 7650 &ARMMCRegisterClasses[DQuadRegClassID], 7651 DQuadSubClassMask, 7652 SuperRegIdxSeqs + 89, 7653 LaneBitmask(0x000003FC), 7654 0, 7655 true, /* HasDisjunctSubRegs */ 7656 true, /* CoveredBySubRegs */ 7657 NullRegClasses, 7658 nullptr 7659 }; 7660 7661 extern const TargetRegisterClass DQuad_with_ssub_0RegClass = { 7662 &ARMMCRegisterClasses[DQuad_with_ssub_0RegClassID], 7663 DQuad_with_ssub_0SubClassMask, 7664 SuperRegIdxSeqs + 89, 7665 LaneBitmask(0x000003FC), 7666 0, 7667 true, /* HasDisjunctSubRegs */ 7668 true, /* CoveredBySubRegs */ 7669 DQuad_with_ssub_0Superclasses, 7670 nullptr 7671 }; 7672 7673 extern const TargetRegisterClass DQuad_with_ssub_2RegClass = { 7674 &ARMMCRegisterClasses[DQuad_with_ssub_2RegClassID], 7675 DQuad_with_ssub_2SubClassMask, 7676 SuperRegIdxSeqs + 89, 7677 LaneBitmask(0x000003FC), 7678 0, 7679 true, /* HasDisjunctSubRegs */ 7680 true, /* CoveredBySubRegs */ 7681 DQuad_with_ssub_2Superclasses, 7682 nullptr 7683 }; 7684 7685 extern const TargetRegisterClass QQPRRegClass = { 7686 &ARMMCRegisterClasses[QQPRRegClassID], 7687 QQPRSubClassMask, 7688 SuperRegIdxSeqs + 85, 7689 LaneBitmask(0x000003FC), 7690 0, 7691 true, /* HasDisjunctSubRegs */ 7692 true, /* CoveredBySubRegs */ 7693 QQPRSuperclasses, 7694 QQPRGetRawAllocationOrder 7695 }; 7696 7697 extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = { 7698 &ARMMCRegisterClasses[DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID], 7699 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask, 7700 SuperRegIdxSeqs + 50, 7701 LaneBitmask(0x000003FC), 7702 0, 7703 true, /* HasDisjunctSubRegs */ 7704 true, /* CoveredBySubRegs */ 7705 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses, 7706 nullptr 7707 }; 7708 7709 extern const TargetRegisterClass DQuad_with_ssub_4RegClass = { 7710 &ARMMCRegisterClasses[DQuad_with_ssub_4RegClassID], 7711 DQuad_with_ssub_4SubClassMask, 7712 SuperRegIdxSeqs + 89, 7713 LaneBitmask(0x000003FC), 7714 0, 7715 true, /* HasDisjunctSubRegs */ 7716 true, /* CoveredBySubRegs */ 7717 DQuad_with_ssub_4Superclasses, 7718 nullptr 7719 }; 7720 7721 extern const TargetRegisterClass DQuad_with_ssub_6RegClass = { 7722 &ARMMCRegisterClasses[DQuad_with_ssub_6RegClassID], 7723 DQuad_with_ssub_6SubClassMask, 7724 SuperRegIdxSeqs + 89, 7725 LaneBitmask(0x000003FC), 7726 0, 7727 true, /* HasDisjunctSubRegs */ 7728 true, /* CoveredBySubRegs */ 7729 DQuad_with_ssub_6Superclasses, 7730 nullptr 7731 }; 7732 7733 extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8RegClass = { 7734 &ARMMCRegisterClasses[DQuad_with_dsub_0_in_DPR_8RegClassID], 7735 DQuad_with_dsub_0_in_DPR_8SubClassMask, 7736 SuperRegIdxSeqs + 89, 7737 LaneBitmask(0x000003FC), 7738 0, 7739 true, /* HasDisjunctSubRegs */ 7740 true, /* CoveredBySubRegs */ 7741 DQuad_with_dsub_0_in_DPR_8Superclasses, 7742 nullptr 7743 }; 7744 7745 extern const TargetRegisterClass DQuad_with_qsub_0_in_MQPRRegClass = { 7746 &ARMMCRegisterClasses[DQuad_with_qsub_0_in_MQPRRegClassID], 7747 DQuad_with_qsub_0_in_MQPRSubClassMask, 7748 SuperRegIdxSeqs + 85, 7749 LaneBitmask(0x000003FC), 7750 0, 7751 true, /* HasDisjunctSubRegs */ 7752 true, /* CoveredBySubRegs */ 7753 DQuad_with_qsub_0_in_MQPRSuperclasses, 7754 DQuad_with_qsub_0_in_MQPRGetRawAllocationOrder 7755 }; 7756 7757 extern const TargetRegisterClass DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = { 7758 &ARMMCRegisterClasses[DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID], 7759 DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask, 7760 SuperRegIdxSeqs + 50, 7761 LaneBitmask(0x000003FC), 7762 0, 7763 true, /* HasDisjunctSubRegs */ 7764 true, /* CoveredBySubRegs */ 7765 DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses, 7766 nullptr 7767 }; 7768 7769 extern const TargetRegisterClass DQuad_with_dsub_1_in_DPR_8RegClass = { 7770 &ARMMCRegisterClasses[DQuad_with_dsub_1_in_DPR_8RegClassID], 7771 DQuad_with_dsub_1_in_DPR_8SubClassMask, 7772 SuperRegIdxSeqs + 89, 7773 LaneBitmask(0x000003FC), 7774 0, 7775 true, /* HasDisjunctSubRegs */ 7776 true, /* CoveredBySubRegs */ 7777 DQuad_with_dsub_1_in_DPR_8Superclasses, 7778 nullptr 7779 }; 7780 7781 extern const TargetRegisterClass DQuad_with_qsub_1_in_MQPRRegClass = { 7782 &ARMMCRegisterClasses[DQuad_with_qsub_1_in_MQPRRegClassID], 7783 DQuad_with_qsub_1_in_MQPRSubClassMask, 7784 SuperRegIdxSeqs + 85, 7785 LaneBitmask(0x000003FC), 7786 0, 7787 true, /* HasDisjunctSubRegs */ 7788 true, /* CoveredBySubRegs */ 7789 DQuad_with_qsub_1_in_MQPRSuperclasses, 7790 DQuad_with_qsub_1_in_MQPRGetRawAllocationOrder 7791 }; 7792 7793 extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass = { 7794 &ARMMCRegisterClasses[DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID], 7795 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask, 7796 SuperRegIdxSeqs + 50, 7797 LaneBitmask(0x000003FC), 7798 0, 7799 true, /* HasDisjunctSubRegs */ 7800 true, /* CoveredBySubRegs */ 7801 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses, 7802 nullptr 7803 }; 7804 7805 extern const TargetRegisterClass DQuad_with_dsub_2_in_DPR_8RegClass = { 7806 &ARMMCRegisterClasses[DQuad_with_dsub_2_in_DPR_8RegClassID], 7807 DQuad_with_dsub_2_in_DPR_8SubClassMask, 7808 SuperRegIdxSeqs + 89, 7809 LaneBitmask(0x000003FC), 7810 0, 7811 true, /* HasDisjunctSubRegs */ 7812 true, /* CoveredBySubRegs */ 7813 DQuad_with_dsub_2_in_DPR_8Superclasses, 7814 nullptr 7815 }; 7816 7817 extern const TargetRegisterClass DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass = { 7818 &ARMMCRegisterClasses[DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID], 7819 DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask, 7820 SuperRegIdxSeqs + 50, 7821 LaneBitmask(0x000003FC), 7822 0, 7823 true, /* HasDisjunctSubRegs */ 7824 true, /* CoveredBySubRegs */ 7825 DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses, 7826 nullptr 7827 }; 7828 7829 extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8RegClass = { 7830 &ARMMCRegisterClasses[DQuad_with_dsub_3_in_DPR_8RegClassID], 7831 DQuad_with_dsub_3_in_DPR_8SubClassMask, 7832 SuperRegIdxSeqs + 89, 7833 LaneBitmask(0x000003FC), 7834 0, 7835 true, /* HasDisjunctSubRegs */ 7836 true, /* CoveredBySubRegs */ 7837 DQuad_with_dsub_3_in_DPR_8Superclasses, 7838 nullptr 7839 }; 7840 7841 extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass = { 7842 &ARMMCRegisterClasses[DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID], 7843 DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask, 7844 SuperRegIdxSeqs + 50, 7845 LaneBitmask(0x000003FC), 7846 0, 7847 true, /* HasDisjunctSubRegs */ 7848 true, /* CoveredBySubRegs */ 7849 DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses, 7850 nullptr 7851 }; 7852 7853 extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_8RegClass = { 7854 &ARMMCRegisterClasses[DQuad_with_qsub_0_in_QPR_8RegClassID], 7855 DQuad_with_qsub_0_in_QPR_8SubClassMask, 7856 SuperRegIdxSeqs + 85, 7857 LaneBitmask(0x000003FC), 7858 0, 7859 true, /* HasDisjunctSubRegs */ 7860 true, /* CoveredBySubRegs */ 7861 DQuad_with_qsub_0_in_QPR_8Superclasses, 7862 DQuad_with_qsub_0_in_QPR_8GetRawAllocationOrder 7863 }; 7864 7865 extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_8RegClass = { 7866 &ARMMCRegisterClasses[DQuad_with_qsub_1_in_QPR_8RegClassID], 7867 DQuad_with_qsub_1_in_QPR_8SubClassMask, 7868 SuperRegIdxSeqs + 85, 7869 LaneBitmask(0x000003FC), 7870 0, 7871 true, /* HasDisjunctSubRegs */ 7872 true, /* CoveredBySubRegs */ 7873 DQuad_with_qsub_1_in_QPR_8Superclasses, 7874 DQuad_with_qsub_1_in_QPR_8GetRawAllocationOrder 7875 }; 7876 7877 extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass = { 7878 &ARMMCRegisterClasses[DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID], 7879 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask, 7880 SuperRegIdxSeqs + 50, 7881 LaneBitmask(0x000003FC), 7882 0, 7883 true, /* HasDisjunctSubRegs */ 7884 true, /* CoveredBySubRegs */ 7885 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses, 7886 nullptr 7887 }; 7888 7889 extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass = { 7890 &ARMMCRegisterClasses[DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID], 7891 DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask, 7892 SuperRegIdxSeqs + 50, 7893 LaneBitmask(0x000003FC), 7894 0, 7895 true, /* HasDisjunctSubRegs */ 7896 true, /* CoveredBySubRegs */ 7897 DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses, 7898 nullptr 7899 }; 7900 7901 extern const TargetRegisterClass QQQQPRRegClass = { 7902 &ARMMCRegisterClasses[QQQQPRRegClassID], 7903 QQQQPRSubClassMask, 7904 SuperRegIdxSeqs + 8, 7905 LaneBitmask(0x0003FFFC), 7906 0, 7907 true, /* HasDisjunctSubRegs */ 7908 true, /* CoveredBySubRegs */ 7909 NullRegClasses, 7910 QQQQPRGetRawAllocationOrder 7911 }; 7912 7913 extern const TargetRegisterClass QQQQPR_with_ssub_0RegClass = { 7914 &ARMMCRegisterClasses[QQQQPR_with_ssub_0RegClassID], 7915 QQQQPR_with_ssub_0SubClassMask, 7916 SuperRegIdxSeqs + 8, 7917 LaneBitmask(0x0003FFFC), 7918 0, 7919 true, /* HasDisjunctSubRegs */ 7920 true, /* CoveredBySubRegs */ 7921 QQQQPR_with_ssub_0Superclasses, 7922 QQQQPR_with_ssub_0GetRawAllocationOrder 7923 }; 7924 7925 extern const TargetRegisterClass QQQQPR_with_ssub_4RegClass = { 7926 &ARMMCRegisterClasses[QQQQPR_with_ssub_4RegClassID], 7927 QQQQPR_with_ssub_4SubClassMask, 7928 SuperRegIdxSeqs + 8, 7929 LaneBitmask(0x0003FFFC), 7930 0, 7931 true, /* HasDisjunctSubRegs */ 7932 true, /* CoveredBySubRegs */ 7933 QQQQPR_with_ssub_4Superclasses, 7934 QQQQPR_with_ssub_4GetRawAllocationOrder 7935 }; 7936 7937 extern const TargetRegisterClass QQQQPR_with_ssub_8RegClass = { 7938 &ARMMCRegisterClasses[QQQQPR_with_ssub_8RegClassID], 7939 QQQQPR_with_ssub_8SubClassMask, 7940 SuperRegIdxSeqs + 8, 7941 LaneBitmask(0x0003FFFC), 7942 0, 7943 true, /* HasDisjunctSubRegs */ 7944 true, /* CoveredBySubRegs */ 7945 QQQQPR_with_ssub_8Superclasses, 7946 QQQQPR_with_ssub_8GetRawAllocationOrder 7947 }; 7948 7949 extern const TargetRegisterClass QQQQPR_with_ssub_12RegClass = { 7950 &ARMMCRegisterClasses[QQQQPR_with_ssub_12RegClassID], 7951 QQQQPR_with_ssub_12SubClassMask, 7952 SuperRegIdxSeqs + 8, 7953 LaneBitmask(0x0003FFFC), 7954 0, 7955 true, /* HasDisjunctSubRegs */ 7956 true, /* CoveredBySubRegs */ 7957 QQQQPR_with_ssub_12Superclasses, 7958 QQQQPR_with_ssub_12GetRawAllocationOrder 7959 }; 7960 7961 extern const TargetRegisterClass QQQQPR_with_dsub_0_in_DPR_8RegClass = { 7962 &ARMMCRegisterClasses[QQQQPR_with_dsub_0_in_DPR_8RegClassID], 7963 QQQQPR_with_dsub_0_in_DPR_8SubClassMask, 7964 SuperRegIdxSeqs + 8, 7965 LaneBitmask(0x0003FFFC), 7966 0, 7967 true, /* HasDisjunctSubRegs */ 7968 true, /* CoveredBySubRegs */ 7969 QQQQPR_with_dsub_0_in_DPR_8Superclasses, 7970 QQQQPR_with_dsub_0_in_DPR_8GetRawAllocationOrder 7971 }; 7972 7973 extern const TargetRegisterClass QQQQPR_with_dsub_2_in_DPR_8RegClass = { 7974 &ARMMCRegisterClasses[QQQQPR_with_dsub_2_in_DPR_8RegClassID], 7975 QQQQPR_with_dsub_2_in_DPR_8SubClassMask, 7976 SuperRegIdxSeqs + 8, 7977 LaneBitmask(0x0003FFFC), 7978 0, 7979 true, /* HasDisjunctSubRegs */ 7980 true, /* CoveredBySubRegs */ 7981 QQQQPR_with_dsub_2_in_DPR_8Superclasses, 7982 QQQQPR_with_dsub_2_in_DPR_8GetRawAllocationOrder 7983 }; 7984 7985 extern const TargetRegisterClass QQQQPR_with_dsub_4_in_DPR_8RegClass = { 7986 &ARMMCRegisterClasses[QQQQPR_with_dsub_4_in_DPR_8RegClassID], 7987 QQQQPR_with_dsub_4_in_DPR_8SubClassMask, 7988 SuperRegIdxSeqs + 8, 7989 LaneBitmask(0x0003FFFC), 7990 0, 7991 true, /* HasDisjunctSubRegs */ 7992 true, /* CoveredBySubRegs */ 7993 QQQQPR_with_dsub_4_in_DPR_8Superclasses, 7994 QQQQPR_with_dsub_4_in_DPR_8GetRawAllocationOrder 7995 }; 7996 7997 extern const TargetRegisterClass QQQQPR_with_dsub_6_in_DPR_8RegClass = { 7998 &ARMMCRegisterClasses[QQQQPR_with_dsub_6_in_DPR_8RegClassID], 7999 QQQQPR_with_dsub_6_in_DPR_8SubClassMask, 8000 SuperRegIdxSeqs + 8, 8001 LaneBitmask(0x0003FFFC), 8002 0, 8003 true, /* HasDisjunctSubRegs */ 8004 true, /* CoveredBySubRegs */ 8005 QQQQPR_with_dsub_6_in_DPR_8Superclasses, 8006 QQQQPR_with_dsub_6_in_DPR_8GetRawAllocationOrder 8007 }; 8008 8009} // end namespace ARM 8010 8011namespace { 8012 const TargetRegisterClass* const RegisterClasses[] = { 8013 &ARM::HPRRegClass, 8014 &ARM::FPWithVPRRegClass, 8015 &ARM::SPRRegClass, 8016 &ARM::FPWithVPR_with_ssub_0RegClass, 8017 &ARM::GPRRegClass, 8018 &ARM::GPRwithAPSRRegClass, 8019 &ARM::GPRwithZRRegClass, 8020 &ARM::SPR_8RegClass, 8021 &ARM::GPRnopcRegClass, 8022 &ARM::GPRwithAPSRnospRegClass, 8023 &ARM::GPRwithZRnospRegClass, 8024 &ARM::rGPRRegClass, 8025 &ARM::tGPRwithpcRegClass, 8026 &ARM::FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClass, 8027 &ARM::hGPRRegClass, 8028 &ARM::tGPRRegClass, 8029 &ARM::tGPREvenRegClass, 8030 &ARM::GPRnopc_and_hGPRRegClass, 8031 &ARM::GPRwithAPSRnosp_and_hGPRRegClass, 8032 &ARM::tGPROddRegClass, 8033 &ARM::tcGPRRegClass, 8034 &ARM::hGPR_and_tGPREvenRegClass, 8035 &ARM::tGPR_and_tGPREvenRegClass, 8036 &ARM::tGPR_and_tGPROddRegClass, 8037 &ARM::tGPR_and_tcGPRRegClass, 8038 &ARM::tGPREven_and_tcGPRRegClass, 8039 &ARM::hGPR_and_tGPROddRegClass, 8040 &ARM::tGPREven_and_tGPR_and_tcGPRRegClass, 8041 &ARM::tGPROdd_and_tcGPRRegClass, 8042 &ARM::CCRRegClass, 8043 &ARM::GPRlrRegClass, 8044 &ARM::GPRspRegClass, 8045 &ARM::VCCRRegClass, 8046 &ARM::cl_FPSCR_NZCVRegClass, 8047 &ARM::hGPR_and_tGPRwithpcRegClass, 8048 &ARM::hGPR_and_tcGPRRegClass, 8049 &ARM::DPRRegClass, 8050 &ARM::DPR_VFP2RegClass, 8051 &ARM::DPR_8RegClass, 8052 &ARM::GPRPairRegClass, 8053 &ARM::GPRPairnospRegClass, 8054 &ARM::GPRPair_with_gsub_0_in_tGPRRegClass, 8055 &ARM::GPRPair_with_gsub_0_in_hGPRRegClass, 8056 &ARM::GPRPair_with_gsub_0_in_tcGPRRegClass, 8057 &ARM::GPRPair_with_gsub_1_in_tcGPRRegClass, 8058 &ARM::GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClass, 8059 &ARM::GPRPair_with_gsub_1_in_GPRspRegClass, 8060 &ARM::DPairSpcRegClass, 8061 &ARM::DPairSpc_with_ssub_0RegClass, 8062 &ARM::DPairSpc_with_ssub_4RegClass, 8063 &ARM::DPairSpc_with_dsub_0_in_DPR_8RegClass, 8064 &ARM::DPairSpc_with_dsub_2_in_DPR_8RegClass, 8065 &ARM::DPairRegClass, 8066 &ARM::DPair_with_ssub_0RegClass, 8067 &ARM::QPRRegClass, 8068 &ARM::DPair_with_ssub_2RegClass, 8069 &ARM::DPair_with_dsub_0_in_DPR_8RegClass, 8070 &ARM::MQPRRegClass, 8071 &ARM::QPR_VFP2RegClass, 8072 &ARM::DPair_with_dsub_1_in_DPR_8RegClass, 8073 &ARM::QPR_8RegClass, 8074 &ARM::DTripleRegClass, 8075 &ARM::DTripleSpcRegClass, 8076 &ARM::DTripleSpc_with_ssub_0RegClass, 8077 &ARM::DTriple_with_ssub_0RegClass, 8078 &ARM::DTriple_with_qsub_0_in_QPRRegClass, 8079 &ARM::DTriple_with_ssub_2RegClass, 8080 &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, 8081 &ARM::DTripleSpc_with_ssub_4RegClass, 8082 &ARM::DTriple_with_ssub_4RegClass, 8083 &ARM::DTripleSpc_with_ssub_8RegClass, 8084 &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass, 8085 &ARM::DTriple_with_dsub_0_in_DPR_8RegClass, 8086 &ARM::DTriple_with_qsub_0_in_MQPRRegClass, 8087 &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, 8088 &ARM::DTriple_with_dsub_1_in_DPR_8RegClass, 8089 &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, 8090 &ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClass, 8091 &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass, 8092 &ARM::DTriple_with_dsub_2_in_DPR_8RegClass, 8093 &ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClass, 8094 &ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, 8095 &ARM::DTriple_with_qsub_0_in_QPR_8RegClass, 8096 &ARM::DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRRegClass, 8097 &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass, 8098 &ARM::DQuadSpcRegClass, 8099 &ARM::DQuadSpc_with_ssub_0RegClass, 8100 &ARM::DQuadSpc_with_ssub_4RegClass, 8101 &ARM::DQuadSpc_with_ssub_8RegClass, 8102 &ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClass, 8103 &ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClass, 8104 &ARM::DQuadSpc_with_dsub_4_in_DPR_8RegClass, 8105 &ARM::DQuadRegClass, 8106 &ARM::DQuad_with_ssub_0RegClass, 8107 &ARM::DQuad_with_ssub_2RegClass, 8108 &ARM::QQPRRegClass, 8109 &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, 8110 &ARM::DQuad_with_ssub_4RegClass, 8111 &ARM::DQuad_with_ssub_6RegClass, 8112 &ARM::DQuad_with_dsub_0_in_DPR_8RegClass, 8113 &ARM::DQuad_with_qsub_0_in_MQPRRegClass, 8114 &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, 8115 &ARM::DQuad_with_dsub_1_in_DPR_8RegClass, 8116 &ARM::DQuad_with_qsub_1_in_MQPRRegClass, 8117 &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, 8118 &ARM::DQuad_with_dsub_2_in_DPR_8RegClass, 8119 &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, 8120 &ARM::DQuad_with_dsub_3_in_DPR_8RegClass, 8121 &ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, 8122 &ARM::DQuad_with_qsub_0_in_QPR_8RegClass, 8123 &ARM::DQuad_with_qsub_1_in_QPR_8RegClass, 8124 &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass, 8125 &ARM::DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, 8126 &ARM::QQQQPRRegClass, 8127 &ARM::QQQQPR_with_ssub_0RegClass, 8128 &ARM::QQQQPR_with_ssub_4RegClass, 8129 &ARM::QQQQPR_with_ssub_8RegClass, 8130 &ARM::QQQQPR_with_ssub_12RegClass, 8131 &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass, 8132 &ARM::QQQQPR_with_dsub_2_in_DPR_8RegClass, 8133 &ARM::QQQQPR_with_dsub_4_in_DPR_8RegClass, 8134 &ARM::QQQQPR_with_dsub_6_in_DPR_8RegClass, 8135 }; 8136} // end anonymous namespace 8137 8138static const TargetRegisterInfoDesc ARMRegInfoDesc[] = { // Extra Descriptors 8139 { 0, false }, 8140 { 0, false }, 8141 { 0, true }, 8142 { 0, false }, 8143 { 0, false }, 8144 { 0, false }, 8145 { 0, false }, 8146 { 0, false }, 8147 { 0, false }, 8148 { 0, true }, 8149 { 0, false }, 8150 { 0, false }, 8151 { 0, false }, 8152 { 1, true }, 8153 { 1, true }, 8154 { 1, true }, 8155 { 0, false }, 8156 { 0, true }, 8157 { 0, true }, 8158 { 0, true }, 8159 { 0, true }, 8160 { 0, true }, 8161 { 0, true }, 8162 { 0, true }, 8163 { 0, true }, 8164 { 0, true }, 8165 { 0, true }, 8166 { 0, true }, 8167 { 0, true }, 8168 { 0, true }, 8169 { 0, true }, 8170 { 0, true }, 8171 { 0, true }, 8172 { 0, true }, 8173 { 0, true }, 8174 { 0, true }, 8175 { 0, true }, 8176 { 0, true }, 8177 { 0, true }, 8178 { 0, true }, 8179 { 0, true }, 8180 { 0, true }, 8181 { 0, true }, 8182 { 0, true }, 8183 { 0, true }, 8184 { 0, true }, 8185 { 0, true }, 8186 { 0, true }, 8187 { 0, true }, 8188 { 0, true }, 8189 { 0, true }, 8190 { 0, false }, 8191 { 0, false }, 8192 { 0, false }, 8193 { 0, false }, 8194 { 0, false }, 8195 { 0, true }, 8196 { 0, true }, 8197 { 0, true }, 8198 { 0, true }, 8199 { 0, true }, 8200 { 0, true }, 8201 { 0, true }, 8202 { 0, true }, 8203 { 0, true }, 8204 { 0, true }, 8205 { 0, true }, 8206 { 0, true }, 8207 { 0, true }, 8208 { 0, true }, 8209 { 0, true }, 8210 { 0, true }, 8211 { 0, true }, 8212 { 0, true }, 8213 { 0, true }, 8214 { 0, true }, 8215 { 0, true }, 8216 { 0, true }, 8217 { 0, true }, 8218 { 0, true }, 8219 { 1, true }, 8220 { 1, true }, 8221 { 1, true }, 8222 { 1, true }, 8223 { 1, true }, 8224 { 0, true }, 8225 { 0, true }, 8226 { 0, true }, 8227 { 0, true }, 8228 { 0, true }, 8229 { 0, true }, 8230 { 0, true }, 8231 { 0, true }, 8232 { 0, true }, 8233 { 0, true }, 8234 { 0, true }, 8235 { 0, true }, 8236 { 0, true }, 8237 { 0, true }, 8238 { 0, true }, 8239 { 0, true }, 8240 { 0, true }, 8241 { 0, true }, 8242 { 0, true }, 8243 { 0, true }, 8244 { 0, true }, 8245 { 0, true }, 8246 { 0, true }, 8247 { 0, true }, 8248 { 0, true }, 8249 { 0, true }, 8250 { 0, true }, 8251 { 0, true }, 8252 { 0, true }, 8253 { 0, true }, 8254 { 0, true }, 8255 { 0, true }, 8256 { 0, true }, 8257 { 0, true }, 8258 { 0, true }, 8259 { 0, true }, 8260 { 0, true }, 8261 { 0, true }, 8262 { 0, true }, 8263 { 0, true }, 8264 { 0, true }, 8265 { 0, true }, 8266 { 0, true }, 8267 { 0, true }, 8268 { 0, true }, 8269 { 0, true }, 8270 { 0, true }, 8271 { 0, true }, 8272 { 0, true }, 8273 { 0, true }, 8274 { 0, true }, 8275 { 0, true }, 8276 { 0, true }, 8277 { 0, true }, 8278 { 0, true }, 8279 { 0, true }, 8280 { 0, true }, 8281 { 0, true }, 8282 { 0, true }, 8283 { 0, true }, 8284 { 0, true }, 8285 { 0, true }, 8286 { 0, true }, 8287 { 0, true }, 8288 { 0, true }, 8289 { 0, true }, 8290 { 0, true }, 8291 { 0, true }, 8292 { 0, true }, 8293 { 0, true }, 8294 { 0, true }, 8295 { 0, true }, 8296 { 0, true }, 8297 { 0, true }, 8298 { 0, true }, 8299 { 0, true }, 8300 { 0, true }, 8301 { 0, true }, 8302 { 0, true }, 8303 { 0, true }, 8304 { 0, true }, 8305 { 0, true }, 8306 { 0, true }, 8307 { 0, true }, 8308 { 0, true }, 8309 { 0, true }, 8310 { 0, true }, 8311 { 0, true }, 8312 { 0, true }, 8313 { 0, true }, 8314 { 0, true }, 8315 { 0, true }, 8316 { 0, true }, 8317 { 0, true }, 8318 { 1, true }, 8319 { 1, true }, 8320 { 1, true }, 8321 { 0, true }, 8322 { 0, true }, 8323 { 0, true }, 8324 { 0, true }, 8325 { 0, true }, 8326 { 0, true }, 8327 { 0, true }, 8328 { 0, true }, 8329 { 0, true }, 8330 { 0, true }, 8331 { 0, true }, 8332 { 0, true }, 8333 { 0, true }, 8334 { 0, true }, 8335 { 0, true }, 8336 { 0, true }, 8337 { 0, true }, 8338 { 0, true }, 8339 { 0, true }, 8340 { 0, true }, 8341 { 0, true }, 8342 { 0, true }, 8343 { 0, true }, 8344 { 0, true }, 8345 { 0, true }, 8346 { 0, true }, 8347 { 0, true }, 8348 { 0, true }, 8349 { 0, true }, 8350 { 0, true }, 8351 { 0, true }, 8352 { 0, true }, 8353 { 0, true }, 8354 { 0, true }, 8355 { 0, true }, 8356 { 0, true }, 8357 { 0, true }, 8358 { 0, true }, 8359 { 0, true }, 8360 { 0, true }, 8361 { 0, true }, 8362 { 0, true }, 8363 { 0, true }, 8364 { 0, true }, 8365 { 0, true }, 8366 { 0, true }, 8367 { 0, true }, 8368 { 0, true }, 8369 { 0, true }, 8370 { 0, true }, 8371 { 0, true }, 8372 { 0, true }, 8373 { 0, true }, 8374 { 0, true }, 8375 { 0, true }, 8376 { 0, true }, 8377 { 0, true }, 8378 { 0, true }, 8379 { 0, false }, 8380 { 0, false }, 8381 { 0, false }, 8382 { 0, false }, 8383 { 0, false }, 8384 { 0, false }, 8385 { 0, false }, 8386 { 0, false }, 8387 { 0, false }, 8388 { 0, false }, 8389 { 0, false }, 8390 { 0, false }, 8391 { 0, false }, 8392 { 0, false }, 8393 { 0, false }, 8394 { 0, false }, 8395 { 0, false }, 8396 { 0, false }, 8397 { 0, false }, 8398 { 0, false }, 8399 { 0, false }, 8400 { 0, false }, 8401 { 0, false }, 8402 { 0, false }, 8403 { 0, false }, 8404 { 0, false }, 8405 { 0, true }, 8406 { 0, true }, 8407 { 0, true }, 8408 { 0, true }, 8409 { 0, true }, 8410 { 0, true }, 8411 { 0, true }, 8412 { 0, true }, 8413 { 0, true }, 8414 { 0, true }, 8415 { 0, true }, 8416 { 0, true }, 8417 { 0, true }, 8418 { 0, true }, 8419 { 0, true }, 8420 { 0, true }, 8421 { 0, true }, 8422 { 0, true }, 8423 { 0, true }, 8424 { 0, true }, 8425 { 0, true }, 8426 { 0, true }, 8427 { 0, true }, 8428 { 0, true }, 8429 { 0, true }, 8430 { 0, true }, 8431 { 0, true }, 8432 { 0, true }, 8433 { 0, true }, 8434}; 8435unsigned ARMGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const { 8436 static const uint8_t RowMap[56] = { 8437 0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 4, 0, 2, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 5, 5, 5, 2, 8438 }; 8439 static const uint8_t Rows[8][56] = { 8440 { ARM::dsub_0, ARM::dsub_1, ARM::dsub_2, ARM::dsub_3, ARM::dsub_4, 0, ARM::dsub_6, 0, 0, 0, 0, 0, ARM::qsub_0, ARM::qsub_1, 0, 0, ARM::ssub_0, ARM::ssub_1, ARM::ssub_2, ARM::ssub_3, ARM::ssub_4, ARM::ssub_5, ARM::ssub_6, ARM::ssub_7, ARM::ssub_8, ARM::ssub_9, 0, 0, ARM::ssub_12, ARM::ssub_13, 0, 0, ARM::ssub_0_ssub_1_ssub_4_ssub_5, ARM::ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5, ARM::ssub_2_ssub_3_ssub_6_ssub_7, ARM::ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, ARM::ssub_2_ssub_3_ssub_4_ssub_5, ARM::ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9, 0, 0, 0, 0, ARM::ssub_4_ssub_5_ssub_8_ssub_9, 0, ARM::ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, 0, 0, 0, 0, 0, ARM::ssub_8_ssub_9_ssub_12_ssub_13, 0, 0, 0, 0, 0, }, 8441 { ARM::dsub_1, ARM::dsub_2, ARM::dsub_3, ARM::dsub_4, ARM::dsub_5, 0, ARM::dsub_7, 0, 0, 0, 0, 0, ARM::ssub_2_ssub_3_ssub_4_ssub_5, ARM::ssub_6_ssub_7_ssub_8_ssub_9, 0, 0, ARM::ssub_2, ARM::ssub_3, ARM::ssub_4, ARM::ssub_5, ARM::ssub_6, ARM::ssub_7, ARM::ssub_8, ARM::ssub_9, ARM::ssub_10, ARM::ssub_11, 0, 0, ARM::dsub_7_then_ssub_0, ARM::dsub_7_then_ssub_1, 0, 0, ARM::ssub_2_ssub_3_ssub_6_ssub_7, ARM::ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, ARM::ssub_4_ssub_5_ssub_8_ssub_9, ARM::ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, ARM::qsub_1, ARM::ssub_2_ssub_3_ssub_6_ssub_7_dsub_5, 0, 0, 0, 0, ARM::ssub_6_ssub_7_dsub_5, 0, ARM::ssub_6_ssub_7_dsub_5_dsub_7, 0, 0, 0, 0, 0, ARM::dsub_5_dsub_7, 0, 0, 0, 0, 0, }, 8442 { ARM::dsub_2, ARM::dsub_3, ARM::dsub_4, ARM::dsub_5, ARM::dsub_6, 0, 0, 0, 0, 0, 0, 0, ARM::qsub_1, ARM::qsub_2, 0, 0, ARM::ssub_4, ARM::ssub_5, ARM::ssub_6, ARM::ssub_7, ARM::ssub_8, ARM::ssub_9, ARM::ssub_10, ARM::ssub_11, ARM::ssub_12, ARM::ssub_13, 0, 0, 0, 0, 0, 0, ARM::ssub_4_ssub_5_ssub_8_ssub_9, ARM::ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, ARM::ssub_6_ssub_7_dsub_5, ARM::ssub_6_ssub_7_ssub_8_ssub_9_dsub_5, ARM::ssub_6_ssub_7_ssub_8_ssub_9, 0, 0, 0, 0, 0, ARM::ssub_8_ssub_9_ssub_12_ssub_13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 8443 { ARM::dsub_3, ARM::dsub_4, ARM::dsub_5, ARM::dsub_6, ARM::dsub_7, 0, 0, 0, 0, 0, 0, 0, ARM::ssub_6_ssub_7_ssub_8_ssub_9, ARM::dsub_5_ssub_12_ssub_13, 0, 0, ARM::ssub_6, ARM::ssub_7, ARM::ssub_8, ARM::ssub_9, ARM::ssub_10, ARM::ssub_11, ARM::ssub_12, ARM::ssub_13, ARM::dsub_7_then_ssub_0, ARM::dsub_7_then_ssub_1, 0, 0, 0, 0, 0, 0, ARM::ssub_6_ssub_7_dsub_5, ARM::ssub_6_ssub_7_ssub_8_ssub_9_dsub_5, ARM::ssub_8_ssub_9_ssub_12_ssub_13, ARM::ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, ARM::qsub_2, 0, 0, 0, 0, 0, ARM::dsub_5_dsub_7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 8444 { ARM::dsub_4, ARM::dsub_5, ARM::dsub_6, ARM::dsub_7, 0, 0, 0, 0, 0, 0, 0, 0, ARM::qsub_2, ARM::qsub_3, 0, 0, ARM::ssub_8, ARM::ssub_9, ARM::ssub_10, ARM::ssub_11, ARM::ssub_12, ARM::ssub_13, ARM::dsub_7_then_ssub_0, ARM::dsub_7_then_ssub_1, 0, 0, 0, 0, 0, 0, 0, 0, ARM::ssub_8_ssub_9_ssub_12_ssub_13, ARM::ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, ARM::dsub_5_dsub_7, ARM::dsub_5_ssub_12_ssub_13_dsub_7, ARM::dsub_5_ssub_12_ssub_13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 8445 { ARM::dsub_5, ARM::dsub_6, ARM::dsub_7, 0, 0, 0, 0, 0, 0, 0, 0, 0, ARM::dsub_5_ssub_12_ssub_13, 0, 0, 0, ARM::ssub_10, ARM::ssub_11, ARM::ssub_12, ARM::ssub_13, ARM::dsub_7_then_ssub_0, ARM::dsub_7_then_ssub_1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ARM::dsub_5_dsub_7, 0, 0, 0, ARM::qsub_3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 8446 { ARM::dsub_6, ARM::dsub_7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ARM::ssub_12, ARM::ssub_13, ARM::dsub_7_then_ssub_0, ARM::dsub_7_then_ssub_1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 8447 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ARM::dsub_7_then_ssub_0, ARM::dsub_7_then_ssub_1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 8448 }; 8449 8450 --IdxA; assert(IdxA < 56); 8451 --IdxB; assert(IdxB < 56); 8452 return Rows[RowMap[IdxA]][IdxB]; 8453} 8454 8455 struct MaskRolOp { 8456 LaneBitmask Mask; 8457 uint8_t RotateLeft; 8458 }; 8459 static const MaskRolOp LaneMaskComposeSequences[] = { 8460 { LaneBitmask(0xFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0 8461 { LaneBitmask(0xFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 2 8462 { LaneBitmask(0xFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 4 8463 { LaneBitmask(0xFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 }, // Sequence 6 8464 { LaneBitmask(0xFFFFFFFF), 8 }, { LaneBitmask::getNone(), 0 }, // Sequence 8 8465 { LaneBitmask(0xFFFFFFFF), 10 }, { LaneBitmask::getNone(), 0 }, // Sequence 10 8466 { LaneBitmask(0xFFFFFFFF), 12 }, { LaneBitmask::getNone(), 0 }, // Sequence 12 8467 { LaneBitmask(0xFFFFFFFF), 14 }, { LaneBitmask::getNone(), 0 }, // Sequence 14 8468 { LaneBitmask(0xFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 16 8469 { LaneBitmask(0xFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 18 8470 { LaneBitmask(0xFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 20 8471 { LaneBitmask(0xFFFFFFFF), 7 }, { LaneBitmask::getNone(), 0 }, // Sequence 22 8472 { LaneBitmask(0xFFFFFFFF), 9 }, { LaneBitmask::getNone(), 0 }, // Sequence 24 8473 { LaneBitmask(0xFFFFFFFF), 11 }, { LaneBitmask::getNone(), 0 }, // Sequence 26 8474 { LaneBitmask(0xFFFFFFFF), 13 }, { LaneBitmask::getNone(), 0 }, // Sequence 28 8475 { LaneBitmask(0xFFFFFFFF), 15 }, { LaneBitmask::getNone(), 0 }, // Sequence 30 8476 { LaneBitmask(0xFFFFFFFF), 16 }, { LaneBitmask::getNone(), 0 }, // Sequence 32 8477 { LaneBitmask(0xFFFFFFFF), 17 }, { LaneBitmask::getNone(), 0 } // Sequence 34 8478 }; 8479 static const MaskRolOp *const CompositeSequences[] = { 8480 &LaneMaskComposeSequences[0], // to dsub_0 8481 &LaneMaskComposeSequences[2], // to dsub_1 8482 &LaneMaskComposeSequences[4], // to dsub_2 8483 &LaneMaskComposeSequences[6], // to dsub_3 8484 &LaneMaskComposeSequences[8], // to dsub_4 8485 &LaneMaskComposeSequences[10], // to dsub_5 8486 &LaneMaskComposeSequences[12], // to dsub_6 8487 &LaneMaskComposeSequences[14], // to dsub_7 8488 &LaneMaskComposeSequences[0], // to gsub_0 8489 &LaneMaskComposeSequences[16], // to gsub_1 8490 &LaneMaskComposeSequences[0], // to qqsub_0 8491 &LaneMaskComposeSequences[8], // to qqsub_1 8492 &LaneMaskComposeSequences[0], // to qsub_0 8493 &LaneMaskComposeSequences[4], // to qsub_1 8494 &LaneMaskComposeSequences[8], // to qsub_2 8495 &LaneMaskComposeSequences[12], // to qsub_3 8496 &LaneMaskComposeSequences[2], // to ssub_0 8497 &LaneMaskComposeSequences[18], // to ssub_1 8498 &LaneMaskComposeSequences[4], // to ssub_2 8499 &LaneMaskComposeSequences[20], // to ssub_3 8500 &LaneMaskComposeSequences[6], // to ssub_4 8501 &LaneMaskComposeSequences[22], // to ssub_5 8502 &LaneMaskComposeSequences[8], // to ssub_6 8503 &LaneMaskComposeSequences[24], // to ssub_7 8504 &LaneMaskComposeSequences[10], // to ssub_8 8505 &LaneMaskComposeSequences[26], // to ssub_9 8506 &LaneMaskComposeSequences[12], // to ssub_10 8507 &LaneMaskComposeSequences[28], // to ssub_11 8508 &LaneMaskComposeSequences[14], // to ssub_12 8509 &LaneMaskComposeSequences[30], // to ssub_13 8510 &LaneMaskComposeSequences[32], // to dsub_7_then_ssub_0 8511 &LaneMaskComposeSequences[34], // to dsub_7_then_ssub_1 8512 &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_4_ssub_5 8513 &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 8514 &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_6_ssub_7 8515 &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 8516 &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_4_ssub_5 8517 &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 8518 &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 8519 &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 8520 &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 8521 &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 8522 &LaneMaskComposeSequences[4], // to ssub_4_ssub_5_ssub_8_ssub_9 8523 &LaneMaskComposeSequences[4], // to ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 8524 &LaneMaskComposeSequences[4], // to ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 8525 &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_dsub_5 8526 &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 8527 &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_dsub_5_dsub_7 8528 &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_ssub_8_ssub_9 8529 &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 8530 &LaneMaskComposeSequences[8], // to ssub_8_ssub_9_ssub_12_ssub_13 8531 &LaneMaskComposeSequences[8], // to ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 8532 &LaneMaskComposeSequences[10], // to dsub_5_dsub_7 8533 &LaneMaskComposeSequences[10], // to dsub_5_ssub_12_ssub_13_dsub_7 8534 &LaneMaskComposeSequences[10], // to dsub_5_ssub_12_ssub_13 8535 &LaneMaskComposeSequences[4] // to ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 8536 }; 8537 8538LaneBitmask ARMGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { 8539 --IdxA; assert(IdxA < 56 && "Subregister index out of bounds"); 8540 LaneBitmask Result; 8541 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) { 8542 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger(); 8543 if (unsigned S = Ops->RotateLeft) 8544 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S))); 8545 else 8546 Result |= LaneBitmask(M); 8547 } 8548 return Result; 8549} 8550 8551LaneBitmask ARMGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { 8552 LaneMask &= getSubRegIndexLaneMask(IdxA); 8553 --IdxA; assert(IdxA < 56 && "Subregister index out of bounds"); 8554 LaneBitmask Result; 8555 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) { 8556 LaneBitmask::Type M = LaneMask.getAsInteger(); 8557 if (unsigned S = Ops->RotateLeft) 8558 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S))); 8559 else 8560 Result |= LaneBitmask(M); 8561 } 8562 return Result; 8563} 8564 8565const TargetRegisterClass *ARMGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { 8566 static const uint8_t Table[122][56] = { 8567 { // HPR 8568 0, // dsub_0 8569 0, // dsub_1 8570 0, // dsub_2 8571 0, // dsub_3 8572 0, // dsub_4 8573 0, // dsub_5 8574 0, // dsub_6 8575 0, // dsub_7 8576 0, // gsub_0 8577 0, // gsub_1 8578 0, // qqsub_0 8579 0, // qqsub_1 8580 0, // qsub_0 8581 0, // qsub_1 8582 0, // qsub_2 8583 0, // qsub_3 8584 0, // ssub_0 8585 0, // ssub_1 8586 0, // ssub_2 8587 0, // ssub_3 8588 0, // ssub_4 8589 0, // ssub_5 8590 0, // ssub_6 8591 0, // ssub_7 8592 0, // ssub_8 8593 0, // ssub_9 8594 0, // ssub_10 8595 0, // ssub_11 8596 0, // ssub_12 8597 0, // ssub_13 8598 0, // dsub_7_then_ssub_0 8599 0, // dsub_7_then_ssub_1 8600 0, // ssub_0_ssub_1_ssub_4_ssub_5 8601 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 8602 0, // ssub_2_ssub_3_ssub_6_ssub_7 8603 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 8604 0, // ssub_2_ssub_3_ssub_4_ssub_5 8605 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 8606 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 8607 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 8608 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 8609 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 8610 0, // ssub_4_ssub_5_ssub_8_ssub_9 8611 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 8612 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 8613 0, // ssub_6_ssub_7_dsub_5 8614 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 8615 0, // ssub_6_ssub_7_dsub_5_dsub_7 8616 0, // ssub_6_ssub_7_ssub_8_ssub_9 8617 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 8618 0, // ssub_8_ssub_9_ssub_12_ssub_13 8619 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 8620 0, // dsub_5_dsub_7 8621 0, // dsub_5_ssub_12_ssub_13_dsub_7 8622 0, // dsub_5_ssub_12_ssub_13 8623 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 8624 }, 8625 { // FPWithVPR 8626 0, // dsub_0 8627 0, // dsub_1 8628 0, // dsub_2 8629 0, // dsub_3 8630 0, // dsub_4 8631 0, // dsub_5 8632 0, // dsub_6 8633 0, // dsub_7 8634 0, // gsub_0 8635 0, // gsub_1 8636 0, // qqsub_0 8637 0, // qqsub_1 8638 0, // qsub_0 8639 0, // qsub_1 8640 0, // qsub_2 8641 0, // qsub_3 8642 4, // ssub_0 -> FPWithVPR_with_ssub_0 8643 4, // ssub_1 -> FPWithVPR_with_ssub_0 8644 0, // ssub_2 8645 0, // ssub_3 8646 0, // ssub_4 8647 0, // ssub_5 8648 0, // ssub_6 8649 0, // ssub_7 8650 0, // ssub_8 8651 0, // ssub_9 8652 0, // ssub_10 8653 0, // ssub_11 8654 0, // ssub_12 8655 0, // ssub_13 8656 0, // dsub_7_then_ssub_0 8657 0, // dsub_7_then_ssub_1 8658 0, // ssub_0_ssub_1_ssub_4_ssub_5 8659 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 8660 0, // ssub_2_ssub_3_ssub_6_ssub_7 8661 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 8662 0, // ssub_2_ssub_3_ssub_4_ssub_5 8663 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 8664 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 8665 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 8666 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 8667 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 8668 0, // ssub_4_ssub_5_ssub_8_ssub_9 8669 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 8670 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 8671 0, // ssub_6_ssub_7_dsub_5 8672 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 8673 0, // ssub_6_ssub_7_dsub_5_dsub_7 8674 0, // ssub_6_ssub_7_ssub_8_ssub_9 8675 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 8676 0, // ssub_8_ssub_9_ssub_12_ssub_13 8677 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 8678 0, // dsub_5_dsub_7 8679 0, // dsub_5_ssub_12_ssub_13_dsub_7 8680 0, // dsub_5_ssub_12_ssub_13 8681 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 8682 }, 8683 { // SPR 8684 0, // dsub_0 8685 0, // dsub_1 8686 0, // dsub_2 8687 0, // dsub_3 8688 0, // dsub_4 8689 0, // dsub_5 8690 0, // dsub_6 8691 0, // dsub_7 8692 0, // gsub_0 8693 0, // gsub_1 8694 0, // qqsub_0 8695 0, // qqsub_1 8696 0, // qsub_0 8697 0, // qsub_1 8698 0, // qsub_2 8699 0, // qsub_3 8700 0, // ssub_0 8701 0, // ssub_1 8702 0, // ssub_2 8703 0, // ssub_3 8704 0, // ssub_4 8705 0, // ssub_5 8706 0, // ssub_6 8707 0, // ssub_7 8708 0, // ssub_8 8709 0, // ssub_9 8710 0, // ssub_10 8711 0, // ssub_11 8712 0, // ssub_12 8713 0, // ssub_13 8714 0, // dsub_7_then_ssub_0 8715 0, // dsub_7_then_ssub_1 8716 0, // ssub_0_ssub_1_ssub_4_ssub_5 8717 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 8718 0, // ssub_2_ssub_3_ssub_6_ssub_7 8719 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 8720 0, // ssub_2_ssub_3_ssub_4_ssub_5 8721 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 8722 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 8723 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 8724 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 8725 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 8726 0, // ssub_4_ssub_5_ssub_8_ssub_9 8727 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 8728 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 8729 0, // ssub_6_ssub_7_dsub_5 8730 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 8731 0, // ssub_6_ssub_7_dsub_5_dsub_7 8732 0, // ssub_6_ssub_7_ssub_8_ssub_9 8733 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 8734 0, // ssub_8_ssub_9_ssub_12_ssub_13 8735 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 8736 0, // dsub_5_dsub_7 8737 0, // dsub_5_ssub_12_ssub_13_dsub_7 8738 0, // dsub_5_ssub_12_ssub_13 8739 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 8740 }, 8741 { // FPWithVPR_with_ssub_0 8742 0, // dsub_0 8743 0, // dsub_1 8744 0, // dsub_2 8745 0, // dsub_3 8746 0, // dsub_4 8747 0, // dsub_5 8748 0, // dsub_6 8749 0, // dsub_7 8750 0, // gsub_0 8751 0, // gsub_1 8752 0, // qqsub_0 8753 0, // qqsub_1 8754 0, // qsub_0 8755 0, // qsub_1 8756 0, // qsub_2 8757 0, // qsub_3 8758 4, // ssub_0 -> FPWithVPR_with_ssub_0 8759 4, // ssub_1 -> FPWithVPR_with_ssub_0 8760 0, // ssub_2 8761 0, // ssub_3 8762 0, // ssub_4 8763 0, // ssub_5 8764 0, // ssub_6 8765 0, // ssub_7 8766 0, // ssub_8 8767 0, // ssub_9 8768 0, // ssub_10 8769 0, // ssub_11 8770 0, // ssub_12 8771 0, // ssub_13 8772 0, // dsub_7_then_ssub_0 8773 0, // dsub_7_then_ssub_1 8774 0, // ssub_0_ssub_1_ssub_4_ssub_5 8775 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 8776 0, // ssub_2_ssub_3_ssub_6_ssub_7 8777 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 8778 0, // ssub_2_ssub_3_ssub_4_ssub_5 8779 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 8780 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 8781 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 8782 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 8783 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 8784 0, // ssub_4_ssub_5_ssub_8_ssub_9 8785 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 8786 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 8787 0, // ssub_6_ssub_7_dsub_5 8788 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 8789 0, // ssub_6_ssub_7_dsub_5_dsub_7 8790 0, // ssub_6_ssub_7_ssub_8_ssub_9 8791 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 8792 0, // ssub_8_ssub_9_ssub_12_ssub_13 8793 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 8794 0, // dsub_5_dsub_7 8795 0, // dsub_5_ssub_12_ssub_13_dsub_7 8796 0, // dsub_5_ssub_12_ssub_13 8797 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 8798 }, 8799 { // GPR 8800 0, // dsub_0 8801 0, // dsub_1 8802 0, // dsub_2 8803 0, // dsub_3 8804 0, // dsub_4 8805 0, // dsub_5 8806 0, // dsub_6 8807 0, // dsub_7 8808 0, // gsub_0 8809 0, // gsub_1 8810 0, // qqsub_0 8811 0, // qqsub_1 8812 0, // qsub_0 8813 0, // qsub_1 8814 0, // qsub_2 8815 0, // qsub_3 8816 0, // ssub_0 8817 0, // ssub_1 8818 0, // ssub_2 8819 0, // ssub_3 8820 0, // ssub_4 8821 0, // ssub_5 8822 0, // ssub_6 8823 0, // ssub_7 8824 0, // ssub_8 8825 0, // ssub_9 8826 0, // ssub_10 8827 0, // ssub_11 8828 0, // ssub_12 8829 0, // ssub_13 8830 0, // dsub_7_then_ssub_0 8831 0, // dsub_7_then_ssub_1 8832 0, // ssub_0_ssub_1_ssub_4_ssub_5 8833 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 8834 0, // ssub_2_ssub_3_ssub_6_ssub_7 8835 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 8836 0, // ssub_2_ssub_3_ssub_4_ssub_5 8837 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 8838 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 8839 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 8840 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 8841 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 8842 0, // ssub_4_ssub_5_ssub_8_ssub_9 8843 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 8844 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 8845 0, // ssub_6_ssub_7_dsub_5 8846 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 8847 0, // ssub_6_ssub_7_dsub_5_dsub_7 8848 0, // ssub_6_ssub_7_ssub_8_ssub_9 8849 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 8850 0, // ssub_8_ssub_9_ssub_12_ssub_13 8851 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 8852 0, // dsub_5_dsub_7 8853 0, // dsub_5_ssub_12_ssub_13_dsub_7 8854 0, // dsub_5_ssub_12_ssub_13 8855 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 8856 }, 8857 { // GPRwithAPSR 8858 0, // dsub_0 8859 0, // dsub_1 8860 0, // dsub_2 8861 0, // dsub_3 8862 0, // dsub_4 8863 0, // dsub_5 8864 0, // dsub_6 8865 0, // dsub_7 8866 0, // gsub_0 8867 0, // gsub_1 8868 0, // qqsub_0 8869 0, // qqsub_1 8870 0, // qsub_0 8871 0, // qsub_1 8872 0, // qsub_2 8873 0, // qsub_3 8874 0, // ssub_0 8875 0, // ssub_1 8876 0, // ssub_2 8877 0, // ssub_3 8878 0, // ssub_4 8879 0, // ssub_5 8880 0, // ssub_6 8881 0, // ssub_7 8882 0, // ssub_8 8883 0, // ssub_9 8884 0, // ssub_10 8885 0, // ssub_11 8886 0, // ssub_12 8887 0, // ssub_13 8888 0, // dsub_7_then_ssub_0 8889 0, // dsub_7_then_ssub_1 8890 0, // ssub_0_ssub_1_ssub_4_ssub_5 8891 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 8892 0, // ssub_2_ssub_3_ssub_6_ssub_7 8893 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 8894 0, // ssub_2_ssub_3_ssub_4_ssub_5 8895 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 8896 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 8897 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 8898 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 8899 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 8900 0, // ssub_4_ssub_5_ssub_8_ssub_9 8901 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 8902 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 8903 0, // ssub_6_ssub_7_dsub_5 8904 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 8905 0, // ssub_6_ssub_7_dsub_5_dsub_7 8906 0, // ssub_6_ssub_7_ssub_8_ssub_9 8907 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 8908 0, // ssub_8_ssub_9_ssub_12_ssub_13 8909 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 8910 0, // dsub_5_dsub_7 8911 0, // dsub_5_ssub_12_ssub_13_dsub_7 8912 0, // dsub_5_ssub_12_ssub_13 8913 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 8914 }, 8915 { // GPRwithZR 8916 0, // dsub_0 8917 0, // dsub_1 8918 0, // dsub_2 8919 0, // dsub_3 8920 0, // dsub_4 8921 0, // dsub_5 8922 0, // dsub_6 8923 0, // dsub_7 8924 0, // gsub_0 8925 0, // gsub_1 8926 0, // qqsub_0 8927 0, // qqsub_1 8928 0, // qsub_0 8929 0, // qsub_1 8930 0, // qsub_2 8931 0, // qsub_3 8932 0, // ssub_0 8933 0, // ssub_1 8934 0, // ssub_2 8935 0, // ssub_3 8936 0, // ssub_4 8937 0, // ssub_5 8938 0, // ssub_6 8939 0, // ssub_7 8940 0, // ssub_8 8941 0, // ssub_9 8942 0, // ssub_10 8943 0, // ssub_11 8944 0, // ssub_12 8945 0, // ssub_13 8946 0, // dsub_7_then_ssub_0 8947 0, // dsub_7_then_ssub_1 8948 0, // ssub_0_ssub_1_ssub_4_ssub_5 8949 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 8950 0, // ssub_2_ssub_3_ssub_6_ssub_7 8951 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 8952 0, // ssub_2_ssub_3_ssub_4_ssub_5 8953 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 8954 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 8955 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 8956 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 8957 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 8958 0, // ssub_4_ssub_5_ssub_8_ssub_9 8959 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 8960 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 8961 0, // ssub_6_ssub_7_dsub_5 8962 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 8963 0, // ssub_6_ssub_7_dsub_5_dsub_7 8964 0, // ssub_6_ssub_7_ssub_8_ssub_9 8965 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 8966 0, // ssub_8_ssub_9_ssub_12_ssub_13 8967 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 8968 0, // dsub_5_dsub_7 8969 0, // dsub_5_ssub_12_ssub_13_dsub_7 8970 0, // dsub_5_ssub_12_ssub_13 8971 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 8972 }, 8973 { // SPR_8 8974 0, // dsub_0 8975 0, // dsub_1 8976 0, // dsub_2 8977 0, // dsub_3 8978 0, // dsub_4 8979 0, // dsub_5 8980 0, // dsub_6 8981 0, // dsub_7 8982 0, // gsub_0 8983 0, // gsub_1 8984 0, // qqsub_0 8985 0, // qqsub_1 8986 0, // qsub_0 8987 0, // qsub_1 8988 0, // qsub_2 8989 0, // qsub_3 8990 0, // ssub_0 8991 0, // ssub_1 8992 0, // ssub_2 8993 0, // ssub_3 8994 0, // ssub_4 8995 0, // ssub_5 8996 0, // ssub_6 8997 0, // ssub_7 8998 0, // ssub_8 8999 0, // ssub_9 9000 0, // ssub_10 9001 0, // ssub_11 9002 0, // ssub_12 9003 0, // ssub_13 9004 0, // dsub_7_then_ssub_0 9005 0, // dsub_7_then_ssub_1 9006 0, // ssub_0_ssub_1_ssub_4_ssub_5 9007 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 9008 0, // ssub_2_ssub_3_ssub_6_ssub_7 9009 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 9010 0, // ssub_2_ssub_3_ssub_4_ssub_5 9011 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 9012 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9013 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 9014 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 9015 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9016 0, // ssub_4_ssub_5_ssub_8_ssub_9 9017 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9018 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9019 0, // ssub_6_ssub_7_dsub_5 9020 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 9021 0, // ssub_6_ssub_7_dsub_5_dsub_7 9022 0, // ssub_6_ssub_7_ssub_8_ssub_9 9023 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9024 0, // ssub_8_ssub_9_ssub_12_ssub_13 9025 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9026 0, // dsub_5_dsub_7 9027 0, // dsub_5_ssub_12_ssub_13_dsub_7 9028 0, // dsub_5_ssub_12_ssub_13 9029 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 9030 }, 9031 { // GPRnopc 9032 0, // dsub_0 9033 0, // dsub_1 9034 0, // dsub_2 9035 0, // dsub_3 9036 0, // dsub_4 9037 0, // dsub_5 9038 0, // dsub_6 9039 0, // dsub_7 9040 0, // gsub_0 9041 0, // gsub_1 9042 0, // qqsub_0 9043 0, // qqsub_1 9044 0, // qsub_0 9045 0, // qsub_1 9046 0, // qsub_2 9047 0, // qsub_3 9048 0, // ssub_0 9049 0, // ssub_1 9050 0, // ssub_2 9051 0, // ssub_3 9052 0, // ssub_4 9053 0, // ssub_5 9054 0, // ssub_6 9055 0, // ssub_7 9056 0, // ssub_8 9057 0, // ssub_9 9058 0, // ssub_10 9059 0, // ssub_11 9060 0, // ssub_12 9061 0, // ssub_13 9062 0, // dsub_7_then_ssub_0 9063 0, // dsub_7_then_ssub_1 9064 0, // ssub_0_ssub_1_ssub_4_ssub_5 9065 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 9066 0, // ssub_2_ssub_3_ssub_6_ssub_7 9067 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 9068 0, // ssub_2_ssub_3_ssub_4_ssub_5 9069 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 9070 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9071 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 9072 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 9073 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9074 0, // ssub_4_ssub_5_ssub_8_ssub_9 9075 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9076 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9077 0, // ssub_6_ssub_7_dsub_5 9078 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 9079 0, // ssub_6_ssub_7_dsub_5_dsub_7 9080 0, // ssub_6_ssub_7_ssub_8_ssub_9 9081 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9082 0, // ssub_8_ssub_9_ssub_12_ssub_13 9083 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9084 0, // dsub_5_dsub_7 9085 0, // dsub_5_ssub_12_ssub_13_dsub_7 9086 0, // dsub_5_ssub_12_ssub_13 9087 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 9088 }, 9089 { // GPRwithAPSRnosp 9090 0, // dsub_0 9091 0, // dsub_1 9092 0, // dsub_2 9093 0, // dsub_3 9094 0, // dsub_4 9095 0, // dsub_5 9096 0, // dsub_6 9097 0, // dsub_7 9098 0, // gsub_0 9099 0, // gsub_1 9100 0, // qqsub_0 9101 0, // qqsub_1 9102 0, // qsub_0 9103 0, // qsub_1 9104 0, // qsub_2 9105 0, // qsub_3 9106 0, // ssub_0 9107 0, // ssub_1 9108 0, // ssub_2 9109 0, // ssub_3 9110 0, // ssub_4 9111 0, // ssub_5 9112 0, // ssub_6 9113 0, // ssub_7 9114 0, // ssub_8 9115 0, // ssub_9 9116 0, // ssub_10 9117 0, // ssub_11 9118 0, // ssub_12 9119 0, // ssub_13 9120 0, // dsub_7_then_ssub_0 9121 0, // dsub_7_then_ssub_1 9122 0, // ssub_0_ssub_1_ssub_4_ssub_5 9123 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 9124 0, // ssub_2_ssub_3_ssub_6_ssub_7 9125 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 9126 0, // ssub_2_ssub_3_ssub_4_ssub_5 9127 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 9128 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9129 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 9130 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 9131 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9132 0, // ssub_4_ssub_5_ssub_8_ssub_9 9133 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9134 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9135 0, // ssub_6_ssub_7_dsub_5 9136 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 9137 0, // ssub_6_ssub_7_dsub_5_dsub_7 9138 0, // ssub_6_ssub_7_ssub_8_ssub_9 9139 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9140 0, // ssub_8_ssub_9_ssub_12_ssub_13 9141 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9142 0, // dsub_5_dsub_7 9143 0, // dsub_5_ssub_12_ssub_13_dsub_7 9144 0, // dsub_5_ssub_12_ssub_13 9145 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 9146 }, 9147 { // GPRwithZRnosp 9148 0, // dsub_0 9149 0, // dsub_1 9150 0, // dsub_2 9151 0, // dsub_3 9152 0, // dsub_4 9153 0, // dsub_5 9154 0, // dsub_6 9155 0, // dsub_7 9156 0, // gsub_0 9157 0, // gsub_1 9158 0, // qqsub_0 9159 0, // qqsub_1 9160 0, // qsub_0 9161 0, // qsub_1 9162 0, // qsub_2 9163 0, // qsub_3 9164 0, // ssub_0 9165 0, // ssub_1 9166 0, // ssub_2 9167 0, // ssub_3 9168 0, // ssub_4 9169 0, // ssub_5 9170 0, // ssub_6 9171 0, // ssub_7 9172 0, // ssub_8 9173 0, // ssub_9 9174 0, // ssub_10 9175 0, // ssub_11 9176 0, // ssub_12 9177 0, // ssub_13 9178 0, // dsub_7_then_ssub_0 9179 0, // dsub_7_then_ssub_1 9180 0, // ssub_0_ssub_1_ssub_4_ssub_5 9181 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 9182 0, // ssub_2_ssub_3_ssub_6_ssub_7 9183 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 9184 0, // ssub_2_ssub_3_ssub_4_ssub_5 9185 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 9186 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9187 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 9188 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 9189 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9190 0, // ssub_4_ssub_5_ssub_8_ssub_9 9191 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9192 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9193 0, // ssub_6_ssub_7_dsub_5 9194 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 9195 0, // ssub_6_ssub_7_dsub_5_dsub_7 9196 0, // ssub_6_ssub_7_ssub_8_ssub_9 9197 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9198 0, // ssub_8_ssub_9_ssub_12_ssub_13 9199 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9200 0, // dsub_5_dsub_7 9201 0, // dsub_5_ssub_12_ssub_13_dsub_7 9202 0, // dsub_5_ssub_12_ssub_13 9203 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 9204 }, 9205 { // rGPR 9206 0, // dsub_0 9207 0, // dsub_1 9208 0, // dsub_2 9209 0, // dsub_3 9210 0, // dsub_4 9211 0, // dsub_5 9212 0, // dsub_6 9213 0, // dsub_7 9214 0, // gsub_0 9215 0, // gsub_1 9216 0, // qqsub_0 9217 0, // qqsub_1 9218 0, // qsub_0 9219 0, // qsub_1 9220 0, // qsub_2 9221 0, // qsub_3 9222 0, // ssub_0 9223 0, // ssub_1 9224 0, // ssub_2 9225 0, // ssub_3 9226 0, // ssub_4 9227 0, // ssub_5 9228 0, // ssub_6 9229 0, // ssub_7 9230 0, // ssub_8 9231 0, // ssub_9 9232 0, // ssub_10 9233 0, // ssub_11 9234 0, // ssub_12 9235 0, // ssub_13 9236 0, // dsub_7_then_ssub_0 9237 0, // dsub_7_then_ssub_1 9238 0, // ssub_0_ssub_1_ssub_4_ssub_5 9239 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 9240 0, // ssub_2_ssub_3_ssub_6_ssub_7 9241 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 9242 0, // ssub_2_ssub_3_ssub_4_ssub_5 9243 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 9244 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9245 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 9246 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 9247 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9248 0, // ssub_4_ssub_5_ssub_8_ssub_9 9249 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9250 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9251 0, // ssub_6_ssub_7_dsub_5 9252 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 9253 0, // ssub_6_ssub_7_dsub_5_dsub_7 9254 0, // ssub_6_ssub_7_ssub_8_ssub_9 9255 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9256 0, // ssub_8_ssub_9_ssub_12_ssub_13 9257 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9258 0, // dsub_5_dsub_7 9259 0, // dsub_5_ssub_12_ssub_13_dsub_7 9260 0, // dsub_5_ssub_12_ssub_13 9261 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 9262 }, 9263 { // tGPRwithpc 9264 0, // dsub_0 9265 0, // dsub_1 9266 0, // dsub_2 9267 0, // dsub_3 9268 0, // dsub_4 9269 0, // dsub_5 9270 0, // dsub_6 9271 0, // dsub_7 9272 0, // gsub_0 9273 0, // gsub_1 9274 0, // qqsub_0 9275 0, // qqsub_1 9276 0, // qsub_0 9277 0, // qsub_1 9278 0, // qsub_2 9279 0, // qsub_3 9280 0, // ssub_0 9281 0, // ssub_1 9282 0, // ssub_2 9283 0, // ssub_3 9284 0, // ssub_4 9285 0, // ssub_5 9286 0, // ssub_6 9287 0, // ssub_7 9288 0, // ssub_8 9289 0, // ssub_9 9290 0, // ssub_10 9291 0, // ssub_11 9292 0, // ssub_12 9293 0, // ssub_13 9294 0, // dsub_7_then_ssub_0 9295 0, // dsub_7_then_ssub_1 9296 0, // ssub_0_ssub_1_ssub_4_ssub_5 9297 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 9298 0, // ssub_2_ssub_3_ssub_6_ssub_7 9299 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 9300 0, // ssub_2_ssub_3_ssub_4_ssub_5 9301 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 9302 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9303 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 9304 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 9305 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9306 0, // ssub_4_ssub_5_ssub_8_ssub_9 9307 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9308 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9309 0, // ssub_6_ssub_7_dsub_5 9310 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 9311 0, // ssub_6_ssub_7_dsub_5_dsub_7 9312 0, // ssub_6_ssub_7_ssub_8_ssub_9 9313 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9314 0, // ssub_8_ssub_9_ssub_12_ssub_13 9315 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9316 0, // dsub_5_dsub_7 9317 0, // dsub_5_ssub_12_ssub_13_dsub_7 9318 0, // dsub_5_ssub_12_ssub_13 9319 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 9320 }, 9321 { // FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 9322 0, // dsub_0 9323 0, // dsub_1 9324 0, // dsub_2 9325 0, // dsub_3 9326 0, // dsub_4 9327 0, // dsub_5 9328 0, // dsub_6 9329 0, // dsub_7 9330 0, // gsub_0 9331 0, // gsub_1 9332 0, // qqsub_0 9333 0, // qqsub_1 9334 0, // qsub_0 9335 0, // qsub_1 9336 0, // qsub_2 9337 0, // qsub_3 9338 14, // ssub_0 -> FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 9339 14, // ssub_1 -> FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 9340 0, // ssub_2 9341 0, // ssub_3 9342 0, // ssub_4 9343 0, // ssub_5 9344 0, // ssub_6 9345 0, // ssub_7 9346 0, // ssub_8 9347 0, // ssub_9 9348 0, // ssub_10 9349 0, // ssub_11 9350 0, // ssub_12 9351 0, // ssub_13 9352 0, // dsub_7_then_ssub_0 9353 0, // dsub_7_then_ssub_1 9354 0, // ssub_0_ssub_1_ssub_4_ssub_5 9355 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 9356 0, // ssub_2_ssub_3_ssub_6_ssub_7 9357 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 9358 0, // ssub_2_ssub_3_ssub_4_ssub_5 9359 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 9360 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9361 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 9362 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 9363 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9364 0, // ssub_4_ssub_5_ssub_8_ssub_9 9365 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9366 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9367 0, // ssub_6_ssub_7_dsub_5 9368 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 9369 0, // ssub_6_ssub_7_dsub_5_dsub_7 9370 0, // ssub_6_ssub_7_ssub_8_ssub_9 9371 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9372 0, // ssub_8_ssub_9_ssub_12_ssub_13 9373 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9374 0, // dsub_5_dsub_7 9375 0, // dsub_5_ssub_12_ssub_13_dsub_7 9376 0, // dsub_5_ssub_12_ssub_13 9377 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 9378 }, 9379 { // hGPR 9380 0, // dsub_0 9381 0, // dsub_1 9382 0, // dsub_2 9383 0, // dsub_3 9384 0, // dsub_4 9385 0, // dsub_5 9386 0, // dsub_6 9387 0, // dsub_7 9388 0, // gsub_0 9389 0, // gsub_1 9390 0, // qqsub_0 9391 0, // qqsub_1 9392 0, // qsub_0 9393 0, // qsub_1 9394 0, // qsub_2 9395 0, // qsub_3 9396 0, // ssub_0 9397 0, // ssub_1 9398 0, // ssub_2 9399 0, // ssub_3 9400 0, // ssub_4 9401 0, // ssub_5 9402 0, // ssub_6 9403 0, // ssub_7 9404 0, // ssub_8 9405 0, // ssub_9 9406 0, // ssub_10 9407 0, // ssub_11 9408 0, // ssub_12 9409 0, // ssub_13 9410 0, // dsub_7_then_ssub_0 9411 0, // dsub_7_then_ssub_1 9412 0, // ssub_0_ssub_1_ssub_4_ssub_5 9413 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 9414 0, // ssub_2_ssub_3_ssub_6_ssub_7 9415 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 9416 0, // ssub_2_ssub_3_ssub_4_ssub_5 9417 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 9418 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9419 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 9420 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 9421 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9422 0, // ssub_4_ssub_5_ssub_8_ssub_9 9423 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9424 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9425 0, // ssub_6_ssub_7_dsub_5 9426 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 9427 0, // ssub_6_ssub_7_dsub_5_dsub_7 9428 0, // ssub_6_ssub_7_ssub_8_ssub_9 9429 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9430 0, // ssub_8_ssub_9_ssub_12_ssub_13 9431 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9432 0, // dsub_5_dsub_7 9433 0, // dsub_5_ssub_12_ssub_13_dsub_7 9434 0, // dsub_5_ssub_12_ssub_13 9435 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 9436 }, 9437 { // tGPR 9438 0, // dsub_0 9439 0, // dsub_1 9440 0, // dsub_2 9441 0, // dsub_3 9442 0, // dsub_4 9443 0, // dsub_5 9444 0, // dsub_6 9445 0, // dsub_7 9446 0, // gsub_0 9447 0, // gsub_1 9448 0, // qqsub_0 9449 0, // qqsub_1 9450 0, // qsub_0 9451 0, // qsub_1 9452 0, // qsub_2 9453 0, // qsub_3 9454 0, // ssub_0 9455 0, // ssub_1 9456 0, // ssub_2 9457 0, // ssub_3 9458 0, // ssub_4 9459 0, // ssub_5 9460 0, // ssub_6 9461 0, // ssub_7 9462 0, // ssub_8 9463 0, // ssub_9 9464 0, // ssub_10 9465 0, // ssub_11 9466 0, // ssub_12 9467 0, // ssub_13 9468 0, // dsub_7_then_ssub_0 9469 0, // dsub_7_then_ssub_1 9470 0, // ssub_0_ssub_1_ssub_4_ssub_5 9471 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 9472 0, // ssub_2_ssub_3_ssub_6_ssub_7 9473 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 9474 0, // ssub_2_ssub_3_ssub_4_ssub_5 9475 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 9476 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9477 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 9478 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 9479 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9480 0, // ssub_4_ssub_5_ssub_8_ssub_9 9481 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9482 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9483 0, // ssub_6_ssub_7_dsub_5 9484 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 9485 0, // ssub_6_ssub_7_dsub_5_dsub_7 9486 0, // ssub_6_ssub_7_ssub_8_ssub_9 9487 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9488 0, // ssub_8_ssub_9_ssub_12_ssub_13 9489 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9490 0, // dsub_5_dsub_7 9491 0, // dsub_5_ssub_12_ssub_13_dsub_7 9492 0, // dsub_5_ssub_12_ssub_13 9493 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 9494 }, 9495 { // tGPREven 9496 0, // dsub_0 9497 0, // dsub_1 9498 0, // dsub_2 9499 0, // dsub_3 9500 0, // dsub_4 9501 0, // dsub_5 9502 0, // dsub_6 9503 0, // dsub_7 9504 0, // gsub_0 9505 0, // gsub_1 9506 0, // qqsub_0 9507 0, // qqsub_1 9508 0, // qsub_0 9509 0, // qsub_1 9510 0, // qsub_2 9511 0, // qsub_3 9512 0, // ssub_0 9513 0, // ssub_1 9514 0, // ssub_2 9515 0, // ssub_3 9516 0, // ssub_4 9517 0, // ssub_5 9518 0, // ssub_6 9519 0, // ssub_7 9520 0, // ssub_8 9521 0, // ssub_9 9522 0, // ssub_10 9523 0, // ssub_11 9524 0, // ssub_12 9525 0, // ssub_13 9526 0, // dsub_7_then_ssub_0 9527 0, // dsub_7_then_ssub_1 9528 0, // ssub_0_ssub_1_ssub_4_ssub_5 9529 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 9530 0, // ssub_2_ssub_3_ssub_6_ssub_7 9531 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 9532 0, // ssub_2_ssub_3_ssub_4_ssub_5 9533 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 9534 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9535 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 9536 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 9537 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9538 0, // ssub_4_ssub_5_ssub_8_ssub_9 9539 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9540 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9541 0, // ssub_6_ssub_7_dsub_5 9542 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 9543 0, // ssub_6_ssub_7_dsub_5_dsub_7 9544 0, // ssub_6_ssub_7_ssub_8_ssub_9 9545 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9546 0, // ssub_8_ssub_9_ssub_12_ssub_13 9547 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9548 0, // dsub_5_dsub_7 9549 0, // dsub_5_ssub_12_ssub_13_dsub_7 9550 0, // dsub_5_ssub_12_ssub_13 9551 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 9552 }, 9553 { // GPRnopc_and_hGPR 9554 0, // dsub_0 9555 0, // dsub_1 9556 0, // dsub_2 9557 0, // dsub_3 9558 0, // dsub_4 9559 0, // dsub_5 9560 0, // dsub_6 9561 0, // dsub_7 9562 0, // gsub_0 9563 0, // gsub_1 9564 0, // qqsub_0 9565 0, // qqsub_1 9566 0, // qsub_0 9567 0, // qsub_1 9568 0, // qsub_2 9569 0, // qsub_3 9570 0, // ssub_0 9571 0, // ssub_1 9572 0, // ssub_2 9573 0, // ssub_3 9574 0, // ssub_4 9575 0, // ssub_5 9576 0, // ssub_6 9577 0, // ssub_7 9578 0, // ssub_8 9579 0, // ssub_9 9580 0, // ssub_10 9581 0, // ssub_11 9582 0, // ssub_12 9583 0, // ssub_13 9584 0, // dsub_7_then_ssub_0 9585 0, // dsub_7_then_ssub_1 9586 0, // ssub_0_ssub_1_ssub_4_ssub_5 9587 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 9588 0, // ssub_2_ssub_3_ssub_6_ssub_7 9589 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 9590 0, // ssub_2_ssub_3_ssub_4_ssub_5 9591 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 9592 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9593 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 9594 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 9595 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9596 0, // ssub_4_ssub_5_ssub_8_ssub_9 9597 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9598 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9599 0, // ssub_6_ssub_7_dsub_5 9600 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 9601 0, // ssub_6_ssub_7_dsub_5_dsub_7 9602 0, // ssub_6_ssub_7_ssub_8_ssub_9 9603 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9604 0, // ssub_8_ssub_9_ssub_12_ssub_13 9605 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9606 0, // dsub_5_dsub_7 9607 0, // dsub_5_ssub_12_ssub_13_dsub_7 9608 0, // dsub_5_ssub_12_ssub_13 9609 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 9610 }, 9611 { // GPRwithAPSRnosp_and_hGPR 9612 0, // dsub_0 9613 0, // dsub_1 9614 0, // dsub_2 9615 0, // dsub_3 9616 0, // dsub_4 9617 0, // dsub_5 9618 0, // dsub_6 9619 0, // dsub_7 9620 0, // gsub_0 9621 0, // gsub_1 9622 0, // qqsub_0 9623 0, // qqsub_1 9624 0, // qsub_0 9625 0, // qsub_1 9626 0, // qsub_2 9627 0, // qsub_3 9628 0, // ssub_0 9629 0, // ssub_1 9630 0, // ssub_2 9631 0, // ssub_3 9632 0, // ssub_4 9633 0, // ssub_5 9634 0, // ssub_6 9635 0, // ssub_7 9636 0, // ssub_8 9637 0, // ssub_9 9638 0, // ssub_10 9639 0, // ssub_11 9640 0, // ssub_12 9641 0, // ssub_13 9642 0, // dsub_7_then_ssub_0 9643 0, // dsub_7_then_ssub_1 9644 0, // ssub_0_ssub_1_ssub_4_ssub_5 9645 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 9646 0, // ssub_2_ssub_3_ssub_6_ssub_7 9647 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 9648 0, // ssub_2_ssub_3_ssub_4_ssub_5 9649 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 9650 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9651 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 9652 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 9653 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9654 0, // ssub_4_ssub_5_ssub_8_ssub_9 9655 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9656 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9657 0, // ssub_6_ssub_7_dsub_5 9658 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 9659 0, // ssub_6_ssub_7_dsub_5_dsub_7 9660 0, // ssub_6_ssub_7_ssub_8_ssub_9 9661 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9662 0, // ssub_8_ssub_9_ssub_12_ssub_13 9663 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9664 0, // dsub_5_dsub_7 9665 0, // dsub_5_ssub_12_ssub_13_dsub_7 9666 0, // dsub_5_ssub_12_ssub_13 9667 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 9668 }, 9669 { // tGPROdd 9670 0, // dsub_0 9671 0, // dsub_1 9672 0, // dsub_2 9673 0, // dsub_3 9674 0, // dsub_4 9675 0, // dsub_5 9676 0, // dsub_6 9677 0, // dsub_7 9678 0, // gsub_0 9679 0, // gsub_1 9680 0, // qqsub_0 9681 0, // qqsub_1 9682 0, // qsub_0 9683 0, // qsub_1 9684 0, // qsub_2 9685 0, // qsub_3 9686 0, // ssub_0 9687 0, // ssub_1 9688 0, // ssub_2 9689 0, // ssub_3 9690 0, // ssub_4 9691 0, // ssub_5 9692 0, // ssub_6 9693 0, // ssub_7 9694 0, // ssub_8 9695 0, // ssub_9 9696 0, // ssub_10 9697 0, // ssub_11 9698 0, // ssub_12 9699 0, // ssub_13 9700 0, // dsub_7_then_ssub_0 9701 0, // dsub_7_then_ssub_1 9702 0, // ssub_0_ssub_1_ssub_4_ssub_5 9703 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 9704 0, // ssub_2_ssub_3_ssub_6_ssub_7 9705 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 9706 0, // ssub_2_ssub_3_ssub_4_ssub_5 9707 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 9708 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9709 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 9710 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 9711 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9712 0, // ssub_4_ssub_5_ssub_8_ssub_9 9713 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9714 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9715 0, // ssub_6_ssub_7_dsub_5 9716 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 9717 0, // ssub_6_ssub_7_dsub_5_dsub_7 9718 0, // ssub_6_ssub_7_ssub_8_ssub_9 9719 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9720 0, // ssub_8_ssub_9_ssub_12_ssub_13 9721 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9722 0, // dsub_5_dsub_7 9723 0, // dsub_5_ssub_12_ssub_13_dsub_7 9724 0, // dsub_5_ssub_12_ssub_13 9725 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 9726 }, 9727 { // tcGPR 9728 0, // dsub_0 9729 0, // dsub_1 9730 0, // dsub_2 9731 0, // dsub_3 9732 0, // dsub_4 9733 0, // dsub_5 9734 0, // dsub_6 9735 0, // dsub_7 9736 0, // gsub_0 9737 0, // gsub_1 9738 0, // qqsub_0 9739 0, // qqsub_1 9740 0, // qsub_0 9741 0, // qsub_1 9742 0, // qsub_2 9743 0, // qsub_3 9744 0, // ssub_0 9745 0, // ssub_1 9746 0, // ssub_2 9747 0, // ssub_3 9748 0, // ssub_4 9749 0, // ssub_5 9750 0, // ssub_6 9751 0, // ssub_7 9752 0, // ssub_8 9753 0, // ssub_9 9754 0, // ssub_10 9755 0, // ssub_11 9756 0, // ssub_12 9757 0, // ssub_13 9758 0, // dsub_7_then_ssub_0 9759 0, // dsub_7_then_ssub_1 9760 0, // ssub_0_ssub_1_ssub_4_ssub_5 9761 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 9762 0, // ssub_2_ssub_3_ssub_6_ssub_7 9763 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 9764 0, // ssub_2_ssub_3_ssub_4_ssub_5 9765 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 9766 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9767 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 9768 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 9769 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9770 0, // ssub_4_ssub_5_ssub_8_ssub_9 9771 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9772 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9773 0, // ssub_6_ssub_7_dsub_5 9774 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 9775 0, // ssub_6_ssub_7_dsub_5_dsub_7 9776 0, // ssub_6_ssub_7_ssub_8_ssub_9 9777 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9778 0, // ssub_8_ssub_9_ssub_12_ssub_13 9779 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9780 0, // dsub_5_dsub_7 9781 0, // dsub_5_ssub_12_ssub_13_dsub_7 9782 0, // dsub_5_ssub_12_ssub_13 9783 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 9784 }, 9785 { // hGPR_and_tGPREven 9786 0, // dsub_0 9787 0, // dsub_1 9788 0, // dsub_2 9789 0, // dsub_3 9790 0, // dsub_4 9791 0, // dsub_5 9792 0, // dsub_6 9793 0, // dsub_7 9794 0, // gsub_0 9795 0, // gsub_1 9796 0, // qqsub_0 9797 0, // qqsub_1 9798 0, // qsub_0 9799 0, // qsub_1 9800 0, // qsub_2 9801 0, // qsub_3 9802 0, // ssub_0 9803 0, // ssub_1 9804 0, // ssub_2 9805 0, // ssub_3 9806 0, // ssub_4 9807 0, // ssub_5 9808 0, // ssub_6 9809 0, // ssub_7 9810 0, // ssub_8 9811 0, // ssub_9 9812 0, // ssub_10 9813 0, // ssub_11 9814 0, // ssub_12 9815 0, // ssub_13 9816 0, // dsub_7_then_ssub_0 9817 0, // dsub_7_then_ssub_1 9818 0, // ssub_0_ssub_1_ssub_4_ssub_5 9819 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 9820 0, // ssub_2_ssub_3_ssub_6_ssub_7 9821 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 9822 0, // ssub_2_ssub_3_ssub_4_ssub_5 9823 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 9824 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9825 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 9826 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 9827 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9828 0, // ssub_4_ssub_5_ssub_8_ssub_9 9829 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9830 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9831 0, // ssub_6_ssub_7_dsub_5 9832 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 9833 0, // ssub_6_ssub_7_dsub_5_dsub_7 9834 0, // ssub_6_ssub_7_ssub_8_ssub_9 9835 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9836 0, // ssub_8_ssub_9_ssub_12_ssub_13 9837 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9838 0, // dsub_5_dsub_7 9839 0, // dsub_5_ssub_12_ssub_13_dsub_7 9840 0, // dsub_5_ssub_12_ssub_13 9841 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 9842 }, 9843 { // tGPR_and_tGPREven 9844 0, // dsub_0 9845 0, // dsub_1 9846 0, // dsub_2 9847 0, // dsub_3 9848 0, // dsub_4 9849 0, // dsub_5 9850 0, // dsub_6 9851 0, // dsub_7 9852 0, // gsub_0 9853 0, // gsub_1 9854 0, // qqsub_0 9855 0, // qqsub_1 9856 0, // qsub_0 9857 0, // qsub_1 9858 0, // qsub_2 9859 0, // qsub_3 9860 0, // ssub_0 9861 0, // ssub_1 9862 0, // ssub_2 9863 0, // ssub_3 9864 0, // ssub_4 9865 0, // ssub_5 9866 0, // ssub_6 9867 0, // ssub_7 9868 0, // ssub_8 9869 0, // ssub_9 9870 0, // ssub_10 9871 0, // ssub_11 9872 0, // ssub_12 9873 0, // ssub_13 9874 0, // dsub_7_then_ssub_0 9875 0, // dsub_7_then_ssub_1 9876 0, // ssub_0_ssub_1_ssub_4_ssub_5 9877 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 9878 0, // ssub_2_ssub_3_ssub_6_ssub_7 9879 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 9880 0, // ssub_2_ssub_3_ssub_4_ssub_5 9881 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 9882 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9883 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 9884 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 9885 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9886 0, // ssub_4_ssub_5_ssub_8_ssub_9 9887 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9888 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9889 0, // ssub_6_ssub_7_dsub_5 9890 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 9891 0, // ssub_6_ssub_7_dsub_5_dsub_7 9892 0, // ssub_6_ssub_7_ssub_8_ssub_9 9893 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9894 0, // ssub_8_ssub_9_ssub_12_ssub_13 9895 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9896 0, // dsub_5_dsub_7 9897 0, // dsub_5_ssub_12_ssub_13_dsub_7 9898 0, // dsub_5_ssub_12_ssub_13 9899 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 9900 }, 9901 { // tGPR_and_tGPROdd 9902 0, // dsub_0 9903 0, // dsub_1 9904 0, // dsub_2 9905 0, // dsub_3 9906 0, // dsub_4 9907 0, // dsub_5 9908 0, // dsub_6 9909 0, // dsub_7 9910 0, // gsub_0 9911 0, // gsub_1 9912 0, // qqsub_0 9913 0, // qqsub_1 9914 0, // qsub_0 9915 0, // qsub_1 9916 0, // qsub_2 9917 0, // qsub_3 9918 0, // ssub_0 9919 0, // ssub_1 9920 0, // ssub_2 9921 0, // ssub_3 9922 0, // ssub_4 9923 0, // ssub_5 9924 0, // ssub_6 9925 0, // ssub_7 9926 0, // ssub_8 9927 0, // ssub_9 9928 0, // ssub_10 9929 0, // ssub_11 9930 0, // ssub_12 9931 0, // ssub_13 9932 0, // dsub_7_then_ssub_0 9933 0, // dsub_7_then_ssub_1 9934 0, // ssub_0_ssub_1_ssub_4_ssub_5 9935 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 9936 0, // ssub_2_ssub_3_ssub_6_ssub_7 9937 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 9938 0, // ssub_2_ssub_3_ssub_4_ssub_5 9939 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 9940 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9941 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 9942 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 9943 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9944 0, // ssub_4_ssub_5_ssub_8_ssub_9 9945 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 9946 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9947 0, // ssub_6_ssub_7_dsub_5 9948 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 9949 0, // ssub_6_ssub_7_dsub_5_dsub_7 9950 0, // ssub_6_ssub_7_ssub_8_ssub_9 9951 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9952 0, // ssub_8_ssub_9_ssub_12_ssub_13 9953 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 9954 0, // dsub_5_dsub_7 9955 0, // dsub_5_ssub_12_ssub_13_dsub_7 9956 0, // dsub_5_ssub_12_ssub_13 9957 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 9958 }, 9959 { // tGPR_and_tcGPR 9960 0, // dsub_0 9961 0, // dsub_1 9962 0, // dsub_2 9963 0, // dsub_3 9964 0, // dsub_4 9965 0, // dsub_5 9966 0, // dsub_6 9967 0, // dsub_7 9968 0, // gsub_0 9969 0, // gsub_1 9970 0, // qqsub_0 9971 0, // qqsub_1 9972 0, // qsub_0 9973 0, // qsub_1 9974 0, // qsub_2 9975 0, // qsub_3 9976 0, // ssub_0 9977 0, // ssub_1 9978 0, // ssub_2 9979 0, // ssub_3 9980 0, // ssub_4 9981 0, // ssub_5 9982 0, // ssub_6 9983 0, // ssub_7 9984 0, // ssub_8 9985 0, // ssub_9 9986 0, // ssub_10 9987 0, // ssub_11 9988 0, // ssub_12 9989 0, // ssub_13 9990 0, // dsub_7_then_ssub_0 9991 0, // dsub_7_then_ssub_1 9992 0, // ssub_0_ssub_1_ssub_4_ssub_5 9993 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 9994 0, // ssub_2_ssub_3_ssub_6_ssub_7 9995 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 9996 0, // ssub_2_ssub_3_ssub_4_ssub_5 9997 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 9998 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 9999 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 10000 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 10001 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10002 0, // ssub_4_ssub_5_ssub_8_ssub_9 10003 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10004 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10005 0, // ssub_6_ssub_7_dsub_5 10006 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 10007 0, // ssub_6_ssub_7_dsub_5_dsub_7 10008 0, // ssub_6_ssub_7_ssub_8_ssub_9 10009 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10010 0, // ssub_8_ssub_9_ssub_12_ssub_13 10011 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10012 0, // dsub_5_dsub_7 10013 0, // dsub_5_ssub_12_ssub_13_dsub_7 10014 0, // dsub_5_ssub_12_ssub_13 10015 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 10016 }, 10017 { // tGPREven_and_tcGPR 10018 0, // dsub_0 10019 0, // dsub_1 10020 0, // dsub_2 10021 0, // dsub_3 10022 0, // dsub_4 10023 0, // dsub_5 10024 0, // dsub_6 10025 0, // dsub_7 10026 0, // gsub_0 10027 0, // gsub_1 10028 0, // qqsub_0 10029 0, // qqsub_1 10030 0, // qsub_0 10031 0, // qsub_1 10032 0, // qsub_2 10033 0, // qsub_3 10034 0, // ssub_0 10035 0, // ssub_1 10036 0, // ssub_2 10037 0, // ssub_3 10038 0, // ssub_4 10039 0, // ssub_5 10040 0, // ssub_6 10041 0, // ssub_7 10042 0, // ssub_8 10043 0, // ssub_9 10044 0, // ssub_10 10045 0, // ssub_11 10046 0, // ssub_12 10047 0, // ssub_13 10048 0, // dsub_7_then_ssub_0 10049 0, // dsub_7_then_ssub_1 10050 0, // ssub_0_ssub_1_ssub_4_ssub_5 10051 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 10052 0, // ssub_2_ssub_3_ssub_6_ssub_7 10053 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 10054 0, // ssub_2_ssub_3_ssub_4_ssub_5 10055 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 10056 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10057 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 10058 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 10059 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10060 0, // ssub_4_ssub_5_ssub_8_ssub_9 10061 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10062 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10063 0, // ssub_6_ssub_7_dsub_5 10064 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 10065 0, // ssub_6_ssub_7_dsub_5_dsub_7 10066 0, // ssub_6_ssub_7_ssub_8_ssub_9 10067 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10068 0, // ssub_8_ssub_9_ssub_12_ssub_13 10069 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10070 0, // dsub_5_dsub_7 10071 0, // dsub_5_ssub_12_ssub_13_dsub_7 10072 0, // dsub_5_ssub_12_ssub_13 10073 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 10074 }, 10075 { // hGPR_and_tGPROdd 10076 0, // dsub_0 10077 0, // dsub_1 10078 0, // dsub_2 10079 0, // dsub_3 10080 0, // dsub_4 10081 0, // dsub_5 10082 0, // dsub_6 10083 0, // dsub_7 10084 0, // gsub_0 10085 0, // gsub_1 10086 0, // qqsub_0 10087 0, // qqsub_1 10088 0, // qsub_0 10089 0, // qsub_1 10090 0, // qsub_2 10091 0, // qsub_3 10092 0, // ssub_0 10093 0, // ssub_1 10094 0, // ssub_2 10095 0, // ssub_3 10096 0, // ssub_4 10097 0, // ssub_5 10098 0, // ssub_6 10099 0, // ssub_7 10100 0, // ssub_8 10101 0, // ssub_9 10102 0, // ssub_10 10103 0, // ssub_11 10104 0, // ssub_12 10105 0, // ssub_13 10106 0, // dsub_7_then_ssub_0 10107 0, // dsub_7_then_ssub_1 10108 0, // ssub_0_ssub_1_ssub_4_ssub_5 10109 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 10110 0, // ssub_2_ssub_3_ssub_6_ssub_7 10111 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 10112 0, // ssub_2_ssub_3_ssub_4_ssub_5 10113 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 10114 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10115 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 10116 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 10117 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10118 0, // ssub_4_ssub_5_ssub_8_ssub_9 10119 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10120 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10121 0, // ssub_6_ssub_7_dsub_5 10122 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 10123 0, // ssub_6_ssub_7_dsub_5_dsub_7 10124 0, // ssub_6_ssub_7_ssub_8_ssub_9 10125 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10126 0, // ssub_8_ssub_9_ssub_12_ssub_13 10127 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10128 0, // dsub_5_dsub_7 10129 0, // dsub_5_ssub_12_ssub_13_dsub_7 10130 0, // dsub_5_ssub_12_ssub_13 10131 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 10132 }, 10133 { // tGPREven_and_tGPR_and_tcGPR 10134 0, // dsub_0 10135 0, // dsub_1 10136 0, // dsub_2 10137 0, // dsub_3 10138 0, // dsub_4 10139 0, // dsub_5 10140 0, // dsub_6 10141 0, // dsub_7 10142 0, // gsub_0 10143 0, // gsub_1 10144 0, // qqsub_0 10145 0, // qqsub_1 10146 0, // qsub_0 10147 0, // qsub_1 10148 0, // qsub_2 10149 0, // qsub_3 10150 0, // ssub_0 10151 0, // ssub_1 10152 0, // ssub_2 10153 0, // ssub_3 10154 0, // ssub_4 10155 0, // ssub_5 10156 0, // ssub_6 10157 0, // ssub_7 10158 0, // ssub_8 10159 0, // ssub_9 10160 0, // ssub_10 10161 0, // ssub_11 10162 0, // ssub_12 10163 0, // ssub_13 10164 0, // dsub_7_then_ssub_0 10165 0, // dsub_7_then_ssub_1 10166 0, // ssub_0_ssub_1_ssub_4_ssub_5 10167 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 10168 0, // ssub_2_ssub_3_ssub_6_ssub_7 10169 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 10170 0, // ssub_2_ssub_3_ssub_4_ssub_5 10171 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 10172 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10173 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 10174 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 10175 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10176 0, // ssub_4_ssub_5_ssub_8_ssub_9 10177 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10178 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10179 0, // ssub_6_ssub_7_dsub_5 10180 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 10181 0, // ssub_6_ssub_7_dsub_5_dsub_7 10182 0, // ssub_6_ssub_7_ssub_8_ssub_9 10183 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10184 0, // ssub_8_ssub_9_ssub_12_ssub_13 10185 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10186 0, // dsub_5_dsub_7 10187 0, // dsub_5_ssub_12_ssub_13_dsub_7 10188 0, // dsub_5_ssub_12_ssub_13 10189 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 10190 }, 10191 { // tGPROdd_and_tcGPR 10192 0, // dsub_0 10193 0, // dsub_1 10194 0, // dsub_2 10195 0, // dsub_3 10196 0, // dsub_4 10197 0, // dsub_5 10198 0, // dsub_6 10199 0, // dsub_7 10200 0, // gsub_0 10201 0, // gsub_1 10202 0, // qqsub_0 10203 0, // qqsub_1 10204 0, // qsub_0 10205 0, // qsub_1 10206 0, // qsub_2 10207 0, // qsub_3 10208 0, // ssub_0 10209 0, // ssub_1 10210 0, // ssub_2 10211 0, // ssub_3 10212 0, // ssub_4 10213 0, // ssub_5 10214 0, // ssub_6 10215 0, // ssub_7 10216 0, // ssub_8 10217 0, // ssub_9 10218 0, // ssub_10 10219 0, // ssub_11 10220 0, // ssub_12 10221 0, // ssub_13 10222 0, // dsub_7_then_ssub_0 10223 0, // dsub_7_then_ssub_1 10224 0, // ssub_0_ssub_1_ssub_4_ssub_5 10225 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 10226 0, // ssub_2_ssub_3_ssub_6_ssub_7 10227 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 10228 0, // ssub_2_ssub_3_ssub_4_ssub_5 10229 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 10230 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10231 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 10232 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 10233 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10234 0, // ssub_4_ssub_5_ssub_8_ssub_9 10235 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10236 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10237 0, // ssub_6_ssub_7_dsub_5 10238 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 10239 0, // ssub_6_ssub_7_dsub_5_dsub_7 10240 0, // ssub_6_ssub_7_ssub_8_ssub_9 10241 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10242 0, // ssub_8_ssub_9_ssub_12_ssub_13 10243 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10244 0, // dsub_5_dsub_7 10245 0, // dsub_5_ssub_12_ssub_13_dsub_7 10246 0, // dsub_5_ssub_12_ssub_13 10247 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 10248 }, 10249 { // CCR 10250 0, // dsub_0 10251 0, // dsub_1 10252 0, // dsub_2 10253 0, // dsub_3 10254 0, // dsub_4 10255 0, // dsub_5 10256 0, // dsub_6 10257 0, // dsub_7 10258 0, // gsub_0 10259 0, // gsub_1 10260 0, // qqsub_0 10261 0, // qqsub_1 10262 0, // qsub_0 10263 0, // qsub_1 10264 0, // qsub_2 10265 0, // qsub_3 10266 0, // ssub_0 10267 0, // ssub_1 10268 0, // ssub_2 10269 0, // ssub_3 10270 0, // ssub_4 10271 0, // ssub_5 10272 0, // ssub_6 10273 0, // ssub_7 10274 0, // ssub_8 10275 0, // ssub_9 10276 0, // ssub_10 10277 0, // ssub_11 10278 0, // ssub_12 10279 0, // ssub_13 10280 0, // dsub_7_then_ssub_0 10281 0, // dsub_7_then_ssub_1 10282 0, // ssub_0_ssub_1_ssub_4_ssub_5 10283 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 10284 0, // ssub_2_ssub_3_ssub_6_ssub_7 10285 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 10286 0, // ssub_2_ssub_3_ssub_4_ssub_5 10287 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 10288 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10289 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 10290 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 10291 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10292 0, // ssub_4_ssub_5_ssub_8_ssub_9 10293 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10294 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10295 0, // ssub_6_ssub_7_dsub_5 10296 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 10297 0, // ssub_6_ssub_7_dsub_5_dsub_7 10298 0, // ssub_6_ssub_7_ssub_8_ssub_9 10299 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10300 0, // ssub_8_ssub_9_ssub_12_ssub_13 10301 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10302 0, // dsub_5_dsub_7 10303 0, // dsub_5_ssub_12_ssub_13_dsub_7 10304 0, // dsub_5_ssub_12_ssub_13 10305 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 10306 }, 10307 { // GPRlr 10308 0, // dsub_0 10309 0, // dsub_1 10310 0, // dsub_2 10311 0, // dsub_3 10312 0, // dsub_4 10313 0, // dsub_5 10314 0, // dsub_6 10315 0, // dsub_7 10316 0, // gsub_0 10317 0, // gsub_1 10318 0, // qqsub_0 10319 0, // qqsub_1 10320 0, // qsub_0 10321 0, // qsub_1 10322 0, // qsub_2 10323 0, // qsub_3 10324 0, // ssub_0 10325 0, // ssub_1 10326 0, // ssub_2 10327 0, // ssub_3 10328 0, // ssub_4 10329 0, // ssub_5 10330 0, // ssub_6 10331 0, // ssub_7 10332 0, // ssub_8 10333 0, // ssub_9 10334 0, // ssub_10 10335 0, // ssub_11 10336 0, // ssub_12 10337 0, // ssub_13 10338 0, // dsub_7_then_ssub_0 10339 0, // dsub_7_then_ssub_1 10340 0, // ssub_0_ssub_1_ssub_4_ssub_5 10341 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 10342 0, // ssub_2_ssub_3_ssub_6_ssub_7 10343 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 10344 0, // ssub_2_ssub_3_ssub_4_ssub_5 10345 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 10346 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10347 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 10348 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 10349 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10350 0, // ssub_4_ssub_5_ssub_8_ssub_9 10351 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10352 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10353 0, // ssub_6_ssub_7_dsub_5 10354 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 10355 0, // ssub_6_ssub_7_dsub_5_dsub_7 10356 0, // ssub_6_ssub_7_ssub_8_ssub_9 10357 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10358 0, // ssub_8_ssub_9_ssub_12_ssub_13 10359 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10360 0, // dsub_5_dsub_7 10361 0, // dsub_5_ssub_12_ssub_13_dsub_7 10362 0, // dsub_5_ssub_12_ssub_13 10363 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 10364 }, 10365 { // GPRsp 10366 0, // dsub_0 10367 0, // dsub_1 10368 0, // dsub_2 10369 0, // dsub_3 10370 0, // dsub_4 10371 0, // dsub_5 10372 0, // dsub_6 10373 0, // dsub_7 10374 0, // gsub_0 10375 0, // gsub_1 10376 0, // qqsub_0 10377 0, // qqsub_1 10378 0, // qsub_0 10379 0, // qsub_1 10380 0, // qsub_2 10381 0, // qsub_3 10382 0, // ssub_0 10383 0, // ssub_1 10384 0, // ssub_2 10385 0, // ssub_3 10386 0, // ssub_4 10387 0, // ssub_5 10388 0, // ssub_6 10389 0, // ssub_7 10390 0, // ssub_8 10391 0, // ssub_9 10392 0, // ssub_10 10393 0, // ssub_11 10394 0, // ssub_12 10395 0, // ssub_13 10396 0, // dsub_7_then_ssub_0 10397 0, // dsub_7_then_ssub_1 10398 0, // ssub_0_ssub_1_ssub_4_ssub_5 10399 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 10400 0, // ssub_2_ssub_3_ssub_6_ssub_7 10401 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 10402 0, // ssub_2_ssub_3_ssub_4_ssub_5 10403 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 10404 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10405 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 10406 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 10407 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10408 0, // ssub_4_ssub_5_ssub_8_ssub_9 10409 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10410 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10411 0, // ssub_6_ssub_7_dsub_5 10412 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 10413 0, // ssub_6_ssub_7_dsub_5_dsub_7 10414 0, // ssub_6_ssub_7_ssub_8_ssub_9 10415 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10416 0, // ssub_8_ssub_9_ssub_12_ssub_13 10417 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10418 0, // dsub_5_dsub_7 10419 0, // dsub_5_ssub_12_ssub_13_dsub_7 10420 0, // dsub_5_ssub_12_ssub_13 10421 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 10422 }, 10423 { // VCCR 10424 0, // dsub_0 10425 0, // dsub_1 10426 0, // dsub_2 10427 0, // dsub_3 10428 0, // dsub_4 10429 0, // dsub_5 10430 0, // dsub_6 10431 0, // dsub_7 10432 0, // gsub_0 10433 0, // gsub_1 10434 0, // qqsub_0 10435 0, // qqsub_1 10436 0, // qsub_0 10437 0, // qsub_1 10438 0, // qsub_2 10439 0, // qsub_3 10440 0, // ssub_0 10441 0, // ssub_1 10442 0, // ssub_2 10443 0, // ssub_3 10444 0, // ssub_4 10445 0, // ssub_5 10446 0, // ssub_6 10447 0, // ssub_7 10448 0, // ssub_8 10449 0, // ssub_9 10450 0, // ssub_10 10451 0, // ssub_11 10452 0, // ssub_12 10453 0, // ssub_13 10454 0, // dsub_7_then_ssub_0 10455 0, // dsub_7_then_ssub_1 10456 0, // ssub_0_ssub_1_ssub_4_ssub_5 10457 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 10458 0, // ssub_2_ssub_3_ssub_6_ssub_7 10459 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 10460 0, // ssub_2_ssub_3_ssub_4_ssub_5 10461 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 10462 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10463 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 10464 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 10465 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10466 0, // ssub_4_ssub_5_ssub_8_ssub_9 10467 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10468 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10469 0, // ssub_6_ssub_7_dsub_5 10470 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 10471 0, // ssub_6_ssub_7_dsub_5_dsub_7 10472 0, // ssub_6_ssub_7_ssub_8_ssub_9 10473 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10474 0, // ssub_8_ssub_9_ssub_12_ssub_13 10475 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10476 0, // dsub_5_dsub_7 10477 0, // dsub_5_ssub_12_ssub_13_dsub_7 10478 0, // dsub_5_ssub_12_ssub_13 10479 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 10480 }, 10481 { // cl_FPSCR_NZCV 10482 0, // dsub_0 10483 0, // dsub_1 10484 0, // dsub_2 10485 0, // dsub_3 10486 0, // dsub_4 10487 0, // dsub_5 10488 0, // dsub_6 10489 0, // dsub_7 10490 0, // gsub_0 10491 0, // gsub_1 10492 0, // qqsub_0 10493 0, // qqsub_1 10494 0, // qsub_0 10495 0, // qsub_1 10496 0, // qsub_2 10497 0, // qsub_3 10498 0, // ssub_0 10499 0, // ssub_1 10500 0, // ssub_2 10501 0, // ssub_3 10502 0, // ssub_4 10503 0, // ssub_5 10504 0, // ssub_6 10505 0, // ssub_7 10506 0, // ssub_8 10507 0, // ssub_9 10508 0, // ssub_10 10509 0, // ssub_11 10510 0, // ssub_12 10511 0, // ssub_13 10512 0, // dsub_7_then_ssub_0 10513 0, // dsub_7_then_ssub_1 10514 0, // ssub_0_ssub_1_ssub_4_ssub_5 10515 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 10516 0, // ssub_2_ssub_3_ssub_6_ssub_7 10517 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 10518 0, // ssub_2_ssub_3_ssub_4_ssub_5 10519 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 10520 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10521 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 10522 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 10523 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10524 0, // ssub_4_ssub_5_ssub_8_ssub_9 10525 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10526 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10527 0, // ssub_6_ssub_7_dsub_5 10528 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 10529 0, // ssub_6_ssub_7_dsub_5_dsub_7 10530 0, // ssub_6_ssub_7_ssub_8_ssub_9 10531 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10532 0, // ssub_8_ssub_9_ssub_12_ssub_13 10533 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10534 0, // dsub_5_dsub_7 10535 0, // dsub_5_ssub_12_ssub_13_dsub_7 10536 0, // dsub_5_ssub_12_ssub_13 10537 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 10538 }, 10539 { // hGPR_and_tGPRwithpc 10540 0, // dsub_0 10541 0, // dsub_1 10542 0, // dsub_2 10543 0, // dsub_3 10544 0, // dsub_4 10545 0, // dsub_5 10546 0, // dsub_6 10547 0, // dsub_7 10548 0, // gsub_0 10549 0, // gsub_1 10550 0, // qqsub_0 10551 0, // qqsub_1 10552 0, // qsub_0 10553 0, // qsub_1 10554 0, // qsub_2 10555 0, // qsub_3 10556 0, // ssub_0 10557 0, // ssub_1 10558 0, // ssub_2 10559 0, // ssub_3 10560 0, // ssub_4 10561 0, // ssub_5 10562 0, // ssub_6 10563 0, // ssub_7 10564 0, // ssub_8 10565 0, // ssub_9 10566 0, // ssub_10 10567 0, // ssub_11 10568 0, // ssub_12 10569 0, // ssub_13 10570 0, // dsub_7_then_ssub_0 10571 0, // dsub_7_then_ssub_1 10572 0, // ssub_0_ssub_1_ssub_4_ssub_5 10573 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 10574 0, // ssub_2_ssub_3_ssub_6_ssub_7 10575 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 10576 0, // ssub_2_ssub_3_ssub_4_ssub_5 10577 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 10578 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10579 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 10580 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 10581 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10582 0, // ssub_4_ssub_5_ssub_8_ssub_9 10583 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10584 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10585 0, // ssub_6_ssub_7_dsub_5 10586 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 10587 0, // ssub_6_ssub_7_dsub_5_dsub_7 10588 0, // ssub_6_ssub_7_ssub_8_ssub_9 10589 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10590 0, // ssub_8_ssub_9_ssub_12_ssub_13 10591 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10592 0, // dsub_5_dsub_7 10593 0, // dsub_5_ssub_12_ssub_13_dsub_7 10594 0, // dsub_5_ssub_12_ssub_13 10595 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 10596 }, 10597 { // hGPR_and_tcGPR 10598 0, // dsub_0 10599 0, // dsub_1 10600 0, // dsub_2 10601 0, // dsub_3 10602 0, // dsub_4 10603 0, // dsub_5 10604 0, // dsub_6 10605 0, // dsub_7 10606 0, // gsub_0 10607 0, // gsub_1 10608 0, // qqsub_0 10609 0, // qqsub_1 10610 0, // qsub_0 10611 0, // qsub_1 10612 0, // qsub_2 10613 0, // qsub_3 10614 0, // ssub_0 10615 0, // ssub_1 10616 0, // ssub_2 10617 0, // ssub_3 10618 0, // ssub_4 10619 0, // ssub_5 10620 0, // ssub_6 10621 0, // ssub_7 10622 0, // ssub_8 10623 0, // ssub_9 10624 0, // ssub_10 10625 0, // ssub_11 10626 0, // ssub_12 10627 0, // ssub_13 10628 0, // dsub_7_then_ssub_0 10629 0, // dsub_7_then_ssub_1 10630 0, // ssub_0_ssub_1_ssub_4_ssub_5 10631 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 10632 0, // ssub_2_ssub_3_ssub_6_ssub_7 10633 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 10634 0, // ssub_2_ssub_3_ssub_4_ssub_5 10635 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 10636 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10637 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 10638 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 10639 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10640 0, // ssub_4_ssub_5_ssub_8_ssub_9 10641 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10642 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10643 0, // ssub_6_ssub_7_dsub_5 10644 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 10645 0, // ssub_6_ssub_7_dsub_5_dsub_7 10646 0, // ssub_6_ssub_7_ssub_8_ssub_9 10647 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10648 0, // ssub_8_ssub_9_ssub_12_ssub_13 10649 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10650 0, // dsub_5_dsub_7 10651 0, // dsub_5_ssub_12_ssub_13_dsub_7 10652 0, // dsub_5_ssub_12_ssub_13 10653 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 10654 }, 10655 { // DPR 10656 0, // dsub_0 10657 0, // dsub_1 10658 0, // dsub_2 10659 0, // dsub_3 10660 0, // dsub_4 10661 0, // dsub_5 10662 0, // dsub_6 10663 0, // dsub_7 10664 0, // gsub_0 10665 0, // gsub_1 10666 0, // qqsub_0 10667 0, // qqsub_1 10668 0, // qsub_0 10669 0, // qsub_1 10670 0, // qsub_2 10671 0, // qsub_3 10672 38, // ssub_0 -> DPR_VFP2 10673 38, // ssub_1 -> DPR_VFP2 10674 0, // ssub_2 10675 0, // ssub_3 10676 0, // ssub_4 10677 0, // ssub_5 10678 0, // ssub_6 10679 0, // ssub_7 10680 0, // ssub_8 10681 0, // ssub_9 10682 0, // ssub_10 10683 0, // ssub_11 10684 0, // ssub_12 10685 0, // ssub_13 10686 0, // dsub_7_then_ssub_0 10687 0, // dsub_7_then_ssub_1 10688 0, // ssub_0_ssub_1_ssub_4_ssub_5 10689 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 10690 0, // ssub_2_ssub_3_ssub_6_ssub_7 10691 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 10692 0, // ssub_2_ssub_3_ssub_4_ssub_5 10693 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 10694 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10695 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 10696 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 10697 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10698 0, // ssub_4_ssub_5_ssub_8_ssub_9 10699 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10700 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10701 0, // ssub_6_ssub_7_dsub_5 10702 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 10703 0, // ssub_6_ssub_7_dsub_5_dsub_7 10704 0, // ssub_6_ssub_7_ssub_8_ssub_9 10705 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10706 0, // ssub_8_ssub_9_ssub_12_ssub_13 10707 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10708 0, // dsub_5_dsub_7 10709 0, // dsub_5_ssub_12_ssub_13_dsub_7 10710 0, // dsub_5_ssub_12_ssub_13 10711 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 10712 }, 10713 { // DPR_VFP2 10714 0, // dsub_0 10715 0, // dsub_1 10716 0, // dsub_2 10717 0, // dsub_3 10718 0, // dsub_4 10719 0, // dsub_5 10720 0, // dsub_6 10721 0, // dsub_7 10722 0, // gsub_0 10723 0, // gsub_1 10724 0, // qqsub_0 10725 0, // qqsub_1 10726 0, // qsub_0 10727 0, // qsub_1 10728 0, // qsub_2 10729 0, // qsub_3 10730 38, // ssub_0 -> DPR_VFP2 10731 38, // ssub_1 -> DPR_VFP2 10732 0, // ssub_2 10733 0, // ssub_3 10734 0, // ssub_4 10735 0, // ssub_5 10736 0, // ssub_6 10737 0, // ssub_7 10738 0, // ssub_8 10739 0, // ssub_9 10740 0, // ssub_10 10741 0, // ssub_11 10742 0, // ssub_12 10743 0, // ssub_13 10744 0, // dsub_7_then_ssub_0 10745 0, // dsub_7_then_ssub_1 10746 0, // ssub_0_ssub_1_ssub_4_ssub_5 10747 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 10748 0, // ssub_2_ssub_3_ssub_6_ssub_7 10749 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 10750 0, // ssub_2_ssub_3_ssub_4_ssub_5 10751 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 10752 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10753 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 10754 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 10755 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10756 0, // ssub_4_ssub_5_ssub_8_ssub_9 10757 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10758 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10759 0, // ssub_6_ssub_7_dsub_5 10760 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 10761 0, // ssub_6_ssub_7_dsub_5_dsub_7 10762 0, // ssub_6_ssub_7_ssub_8_ssub_9 10763 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10764 0, // ssub_8_ssub_9_ssub_12_ssub_13 10765 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10766 0, // dsub_5_dsub_7 10767 0, // dsub_5_ssub_12_ssub_13_dsub_7 10768 0, // dsub_5_ssub_12_ssub_13 10769 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 10770 }, 10771 { // DPR_8 10772 0, // dsub_0 10773 0, // dsub_1 10774 0, // dsub_2 10775 0, // dsub_3 10776 0, // dsub_4 10777 0, // dsub_5 10778 0, // dsub_6 10779 0, // dsub_7 10780 0, // gsub_0 10781 0, // gsub_1 10782 0, // qqsub_0 10783 0, // qqsub_1 10784 0, // qsub_0 10785 0, // qsub_1 10786 0, // qsub_2 10787 0, // qsub_3 10788 39, // ssub_0 -> DPR_8 10789 39, // ssub_1 -> DPR_8 10790 0, // ssub_2 10791 0, // ssub_3 10792 0, // ssub_4 10793 0, // ssub_5 10794 0, // ssub_6 10795 0, // ssub_7 10796 0, // ssub_8 10797 0, // ssub_9 10798 0, // ssub_10 10799 0, // ssub_11 10800 0, // ssub_12 10801 0, // ssub_13 10802 0, // dsub_7_then_ssub_0 10803 0, // dsub_7_then_ssub_1 10804 0, // ssub_0_ssub_1_ssub_4_ssub_5 10805 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 10806 0, // ssub_2_ssub_3_ssub_6_ssub_7 10807 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 10808 0, // ssub_2_ssub_3_ssub_4_ssub_5 10809 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 10810 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10811 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 10812 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 10813 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10814 0, // ssub_4_ssub_5_ssub_8_ssub_9 10815 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10816 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10817 0, // ssub_6_ssub_7_dsub_5 10818 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 10819 0, // ssub_6_ssub_7_dsub_5_dsub_7 10820 0, // ssub_6_ssub_7_ssub_8_ssub_9 10821 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10822 0, // ssub_8_ssub_9_ssub_12_ssub_13 10823 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10824 0, // dsub_5_dsub_7 10825 0, // dsub_5_ssub_12_ssub_13_dsub_7 10826 0, // dsub_5_ssub_12_ssub_13 10827 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 10828 }, 10829 { // GPRPair 10830 0, // dsub_0 10831 0, // dsub_1 10832 0, // dsub_2 10833 0, // dsub_3 10834 0, // dsub_4 10835 0, // dsub_5 10836 0, // dsub_6 10837 0, // dsub_7 10838 40, // gsub_0 -> GPRPair 10839 40, // gsub_1 -> GPRPair 10840 0, // qqsub_0 10841 0, // qqsub_1 10842 0, // qsub_0 10843 0, // qsub_1 10844 0, // qsub_2 10845 0, // qsub_3 10846 0, // ssub_0 10847 0, // ssub_1 10848 0, // ssub_2 10849 0, // ssub_3 10850 0, // ssub_4 10851 0, // ssub_5 10852 0, // ssub_6 10853 0, // ssub_7 10854 0, // ssub_8 10855 0, // ssub_9 10856 0, // ssub_10 10857 0, // ssub_11 10858 0, // ssub_12 10859 0, // ssub_13 10860 0, // dsub_7_then_ssub_0 10861 0, // dsub_7_then_ssub_1 10862 0, // ssub_0_ssub_1_ssub_4_ssub_5 10863 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 10864 0, // ssub_2_ssub_3_ssub_6_ssub_7 10865 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 10866 0, // ssub_2_ssub_3_ssub_4_ssub_5 10867 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 10868 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10869 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 10870 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 10871 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10872 0, // ssub_4_ssub_5_ssub_8_ssub_9 10873 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10874 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10875 0, // ssub_6_ssub_7_dsub_5 10876 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 10877 0, // ssub_6_ssub_7_dsub_5_dsub_7 10878 0, // ssub_6_ssub_7_ssub_8_ssub_9 10879 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10880 0, // ssub_8_ssub_9_ssub_12_ssub_13 10881 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10882 0, // dsub_5_dsub_7 10883 0, // dsub_5_ssub_12_ssub_13_dsub_7 10884 0, // dsub_5_ssub_12_ssub_13 10885 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 10886 }, 10887 { // GPRPairnosp 10888 0, // dsub_0 10889 0, // dsub_1 10890 0, // dsub_2 10891 0, // dsub_3 10892 0, // dsub_4 10893 0, // dsub_5 10894 0, // dsub_6 10895 0, // dsub_7 10896 41, // gsub_0 -> GPRPairnosp 10897 41, // gsub_1 -> GPRPairnosp 10898 0, // qqsub_0 10899 0, // qqsub_1 10900 0, // qsub_0 10901 0, // qsub_1 10902 0, // qsub_2 10903 0, // qsub_3 10904 0, // ssub_0 10905 0, // ssub_1 10906 0, // ssub_2 10907 0, // ssub_3 10908 0, // ssub_4 10909 0, // ssub_5 10910 0, // ssub_6 10911 0, // ssub_7 10912 0, // ssub_8 10913 0, // ssub_9 10914 0, // ssub_10 10915 0, // ssub_11 10916 0, // ssub_12 10917 0, // ssub_13 10918 0, // dsub_7_then_ssub_0 10919 0, // dsub_7_then_ssub_1 10920 0, // ssub_0_ssub_1_ssub_4_ssub_5 10921 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 10922 0, // ssub_2_ssub_3_ssub_6_ssub_7 10923 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 10924 0, // ssub_2_ssub_3_ssub_4_ssub_5 10925 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 10926 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10927 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 10928 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 10929 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10930 0, // ssub_4_ssub_5_ssub_8_ssub_9 10931 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10932 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10933 0, // ssub_6_ssub_7_dsub_5 10934 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 10935 0, // ssub_6_ssub_7_dsub_5_dsub_7 10936 0, // ssub_6_ssub_7_ssub_8_ssub_9 10937 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10938 0, // ssub_8_ssub_9_ssub_12_ssub_13 10939 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10940 0, // dsub_5_dsub_7 10941 0, // dsub_5_ssub_12_ssub_13_dsub_7 10942 0, // dsub_5_ssub_12_ssub_13 10943 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 10944 }, 10945 { // GPRPair_with_gsub_0_in_tGPR 10946 0, // dsub_0 10947 0, // dsub_1 10948 0, // dsub_2 10949 0, // dsub_3 10950 0, // dsub_4 10951 0, // dsub_5 10952 0, // dsub_6 10953 0, // dsub_7 10954 42, // gsub_0 -> GPRPair_with_gsub_0_in_tGPR 10955 42, // gsub_1 -> GPRPair_with_gsub_0_in_tGPR 10956 0, // qqsub_0 10957 0, // qqsub_1 10958 0, // qsub_0 10959 0, // qsub_1 10960 0, // qsub_2 10961 0, // qsub_3 10962 0, // ssub_0 10963 0, // ssub_1 10964 0, // ssub_2 10965 0, // ssub_3 10966 0, // ssub_4 10967 0, // ssub_5 10968 0, // ssub_6 10969 0, // ssub_7 10970 0, // ssub_8 10971 0, // ssub_9 10972 0, // ssub_10 10973 0, // ssub_11 10974 0, // ssub_12 10975 0, // ssub_13 10976 0, // dsub_7_then_ssub_0 10977 0, // dsub_7_then_ssub_1 10978 0, // ssub_0_ssub_1_ssub_4_ssub_5 10979 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 10980 0, // ssub_2_ssub_3_ssub_6_ssub_7 10981 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 10982 0, // ssub_2_ssub_3_ssub_4_ssub_5 10983 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 10984 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10985 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 10986 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 10987 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10988 0, // ssub_4_ssub_5_ssub_8_ssub_9 10989 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 10990 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 10991 0, // ssub_6_ssub_7_dsub_5 10992 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 10993 0, // ssub_6_ssub_7_dsub_5_dsub_7 10994 0, // ssub_6_ssub_7_ssub_8_ssub_9 10995 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10996 0, // ssub_8_ssub_9_ssub_12_ssub_13 10997 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 10998 0, // dsub_5_dsub_7 10999 0, // dsub_5_ssub_12_ssub_13_dsub_7 11000 0, // dsub_5_ssub_12_ssub_13 11001 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 11002 }, 11003 { // GPRPair_with_gsub_0_in_hGPR 11004 0, // dsub_0 11005 0, // dsub_1 11006 0, // dsub_2 11007 0, // dsub_3 11008 0, // dsub_4 11009 0, // dsub_5 11010 0, // dsub_6 11011 0, // dsub_7 11012 43, // gsub_0 -> GPRPair_with_gsub_0_in_hGPR 11013 43, // gsub_1 -> GPRPair_with_gsub_0_in_hGPR 11014 0, // qqsub_0 11015 0, // qqsub_1 11016 0, // qsub_0 11017 0, // qsub_1 11018 0, // qsub_2 11019 0, // qsub_3 11020 0, // ssub_0 11021 0, // ssub_1 11022 0, // ssub_2 11023 0, // ssub_3 11024 0, // ssub_4 11025 0, // ssub_5 11026 0, // ssub_6 11027 0, // ssub_7 11028 0, // ssub_8 11029 0, // ssub_9 11030 0, // ssub_10 11031 0, // ssub_11 11032 0, // ssub_12 11033 0, // ssub_13 11034 0, // dsub_7_then_ssub_0 11035 0, // dsub_7_then_ssub_1 11036 0, // ssub_0_ssub_1_ssub_4_ssub_5 11037 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 11038 0, // ssub_2_ssub_3_ssub_6_ssub_7 11039 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 11040 0, // ssub_2_ssub_3_ssub_4_ssub_5 11041 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 11042 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11043 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 11044 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 11045 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11046 0, // ssub_4_ssub_5_ssub_8_ssub_9 11047 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11048 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11049 0, // ssub_6_ssub_7_dsub_5 11050 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 11051 0, // ssub_6_ssub_7_dsub_5_dsub_7 11052 0, // ssub_6_ssub_7_ssub_8_ssub_9 11053 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11054 0, // ssub_8_ssub_9_ssub_12_ssub_13 11055 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11056 0, // dsub_5_dsub_7 11057 0, // dsub_5_ssub_12_ssub_13_dsub_7 11058 0, // dsub_5_ssub_12_ssub_13 11059 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 11060 }, 11061 { // GPRPair_with_gsub_0_in_tcGPR 11062 0, // dsub_0 11063 0, // dsub_1 11064 0, // dsub_2 11065 0, // dsub_3 11066 0, // dsub_4 11067 0, // dsub_5 11068 0, // dsub_6 11069 0, // dsub_7 11070 44, // gsub_0 -> GPRPair_with_gsub_0_in_tcGPR 11071 44, // gsub_1 -> GPRPair_with_gsub_0_in_tcGPR 11072 0, // qqsub_0 11073 0, // qqsub_1 11074 0, // qsub_0 11075 0, // qsub_1 11076 0, // qsub_2 11077 0, // qsub_3 11078 0, // ssub_0 11079 0, // ssub_1 11080 0, // ssub_2 11081 0, // ssub_3 11082 0, // ssub_4 11083 0, // ssub_5 11084 0, // ssub_6 11085 0, // ssub_7 11086 0, // ssub_8 11087 0, // ssub_9 11088 0, // ssub_10 11089 0, // ssub_11 11090 0, // ssub_12 11091 0, // ssub_13 11092 0, // dsub_7_then_ssub_0 11093 0, // dsub_7_then_ssub_1 11094 0, // ssub_0_ssub_1_ssub_4_ssub_5 11095 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 11096 0, // ssub_2_ssub_3_ssub_6_ssub_7 11097 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 11098 0, // ssub_2_ssub_3_ssub_4_ssub_5 11099 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 11100 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11101 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 11102 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 11103 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11104 0, // ssub_4_ssub_5_ssub_8_ssub_9 11105 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11106 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11107 0, // ssub_6_ssub_7_dsub_5 11108 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 11109 0, // ssub_6_ssub_7_dsub_5_dsub_7 11110 0, // ssub_6_ssub_7_ssub_8_ssub_9 11111 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11112 0, // ssub_8_ssub_9_ssub_12_ssub_13 11113 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11114 0, // dsub_5_dsub_7 11115 0, // dsub_5_ssub_12_ssub_13_dsub_7 11116 0, // dsub_5_ssub_12_ssub_13 11117 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 11118 }, 11119 { // GPRPair_with_gsub_1_in_tcGPR 11120 0, // dsub_0 11121 0, // dsub_1 11122 0, // dsub_2 11123 0, // dsub_3 11124 0, // dsub_4 11125 0, // dsub_5 11126 0, // dsub_6 11127 0, // dsub_7 11128 45, // gsub_0 -> GPRPair_with_gsub_1_in_tcGPR 11129 45, // gsub_1 -> GPRPair_with_gsub_1_in_tcGPR 11130 0, // qqsub_0 11131 0, // qqsub_1 11132 0, // qsub_0 11133 0, // qsub_1 11134 0, // qsub_2 11135 0, // qsub_3 11136 0, // ssub_0 11137 0, // ssub_1 11138 0, // ssub_2 11139 0, // ssub_3 11140 0, // ssub_4 11141 0, // ssub_5 11142 0, // ssub_6 11143 0, // ssub_7 11144 0, // ssub_8 11145 0, // ssub_9 11146 0, // ssub_10 11147 0, // ssub_11 11148 0, // ssub_12 11149 0, // ssub_13 11150 0, // dsub_7_then_ssub_0 11151 0, // dsub_7_then_ssub_1 11152 0, // ssub_0_ssub_1_ssub_4_ssub_5 11153 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 11154 0, // ssub_2_ssub_3_ssub_6_ssub_7 11155 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 11156 0, // ssub_2_ssub_3_ssub_4_ssub_5 11157 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 11158 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11159 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 11160 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 11161 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11162 0, // ssub_4_ssub_5_ssub_8_ssub_9 11163 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11164 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11165 0, // ssub_6_ssub_7_dsub_5 11166 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 11167 0, // ssub_6_ssub_7_dsub_5_dsub_7 11168 0, // ssub_6_ssub_7_ssub_8_ssub_9 11169 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11170 0, // ssub_8_ssub_9_ssub_12_ssub_13 11171 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11172 0, // dsub_5_dsub_7 11173 0, // dsub_5_ssub_12_ssub_13_dsub_7 11174 0, // dsub_5_ssub_12_ssub_13 11175 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 11176 }, 11177 { // GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR 11178 0, // dsub_0 11179 0, // dsub_1 11180 0, // dsub_2 11181 0, // dsub_3 11182 0, // dsub_4 11183 0, // dsub_5 11184 0, // dsub_6 11185 0, // dsub_7 11186 46, // gsub_0 -> GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR 11187 46, // gsub_1 -> GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR 11188 0, // qqsub_0 11189 0, // qqsub_1 11190 0, // qsub_0 11191 0, // qsub_1 11192 0, // qsub_2 11193 0, // qsub_3 11194 0, // ssub_0 11195 0, // ssub_1 11196 0, // ssub_2 11197 0, // ssub_3 11198 0, // ssub_4 11199 0, // ssub_5 11200 0, // ssub_6 11201 0, // ssub_7 11202 0, // ssub_8 11203 0, // ssub_9 11204 0, // ssub_10 11205 0, // ssub_11 11206 0, // ssub_12 11207 0, // ssub_13 11208 0, // dsub_7_then_ssub_0 11209 0, // dsub_7_then_ssub_1 11210 0, // ssub_0_ssub_1_ssub_4_ssub_5 11211 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 11212 0, // ssub_2_ssub_3_ssub_6_ssub_7 11213 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 11214 0, // ssub_2_ssub_3_ssub_4_ssub_5 11215 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 11216 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11217 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 11218 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 11219 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11220 0, // ssub_4_ssub_5_ssub_8_ssub_9 11221 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11222 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11223 0, // ssub_6_ssub_7_dsub_5 11224 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 11225 0, // ssub_6_ssub_7_dsub_5_dsub_7 11226 0, // ssub_6_ssub_7_ssub_8_ssub_9 11227 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11228 0, // ssub_8_ssub_9_ssub_12_ssub_13 11229 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11230 0, // dsub_5_dsub_7 11231 0, // dsub_5_ssub_12_ssub_13_dsub_7 11232 0, // dsub_5_ssub_12_ssub_13 11233 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 11234 }, 11235 { // GPRPair_with_gsub_1_in_GPRsp 11236 0, // dsub_0 11237 0, // dsub_1 11238 0, // dsub_2 11239 0, // dsub_3 11240 0, // dsub_4 11241 0, // dsub_5 11242 0, // dsub_6 11243 0, // dsub_7 11244 47, // gsub_0 -> GPRPair_with_gsub_1_in_GPRsp 11245 47, // gsub_1 -> GPRPair_with_gsub_1_in_GPRsp 11246 0, // qqsub_0 11247 0, // qqsub_1 11248 0, // qsub_0 11249 0, // qsub_1 11250 0, // qsub_2 11251 0, // qsub_3 11252 0, // ssub_0 11253 0, // ssub_1 11254 0, // ssub_2 11255 0, // ssub_3 11256 0, // ssub_4 11257 0, // ssub_5 11258 0, // ssub_6 11259 0, // ssub_7 11260 0, // ssub_8 11261 0, // ssub_9 11262 0, // ssub_10 11263 0, // ssub_11 11264 0, // ssub_12 11265 0, // ssub_13 11266 0, // dsub_7_then_ssub_0 11267 0, // dsub_7_then_ssub_1 11268 0, // ssub_0_ssub_1_ssub_4_ssub_5 11269 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 11270 0, // ssub_2_ssub_3_ssub_6_ssub_7 11271 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 11272 0, // ssub_2_ssub_3_ssub_4_ssub_5 11273 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 11274 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11275 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 11276 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 11277 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11278 0, // ssub_4_ssub_5_ssub_8_ssub_9 11279 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11280 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11281 0, // ssub_6_ssub_7_dsub_5 11282 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 11283 0, // ssub_6_ssub_7_dsub_5_dsub_7 11284 0, // ssub_6_ssub_7_ssub_8_ssub_9 11285 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11286 0, // ssub_8_ssub_9_ssub_12_ssub_13 11287 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11288 0, // dsub_5_dsub_7 11289 0, // dsub_5_ssub_12_ssub_13_dsub_7 11290 0, // dsub_5_ssub_12_ssub_13 11291 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 11292 }, 11293 { // DPairSpc 11294 48, // dsub_0 -> DPairSpc 11295 0, // dsub_1 11296 48, // dsub_2 -> DPairSpc 11297 0, // dsub_3 11298 0, // dsub_4 11299 0, // dsub_5 11300 0, // dsub_6 11301 0, // dsub_7 11302 0, // gsub_0 11303 0, // gsub_1 11304 0, // qqsub_0 11305 0, // qqsub_1 11306 0, // qsub_0 11307 0, // qsub_1 11308 0, // qsub_2 11309 0, // qsub_3 11310 49, // ssub_0 -> DPairSpc_with_ssub_0 11311 49, // ssub_1 -> DPairSpc_with_ssub_0 11312 0, // ssub_2 11313 0, // ssub_3 11314 50, // ssub_4 -> DPairSpc_with_ssub_4 11315 50, // ssub_5 -> DPairSpc_with_ssub_4 11316 0, // ssub_6 11317 0, // ssub_7 11318 0, // ssub_8 11319 0, // ssub_9 11320 0, // ssub_10 11321 0, // ssub_11 11322 0, // ssub_12 11323 0, // ssub_13 11324 0, // dsub_7_then_ssub_0 11325 0, // dsub_7_then_ssub_1 11326 0, // ssub_0_ssub_1_ssub_4_ssub_5 11327 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 11328 0, // ssub_2_ssub_3_ssub_6_ssub_7 11329 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 11330 0, // ssub_2_ssub_3_ssub_4_ssub_5 11331 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 11332 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11333 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 11334 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 11335 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11336 0, // ssub_4_ssub_5_ssub_8_ssub_9 11337 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11338 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11339 0, // ssub_6_ssub_7_dsub_5 11340 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 11341 0, // ssub_6_ssub_7_dsub_5_dsub_7 11342 0, // ssub_6_ssub_7_ssub_8_ssub_9 11343 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11344 0, // ssub_8_ssub_9_ssub_12_ssub_13 11345 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11346 0, // dsub_5_dsub_7 11347 0, // dsub_5_ssub_12_ssub_13_dsub_7 11348 0, // dsub_5_ssub_12_ssub_13 11349 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 11350 }, 11351 { // DPairSpc_with_ssub_0 11352 49, // dsub_0 -> DPairSpc_with_ssub_0 11353 0, // dsub_1 11354 49, // dsub_2 -> DPairSpc_with_ssub_0 11355 0, // dsub_3 11356 0, // dsub_4 11357 0, // dsub_5 11358 0, // dsub_6 11359 0, // dsub_7 11360 0, // gsub_0 11361 0, // gsub_1 11362 0, // qqsub_0 11363 0, // qqsub_1 11364 0, // qsub_0 11365 0, // qsub_1 11366 0, // qsub_2 11367 0, // qsub_3 11368 49, // ssub_0 -> DPairSpc_with_ssub_0 11369 49, // ssub_1 -> DPairSpc_with_ssub_0 11370 0, // ssub_2 11371 0, // ssub_3 11372 50, // ssub_4 -> DPairSpc_with_ssub_4 11373 50, // ssub_5 -> DPairSpc_with_ssub_4 11374 0, // ssub_6 11375 0, // ssub_7 11376 0, // ssub_8 11377 0, // ssub_9 11378 0, // ssub_10 11379 0, // ssub_11 11380 0, // ssub_12 11381 0, // ssub_13 11382 0, // dsub_7_then_ssub_0 11383 0, // dsub_7_then_ssub_1 11384 0, // ssub_0_ssub_1_ssub_4_ssub_5 11385 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 11386 0, // ssub_2_ssub_3_ssub_6_ssub_7 11387 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 11388 0, // ssub_2_ssub_3_ssub_4_ssub_5 11389 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 11390 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11391 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 11392 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 11393 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11394 0, // ssub_4_ssub_5_ssub_8_ssub_9 11395 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11396 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11397 0, // ssub_6_ssub_7_dsub_5 11398 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 11399 0, // ssub_6_ssub_7_dsub_5_dsub_7 11400 0, // ssub_6_ssub_7_ssub_8_ssub_9 11401 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11402 0, // ssub_8_ssub_9_ssub_12_ssub_13 11403 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11404 0, // dsub_5_dsub_7 11405 0, // dsub_5_ssub_12_ssub_13_dsub_7 11406 0, // dsub_5_ssub_12_ssub_13 11407 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 11408 }, 11409 { // DPairSpc_with_ssub_4 11410 50, // dsub_0 -> DPairSpc_with_ssub_4 11411 0, // dsub_1 11412 50, // dsub_2 -> DPairSpc_with_ssub_4 11413 0, // dsub_3 11414 0, // dsub_4 11415 0, // dsub_5 11416 0, // dsub_6 11417 0, // dsub_7 11418 0, // gsub_0 11419 0, // gsub_1 11420 0, // qqsub_0 11421 0, // qqsub_1 11422 0, // qsub_0 11423 0, // qsub_1 11424 0, // qsub_2 11425 0, // qsub_3 11426 50, // ssub_0 -> DPairSpc_with_ssub_4 11427 50, // ssub_1 -> DPairSpc_with_ssub_4 11428 0, // ssub_2 11429 0, // ssub_3 11430 50, // ssub_4 -> DPairSpc_with_ssub_4 11431 50, // ssub_5 -> DPairSpc_with_ssub_4 11432 0, // ssub_6 11433 0, // ssub_7 11434 0, // ssub_8 11435 0, // ssub_9 11436 0, // ssub_10 11437 0, // ssub_11 11438 0, // ssub_12 11439 0, // ssub_13 11440 0, // dsub_7_then_ssub_0 11441 0, // dsub_7_then_ssub_1 11442 0, // ssub_0_ssub_1_ssub_4_ssub_5 11443 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 11444 0, // ssub_2_ssub_3_ssub_6_ssub_7 11445 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 11446 0, // ssub_2_ssub_3_ssub_4_ssub_5 11447 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 11448 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11449 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 11450 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 11451 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11452 0, // ssub_4_ssub_5_ssub_8_ssub_9 11453 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11454 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11455 0, // ssub_6_ssub_7_dsub_5 11456 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 11457 0, // ssub_6_ssub_7_dsub_5_dsub_7 11458 0, // ssub_6_ssub_7_ssub_8_ssub_9 11459 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11460 0, // ssub_8_ssub_9_ssub_12_ssub_13 11461 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11462 0, // dsub_5_dsub_7 11463 0, // dsub_5_ssub_12_ssub_13_dsub_7 11464 0, // dsub_5_ssub_12_ssub_13 11465 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 11466 }, 11467 { // DPairSpc_with_dsub_0_in_DPR_8 11468 51, // dsub_0 -> DPairSpc_with_dsub_0_in_DPR_8 11469 0, // dsub_1 11470 51, // dsub_2 -> DPairSpc_with_dsub_0_in_DPR_8 11471 0, // dsub_3 11472 0, // dsub_4 11473 0, // dsub_5 11474 0, // dsub_6 11475 0, // dsub_7 11476 0, // gsub_0 11477 0, // gsub_1 11478 0, // qqsub_0 11479 0, // qqsub_1 11480 0, // qsub_0 11481 0, // qsub_1 11482 0, // qsub_2 11483 0, // qsub_3 11484 51, // ssub_0 -> DPairSpc_with_dsub_0_in_DPR_8 11485 51, // ssub_1 -> DPairSpc_with_dsub_0_in_DPR_8 11486 0, // ssub_2 11487 0, // ssub_3 11488 51, // ssub_4 -> DPairSpc_with_dsub_0_in_DPR_8 11489 51, // ssub_5 -> DPairSpc_with_dsub_0_in_DPR_8 11490 0, // ssub_6 11491 0, // ssub_7 11492 0, // ssub_8 11493 0, // ssub_9 11494 0, // ssub_10 11495 0, // ssub_11 11496 0, // ssub_12 11497 0, // ssub_13 11498 0, // dsub_7_then_ssub_0 11499 0, // dsub_7_then_ssub_1 11500 0, // ssub_0_ssub_1_ssub_4_ssub_5 11501 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 11502 0, // ssub_2_ssub_3_ssub_6_ssub_7 11503 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 11504 0, // ssub_2_ssub_3_ssub_4_ssub_5 11505 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 11506 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11507 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 11508 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 11509 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11510 0, // ssub_4_ssub_5_ssub_8_ssub_9 11511 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11512 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11513 0, // ssub_6_ssub_7_dsub_5 11514 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 11515 0, // ssub_6_ssub_7_dsub_5_dsub_7 11516 0, // ssub_6_ssub_7_ssub_8_ssub_9 11517 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11518 0, // ssub_8_ssub_9_ssub_12_ssub_13 11519 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11520 0, // dsub_5_dsub_7 11521 0, // dsub_5_ssub_12_ssub_13_dsub_7 11522 0, // dsub_5_ssub_12_ssub_13 11523 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 11524 }, 11525 { // DPairSpc_with_dsub_2_in_DPR_8 11526 52, // dsub_0 -> DPairSpc_with_dsub_2_in_DPR_8 11527 0, // dsub_1 11528 52, // dsub_2 -> DPairSpc_with_dsub_2_in_DPR_8 11529 0, // dsub_3 11530 0, // dsub_4 11531 0, // dsub_5 11532 0, // dsub_6 11533 0, // dsub_7 11534 0, // gsub_0 11535 0, // gsub_1 11536 0, // qqsub_0 11537 0, // qqsub_1 11538 0, // qsub_0 11539 0, // qsub_1 11540 0, // qsub_2 11541 0, // qsub_3 11542 52, // ssub_0 -> DPairSpc_with_dsub_2_in_DPR_8 11543 52, // ssub_1 -> DPairSpc_with_dsub_2_in_DPR_8 11544 0, // ssub_2 11545 0, // ssub_3 11546 52, // ssub_4 -> DPairSpc_with_dsub_2_in_DPR_8 11547 52, // ssub_5 -> DPairSpc_with_dsub_2_in_DPR_8 11548 0, // ssub_6 11549 0, // ssub_7 11550 0, // ssub_8 11551 0, // ssub_9 11552 0, // ssub_10 11553 0, // ssub_11 11554 0, // ssub_12 11555 0, // ssub_13 11556 0, // dsub_7_then_ssub_0 11557 0, // dsub_7_then_ssub_1 11558 0, // ssub_0_ssub_1_ssub_4_ssub_5 11559 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 11560 0, // ssub_2_ssub_3_ssub_6_ssub_7 11561 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 11562 0, // ssub_2_ssub_3_ssub_4_ssub_5 11563 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 11564 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11565 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 11566 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 11567 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11568 0, // ssub_4_ssub_5_ssub_8_ssub_9 11569 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11570 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11571 0, // ssub_6_ssub_7_dsub_5 11572 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 11573 0, // ssub_6_ssub_7_dsub_5_dsub_7 11574 0, // ssub_6_ssub_7_ssub_8_ssub_9 11575 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11576 0, // ssub_8_ssub_9_ssub_12_ssub_13 11577 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11578 0, // dsub_5_dsub_7 11579 0, // dsub_5_ssub_12_ssub_13_dsub_7 11580 0, // dsub_5_ssub_12_ssub_13 11581 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 11582 }, 11583 { // DPair 11584 53, // dsub_0 -> DPair 11585 53, // dsub_1 -> DPair 11586 0, // dsub_2 11587 0, // dsub_3 11588 0, // dsub_4 11589 0, // dsub_5 11590 0, // dsub_6 11591 0, // dsub_7 11592 0, // gsub_0 11593 0, // gsub_1 11594 0, // qqsub_0 11595 0, // qqsub_1 11596 0, // qsub_0 11597 0, // qsub_1 11598 0, // qsub_2 11599 0, // qsub_3 11600 54, // ssub_0 -> DPair_with_ssub_0 11601 54, // ssub_1 -> DPair_with_ssub_0 11602 56, // ssub_2 -> DPair_with_ssub_2 11603 56, // ssub_3 -> DPair_with_ssub_2 11604 0, // ssub_4 11605 0, // ssub_5 11606 0, // ssub_6 11607 0, // ssub_7 11608 0, // ssub_8 11609 0, // ssub_9 11610 0, // ssub_10 11611 0, // ssub_11 11612 0, // ssub_12 11613 0, // ssub_13 11614 0, // dsub_7_then_ssub_0 11615 0, // dsub_7_then_ssub_1 11616 0, // ssub_0_ssub_1_ssub_4_ssub_5 11617 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 11618 0, // ssub_2_ssub_3_ssub_6_ssub_7 11619 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 11620 0, // ssub_2_ssub_3_ssub_4_ssub_5 11621 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 11622 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11623 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 11624 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 11625 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11626 0, // ssub_4_ssub_5_ssub_8_ssub_9 11627 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11628 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11629 0, // ssub_6_ssub_7_dsub_5 11630 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 11631 0, // ssub_6_ssub_7_dsub_5_dsub_7 11632 0, // ssub_6_ssub_7_ssub_8_ssub_9 11633 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11634 0, // ssub_8_ssub_9_ssub_12_ssub_13 11635 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11636 0, // dsub_5_dsub_7 11637 0, // dsub_5_ssub_12_ssub_13_dsub_7 11638 0, // dsub_5_ssub_12_ssub_13 11639 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 11640 }, 11641 { // DPair_with_ssub_0 11642 54, // dsub_0 -> DPair_with_ssub_0 11643 54, // dsub_1 -> DPair_with_ssub_0 11644 0, // dsub_2 11645 0, // dsub_3 11646 0, // dsub_4 11647 0, // dsub_5 11648 0, // dsub_6 11649 0, // dsub_7 11650 0, // gsub_0 11651 0, // gsub_1 11652 0, // qqsub_0 11653 0, // qqsub_1 11654 0, // qsub_0 11655 0, // qsub_1 11656 0, // qsub_2 11657 0, // qsub_3 11658 54, // ssub_0 -> DPair_with_ssub_0 11659 54, // ssub_1 -> DPair_with_ssub_0 11660 56, // ssub_2 -> DPair_with_ssub_2 11661 56, // ssub_3 -> DPair_with_ssub_2 11662 0, // ssub_4 11663 0, // ssub_5 11664 0, // ssub_6 11665 0, // ssub_7 11666 0, // ssub_8 11667 0, // ssub_9 11668 0, // ssub_10 11669 0, // ssub_11 11670 0, // ssub_12 11671 0, // ssub_13 11672 0, // dsub_7_then_ssub_0 11673 0, // dsub_7_then_ssub_1 11674 0, // ssub_0_ssub_1_ssub_4_ssub_5 11675 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 11676 0, // ssub_2_ssub_3_ssub_6_ssub_7 11677 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 11678 0, // ssub_2_ssub_3_ssub_4_ssub_5 11679 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 11680 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11681 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 11682 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 11683 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11684 0, // ssub_4_ssub_5_ssub_8_ssub_9 11685 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11686 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11687 0, // ssub_6_ssub_7_dsub_5 11688 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 11689 0, // ssub_6_ssub_7_dsub_5_dsub_7 11690 0, // ssub_6_ssub_7_ssub_8_ssub_9 11691 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11692 0, // ssub_8_ssub_9_ssub_12_ssub_13 11693 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11694 0, // dsub_5_dsub_7 11695 0, // dsub_5_ssub_12_ssub_13_dsub_7 11696 0, // dsub_5_ssub_12_ssub_13 11697 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 11698 }, 11699 { // QPR 11700 55, // dsub_0 -> QPR 11701 55, // dsub_1 -> QPR 11702 0, // dsub_2 11703 0, // dsub_3 11704 0, // dsub_4 11705 0, // dsub_5 11706 0, // dsub_6 11707 0, // dsub_7 11708 0, // gsub_0 11709 0, // gsub_1 11710 0, // qqsub_0 11711 0, // qqsub_1 11712 0, // qsub_0 11713 0, // qsub_1 11714 0, // qsub_2 11715 0, // qsub_3 11716 58, // ssub_0 -> MQPR 11717 58, // ssub_1 -> MQPR 11718 58, // ssub_2 -> MQPR 11719 58, // ssub_3 -> MQPR 11720 0, // ssub_4 11721 0, // ssub_5 11722 0, // ssub_6 11723 0, // ssub_7 11724 0, // ssub_8 11725 0, // ssub_9 11726 0, // ssub_10 11727 0, // ssub_11 11728 0, // ssub_12 11729 0, // ssub_13 11730 0, // dsub_7_then_ssub_0 11731 0, // dsub_7_then_ssub_1 11732 0, // ssub_0_ssub_1_ssub_4_ssub_5 11733 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 11734 0, // ssub_2_ssub_3_ssub_6_ssub_7 11735 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 11736 0, // ssub_2_ssub_3_ssub_4_ssub_5 11737 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 11738 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11739 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 11740 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 11741 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11742 0, // ssub_4_ssub_5_ssub_8_ssub_9 11743 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11744 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11745 0, // ssub_6_ssub_7_dsub_5 11746 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 11747 0, // ssub_6_ssub_7_dsub_5_dsub_7 11748 0, // ssub_6_ssub_7_ssub_8_ssub_9 11749 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11750 0, // ssub_8_ssub_9_ssub_12_ssub_13 11751 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11752 0, // dsub_5_dsub_7 11753 0, // dsub_5_ssub_12_ssub_13_dsub_7 11754 0, // dsub_5_ssub_12_ssub_13 11755 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 11756 }, 11757 { // DPair_with_ssub_2 11758 56, // dsub_0 -> DPair_with_ssub_2 11759 56, // dsub_1 -> DPair_with_ssub_2 11760 0, // dsub_2 11761 0, // dsub_3 11762 0, // dsub_4 11763 0, // dsub_5 11764 0, // dsub_6 11765 0, // dsub_7 11766 0, // gsub_0 11767 0, // gsub_1 11768 0, // qqsub_0 11769 0, // qqsub_1 11770 0, // qsub_0 11771 0, // qsub_1 11772 0, // qsub_2 11773 0, // qsub_3 11774 56, // ssub_0 -> DPair_with_ssub_2 11775 56, // ssub_1 -> DPair_with_ssub_2 11776 56, // ssub_2 -> DPair_with_ssub_2 11777 56, // ssub_3 -> DPair_with_ssub_2 11778 0, // ssub_4 11779 0, // ssub_5 11780 0, // ssub_6 11781 0, // ssub_7 11782 0, // ssub_8 11783 0, // ssub_9 11784 0, // ssub_10 11785 0, // ssub_11 11786 0, // ssub_12 11787 0, // ssub_13 11788 0, // dsub_7_then_ssub_0 11789 0, // dsub_7_then_ssub_1 11790 0, // ssub_0_ssub_1_ssub_4_ssub_5 11791 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 11792 0, // ssub_2_ssub_3_ssub_6_ssub_7 11793 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 11794 0, // ssub_2_ssub_3_ssub_4_ssub_5 11795 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 11796 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11797 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 11798 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 11799 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11800 0, // ssub_4_ssub_5_ssub_8_ssub_9 11801 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11802 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11803 0, // ssub_6_ssub_7_dsub_5 11804 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 11805 0, // ssub_6_ssub_7_dsub_5_dsub_7 11806 0, // ssub_6_ssub_7_ssub_8_ssub_9 11807 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11808 0, // ssub_8_ssub_9_ssub_12_ssub_13 11809 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11810 0, // dsub_5_dsub_7 11811 0, // dsub_5_ssub_12_ssub_13_dsub_7 11812 0, // dsub_5_ssub_12_ssub_13 11813 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 11814 }, 11815 { // DPair_with_dsub_0_in_DPR_8 11816 57, // dsub_0 -> DPair_with_dsub_0_in_DPR_8 11817 57, // dsub_1 -> DPair_with_dsub_0_in_DPR_8 11818 0, // dsub_2 11819 0, // dsub_3 11820 0, // dsub_4 11821 0, // dsub_5 11822 0, // dsub_6 11823 0, // dsub_7 11824 0, // gsub_0 11825 0, // gsub_1 11826 0, // qqsub_0 11827 0, // qqsub_1 11828 0, // qsub_0 11829 0, // qsub_1 11830 0, // qsub_2 11831 0, // qsub_3 11832 57, // ssub_0 -> DPair_with_dsub_0_in_DPR_8 11833 57, // ssub_1 -> DPair_with_dsub_0_in_DPR_8 11834 57, // ssub_2 -> DPair_with_dsub_0_in_DPR_8 11835 57, // ssub_3 -> DPair_with_dsub_0_in_DPR_8 11836 0, // ssub_4 11837 0, // ssub_5 11838 0, // ssub_6 11839 0, // ssub_7 11840 0, // ssub_8 11841 0, // ssub_9 11842 0, // ssub_10 11843 0, // ssub_11 11844 0, // ssub_12 11845 0, // ssub_13 11846 0, // dsub_7_then_ssub_0 11847 0, // dsub_7_then_ssub_1 11848 0, // ssub_0_ssub_1_ssub_4_ssub_5 11849 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 11850 0, // ssub_2_ssub_3_ssub_6_ssub_7 11851 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 11852 0, // ssub_2_ssub_3_ssub_4_ssub_5 11853 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 11854 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11855 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 11856 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 11857 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11858 0, // ssub_4_ssub_5_ssub_8_ssub_9 11859 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11860 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11861 0, // ssub_6_ssub_7_dsub_5 11862 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 11863 0, // ssub_6_ssub_7_dsub_5_dsub_7 11864 0, // ssub_6_ssub_7_ssub_8_ssub_9 11865 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11866 0, // ssub_8_ssub_9_ssub_12_ssub_13 11867 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11868 0, // dsub_5_dsub_7 11869 0, // dsub_5_ssub_12_ssub_13_dsub_7 11870 0, // dsub_5_ssub_12_ssub_13 11871 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 11872 }, 11873 { // MQPR 11874 58, // dsub_0 -> MQPR 11875 58, // dsub_1 -> MQPR 11876 0, // dsub_2 11877 0, // dsub_3 11878 0, // dsub_4 11879 0, // dsub_5 11880 0, // dsub_6 11881 0, // dsub_7 11882 0, // gsub_0 11883 0, // gsub_1 11884 0, // qqsub_0 11885 0, // qqsub_1 11886 0, // qsub_0 11887 0, // qsub_1 11888 0, // qsub_2 11889 0, // qsub_3 11890 58, // ssub_0 -> MQPR 11891 58, // ssub_1 -> MQPR 11892 58, // ssub_2 -> MQPR 11893 58, // ssub_3 -> MQPR 11894 0, // ssub_4 11895 0, // ssub_5 11896 0, // ssub_6 11897 0, // ssub_7 11898 0, // ssub_8 11899 0, // ssub_9 11900 0, // ssub_10 11901 0, // ssub_11 11902 0, // ssub_12 11903 0, // ssub_13 11904 0, // dsub_7_then_ssub_0 11905 0, // dsub_7_then_ssub_1 11906 0, // ssub_0_ssub_1_ssub_4_ssub_5 11907 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 11908 0, // ssub_2_ssub_3_ssub_6_ssub_7 11909 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 11910 0, // ssub_2_ssub_3_ssub_4_ssub_5 11911 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 11912 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11913 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 11914 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 11915 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11916 0, // ssub_4_ssub_5_ssub_8_ssub_9 11917 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11918 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11919 0, // ssub_6_ssub_7_dsub_5 11920 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 11921 0, // ssub_6_ssub_7_dsub_5_dsub_7 11922 0, // ssub_6_ssub_7_ssub_8_ssub_9 11923 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11924 0, // ssub_8_ssub_9_ssub_12_ssub_13 11925 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11926 0, // dsub_5_dsub_7 11927 0, // dsub_5_ssub_12_ssub_13_dsub_7 11928 0, // dsub_5_ssub_12_ssub_13 11929 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 11930 }, 11931 { // QPR_VFP2 11932 59, // dsub_0 -> QPR_VFP2 11933 59, // dsub_1 -> QPR_VFP2 11934 0, // dsub_2 11935 0, // dsub_3 11936 0, // dsub_4 11937 0, // dsub_5 11938 0, // dsub_6 11939 0, // dsub_7 11940 0, // gsub_0 11941 0, // gsub_1 11942 0, // qqsub_0 11943 0, // qqsub_1 11944 0, // qsub_0 11945 0, // qsub_1 11946 0, // qsub_2 11947 0, // qsub_3 11948 59, // ssub_0 -> QPR_VFP2 11949 59, // ssub_1 -> QPR_VFP2 11950 59, // ssub_2 -> QPR_VFP2 11951 59, // ssub_3 -> QPR_VFP2 11952 0, // ssub_4 11953 0, // ssub_5 11954 0, // ssub_6 11955 0, // ssub_7 11956 0, // ssub_8 11957 0, // ssub_9 11958 0, // ssub_10 11959 0, // ssub_11 11960 0, // ssub_12 11961 0, // ssub_13 11962 0, // dsub_7_then_ssub_0 11963 0, // dsub_7_then_ssub_1 11964 0, // ssub_0_ssub_1_ssub_4_ssub_5 11965 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 11966 0, // ssub_2_ssub_3_ssub_6_ssub_7 11967 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 11968 0, // ssub_2_ssub_3_ssub_4_ssub_5 11969 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 11970 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11971 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 11972 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 11973 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11974 0, // ssub_4_ssub_5_ssub_8_ssub_9 11975 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 11976 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 11977 0, // ssub_6_ssub_7_dsub_5 11978 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 11979 0, // ssub_6_ssub_7_dsub_5_dsub_7 11980 0, // ssub_6_ssub_7_ssub_8_ssub_9 11981 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11982 0, // ssub_8_ssub_9_ssub_12_ssub_13 11983 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 11984 0, // dsub_5_dsub_7 11985 0, // dsub_5_ssub_12_ssub_13_dsub_7 11986 0, // dsub_5_ssub_12_ssub_13 11987 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 11988 }, 11989 { // DPair_with_dsub_1_in_DPR_8 11990 60, // dsub_0 -> DPair_with_dsub_1_in_DPR_8 11991 60, // dsub_1 -> DPair_with_dsub_1_in_DPR_8 11992 0, // dsub_2 11993 0, // dsub_3 11994 0, // dsub_4 11995 0, // dsub_5 11996 0, // dsub_6 11997 0, // dsub_7 11998 0, // gsub_0 11999 0, // gsub_1 12000 0, // qqsub_0 12001 0, // qqsub_1 12002 0, // qsub_0 12003 0, // qsub_1 12004 0, // qsub_2 12005 0, // qsub_3 12006 60, // ssub_0 -> DPair_with_dsub_1_in_DPR_8 12007 60, // ssub_1 -> DPair_with_dsub_1_in_DPR_8 12008 60, // ssub_2 -> DPair_with_dsub_1_in_DPR_8 12009 60, // ssub_3 -> DPair_with_dsub_1_in_DPR_8 12010 0, // ssub_4 12011 0, // ssub_5 12012 0, // ssub_6 12013 0, // ssub_7 12014 0, // ssub_8 12015 0, // ssub_9 12016 0, // ssub_10 12017 0, // ssub_11 12018 0, // ssub_12 12019 0, // ssub_13 12020 0, // dsub_7_then_ssub_0 12021 0, // dsub_7_then_ssub_1 12022 0, // ssub_0_ssub_1_ssub_4_ssub_5 12023 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 12024 0, // ssub_2_ssub_3_ssub_6_ssub_7 12025 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 12026 0, // ssub_2_ssub_3_ssub_4_ssub_5 12027 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 12028 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12029 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 12030 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 12031 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12032 0, // ssub_4_ssub_5_ssub_8_ssub_9 12033 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12034 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12035 0, // ssub_6_ssub_7_dsub_5 12036 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 12037 0, // ssub_6_ssub_7_dsub_5_dsub_7 12038 0, // ssub_6_ssub_7_ssub_8_ssub_9 12039 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12040 0, // ssub_8_ssub_9_ssub_12_ssub_13 12041 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12042 0, // dsub_5_dsub_7 12043 0, // dsub_5_ssub_12_ssub_13_dsub_7 12044 0, // dsub_5_ssub_12_ssub_13 12045 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 12046 }, 12047 { // QPR_8 12048 61, // dsub_0 -> QPR_8 12049 61, // dsub_1 -> QPR_8 12050 0, // dsub_2 12051 0, // dsub_3 12052 0, // dsub_4 12053 0, // dsub_5 12054 0, // dsub_6 12055 0, // dsub_7 12056 0, // gsub_0 12057 0, // gsub_1 12058 0, // qqsub_0 12059 0, // qqsub_1 12060 0, // qsub_0 12061 0, // qsub_1 12062 0, // qsub_2 12063 0, // qsub_3 12064 61, // ssub_0 -> QPR_8 12065 61, // ssub_1 -> QPR_8 12066 61, // ssub_2 -> QPR_8 12067 61, // ssub_3 -> QPR_8 12068 0, // ssub_4 12069 0, // ssub_5 12070 0, // ssub_6 12071 0, // ssub_7 12072 0, // ssub_8 12073 0, // ssub_9 12074 0, // ssub_10 12075 0, // ssub_11 12076 0, // ssub_12 12077 0, // ssub_13 12078 0, // dsub_7_then_ssub_0 12079 0, // dsub_7_then_ssub_1 12080 0, // ssub_0_ssub_1_ssub_4_ssub_5 12081 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 12082 0, // ssub_2_ssub_3_ssub_6_ssub_7 12083 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 12084 0, // ssub_2_ssub_3_ssub_4_ssub_5 12085 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 12086 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12087 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 12088 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 12089 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12090 0, // ssub_4_ssub_5_ssub_8_ssub_9 12091 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12092 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12093 0, // ssub_6_ssub_7_dsub_5 12094 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 12095 0, // ssub_6_ssub_7_dsub_5_dsub_7 12096 0, // ssub_6_ssub_7_ssub_8_ssub_9 12097 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12098 0, // ssub_8_ssub_9_ssub_12_ssub_13 12099 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12100 0, // dsub_5_dsub_7 12101 0, // dsub_5_ssub_12_ssub_13_dsub_7 12102 0, // dsub_5_ssub_12_ssub_13 12103 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 12104 }, 12105 { // DTriple 12106 62, // dsub_0 -> DTriple 12107 62, // dsub_1 -> DTriple 12108 62, // dsub_2 -> DTriple 12109 0, // dsub_3 12110 0, // dsub_4 12111 0, // dsub_5 12112 0, // dsub_6 12113 0, // dsub_7 12114 0, // gsub_0 12115 0, // gsub_1 12116 0, // qqsub_0 12117 0, // qqsub_1 12118 62, // qsub_0 -> DTriple 12119 0, // qsub_1 12120 0, // qsub_2 12121 0, // qsub_3 12122 65, // ssub_0 -> DTriple_with_ssub_0 12123 65, // ssub_1 -> DTriple_with_ssub_0 12124 67, // ssub_2 -> DTriple_with_ssub_2 12125 67, // ssub_3 -> DTriple_with_ssub_2 12126 70, // ssub_4 -> DTriple_with_ssub_4 12127 70, // ssub_5 -> DTriple_with_ssub_4 12128 0, // ssub_6 12129 0, // ssub_7 12130 0, // ssub_8 12131 0, // ssub_9 12132 0, // ssub_10 12133 0, // ssub_11 12134 0, // ssub_12 12135 0, // ssub_13 12136 0, // dsub_7_then_ssub_0 12137 0, // dsub_7_then_ssub_1 12138 62, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple 12139 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 12140 0, // ssub_2_ssub_3_ssub_6_ssub_7 12141 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 12142 62, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple 12143 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 12144 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12145 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 12146 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 12147 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12148 0, // ssub_4_ssub_5_ssub_8_ssub_9 12149 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12150 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12151 0, // ssub_6_ssub_7_dsub_5 12152 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 12153 0, // ssub_6_ssub_7_dsub_5_dsub_7 12154 0, // ssub_6_ssub_7_ssub_8_ssub_9 12155 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12156 0, // ssub_8_ssub_9_ssub_12_ssub_13 12157 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12158 0, // dsub_5_dsub_7 12159 0, // dsub_5_ssub_12_ssub_13_dsub_7 12160 0, // dsub_5_ssub_12_ssub_13 12161 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 12162 }, 12163 { // DTripleSpc 12164 63, // dsub_0 -> DTripleSpc 12165 0, // dsub_1 12166 63, // dsub_2 -> DTripleSpc 12167 0, // dsub_3 12168 63, // dsub_4 -> DTripleSpc 12169 0, // dsub_5 12170 0, // dsub_6 12171 0, // dsub_7 12172 0, // gsub_0 12173 0, // gsub_1 12174 0, // qqsub_0 12175 0, // qqsub_1 12176 0, // qsub_0 12177 0, // qsub_1 12178 0, // qsub_2 12179 0, // qsub_3 12180 64, // ssub_0 -> DTripleSpc_with_ssub_0 12181 64, // ssub_1 -> DTripleSpc_with_ssub_0 12182 0, // ssub_2 12183 0, // ssub_3 12184 69, // ssub_4 -> DTripleSpc_with_ssub_4 12185 69, // ssub_5 -> DTripleSpc_with_ssub_4 12186 0, // ssub_6 12187 0, // ssub_7 12188 71, // ssub_8 -> DTripleSpc_with_ssub_8 12189 71, // ssub_9 -> DTripleSpc_with_ssub_8 12190 0, // ssub_10 12191 0, // ssub_11 12192 0, // ssub_12 12193 0, // ssub_13 12194 0, // dsub_7_then_ssub_0 12195 0, // dsub_7_then_ssub_1 12196 63, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc 12197 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 12198 0, // ssub_2_ssub_3_ssub_6_ssub_7 12199 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 12200 0, // ssub_2_ssub_3_ssub_4_ssub_5 12201 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 12202 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12203 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 12204 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 12205 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12206 63, // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc 12207 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12208 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12209 0, // ssub_6_ssub_7_dsub_5 12210 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 12211 0, // ssub_6_ssub_7_dsub_5_dsub_7 12212 0, // ssub_6_ssub_7_ssub_8_ssub_9 12213 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12214 0, // ssub_8_ssub_9_ssub_12_ssub_13 12215 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12216 0, // dsub_5_dsub_7 12217 0, // dsub_5_ssub_12_ssub_13_dsub_7 12218 0, // dsub_5_ssub_12_ssub_13 12219 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 12220 }, 12221 { // DTripleSpc_with_ssub_0 12222 64, // dsub_0 -> DTripleSpc_with_ssub_0 12223 0, // dsub_1 12224 64, // dsub_2 -> DTripleSpc_with_ssub_0 12225 0, // dsub_3 12226 64, // dsub_4 -> DTripleSpc_with_ssub_0 12227 0, // dsub_5 12228 0, // dsub_6 12229 0, // dsub_7 12230 0, // gsub_0 12231 0, // gsub_1 12232 0, // qqsub_0 12233 0, // qqsub_1 12234 0, // qsub_0 12235 0, // qsub_1 12236 0, // qsub_2 12237 0, // qsub_3 12238 64, // ssub_0 -> DTripleSpc_with_ssub_0 12239 64, // ssub_1 -> DTripleSpc_with_ssub_0 12240 0, // ssub_2 12241 0, // ssub_3 12242 69, // ssub_4 -> DTripleSpc_with_ssub_4 12243 69, // ssub_5 -> DTripleSpc_with_ssub_4 12244 0, // ssub_6 12245 0, // ssub_7 12246 71, // ssub_8 -> DTripleSpc_with_ssub_8 12247 71, // ssub_9 -> DTripleSpc_with_ssub_8 12248 0, // ssub_10 12249 0, // ssub_11 12250 0, // ssub_12 12251 0, // ssub_13 12252 0, // dsub_7_then_ssub_0 12253 0, // dsub_7_then_ssub_1 12254 64, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_ssub_0 12255 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 12256 0, // ssub_2_ssub_3_ssub_6_ssub_7 12257 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 12258 0, // ssub_2_ssub_3_ssub_4_ssub_5 12259 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 12260 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12261 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 12262 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 12263 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12264 64, // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_ssub_0 12265 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12266 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12267 0, // ssub_6_ssub_7_dsub_5 12268 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 12269 0, // ssub_6_ssub_7_dsub_5_dsub_7 12270 0, // ssub_6_ssub_7_ssub_8_ssub_9 12271 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12272 0, // ssub_8_ssub_9_ssub_12_ssub_13 12273 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12274 0, // dsub_5_dsub_7 12275 0, // dsub_5_ssub_12_ssub_13_dsub_7 12276 0, // dsub_5_ssub_12_ssub_13 12277 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 12278 }, 12279 { // DTriple_with_ssub_0 12280 65, // dsub_0 -> DTriple_with_ssub_0 12281 65, // dsub_1 -> DTriple_with_ssub_0 12282 65, // dsub_2 -> DTriple_with_ssub_0 12283 0, // dsub_3 12284 0, // dsub_4 12285 0, // dsub_5 12286 0, // dsub_6 12287 0, // dsub_7 12288 0, // gsub_0 12289 0, // gsub_1 12290 0, // qqsub_0 12291 0, // qqsub_1 12292 65, // qsub_0 -> DTriple_with_ssub_0 12293 0, // qsub_1 12294 0, // qsub_2 12295 0, // qsub_3 12296 65, // ssub_0 -> DTriple_with_ssub_0 12297 65, // ssub_1 -> DTriple_with_ssub_0 12298 67, // ssub_2 -> DTriple_with_ssub_2 12299 67, // ssub_3 -> DTriple_with_ssub_2 12300 70, // ssub_4 -> DTriple_with_ssub_4 12301 70, // ssub_5 -> DTriple_with_ssub_4 12302 0, // ssub_6 12303 0, // ssub_7 12304 0, // ssub_8 12305 0, // ssub_9 12306 0, // ssub_10 12307 0, // ssub_11 12308 0, // ssub_12 12309 0, // ssub_13 12310 0, // dsub_7_then_ssub_0 12311 0, // dsub_7_then_ssub_1 12312 65, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_0 12313 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 12314 0, // ssub_2_ssub_3_ssub_6_ssub_7 12315 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 12316 65, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_0 12317 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 12318 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12319 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 12320 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 12321 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12322 0, // ssub_4_ssub_5_ssub_8_ssub_9 12323 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12324 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12325 0, // ssub_6_ssub_7_dsub_5 12326 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 12327 0, // ssub_6_ssub_7_dsub_5_dsub_7 12328 0, // ssub_6_ssub_7_ssub_8_ssub_9 12329 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12330 0, // ssub_8_ssub_9_ssub_12_ssub_13 12331 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12332 0, // dsub_5_dsub_7 12333 0, // dsub_5_ssub_12_ssub_13_dsub_7 12334 0, // dsub_5_ssub_12_ssub_13 12335 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 12336 }, 12337 { // DTriple_with_qsub_0_in_QPR 12338 66, // dsub_0 -> DTriple_with_qsub_0_in_QPR 12339 66, // dsub_1 -> DTriple_with_qsub_0_in_QPR 12340 66, // dsub_2 -> DTriple_with_qsub_0_in_QPR 12341 0, // dsub_3 12342 0, // dsub_4 12343 0, // dsub_5 12344 0, // dsub_6 12345 0, // dsub_7 12346 0, // gsub_0 12347 0, // gsub_1 12348 0, // qqsub_0 12349 0, // qqsub_1 12350 66, // qsub_0 -> DTriple_with_qsub_0_in_QPR 12351 0, // qsub_1 12352 0, // qsub_2 12353 0, // qsub_3 12354 74, // ssub_0 -> DTriple_with_qsub_0_in_MQPR 12355 74, // ssub_1 -> DTriple_with_qsub_0_in_MQPR 12356 74, // ssub_2 -> DTriple_with_qsub_0_in_MQPR 12357 74, // ssub_3 -> DTriple_with_qsub_0_in_MQPR 12358 78, // ssub_4 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR 12359 78, // ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR 12360 0, // ssub_6 12361 0, // ssub_7 12362 0, // ssub_8 12363 0, // ssub_9 12364 0, // ssub_10 12365 0, // ssub_11 12366 0, // ssub_12 12367 0, // ssub_13 12368 0, // dsub_7_then_ssub_0 12369 0, // dsub_7_then_ssub_1 12370 66, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR 12371 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 12372 0, // ssub_2_ssub_3_ssub_6_ssub_7 12373 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 12374 66, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR 12375 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 12376 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12377 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 12378 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 12379 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12380 0, // ssub_4_ssub_5_ssub_8_ssub_9 12381 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12382 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12383 0, // ssub_6_ssub_7_dsub_5 12384 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 12385 0, // ssub_6_ssub_7_dsub_5_dsub_7 12386 0, // ssub_6_ssub_7_ssub_8_ssub_9 12387 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12388 0, // ssub_8_ssub_9_ssub_12_ssub_13 12389 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12390 0, // dsub_5_dsub_7 12391 0, // dsub_5_ssub_12_ssub_13_dsub_7 12392 0, // dsub_5_ssub_12_ssub_13 12393 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 12394 }, 12395 { // DTriple_with_ssub_2 12396 67, // dsub_0 -> DTriple_with_ssub_2 12397 67, // dsub_1 -> DTriple_with_ssub_2 12398 67, // dsub_2 -> DTriple_with_ssub_2 12399 0, // dsub_3 12400 0, // dsub_4 12401 0, // dsub_5 12402 0, // dsub_6 12403 0, // dsub_7 12404 0, // gsub_0 12405 0, // gsub_1 12406 0, // qqsub_0 12407 0, // qqsub_1 12408 67, // qsub_0 -> DTriple_with_ssub_2 12409 0, // qsub_1 12410 0, // qsub_2 12411 0, // qsub_3 12412 67, // ssub_0 -> DTriple_with_ssub_2 12413 67, // ssub_1 -> DTriple_with_ssub_2 12414 67, // ssub_2 -> DTriple_with_ssub_2 12415 67, // ssub_3 -> DTriple_with_ssub_2 12416 70, // ssub_4 -> DTriple_with_ssub_4 12417 70, // ssub_5 -> DTriple_with_ssub_4 12418 0, // ssub_6 12419 0, // ssub_7 12420 0, // ssub_8 12421 0, // ssub_9 12422 0, // ssub_10 12423 0, // ssub_11 12424 0, // ssub_12 12425 0, // ssub_13 12426 0, // dsub_7_then_ssub_0 12427 0, // dsub_7_then_ssub_1 12428 67, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2 12429 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 12430 0, // ssub_2_ssub_3_ssub_6_ssub_7 12431 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 12432 67, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2 12433 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 12434 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12435 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 12436 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 12437 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12438 0, // ssub_4_ssub_5_ssub_8_ssub_9 12439 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12440 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12441 0, // ssub_6_ssub_7_dsub_5 12442 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 12443 0, // ssub_6_ssub_7_dsub_5_dsub_7 12444 0, // ssub_6_ssub_7_ssub_8_ssub_9 12445 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12446 0, // ssub_8_ssub_9_ssub_12_ssub_13 12447 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12448 0, // dsub_5_dsub_7 12449 0, // dsub_5_ssub_12_ssub_13_dsub_7 12450 0, // dsub_5_ssub_12_ssub_13 12451 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 12452 }, 12453 { // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 12454 68, // dsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 12455 68, // dsub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 12456 68, // dsub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 12457 0, // dsub_3 12458 0, // dsub_4 12459 0, // dsub_5 12460 0, // dsub_6 12461 0, // dsub_7 12462 0, // gsub_0 12463 0, // gsub_1 12464 0, // qqsub_0 12465 0, // qqsub_1 12466 68, // qsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 12467 0, // qsub_1 12468 0, // qsub_2 12469 0, // qsub_3 12470 75, // ssub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 12471 75, // ssub_1 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 12472 77, // ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 12473 77, // ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 12474 77, // ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 12475 77, // ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 12476 0, // ssub_6 12477 0, // ssub_7 12478 0, // ssub_8 12479 0, // ssub_9 12480 0, // ssub_10 12481 0, // ssub_11 12482 0, // ssub_12 12483 0, // ssub_13 12484 0, // dsub_7_then_ssub_0 12485 0, // dsub_7_then_ssub_1 12486 68, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 12487 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 12488 0, // ssub_2_ssub_3_ssub_6_ssub_7 12489 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 12490 68, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 12491 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 12492 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12493 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 12494 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 12495 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12496 0, // ssub_4_ssub_5_ssub_8_ssub_9 12497 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12498 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12499 0, // ssub_6_ssub_7_dsub_5 12500 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 12501 0, // ssub_6_ssub_7_dsub_5_dsub_7 12502 0, // ssub_6_ssub_7_ssub_8_ssub_9 12503 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12504 0, // ssub_8_ssub_9_ssub_12_ssub_13 12505 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12506 0, // dsub_5_dsub_7 12507 0, // dsub_5_ssub_12_ssub_13_dsub_7 12508 0, // dsub_5_ssub_12_ssub_13 12509 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 12510 }, 12511 { // DTripleSpc_with_ssub_4 12512 69, // dsub_0 -> DTripleSpc_with_ssub_4 12513 0, // dsub_1 12514 69, // dsub_2 -> DTripleSpc_with_ssub_4 12515 0, // dsub_3 12516 69, // dsub_4 -> DTripleSpc_with_ssub_4 12517 0, // dsub_5 12518 0, // dsub_6 12519 0, // dsub_7 12520 0, // gsub_0 12521 0, // gsub_1 12522 0, // qqsub_0 12523 0, // qqsub_1 12524 0, // qsub_0 12525 0, // qsub_1 12526 0, // qsub_2 12527 0, // qsub_3 12528 69, // ssub_0 -> DTripleSpc_with_ssub_4 12529 69, // ssub_1 -> DTripleSpc_with_ssub_4 12530 0, // ssub_2 12531 0, // ssub_3 12532 69, // ssub_4 -> DTripleSpc_with_ssub_4 12533 69, // ssub_5 -> DTripleSpc_with_ssub_4 12534 0, // ssub_6 12535 0, // ssub_7 12536 71, // ssub_8 -> DTripleSpc_with_ssub_8 12537 71, // ssub_9 -> DTripleSpc_with_ssub_8 12538 0, // ssub_10 12539 0, // ssub_11 12540 0, // ssub_12 12541 0, // ssub_13 12542 0, // dsub_7_then_ssub_0 12543 0, // dsub_7_then_ssub_1 12544 69, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_ssub_4 12545 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 12546 0, // ssub_2_ssub_3_ssub_6_ssub_7 12547 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 12548 0, // ssub_2_ssub_3_ssub_4_ssub_5 12549 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 12550 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12551 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 12552 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 12553 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12554 69, // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_ssub_4 12555 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12556 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12557 0, // ssub_6_ssub_7_dsub_5 12558 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 12559 0, // ssub_6_ssub_7_dsub_5_dsub_7 12560 0, // ssub_6_ssub_7_ssub_8_ssub_9 12561 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12562 0, // ssub_8_ssub_9_ssub_12_ssub_13 12563 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12564 0, // dsub_5_dsub_7 12565 0, // dsub_5_ssub_12_ssub_13_dsub_7 12566 0, // dsub_5_ssub_12_ssub_13 12567 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 12568 }, 12569 { // DTriple_with_ssub_4 12570 70, // dsub_0 -> DTriple_with_ssub_4 12571 70, // dsub_1 -> DTriple_with_ssub_4 12572 70, // dsub_2 -> DTriple_with_ssub_4 12573 0, // dsub_3 12574 0, // dsub_4 12575 0, // dsub_5 12576 0, // dsub_6 12577 0, // dsub_7 12578 0, // gsub_0 12579 0, // gsub_1 12580 0, // qqsub_0 12581 0, // qqsub_1 12582 70, // qsub_0 -> DTriple_with_ssub_4 12583 0, // qsub_1 12584 0, // qsub_2 12585 0, // qsub_3 12586 70, // ssub_0 -> DTriple_with_ssub_4 12587 70, // ssub_1 -> DTriple_with_ssub_4 12588 70, // ssub_2 -> DTriple_with_ssub_4 12589 70, // ssub_3 -> DTriple_with_ssub_4 12590 70, // ssub_4 -> DTriple_with_ssub_4 12591 70, // ssub_5 -> DTriple_with_ssub_4 12592 0, // ssub_6 12593 0, // ssub_7 12594 0, // ssub_8 12595 0, // ssub_9 12596 0, // ssub_10 12597 0, // ssub_11 12598 0, // ssub_12 12599 0, // ssub_13 12600 0, // dsub_7_then_ssub_0 12601 0, // dsub_7_then_ssub_1 12602 70, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_4 12603 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 12604 0, // ssub_2_ssub_3_ssub_6_ssub_7 12605 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 12606 70, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_4 12607 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 12608 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12609 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 12610 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 12611 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12612 0, // ssub_4_ssub_5_ssub_8_ssub_9 12613 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12614 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12615 0, // ssub_6_ssub_7_dsub_5 12616 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 12617 0, // ssub_6_ssub_7_dsub_5_dsub_7 12618 0, // ssub_6_ssub_7_ssub_8_ssub_9 12619 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12620 0, // ssub_8_ssub_9_ssub_12_ssub_13 12621 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12622 0, // dsub_5_dsub_7 12623 0, // dsub_5_ssub_12_ssub_13_dsub_7 12624 0, // dsub_5_ssub_12_ssub_13 12625 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 12626 }, 12627 { // DTripleSpc_with_ssub_8 12628 71, // dsub_0 -> DTripleSpc_with_ssub_8 12629 0, // dsub_1 12630 71, // dsub_2 -> DTripleSpc_with_ssub_8 12631 0, // dsub_3 12632 71, // dsub_4 -> DTripleSpc_with_ssub_8 12633 0, // dsub_5 12634 0, // dsub_6 12635 0, // dsub_7 12636 0, // gsub_0 12637 0, // gsub_1 12638 0, // qqsub_0 12639 0, // qqsub_1 12640 0, // qsub_0 12641 0, // qsub_1 12642 0, // qsub_2 12643 0, // qsub_3 12644 71, // ssub_0 -> DTripleSpc_with_ssub_8 12645 71, // ssub_1 -> DTripleSpc_with_ssub_8 12646 0, // ssub_2 12647 0, // ssub_3 12648 71, // ssub_4 -> DTripleSpc_with_ssub_8 12649 71, // ssub_5 -> DTripleSpc_with_ssub_8 12650 0, // ssub_6 12651 0, // ssub_7 12652 71, // ssub_8 -> DTripleSpc_with_ssub_8 12653 71, // ssub_9 -> DTripleSpc_with_ssub_8 12654 0, // ssub_10 12655 0, // ssub_11 12656 0, // ssub_12 12657 0, // ssub_13 12658 0, // dsub_7_then_ssub_0 12659 0, // dsub_7_then_ssub_1 12660 71, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_ssub_8 12661 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 12662 0, // ssub_2_ssub_3_ssub_6_ssub_7 12663 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 12664 0, // ssub_2_ssub_3_ssub_4_ssub_5 12665 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 12666 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12667 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 12668 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 12669 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12670 71, // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_ssub_8 12671 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12672 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12673 0, // ssub_6_ssub_7_dsub_5 12674 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 12675 0, // ssub_6_ssub_7_dsub_5_dsub_7 12676 0, // ssub_6_ssub_7_ssub_8_ssub_9 12677 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12678 0, // ssub_8_ssub_9_ssub_12_ssub_13 12679 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12680 0, // dsub_5_dsub_7 12681 0, // dsub_5_ssub_12_ssub_13_dsub_7 12682 0, // dsub_5_ssub_12_ssub_13 12683 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 12684 }, 12685 { // DTripleSpc_with_dsub_0_in_DPR_8 12686 72, // dsub_0 -> DTripleSpc_with_dsub_0_in_DPR_8 12687 0, // dsub_1 12688 72, // dsub_2 -> DTripleSpc_with_dsub_0_in_DPR_8 12689 0, // dsub_3 12690 72, // dsub_4 -> DTripleSpc_with_dsub_0_in_DPR_8 12691 0, // dsub_5 12692 0, // dsub_6 12693 0, // dsub_7 12694 0, // gsub_0 12695 0, // gsub_1 12696 0, // qqsub_0 12697 0, // qqsub_1 12698 0, // qsub_0 12699 0, // qsub_1 12700 0, // qsub_2 12701 0, // qsub_3 12702 72, // ssub_0 -> DTripleSpc_with_dsub_0_in_DPR_8 12703 72, // ssub_1 -> DTripleSpc_with_dsub_0_in_DPR_8 12704 0, // ssub_2 12705 0, // ssub_3 12706 72, // ssub_4 -> DTripleSpc_with_dsub_0_in_DPR_8 12707 72, // ssub_5 -> DTripleSpc_with_dsub_0_in_DPR_8 12708 0, // ssub_6 12709 0, // ssub_7 12710 72, // ssub_8 -> DTripleSpc_with_dsub_0_in_DPR_8 12711 72, // ssub_9 -> DTripleSpc_with_dsub_0_in_DPR_8 12712 0, // ssub_10 12713 0, // ssub_11 12714 0, // ssub_12 12715 0, // ssub_13 12716 0, // dsub_7_then_ssub_0 12717 0, // dsub_7_then_ssub_1 12718 72, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_dsub_0_in_DPR_8 12719 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 12720 0, // ssub_2_ssub_3_ssub_6_ssub_7 12721 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 12722 0, // ssub_2_ssub_3_ssub_4_ssub_5 12723 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 12724 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12725 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 12726 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 12727 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12728 72, // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_dsub_0_in_DPR_8 12729 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12730 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12731 0, // ssub_6_ssub_7_dsub_5 12732 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 12733 0, // ssub_6_ssub_7_dsub_5_dsub_7 12734 0, // ssub_6_ssub_7_ssub_8_ssub_9 12735 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12736 0, // ssub_8_ssub_9_ssub_12_ssub_13 12737 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12738 0, // dsub_5_dsub_7 12739 0, // dsub_5_ssub_12_ssub_13_dsub_7 12740 0, // dsub_5_ssub_12_ssub_13 12741 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 12742 }, 12743 { // DTriple_with_dsub_0_in_DPR_8 12744 73, // dsub_0 -> DTriple_with_dsub_0_in_DPR_8 12745 73, // dsub_1 -> DTriple_with_dsub_0_in_DPR_8 12746 73, // dsub_2 -> DTriple_with_dsub_0_in_DPR_8 12747 0, // dsub_3 12748 0, // dsub_4 12749 0, // dsub_5 12750 0, // dsub_6 12751 0, // dsub_7 12752 0, // gsub_0 12753 0, // gsub_1 12754 0, // qqsub_0 12755 0, // qqsub_1 12756 73, // qsub_0 -> DTriple_with_dsub_0_in_DPR_8 12757 0, // qsub_1 12758 0, // qsub_2 12759 0, // qsub_3 12760 73, // ssub_0 -> DTriple_with_dsub_0_in_DPR_8 12761 73, // ssub_1 -> DTriple_with_dsub_0_in_DPR_8 12762 73, // ssub_2 -> DTriple_with_dsub_0_in_DPR_8 12763 73, // ssub_3 -> DTriple_with_dsub_0_in_DPR_8 12764 73, // ssub_4 -> DTriple_with_dsub_0_in_DPR_8 12765 73, // ssub_5 -> DTriple_with_dsub_0_in_DPR_8 12766 0, // ssub_6 12767 0, // ssub_7 12768 0, // ssub_8 12769 0, // ssub_9 12770 0, // ssub_10 12771 0, // ssub_11 12772 0, // ssub_12 12773 0, // ssub_13 12774 0, // dsub_7_then_ssub_0 12775 0, // dsub_7_then_ssub_1 12776 73, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_0_in_DPR_8 12777 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 12778 0, // ssub_2_ssub_3_ssub_6_ssub_7 12779 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 12780 73, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_0_in_DPR_8 12781 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 12782 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12783 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 12784 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 12785 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12786 0, // ssub_4_ssub_5_ssub_8_ssub_9 12787 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12788 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12789 0, // ssub_6_ssub_7_dsub_5 12790 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 12791 0, // ssub_6_ssub_7_dsub_5_dsub_7 12792 0, // ssub_6_ssub_7_ssub_8_ssub_9 12793 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12794 0, // ssub_8_ssub_9_ssub_12_ssub_13 12795 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12796 0, // dsub_5_dsub_7 12797 0, // dsub_5_ssub_12_ssub_13_dsub_7 12798 0, // dsub_5_ssub_12_ssub_13 12799 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 12800 }, 12801 { // DTriple_with_qsub_0_in_MQPR 12802 74, // dsub_0 -> DTriple_with_qsub_0_in_MQPR 12803 74, // dsub_1 -> DTriple_with_qsub_0_in_MQPR 12804 74, // dsub_2 -> DTriple_with_qsub_0_in_MQPR 12805 0, // dsub_3 12806 0, // dsub_4 12807 0, // dsub_5 12808 0, // dsub_6 12809 0, // dsub_7 12810 0, // gsub_0 12811 0, // gsub_1 12812 0, // qqsub_0 12813 0, // qqsub_1 12814 74, // qsub_0 -> DTriple_with_qsub_0_in_MQPR 12815 0, // qsub_1 12816 0, // qsub_2 12817 0, // qsub_3 12818 74, // ssub_0 -> DTriple_with_qsub_0_in_MQPR 12819 74, // ssub_1 -> DTriple_with_qsub_0_in_MQPR 12820 74, // ssub_2 -> DTriple_with_qsub_0_in_MQPR 12821 74, // ssub_3 -> DTriple_with_qsub_0_in_MQPR 12822 78, // ssub_4 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR 12823 78, // ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR 12824 0, // ssub_6 12825 0, // ssub_7 12826 0, // ssub_8 12827 0, // ssub_9 12828 0, // ssub_10 12829 0, // ssub_11 12830 0, // ssub_12 12831 0, // ssub_13 12832 0, // dsub_7_then_ssub_0 12833 0, // dsub_7_then_ssub_1 12834 74, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_MQPR 12835 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 12836 0, // ssub_2_ssub_3_ssub_6_ssub_7 12837 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 12838 74, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_MQPR 12839 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 12840 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12841 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 12842 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 12843 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12844 0, // ssub_4_ssub_5_ssub_8_ssub_9 12845 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12846 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12847 0, // ssub_6_ssub_7_dsub_5 12848 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 12849 0, // ssub_6_ssub_7_dsub_5_dsub_7 12850 0, // ssub_6_ssub_7_ssub_8_ssub_9 12851 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12852 0, // ssub_8_ssub_9_ssub_12_ssub_13 12853 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12854 0, // dsub_5_dsub_7 12855 0, // dsub_5_ssub_12_ssub_13_dsub_7 12856 0, // dsub_5_ssub_12_ssub_13 12857 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 12858 }, 12859 { // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 12860 75, // dsub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 12861 75, // dsub_1 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 12862 75, // dsub_2 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 12863 0, // dsub_3 12864 0, // dsub_4 12865 0, // dsub_5 12866 0, // dsub_6 12867 0, // dsub_7 12868 0, // gsub_0 12869 0, // gsub_1 12870 0, // qqsub_0 12871 0, // qqsub_1 12872 75, // qsub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 12873 0, // qsub_1 12874 0, // qsub_2 12875 0, // qsub_3 12876 75, // ssub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 12877 75, // ssub_1 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 12878 77, // ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 12879 77, // ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 12880 77, // ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 12881 77, // ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 12882 0, // ssub_6 12883 0, // ssub_7 12884 0, // ssub_8 12885 0, // ssub_9 12886 0, // ssub_10 12887 0, // ssub_11 12888 0, // ssub_12 12889 0, // ssub_13 12890 0, // dsub_7_then_ssub_0 12891 0, // dsub_7_then_ssub_1 12892 75, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 12893 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 12894 0, // ssub_2_ssub_3_ssub_6_ssub_7 12895 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 12896 75, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 12897 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 12898 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12899 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 12900 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 12901 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12902 0, // ssub_4_ssub_5_ssub_8_ssub_9 12903 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12904 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12905 0, // ssub_6_ssub_7_dsub_5 12906 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 12907 0, // ssub_6_ssub_7_dsub_5_dsub_7 12908 0, // ssub_6_ssub_7_ssub_8_ssub_9 12909 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12910 0, // ssub_8_ssub_9_ssub_12_ssub_13 12911 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12912 0, // dsub_5_dsub_7 12913 0, // dsub_5_ssub_12_ssub_13_dsub_7 12914 0, // dsub_5_ssub_12_ssub_13 12915 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 12916 }, 12917 { // DTriple_with_dsub_1_in_DPR_8 12918 76, // dsub_0 -> DTriple_with_dsub_1_in_DPR_8 12919 76, // dsub_1 -> DTriple_with_dsub_1_in_DPR_8 12920 76, // dsub_2 -> DTriple_with_dsub_1_in_DPR_8 12921 0, // dsub_3 12922 0, // dsub_4 12923 0, // dsub_5 12924 0, // dsub_6 12925 0, // dsub_7 12926 0, // gsub_0 12927 0, // gsub_1 12928 0, // qqsub_0 12929 0, // qqsub_1 12930 76, // qsub_0 -> DTriple_with_dsub_1_in_DPR_8 12931 0, // qsub_1 12932 0, // qsub_2 12933 0, // qsub_3 12934 76, // ssub_0 -> DTriple_with_dsub_1_in_DPR_8 12935 76, // ssub_1 -> DTriple_with_dsub_1_in_DPR_8 12936 76, // ssub_2 -> DTriple_with_dsub_1_in_DPR_8 12937 76, // ssub_3 -> DTriple_with_dsub_1_in_DPR_8 12938 76, // ssub_4 -> DTriple_with_dsub_1_in_DPR_8 12939 76, // ssub_5 -> DTriple_with_dsub_1_in_DPR_8 12940 0, // ssub_6 12941 0, // ssub_7 12942 0, // ssub_8 12943 0, // ssub_9 12944 0, // ssub_10 12945 0, // ssub_11 12946 0, // ssub_12 12947 0, // ssub_13 12948 0, // dsub_7_then_ssub_0 12949 0, // dsub_7_then_ssub_1 12950 76, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_1_in_DPR_8 12951 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 12952 0, // ssub_2_ssub_3_ssub_6_ssub_7 12953 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 12954 76, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_1_in_DPR_8 12955 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 12956 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12957 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 12958 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 12959 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12960 0, // ssub_4_ssub_5_ssub_8_ssub_9 12961 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 12962 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 12963 0, // ssub_6_ssub_7_dsub_5 12964 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 12965 0, // ssub_6_ssub_7_dsub_5_dsub_7 12966 0, // ssub_6_ssub_7_ssub_8_ssub_9 12967 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12968 0, // ssub_8_ssub_9_ssub_12_ssub_13 12969 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 12970 0, // dsub_5_dsub_7 12971 0, // dsub_5_ssub_12_ssub_13_dsub_7 12972 0, // dsub_5_ssub_12_ssub_13 12973 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 12974 }, 12975 { // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 12976 77, // dsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 12977 77, // dsub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 12978 77, // dsub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 12979 0, // dsub_3 12980 0, // dsub_4 12981 0, // dsub_5 12982 0, // dsub_6 12983 0, // dsub_7 12984 0, // gsub_0 12985 0, // gsub_1 12986 0, // qqsub_0 12987 0, // qqsub_1 12988 77, // qsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 12989 0, // qsub_1 12990 0, // qsub_2 12991 0, // qsub_3 12992 77, // ssub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 12993 77, // ssub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 12994 77, // ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 12995 77, // ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 12996 77, // ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 12997 77, // ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 12998 0, // ssub_6 12999 0, // ssub_7 13000 0, // ssub_8 13001 0, // ssub_9 13002 0, // ssub_10 13003 0, // ssub_11 13004 0, // ssub_12 13005 0, // ssub_13 13006 0, // dsub_7_then_ssub_0 13007 0, // dsub_7_then_ssub_1 13008 77, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 13009 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 13010 0, // ssub_2_ssub_3_ssub_6_ssub_7 13011 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 13012 77, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 13013 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 13014 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13015 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 13016 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 13017 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13018 0, // ssub_4_ssub_5_ssub_8_ssub_9 13019 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13020 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13021 0, // ssub_6_ssub_7_dsub_5 13022 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 13023 0, // ssub_6_ssub_7_dsub_5_dsub_7 13024 0, // ssub_6_ssub_7_ssub_8_ssub_9 13025 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13026 0, // ssub_8_ssub_9_ssub_12_ssub_13 13027 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13028 0, // dsub_5_dsub_7 13029 0, // dsub_5_ssub_12_ssub_13_dsub_7 13030 0, // dsub_5_ssub_12_ssub_13 13031 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 13032 }, 13033 { // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR 13034 78, // dsub_0 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR 13035 78, // dsub_1 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR 13036 78, // dsub_2 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR 13037 0, // dsub_3 13038 0, // dsub_4 13039 0, // dsub_5 13040 0, // dsub_6 13041 0, // dsub_7 13042 0, // gsub_0 13043 0, // gsub_1 13044 0, // qqsub_0 13045 0, // qqsub_1 13046 78, // qsub_0 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR 13047 0, // qsub_1 13048 0, // qsub_2 13049 0, // qsub_3 13050 78, // ssub_0 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR 13051 78, // ssub_1 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR 13052 78, // ssub_2 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR 13053 78, // ssub_3 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR 13054 78, // ssub_4 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR 13055 78, // ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR 13056 0, // ssub_6 13057 0, // ssub_7 13058 0, // ssub_8 13059 0, // ssub_9 13060 0, // ssub_10 13061 0, // ssub_11 13062 0, // ssub_12 13063 0, // ssub_13 13064 0, // dsub_7_then_ssub_0 13065 0, // dsub_7_then_ssub_1 13066 78, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR 13067 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 13068 0, // ssub_2_ssub_3_ssub_6_ssub_7 13069 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 13070 78, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR 13071 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 13072 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13073 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 13074 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 13075 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13076 0, // ssub_4_ssub_5_ssub_8_ssub_9 13077 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13078 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13079 0, // ssub_6_ssub_7_dsub_5 13080 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 13081 0, // ssub_6_ssub_7_dsub_5_dsub_7 13082 0, // ssub_6_ssub_7_ssub_8_ssub_9 13083 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13084 0, // ssub_8_ssub_9_ssub_12_ssub_13 13085 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13086 0, // dsub_5_dsub_7 13087 0, // dsub_5_ssub_12_ssub_13_dsub_7 13088 0, // dsub_5_ssub_12_ssub_13 13089 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 13090 }, 13091 { // DTripleSpc_with_dsub_2_in_DPR_8 13092 79, // dsub_0 -> DTripleSpc_with_dsub_2_in_DPR_8 13093 0, // dsub_1 13094 79, // dsub_2 -> DTripleSpc_with_dsub_2_in_DPR_8 13095 0, // dsub_3 13096 79, // dsub_4 -> DTripleSpc_with_dsub_2_in_DPR_8 13097 0, // dsub_5 13098 0, // dsub_6 13099 0, // dsub_7 13100 0, // gsub_0 13101 0, // gsub_1 13102 0, // qqsub_0 13103 0, // qqsub_1 13104 0, // qsub_0 13105 0, // qsub_1 13106 0, // qsub_2 13107 0, // qsub_3 13108 79, // ssub_0 -> DTripleSpc_with_dsub_2_in_DPR_8 13109 79, // ssub_1 -> DTripleSpc_with_dsub_2_in_DPR_8 13110 0, // ssub_2 13111 0, // ssub_3 13112 79, // ssub_4 -> DTripleSpc_with_dsub_2_in_DPR_8 13113 79, // ssub_5 -> DTripleSpc_with_dsub_2_in_DPR_8 13114 0, // ssub_6 13115 0, // ssub_7 13116 79, // ssub_8 -> DTripleSpc_with_dsub_2_in_DPR_8 13117 79, // ssub_9 -> DTripleSpc_with_dsub_2_in_DPR_8 13118 0, // ssub_10 13119 0, // ssub_11 13120 0, // ssub_12 13121 0, // ssub_13 13122 0, // dsub_7_then_ssub_0 13123 0, // dsub_7_then_ssub_1 13124 79, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_dsub_2_in_DPR_8 13125 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 13126 0, // ssub_2_ssub_3_ssub_6_ssub_7 13127 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 13128 0, // ssub_2_ssub_3_ssub_4_ssub_5 13129 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 13130 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13131 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 13132 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 13133 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13134 79, // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_dsub_2_in_DPR_8 13135 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13136 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13137 0, // ssub_6_ssub_7_dsub_5 13138 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 13139 0, // ssub_6_ssub_7_dsub_5_dsub_7 13140 0, // ssub_6_ssub_7_ssub_8_ssub_9 13141 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13142 0, // ssub_8_ssub_9_ssub_12_ssub_13 13143 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13144 0, // dsub_5_dsub_7 13145 0, // dsub_5_ssub_12_ssub_13_dsub_7 13146 0, // dsub_5_ssub_12_ssub_13 13147 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 13148 }, 13149 { // DTriple_with_dsub_2_in_DPR_8 13150 80, // dsub_0 -> DTriple_with_dsub_2_in_DPR_8 13151 80, // dsub_1 -> DTriple_with_dsub_2_in_DPR_8 13152 80, // dsub_2 -> DTriple_with_dsub_2_in_DPR_8 13153 0, // dsub_3 13154 0, // dsub_4 13155 0, // dsub_5 13156 0, // dsub_6 13157 0, // dsub_7 13158 0, // gsub_0 13159 0, // gsub_1 13160 0, // qqsub_0 13161 0, // qqsub_1 13162 80, // qsub_0 -> DTriple_with_dsub_2_in_DPR_8 13163 0, // qsub_1 13164 0, // qsub_2 13165 0, // qsub_3 13166 80, // ssub_0 -> DTriple_with_dsub_2_in_DPR_8 13167 80, // ssub_1 -> DTriple_with_dsub_2_in_DPR_8 13168 80, // ssub_2 -> DTriple_with_dsub_2_in_DPR_8 13169 80, // ssub_3 -> DTriple_with_dsub_2_in_DPR_8 13170 80, // ssub_4 -> DTriple_with_dsub_2_in_DPR_8 13171 80, // ssub_5 -> DTriple_with_dsub_2_in_DPR_8 13172 0, // ssub_6 13173 0, // ssub_7 13174 0, // ssub_8 13175 0, // ssub_9 13176 0, // ssub_10 13177 0, // ssub_11 13178 0, // ssub_12 13179 0, // ssub_13 13180 0, // dsub_7_then_ssub_0 13181 0, // dsub_7_then_ssub_1 13182 80, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_2_in_DPR_8 13183 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 13184 0, // ssub_2_ssub_3_ssub_6_ssub_7 13185 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 13186 80, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_2_in_DPR_8 13187 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 13188 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13189 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 13190 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 13191 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13192 0, // ssub_4_ssub_5_ssub_8_ssub_9 13193 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13194 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13195 0, // ssub_6_ssub_7_dsub_5 13196 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 13197 0, // ssub_6_ssub_7_dsub_5_dsub_7 13198 0, // ssub_6_ssub_7_ssub_8_ssub_9 13199 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13200 0, // ssub_8_ssub_9_ssub_12_ssub_13 13201 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13202 0, // dsub_5_dsub_7 13203 0, // dsub_5_ssub_12_ssub_13_dsub_7 13204 0, // dsub_5_ssub_12_ssub_13 13205 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 13206 }, 13207 { // DTripleSpc_with_dsub_4_in_DPR_8 13208 81, // dsub_0 -> DTripleSpc_with_dsub_4_in_DPR_8 13209 0, // dsub_1 13210 81, // dsub_2 -> DTripleSpc_with_dsub_4_in_DPR_8 13211 0, // dsub_3 13212 81, // dsub_4 -> DTripleSpc_with_dsub_4_in_DPR_8 13213 0, // dsub_5 13214 0, // dsub_6 13215 0, // dsub_7 13216 0, // gsub_0 13217 0, // gsub_1 13218 0, // qqsub_0 13219 0, // qqsub_1 13220 0, // qsub_0 13221 0, // qsub_1 13222 0, // qsub_2 13223 0, // qsub_3 13224 81, // ssub_0 -> DTripleSpc_with_dsub_4_in_DPR_8 13225 81, // ssub_1 -> DTripleSpc_with_dsub_4_in_DPR_8 13226 0, // ssub_2 13227 0, // ssub_3 13228 81, // ssub_4 -> DTripleSpc_with_dsub_4_in_DPR_8 13229 81, // ssub_5 -> DTripleSpc_with_dsub_4_in_DPR_8 13230 0, // ssub_6 13231 0, // ssub_7 13232 81, // ssub_8 -> DTripleSpc_with_dsub_4_in_DPR_8 13233 81, // ssub_9 -> DTripleSpc_with_dsub_4_in_DPR_8 13234 0, // ssub_10 13235 0, // ssub_11 13236 0, // ssub_12 13237 0, // ssub_13 13238 0, // dsub_7_then_ssub_0 13239 0, // dsub_7_then_ssub_1 13240 81, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_dsub_4_in_DPR_8 13241 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 13242 0, // ssub_2_ssub_3_ssub_6_ssub_7 13243 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 13244 0, // ssub_2_ssub_3_ssub_4_ssub_5 13245 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 13246 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13247 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 13248 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 13249 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13250 81, // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_dsub_4_in_DPR_8 13251 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13252 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13253 0, // ssub_6_ssub_7_dsub_5 13254 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 13255 0, // ssub_6_ssub_7_dsub_5_dsub_7 13256 0, // ssub_6_ssub_7_ssub_8_ssub_9 13257 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13258 0, // ssub_8_ssub_9_ssub_12_ssub_13 13259 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13260 0, // dsub_5_dsub_7 13261 0, // dsub_5_ssub_12_ssub_13_dsub_7 13262 0, // dsub_5_ssub_12_ssub_13 13263 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 13264 }, 13265 { // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 13266 82, // dsub_0 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 13267 82, // dsub_1 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 13268 82, // dsub_2 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 13269 0, // dsub_3 13270 0, // dsub_4 13271 0, // dsub_5 13272 0, // dsub_6 13273 0, // dsub_7 13274 0, // gsub_0 13275 0, // gsub_1 13276 0, // qqsub_0 13277 0, // qqsub_1 13278 82, // qsub_0 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 13279 0, // qsub_1 13280 0, // qsub_2 13281 0, // qsub_3 13282 82, // ssub_0 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 13283 82, // ssub_1 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 13284 82, // ssub_2 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 13285 82, // ssub_3 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 13286 82, // ssub_4 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 13287 82, // ssub_5 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 13288 0, // ssub_6 13289 0, // ssub_7 13290 0, // ssub_8 13291 0, // ssub_9 13292 0, // ssub_10 13293 0, // ssub_11 13294 0, // ssub_12 13295 0, // ssub_13 13296 0, // dsub_7_then_ssub_0 13297 0, // dsub_7_then_ssub_1 13298 82, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 13299 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 13300 0, // ssub_2_ssub_3_ssub_6_ssub_7 13301 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 13302 82, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 13303 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 13304 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13305 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 13306 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 13307 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13308 0, // ssub_4_ssub_5_ssub_8_ssub_9 13309 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13310 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13311 0, // ssub_6_ssub_7_dsub_5 13312 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 13313 0, // ssub_6_ssub_7_dsub_5_dsub_7 13314 0, // ssub_6_ssub_7_ssub_8_ssub_9 13315 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13316 0, // ssub_8_ssub_9_ssub_12_ssub_13 13317 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13318 0, // dsub_5_dsub_7 13319 0, // dsub_5_ssub_12_ssub_13_dsub_7 13320 0, // dsub_5_ssub_12_ssub_13 13321 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 13322 }, 13323 { // DTriple_with_qsub_0_in_QPR_8 13324 83, // dsub_0 -> DTriple_with_qsub_0_in_QPR_8 13325 83, // dsub_1 -> DTriple_with_qsub_0_in_QPR_8 13326 83, // dsub_2 -> DTriple_with_qsub_0_in_QPR_8 13327 0, // dsub_3 13328 0, // dsub_4 13329 0, // dsub_5 13330 0, // dsub_6 13331 0, // dsub_7 13332 0, // gsub_0 13333 0, // gsub_1 13334 0, // qqsub_0 13335 0, // qqsub_1 13336 83, // qsub_0 -> DTriple_with_qsub_0_in_QPR_8 13337 0, // qsub_1 13338 0, // qsub_2 13339 0, // qsub_3 13340 83, // ssub_0 -> DTriple_with_qsub_0_in_QPR_8 13341 83, // ssub_1 -> DTriple_with_qsub_0_in_QPR_8 13342 83, // ssub_2 -> DTriple_with_qsub_0_in_QPR_8 13343 83, // ssub_3 -> DTriple_with_qsub_0_in_QPR_8 13344 83, // ssub_4 -> DTriple_with_qsub_0_in_QPR_8 13345 83, // ssub_5 -> DTriple_with_qsub_0_in_QPR_8 13346 0, // ssub_6 13347 0, // ssub_7 13348 0, // ssub_8 13349 0, // ssub_9 13350 0, // ssub_10 13351 0, // ssub_11 13352 0, // ssub_12 13353 0, // ssub_13 13354 0, // dsub_7_then_ssub_0 13355 0, // dsub_7_then_ssub_1 13356 83, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR_8 13357 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 13358 0, // ssub_2_ssub_3_ssub_6_ssub_7 13359 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 13360 83, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR_8 13361 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 13362 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13363 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 13364 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 13365 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13366 0, // ssub_4_ssub_5_ssub_8_ssub_9 13367 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13368 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13369 0, // ssub_6_ssub_7_dsub_5 13370 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 13371 0, // ssub_6_ssub_7_dsub_5_dsub_7 13372 0, // ssub_6_ssub_7_ssub_8_ssub_9 13373 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13374 0, // ssub_8_ssub_9_ssub_12_ssub_13 13375 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13376 0, // dsub_5_dsub_7 13377 0, // dsub_5_ssub_12_ssub_13_dsub_7 13378 0, // dsub_5_ssub_12_ssub_13 13379 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 13380 }, 13381 { // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR 13382 84, // dsub_0 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR 13383 84, // dsub_1 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR 13384 84, // dsub_2 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR 13385 0, // dsub_3 13386 0, // dsub_4 13387 0, // dsub_5 13388 0, // dsub_6 13389 0, // dsub_7 13390 0, // gsub_0 13391 0, // gsub_1 13392 0, // qqsub_0 13393 0, // qqsub_1 13394 84, // qsub_0 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR 13395 0, // qsub_1 13396 0, // qsub_2 13397 0, // qsub_3 13398 84, // ssub_0 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR 13399 84, // ssub_1 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR 13400 84, // ssub_2 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR 13401 84, // ssub_3 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR 13402 84, // ssub_4 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR 13403 84, // ssub_5 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR 13404 0, // ssub_6 13405 0, // ssub_7 13406 0, // ssub_8 13407 0, // ssub_9 13408 0, // ssub_10 13409 0, // ssub_11 13410 0, // ssub_12 13411 0, // ssub_13 13412 0, // dsub_7_then_ssub_0 13413 0, // dsub_7_then_ssub_1 13414 84, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR 13415 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 13416 0, // ssub_2_ssub_3_ssub_6_ssub_7 13417 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 13418 84, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR 13419 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 13420 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13421 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 13422 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 13423 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13424 0, // ssub_4_ssub_5_ssub_8_ssub_9 13425 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13426 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13427 0, // ssub_6_ssub_7_dsub_5 13428 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 13429 0, // ssub_6_ssub_7_dsub_5_dsub_7 13430 0, // ssub_6_ssub_7_ssub_8_ssub_9 13431 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13432 0, // ssub_8_ssub_9_ssub_12_ssub_13 13433 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13434 0, // dsub_5_dsub_7 13435 0, // dsub_5_ssub_12_ssub_13_dsub_7 13436 0, // dsub_5_ssub_12_ssub_13 13437 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 13438 }, 13439 { // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 13440 85, // dsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 13441 85, // dsub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 13442 85, // dsub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 13443 0, // dsub_3 13444 0, // dsub_4 13445 0, // dsub_5 13446 0, // dsub_6 13447 0, // dsub_7 13448 0, // gsub_0 13449 0, // gsub_1 13450 0, // qqsub_0 13451 0, // qqsub_1 13452 85, // qsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 13453 0, // qsub_1 13454 0, // qsub_2 13455 0, // qsub_3 13456 85, // ssub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 13457 85, // ssub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 13458 85, // ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 13459 85, // ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 13460 85, // ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 13461 85, // ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 13462 0, // ssub_6 13463 0, // ssub_7 13464 0, // ssub_8 13465 0, // ssub_9 13466 0, // ssub_10 13467 0, // ssub_11 13468 0, // ssub_12 13469 0, // ssub_13 13470 0, // dsub_7_then_ssub_0 13471 0, // dsub_7_then_ssub_1 13472 85, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 13473 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 13474 0, // ssub_2_ssub_3_ssub_6_ssub_7 13475 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 13476 85, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 13477 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 13478 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13479 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 13480 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 13481 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13482 0, // ssub_4_ssub_5_ssub_8_ssub_9 13483 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13484 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13485 0, // ssub_6_ssub_7_dsub_5 13486 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 13487 0, // ssub_6_ssub_7_dsub_5_dsub_7 13488 0, // ssub_6_ssub_7_ssub_8_ssub_9 13489 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13490 0, // ssub_8_ssub_9_ssub_12_ssub_13 13491 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13492 0, // dsub_5_dsub_7 13493 0, // dsub_5_ssub_12_ssub_13_dsub_7 13494 0, // dsub_5_ssub_12_ssub_13 13495 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 13496 }, 13497 { // DQuadSpc 13498 86, // dsub_0 -> DQuadSpc 13499 0, // dsub_1 13500 86, // dsub_2 -> DQuadSpc 13501 0, // dsub_3 13502 86, // dsub_4 -> DQuadSpc 13503 0, // dsub_5 13504 0, // dsub_6 13505 0, // dsub_7 13506 0, // gsub_0 13507 0, // gsub_1 13508 0, // qqsub_0 13509 0, // qqsub_1 13510 0, // qsub_0 13511 0, // qsub_1 13512 0, // qsub_2 13513 0, // qsub_3 13514 87, // ssub_0 -> DQuadSpc_with_ssub_0 13515 87, // ssub_1 -> DQuadSpc_with_ssub_0 13516 0, // ssub_2 13517 0, // ssub_3 13518 88, // ssub_4 -> DQuadSpc_with_ssub_4 13519 88, // ssub_5 -> DQuadSpc_with_ssub_4 13520 0, // ssub_6 13521 0, // ssub_7 13522 89, // ssub_8 -> DQuadSpc_with_ssub_8 13523 89, // ssub_9 -> DQuadSpc_with_ssub_8 13524 0, // ssub_10 13525 0, // ssub_11 13526 0, // ssub_12 13527 0, // ssub_13 13528 0, // dsub_7_then_ssub_0 13529 0, // dsub_7_then_ssub_1 13530 86, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc 13531 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 13532 0, // ssub_2_ssub_3_ssub_6_ssub_7 13533 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 13534 0, // ssub_2_ssub_3_ssub_4_ssub_5 13535 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 13536 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13537 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 13538 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 13539 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13540 86, // ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc 13541 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13542 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13543 0, // ssub_6_ssub_7_dsub_5 13544 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 13545 0, // ssub_6_ssub_7_dsub_5_dsub_7 13546 0, // ssub_6_ssub_7_ssub_8_ssub_9 13547 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13548 0, // ssub_8_ssub_9_ssub_12_ssub_13 13549 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13550 0, // dsub_5_dsub_7 13551 0, // dsub_5_ssub_12_ssub_13_dsub_7 13552 0, // dsub_5_ssub_12_ssub_13 13553 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 13554 }, 13555 { // DQuadSpc_with_ssub_0 13556 87, // dsub_0 -> DQuadSpc_with_ssub_0 13557 0, // dsub_1 13558 87, // dsub_2 -> DQuadSpc_with_ssub_0 13559 0, // dsub_3 13560 87, // dsub_4 -> DQuadSpc_with_ssub_0 13561 0, // dsub_5 13562 0, // dsub_6 13563 0, // dsub_7 13564 0, // gsub_0 13565 0, // gsub_1 13566 0, // qqsub_0 13567 0, // qqsub_1 13568 0, // qsub_0 13569 0, // qsub_1 13570 0, // qsub_2 13571 0, // qsub_3 13572 87, // ssub_0 -> DQuadSpc_with_ssub_0 13573 87, // ssub_1 -> DQuadSpc_with_ssub_0 13574 0, // ssub_2 13575 0, // ssub_3 13576 88, // ssub_4 -> DQuadSpc_with_ssub_4 13577 88, // ssub_5 -> DQuadSpc_with_ssub_4 13578 0, // ssub_6 13579 0, // ssub_7 13580 89, // ssub_8 -> DQuadSpc_with_ssub_8 13581 89, // ssub_9 -> DQuadSpc_with_ssub_8 13582 0, // ssub_10 13583 0, // ssub_11 13584 0, // ssub_12 13585 0, // ssub_13 13586 0, // dsub_7_then_ssub_0 13587 0, // dsub_7_then_ssub_1 13588 87, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_ssub_0 13589 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 13590 0, // ssub_2_ssub_3_ssub_6_ssub_7 13591 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 13592 0, // ssub_2_ssub_3_ssub_4_ssub_5 13593 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 13594 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13595 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 13596 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 13597 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13598 87, // ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_ssub_0 13599 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13600 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13601 0, // ssub_6_ssub_7_dsub_5 13602 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 13603 0, // ssub_6_ssub_7_dsub_5_dsub_7 13604 0, // ssub_6_ssub_7_ssub_8_ssub_9 13605 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13606 0, // ssub_8_ssub_9_ssub_12_ssub_13 13607 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13608 0, // dsub_5_dsub_7 13609 0, // dsub_5_ssub_12_ssub_13_dsub_7 13610 0, // dsub_5_ssub_12_ssub_13 13611 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 13612 }, 13613 { // DQuadSpc_with_ssub_4 13614 88, // dsub_0 -> DQuadSpc_with_ssub_4 13615 0, // dsub_1 13616 88, // dsub_2 -> DQuadSpc_with_ssub_4 13617 0, // dsub_3 13618 88, // dsub_4 -> DQuadSpc_with_ssub_4 13619 0, // dsub_5 13620 0, // dsub_6 13621 0, // dsub_7 13622 0, // gsub_0 13623 0, // gsub_1 13624 0, // qqsub_0 13625 0, // qqsub_1 13626 0, // qsub_0 13627 0, // qsub_1 13628 0, // qsub_2 13629 0, // qsub_3 13630 88, // ssub_0 -> DQuadSpc_with_ssub_4 13631 88, // ssub_1 -> DQuadSpc_with_ssub_4 13632 0, // ssub_2 13633 0, // ssub_3 13634 88, // ssub_4 -> DQuadSpc_with_ssub_4 13635 88, // ssub_5 -> DQuadSpc_with_ssub_4 13636 0, // ssub_6 13637 0, // ssub_7 13638 89, // ssub_8 -> DQuadSpc_with_ssub_8 13639 89, // ssub_9 -> DQuadSpc_with_ssub_8 13640 0, // ssub_10 13641 0, // ssub_11 13642 0, // ssub_12 13643 0, // ssub_13 13644 0, // dsub_7_then_ssub_0 13645 0, // dsub_7_then_ssub_1 13646 88, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_ssub_4 13647 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 13648 0, // ssub_2_ssub_3_ssub_6_ssub_7 13649 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 13650 0, // ssub_2_ssub_3_ssub_4_ssub_5 13651 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 13652 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13653 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 13654 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 13655 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13656 88, // ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_ssub_4 13657 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13658 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13659 0, // ssub_6_ssub_7_dsub_5 13660 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 13661 0, // ssub_6_ssub_7_dsub_5_dsub_7 13662 0, // ssub_6_ssub_7_ssub_8_ssub_9 13663 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13664 0, // ssub_8_ssub_9_ssub_12_ssub_13 13665 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13666 0, // dsub_5_dsub_7 13667 0, // dsub_5_ssub_12_ssub_13_dsub_7 13668 0, // dsub_5_ssub_12_ssub_13 13669 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 13670 }, 13671 { // DQuadSpc_with_ssub_8 13672 89, // dsub_0 -> DQuadSpc_with_ssub_8 13673 0, // dsub_1 13674 89, // dsub_2 -> DQuadSpc_with_ssub_8 13675 0, // dsub_3 13676 89, // dsub_4 -> DQuadSpc_with_ssub_8 13677 0, // dsub_5 13678 0, // dsub_6 13679 0, // dsub_7 13680 0, // gsub_0 13681 0, // gsub_1 13682 0, // qqsub_0 13683 0, // qqsub_1 13684 0, // qsub_0 13685 0, // qsub_1 13686 0, // qsub_2 13687 0, // qsub_3 13688 89, // ssub_0 -> DQuadSpc_with_ssub_8 13689 89, // ssub_1 -> DQuadSpc_with_ssub_8 13690 0, // ssub_2 13691 0, // ssub_3 13692 89, // ssub_4 -> DQuadSpc_with_ssub_8 13693 89, // ssub_5 -> DQuadSpc_with_ssub_8 13694 0, // ssub_6 13695 0, // ssub_7 13696 89, // ssub_8 -> DQuadSpc_with_ssub_8 13697 89, // ssub_9 -> DQuadSpc_with_ssub_8 13698 0, // ssub_10 13699 0, // ssub_11 13700 0, // ssub_12 13701 0, // ssub_13 13702 0, // dsub_7_then_ssub_0 13703 0, // dsub_7_then_ssub_1 13704 89, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_ssub_8 13705 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 13706 0, // ssub_2_ssub_3_ssub_6_ssub_7 13707 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 13708 0, // ssub_2_ssub_3_ssub_4_ssub_5 13709 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 13710 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13711 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 13712 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 13713 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13714 89, // ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_ssub_8 13715 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13716 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13717 0, // ssub_6_ssub_7_dsub_5 13718 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 13719 0, // ssub_6_ssub_7_dsub_5_dsub_7 13720 0, // ssub_6_ssub_7_ssub_8_ssub_9 13721 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13722 0, // ssub_8_ssub_9_ssub_12_ssub_13 13723 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13724 0, // dsub_5_dsub_7 13725 0, // dsub_5_ssub_12_ssub_13_dsub_7 13726 0, // dsub_5_ssub_12_ssub_13 13727 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 13728 }, 13729 { // DQuadSpc_with_dsub_0_in_DPR_8 13730 90, // dsub_0 -> DQuadSpc_with_dsub_0_in_DPR_8 13731 0, // dsub_1 13732 90, // dsub_2 -> DQuadSpc_with_dsub_0_in_DPR_8 13733 0, // dsub_3 13734 90, // dsub_4 -> DQuadSpc_with_dsub_0_in_DPR_8 13735 0, // dsub_5 13736 0, // dsub_6 13737 0, // dsub_7 13738 0, // gsub_0 13739 0, // gsub_1 13740 0, // qqsub_0 13741 0, // qqsub_1 13742 0, // qsub_0 13743 0, // qsub_1 13744 0, // qsub_2 13745 0, // qsub_3 13746 90, // ssub_0 -> DQuadSpc_with_dsub_0_in_DPR_8 13747 90, // ssub_1 -> DQuadSpc_with_dsub_0_in_DPR_8 13748 0, // ssub_2 13749 0, // ssub_3 13750 90, // ssub_4 -> DQuadSpc_with_dsub_0_in_DPR_8 13751 90, // ssub_5 -> DQuadSpc_with_dsub_0_in_DPR_8 13752 0, // ssub_6 13753 0, // ssub_7 13754 90, // ssub_8 -> DQuadSpc_with_dsub_0_in_DPR_8 13755 90, // ssub_9 -> DQuadSpc_with_dsub_0_in_DPR_8 13756 0, // ssub_10 13757 0, // ssub_11 13758 0, // ssub_12 13759 0, // ssub_13 13760 0, // dsub_7_then_ssub_0 13761 0, // dsub_7_then_ssub_1 13762 90, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_dsub_0_in_DPR_8 13763 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 13764 0, // ssub_2_ssub_3_ssub_6_ssub_7 13765 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 13766 0, // ssub_2_ssub_3_ssub_4_ssub_5 13767 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 13768 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13769 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 13770 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 13771 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13772 90, // ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_dsub_0_in_DPR_8 13773 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13774 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13775 0, // ssub_6_ssub_7_dsub_5 13776 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 13777 0, // ssub_6_ssub_7_dsub_5_dsub_7 13778 0, // ssub_6_ssub_7_ssub_8_ssub_9 13779 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13780 0, // ssub_8_ssub_9_ssub_12_ssub_13 13781 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13782 0, // dsub_5_dsub_7 13783 0, // dsub_5_ssub_12_ssub_13_dsub_7 13784 0, // dsub_5_ssub_12_ssub_13 13785 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 13786 }, 13787 { // DQuadSpc_with_dsub_2_in_DPR_8 13788 91, // dsub_0 -> DQuadSpc_with_dsub_2_in_DPR_8 13789 0, // dsub_1 13790 91, // dsub_2 -> DQuadSpc_with_dsub_2_in_DPR_8 13791 0, // dsub_3 13792 91, // dsub_4 -> DQuadSpc_with_dsub_2_in_DPR_8 13793 0, // dsub_5 13794 0, // dsub_6 13795 0, // dsub_7 13796 0, // gsub_0 13797 0, // gsub_1 13798 0, // qqsub_0 13799 0, // qqsub_1 13800 0, // qsub_0 13801 0, // qsub_1 13802 0, // qsub_2 13803 0, // qsub_3 13804 91, // ssub_0 -> DQuadSpc_with_dsub_2_in_DPR_8 13805 91, // ssub_1 -> DQuadSpc_with_dsub_2_in_DPR_8 13806 0, // ssub_2 13807 0, // ssub_3 13808 91, // ssub_4 -> DQuadSpc_with_dsub_2_in_DPR_8 13809 91, // ssub_5 -> DQuadSpc_with_dsub_2_in_DPR_8 13810 0, // ssub_6 13811 0, // ssub_7 13812 91, // ssub_8 -> DQuadSpc_with_dsub_2_in_DPR_8 13813 91, // ssub_9 -> DQuadSpc_with_dsub_2_in_DPR_8 13814 0, // ssub_10 13815 0, // ssub_11 13816 0, // ssub_12 13817 0, // ssub_13 13818 0, // dsub_7_then_ssub_0 13819 0, // dsub_7_then_ssub_1 13820 91, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_dsub_2_in_DPR_8 13821 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 13822 0, // ssub_2_ssub_3_ssub_6_ssub_7 13823 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 13824 0, // ssub_2_ssub_3_ssub_4_ssub_5 13825 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 13826 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13827 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 13828 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 13829 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13830 91, // ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_dsub_2_in_DPR_8 13831 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13832 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13833 0, // ssub_6_ssub_7_dsub_5 13834 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 13835 0, // ssub_6_ssub_7_dsub_5_dsub_7 13836 0, // ssub_6_ssub_7_ssub_8_ssub_9 13837 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13838 0, // ssub_8_ssub_9_ssub_12_ssub_13 13839 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13840 0, // dsub_5_dsub_7 13841 0, // dsub_5_ssub_12_ssub_13_dsub_7 13842 0, // dsub_5_ssub_12_ssub_13 13843 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 13844 }, 13845 { // DQuadSpc_with_dsub_4_in_DPR_8 13846 92, // dsub_0 -> DQuadSpc_with_dsub_4_in_DPR_8 13847 0, // dsub_1 13848 92, // dsub_2 -> DQuadSpc_with_dsub_4_in_DPR_8 13849 0, // dsub_3 13850 92, // dsub_4 -> DQuadSpc_with_dsub_4_in_DPR_8 13851 0, // dsub_5 13852 0, // dsub_6 13853 0, // dsub_7 13854 0, // gsub_0 13855 0, // gsub_1 13856 0, // qqsub_0 13857 0, // qqsub_1 13858 0, // qsub_0 13859 0, // qsub_1 13860 0, // qsub_2 13861 0, // qsub_3 13862 92, // ssub_0 -> DQuadSpc_with_dsub_4_in_DPR_8 13863 92, // ssub_1 -> DQuadSpc_with_dsub_4_in_DPR_8 13864 0, // ssub_2 13865 0, // ssub_3 13866 92, // ssub_4 -> DQuadSpc_with_dsub_4_in_DPR_8 13867 92, // ssub_5 -> DQuadSpc_with_dsub_4_in_DPR_8 13868 0, // ssub_6 13869 0, // ssub_7 13870 92, // ssub_8 -> DQuadSpc_with_dsub_4_in_DPR_8 13871 92, // ssub_9 -> DQuadSpc_with_dsub_4_in_DPR_8 13872 0, // ssub_10 13873 0, // ssub_11 13874 0, // ssub_12 13875 0, // ssub_13 13876 0, // dsub_7_then_ssub_0 13877 0, // dsub_7_then_ssub_1 13878 92, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_dsub_4_in_DPR_8 13879 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 13880 0, // ssub_2_ssub_3_ssub_6_ssub_7 13881 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 13882 0, // ssub_2_ssub_3_ssub_4_ssub_5 13883 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 13884 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13885 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 13886 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 13887 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13888 92, // ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_dsub_4_in_DPR_8 13889 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13890 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13891 0, // ssub_6_ssub_7_dsub_5 13892 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 13893 0, // ssub_6_ssub_7_dsub_5_dsub_7 13894 0, // ssub_6_ssub_7_ssub_8_ssub_9 13895 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13896 0, // ssub_8_ssub_9_ssub_12_ssub_13 13897 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13898 0, // dsub_5_dsub_7 13899 0, // dsub_5_ssub_12_ssub_13_dsub_7 13900 0, // dsub_5_ssub_12_ssub_13 13901 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 13902 }, 13903 { // DQuad 13904 93, // dsub_0 -> DQuad 13905 93, // dsub_1 -> DQuad 13906 93, // dsub_2 -> DQuad 13907 93, // dsub_3 -> DQuad 13908 0, // dsub_4 13909 0, // dsub_5 13910 0, // dsub_6 13911 0, // dsub_7 13912 0, // gsub_0 13913 0, // gsub_1 13914 0, // qqsub_0 13915 0, // qqsub_1 13916 93, // qsub_0 -> DQuad 13917 93, // qsub_1 -> DQuad 13918 0, // qsub_2 13919 0, // qsub_3 13920 94, // ssub_0 -> DQuad_with_ssub_0 13921 94, // ssub_1 -> DQuad_with_ssub_0 13922 95, // ssub_2 -> DQuad_with_ssub_2 13923 95, // ssub_3 -> DQuad_with_ssub_2 13924 98, // ssub_4 -> DQuad_with_ssub_4 13925 98, // ssub_5 -> DQuad_with_ssub_4 13926 99, // ssub_6 -> DQuad_with_ssub_6 13927 99, // ssub_7 -> DQuad_with_ssub_6 13928 0, // ssub_8 13929 0, // ssub_9 13930 0, // ssub_10 13931 0, // ssub_11 13932 0, // ssub_12 13933 0, // ssub_13 13934 0, // dsub_7_then_ssub_0 13935 0, // dsub_7_then_ssub_1 13936 93, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad 13937 93, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad 13938 93, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad 13939 93, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad 13940 93, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad 13941 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 13942 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13943 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 13944 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 13945 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13946 0, // ssub_4_ssub_5_ssub_8_ssub_9 13947 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 13948 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 13949 0, // ssub_6_ssub_7_dsub_5 13950 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 13951 0, // ssub_6_ssub_7_dsub_5_dsub_7 13952 0, // ssub_6_ssub_7_ssub_8_ssub_9 13953 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13954 0, // ssub_8_ssub_9_ssub_12_ssub_13 13955 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 13956 0, // dsub_5_dsub_7 13957 0, // dsub_5_ssub_12_ssub_13_dsub_7 13958 0, // dsub_5_ssub_12_ssub_13 13959 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 13960 }, 13961 { // DQuad_with_ssub_0 13962 94, // dsub_0 -> DQuad_with_ssub_0 13963 94, // dsub_1 -> DQuad_with_ssub_0 13964 94, // dsub_2 -> DQuad_with_ssub_0 13965 94, // dsub_3 -> DQuad_with_ssub_0 13966 0, // dsub_4 13967 0, // dsub_5 13968 0, // dsub_6 13969 0, // dsub_7 13970 0, // gsub_0 13971 0, // gsub_1 13972 0, // qqsub_0 13973 0, // qqsub_1 13974 94, // qsub_0 -> DQuad_with_ssub_0 13975 94, // qsub_1 -> DQuad_with_ssub_0 13976 0, // qsub_2 13977 0, // qsub_3 13978 94, // ssub_0 -> DQuad_with_ssub_0 13979 94, // ssub_1 -> DQuad_with_ssub_0 13980 95, // ssub_2 -> DQuad_with_ssub_2 13981 95, // ssub_3 -> DQuad_with_ssub_2 13982 98, // ssub_4 -> DQuad_with_ssub_4 13983 98, // ssub_5 -> DQuad_with_ssub_4 13984 99, // ssub_6 -> DQuad_with_ssub_6 13985 99, // ssub_7 -> DQuad_with_ssub_6 13986 0, // ssub_8 13987 0, // ssub_9 13988 0, // ssub_10 13989 0, // ssub_11 13990 0, // ssub_12 13991 0, // ssub_13 13992 0, // dsub_7_then_ssub_0 13993 0, // dsub_7_then_ssub_1 13994 94, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_0 13995 94, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_0 13996 94, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_0 13997 94, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_0 13998 94, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_0 13999 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 14000 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14001 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 14002 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 14003 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14004 0, // ssub_4_ssub_5_ssub_8_ssub_9 14005 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14006 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14007 0, // ssub_6_ssub_7_dsub_5 14008 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 14009 0, // ssub_6_ssub_7_dsub_5_dsub_7 14010 0, // ssub_6_ssub_7_ssub_8_ssub_9 14011 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14012 0, // ssub_8_ssub_9_ssub_12_ssub_13 14013 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14014 0, // dsub_5_dsub_7 14015 0, // dsub_5_ssub_12_ssub_13_dsub_7 14016 0, // dsub_5_ssub_12_ssub_13 14017 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 14018 }, 14019 { // DQuad_with_ssub_2 14020 95, // dsub_0 -> DQuad_with_ssub_2 14021 95, // dsub_1 -> DQuad_with_ssub_2 14022 95, // dsub_2 -> DQuad_with_ssub_2 14023 95, // dsub_3 -> DQuad_with_ssub_2 14024 0, // dsub_4 14025 0, // dsub_5 14026 0, // dsub_6 14027 0, // dsub_7 14028 0, // gsub_0 14029 0, // gsub_1 14030 0, // qqsub_0 14031 0, // qqsub_1 14032 95, // qsub_0 -> DQuad_with_ssub_2 14033 95, // qsub_1 -> DQuad_with_ssub_2 14034 0, // qsub_2 14035 0, // qsub_3 14036 95, // ssub_0 -> DQuad_with_ssub_2 14037 95, // ssub_1 -> DQuad_with_ssub_2 14038 95, // ssub_2 -> DQuad_with_ssub_2 14039 95, // ssub_3 -> DQuad_with_ssub_2 14040 98, // ssub_4 -> DQuad_with_ssub_4 14041 98, // ssub_5 -> DQuad_with_ssub_4 14042 99, // ssub_6 -> DQuad_with_ssub_6 14043 99, // ssub_7 -> DQuad_with_ssub_6 14044 0, // ssub_8 14045 0, // ssub_9 14046 0, // ssub_10 14047 0, // ssub_11 14048 0, // ssub_12 14049 0, // ssub_13 14050 0, // dsub_7_then_ssub_0 14051 0, // dsub_7_then_ssub_1 14052 95, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_2 14053 95, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2 14054 95, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_2 14055 95, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_2 14056 95, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2 14057 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 14058 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14059 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 14060 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 14061 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14062 0, // ssub_4_ssub_5_ssub_8_ssub_9 14063 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14064 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14065 0, // ssub_6_ssub_7_dsub_5 14066 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 14067 0, // ssub_6_ssub_7_dsub_5_dsub_7 14068 0, // ssub_6_ssub_7_ssub_8_ssub_9 14069 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14070 0, // ssub_8_ssub_9_ssub_12_ssub_13 14071 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14072 0, // dsub_5_dsub_7 14073 0, // dsub_5_ssub_12_ssub_13_dsub_7 14074 0, // dsub_5_ssub_12_ssub_13 14075 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 14076 }, 14077 { // QQPR 14078 96, // dsub_0 -> QQPR 14079 96, // dsub_1 -> QQPR 14080 96, // dsub_2 -> QQPR 14081 96, // dsub_3 -> QQPR 14082 0, // dsub_4 14083 0, // dsub_5 14084 0, // dsub_6 14085 0, // dsub_7 14086 0, // gsub_0 14087 0, // gsub_1 14088 0, // qqsub_0 14089 0, // qqsub_1 14090 96, // qsub_0 -> QQPR 14091 96, // qsub_1 -> QQPR 14092 0, // qsub_2 14093 0, // qsub_3 14094 101, // ssub_0 -> DQuad_with_qsub_0_in_MQPR 14095 101, // ssub_1 -> DQuad_with_qsub_0_in_MQPR 14096 101, // ssub_2 -> DQuad_with_qsub_0_in_MQPR 14097 101, // ssub_3 -> DQuad_with_qsub_0_in_MQPR 14098 104, // ssub_4 -> DQuad_with_qsub_1_in_MQPR 14099 104, // ssub_5 -> DQuad_with_qsub_1_in_MQPR 14100 104, // ssub_6 -> DQuad_with_qsub_1_in_MQPR 14101 104, // ssub_7 -> DQuad_with_qsub_1_in_MQPR 14102 0, // ssub_8 14103 0, // ssub_9 14104 0, // ssub_10 14105 0, // ssub_11 14106 0, // ssub_12 14107 0, // ssub_13 14108 0, // dsub_7_then_ssub_0 14109 0, // dsub_7_then_ssub_1 14110 96, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQPR 14111 96, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQPR 14112 96, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQPR 14113 96, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQPR 14114 96, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQPR 14115 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 14116 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14117 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 14118 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 14119 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14120 0, // ssub_4_ssub_5_ssub_8_ssub_9 14121 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14122 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14123 0, // ssub_6_ssub_7_dsub_5 14124 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 14125 0, // ssub_6_ssub_7_dsub_5_dsub_7 14126 0, // ssub_6_ssub_7_ssub_8_ssub_9 14127 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14128 0, // ssub_8_ssub_9_ssub_12_ssub_13 14129 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14130 0, // dsub_5_dsub_7 14131 0, // dsub_5_ssub_12_ssub_13_dsub_7 14132 0, // dsub_5_ssub_12_ssub_13 14133 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 14134 }, 14135 { // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14136 97, // dsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14137 97, // dsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14138 97, // dsub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14139 97, // dsub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14140 0, // dsub_4 14141 0, // dsub_5 14142 0, // dsub_6 14143 0, // dsub_7 14144 0, // gsub_0 14145 0, // gsub_1 14146 0, // qqsub_0 14147 0, // qqsub_1 14148 97, // qsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14149 97, // qsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14150 0, // qsub_2 14151 0, // qsub_3 14152 102, // ssub_0 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14153 102, // ssub_1 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14154 105, // ssub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14155 105, // ssub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14156 105, // ssub_4 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14157 105, // ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14158 107, // ssub_6 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14159 107, // ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14160 0, // ssub_8 14161 0, // ssub_9 14162 0, // ssub_10 14163 0, // ssub_11 14164 0, // ssub_12 14165 0, // ssub_13 14166 0, // dsub_7_then_ssub_0 14167 0, // dsub_7_then_ssub_1 14168 97, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14169 97, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14170 97, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14171 97, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14172 97, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14173 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 14174 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14175 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 14176 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 14177 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14178 0, // ssub_4_ssub_5_ssub_8_ssub_9 14179 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14180 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14181 0, // ssub_6_ssub_7_dsub_5 14182 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 14183 0, // ssub_6_ssub_7_dsub_5_dsub_7 14184 0, // ssub_6_ssub_7_ssub_8_ssub_9 14185 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14186 0, // ssub_8_ssub_9_ssub_12_ssub_13 14187 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14188 0, // dsub_5_dsub_7 14189 0, // dsub_5_ssub_12_ssub_13_dsub_7 14190 0, // dsub_5_ssub_12_ssub_13 14191 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 14192 }, 14193 { // DQuad_with_ssub_4 14194 98, // dsub_0 -> DQuad_with_ssub_4 14195 98, // dsub_1 -> DQuad_with_ssub_4 14196 98, // dsub_2 -> DQuad_with_ssub_4 14197 98, // dsub_3 -> DQuad_with_ssub_4 14198 0, // dsub_4 14199 0, // dsub_5 14200 0, // dsub_6 14201 0, // dsub_7 14202 0, // gsub_0 14203 0, // gsub_1 14204 0, // qqsub_0 14205 0, // qqsub_1 14206 98, // qsub_0 -> DQuad_with_ssub_4 14207 98, // qsub_1 -> DQuad_with_ssub_4 14208 0, // qsub_2 14209 0, // qsub_3 14210 98, // ssub_0 -> DQuad_with_ssub_4 14211 98, // ssub_1 -> DQuad_with_ssub_4 14212 98, // ssub_2 -> DQuad_with_ssub_4 14213 98, // ssub_3 -> DQuad_with_ssub_4 14214 98, // ssub_4 -> DQuad_with_ssub_4 14215 98, // ssub_5 -> DQuad_with_ssub_4 14216 99, // ssub_6 -> DQuad_with_ssub_6 14217 99, // ssub_7 -> DQuad_with_ssub_6 14218 0, // ssub_8 14219 0, // ssub_9 14220 0, // ssub_10 14221 0, // ssub_11 14222 0, // ssub_12 14223 0, // ssub_13 14224 0, // dsub_7_then_ssub_0 14225 0, // dsub_7_then_ssub_1 14226 98, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_4 14227 98, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_4 14228 98, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_4 14229 98, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_4 14230 98, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_4 14231 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 14232 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14233 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 14234 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 14235 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14236 0, // ssub_4_ssub_5_ssub_8_ssub_9 14237 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14238 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14239 0, // ssub_6_ssub_7_dsub_5 14240 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 14241 0, // ssub_6_ssub_7_dsub_5_dsub_7 14242 0, // ssub_6_ssub_7_ssub_8_ssub_9 14243 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14244 0, // ssub_8_ssub_9_ssub_12_ssub_13 14245 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14246 0, // dsub_5_dsub_7 14247 0, // dsub_5_ssub_12_ssub_13_dsub_7 14248 0, // dsub_5_ssub_12_ssub_13 14249 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 14250 }, 14251 { // DQuad_with_ssub_6 14252 99, // dsub_0 -> DQuad_with_ssub_6 14253 99, // dsub_1 -> DQuad_with_ssub_6 14254 99, // dsub_2 -> DQuad_with_ssub_6 14255 99, // dsub_3 -> DQuad_with_ssub_6 14256 0, // dsub_4 14257 0, // dsub_5 14258 0, // dsub_6 14259 0, // dsub_7 14260 0, // gsub_0 14261 0, // gsub_1 14262 0, // qqsub_0 14263 0, // qqsub_1 14264 99, // qsub_0 -> DQuad_with_ssub_6 14265 99, // qsub_1 -> DQuad_with_ssub_6 14266 0, // qsub_2 14267 0, // qsub_3 14268 99, // ssub_0 -> DQuad_with_ssub_6 14269 99, // ssub_1 -> DQuad_with_ssub_6 14270 99, // ssub_2 -> DQuad_with_ssub_6 14271 99, // ssub_3 -> DQuad_with_ssub_6 14272 99, // ssub_4 -> DQuad_with_ssub_6 14273 99, // ssub_5 -> DQuad_with_ssub_6 14274 99, // ssub_6 -> DQuad_with_ssub_6 14275 99, // ssub_7 -> DQuad_with_ssub_6 14276 0, // ssub_8 14277 0, // ssub_9 14278 0, // ssub_10 14279 0, // ssub_11 14280 0, // ssub_12 14281 0, // ssub_13 14282 0, // dsub_7_then_ssub_0 14283 0, // dsub_7_then_ssub_1 14284 99, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_6 14285 99, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_6 14286 99, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_6 14287 99, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_6 14288 99, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_6 14289 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 14290 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14291 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 14292 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 14293 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14294 0, // ssub_4_ssub_5_ssub_8_ssub_9 14295 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14296 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14297 0, // ssub_6_ssub_7_dsub_5 14298 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 14299 0, // ssub_6_ssub_7_dsub_5_dsub_7 14300 0, // ssub_6_ssub_7_ssub_8_ssub_9 14301 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14302 0, // ssub_8_ssub_9_ssub_12_ssub_13 14303 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14304 0, // dsub_5_dsub_7 14305 0, // dsub_5_ssub_12_ssub_13_dsub_7 14306 0, // dsub_5_ssub_12_ssub_13 14307 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 14308 }, 14309 { // DQuad_with_dsub_0_in_DPR_8 14310 100, // dsub_0 -> DQuad_with_dsub_0_in_DPR_8 14311 100, // dsub_1 -> DQuad_with_dsub_0_in_DPR_8 14312 100, // dsub_2 -> DQuad_with_dsub_0_in_DPR_8 14313 100, // dsub_3 -> DQuad_with_dsub_0_in_DPR_8 14314 0, // dsub_4 14315 0, // dsub_5 14316 0, // dsub_6 14317 0, // dsub_7 14318 0, // gsub_0 14319 0, // gsub_1 14320 0, // qqsub_0 14321 0, // qqsub_1 14322 100, // qsub_0 -> DQuad_with_dsub_0_in_DPR_8 14323 100, // qsub_1 -> DQuad_with_dsub_0_in_DPR_8 14324 0, // qsub_2 14325 0, // qsub_3 14326 100, // ssub_0 -> DQuad_with_dsub_0_in_DPR_8 14327 100, // ssub_1 -> DQuad_with_dsub_0_in_DPR_8 14328 100, // ssub_2 -> DQuad_with_dsub_0_in_DPR_8 14329 100, // ssub_3 -> DQuad_with_dsub_0_in_DPR_8 14330 100, // ssub_4 -> DQuad_with_dsub_0_in_DPR_8 14331 100, // ssub_5 -> DQuad_with_dsub_0_in_DPR_8 14332 100, // ssub_6 -> DQuad_with_dsub_0_in_DPR_8 14333 100, // ssub_7 -> DQuad_with_dsub_0_in_DPR_8 14334 0, // ssub_8 14335 0, // ssub_9 14336 0, // ssub_10 14337 0, // ssub_11 14338 0, // ssub_12 14339 0, // ssub_13 14340 0, // dsub_7_then_ssub_0 14341 0, // dsub_7_then_ssub_1 14342 100, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8 14343 100, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8 14344 100, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_0_in_DPR_8 14345 100, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_0_in_DPR_8 14346 100, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8 14347 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 14348 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14349 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 14350 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 14351 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14352 0, // ssub_4_ssub_5_ssub_8_ssub_9 14353 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14354 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14355 0, // ssub_6_ssub_7_dsub_5 14356 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 14357 0, // ssub_6_ssub_7_dsub_5_dsub_7 14358 0, // ssub_6_ssub_7_ssub_8_ssub_9 14359 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14360 0, // ssub_8_ssub_9_ssub_12_ssub_13 14361 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14362 0, // dsub_5_dsub_7 14363 0, // dsub_5_ssub_12_ssub_13_dsub_7 14364 0, // dsub_5_ssub_12_ssub_13 14365 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 14366 }, 14367 { // DQuad_with_qsub_0_in_MQPR 14368 101, // dsub_0 -> DQuad_with_qsub_0_in_MQPR 14369 101, // dsub_1 -> DQuad_with_qsub_0_in_MQPR 14370 101, // dsub_2 -> DQuad_with_qsub_0_in_MQPR 14371 101, // dsub_3 -> DQuad_with_qsub_0_in_MQPR 14372 0, // dsub_4 14373 0, // dsub_5 14374 0, // dsub_6 14375 0, // dsub_7 14376 0, // gsub_0 14377 0, // gsub_1 14378 0, // qqsub_0 14379 0, // qqsub_1 14380 101, // qsub_0 -> DQuad_with_qsub_0_in_MQPR 14381 101, // qsub_1 -> DQuad_with_qsub_0_in_MQPR 14382 0, // qsub_2 14383 0, // qsub_3 14384 101, // ssub_0 -> DQuad_with_qsub_0_in_MQPR 14385 101, // ssub_1 -> DQuad_with_qsub_0_in_MQPR 14386 101, // ssub_2 -> DQuad_with_qsub_0_in_MQPR 14387 101, // ssub_3 -> DQuad_with_qsub_0_in_MQPR 14388 104, // ssub_4 -> DQuad_with_qsub_1_in_MQPR 14389 104, // ssub_5 -> DQuad_with_qsub_1_in_MQPR 14390 104, // ssub_6 -> DQuad_with_qsub_1_in_MQPR 14391 104, // ssub_7 -> DQuad_with_qsub_1_in_MQPR 14392 0, // ssub_8 14393 0, // ssub_9 14394 0, // ssub_10 14395 0, // ssub_11 14396 0, // ssub_12 14397 0, // ssub_13 14398 0, // dsub_7_then_ssub_0 14399 0, // dsub_7_then_ssub_1 14400 101, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_MQPR 14401 101, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_MQPR 14402 101, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_qsub_0_in_MQPR 14403 101, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_qsub_0_in_MQPR 14404 101, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_MQPR 14405 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 14406 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14407 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 14408 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 14409 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14410 0, // ssub_4_ssub_5_ssub_8_ssub_9 14411 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14412 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14413 0, // ssub_6_ssub_7_dsub_5 14414 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 14415 0, // ssub_6_ssub_7_dsub_5_dsub_7 14416 0, // ssub_6_ssub_7_ssub_8_ssub_9 14417 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14418 0, // ssub_8_ssub_9_ssub_12_ssub_13 14419 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14420 0, // dsub_5_dsub_7 14421 0, // dsub_5_ssub_12_ssub_13_dsub_7 14422 0, // dsub_5_ssub_12_ssub_13 14423 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 14424 }, 14425 { // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14426 102, // dsub_0 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14427 102, // dsub_1 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14428 102, // dsub_2 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14429 102, // dsub_3 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14430 0, // dsub_4 14431 0, // dsub_5 14432 0, // dsub_6 14433 0, // dsub_7 14434 0, // gsub_0 14435 0, // gsub_1 14436 0, // qqsub_0 14437 0, // qqsub_1 14438 102, // qsub_0 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14439 102, // qsub_1 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14440 0, // qsub_2 14441 0, // qsub_3 14442 102, // ssub_0 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14443 102, // ssub_1 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14444 105, // ssub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14445 105, // ssub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14446 105, // ssub_4 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14447 105, // ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14448 107, // ssub_6 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14449 107, // ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14450 0, // ssub_8 14451 0, // ssub_9 14452 0, // ssub_10 14453 0, // ssub_11 14454 0, // ssub_12 14455 0, // ssub_13 14456 0, // dsub_7_then_ssub_0 14457 0, // dsub_7_then_ssub_1 14458 102, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14459 102, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14460 102, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14461 102, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14462 102, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 14463 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 14464 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14465 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 14466 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 14467 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14468 0, // ssub_4_ssub_5_ssub_8_ssub_9 14469 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14470 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14471 0, // ssub_6_ssub_7_dsub_5 14472 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 14473 0, // ssub_6_ssub_7_dsub_5_dsub_7 14474 0, // ssub_6_ssub_7_ssub_8_ssub_9 14475 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14476 0, // ssub_8_ssub_9_ssub_12_ssub_13 14477 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14478 0, // dsub_5_dsub_7 14479 0, // dsub_5_ssub_12_ssub_13_dsub_7 14480 0, // dsub_5_ssub_12_ssub_13 14481 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 14482 }, 14483 { // DQuad_with_dsub_1_in_DPR_8 14484 103, // dsub_0 -> DQuad_with_dsub_1_in_DPR_8 14485 103, // dsub_1 -> DQuad_with_dsub_1_in_DPR_8 14486 103, // dsub_2 -> DQuad_with_dsub_1_in_DPR_8 14487 103, // dsub_3 -> DQuad_with_dsub_1_in_DPR_8 14488 0, // dsub_4 14489 0, // dsub_5 14490 0, // dsub_6 14491 0, // dsub_7 14492 0, // gsub_0 14493 0, // gsub_1 14494 0, // qqsub_0 14495 0, // qqsub_1 14496 103, // qsub_0 -> DQuad_with_dsub_1_in_DPR_8 14497 103, // qsub_1 -> DQuad_with_dsub_1_in_DPR_8 14498 0, // qsub_2 14499 0, // qsub_3 14500 103, // ssub_0 -> DQuad_with_dsub_1_in_DPR_8 14501 103, // ssub_1 -> DQuad_with_dsub_1_in_DPR_8 14502 103, // ssub_2 -> DQuad_with_dsub_1_in_DPR_8 14503 103, // ssub_3 -> DQuad_with_dsub_1_in_DPR_8 14504 103, // ssub_4 -> DQuad_with_dsub_1_in_DPR_8 14505 103, // ssub_5 -> DQuad_with_dsub_1_in_DPR_8 14506 103, // ssub_6 -> DQuad_with_dsub_1_in_DPR_8 14507 103, // ssub_7 -> DQuad_with_dsub_1_in_DPR_8 14508 0, // ssub_8 14509 0, // ssub_9 14510 0, // ssub_10 14511 0, // ssub_11 14512 0, // ssub_12 14513 0, // ssub_13 14514 0, // dsub_7_then_ssub_0 14515 0, // dsub_7_then_ssub_1 14516 103, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_1_in_DPR_8 14517 103, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_1_in_DPR_8 14518 103, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_1_in_DPR_8 14519 103, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_1_in_DPR_8 14520 103, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_1_in_DPR_8 14521 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 14522 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14523 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 14524 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 14525 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14526 0, // ssub_4_ssub_5_ssub_8_ssub_9 14527 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14528 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14529 0, // ssub_6_ssub_7_dsub_5 14530 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 14531 0, // ssub_6_ssub_7_dsub_5_dsub_7 14532 0, // ssub_6_ssub_7_ssub_8_ssub_9 14533 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14534 0, // ssub_8_ssub_9_ssub_12_ssub_13 14535 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14536 0, // dsub_5_dsub_7 14537 0, // dsub_5_ssub_12_ssub_13_dsub_7 14538 0, // dsub_5_ssub_12_ssub_13 14539 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 14540 }, 14541 { // DQuad_with_qsub_1_in_MQPR 14542 104, // dsub_0 -> DQuad_with_qsub_1_in_MQPR 14543 104, // dsub_1 -> DQuad_with_qsub_1_in_MQPR 14544 104, // dsub_2 -> DQuad_with_qsub_1_in_MQPR 14545 104, // dsub_3 -> DQuad_with_qsub_1_in_MQPR 14546 0, // dsub_4 14547 0, // dsub_5 14548 0, // dsub_6 14549 0, // dsub_7 14550 0, // gsub_0 14551 0, // gsub_1 14552 0, // qqsub_0 14553 0, // qqsub_1 14554 104, // qsub_0 -> DQuad_with_qsub_1_in_MQPR 14555 104, // qsub_1 -> DQuad_with_qsub_1_in_MQPR 14556 0, // qsub_2 14557 0, // qsub_3 14558 104, // ssub_0 -> DQuad_with_qsub_1_in_MQPR 14559 104, // ssub_1 -> DQuad_with_qsub_1_in_MQPR 14560 104, // ssub_2 -> DQuad_with_qsub_1_in_MQPR 14561 104, // ssub_3 -> DQuad_with_qsub_1_in_MQPR 14562 104, // ssub_4 -> DQuad_with_qsub_1_in_MQPR 14563 104, // ssub_5 -> DQuad_with_qsub_1_in_MQPR 14564 104, // ssub_6 -> DQuad_with_qsub_1_in_MQPR 14565 104, // ssub_7 -> DQuad_with_qsub_1_in_MQPR 14566 0, // ssub_8 14567 0, // ssub_9 14568 0, // ssub_10 14569 0, // ssub_11 14570 0, // ssub_12 14571 0, // ssub_13 14572 0, // dsub_7_then_ssub_0 14573 0, // dsub_7_then_ssub_1 14574 104, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_MQPR 14575 104, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_MQPR 14576 104, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_qsub_1_in_MQPR 14577 104, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_qsub_1_in_MQPR 14578 104, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_MQPR 14579 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 14580 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14581 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 14582 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 14583 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14584 0, // ssub_4_ssub_5_ssub_8_ssub_9 14585 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14586 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14587 0, // ssub_6_ssub_7_dsub_5 14588 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 14589 0, // ssub_6_ssub_7_dsub_5_dsub_7 14590 0, // ssub_6_ssub_7_ssub_8_ssub_9 14591 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14592 0, // ssub_8_ssub_9_ssub_12_ssub_13 14593 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14594 0, // dsub_5_dsub_7 14595 0, // dsub_5_ssub_12_ssub_13_dsub_7 14596 0, // dsub_5_ssub_12_ssub_13 14597 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 14598 }, 14599 { // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14600 105, // dsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14601 105, // dsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14602 105, // dsub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14603 105, // dsub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14604 0, // dsub_4 14605 0, // dsub_5 14606 0, // dsub_6 14607 0, // dsub_7 14608 0, // gsub_0 14609 0, // gsub_1 14610 0, // qqsub_0 14611 0, // qqsub_1 14612 105, // qsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14613 105, // qsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14614 0, // qsub_2 14615 0, // qsub_3 14616 105, // ssub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14617 105, // ssub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14618 105, // ssub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14619 105, // ssub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14620 105, // ssub_4 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14621 105, // ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14622 107, // ssub_6 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14623 107, // ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14624 0, // ssub_8 14625 0, // ssub_9 14626 0, // ssub_10 14627 0, // ssub_11 14628 0, // ssub_12 14629 0, // ssub_13 14630 0, // dsub_7_then_ssub_0 14631 0, // dsub_7_then_ssub_1 14632 105, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14633 105, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14634 105, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14635 105, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14636 105, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14637 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 14638 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14639 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 14640 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 14641 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14642 0, // ssub_4_ssub_5_ssub_8_ssub_9 14643 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14644 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14645 0, // ssub_6_ssub_7_dsub_5 14646 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 14647 0, // ssub_6_ssub_7_dsub_5_dsub_7 14648 0, // ssub_6_ssub_7_ssub_8_ssub_9 14649 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14650 0, // ssub_8_ssub_9_ssub_12_ssub_13 14651 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14652 0, // dsub_5_dsub_7 14653 0, // dsub_5_ssub_12_ssub_13_dsub_7 14654 0, // dsub_5_ssub_12_ssub_13 14655 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 14656 }, 14657 { // DQuad_with_dsub_2_in_DPR_8 14658 106, // dsub_0 -> DQuad_with_dsub_2_in_DPR_8 14659 106, // dsub_1 -> DQuad_with_dsub_2_in_DPR_8 14660 106, // dsub_2 -> DQuad_with_dsub_2_in_DPR_8 14661 106, // dsub_3 -> DQuad_with_dsub_2_in_DPR_8 14662 0, // dsub_4 14663 0, // dsub_5 14664 0, // dsub_6 14665 0, // dsub_7 14666 0, // gsub_0 14667 0, // gsub_1 14668 0, // qqsub_0 14669 0, // qqsub_1 14670 106, // qsub_0 -> DQuad_with_dsub_2_in_DPR_8 14671 106, // qsub_1 -> DQuad_with_dsub_2_in_DPR_8 14672 0, // qsub_2 14673 0, // qsub_3 14674 106, // ssub_0 -> DQuad_with_dsub_2_in_DPR_8 14675 106, // ssub_1 -> DQuad_with_dsub_2_in_DPR_8 14676 106, // ssub_2 -> DQuad_with_dsub_2_in_DPR_8 14677 106, // ssub_3 -> DQuad_with_dsub_2_in_DPR_8 14678 106, // ssub_4 -> DQuad_with_dsub_2_in_DPR_8 14679 106, // ssub_5 -> DQuad_with_dsub_2_in_DPR_8 14680 106, // ssub_6 -> DQuad_with_dsub_2_in_DPR_8 14681 106, // ssub_7 -> DQuad_with_dsub_2_in_DPR_8 14682 0, // ssub_8 14683 0, // ssub_9 14684 0, // ssub_10 14685 0, // ssub_11 14686 0, // ssub_12 14687 0, // ssub_13 14688 0, // dsub_7_then_ssub_0 14689 0, // dsub_7_then_ssub_1 14690 106, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_2_in_DPR_8 14691 106, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_2_in_DPR_8 14692 106, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_2_in_DPR_8 14693 106, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_2_in_DPR_8 14694 106, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_2_in_DPR_8 14695 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 14696 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14697 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 14698 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 14699 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14700 0, // ssub_4_ssub_5_ssub_8_ssub_9 14701 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14702 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14703 0, // ssub_6_ssub_7_dsub_5 14704 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 14705 0, // ssub_6_ssub_7_dsub_5_dsub_7 14706 0, // ssub_6_ssub_7_ssub_8_ssub_9 14707 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14708 0, // ssub_8_ssub_9_ssub_12_ssub_13 14709 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14710 0, // dsub_5_dsub_7 14711 0, // dsub_5_ssub_12_ssub_13_dsub_7 14712 0, // dsub_5_ssub_12_ssub_13 14713 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 14714 }, 14715 { // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14716 107, // dsub_0 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14717 107, // dsub_1 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14718 107, // dsub_2 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14719 107, // dsub_3 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14720 0, // dsub_4 14721 0, // dsub_5 14722 0, // dsub_6 14723 0, // dsub_7 14724 0, // gsub_0 14725 0, // gsub_1 14726 0, // qqsub_0 14727 0, // qqsub_1 14728 107, // qsub_0 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14729 107, // qsub_1 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14730 0, // qsub_2 14731 0, // qsub_3 14732 107, // ssub_0 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14733 107, // ssub_1 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14734 107, // ssub_2 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14735 107, // ssub_3 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14736 107, // ssub_4 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14737 107, // ssub_5 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14738 107, // ssub_6 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14739 107, // ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14740 0, // ssub_8 14741 0, // ssub_9 14742 0, // ssub_10 14743 0, // ssub_11 14744 0, // ssub_12 14745 0, // ssub_13 14746 0, // dsub_7_then_ssub_0 14747 0, // dsub_7_then_ssub_1 14748 107, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14749 107, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14750 107, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14751 107, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14752 107, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14753 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 14754 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14755 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 14756 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 14757 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14758 0, // ssub_4_ssub_5_ssub_8_ssub_9 14759 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14760 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14761 0, // ssub_6_ssub_7_dsub_5 14762 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 14763 0, // ssub_6_ssub_7_dsub_5_dsub_7 14764 0, // ssub_6_ssub_7_ssub_8_ssub_9 14765 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14766 0, // ssub_8_ssub_9_ssub_12_ssub_13 14767 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14768 0, // dsub_5_dsub_7 14769 0, // dsub_5_ssub_12_ssub_13_dsub_7 14770 0, // dsub_5_ssub_12_ssub_13 14771 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 14772 }, 14773 { // DQuad_with_dsub_3_in_DPR_8 14774 108, // dsub_0 -> DQuad_with_dsub_3_in_DPR_8 14775 108, // dsub_1 -> DQuad_with_dsub_3_in_DPR_8 14776 108, // dsub_2 -> DQuad_with_dsub_3_in_DPR_8 14777 108, // dsub_3 -> DQuad_with_dsub_3_in_DPR_8 14778 0, // dsub_4 14779 0, // dsub_5 14780 0, // dsub_6 14781 0, // dsub_7 14782 0, // gsub_0 14783 0, // gsub_1 14784 0, // qqsub_0 14785 0, // qqsub_1 14786 108, // qsub_0 -> DQuad_with_dsub_3_in_DPR_8 14787 108, // qsub_1 -> DQuad_with_dsub_3_in_DPR_8 14788 0, // qsub_2 14789 0, // qsub_3 14790 108, // ssub_0 -> DQuad_with_dsub_3_in_DPR_8 14791 108, // ssub_1 -> DQuad_with_dsub_3_in_DPR_8 14792 108, // ssub_2 -> DQuad_with_dsub_3_in_DPR_8 14793 108, // ssub_3 -> DQuad_with_dsub_3_in_DPR_8 14794 108, // ssub_4 -> DQuad_with_dsub_3_in_DPR_8 14795 108, // ssub_5 -> DQuad_with_dsub_3_in_DPR_8 14796 108, // ssub_6 -> DQuad_with_dsub_3_in_DPR_8 14797 108, // ssub_7 -> DQuad_with_dsub_3_in_DPR_8 14798 0, // ssub_8 14799 0, // ssub_9 14800 0, // ssub_10 14801 0, // ssub_11 14802 0, // ssub_12 14803 0, // ssub_13 14804 0, // dsub_7_then_ssub_0 14805 0, // dsub_7_then_ssub_1 14806 108, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8 14807 108, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8 14808 108, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_3_in_DPR_8 14809 108, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_3_in_DPR_8 14810 108, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8 14811 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 14812 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14813 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 14814 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 14815 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14816 0, // ssub_4_ssub_5_ssub_8_ssub_9 14817 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14818 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14819 0, // ssub_6_ssub_7_dsub_5 14820 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 14821 0, // ssub_6_ssub_7_dsub_5_dsub_7 14822 0, // ssub_6_ssub_7_ssub_8_ssub_9 14823 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14824 0, // ssub_8_ssub_9_ssub_12_ssub_13 14825 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14826 0, // dsub_5_dsub_7 14827 0, // dsub_5_ssub_12_ssub_13_dsub_7 14828 0, // dsub_5_ssub_12_ssub_13 14829 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 14830 }, 14831 { // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14832 109, // dsub_0 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14833 109, // dsub_1 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14834 109, // dsub_2 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14835 109, // dsub_3 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14836 0, // dsub_4 14837 0, // dsub_5 14838 0, // dsub_6 14839 0, // dsub_7 14840 0, // gsub_0 14841 0, // gsub_1 14842 0, // qqsub_0 14843 0, // qqsub_1 14844 109, // qsub_0 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14845 109, // qsub_1 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14846 0, // qsub_2 14847 0, // qsub_3 14848 109, // ssub_0 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14849 109, // ssub_1 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14850 109, // ssub_2 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14851 109, // ssub_3 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14852 109, // ssub_4 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14853 109, // ssub_5 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14854 109, // ssub_6 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14855 109, // ssub_7 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14856 0, // ssub_8 14857 0, // ssub_9 14858 0, // ssub_10 14859 0, // ssub_11 14860 0, // ssub_12 14861 0, // ssub_13 14862 0, // dsub_7_then_ssub_0 14863 0, // dsub_7_then_ssub_1 14864 109, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14865 109, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14866 109, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14867 109, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14868 109, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 14869 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 14870 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14871 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 14872 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 14873 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14874 0, // ssub_4_ssub_5_ssub_8_ssub_9 14875 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14876 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14877 0, // ssub_6_ssub_7_dsub_5 14878 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 14879 0, // ssub_6_ssub_7_dsub_5_dsub_7 14880 0, // ssub_6_ssub_7_ssub_8_ssub_9 14881 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14882 0, // ssub_8_ssub_9_ssub_12_ssub_13 14883 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14884 0, // dsub_5_dsub_7 14885 0, // dsub_5_ssub_12_ssub_13_dsub_7 14886 0, // dsub_5_ssub_12_ssub_13 14887 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 14888 }, 14889 { // DQuad_with_qsub_0_in_QPR_8 14890 110, // dsub_0 -> DQuad_with_qsub_0_in_QPR_8 14891 110, // dsub_1 -> DQuad_with_qsub_0_in_QPR_8 14892 110, // dsub_2 -> DQuad_with_qsub_0_in_QPR_8 14893 110, // dsub_3 -> DQuad_with_qsub_0_in_QPR_8 14894 0, // dsub_4 14895 0, // dsub_5 14896 0, // dsub_6 14897 0, // dsub_7 14898 0, // gsub_0 14899 0, // gsub_1 14900 0, // qqsub_0 14901 0, // qqsub_1 14902 110, // qsub_0 -> DQuad_with_qsub_0_in_QPR_8 14903 110, // qsub_1 -> DQuad_with_qsub_0_in_QPR_8 14904 0, // qsub_2 14905 0, // qsub_3 14906 110, // ssub_0 -> DQuad_with_qsub_0_in_QPR_8 14907 110, // ssub_1 -> DQuad_with_qsub_0_in_QPR_8 14908 110, // ssub_2 -> DQuad_with_qsub_0_in_QPR_8 14909 110, // ssub_3 -> DQuad_with_qsub_0_in_QPR_8 14910 110, // ssub_4 -> DQuad_with_qsub_0_in_QPR_8 14911 110, // ssub_5 -> DQuad_with_qsub_0_in_QPR_8 14912 110, // ssub_6 -> DQuad_with_qsub_0_in_QPR_8 14913 110, // ssub_7 -> DQuad_with_qsub_0_in_QPR_8 14914 0, // ssub_8 14915 0, // ssub_9 14916 0, // ssub_10 14917 0, // ssub_11 14918 0, // ssub_12 14919 0, // ssub_13 14920 0, // dsub_7_then_ssub_0 14921 0, // dsub_7_then_ssub_1 14922 110, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_8 14923 110, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_8 14924 110, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_qsub_0_in_QPR_8 14925 110, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_qsub_0_in_QPR_8 14926 110, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_8 14927 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 14928 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14929 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 14930 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 14931 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14932 0, // ssub_4_ssub_5_ssub_8_ssub_9 14933 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14934 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14935 0, // ssub_6_ssub_7_dsub_5 14936 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 14937 0, // ssub_6_ssub_7_dsub_5_dsub_7 14938 0, // ssub_6_ssub_7_ssub_8_ssub_9 14939 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14940 0, // ssub_8_ssub_9_ssub_12_ssub_13 14941 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14942 0, // dsub_5_dsub_7 14943 0, // dsub_5_ssub_12_ssub_13_dsub_7 14944 0, // dsub_5_ssub_12_ssub_13 14945 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 14946 }, 14947 { // DQuad_with_qsub_1_in_QPR_8 14948 111, // dsub_0 -> DQuad_with_qsub_1_in_QPR_8 14949 111, // dsub_1 -> DQuad_with_qsub_1_in_QPR_8 14950 111, // dsub_2 -> DQuad_with_qsub_1_in_QPR_8 14951 111, // dsub_3 -> DQuad_with_qsub_1_in_QPR_8 14952 0, // dsub_4 14953 0, // dsub_5 14954 0, // dsub_6 14955 0, // dsub_7 14956 0, // gsub_0 14957 0, // gsub_1 14958 0, // qqsub_0 14959 0, // qqsub_1 14960 111, // qsub_0 -> DQuad_with_qsub_1_in_QPR_8 14961 111, // qsub_1 -> DQuad_with_qsub_1_in_QPR_8 14962 0, // qsub_2 14963 0, // qsub_3 14964 111, // ssub_0 -> DQuad_with_qsub_1_in_QPR_8 14965 111, // ssub_1 -> DQuad_with_qsub_1_in_QPR_8 14966 111, // ssub_2 -> DQuad_with_qsub_1_in_QPR_8 14967 111, // ssub_3 -> DQuad_with_qsub_1_in_QPR_8 14968 111, // ssub_4 -> DQuad_with_qsub_1_in_QPR_8 14969 111, // ssub_5 -> DQuad_with_qsub_1_in_QPR_8 14970 111, // ssub_6 -> DQuad_with_qsub_1_in_QPR_8 14971 111, // ssub_7 -> DQuad_with_qsub_1_in_QPR_8 14972 0, // ssub_8 14973 0, // ssub_9 14974 0, // ssub_10 14975 0, // ssub_11 14976 0, // ssub_12 14977 0, // ssub_13 14978 0, // dsub_7_then_ssub_0 14979 0, // dsub_7_then_ssub_1 14980 111, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_8 14981 111, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_8 14982 111, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_qsub_1_in_QPR_8 14983 111, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_qsub_1_in_QPR_8 14984 111, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_8 14985 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 14986 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14987 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 14988 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 14989 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14990 0, // ssub_4_ssub_5_ssub_8_ssub_9 14991 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 14992 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 14993 0, // ssub_6_ssub_7_dsub_5 14994 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 14995 0, // ssub_6_ssub_7_dsub_5_dsub_7 14996 0, // ssub_6_ssub_7_ssub_8_ssub_9 14997 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 14998 0, // ssub_8_ssub_9_ssub_12_ssub_13 14999 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 15000 0, // dsub_5_dsub_7 15001 0, // dsub_5_ssub_12_ssub_13_dsub_7 15002 0, // dsub_5_ssub_12_ssub_13 15003 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 15004 }, 15005 { // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 15006 112, // dsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 15007 112, // dsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 15008 112, // dsub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 15009 112, // dsub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 15010 0, // dsub_4 15011 0, // dsub_5 15012 0, // dsub_6 15013 0, // dsub_7 15014 0, // gsub_0 15015 0, // gsub_1 15016 0, // qqsub_0 15017 0, // qqsub_1 15018 112, // qsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 15019 112, // qsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 15020 0, // qsub_2 15021 0, // qsub_3 15022 112, // ssub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 15023 112, // ssub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 15024 112, // ssub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 15025 112, // ssub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 15026 112, // ssub_4 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 15027 112, // ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 15028 112, // ssub_6 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 15029 112, // ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 15030 0, // ssub_8 15031 0, // ssub_9 15032 0, // ssub_10 15033 0, // ssub_11 15034 0, // ssub_12 15035 0, // ssub_13 15036 0, // dsub_7_then_ssub_0 15037 0, // dsub_7_then_ssub_1 15038 112, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 15039 112, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 15040 112, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 15041 112, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 15042 112, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 15043 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 15044 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 15045 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 15046 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 15047 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 15048 0, // ssub_4_ssub_5_ssub_8_ssub_9 15049 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 15050 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 15051 0, // ssub_6_ssub_7_dsub_5 15052 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 15053 0, // ssub_6_ssub_7_dsub_5_dsub_7 15054 0, // ssub_6_ssub_7_ssub_8_ssub_9 15055 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 15056 0, // ssub_8_ssub_9_ssub_12_ssub_13 15057 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 15058 0, // dsub_5_dsub_7 15059 0, // dsub_5_ssub_12_ssub_13_dsub_7 15060 0, // dsub_5_ssub_12_ssub_13 15061 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 15062 }, 15063 { // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15064 113, // dsub_0 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15065 113, // dsub_1 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15066 113, // dsub_2 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15067 113, // dsub_3 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15068 0, // dsub_4 15069 0, // dsub_5 15070 0, // dsub_6 15071 0, // dsub_7 15072 0, // gsub_0 15073 0, // gsub_1 15074 0, // qqsub_0 15075 0, // qqsub_1 15076 113, // qsub_0 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15077 113, // qsub_1 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15078 0, // qsub_2 15079 0, // qsub_3 15080 113, // ssub_0 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15081 113, // ssub_1 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15082 113, // ssub_2 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15083 113, // ssub_3 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15084 113, // ssub_4 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15085 113, // ssub_5 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15086 113, // ssub_6 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15087 113, // ssub_7 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15088 0, // ssub_8 15089 0, // ssub_9 15090 0, // ssub_10 15091 0, // ssub_11 15092 0, // ssub_12 15093 0, // ssub_13 15094 0, // dsub_7_then_ssub_0 15095 0, // dsub_7_then_ssub_1 15096 113, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15097 113, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15098 113, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15099 113, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15100 113, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15101 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 15102 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 15103 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 15104 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 15105 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 15106 0, // ssub_4_ssub_5_ssub_8_ssub_9 15107 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 15108 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 15109 0, // ssub_6_ssub_7_dsub_5 15110 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 15111 0, // ssub_6_ssub_7_dsub_5_dsub_7 15112 0, // ssub_6_ssub_7_ssub_8_ssub_9 15113 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 15114 0, // ssub_8_ssub_9_ssub_12_ssub_13 15115 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 15116 0, // dsub_5_dsub_7 15117 0, // dsub_5_ssub_12_ssub_13_dsub_7 15118 0, // dsub_5_ssub_12_ssub_13 15119 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 15120 }, 15121 { // QQQQPR 15122 114, // dsub_0 -> QQQQPR 15123 114, // dsub_1 -> QQQQPR 15124 114, // dsub_2 -> QQQQPR 15125 114, // dsub_3 -> QQQQPR 15126 114, // dsub_4 -> QQQQPR 15127 114, // dsub_5 -> QQQQPR 15128 114, // dsub_6 -> QQQQPR 15129 114, // dsub_7 -> QQQQPR 15130 0, // gsub_0 15131 0, // gsub_1 15132 114, // qqsub_0 -> QQQQPR 15133 114, // qqsub_1 -> QQQQPR 15134 114, // qsub_0 -> QQQQPR 15135 114, // qsub_1 -> QQQQPR 15136 114, // qsub_2 -> QQQQPR 15137 114, // qsub_3 -> QQQQPR 15138 115, // ssub_0 -> QQQQPR_with_ssub_0 15139 115, // ssub_1 -> QQQQPR_with_ssub_0 15140 115, // ssub_2 -> QQQQPR_with_ssub_0 15141 115, // ssub_3 -> QQQQPR_with_ssub_0 15142 116, // ssub_4 -> QQQQPR_with_ssub_4 15143 116, // ssub_5 -> QQQQPR_with_ssub_4 15144 116, // ssub_6 -> QQQQPR_with_ssub_4 15145 116, // ssub_7 -> QQQQPR_with_ssub_4 15146 117, // ssub_8 -> QQQQPR_with_ssub_8 15147 117, // ssub_9 -> QQQQPR_with_ssub_8 15148 117, // ssub_10 -> QQQQPR_with_ssub_8 15149 117, // ssub_11 -> QQQQPR_with_ssub_8 15150 118, // ssub_12 -> QQQQPR_with_ssub_12 15151 118, // ssub_13 -> QQQQPR_with_ssub_12 15152 118, // dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12 15153 118, // dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12 15154 114, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR 15155 114, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR 15156 114, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR 15157 114, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR 15158 114, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR 15159 114, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR 15160 114, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR 15161 114, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR 15162 114, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR 15163 114, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR 15164 114, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR 15165 114, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR 15166 114, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR 15167 114, // ssub_6_ssub_7_dsub_5 -> QQQQPR 15168 114, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR 15169 114, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR 15170 114, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR 15171 114, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR 15172 114, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR 15173 114, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR 15174 114, // dsub_5_dsub_7 -> QQQQPR 15175 114, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR 15176 114, // dsub_5_ssub_12_ssub_13 -> QQQQPR 15177 114, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR 15178 }, 15179 { // QQQQPR_with_ssub_0 15180 115, // dsub_0 -> QQQQPR_with_ssub_0 15181 115, // dsub_1 -> QQQQPR_with_ssub_0 15182 115, // dsub_2 -> QQQQPR_with_ssub_0 15183 115, // dsub_3 -> QQQQPR_with_ssub_0 15184 115, // dsub_4 -> QQQQPR_with_ssub_0 15185 115, // dsub_5 -> QQQQPR_with_ssub_0 15186 115, // dsub_6 -> QQQQPR_with_ssub_0 15187 115, // dsub_7 -> QQQQPR_with_ssub_0 15188 0, // gsub_0 15189 0, // gsub_1 15190 115, // qqsub_0 -> QQQQPR_with_ssub_0 15191 115, // qqsub_1 -> QQQQPR_with_ssub_0 15192 115, // qsub_0 -> QQQQPR_with_ssub_0 15193 115, // qsub_1 -> QQQQPR_with_ssub_0 15194 115, // qsub_2 -> QQQQPR_with_ssub_0 15195 115, // qsub_3 -> QQQQPR_with_ssub_0 15196 115, // ssub_0 -> QQQQPR_with_ssub_0 15197 115, // ssub_1 -> QQQQPR_with_ssub_0 15198 115, // ssub_2 -> QQQQPR_with_ssub_0 15199 115, // ssub_3 -> QQQQPR_with_ssub_0 15200 116, // ssub_4 -> QQQQPR_with_ssub_4 15201 116, // ssub_5 -> QQQQPR_with_ssub_4 15202 116, // ssub_6 -> QQQQPR_with_ssub_4 15203 116, // ssub_7 -> QQQQPR_with_ssub_4 15204 117, // ssub_8 -> QQQQPR_with_ssub_8 15205 117, // ssub_9 -> QQQQPR_with_ssub_8 15206 117, // ssub_10 -> QQQQPR_with_ssub_8 15207 117, // ssub_11 -> QQQQPR_with_ssub_8 15208 118, // ssub_12 -> QQQQPR_with_ssub_12 15209 118, // ssub_13 -> QQQQPR_with_ssub_12 15210 118, // dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12 15211 118, // dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12 15212 115, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_ssub_0 15213 115, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_0 15214 115, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_ssub_0 15215 115, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_ssub_0 15216 115, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_0 15217 115, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_0 15218 115, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_0 15219 115, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_0 15220 115, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_0 15221 115, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_0 15222 115, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_0 15223 115, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_0 15224 115, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_0 15225 115, // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_0 15226 115, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_ssub_0 15227 115, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_0 15228 115, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_0 15229 115, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_0 15230 115, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_0 15231 115, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_0 15232 115, // dsub_5_dsub_7 -> QQQQPR_with_ssub_0 15233 115, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_ssub_0 15234 115, // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_0 15235 115, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_ssub_0 15236 }, 15237 { // QQQQPR_with_ssub_4 15238 116, // dsub_0 -> QQQQPR_with_ssub_4 15239 116, // dsub_1 -> QQQQPR_with_ssub_4 15240 116, // dsub_2 -> QQQQPR_with_ssub_4 15241 116, // dsub_3 -> QQQQPR_with_ssub_4 15242 116, // dsub_4 -> QQQQPR_with_ssub_4 15243 116, // dsub_5 -> QQQQPR_with_ssub_4 15244 116, // dsub_6 -> QQQQPR_with_ssub_4 15245 116, // dsub_7 -> QQQQPR_with_ssub_4 15246 0, // gsub_0 15247 0, // gsub_1 15248 116, // qqsub_0 -> QQQQPR_with_ssub_4 15249 116, // qqsub_1 -> QQQQPR_with_ssub_4 15250 116, // qsub_0 -> QQQQPR_with_ssub_4 15251 116, // qsub_1 -> QQQQPR_with_ssub_4 15252 116, // qsub_2 -> QQQQPR_with_ssub_4 15253 116, // qsub_3 -> QQQQPR_with_ssub_4 15254 116, // ssub_0 -> QQQQPR_with_ssub_4 15255 116, // ssub_1 -> QQQQPR_with_ssub_4 15256 116, // ssub_2 -> QQQQPR_with_ssub_4 15257 116, // ssub_3 -> QQQQPR_with_ssub_4 15258 116, // ssub_4 -> QQQQPR_with_ssub_4 15259 116, // ssub_5 -> QQQQPR_with_ssub_4 15260 116, // ssub_6 -> QQQQPR_with_ssub_4 15261 116, // ssub_7 -> QQQQPR_with_ssub_4 15262 117, // ssub_8 -> QQQQPR_with_ssub_8 15263 117, // ssub_9 -> QQQQPR_with_ssub_8 15264 117, // ssub_10 -> QQQQPR_with_ssub_8 15265 117, // ssub_11 -> QQQQPR_with_ssub_8 15266 118, // ssub_12 -> QQQQPR_with_ssub_12 15267 118, // ssub_13 -> QQQQPR_with_ssub_12 15268 118, // dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12 15269 118, // dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12 15270 116, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_ssub_4 15271 116, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_4 15272 116, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_ssub_4 15273 116, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_ssub_4 15274 116, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_4 15275 116, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_4 15276 116, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_4 15277 116, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_4 15278 116, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_4 15279 116, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_4 15280 116, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_4 15281 116, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_4 15282 116, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_4 15283 116, // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_4 15284 116, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_ssub_4 15285 116, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_4 15286 116, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_4 15287 116, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_4 15288 116, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_4 15289 116, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_4 15290 116, // dsub_5_dsub_7 -> QQQQPR_with_ssub_4 15291 116, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_ssub_4 15292 116, // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_4 15293 116, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_ssub_4 15294 }, 15295 { // QQQQPR_with_ssub_8 15296 117, // dsub_0 -> QQQQPR_with_ssub_8 15297 117, // dsub_1 -> QQQQPR_with_ssub_8 15298 117, // dsub_2 -> QQQQPR_with_ssub_8 15299 117, // dsub_3 -> QQQQPR_with_ssub_8 15300 117, // dsub_4 -> QQQQPR_with_ssub_8 15301 117, // dsub_5 -> QQQQPR_with_ssub_8 15302 117, // dsub_6 -> QQQQPR_with_ssub_8 15303 117, // dsub_7 -> QQQQPR_with_ssub_8 15304 0, // gsub_0 15305 0, // gsub_1 15306 117, // qqsub_0 -> QQQQPR_with_ssub_8 15307 117, // qqsub_1 -> QQQQPR_with_ssub_8 15308 117, // qsub_0 -> QQQQPR_with_ssub_8 15309 117, // qsub_1 -> QQQQPR_with_ssub_8 15310 117, // qsub_2 -> QQQQPR_with_ssub_8 15311 117, // qsub_3 -> QQQQPR_with_ssub_8 15312 117, // ssub_0 -> QQQQPR_with_ssub_8 15313 117, // ssub_1 -> QQQQPR_with_ssub_8 15314 117, // ssub_2 -> QQQQPR_with_ssub_8 15315 117, // ssub_3 -> QQQQPR_with_ssub_8 15316 117, // ssub_4 -> QQQQPR_with_ssub_8 15317 117, // ssub_5 -> QQQQPR_with_ssub_8 15318 117, // ssub_6 -> QQQQPR_with_ssub_8 15319 117, // ssub_7 -> QQQQPR_with_ssub_8 15320 117, // ssub_8 -> QQQQPR_with_ssub_8 15321 117, // ssub_9 -> QQQQPR_with_ssub_8 15322 117, // ssub_10 -> QQQQPR_with_ssub_8 15323 117, // ssub_11 -> QQQQPR_with_ssub_8 15324 118, // ssub_12 -> QQQQPR_with_ssub_12 15325 118, // ssub_13 -> QQQQPR_with_ssub_12 15326 118, // dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12 15327 118, // dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12 15328 117, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_ssub_8 15329 117, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_8 15330 117, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_ssub_8 15331 117, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_ssub_8 15332 117, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_8 15333 117, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_8 15334 117, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_8 15335 117, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_8 15336 117, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_8 15337 117, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_8 15338 117, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_8 15339 117, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_8 15340 117, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_8 15341 117, // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_8 15342 117, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_ssub_8 15343 117, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_8 15344 117, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_8 15345 117, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_8 15346 117, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_8 15347 117, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_8 15348 117, // dsub_5_dsub_7 -> QQQQPR_with_ssub_8 15349 117, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_ssub_8 15350 117, // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_8 15351 117, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_ssub_8 15352 }, 15353 { // QQQQPR_with_ssub_12 15354 118, // dsub_0 -> QQQQPR_with_ssub_12 15355 118, // dsub_1 -> QQQQPR_with_ssub_12 15356 118, // dsub_2 -> QQQQPR_with_ssub_12 15357 118, // dsub_3 -> QQQQPR_with_ssub_12 15358 118, // dsub_4 -> QQQQPR_with_ssub_12 15359 118, // dsub_5 -> QQQQPR_with_ssub_12 15360 118, // dsub_6 -> QQQQPR_with_ssub_12 15361 118, // dsub_7 -> QQQQPR_with_ssub_12 15362 0, // gsub_0 15363 0, // gsub_1 15364 118, // qqsub_0 -> QQQQPR_with_ssub_12 15365 118, // qqsub_1 -> QQQQPR_with_ssub_12 15366 118, // qsub_0 -> QQQQPR_with_ssub_12 15367 118, // qsub_1 -> QQQQPR_with_ssub_12 15368 118, // qsub_2 -> QQQQPR_with_ssub_12 15369 118, // qsub_3 -> QQQQPR_with_ssub_12 15370 118, // ssub_0 -> QQQQPR_with_ssub_12 15371 118, // ssub_1 -> QQQQPR_with_ssub_12 15372 118, // ssub_2 -> QQQQPR_with_ssub_12 15373 118, // ssub_3 -> QQQQPR_with_ssub_12 15374 118, // ssub_4 -> QQQQPR_with_ssub_12 15375 118, // ssub_5 -> QQQQPR_with_ssub_12 15376 118, // ssub_6 -> QQQQPR_with_ssub_12 15377 118, // ssub_7 -> QQQQPR_with_ssub_12 15378 118, // ssub_8 -> QQQQPR_with_ssub_12 15379 118, // ssub_9 -> QQQQPR_with_ssub_12 15380 118, // ssub_10 -> QQQQPR_with_ssub_12 15381 118, // ssub_11 -> QQQQPR_with_ssub_12 15382 118, // ssub_12 -> QQQQPR_with_ssub_12 15383 118, // ssub_13 -> QQQQPR_with_ssub_12 15384 118, // dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12 15385 118, // dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12 15386 118, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_ssub_12 15387 118, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_12 15388 118, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_ssub_12 15389 118, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_ssub_12 15390 118, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_12 15391 118, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_12 15392 118, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_12 15393 118, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_12 15394 118, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_12 15395 118, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_12 15396 118, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_12 15397 118, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_12 15398 118, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_12 15399 118, // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_12 15400 118, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_ssub_12 15401 118, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_12 15402 118, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_12 15403 118, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_12 15404 118, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_12 15405 118, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_12 15406 118, // dsub_5_dsub_7 -> QQQQPR_with_ssub_12 15407 118, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_ssub_12 15408 118, // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_12 15409 118, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_ssub_12 15410 }, 15411 { // QQQQPR_with_dsub_0_in_DPR_8 15412 119, // dsub_0 -> QQQQPR_with_dsub_0_in_DPR_8 15413 119, // dsub_1 -> QQQQPR_with_dsub_0_in_DPR_8 15414 119, // dsub_2 -> QQQQPR_with_dsub_0_in_DPR_8 15415 119, // dsub_3 -> QQQQPR_with_dsub_0_in_DPR_8 15416 119, // dsub_4 -> QQQQPR_with_dsub_0_in_DPR_8 15417 119, // dsub_5 -> QQQQPR_with_dsub_0_in_DPR_8 15418 119, // dsub_6 -> QQQQPR_with_dsub_0_in_DPR_8 15419 119, // dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8 15420 0, // gsub_0 15421 0, // gsub_1 15422 119, // qqsub_0 -> QQQQPR_with_dsub_0_in_DPR_8 15423 119, // qqsub_1 -> QQQQPR_with_dsub_0_in_DPR_8 15424 119, // qsub_0 -> QQQQPR_with_dsub_0_in_DPR_8 15425 119, // qsub_1 -> QQQQPR_with_dsub_0_in_DPR_8 15426 119, // qsub_2 -> QQQQPR_with_dsub_0_in_DPR_8 15427 119, // qsub_3 -> QQQQPR_with_dsub_0_in_DPR_8 15428 119, // ssub_0 -> QQQQPR_with_dsub_0_in_DPR_8 15429 119, // ssub_1 -> QQQQPR_with_dsub_0_in_DPR_8 15430 119, // ssub_2 -> QQQQPR_with_dsub_0_in_DPR_8 15431 119, // ssub_3 -> QQQQPR_with_dsub_0_in_DPR_8 15432 119, // ssub_4 -> QQQQPR_with_dsub_0_in_DPR_8 15433 119, // ssub_5 -> QQQQPR_with_dsub_0_in_DPR_8 15434 119, // ssub_6 -> QQQQPR_with_dsub_0_in_DPR_8 15435 119, // ssub_7 -> QQQQPR_with_dsub_0_in_DPR_8 15436 119, // ssub_8 -> QQQQPR_with_dsub_0_in_DPR_8 15437 119, // ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8 15438 119, // ssub_10 -> QQQQPR_with_dsub_0_in_DPR_8 15439 119, // ssub_11 -> QQQQPR_with_dsub_0_in_DPR_8 15440 119, // ssub_12 -> QQQQPR_with_dsub_0_in_DPR_8 15441 119, // ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8 15442 119, // dsub_7_then_ssub_0 -> QQQQPR_with_dsub_0_in_DPR_8 15443 119, // dsub_7_then_ssub_1 -> QQQQPR_with_dsub_0_in_DPR_8 15444 119, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_dsub_0_in_DPR_8 15445 119, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_0_in_DPR_8 15446 119, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_dsub_0_in_DPR_8 15447 119, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_dsub_0_in_DPR_8 15448 119, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_0_in_DPR_8 15449 119, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8 15450 119, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8 15451 119, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_0_in_DPR_8 15452 119, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8 15453 119, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8 15454 119, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8 15455 119, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8 15456 119, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8 15457 119, // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_0_in_DPR_8 15458 119, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_dsub_0_in_DPR_8 15459 119, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8 15460 119, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8 15461 119, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8 15462 119, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8 15463 119, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8 15464 119, // dsub_5_dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8 15465 119, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8 15466 119, // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8 15467 119, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_dsub_0_in_DPR_8 15468 }, 15469 { // QQQQPR_with_dsub_2_in_DPR_8 15470 120, // dsub_0 -> QQQQPR_with_dsub_2_in_DPR_8 15471 120, // dsub_1 -> QQQQPR_with_dsub_2_in_DPR_8 15472 120, // dsub_2 -> QQQQPR_with_dsub_2_in_DPR_8 15473 120, // dsub_3 -> QQQQPR_with_dsub_2_in_DPR_8 15474 120, // dsub_4 -> QQQQPR_with_dsub_2_in_DPR_8 15475 120, // dsub_5 -> QQQQPR_with_dsub_2_in_DPR_8 15476 120, // dsub_6 -> QQQQPR_with_dsub_2_in_DPR_8 15477 120, // dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8 15478 0, // gsub_0 15479 0, // gsub_1 15480 120, // qqsub_0 -> QQQQPR_with_dsub_2_in_DPR_8 15481 120, // qqsub_1 -> QQQQPR_with_dsub_2_in_DPR_8 15482 120, // qsub_0 -> QQQQPR_with_dsub_2_in_DPR_8 15483 120, // qsub_1 -> QQQQPR_with_dsub_2_in_DPR_8 15484 120, // qsub_2 -> QQQQPR_with_dsub_2_in_DPR_8 15485 120, // qsub_3 -> QQQQPR_with_dsub_2_in_DPR_8 15486 120, // ssub_0 -> QQQQPR_with_dsub_2_in_DPR_8 15487 120, // ssub_1 -> QQQQPR_with_dsub_2_in_DPR_8 15488 120, // ssub_2 -> QQQQPR_with_dsub_2_in_DPR_8 15489 120, // ssub_3 -> QQQQPR_with_dsub_2_in_DPR_8 15490 120, // ssub_4 -> QQQQPR_with_dsub_2_in_DPR_8 15491 120, // ssub_5 -> QQQQPR_with_dsub_2_in_DPR_8 15492 120, // ssub_6 -> QQQQPR_with_dsub_2_in_DPR_8 15493 120, // ssub_7 -> QQQQPR_with_dsub_2_in_DPR_8 15494 120, // ssub_8 -> QQQQPR_with_dsub_2_in_DPR_8 15495 120, // ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8 15496 120, // ssub_10 -> QQQQPR_with_dsub_2_in_DPR_8 15497 120, // ssub_11 -> QQQQPR_with_dsub_2_in_DPR_8 15498 120, // ssub_12 -> QQQQPR_with_dsub_2_in_DPR_8 15499 120, // ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8 15500 120, // dsub_7_then_ssub_0 -> QQQQPR_with_dsub_2_in_DPR_8 15501 120, // dsub_7_then_ssub_1 -> QQQQPR_with_dsub_2_in_DPR_8 15502 120, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_dsub_2_in_DPR_8 15503 120, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_2_in_DPR_8 15504 120, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_dsub_2_in_DPR_8 15505 120, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_dsub_2_in_DPR_8 15506 120, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_2_in_DPR_8 15507 120, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8 15508 120, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8 15509 120, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_2_in_DPR_8 15510 120, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8 15511 120, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8 15512 120, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8 15513 120, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8 15514 120, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8 15515 120, // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_2_in_DPR_8 15516 120, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_dsub_2_in_DPR_8 15517 120, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8 15518 120, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8 15519 120, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8 15520 120, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8 15521 120, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8 15522 120, // dsub_5_dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8 15523 120, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8 15524 120, // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8 15525 120, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_dsub_2_in_DPR_8 15526 }, 15527 { // QQQQPR_with_dsub_4_in_DPR_8 15528 121, // dsub_0 -> QQQQPR_with_dsub_4_in_DPR_8 15529 121, // dsub_1 -> QQQQPR_with_dsub_4_in_DPR_8 15530 121, // dsub_2 -> QQQQPR_with_dsub_4_in_DPR_8 15531 121, // dsub_3 -> QQQQPR_with_dsub_4_in_DPR_8 15532 121, // dsub_4 -> QQQQPR_with_dsub_4_in_DPR_8 15533 121, // dsub_5 -> QQQQPR_with_dsub_4_in_DPR_8 15534 121, // dsub_6 -> QQQQPR_with_dsub_4_in_DPR_8 15535 121, // dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8 15536 0, // gsub_0 15537 0, // gsub_1 15538 121, // qqsub_0 -> QQQQPR_with_dsub_4_in_DPR_8 15539 121, // qqsub_1 -> QQQQPR_with_dsub_4_in_DPR_8 15540 121, // qsub_0 -> QQQQPR_with_dsub_4_in_DPR_8 15541 121, // qsub_1 -> QQQQPR_with_dsub_4_in_DPR_8 15542 121, // qsub_2 -> QQQQPR_with_dsub_4_in_DPR_8 15543 121, // qsub_3 -> QQQQPR_with_dsub_4_in_DPR_8 15544 121, // ssub_0 -> QQQQPR_with_dsub_4_in_DPR_8 15545 121, // ssub_1 -> QQQQPR_with_dsub_4_in_DPR_8 15546 121, // ssub_2 -> QQQQPR_with_dsub_4_in_DPR_8 15547 121, // ssub_3 -> QQQQPR_with_dsub_4_in_DPR_8 15548 121, // ssub_4 -> QQQQPR_with_dsub_4_in_DPR_8 15549 121, // ssub_5 -> QQQQPR_with_dsub_4_in_DPR_8 15550 121, // ssub_6 -> QQQQPR_with_dsub_4_in_DPR_8 15551 121, // ssub_7 -> QQQQPR_with_dsub_4_in_DPR_8 15552 121, // ssub_8 -> QQQQPR_with_dsub_4_in_DPR_8 15553 121, // ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8 15554 121, // ssub_10 -> QQQQPR_with_dsub_4_in_DPR_8 15555 121, // ssub_11 -> QQQQPR_with_dsub_4_in_DPR_8 15556 121, // ssub_12 -> QQQQPR_with_dsub_4_in_DPR_8 15557 121, // ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8 15558 121, // dsub_7_then_ssub_0 -> QQQQPR_with_dsub_4_in_DPR_8 15559 121, // dsub_7_then_ssub_1 -> QQQQPR_with_dsub_4_in_DPR_8 15560 121, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_dsub_4_in_DPR_8 15561 121, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_4_in_DPR_8 15562 121, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_dsub_4_in_DPR_8 15563 121, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_dsub_4_in_DPR_8 15564 121, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_4_in_DPR_8 15565 121, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8 15566 121, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8 15567 121, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_4_in_DPR_8 15568 121, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8 15569 121, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8 15570 121, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8 15571 121, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8 15572 121, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8 15573 121, // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_4_in_DPR_8 15574 121, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_dsub_4_in_DPR_8 15575 121, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8 15576 121, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8 15577 121, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8 15578 121, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8 15579 121, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8 15580 121, // dsub_5_dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8 15581 121, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8 15582 121, // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8 15583 121, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_dsub_4_in_DPR_8 15584 }, 15585 { // QQQQPR_with_dsub_6_in_DPR_8 15586 122, // dsub_0 -> QQQQPR_with_dsub_6_in_DPR_8 15587 122, // dsub_1 -> QQQQPR_with_dsub_6_in_DPR_8 15588 122, // dsub_2 -> QQQQPR_with_dsub_6_in_DPR_8 15589 122, // dsub_3 -> QQQQPR_with_dsub_6_in_DPR_8 15590 122, // dsub_4 -> QQQQPR_with_dsub_6_in_DPR_8 15591 122, // dsub_5 -> QQQQPR_with_dsub_6_in_DPR_8 15592 122, // dsub_6 -> QQQQPR_with_dsub_6_in_DPR_8 15593 122, // dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8 15594 0, // gsub_0 15595 0, // gsub_1 15596 122, // qqsub_0 -> QQQQPR_with_dsub_6_in_DPR_8 15597 122, // qqsub_1 -> QQQQPR_with_dsub_6_in_DPR_8 15598 122, // qsub_0 -> QQQQPR_with_dsub_6_in_DPR_8 15599 122, // qsub_1 -> QQQQPR_with_dsub_6_in_DPR_8 15600 122, // qsub_2 -> QQQQPR_with_dsub_6_in_DPR_8 15601 122, // qsub_3 -> QQQQPR_with_dsub_6_in_DPR_8 15602 122, // ssub_0 -> QQQQPR_with_dsub_6_in_DPR_8 15603 122, // ssub_1 -> QQQQPR_with_dsub_6_in_DPR_8 15604 122, // ssub_2 -> QQQQPR_with_dsub_6_in_DPR_8 15605 122, // ssub_3 -> QQQQPR_with_dsub_6_in_DPR_8 15606 122, // ssub_4 -> QQQQPR_with_dsub_6_in_DPR_8 15607 122, // ssub_5 -> QQQQPR_with_dsub_6_in_DPR_8 15608 122, // ssub_6 -> QQQQPR_with_dsub_6_in_DPR_8 15609 122, // ssub_7 -> QQQQPR_with_dsub_6_in_DPR_8 15610 122, // ssub_8 -> QQQQPR_with_dsub_6_in_DPR_8 15611 122, // ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8 15612 122, // ssub_10 -> QQQQPR_with_dsub_6_in_DPR_8 15613 122, // ssub_11 -> QQQQPR_with_dsub_6_in_DPR_8 15614 122, // ssub_12 -> QQQQPR_with_dsub_6_in_DPR_8 15615 122, // ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8 15616 122, // dsub_7_then_ssub_0 -> QQQQPR_with_dsub_6_in_DPR_8 15617 122, // dsub_7_then_ssub_1 -> QQQQPR_with_dsub_6_in_DPR_8 15618 122, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_dsub_6_in_DPR_8 15619 122, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_6_in_DPR_8 15620 122, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_dsub_6_in_DPR_8 15621 122, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_dsub_6_in_DPR_8 15622 122, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_6_in_DPR_8 15623 122, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8 15624 122, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8 15625 122, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_6_in_DPR_8 15626 122, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8 15627 122, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8 15628 122, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8 15629 122, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8 15630 122, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8 15631 122, // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_6_in_DPR_8 15632 122, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_dsub_6_in_DPR_8 15633 122, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8 15634 122, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8 15635 122, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8 15636 122, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8 15637 122, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8 15638 122, // dsub_5_dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8 15639 122, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8 15640 122, // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8 15641 122, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_dsub_6_in_DPR_8 15642 }, 15643 }; 15644 assert(RC && "Missing regclass"); 15645 if (!Idx) return RC; 15646 --Idx; 15647 assert(Idx < 56 && "Bad subreg"); 15648 unsigned TV = Table[RC->getID()][Idx]; 15649 return TV ? getRegClass(TV - 1) : nullptr; 15650} 15651 15652/// Get the weight in units of pressure for this register class. 15653const RegClassWeight &ARMGenRegisterInfo:: 15654getRegClassWeight(const TargetRegisterClass *RC) const { 15655 static const RegClassWeight RCWeightTable[] = { 15656 {1, 32}, // HPR 15657 {1, 65}, // FPWithVPR 15658 {1, 32}, // SPR 15659 {2, 32}, // FPWithVPR_with_ssub_0 15660 {1, 16}, // GPR 15661 {1, 16}, // GPRwithAPSR 15662 {1, 16}, // GPRwithZR 15663 {1, 16}, // SPR_8 15664 {1, 15}, // GPRnopc 15665 {0, 14}, // GPRwithAPSRnosp 15666 {1, 15}, // GPRwithZRnosp 15667 {1, 14}, // rGPR 15668 {1, 9}, // tGPRwithpc 15669 {2, 16}, // FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 15670 {1, 8}, // hGPR 15671 {1, 8}, // tGPR 15672 {1, 8}, // tGPREven 15673 {1, 7}, // GPRnopc_and_hGPR 15674 {1, 6}, // GPRwithAPSRnosp_and_hGPR 15675 {1, 6}, // tGPROdd 15676 {1, 5}, // tcGPR 15677 {1, 4}, // hGPR_and_tGPREven 15678 {1, 4}, // tGPR_and_tGPREven 15679 {1, 4}, // tGPR_and_tGPROdd 15680 {1, 4}, // tGPR_and_tcGPR 15681 {1, 3}, // tGPREven_and_tcGPR 15682 {1, 2}, // hGPR_and_tGPROdd 15683 {1, 2}, // tGPREven_and_tGPR_and_tcGPR 15684 {1, 2}, // tGPROdd_and_tcGPR 15685 {0, 0}, // CCR 15686 {1, 1}, // GPRlr 15687 {1, 1}, // GPRsp 15688 {1, 1}, // VCCR 15689 {1, 1}, // cl_FPSCR_NZCV 15690 {1, 1}, // hGPR_and_tGPRwithpc 15691 {1, 1}, // hGPR_and_tcGPR 15692 {2, 64}, // DPR 15693 {2, 32}, // DPR_VFP2 15694 {2, 16}, // DPR_8 15695 {2, 14}, // GPRPair 15696 {2, 12}, // GPRPairnosp 15697 {2, 8}, // GPRPair_with_gsub_0_in_tGPR 15698 {2, 6}, // GPRPair_with_gsub_0_in_hGPR 15699 {2, 6}, // GPRPair_with_gsub_0_in_tcGPR 15700 {2, 4}, // GPRPair_with_gsub_1_in_tcGPR 15701 {2, 4}, // GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR 15702 {2, 2}, // GPRPair_with_gsub_1_in_GPRsp 15703 {4, 64}, // DPairSpc 15704 {4, 36}, // DPairSpc_with_ssub_0 15705 {4, 32}, // DPairSpc_with_ssub_4 15706 {4, 20}, // DPairSpc_with_dsub_0_in_DPR_8 15707 {4, 16}, // DPairSpc_with_dsub_2_in_DPR_8 15708 {4, 64}, // DPair 15709 {4, 34}, // DPair_with_ssub_0 15710 {4, 64}, // QPR 15711 {4, 32}, // DPair_with_ssub_2 15712 {4, 18}, // DPair_with_dsub_0_in_DPR_8 15713 {4, 32}, // MQPR 15714 {4, 32}, // QPR_VFP2 15715 {4, 16}, // DPair_with_dsub_1_in_DPR_8 15716 {4, 16}, // QPR_8 15717 {6, 64}, // DTriple 15718 {6, 64}, // DTripleSpc 15719 {6, 40}, // DTripleSpc_with_ssub_0 15720 {6, 36}, // DTriple_with_ssub_0 15721 {6, 62}, // DTriple_with_qsub_0_in_QPR 15722 {6, 34}, // DTriple_with_ssub_2 15723 {6, 62}, // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 15724 {6, 36}, // DTripleSpc_with_ssub_4 15725 {6, 32}, // DTriple_with_ssub_4 15726 {6, 32}, // DTripleSpc_with_ssub_8 15727 {6, 24}, // DTripleSpc_with_dsub_0_in_DPR_8 15728 {6, 20}, // DTriple_with_dsub_0_in_DPR_8 15729 {6, 34}, // DTriple_with_qsub_0_in_MQPR 15730 {6, 34}, // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 15731 {6, 18}, // DTriple_with_dsub_1_in_DPR_8 15732 {6, 30}, // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15733 {6, 30}, // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR 15734 {6, 20}, // DTripleSpc_with_dsub_2_in_DPR_8 15735 {6, 16}, // DTriple_with_dsub_2_in_DPR_8 15736 {6, 16}, // DTripleSpc_with_dsub_4_in_DPR_8 15737 {6, 18}, // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15738 {6, 18}, // DTriple_with_qsub_0_in_QPR_8 15739 {6, 14}, // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR 15740 {6, 14}, // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 15741 {6, 64}, // DQuadSpc 15742 {6, 40}, // DQuadSpc_with_ssub_0 15743 {6, 36}, // DQuadSpc_with_ssub_4 15744 {6, 32}, // DQuadSpc_with_ssub_8 15745 {6, 24}, // DQuadSpc_with_dsub_0_in_DPR_8 15746 {6, 20}, // DQuadSpc_with_dsub_2_in_DPR_8 15747 {6, 16}, // DQuadSpc_with_dsub_4_in_DPR_8 15748 {8, 64}, // DQuad 15749 {8, 38}, // DQuad_with_ssub_0 15750 {8, 36}, // DQuad_with_ssub_2 15751 {8, 64}, // QQPR 15752 {8, 60}, // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 15753 {8, 34}, // DQuad_with_ssub_4 15754 {8, 32}, // DQuad_with_ssub_6 15755 {8, 22}, // DQuad_with_dsub_0_in_DPR_8 15756 {8, 36}, // DQuad_with_qsub_0_in_MQPR 15757 {8, 36}, // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 15758 {8, 20}, // DQuad_with_dsub_1_in_DPR_8 15759 {8, 32}, // DQuad_with_qsub_1_in_MQPR 15760 {8, 32}, // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15761 {8, 18}, // DQuad_with_dsub_2_in_DPR_8 15762 {8, 28}, // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15763 {8, 16}, // DQuad_with_dsub_3_in_DPR_8 15764 {8, 20}, // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15765 {8, 20}, // DQuad_with_qsub_0_in_QPR_8 15766 {8, 16}, // DQuad_with_qsub_1_in_QPR_8 15767 {8, 16}, // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 15768 {8, 12}, // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15769 {16, 64}, // QQQQPR 15770 {16, 44}, // QQQQPR_with_ssub_0 15771 {16, 40}, // QQQQPR_with_ssub_4 15772 {16, 36}, // QQQQPR_with_ssub_8 15773 {16, 32}, // QQQQPR_with_ssub_12 15774 {16, 28}, // QQQQPR_with_dsub_0_in_DPR_8 15775 {16, 24}, // QQQQPR_with_dsub_2_in_DPR_8 15776 {16, 20}, // QQQQPR_with_dsub_4_in_DPR_8 15777 {16, 16}, // QQQQPR_with_dsub_6_in_DPR_8 15778 }; 15779 return RCWeightTable[RC->getID()]; 15780} 15781 15782/// Get the weight in units of pressure for this register unit. 15783unsigned ARMGenRegisterInfo:: 15784getRegUnitWeight(unsigned RegUnit) const { 15785 assert(RegUnit < 83 && "invalid register unit"); 15786 static const uint8_t RUWeightTable[] = { 15787 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; 15788 return RUWeightTable[RegUnit]; 15789} 15790 15791 15792// Get the number of dimensions of register pressure. 15793unsigned ARMGenRegisterInfo::getNumRegPressureSets() const { 15794 return 34; 15795} 15796 15797// Get the name of this register unit pressure set. 15798const char *ARMGenRegisterInfo:: 15799getRegPressureSetName(unsigned Idx) const { 15800 static const char *const PressureNameTable[] = { 15801 "GPRlr", 15802 "VCCR", 15803 "cl_FPSCR_NZCV", 15804 "hGPR_and_tGPRwithpc", 15805 "GPRsp", 15806 "tGPR_and_tGPREven", 15807 "tGPROdd", 15808 "hGPR", 15809 "tcGPR", 15810 "tGPROdd+tcGPR", 15811 "tGPR", 15812 "tGPR+tcGPR", 15813 "tGPREven", 15814 "hGPR+tGPREven", 15815 "hGPR+tGPROdd", 15816 "hGPR+tcGPR", 15817 "tGPR+tGPREven", 15818 "GPR", 15819 "GPRwithZR", 15820 "GPRwithAPSR+GPRwithZR", 15821 "DQuad_with_dsub_0_in_DPR_8", 15822 "DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR", 15823 "HPR", 15824 "DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR", 15825 "DPair_with_ssub_0", 15826 "DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR", 15827 "DPairSpc_with_ssub_0", 15828 "DQuad_with_ssub_0", 15829 "DTripleSpc_with_ssub_0", 15830 "QQQQPR_with_ssub_0", 15831 "DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR", 15832 "DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR", 15833 "DTriple_with_qsub_0_in_QPR", 15834 "DPR", 15835 }; 15836 return PressureNameTable[Idx]; 15837} 15838 15839// Get the register unit pressure limit for this dimension. 15840// This limit must be adjusted dynamically for reserved registers. 15841unsigned ARMGenRegisterInfo:: 15842getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const { 15843 static const uint8_t PressureLimitTable[] = { 15844 1, // 0: GPRlr 15845 1, // 1: VCCR 15846 1, // 2: cl_FPSCR_NZCV 15847 1, // 3: hGPR_and_tGPRwithpc 15848 2, // 4: GPRsp 15849 4, // 5: tGPR_and_tGPREven 15850 6, // 6: tGPROdd 15851 8, // 7: hGPR 15852 8, // 8: tcGPR 15853 10, // 9: tGPROdd+tcGPR 15854 11, // 10: tGPR 15855 11, // 11: tGPR+tcGPR 15856 11, // 12: tGPREven 15857 12, // 13: hGPR+tGPREven 15858 12, // 14: hGPR+tGPROdd 15859 12, // 15: hGPR+tcGPR 15860 13, // 16: tGPR+tGPREven 15861 17, // 17: GPR 15862 17, // 18: GPRwithZR 15863 17, // 19: GPRwithAPSR+GPRwithZR 15864 24, // 20: DQuad_with_dsub_0_in_DPR_8 15865 32, // 21: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR 15866 32, // 22: HPR 15867 34, // 23: DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 15868 34, // 24: DPair_with_ssub_0 15869 36, // 25: DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 15870 36, // 26: DPairSpc_with_ssub_0 15871 38, // 27: DQuad_with_ssub_0 15872 40, // 28: DTripleSpc_with_ssub_0 15873 44, // 29: QQQQPR_with_ssub_0 15874 60, // 30: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 15875 62, // 31: DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR 15876 62, // 32: DTriple_with_qsub_0_in_QPR 15877 64, // 33: DPR 15878 }; 15879 return PressureLimitTable[Idx]; 15880} 15881 15882/// Table of pressure sets per register class or unit. 15883static const int RCSetsTable[] = { 15884 /* 0 */ 1, -1, 15885 /* 2 */ 2, -1, 15886 /* 4 */ 7, 13, 14, 15, 17, 18, -1, 15887 /* 11 */ 10, 11, 16, 17, 18, -1, 15888 /* 17 */ 3, 7, 10, 11, 13, 14, 15, 16, 17, 18, -1, 15889 /* 28 */ 17, 19, -1, 15890 /* 31 */ 6, 9, 10, 14, 17, 18, 19, -1, 15891 /* 39 */ 8, 9, 11, 12, 15, 17, 18, 19, -1, 15892 /* 48 */ 7, 13, 14, 15, 17, 18, 19, -1, 15893 /* 56 */ 6, 7, 9, 10, 13, 14, 15, 17, 18, 19, -1, 15894 /* 67 */ 4, 7, 8, 9, 11, 12, 13, 14, 15, 17, 18, 19, -1, 15895 /* 80 */ 10, 11, 16, 17, 18, 19, -1, 15896 /* 87 */ 5, 8, 10, 11, 12, 13, 16, 17, 18, 19, -1, 15897 /* 98 */ 6, 9, 10, 11, 14, 16, 17, 18, 19, -1, 15898 /* 108 */ 8, 9, 11, 12, 15, 16, 17, 18, 19, -1, 15899 /* 118 */ 8, 9, 10, 11, 12, 15, 16, 17, 18, 19, -1, 15900 /* 129 */ 8, 9, 11, 12, 13, 15, 16, 17, 18, 19, -1, 15901 /* 140 */ 5, 8, 9, 10, 11, 12, 13, 15, 16, 17, 18, 19, -1, 15902 /* 153 */ 6, 8, 9, 10, 11, 12, 14, 15, 16, 17, 18, 19, -1, 15903 /* 166 */ 0, 7, 12, 13, 14, 15, 16, 17, 18, 19, -1, 15904 /* 177 */ 4, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19, -1, 15905 /* 191 */ 31, 33, -1, 15906 /* 194 */ 20, 22, 24, 26, 27, 28, 29, 32, 33, -1, 15907 /* 204 */ 25, 27, 28, 29, 30, 31, 32, 33, -1, 15908 /* 213 */ 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, -1, 15909 /* 224 */ 21, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, -1, 15910 /* 237 */ 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, -1, 15911}; 15912 15913/// Get the dimensions of register pressure impacted by this register class. 15914/// Returns a -1 terminated array of pressure set IDs 15915const int* ARMGenRegisterInfo:: 15916getRegClassPressureSets(const TargetRegisterClass *RC) const { 15917 static const uint8_t RCSetStartTable[] = { 15918 195,1,195,1,8,28,36,194,35,1,36,35,11,1,4,80,91,48,48,31,108,167,87,98,118,129,56,140,153,1,166,67,0,2,17,177,192,195,194,35,35,80,48,39,118,48,67,192,197,195,194,194,192,196,192,195,194,195,195,194,194,192,192,199,197,201,196,191,197,195,195,194,194,196,213,194,238,195,194,194,194,237,194,194,237,192,199,197,195,194,194,194,192,198,197,192,208,196,195,194,197,204,194,195,224,194,238,194,237,194,194,237,237,192,200,199,197,195,195,194,194,194,}; 15919 return &RCSetsTable[RCSetStartTable[RC->getID()]]; 15920} 15921 15922/// Get the dimensions of register pressure impacted by this register unit. 15923/// Returns a -1 terminated array of pressure set IDs 15924const int* ARMGenRegisterInfo:: 15925getRegUnitPressureSets(unsigned RegUnit) const { 15926 assert(RegUnit < 83 && "invalid register unit"); 15927 static const uint8_t RUSetStartTable[] = { 15928 1,28,1,1,1,1,1,2,1,1,1,166,17,67,1,0,36,194,194,237,237,237,237,237,237,237,237,237,237,237,237,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,224,213,204,206,207,207,208,208,208,208,208,208,208,208,208,191,1,1,1,1,1,140,153,140,153,87,98,87,98,167,56,167,56,177,}; 15929 return &RCSetsTable[RUSetStartTable[RegUnit]]; 15930} 15931 15932extern const MCRegisterDesc ARMRegDesc[]; 15933extern const MCPhysReg ARMRegDiffLists[]; 15934extern const LaneBitmask ARMLaneMaskLists[]; 15935extern const char ARMRegStrings[]; 15936extern const char ARMRegClassStrings[]; 15937extern const MCPhysReg ARMRegUnitRoots[][2]; 15938extern const uint16_t ARMSubRegIdxLists[]; 15939extern const MCRegisterInfo::SubRegCoveredBits ARMSubRegIdxRanges[]; 15940extern const uint16_t ARMRegEncodingTable[]; 15941// ARM Dwarf<->LLVM register mappings. 15942extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0Dwarf2L[]; 15943extern const unsigned ARMDwarfFlavour0Dwarf2LSize; 15944 15945extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0Dwarf2L[]; 15946extern const unsigned ARMEHFlavour0Dwarf2LSize; 15947 15948extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0L2Dwarf[]; 15949extern const unsigned ARMDwarfFlavour0L2DwarfSize; 15950 15951extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0L2Dwarf[]; 15952extern const unsigned ARMEHFlavour0L2DwarfSize; 15953 15954ARMGenRegisterInfo:: 15955ARMGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, 15956 unsigned PC, unsigned HwMode) 15957 : TargetRegisterInfo(ARMRegInfoDesc, RegisterClasses, RegisterClasses+122, 15958 SubRegIndexNameTable, SubRegIndexLaneMaskTable, 15959 LaneBitmask(0xFFFFFFFF), RegClassInfos, HwMode) { 15960 InitMCRegisterInfo(ARMRegDesc, 295, RA, PC, 15961 ARMMCRegisterClasses, 122, 15962 ARMRegUnitRoots, 15963 83, 15964 ARMRegDiffLists, 15965 ARMLaneMaskLists, 15966 ARMRegStrings, 15967 ARMRegClassStrings, 15968 ARMSubRegIdxLists, 15969 57, 15970 ARMSubRegIdxRanges, 15971 ARMRegEncodingTable); 15972 15973 switch (DwarfFlavour) { 15974 default: 15975 llvm_unreachable("Unknown DWARF flavour"); 15976 case 0: 15977 mapDwarfRegsToLLVMRegs(ARMDwarfFlavour0Dwarf2L, ARMDwarfFlavour0Dwarf2LSize, false); 15978 break; 15979 } 15980 switch (EHFlavour) { 15981 default: 15982 llvm_unreachable("Unknown DWARF flavour"); 15983 case 0: 15984 mapDwarfRegsToLLVMRegs(ARMEHFlavour0Dwarf2L, ARMEHFlavour0Dwarf2LSize, true); 15985 break; 15986 } 15987 switch (DwarfFlavour) { 15988 default: 15989 llvm_unreachable("Unknown DWARF flavour"); 15990 case 0: 15991 mapLLVMRegsToDwarfRegs(ARMDwarfFlavour0L2Dwarf, ARMDwarfFlavour0L2DwarfSize, false); 15992 break; 15993 } 15994 switch (EHFlavour) { 15995 default: 15996 llvm_unreachable("Unknown DWARF flavour"); 15997 case 0: 15998 mapLLVMRegsToDwarfRegs(ARMEHFlavour0L2Dwarf, ARMEHFlavour0L2DwarfSize, true); 15999 break; 16000 } 16001} 16002 16003static const MCPhysReg CSR_AAPCS_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 }; 16004static const uint32_t CSR_AAPCS_RegMask[] = { 0xf8002000, 0xf0000007, 0x000ff000, 0xe01fffe0, 0x03800007, 0xc01e0040, 0xf000000f, 0x03000000, 0x6001c000, 0x00000000, }; 16005static const MCPhysReg CSR_AAPCS_SplitPush_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 }; 16006static const uint32_t CSR_AAPCS_SplitPush_RegMask[] = { 0xf8002000, 0xf0000007, 0x000ff000, 0xe01fffe0, 0x03800007, 0xc01e0040, 0xf000000f, 0x03000000, 0x6001c000, 0x00000000, }; 16007static const MCPhysReg CSR_AAPCS_SplitPush_SwiftError_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R9, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 }; 16008static const uint32_t CSR_AAPCS_SplitPush_SwiftError_RegMask[] = { 0xf8002000, 0xf0000007, 0x000ef000, 0xe01fffe0, 0x03800007, 0xc0160040, 0xf000000f, 0x03000000, 0x6001c000, 0x00000000, }; 16009static const MCPhysReg CSR_AAPCS_SwiftError_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 }; 16010static const uint32_t CSR_AAPCS_SwiftError_RegMask[] = { 0xf8002000, 0xf0000007, 0x000ef000, 0xe01fffe0, 0x03800007, 0xc0160040, 0xf000000f, 0x03000000, 0x6001c000, 0x00000000, }; 16011static const MCPhysReg CSR_AAPCS_ThisReturn_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R0, 0 }; 16012static const uint32_t CSR_AAPCS_ThisReturn_RegMask[] = { 0xf8002000, 0xf0000007, 0x000ff100, 0xe01fffe0, 0x03800007, 0xc01e0040, 0xf000000f, 0x03000000, 0x6001c000, 0x00000000, }; 16013static const MCPhysReg CSR_FIQ_SaveList[] = { ARM::LR, ARM::R11, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::R0, 0 }; 16014static const uint32_t CSR_FIQ_RegMask[] = { 0x00002000, 0x00000000, 0x0008ff00, 0x00000000, 0x00000000, 0x00078000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; 16015static const MCPhysReg CSR_FPRegs_SaveList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, 0 }; 16016static const uint32_t CSR_FPRegs_RegMask[] = { 0xfff80000, 0xff07ffff, 0xffe000ff, 0xffffffff, 0xffffffff, 0xffc07fff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0000007f, }; 16017static const MCPhysReg CSR_GenericInt_SaveList[] = { ARM::LR, ARM::R12, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::R0, 0 }; 16018static const uint32_t CSR_GenericInt_RegMask[] = { 0x00002000, 0x00000000, 0x001fff00, 0x00000000, 0x00000000, 0x001f8000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; 16019static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 }; 16020static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; 16021static const MCPhysReg CSR_Win_AAPCS_CFGuard_Check_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 }; 16022static const uint32_t CSR_Win_AAPCS_CFGuard_Check_RegMask[] = { 0xfff82000, 0xff000007, 0xffeff000, 0xffffffff, 0x03f80007, 0xffde007c, 0xfff0000f, 0x03ff0000, 0x7e01fc00, 0x00000000, }; 16023static const MCPhysReg CSR_iOS_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 }; 16024static const uint32_t CSR_iOS_RegMask[] = { 0xf8002000, 0xf0000007, 0x000df000, 0xe01fffe0, 0x03800007, 0xc0160040, 0xf000000f, 0x03000000, 0x6001c000, 0x00000000, }; 16025static const MCPhysReg CSR_iOS_CXX_TLS_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R12, ARM::R9, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 }; 16026static const uint32_t CSR_iOS_CXX_TLS_RegMask[] = { 0xfff82000, 0xff07ffff, 0xfffffeff, 0xffffffff, 0xffffffff, 0xffdf7fff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0000007f, }; 16027static const MCPhysReg CSR_iOS_CXX_TLS_PE_SaveList[] = { ARM::LR, ARM::R12, ARM::R11, ARM::R7, ARM::R5, ARM::R4, 0 }; 16028static const uint32_t CSR_iOS_CXX_TLS_PE_RegMask[] = { 0x00002000, 0x00000000, 0x0018b000, 0x00000000, 0x00000000, 0x00020000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; 16029static const MCPhysReg CSR_iOS_CXX_TLS_ViaCopy_SaveList[] = { ARM::R6, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R9, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 }; 16030static const uint32_t CSR_iOS_CXX_TLS_ViaCopy_RegMask[] = { 0xfff80000, 0xff07ffff, 0xffe74eff, 0xffffffff, 0xffffffff, 0xffc97fff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0000007f, }; 16031static const MCPhysReg CSR_iOS_SwiftError_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 }; 16032static const uint32_t CSR_iOS_SwiftError_RegMask[] = { 0xf8002000, 0xf0000007, 0x000cf000, 0xe01fffe0, 0x03800007, 0xc0160040, 0xf000000f, 0x03000000, 0x6001c000, 0x00000000, }; 16033static const MCPhysReg CSR_iOS_TLSCall_SaveList[] = { ARM::LR, ARM::SP, ARM::R11, ARM::R10, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 }; 16034static const uint32_t CSR_iOS_TLSCall_RegMask[] = { 0xfff8a000, 0xff07ffff, 0xffedfeff, 0xffffffff, 0xffffffff, 0xffd77fff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0000007f, }; 16035static const MCPhysReg CSR_iOS_ThisReturn_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R0, 0 }; 16036static const uint32_t CSR_iOS_ThisReturn_RegMask[] = { 0xf8002000, 0xf0000007, 0x000df100, 0xe01fffe0, 0x03800007, 0xc0160040, 0xf000000f, 0x03000000, 0x6001c000, 0x00000000, }; 16037 16038 16039ArrayRef<const uint32_t *> ARMGenRegisterInfo::getRegMasks() const { 16040 static const uint32_t *const Masks[] = { 16041 CSR_AAPCS_RegMask, 16042 CSR_AAPCS_SplitPush_RegMask, 16043 CSR_AAPCS_SplitPush_SwiftError_RegMask, 16044 CSR_AAPCS_SwiftError_RegMask, 16045 CSR_AAPCS_ThisReturn_RegMask, 16046 CSR_FIQ_RegMask, 16047 CSR_FPRegs_RegMask, 16048 CSR_GenericInt_RegMask, 16049 CSR_NoRegs_RegMask, 16050 CSR_Win_AAPCS_CFGuard_Check_RegMask, 16051 CSR_iOS_RegMask, 16052 CSR_iOS_CXX_TLS_RegMask, 16053 CSR_iOS_CXX_TLS_PE_RegMask, 16054 CSR_iOS_CXX_TLS_ViaCopy_RegMask, 16055 CSR_iOS_SwiftError_RegMask, 16056 CSR_iOS_TLSCall_RegMask, 16057 CSR_iOS_ThisReturn_RegMask, 16058 }; 16059 return makeArrayRef(Masks); 16060} 16061 16062ArrayRef<const char *> ARMGenRegisterInfo::getRegMaskNames() const { 16063 static const char *const Names[] = { 16064 "CSR_AAPCS", 16065 "CSR_AAPCS_SplitPush", 16066 "CSR_AAPCS_SplitPush_SwiftError", 16067 "CSR_AAPCS_SwiftError", 16068 "CSR_AAPCS_ThisReturn", 16069 "CSR_FIQ", 16070 "CSR_FPRegs", 16071 "CSR_GenericInt", 16072 "CSR_NoRegs", 16073 "CSR_Win_AAPCS_CFGuard_Check", 16074 "CSR_iOS", 16075 "CSR_iOS_CXX_TLS", 16076 "CSR_iOS_CXX_TLS_PE", 16077 "CSR_iOS_CXX_TLS_ViaCopy", 16078 "CSR_iOS_SwiftError", 16079 "CSR_iOS_TLSCall", 16080 "CSR_iOS_ThisReturn", 16081 }; 16082 return makeArrayRef(Names); 16083} 16084 16085const ARMFrameLowering * 16086ARMGenRegisterInfo::getFrameLowering(const MachineFunction &MF) { 16087 return static_cast<const ARMFrameLowering *>( 16088 MF.getSubtarget().getFrameLowering()); 16089} 16090 16091} // end namespace llvm 16092 16093#endif // GET_REGINFO_TARGET_DESC 16094 16095