1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Subtarget Enumeration Source Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10#ifdef GET_SUBTARGETINFO_ENUM 11#undef GET_SUBTARGETINFO_ENUM 12 13namespace llvm { 14namespace RISCV { 15enum { 16 Feature64Bit = 0, 17 FeatureRV32E = 1, 18 FeatureRVCHints = 2, 19 FeatureRelax = 3, 20 FeatureReserveX1 = 4, 21 FeatureReserveX2 = 5, 22 FeatureReserveX3 = 6, 23 FeatureReserveX4 = 7, 24 FeatureReserveX5 = 8, 25 FeatureReserveX6 = 9, 26 FeatureReserveX7 = 10, 27 FeatureReserveX8 = 11, 28 FeatureReserveX9 = 12, 29 FeatureReserveX10 = 13, 30 FeatureReserveX11 = 14, 31 FeatureReserveX12 = 15, 32 FeatureReserveX13 = 16, 33 FeatureReserveX14 = 17, 34 FeatureReserveX15 = 18, 35 FeatureReserveX16 = 19, 36 FeatureReserveX17 = 20, 37 FeatureReserveX18 = 21, 38 FeatureReserveX19 = 22, 39 FeatureReserveX20 = 23, 40 FeatureReserveX21 = 24, 41 FeatureReserveX22 = 25, 42 FeatureReserveX23 = 26, 43 FeatureReserveX24 = 27, 44 FeatureReserveX25 = 28, 45 FeatureReserveX26 = 29, 46 FeatureReserveX27 = 30, 47 FeatureReserveX28 = 31, 48 FeatureReserveX29 = 32, 49 FeatureReserveX30 = 33, 50 FeatureReserveX31 = 34, 51 FeatureStdExtA = 35, 52 FeatureStdExtC = 36, 53 FeatureStdExtD = 37, 54 FeatureStdExtF = 38, 55 FeatureStdExtM = 39, 56 NumSubtargetFeatures = 40 57}; 58} // end namespace RISCV 59} // end namespace llvm 60 61#endif // GET_SUBTARGETINFO_ENUM 62 63 64#ifdef GET_SUBTARGETINFO_MC_DESC 65#undef GET_SUBTARGETINFO_MC_DESC 66 67namespace llvm { 68// Sorted (by key) array of values for CPU features. 69extern const llvm::SubtargetFeatureKV RISCVFeatureKV[] = { 70 { "64bit", "Implements RV64", RISCV::Feature64Bit, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 71 { "a", "'A' (Atomic Instructions)", RISCV::FeatureStdExtA, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 72 { "c", "'C' (Compressed Instructions)", RISCV::FeatureStdExtC, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 73 { "d", "'D' (Double-Precision Floating-Point)", RISCV::FeatureStdExtD, { { { 0x4000000000ULL, 0x0ULL, 0x0ULL, } } } }, 74 { "e", "Implements RV32E (provides 16 rather than 32 GPRs)", RISCV::FeatureRV32E, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 75 { "f", "'F' (Single-Precision Floating-Point)", RISCV::FeatureStdExtF, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 76 { "m", "'M' (Integer Multiplication and Division)", RISCV::FeatureStdExtM, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 77 { "relax", "Enable Linker relaxation.", RISCV::FeatureRelax, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 78 { "reserve-x1", "Reserve X1", RISCV::FeatureReserveX1, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 79 { "reserve-x10", "Reserve X10", RISCV::FeatureReserveX10, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 80 { "reserve-x11", "Reserve X11", RISCV::FeatureReserveX11, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 81 { "reserve-x12", "Reserve X12", RISCV::FeatureReserveX12, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 82 { "reserve-x13", "Reserve X13", RISCV::FeatureReserveX13, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 83 { "reserve-x14", "Reserve X14", RISCV::FeatureReserveX14, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 84 { "reserve-x15", "Reserve X15", RISCV::FeatureReserveX15, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 85 { "reserve-x16", "Reserve X16", RISCV::FeatureReserveX16, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 86 { "reserve-x17", "Reserve X17", RISCV::FeatureReserveX17, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 87 { "reserve-x18", "Reserve X18", RISCV::FeatureReserveX18, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 88 { "reserve-x19", "Reserve X19", RISCV::FeatureReserveX19, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 89 { "reserve-x2", "Reserve X2", RISCV::FeatureReserveX2, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 90 { "reserve-x20", "Reserve X20", RISCV::FeatureReserveX20, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 91 { "reserve-x21", "Reserve X21", RISCV::FeatureReserveX21, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 92 { "reserve-x22", "Reserve X22", RISCV::FeatureReserveX22, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 93 { "reserve-x23", "Reserve X23", RISCV::FeatureReserveX23, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 94 { "reserve-x24", "Reserve X24", RISCV::FeatureReserveX24, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 95 { "reserve-x25", "Reserve X25", RISCV::FeatureReserveX25, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 96 { "reserve-x26", "Reserve X26", RISCV::FeatureReserveX26, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 97 { "reserve-x27", "Reserve X27", RISCV::FeatureReserveX27, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 98 { "reserve-x28", "Reserve X28", RISCV::FeatureReserveX28, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 99 { "reserve-x29", "Reserve X29", RISCV::FeatureReserveX29, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 100 { "reserve-x3", "Reserve X3", RISCV::FeatureReserveX3, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 101 { "reserve-x30", "Reserve X30", RISCV::FeatureReserveX30, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 102 { "reserve-x31", "Reserve X31", RISCV::FeatureReserveX31, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 103 { "reserve-x4", "Reserve X4", RISCV::FeatureReserveX4, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 104 { "reserve-x5", "Reserve X5", RISCV::FeatureReserveX5, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 105 { "reserve-x6", "Reserve X6", RISCV::FeatureReserveX6, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 106 { "reserve-x7", "Reserve X7", RISCV::FeatureReserveX7, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 107 { "reserve-x8", "Reserve X8", RISCV::FeatureReserveX8, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 108 { "reserve-x9", "Reserve X9", RISCV::FeatureReserveX9, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 109 { "rvc-hints", "Enable RVC Hint Instructions.", RISCV::FeatureRVCHints, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 110}; 111 112#ifdef DBGFIELD 113#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro" 114#endif 115#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 116#define DBGFIELD(x) x, 117#else 118#define DBGFIELD(x) 119#endif 120 121// =============================================================== 122// Data tables for the new per-operand machine model. 123 124// {ProcResourceIdx, Cycles} 125extern const llvm::MCWriteProcResEntry RISCVWriteProcResTable[] = { 126 { 0, 0}, // Invalid 127 { 1, 1}, // #1 128 { 7, 1}, // #2 129 { 2, 1}, // #3 130 { 5, 34}, // #4 131 { 3, 1}, // #5 132 { 4, 20}, // #6 133 { 6, 1}, // #7 134 { 8, 1}, // #8 135 { 6, 33}, // #9 136 { 6, 34}, // #10 137 { 4, 1}, // #11 138 { 5, 20} // #12 139}; // RISCVWriteProcResTable 140 141// {Cycles, WriteResourceID} 142extern const llvm::MCWriteLatencyEntry RISCVWriteLatencyTable[] = { 143 { 0, 0}, // Invalid 144 { 1, 0}, // #1 WriteIALU_WriteJmp_WriteFST64_WriteFST32_WriteJal_WriteJalr_WriteJmpReg_WriteNop_WriteShift_WriteSTW_WriteSTB_WriteAtomicSTW_WriteSTH_WriteIALU32_WriteSTD_WriteAtomicSTD_WriteShift32 145 { 2, 0}, // #2 WriteAtomicW_WriteFLD64_WriteFLD32_WriteLDW_WriteFClass64_WriteFClass32_WriteFCvtF32ToF64_WriteFCvtI32ToF64_WriteFCvtF64ToF32_WriteFCvtI32ToF32_WriteFCvtF64ToI32_WriteFCvtF32ToI32_WriteFCmp64_WriteFCmp32_WriteFMovI32ToF32_WriteFMovF32ToI32_WriteAtomicLDW_WriteAtomicD_WriteLDD_WriteFCvtI64ToF64_WriteFCvtF64ToI64_WriteFCvtF32ToI64_WriteFCvtI64ToF32_WriteFMovI64ToF64_WriteFMovF64ToI64_WriteAtomicLDD_WriteLDWU 146 { 3, 0}, // #3 WriteCSR_WriteLDB_WriteLDH 147 {34, 0}, // #4 WriteIDiv_WriteIDiv32 148 { 6, 0}, // #5 WriteFALU64 149 { 4, 0}, // #6 WriteFALU32_WriteIMul_WriteIMul32 150 {20, 0}, // #7 WriteFDiv32_WriteFSqrt32 151 { 7, 0}, // #8 WriteFMulAdd64_WriteFMulSub64 152 { 5, 0}, // #9 WriteFMulAdd32_WriteFMulSub32_WriteFMul32 153 {33, 0} // #10 WriteIDiv 154}; // RISCVWriteLatencyTable 155 156// {UseIdx, WriteResourceID, Cycles} 157extern const llvm::MCReadAdvanceEntry RISCVReadAdvanceTable[] = { 158 {0, 0, 0}, // Invalid 159 {0, 0, 0}, // #1 160 {1, 0, 0}, // #2 161 {0, 0, 0}, // #3 162 {1, 0, 0}, // #4 163 {2, 0, 0} // #5 164}; // RISCVReadAdvanceTable 165 166// {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#} 167static const llvm::MCSchedClassDesc Rocket32ModelSchedClasses[] = { 168 {DBGFIELD("InvalidSchedClass") 16383, false, false, 0, 0, 0, 0, 0, 0}, 169 {DBGFIELD("WriteIALU_ReadIALU_ReadIALU") 1, false, false, 1, 1, 1, 1, 1, 2}, // #1 170 {DBGFIELD("WriteIALU_ReadIALU") 1, false, false, 1, 1, 1, 1, 0, 1}, // #2 171 {DBGFIELD("WriteIALU32_ReadIALU32") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #3 172 {DBGFIELD("WriteIALU32_ReadIALU32_ReadIALU32") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #4 173 {DBGFIELD("WriteAtomicD_ReadAtomicDA_ReadAtomicDD") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #5 174 {DBGFIELD("WriteAtomicW_ReadAtomicWA_ReadAtomicWD") 1, false, false, 2, 1, 2, 1, 1, 2}, // #6 175 {DBGFIELD("WriteIALU") 1, false, false, 1, 1, 1, 1, 0, 0}, // #7 176 {DBGFIELD("WriteJmp") 1, false, false, 3, 1, 1, 1, 0, 0}, // #8 177 {DBGFIELD("WriteCSR_ReadCSR") 1, false, false, 1, 1, 3, 1, 0, 1}, // #9 178 {DBGFIELD("WriteCSR") 1, false, false, 1, 1, 3, 1, 0, 0}, // #10 179 {DBGFIELD("WriteFLD64_ReadMemBase") 1, false, false, 2, 1, 2, 1, 0, 1}, // #11 180 {DBGFIELD("WriteFLD32_ReadMemBase") 1, false, false, 2, 1, 2, 1, 0, 1}, // #12 181 {DBGFIELD("WriteFST64_ReadStoreData_ReadMemBase") 1, false, false, 2, 1, 1, 1, 1, 2}, // #13 182 {DBGFIELD("WriteFST32_ReadStoreData_ReadMemBase") 1, false, false, 2, 1, 1, 1, 1, 2}, // #14 183 {DBGFIELD("WriteJal") 1, false, false, 3, 1, 1, 1, 0, 0}, // #15 184 {DBGFIELD("WriteJalr_ReadJalr") 1, false, false, 3, 1, 1, 1, 0, 1}, // #16 185 {DBGFIELD("WriteJmpReg") 1, false, false, 3, 1, 1, 1, 0, 0}, // #17 186 {DBGFIELD("WriteLDD_ReadMemBase") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #18 187 {DBGFIELD("WriteLDW_ReadMemBase") 1, false, false, 2, 1, 2, 1, 0, 1}, // #19 188 {DBGFIELD("WriteNop") 1, false, false, 0, 0, 1, 1, 0, 0}, // #20 189 {DBGFIELD("WriteSTD_ReadStoreData_ReadMemBase") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #21 190 {DBGFIELD("WriteShift_ReadShift") 1, false, false, 1, 1, 1, 1, 0, 1}, // #22 191 {DBGFIELD("WriteSTW_ReadStoreData_ReadMemBase") 1, false, false, 2, 1, 1, 1, 1, 2}, // #23 192 {DBGFIELD("WriteIDiv_ReadIDiv_ReadIDiv") 1, false, false, 4, 1, 4, 1, 1, 2}, // #24 193 {DBGFIELD("WriteIDiv32_ReadIDiv32_ReadIDiv32") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #25 194 {DBGFIELD("WriteFALU64_ReadFALU64_ReadFALU64") 1, false, false, 5, 1, 5, 1, 1, 2}, // #26 195 {DBGFIELD("WriteFALU32_ReadFALU32_ReadFALU32") 1, false, false, 5, 1, 6, 1, 1, 2}, // #27 196 {DBGFIELD("WriteFClass64_ReadFClass64") 1, false, false, 5, 1, 2, 1, 0, 1}, // #28 197 {DBGFIELD("WriteFClass32_ReadFClass32") 1, false, false, 5, 1, 2, 1, 0, 1}, // #29 198 {DBGFIELD("WriteFCvtI64ToF64_ReadFCvtI64ToF64") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #30 199 {DBGFIELD("WriteFCvtF32ToF64_ReadFCvtF32ToF64") 1, false, false, 5, 1, 2, 1, 0, 1}, // #31 200 {DBGFIELD("WriteFCvtI32ToF64_ReadFCvtI32ToF64") 1, false, false, 5, 1, 2, 1, 0, 1}, // #32 201 {DBGFIELD("WriteFCvtF64ToI64_ReadFCvtF64ToI64") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #33 202 {DBGFIELD("WriteFCvtF32ToI64_ReadFCvtF32ToI64") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #34 203 {DBGFIELD("WriteFCvtF64ToF32_ReadFCvtF64ToF32") 1, false, false, 5, 1, 2, 1, 0, 1}, // #35 204 {DBGFIELD("WriteFCvtI64ToF32_ReadFCvtI64ToF32") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #36 205 {DBGFIELD("WriteFCvtI32ToF32_ReadFCvtI32ToF32") 1, false, false, 5, 1, 2, 1, 0, 1}, // #37 206 {DBGFIELD("WriteFCvtF64ToI32_ReadFCvtF64ToI32") 1, false, false, 5, 1, 2, 1, 0, 1}, // #38 207 {DBGFIELD("WriteFCvtF32ToI32_ReadFCvtF32ToI32") 1, false, false, 5, 1, 2, 1, 0, 1}, // #39 208 {DBGFIELD("WriteFDiv32_ReadFDiv32_ReadFDiv32") 1, false, false, 6, 1, 7, 1, 1, 2}, // #40 209 {DBGFIELD("WriteFCmp64_ReadFCmp64_ReadFCmp64") 1, false, false, 5, 1, 2, 1, 1, 2}, // #41 210 {DBGFIELD("WriteFCmp32_ReadFCmp32_ReadFCmp32") 1, false, false, 5, 1, 2, 1, 1, 2}, // #42 211 {DBGFIELD("WriteFMulAdd64_ReadFMulAdd64_ReadFMulAdd64_ReadFMulAdd64") 1, false, false, 5, 1, 8, 1, 3, 3}, // #43 212 {DBGFIELD("WriteFMulAdd32_ReadFMulAdd32_ReadFMulAdd32_ReadFMulAdd32") 1, false, false, 5, 1, 9, 1, 3, 3}, // #44 213 {DBGFIELD("WriteFMulSub64_ReadFMulSub64_ReadFMulSub64_ReadFMulSub64") 1, false, false, 5, 1, 8, 1, 3, 3}, // #45 214 {DBGFIELD("WriteFMulSub32_ReadFMulSub32_ReadFMulSub32_ReadFMulSub32") 1, false, false, 5, 1, 9, 1, 3, 3}, // #46 215 {DBGFIELD("WriteFMul32_ReadFMul32_ReadFMul32") 1, false, false, 5, 1, 9, 1, 1, 2}, // #47 216 {DBGFIELD("WriteFMovI64ToF64_ReadFMovI64ToF64") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #48 217 {DBGFIELD("WriteFMovI32ToF32_ReadFMovI32ToF32") 1, false, false, 5, 1, 2, 1, 0, 1}, // #49 218 {DBGFIELD("WriteFMovF64ToI64_ReadFMovF64ToI64") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #50 219 {DBGFIELD("WriteFMovF32ToI32_ReadFMovF32ToI32") 1, false, false, 5, 1, 2, 1, 0, 1}, // #51 220 {DBGFIELD("WriteFSqrt32_ReadFSqrt32") 1, false, false, 6, 1, 7, 1, 0, 1}, // #52 221 {DBGFIELD("WriteLDB_ReadMemBase") 1, false, false, 2, 1, 3, 1, 0, 1}, // #53 222 {DBGFIELD("WriteLDH_ReadMemBase") 1, false, false, 2, 1, 3, 1, 0, 1}, // #54 223 {DBGFIELD("WriteAtomicLDD_ReadAtomicLDD") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #55 224 {DBGFIELD("WriteAtomicLDW_ReadAtomicLDW") 1, false, false, 2, 1, 2, 1, 0, 1}, // #56 225 {DBGFIELD("WriteLDWU_ReadMemBase") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #57 226 {DBGFIELD("WriteIMul_ReadIMul_ReadIMul") 1, false, false, 7, 1, 6, 1, 1, 2}, // #58 227 {DBGFIELD("WriteIMul32_ReadIMul32_ReadIMul32") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #59 228 {DBGFIELD("WriteSTB_ReadStoreData_ReadMemBase") 1, false, false, 2, 1, 1, 1, 1, 2}, // #60 229 {DBGFIELD("WriteAtomicSTD_ReadAtomicSTD_ReadAtomicSTD") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #61 230 {DBGFIELD("WriteAtomicSTW_ReadAtomicSTW_ReadAtomicSTW") 1, false, false, 2, 1, 1, 1, 1, 2}, // #62 231 {DBGFIELD("WriteSTH_ReadStoreData_ReadMemBase") 1, false, false, 2, 1, 1, 1, 1, 2}, // #63 232 {DBGFIELD("WriteShift32_ReadShift32") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #64 233 {DBGFIELD("COPY") 1, false, false, 1, 1, 1, 1, 0, 0}, // #65 234}; // Rocket32ModelSchedClasses 235 236// {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#} 237static const llvm::MCSchedClassDesc Rocket64ModelSchedClasses[] = { 238 {DBGFIELD("InvalidSchedClass") 16383, false, false, 0, 0, 0, 0, 0, 0}, 239 {DBGFIELD("WriteIALU_ReadIALU_ReadIALU") 1, false, false, 3, 1, 1, 1, 1, 2}, // #1 240 {DBGFIELD("WriteIALU_ReadIALU") 1, false, false, 3, 1, 1, 1, 0, 1}, // #2 241 {DBGFIELD("WriteIALU32_ReadIALU32") 1, false, false, 3, 1, 1, 1, 0, 1}, // #3 242 {DBGFIELD("WriteIALU32_ReadIALU32_ReadIALU32") 1, false, false, 3, 1, 1, 1, 1, 2}, // #4 243 {DBGFIELD("WriteAtomicD_ReadAtomicDA_ReadAtomicDD") 1, false, false, 8, 1, 2, 1, 1, 2}, // #5 244 {DBGFIELD("WriteAtomicW_ReadAtomicWA_ReadAtomicWD") 1, false, false, 8, 1, 2, 1, 1, 2}, // #6 245 {DBGFIELD("WriteIALU") 1, false, false, 3, 1, 1, 1, 0, 0}, // #7 246 {DBGFIELD("WriteJmp") 1, false, false, 5, 1, 1, 1, 0, 0}, // #8 247 {DBGFIELD("WriteCSR_ReadCSR") 1, false, false, 3, 1, 3, 1, 0, 1}, // #9 248 {DBGFIELD("WriteCSR") 1, false, false, 3, 1, 3, 1, 0, 0}, // #10 249 {DBGFIELD("WriteFLD64_ReadMemBase") 1, false, false, 8, 1, 2, 1, 0, 1}, // #11 250 {DBGFIELD("WriteFLD32_ReadMemBase") 1, false, false, 8, 1, 2, 1, 0, 1}, // #12 251 {DBGFIELD("WriteFST64_ReadStoreData_ReadMemBase") 1, false, false, 8, 1, 1, 1, 1, 2}, // #13 252 {DBGFIELD("WriteFST32_ReadStoreData_ReadMemBase") 1, false, false, 8, 1, 1, 1, 1, 2}, // #14 253 {DBGFIELD("WriteJal") 1, false, false, 5, 1, 1, 1, 0, 0}, // #15 254 {DBGFIELD("WriteJalr_ReadJalr") 1, false, false, 5, 1, 1, 1, 0, 1}, // #16 255 {DBGFIELD("WriteJmpReg") 1, false, false, 5, 1, 1, 1, 0, 0}, // #17 256 {DBGFIELD("WriteLDD_ReadMemBase") 1, false, false, 8, 1, 2, 1, 0, 1}, // #18 257 {DBGFIELD("WriteLDW_ReadMemBase") 1, false, false, 8, 1, 2, 1, 0, 1}, // #19 258 {DBGFIELD("WriteNop") 1, false, false, 0, 0, 1, 1, 0, 0}, // #20 259 {DBGFIELD("WriteSTD_ReadStoreData_ReadMemBase") 1, false, false, 8, 1, 1, 1, 1, 2}, // #21 260 {DBGFIELD("WriteShift_ReadShift") 1, false, false, 3, 1, 1, 1, 0, 1}, // #22 261 {DBGFIELD("WriteSTW_ReadStoreData_ReadMemBase") 1, false, false, 8, 1, 1, 1, 1, 2}, // #23 262 {DBGFIELD("WriteIDiv_ReadIDiv_ReadIDiv") 1, false, false, 9, 1, 10, 1, 1, 2}, // #24 263 {DBGFIELD("WriteIDiv32_ReadIDiv32_ReadIDiv32") 1, false, false, 10, 1, 4, 1, 1, 2}, // #25 264 {DBGFIELD("WriteFALU64_ReadFALU64_ReadFALU64") 1, false, false, 11, 1, 5, 1, 1, 2}, // #26 265 {DBGFIELD("WriteFALU32_ReadFALU32_ReadFALU32") 1, false, false, 11, 1, 6, 1, 1, 2}, // #27 266 {DBGFIELD("WriteFClass64_ReadFClass64") 1, false, false, 11, 1, 2, 1, 0, 1}, // #28 267 {DBGFIELD("WriteFClass32_ReadFClass32") 1, false, false, 11, 1, 2, 1, 0, 1}, // #29 268 {DBGFIELD("WriteFCvtI64ToF64_ReadFCvtI64ToF64") 1, false, false, 1, 1, 2, 1, 0, 1}, // #30 269 {DBGFIELD("WriteFCvtF32ToF64_ReadFCvtF32ToF64") 1, false, false, 1, 1, 2, 1, 0, 1}, // #31 270 {DBGFIELD("WriteFCvtI32ToF64_ReadFCvtI32ToF64") 1, false, false, 1, 1, 2, 1, 0, 1}, // #32 271 {DBGFIELD("WriteFCvtF64ToI64_ReadFCvtF64ToI64") 1, false, false, 1, 1, 2, 1, 0, 1}, // #33 272 {DBGFIELD("WriteFCvtF32ToI64_ReadFCvtF32ToI64") 1, false, false, 1, 1, 2, 1, 0, 1}, // #34 273 {DBGFIELD("WriteFCvtF64ToF32_ReadFCvtF64ToF32") 1, false, false, 1, 1, 2, 1, 0, 1}, // #35 274 {DBGFIELD("WriteFCvtI64ToF32_ReadFCvtI64ToF32") 1, false, false, 1, 1, 2, 1, 0, 1}, // #36 275 {DBGFIELD("WriteFCvtI32ToF32_ReadFCvtI32ToF32") 1, false, false, 1, 1, 2, 1, 0, 1}, // #37 276 {DBGFIELD("WriteFCvtF64ToI32_ReadFCvtF64ToI32") 1, false, false, 1, 1, 2, 1, 0, 1}, // #38 277 {DBGFIELD("WriteFCvtF32ToI32_ReadFCvtF32ToI32") 1, false, false, 1, 1, 2, 1, 0, 1}, // #39 278 {DBGFIELD("WriteFDiv32_ReadFDiv32_ReadFDiv32") 1, false, false, 12, 1, 7, 1, 1, 2}, // #40 279 {DBGFIELD("WriteFCmp64_ReadFCmp64_ReadFCmp64") 1, false, false, 11, 1, 2, 1, 1, 2}, // #41 280 {DBGFIELD("WriteFCmp32_ReadFCmp32_ReadFCmp32") 1, false, false, 11, 1, 2, 1, 1, 2}, // #42 281 {DBGFIELD("WriteFMulAdd64_ReadFMulAdd64_ReadFMulAdd64_ReadFMulAdd64") 1, false, false, 11, 1, 8, 1, 3, 3}, // #43 282 {DBGFIELD("WriteFMulAdd32_ReadFMulAdd32_ReadFMulAdd32_ReadFMulAdd32") 1, false, false, 11, 1, 9, 1, 3, 3}, // #44 283 {DBGFIELD("WriteFMulSub64_ReadFMulSub64_ReadFMulSub64_ReadFMulSub64") 1, false, false, 11, 1, 8, 1, 3, 3}, // #45 284 {DBGFIELD("WriteFMulSub32_ReadFMulSub32_ReadFMulSub32_ReadFMulSub32") 1, false, false, 11, 1, 9, 1, 3, 3}, // #46 285 {DBGFIELD("WriteFMul32_ReadFMul32_ReadFMul32") 1, false, false, 11, 1, 9, 1, 1, 2}, // #47 286 {DBGFIELD("WriteFMovI64ToF64_ReadFMovI64ToF64") 1, false, false, 11, 1, 2, 1, 0, 1}, // #48 287 {DBGFIELD("WriteFMovI32ToF32_ReadFMovI32ToF32") 1, false, false, 11, 1, 2, 1, 0, 1}, // #49 288 {DBGFIELD("WriteFMovF64ToI64_ReadFMovF64ToI64") 1, false, false, 11, 1, 2, 1, 0, 1}, // #50 289 {DBGFIELD("WriteFMovF32ToI32_ReadFMovF32ToI32") 1, false, false, 11, 1, 2, 1, 0, 1}, // #51 290 {DBGFIELD("WriteFSqrt32_ReadFSqrt32") 1, false, false, 12, 1, 7, 1, 0, 1}, // #52 291 {DBGFIELD("WriteLDB_ReadMemBase") 1, false, false, 8, 1, 3, 1, 0, 1}, // #53 292 {DBGFIELD("WriteLDH_ReadMemBase") 1, false, false, 8, 1, 3, 1, 0, 1}, // #54 293 {DBGFIELD("WriteAtomicLDD_ReadAtomicLDD") 1, false, false, 8, 1, 2, 1, 0, 1}, // #55 294 {DBGFIELD("WriteAtomicLDW_ReadAtomicLDW") 1, false, false, 8, 1, 2, 1, 0, 1}, // #56 295 {DBGFIELD("WriteLDWU_ReadMemBase") 1, false, false, 8, 1, 2, 1, 0, 1}, // #57 296 {DBGFIELD("WriteIMul_ReadIMul_ReadIMul") 1, false, false, 2, 1, 6, 1, 1, 2}, // #58 297 {DBGFIELD("WriteIMul32_ReadIMul32_ReadIMul32") 1, false, false, 2, 1, 6, 1, 1, 2}, // #59 298 {DBGFIELD("WriteSTB_ReadStoreData_ReadMemBase") 1, false, false, 8, 1, 1, 1, 1, 2}, // #60 299 {DBGFIELD("WriteAtomicSTD_ReadAtomicSTD_ReadAtomicSTD") 1, false, false, 8, 1, 1, 1, 1, 2}, // #61 300 {DBGFIELD("WriteAtomicSTW_ReadAtomicSTW_ReadAtomicSTW") 1, false, false, 8, 1, 1, 1, 1, 2}, // #62 301 {DBGFIELD("WriteSTH_ReadStoreData_ReadMemBase") 1, false, false, 8, 1, 1, 1, 1, 2}, // #63 302 {DBGFIELD("WriteShift32_ReadShift32") 1, false, false, 3, 1, 1, 1, 0, 1}, // #64 303 {DBGFIELD("COPY") 1, false, false, 3, 1, 1, 1, 0, 0}, // #65 304}; // Rocket64ModelSchedClasses 305 306#undef DBGFIELD 307 308static const llvm::MCSchedModel NoSchedModel = { 309 MCSchedModel::DefaultIssueWidth, 310 MCSchedModel::DefaultMicroOpBufferSize, 311 MCSchedModel::DefaultLoopMicroOpBufferSize, 312 MCSchedModel::DefaultLoadLatency, 313 MCSchedModel::DefaultHighLatency, 314 MCSchedModel::DefaultMispredictPenalty, 315 false, // PostRAScheduler 316 false, // CompleteModel 317 0, // Processor ID 318 nullptr, nullptr, 0, 0, // No instruction-level machine model. 319 nullptr, // No Itinerary 320 nullptr // No extra processor descriptor 321}; 322 323static const unsigned Rocket32ModelProcResourceSubUnits[] = { 324 0, // Invalid 325}; 326 327// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin} 328static const llvm::MCProcResourceDesc Rocket32ModelProcResources[] = { 329 {"InvalidUnit", 0, 0, 0, 0}, 330 {"Rocket32UnitALU", 1, 0, 0, nullptr}, // #1 331 {"Rocket32UnitB", 1, 0, 0, nullptr}, // #2 332 {"Rocket32UnitFPALU", 1, 0, 0, nullptr}, // #3 333 {"Rocket32UnitFPDivSqrt", 1, 0, 1, nullptr}, // #4 334 {"Rocket32UnitIDiv", 1, 0, 1, nullptr}, // #5 335 {"Rocket32UnitIMul", 1, 0, 0, nullptr}, // #6 336 {"Rocket32UnitMem", 1, 0, 0, nullptr}, // #7 337}; 338 339static const llvm::MCSchedModel Rocket32Model = { 340 1, // IssueWidth 341 0, // MicroOpBufferSize 342 MCSchedModel::DefaultLoopMicroOpBufferSize, 343 3, // LoadLatency 344 MCSchedModel::DefaultHighLatency, 345 3, // MispredictPenalty 346 false, // PostRAScheduler 347 true, // CompleteModel 348 1, // Processor ID 349 Rocket32ModelProcResources, 350 Rocket32ModelSchedClasses, 351 8, 352 66, 353 nullptr, // No Itinerary 354 nullptr // No extra processor descriptor 355}; 356 357static const unsigned Rocket64ModelProcResourceSubUnits[] = { 358 0, // Invalid 359}; 360 361// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin} 362static const llvm::MCProcResourceDesc Rocket64ModelProcResources[] = { 363 {"InvalidUnit", 0, 0, 0, 0}, 364 {"Rocket32UnitFPALU", 1, 0, 0, nullptr}, // #1 365 {"Rocket64UnitALU", 1, 0, 0, nullptr}, // #2 366 {"Rocket64UnitB", 1, 0, 0, nullptr}, // #3 367 {"Rocket64UnitFPALU", 1, 0, 0, nullptr}, // #4 368 {"Rocket64UnitFPDivSqrt", 1, 0, 1, nullptr}, // #5 369 {"Rocket64UnitIDiv", 1, 0, 1, nullptr}, // #6 370 {"Rocket64UnitIMul", 1, 0, 0, nullptr}, // #7 371 {"Rocket64UnitMem", 1, 0, 0, nullptr}, // #8 372}; 373 374static const llvm::MCSchedModel Rocket64Model = { 375 1, // IssueWidth 376 0, // MicroOpBufferSize 377 MCSchedModel::DefaultLoopMicroOpBufferSize, 378 3, // LoadLatency 379 MCSchedModel::DefaultHighLatency, 380 3, // MispredictPenalty 381 false, // PostRAScheduler 382 true, // CompleteModel 383 2, // Processor ID 384 Rocket64ModelProcResources, 385 Rocket64ModelSchedClasses, 386 9, 387 66, 388 nullptr, // No Itinerary 389 nullptr // No extra processor descriptor 390}; 391 392// Sorted (by key) array of values for CPU subtype. 393extern const llvm::SubtargetSubTypeKV RISCVSubTypeKV[] = { 394 { "generic-rv32", { { { 0x4ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel }, 395 { "generic-rv64", { { { 0x5ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel }, 396 { "rocket-rv32", { { { 0x4ULL, 0x0ULL, 0x0ULL, } } }, &Rocket32Model }, 397 { "rocket-rv64", { { { 0x5ULL, 0x0ULL, 0x0ULL, } } }, &Rocket64Model }, 398}; 399 400namespace RISCV_MC { 401unsigned resolveVariantSchedClassImpl(unsigned SchedClass, 402 const MCInst *MI, unsigned CPUID) { 403 // Don't know how to resolve this scheduling class. 404 return 0; 405} 406} // end namespace RISCV_MC 407 408struct RISCVGenMCSubtargetInfo : public MCSubtargetInfo { 409 RISCVGenMCSubtargetInfo(const Triple &TT, 410 StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF, 411 ArrayRef<SubtargetSubTypeKV> PD, 412 const MCWriteProcResEntry *WPR, 413 const MCWriteLatencyEntry *WL, 414 const MCReadAdvanceEntry *RA, const InstrStage *IS, 415 const unsigned *OC, const unsigned *FP) : 416 MCSubtargetInfo(TT, CPU, FS, PF, PD, 417 WPR, WL, RA, IS, OC, FP) { } 418 419 unsigned resolveVariantSchedClass(unsigned SchedClass, 420 const MCInst *MI, unsigned CPUID) const override { 421 return RISCV_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID); 422 } 423 unsigned getHwMode() const override; 424}; 425unsigned RISCVGenMCSubtargetInfo::getHwMode() const { 426 if (checkFeatures("-64bit")) return 1; 427 if (checkFeatures("+64bit")) return 2; 428 return 0; 429} 430 431static inline MCSubtargetInfo *createRISCVMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) { 432 return new RISCVGenMCSubtargetInfo(TT, CPU, FS, RISCVFeatureKV, RISCVSubTypeKV, 433 RISCVWriteProcResTable, RISCVWriteLatencyTable, RISCVReadAdvanceTable, 434 nullptr, nullptr, nullptr); 435} 436 437} // end namespace llvm 438 439#endif // GET_SUBTARGETINFO_MC_DESC 440 441 442#ifdef GET_SUBTARGETINFO_TARGET_DESC 443#undef GET_SUBTARGETINFO_TARGET_DESC 444 445#include "llvm/Support/Debug.h" 446#include "llvm/Support/raw_ostream.h" 447 448// ParseSubtargetFeatures - Parses features string setting specified 449// subtarget options. 450void llvm::RISCVSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) { 451 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS); 452 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n"); 453 InitMCProcessorInfo(CPU, FS); 454 const FeatureBitset& Bits = getFeatureBits(); 455 if (Bits[RISCV::Feature64Bit]) HasRV64 = true; 456 if (Bits[RISCV::FeatureRV32E]) IsRV32E = true; 457 if (Bits[RISCV::FeatureRVCHints]) EnableRVCHintInstrs = true; 458 if (Bits[RISCV::FeatureRelax]) EnableLinkerRelax = true; 459 if (Bits[RISCV::FeatureReserveX1]) UserReservedRegister[RISCV::X1] = true; 460 if (Bits[RISCV::FeatureReserveX2]) UserReservedRegister[RISCV::X2] = true; 461 if (Bits[RISCV::FeatureReserveX3]) UserReservedRegister[RISCV::X3] = true; 462 if (Bits[RISCV::FeatureReserveX4]) UserReservedRegister[RISCV::X4] = true; 463 if (Bits[RISCV::FeatureReserveX5]) UserReservedRegister[RISCV::X5] = true; 464 if (Bits[RISCV::FeatureReserveX6]) UserReservedRegister[RISCV::X6] = true; 465 if (Bits[RISCV::FeatureReserveX7]) UserReservedRegister[RISCV::X7] = true; 466 if (Bits[RISCV::FeatureReserveX8]) UserReservedRegister[RISCV::X8] = true; 467 if (Bits[RISCV::FeatureReserveX9]) UserReservedRegister[RISCV::X9] = true; 468 if (Bits[RISCV::FeatureReserveX10]) UserReservedRegister[RISCV::X10] = true; 469 if (Bits[RISCV::FeatureReserveX11]) UserReservedRegister[RISCV::X11] = true; 470 if (Bits[RISCV::FeatureReserveX12]) UserReservedRegister[RISCV::X12] = true; 471 if (Bits[RISCV::FeatureReserveX13]) UserReservedRegister[RISCV::X13] = true; 472 if (Bits[RISCV::FeatureReserveX14]) UserReservedRegister[RISCV::X14] = true; 473 if (Bits[RISCV::FeatureReserveX15]) UserReservedRegister[RISCV::X15] = true; 474 if (Bits[RISCV::FeatureReserveX16]) UserReservedRegister[RISCV::X16] = true; 475 if (Bits[RISCV::FeatureReserveX17]) UserReservedRegister[RISCV::X17] = true; 476 if (Bits[RISCV::FeatureReserveX18]) UserReservedRegister[RISCV::X18] = true; 477 if (Bits[RISCV::FeatureReserveX19]) UserReservedRegister[RISCV::X19] = true; 478 if (Bits[RISCV::FeatureReserveX20]) UserReservedRegister[RISCV::X20] = true; 479 if (Bits[RISCV::FeatureReserveX21]) UserReservedRegister[RISCV::X21] = true; 480 if (Bits[RISCV::FeatureReserveX22]) UserReservedRegister[RISCV::X22] = true; 481 if (Bits[RISCV::FeatureReserveX23]) UserReservedRegister[RISCV::X23] = true; 482 if (Bits[RISCV::FeatureReserveX24]) UserReservedRegister[RISCV::X24] = true; 483 if (Bits[RISCV::FeatureReserveX25]) UserReservedRegister[RISCV::X25] = true; 484 if (Bits[RISCV::FeatureReserveX26]) UserReservedRegister[RISCV::X26] = true; 485 if (Bits[RISCV::FeatureReserveX27]) UserReservedRegister[RISCV::X27] = true; 486 if (Bits[RISCV::FeatureReserveX28]) UserReservedRegister[RISCV::X28] = true; 487 if (Bits[RISCV::FeatureReserveX29]) UserReservedRegister[RISCV::X29] = true; 488 if (Bits[RISCV::FeatureReserveX30]) UserReservedRegister[RISCV::X30] = true; 489 if (Bits[RISCV::FeatureReserveX31]) UserReservedRegister[RISCV::X31] = true; 490 if (Bits[RISCV::FeatureStdExtA]) HasStdExtA = true; 491 if (Bits[RISCV::FeatureStdExtC]) HasStdExtC = true; 492 if (Bits[RISCV::FeatureStdExtD]) HasStdExtD = true; 493 if (Bits[RISCV::FeatureStdExtF]) HasStdExtF = true; 494 if (Bits[RISCV::FeatureStdExtM]) HasStdExtM = true; 495} 496#endif // GET_SUBTARGETINFO_TARGET_DESC 497 498 499#ifdef GET_SUBTARGETINFO_HEADER 500#undef GET_SUBTARGETINFO_HEADER 501 502namespace llvm { 503class DFAPacketizer; 504namespace RISCV_MC { 505unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID); 506} // end namespace RISCV_MC 507 508struct RISCVGenSubtargetInfo : public TargetSubtargetInfo { 509 explicit RISCVGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS); 510public: 511 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override; 512 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override; 513 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const; 514 unsigned getHwMode() const override; 515}; 516} // end namespace llvm 517 518#endif // GET_SUBTARGETINFO_HEADER 519 520 521#ifdef GET_SUBTARGETINFO_CTOR 522#undef GET_SUBTARGETINFO_CTOR 523 524#include "llvm/CodeGen/TargetSchedule.h" 525 526namespace llvm { 527extern const llvm::SubtargetFeatureKV RISCVFeatureKV[]; 528extern const llvm::SubtargetSubTypeKV RISCVSubTypeKV[]; 529extern const llvm::MCWriteProcResEntry RISCVWriteProcResTable[]; 530extern const llvm::MCWriteLatencyEntry RISCVWriteLatencyTable[]; 531extern const llvm::MCReadAdvanceEntry RISCVReadAdvanceTable[]; 532RISCVGenSubtargetInfo::RISCVGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) 533 : TargetSubtargetInfo(TT, CPU, FS, makeArrayRef(RISCVFeatureKV, 40), makeArrayRef(RISCVSubTypeKV, 4), 534 RISCVWriteProcResTable, RISCVWriteLatencyTable, RISCVReadAdvanceTable, 535 nullptr, nullptr, nullptr) {} 536 537unsigned RISCVGenSubtargetInfo 538::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const { 539 report_fatal_error("Expected a variant SchedClass"); 540} // RISCVGenSubtargetInfo::resolveSchedClass 541 542unsigned RISCVGenSubtargetInfo 543::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const { 544 return RISCV_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID); 545} // RISCVGenSubtargetInfo::resolveVariantSchedClass 546 547unsigned RISCVGenSubtargetInfo::getHwMode() const { 548 if (checkFeatures("-64bit")) return 1; 549 if (checkFeatures("+64bit")) return 2; 550 return 0; 551} 552} // end namespace llvm 553 554#endif // GET_SUBTARGETINFO_CTOR 555 556 557#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS 558#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS 559 560#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS 561 562 563#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS 564#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS 565 566#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS 567 568