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1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|* Global Instruction Selector for the ARM target                             *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10const unsigned MAX_SUBTARGET_PREDICATES = 80;
11using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15  mutable MatcherState State;
16  typedef ComplexRendererFns(ARMInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17  typedef void(ARMInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
18  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19  static ARMInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20  static ARMInstructionSelector::CustomRendererFn CustomRenderers[];
21  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24  const int64_t *getMatchTable() const override;
25  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const std::array<const MachineOperand *, 3> &Operands) const override;
26#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27
28#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29, State(0),
30ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32
33#ifdef GET_GLOBALISEL_IMPL
34// Bits for subtarget features that participate in instruction matching.
35enum SubtargetFeatureBits : uint8_t {
36  Feature_NoHonorSignDependentRoundingBit = 71,
37  Feature_HasV4TBit = 6,
38  Feature_NoV4TBit = 7,
39  Feature_HasV5TBit = 13,
40  Feature_NoV5TBit = 65,
41  Feature_HasV5TEBit = 11,
42  Feature_HasV6Bit = 0,
43  Feature_NoV6Bit = 9,
44  Feature_HasV6MBit = 29,
45  Feature_HasV8MBaselineBit = 34,
46  Feature_HasV8_1MMainlineBit = 40,
47  Feature_HasMVEIntBit = 63,
48  Feature_HasMVEFloatBit = 64,
49  Feature_HasCDEBit = 79,
50  Feature_HasFPRegsBit = 41,
51  Feature_HasFPRegs16Bit = 42,
52  Feature_HasNoFPRegs16Bit = 70,
53  Feature_HasFPRegs64Bit = 51,
54  Feature_HasV6T2Bit = 8,
55  Feature_HasV6KBit = 19,
56  Feature_HasV7Bit = 3,
57  Feature_HasV8Bit = 15,
58  Feature_PreV8Bit = 20,
59  Feature_HasV8_1aBit = 73,
60  Feature_HasV8_3aBit = 74,
61  Feature_NoVFPBit = 23,
62  Feature_HasVFP2Bit = 22,
63  Feature_HasVFP3Bit = 52,
64  Feature_HasVFP4Bit = 49,
65  Feature_HasDPVFPBit = 43,
66  Feature_HasFPARMv8Bit = 46,
67  Feature_HasNEONBit = 53,
68  Feature_HasSHA2Bit = 61,
69  Feature_HasAESBit = 54,
70  Feature_HasDotProdBit = 55,
71  Feature_HasCRCBit = 14,
72  Feature_HasLOBBit = 39,
73  Feature_HasFP16Bit = 60,
74  Feature_HasFullFP16Bit = 45,
75  Feature_HasBF16Bit = 62,
76  Feature_HasMatMulInt8Bit = 56,
77  Feature_HasDivideInThumbBit = 36,
78  Feature_HasDivideInARMBit = 12,
79  Feature_HasDSPBit = 35,
80  Feature_HasDBBit = 16,
81  Feature_HasV7ClrexBit = 18,
82  Feature_HasAcquireReleaseBit = 17,
83  Feature_HasMPBit = 2,
84  Feature_Has8MSecExtBit = 30,
85  Feature_HasZCZBit = 57,
86  Feature_UseNEONForFPBit = 77,
87  Feature_DontUseNEONForFPBit = 44,
88  Feature_IsThumbBit = 27,
89  Feature_IsThumb1OnlyBit = 28,
90  Feature_IsThumb2Bit = 33,
91  Feature_IsNotMClassBit = 37,
92  Feature_IsARMBit = 1,
93  Feature_IsWindowsBit = 31,
94  Feature_IsNotWindowsBit = 32,
95  Feature_IsReadTPHardBit = 68,
96  Feature_IsReadTPSoftBit = 21,
97  Feature_UseNaClTrapBit = 4,
98  Feature_DontUseNaClTrapBit = 5,
99  Feature_UseMovtBit = 38,
100  Feature_DontUseMovtBit = 24,
101  Feature_UseMovtInPicBit = 25,
102  Feature_DontUseMovtInPicBit = 26,
103  Feature_UseFPVMLxBit = 48,
104  Feature_SLSBLRMitigationBit = 67,
105  Feature_NoSLSBLRMitigationBit = 66,
106  Feature_UseMulOpsBit = 10,
107  Feature_UseFusedMACBit = 50,
108  Feature_HasFastVGETLNi32Bit = 58,
109  Feature_HasSlowVGETLNi32Bit = 75,
110  Feature_HasFastVDUP32Bit = 59,
111  Feature_HasSlowVDUP32Bit = 76,
112  Feature_UseVMOVSRBit = 47,
113  Feature_DontUseVMOVSRBit = 78,
114  Feature_IsLEBit = 69,
115  Feature_IsBEBit = 72,
116};
117
118PredicateBitset ARMInstructionSelector::
119computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const {
120  PredicateBitset Features;
121  if (!TM.Options.HonorSignDependentRoundingFPMath())
122    Features.set(Feature_NoHonorSignDependentRoundingBit);
123  if (Subtarget->hasV4TOps())
124    Features.set(Feature_HasV4TBit);
125  if (!Subtarget->hasV4TOps())
126    Features.set(Feature_NoV4TBit);
127  if (Subtarget->hasV5TOps())
128    Features.set(Feature_HasV5TBit);
129  if (!Subtarget->hasV5TOps())
130    Features.set(Feature_NoV5TBit);
131  if (Subtarget->hasV5TEOps())
132    Features.set(Feature_HasV5TEBit);
133  if (Subtarget->hasV6Ops())
134    Features.set(Feature_HasV6Bit);
135  if (!Subtarget->hasV6Ops())
136    Features.set(Feature_NoV6Bit);
137  if (Subtarget->hasV6MOps())
138    Features.set(Feature_HasV6MBit);
139  if (Subtarget->hasV8MBaselineOps())
140    Features.set(Feature_HasV8MBaselineBit);
141  if (Subtarget->hasV8_1MMainlineOps())
142    Features.set(Feature_HasV8_1MMainlineBit);
143  if (Subtarget->hasMVEIntegerOps())
144    Features.set(Feature_HasMVEIntBit);
145  if (Subtarget->hasMVEFloatOps())
146    Features.set(Feature_HasMVEFloatBit);
147  if (Subtarget->hasCDEOps())
148    Features.set(Feature_HasCDEBit);
149  if (Subtarget->hasFPRegs())
150    Features.set(Feature_HasFPRegsBit);
151  if (Subtarget->hasFPRegs16())
152    Features.set(Feature_HasFPRegs16Bit);
153  if (!Subtarget->hasFPRegs16())
154    Features.set(Feature_HasNoFPRegs16Bit);
155  if (Subtarget->hasFPRegs64())
156    Features.set(Feature_HasFPRegs64Bit);
157  if (Subtarget->hasV6T2Ops())
158    Features.set(Feature_HasV6T2Bit);
159  if (Subtarget->hasV6KOps())
160    Features.set(Feature_HasV6KBit);
161  if (Subtarget->hasV7Ops())
162    Features.set(Feature_HasV7Bit);
163  if (Subtarget->hasV8Ops())
164    Features.set(Feature_HasV8Bit);
165  if (!Subtarget->hasV8Ops())
166    Features.set(Feature_PreV8Bit);
167  if (Subtarget->hasV8_1aOps())
168    Features.set(Feature_HasV8_1aBit);
169  if (Subtarget->hasV8_3aOps())
170    Features.set(Feature_HasV8_3aBit);
171  if (!Subtarget->hasVFP2Base())
172    Features.set(Feature_NoVFPBit);
173  if (Subtarget->hasVFP2Base())
174    Features.set(Feature_HasVFP2Bit);
175  if (Subtarget->hasVFP3Base())
176    Features.set(Feature_HasVFP3Bit);
177  if (Subtarget->hasVFP4Base())
178    Features.set(Feature_HasVFP4Bit);
179  if (Subtarget->hasFP64())
180    Features.set(Feature_HasDPVFPBit);
181  if (Subtarget->hasFPARMv8Base())
182    Features.set(Feature_HasFPARMv8Bit);
183  if (Subtarget->hasNEON())
184    Features.set(Feature_HasNEONBit);
185  if (Subtarget->hasSHA2())
186    Features.set(Feature_HasSHA2Bit);
187  if (Subtarget->hasAES())
188    Features.set(Feature_HasAESBit);
189  if (Subtarget->hasDotProd())
190    Features.set(Feature_HasDotProdBit);
191  if (Subtarget->hasCRC())
192    Features.set(Feature_HasCRCBit);
193  if (Subtarget->hasLOB())
194    Features.set(Feature_HasLOBBit);
195  if (Subtarget->hasFP16())
196    Features.set(Feature_HasFP16Bit);
197  if (Subtarget->hasFullFP16())
198    Features.set(Feature_HasFullFP16Bit);
199  if (Subtarget->hasBF16())
200    Features.set(Feature_HasBF16Bit);
201  if (Subtarget->hasMatMulInt8())
202    Features.set(Feature_HasMatMulInt8Bit);
203  if (Subtarget->hasDivideInThumbMode())
204    Features.set(Feature_HasDivideInThumbBit);
205  if (Subtarget->hasDivideInARMMode())
206    Features.set(Feature_HasDivideInARMBit);
207  if (Subtarget->hasDSP())
208    Features.set(Feature_HasDSPBit);
209  if (Subtarget->hasDataBarrier())
210    Features.set(Feature_HasDBBit);
211  if (Subtarget->hasV7Clrex())
212    Features.set(Feature_HasV7ClrexBit);
213  if (Subtarget->hasAcquireRelease())
214    Features.set(Feature_HasAcquireReleaseBit);
215  if (Subtarget->hasMPExtension())
216    Features.set(Feature_HasMPBit);
217  if (Subtarget->has8MSecExt())
218    Features.set(Feature_Has8MSecExtBit);
219  if (Subtarget->hasZeroCycleZeroing())
220    Features.set(Feature_HasZCZBit);
221  if (Subtarget->useNEONForSinglePrecisionFP())
222    Features.set(Feature_UseNEONForFPBit);
223  if (!Subtarget->useNEONForSinglePrecisionFP())
224    Features.set(Feature_DontUseNEONForFPBit);
225  if (Subtarget->isThumb())
226    Features.set(Feature_IsThumbBit);
227  if (Subtarget->isThumb1Only())
228    Features.set(Feature_IsThumb1OnlyBit);
229  if (Subtarget->isThumb2())
230    Features.set(Feature_IsThumb2Bit);
231  if (!Subtarget->isMClass())
232    Features.set(Feature_IsNotMClassBit);
233  if (!Subtarget->isThumb())
234    Features.set(Feature_IsARMBit);
235  if (Subtarget->isTargetWindows())
236    Features.set(Feature_IsWindowsBit);
237  if (!Subtarget->isTargetWindows())
238    Features.set(Feature_IsNotWindowsBit);
239  if (Subtarget->isReadTPHard())
240    Features.set(Feature_IsReadTPHardBit);
241  if (!Subtarget->isReadTPHard())
242    Features.set(Feature_IsReadTPSoftBit);
243  if (Subtarget->useNaClTrap())
244    Features.set(Feature_UseNaClTrapBit);
245  if (!Subtarget->useNaClTrap())
246    Features.set(Feature_DontUseNaClTrapBit);
247  if (Subtarget->useMulOps())
248    Features.set(Feature_UseMulOpsBit);
249  if (TM.Options.AllowFPOpFusion ==  FPOpFusion::Fast && Subtarget->useFPVFMx())
250    Features.set(Feature_UseFusedMACBit);
251  if (!Subtarget->hasSlowVGETLNi32())
252    Features.set(Feature_HasFastVGETLNi32Bit);
253  if (Subtarget->hasSlowVGETLNi32())
254    Features.set(Feature_HasSlowVGETLNi32Bit);
255  if (!Subtarget->hasSlowVDUP32())
256    Features.set(Feature_HasFastVDUP32Bit);
257  if (Subtarget->hasSlowVDUP32())
258    Features.set(Feature_HasSlowVDUP32Bit);
259  if (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())
260    Features.set(Feature_UseVMOVSRBit);
261  if (!Subtarget->preferVMOVSR() &&Subtarget->useNEONForSinglePrecisionFP())
262    Features.set(Feature_DontUseVMOVSRBit);
263  return Features;
264}
265
266void ARMInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
267  AvailableFunctionFeatures = computeAvailableFunctionFeatures((const ARMSubtarget *)&MF.getSubtarget(), &MF);
268}
269PredicateBitset ARMInstructionSelector::
270computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, const MachineFunction *MF) const {
271  PredicateBitset Features;
272  if (Subtarget->useMovt())
273    Features.set(Feature_UseMovtBit);
274  if (!Subtarget->useMovt())
275    Features.set(Feature_DontUseMovtBit);
276  if (Subtarget->useMovt() && Subtarget->allowPositionIndependentMovt())
277    Features.set(Feature_UseMovtInPicBit);
278  if (!Subtarget->useMovt() || !Subtarget->allowPositionIndependentMovt())
279    Features.set(Feature_DontUseMovtInPicBit);
280  if (((Subtarget->useFPVMLx() &&  TM.Options.AllowFPOpFusion != FPOpFusion::Fast) ||Subtarget->hasMinSize()))
281    Features.set(Feature_UseFPVMLxBit);
282  if ( MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() )
283    Features.set(Feature_SLSBLRMitigationBit);
284  if ( !MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() )
285    Features.set(Feature_NoSLSBLRMitigationBit);
286  if (MF->getDataLayout().isLittleEndian())
287    Features.set(Feature_IsLEBit);
288  if (MF->getDataLayout().isBigEndian())
289    Features.set(Feature_IsBEBit);
290  return Features;
291}
292
293// LLT Objects.
294enum {
295  GILLT_s16,
296  GILLT_s32,
297  GILLT_s64,
298  GILLT_v2s1,
299  GILLT_v2s32,
300  GILLT_v2s64,
301  GILLT_v4s1,
302  GILLT_v4s16,
303  GILLT_v4s32,
304  GILLT_v4s64,
305  GILLT_v8s1,
306  GILLT_v8s8,
307  GILLT_v8s16,
308  GILLT_v8s64,
309  GILLT_v16s1,
310  GILLT_v16s8,
311};
312const static size_t NumTypeObjects = 16;
313const static LLT TypeObjects[] = {
314  LLT::scalar(16),
315  LLT::scalar(32),
316  LLT::scalar(64),
317  LLT::vector(ElementCount::getFixed(2), 1),
318  LLT::vector(ElementCount::getFixed(2), 32),
319  LLT::vector(ElementCount::getFixed(2), 64),
320  LLT::vector(ElementCount::getFixed(4), 1),
321  LLT::vector(ElementCount::getFixed(4), 16),
322  LLT::vector(ElementCount::getFixed(4), 32),
323  LLT::vector(ElementCount::getFixed(4), 64),
324  LLT::vector(ElementCount::getFixed(8), 1),
325  LLT::vector(ElementCount::getFixed(8), 8),
326  LLT::vector(ElementCount::getFixed(8), 16),
327  LLT::vector(ElementCount::getFixed(8), 64),
328  LLT::vector(ElementCount::getFixed(16), 1),
329  LLT::vector(ElementCount::getFixed(16), 8),
330};
331
332// Feature bitsets.
333enum {
334  GIFBS_Invalid,
335  GIFBS_HasDotProd,
336  GIFBS_HasFP16,
337  GIFBS_HasFPARMv8,
338  GIFBS_HasFPRegs,
339  GIFBS_HasFullFP16,
340  GIFBS_HasMVEFloat,
341  GIFBS_HasMVEInt,
342  GIFBS_HasMatMulInt8,
343  GIFBS_HasNEON,
344  GIFBS_HasVFP2,
345  GIFBS_HasVFP3,
346  GIFBS_HasVFP4,
347  GIFBS_IsARM,
348  GIFBS_IsThumb,
349  GIFBS_IsThumb2,
350  GIFBS_NoHonorSignDependentRounding,
351  GIFBS_DontUseNEONForFP_HasVFP2,
352  GIFBS_DontUseVMOVSR_HasNEON,
353  GIFBS_Has8MSecExt_IsThumb,
354  GIFBS_HasAES_HasV8,
355  GIFBS_HasBF16_HasNEON,
356  GIFBS_HasDB_IsARM,
357  GIFBS_HasDB_IsThumb,
358  GIFBS_HasDPVFP_HasFPARMv8,
359  GIFBS_HasDPVFP_HasVFP2,
360  GIFBS_HasDPVFP_HasVFP3,
361  GIFBS_HasDPVFP_HasVFP4,
362  GIFBS_HasDPVFP_NoHonorSignDependentRounding,
363  GIFBS_HasDSP_IsThumb2,
364  GIFBS_HasDivideInARM_IsARM,
365  GIFBS_HasFP16_HasNEON,
366  GIFBS_HasFPRegs_HasFastVGETLNi32,
367  GIFBS_HasFPRegs_UseVMOVSR,
368  GIFBS_HasFullFP16_HasNEON,
369  GIFBS_HasMVEInt_HasV8_1MMainline,
370  GIFBS_HasMVEInt_IsBE,
371  GIFBS_HasMVEInt_IsLE,
372  GIFBS_HasNEON_HasV8,
373  GIFBS_HasNEON_HasV8_1a,
374  GIFBS_HasNEON_HasV8_3a,
375  GIFBS_HasNEON_HasVFP4,
376  GIFBS_HasNEON_IsBE,
377  GIFBS_HasNEON_IsLE,
378  GIFBS_HasNEON_UseNEONForFP,
379  GIFBS_HasSHA2_HasV8,
380  GIFBS_HasV5T_IsARM,
381  GIFBS_HasV5TE_IsARM,
382  GIFBS_HasV6_IsARM,
383  GIFBS_HasV6K_IsARM,
384  GIFBS_HasV6M_IsThumb,
385  GIFBS_HasV6T2_IsARM,
386  GIFBS_HasV7_IsARM,
387  GIFBS_HasV7Clrex_IsThumb,
388  GIFBS_HasV8MBaseline_IsThumb,
389  GIFBS_IsARM_NoV6,
390  GIFBS_IsARM_PreV8,
391  GIFBS_IsThumb_IsThumb1Only,
392  GIFBS_IsThumb_IsWindows,
393  GIFBS_IsThumb_UseMovt,
394  GIFBS_IsThumb2_PreV8,
395  GIFBS_IsThumb2_UseMulOps,
396  GIFBS_HasCRC_HasV8_IsARM,
397  GIFBS_HasCRC_HasV8_IsThumb2,
398  GIFBS_HasDSP_IsThumb2_UseMulOps,
399  GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
400  GIFBS_HasFullFP16_HasNEON_HasV8,
401  GIFBS_HasFullFP16_HasNEON_HasV8_3a,
402  GIFBS_HasFullFP16_HasNEON_UseFPVMLx,
403  GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
404  GIFBS_HasLOB_HasV8_1MMainline_IsThumb2,
405  GIFBS_HasNEON_UseFPVMLx_UseNEONForFP,
406  GIFBS_HasV5TE_IsARM_UseMulOps,
407  GIFBS_HasV6_IsARM_UseMulOps,
408  GIFBS_HasV6_IsThumb_IsThumb1Only,
409  GIFBS_HasV6T2_IsARM_UseMulOps,
410  GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP,
411  GIFBS_IsARM_NoV6_UseMulOps,
412};
413const static PredicateBitset FeatureBitsets[] {
414  {}, // GIFBS_Invalid
415  {Feature_HasDotProdBit, },
416  {Feature_HasFP16Bit, },
417  {Feature_HasFPARMv8Bit, },
418  {Feature_HasFPRegsBit, },
419  {Feature_HasFullFP16Bit, },
420  {Feature_HasMVEFloatBit, },
421  {Feature_HasMVEIntBit, },
422  {Feature_HasMatMulInt8Bit, },
423  {Feature_HasNEONBit, },
424  {Feature_HasVFP2Bit, },
425  {Feature_HasVFP3Bit, },
426  {Feature_HasVFP4Bit, },
427  {Feature_IsARMBit, },
428  {Feature_IsThumbBit, },
429  {Feature_IsThumb2Bit, },
430  {Feature_NoHonorSignDependentRoundingBit, },
431  {Feature_DontUseNEONForFPBit, Feature_HasVFP2Bit, },
432  {Feature_DontUseVMOVSRBit, Feature_HasNEONBit, },
433  {Feature_Has8MSecExtBit, Feature_IsThumbBit, },
434  {Feature_HasAESBit, Feature_HasV8Bit, },
435  {Feature_HasBF16Bit, Feature_HasNEONBit, },
436  {Feature_HasDBBit, Feature_IsARMBit, },
437  {Feature_HasDBBit, Feature_IsThumbBit, },
438  {Feature_HasDPVFPBit, Feature_HasFPARMv8Bit, },
439  {Feature_HasDPVFPBit, Feature_HasVFP2Bit, },
440  {Feature_HasDPVFPBit, Feature_HasVFP3Bit, },
441  {Feature_HasDPVFPBit, Feature_HasVFP4Bit, },
442  {Feature_HasDPVFPBit, Feature_NoHonorSignDependentRoundingBit, },
443  {Feature_HasDSPBit, Feature_IsThumb2Bit, },
444  {Feature_HasDivideInARMBit, Feature_IsARMBit, },
445  {Feature_HasFP16Bit, Feature_HasNEONBit, },
446  {Feature_HasFPRegsBit, Feature_HasFastVGETLNi32Bit, },
447  {Feature_HasFPRegsBit, Feature_UseVMOVSRBit, },
448  {Feature_HasFullFP16Bit, Feature_HasNEONBit, },
449  {Feature_HasMVEIntBit, Feature_HasV8_1MMainlineBit, },
450  {Feature_HasMVEIntBit, Feature_IsBEBit, },
451  {Feature_HasMVEIntBit, Feature_IsLEBit, },
452  {Feature_HasNEONBit, Feature_HasV8Bit, },
453  {Feature_HasNEONBit, Feature_HasV8_1aBit, },
454  {Feature_HasNEONBit, Feature_HasV8_3aBit, },
455  {Feature_HasNEONBit, Feature_HasVFP4Bit, },
456  {Feature_HasNEONBit, Feature_IsBEBit, },
457  {Feature_HasNEONBit, Feature_IsLEBit, },
458  {Feature_HasNEONBit, Feature_UseNEONForFPBit, },
459  {Feature_HasSHA2Bit, Feature_HasV8Bit, },
460  {Feature_HasV5TBit, Feature_IsARMBit, },
461  {Feature_HasV5TEBit, Feature_IsARMBit, },
462  {Feature_HasV6Bit, Feature_IsARMBit, },
463  {Feature_HasV6KBit, Feature_IsARMBit, },
464  {Feature_HasV6MBit, Feature_IsThumbBit, },
465  {Feature_HasV6T2Bit, Feature_IsARMBit, },
466  {Feature_HasV7Bit, Feature_IsARMBit, },
467  {Feature_HasV7ClrexBit, Feature_IsThumbBit, },
468  {Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
469  {Feature_IsARMBit, Feature_NoV6Bit, },
470  {Feature_IsARMBit, Feature_PreV8Bit, },
471  {Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
472  {Feature_IsThumbBit, Feature_IsWindowsBit, },
473  {Feature_IsThumbBit, Feature_UseMovtBit, },
474  {Feature_IsThumb2Bit, Feature_PreV8Bit, },
475  {Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
476  {Feature_HasCRCBit, Feature_HasV8Bit, Feature_IsARMBit, },
477  {Feature_HasCRCBit, Feature_HasV8Bit, Feature_IsThumb2Bit, },
478  {Feature_HasDSPBit, Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
479  {Feature_HasDivideInThumbBit, Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
480  {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8Bit, },
481  {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8_3aBit, },
482  {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFPVMLxBit, },
483  {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFusedMACBit, },
484  {Feature_HasLOBBit, Feature_HasV8_1MMainlineBit, Feature_IsThumb2Bit, },
485  {Feature_HasNEONBit, Feature_UseFPVMLxBit, Feature_UseNEONForFPBit, },
486  {Feature_HasV5TEBit, Feature_IsARMBit, Feature_UseMulOpsBit, },
487  {Feature_HasV6Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
488  {Feature_HasV6Bit, Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
489  {Feature_HasV6T2Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
490  {Feature_HasVFP4Bit, Feature_UseFusedMACBit, Feature_UseNEONForFPBit, },
491  {Feature_IsARMBit, Feature_NoV6Bit, Feature_UseMulOpsBit, },
492};
493
494// ComplexPattern predicates.
495enum {
496  GICP_Invalid,
497};
498// See constructor for table contents
499
500// PatFrag predicates.
501enum {
502  GIPFP_I64_Predicate_VectorIndex16 = GIPFP_I64_Invalid + 1,
503  GIPFP_I64_Predicate_VectorIndex32,
504  GIPFP_I64_Predicate_VectorIndex64,
505  GIPFP_I64_Predicate_VectorIndex8,
506  GIPFP_I64_Predicate_asr_imm,
507  GIPFP_I64_Predicate_imm0_15,
508  GIPFP_I64_Predicate_imm0_239,
509  GIPFP_I64_Predicate_imm0_255,
510  GIPFP_I64_Predicate_imm0_31,
511  GIPFP_I64_Predicate_imm0_32,
512  GIPFP_I64_Predicate_imm0_4095,
513  GIPFP_I64_Predicate_imm0_63,
514  GIPFP_I64_Predicate_imm0_65535,
515  GIPFP_I64_Predicate_imm0_65535_neg,
516  GIPFP_I64_Predicate_imm0_7,
517  GIPFP_I64_Predicate_imm16,
518  GIPFP_I64_Predicate_imm16_31,
519  GIPFP_I64_Predicate_imm1_15,
520  GIPFP_I64_Predicate_imm1_16,
521  GIPFP_I64_Predicate_imm1_31,
522  GIPFP_I64_Predicate_imm1_7,
523  GIPFP_I64_Predicate_imm24b,
524  GIPFP_I64_Predicate_imm256_510,
525  GIPFP_I64_Predicate_imm32,
526  GIPFP_I64_Predicate_imm8,
527  GIPFP_I64_Predicate_imm8_255,
528  GIPFP_I64_Predicate_imm8_or_16,
529  GIPFP_I64_Predicate_imm_11b,
530  GIPFP_I64_Predicate_imm_12b,
531  GIPFP_I64_Predicate_imm_13b,
532  GIPFP_I64_Predicate_imm_3b,
533  GIPFP_I64_Predicate_imm_4b,
534  GIPFP_I64_Predicate_imm_6b,
535  GIPFP_I64_Predicate_imm_7b,
536  GIPFP_I64_Predicate_imm_9b,
537  GIPFP_I64_Predicate_imm_even,
538  GIPFP_I64_Predicate_imm_odd,
539  GIPFP_I64_Predicate_long_shift,
540  GIPFP_I64_Predicate_mod_imm,
541  GIPFP_I64_Predicate_pkh_asr_amt,
542  GIPFP_I64_Predicate_pkh_lsl_amt,
543  GIPFP_I64_Predicate_shr_imm16,
544  GIPFP_I64_Predicate_shr_imm32,
545  GIPFP_I64_Predicate_shr_imm64,
546  GIPFP_I64_Predicate_shr_imm8,
547  GIPFP_I64_Predicate_t2_so_imm,
548  GIPFP_I64_Predicate_t2_so_imm_neg,
549};
550bool ARMInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
551  switch (PredicateID) {
552  case GIPFP_I64_Predicate_VectorIndex16: {
553
554  return ((uint64_t)Imm) < 4;
555
556    llvm_unreachable("ImmediateCode should have returned");
557    return false;
558  }
559  case GIPFP_I64_Predicate_VectorIndex32: {
560
561  return ((uint64_t)Imm) < 2;
562
563    llvm_unreachable("ImmediateCode should have returned");
564    return false;
565  }
566  case GIPFP_I64_Predicate_VectorIndex64: {
567
568  return ((uint64_t)Imm) < 1;
569
570    llvm_unreachable("ImmediateCode should have returned");
571    return false;
572  }
573  case GIPFP_I64_Predicate_VectorIndex8: {
574
575  return ((uint64_t)Imm) < 8;
576
577    llvm_unreachable("ImmediateCode should have returned");
578    return false;
579  }
580  case GIPFP_I64_Predicate_asr_imm: {
581     return Imm > 0 && Imm <= 32;
582    llvm_unreachable("ImmediateCode should have returned");
583    return false;
584  }
585  case GIPFP_I64_Predicate_imm0_15: {
586
587  return Imm >= 0 && Imm < 16;
588
589    llvm_unreachable("ImmediateCode should have returned");
590    return false;
591  }
592  case GIPFP_I64_Predicate_imm0_239: {
593     return Imm >= 0 && Imm < 240;
594    llvm_unreachable("ImmediateCode should have returned");
595    return false;
596  }
597  case GIPFP_I64_Predicate_imm0_255: {
598     return Imm >= 0 && Imm < 256;
599    llvm_unreachable("ImmediateCode should have returned");
600    return false;
601  }
602  case GIPFP_I64_Predicate_imm0_31: {
603
604  return Imm >= 0 && Imm < 32;
605
606    llvm_unreachable("ImmediateCode should have returned");
607    return false;
608  }
609  case GIPFP_I64_Predicate_imm0_32: {
610
611  return Imm >= 0 && Imm < 33;
612
613    llvm_unreachable("ImmediateCode should have returned");
614    return false;
615  }
616  case GIPFP_I64_Predicate_imm0_4095: {
617
618  return Imm >= 0 && Imm < 4096;
619
620    llvm_unreachable("ImmediateCode should have returned");
621    return false;
622  }
623  case GIPFP_I64_Predicate_imm0_63: {
624
625  return Imm >= 0 && Imm < 64;
626
627    llvm_unreachable("ImmediateCode should have returned");
628    return false;
629  }
630  case GIPFP_I64_Predicate_imm0_65535: {
631
632  return Imm >= 0 && Imm < 65536;
633
634    llvm_unreachable("ImmediateCode should have returned");
635    return false;
636  }
637  case GIPFP_I64_Predicate_imm0_65535_neg: {
638
639  return -Imm >= 0 && -Imm < 65536;
640
641    llvm_unreachable("ImmediateCode should have returned");
642    return false;
643  }
644  case GIPFP_I64_Predicate_imm0_7: {
645
646  return Imm >= 0 && Imm < 8;
647
648    llvm_unreachable("ImmediateCode should have returned");
649    return false;
650  }
651  case GIPFP_I64_Predicate_imm16: {
652     return Imm == 16;
653    llvm_unreachable("ImmediateCode should have returned");
654    return false;
655  }
656  case GIPFP_I64_Predicate_imm16_31: {
657
658  return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
659
660    llvm_unreachable("ImmediateCode should have returned");
661    return false;
662  }
663  case GIPFP_I64_Predicate_imm1_15: {
664     return Imm > 0 && Imm < 16;
665    llvm_unreachable("ImmediateCode should have returned");
666    return false;
667  }
668  case GIPFP_I64_Predicate_imm1_16: {
669
670    return Imm > 0 && Imm <= 16;
671
672    llvm_unreachable("ImmediateCode should have returned");
673    return false;
674  }
675  case GIPFP_I64_Predicate_imm1_31: {
676     return Imm > 0 && Imm < 32;
677    llvm_unreachable("ImmediateCode should have returned");
678    return false;
679  }
680  case GIPFP_I64_Predicate_imm1_7: {
681     return Imm > 0 && Imm < 8;
682    llvm_unreachable("ImmediateCode should have returned");
683    return false;
684  }
685  case GIPFP_I64_Predicate_imm24b: {
686
687  return Imm >= 0 && Imm <= 0xffffff;
688
689    llvm_unreachable("ImmediateCode should have returned");
690    return false;
691  }
692  case GIPFP_I64_Predicate_imm256_510: {
693
694  return Imm >= 256 && Imm < 511;
695
696    llvm_unreachable("ImmediateCode should have returned");
697    return false;
698  }
699  case GIPFP_I64_Predicate_imm32: {
700     return Imm == 32;
701    llvm_unreachable("ImmediateCode should have returned");
702    return false;
703  }
704  case GIPFP_I64_Predicate_imm8: {
705     return Imm == 8;
706    llvm_unreachable("ImmediateCode should have returned");
707    return false;
708  }
709  case GIPFP_I64_Predicate_imm8_255: {
710
711  return Imm >= 8 && Imm < 256;
712
713    llvm_unreachable("ImmediateCode should have returned");
714    return false;
715  }
716  case GIPFP_I64_Predicate_imm8_or_16: {
717     return Imm == 8 || Imm == 16;
718    llvm_unreachable("ImmediateCode should have returned");
719    return false;
720  }
721  case GIPFP_I64_Predicate_imm_11b: {
722    { return Imm >= 0 && Imm < (1 << 11); }
723    llvm_unreachable("ImmediateCode should have returned");
724    return false;
725  }
726  case GIPFP_I64_Predicate_imm_12b: {
727    { return Imm >= 0 && Imm < (1 << 12); }
728    llvm_unreachable("ImmediateCode should have returned");
729    return false;
730  }
731  case GIPFP_I64_Predicate_imm_13b: {
732    { return Imm >= 0 && Imm < (1 << 13); }
733    llvm_unreachable("ImmediateCode should have returned");
734    return false;
735  }
736  case GIPFP_I64_Predicate_imm_3b: {
737    { return Imm >= 0 && Imm < (1 << 3); }
738    llvm_unreachable("ImmediateCode should have returned");
739    return false;
740  }
741  case GIPFP_I64_Predicate_imm_4b: {
742    { return Imm >= 0 && Imm < (1 << 4); }
743    llvm_unreachable("ImmediateCode should have returned");
744    return false;
745  }
746  case GIPFP_I64_Predicate_imm_6b: {
747    { return Imm >= 0 && Imm < (1 << 6); }
748    llvm_unreachable("ImmediateCode should have returned");
749    return false;
750  }
751  case GIPFP_I64_Predicate_imm_7b: {
752    { return Imm >= 0 && Imm < (1 << 7); }
753    llvm_unreachable("ImmediateCode should have returned");
754    return false;
755  }
756  case GIPFP_I64_Predicate_imm_9b: {
757    { return Imm >= 0 && Imm < (1 << 9); }
758    llvm_unreachable("ImmediateCode should have returned");
759    return false;
760  }
761  case GIPFP_I64_Predicate_imm_even: {
762     return (Imm & 1) == 0;
763    llvm_unreachable("ImmediateCode should have returned");
764    return false;
765  }
766  case GIPFP_I64_Predicate_imm_odd: {
767     return (Imm & 1) == 1;
768    llvm_unreachable("ImmediateCode should have returned");
769    return false;
770  }
771  case GIPFP_I64_Predicate_long_shift: {
772     return Imm > 0 && Imm <= 32;
773    llvm_unreachable("ImmediateCode should have returned");
774    return false;
775  }
776  case GIPFP_I64_Predicate_mod_imm: {
777
778    return ARM_AM::getSOImmVal(Imm) != -1;
779
780    llvm_unreachable("ImmediateCode should have returned");
781    return false;
782  }
783  case GIPFP_I64_Predicate_pkh_asr_amt: {
784     return Imm > 0 && Imm <= 32;
785    llvm_unreachable("ImmediateCode should have returned");
786    return false;
787  }
788  case GIPFP_I64_Predicate_pkh_lsl_amt: {
789     return Imm >= 0 && Imm < 32;
790    llvm_unreachable("ImmediateCode should have returned");
791    return false;
792  }
793  case GIPFP_I64_Predicate_shr_imm16: {
794     return Imm > 0 && Imm <= 16;
795    llvm_unreachable("ImmediateCode should have returned");
796    return false;
797  }
798  case GIPFP_I64_Predicate_shr_imm32: {
799     return Imm > 0 && Imm <= 32;
800    llvm_unreachable("ImmediateCode should have returned");
801    return false;
802  }
803  case GIPFP_I64_Predicate_shr_imm64: {
804     return Imm > 0 && Imm <= 64;
805    llvm_unreachable("ImmediateCode should have returned");
806    return false;
807  }
808  case GIPFP_I64_Predicate_shr_imm8: {
809     return Imm > 0 && Imm <= 8;
810    llvm_unreachable("ImmediateCode should have returned");
811    return false;
812  }
813  case GIPFP_I64_Predicate_t2_so_imm: {
814
815    return ARM_AM::getT2SOImmVal(Imm) != -1;
816
817    llvm_unreachable("ImmediateCode should have returned");
818    return false;
819  }
820  case GIPFP_I64_Predicate_t2_so_imm_neg: {
821
822  return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
823
824    llvm_unreachable("ImmediateCode should have returned");
825    return false;
826  }
827  }
828  llvm_unreachable("Unknown predicate");
829  return false;
830}
831bool ARMInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
832  llvm_unreachable("Unknown predicate");
833  return false;
834}
835// PatFrag predicates.
836enum {
837  GIPFP_APInt_Predicate_arm_i32imm = GIPFP_APInt_Invalid + 1,
838};
839bool ARMInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
840  switch (PredicateID) {
841  case GIPFP_APInt_Predicate_arm_i32imm: {
842
843  if (Subtarget->useMovt())
844    return true;
845  if (ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue()))
846    return true;
847  return ARM_AM::isSOImmTwoPartValNeg(Imm.getZExtValue());
848
849    llvm_unreachable("ImmediateCode should have returned");
850    return false;
851  }
852  }
853  llvm_unreachable("Unknown predicate");
854  return false;
855}
856// PatFrag predicates.
857enum {
858  GIPFP_MI_Predicate_bf_inv_mask_imm = GIPFP_MI_Invalid + 1,
859  GIPFP_MI_Predicate_vfp_f32imm,
860  GIPFP_MI_Predicate_vfp_f64imm,
861};
862bool ARMInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const std::array<const MachineOperand *, 3> &Operands) const {
863  const MachineFunction &MF = *MI.getParent()->getParent();
864  const MachineRegisterInfo &MRI = MF.getRegInfo();
865  (void)MRI;
866  switch (PredicateID) {
867  case GIPFP_MI_Predicate_bf_inv_mask_imm: {
868
869    // There's better methods of implementing this check. IntImmLeaf<> would be
870    // equivalent and have less boilerplate but we need a test for C++
871    // predicates and this one causes new rules to be imported into GlobalISel
872    // without requiring additional features first.
873    const auto &MO = MI.getOperand(1);
874    if (!MO.isCImm())
875      return false;
876    return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue());
877
878    llvm_unreachable("GISelPredicateCode should have returned");
879    return false;
880  }
881  case GIPFP_MI_Predicate_vfp_f32imm: {
882
883      const auto &MO = MI.getOperand(1);
884      if (!MO.isFPImm())
885        return false;
886      return ARM_AM::getFP32Imm(MO.getFPImm()->getValueAPF()) != -1;
887
888    llvm_unreachable("GISelPredicateCode should have returned");
889    return false;
890  }
891  case GIPFP_MI_Predicate_vfp_f64imm: {
892
893      const auto &MO = MI.getOperand(1);
894      if (!MO.isFPImm())
895        return false;
896      return ARM_AM::getFP64Imm(MO.getFPImm()->getValueAPF()) != -1;
897
898    llvm_unreachable("GISelPredicateCode should have returned");
899    return false;
900  }
901  }
902  llvm_unreachable("Unknown predicate");
903  return false;
904}
905
906ARMInstructionSelector::ComplexMatcherMemFn
907ARMInstructionSelector::ComplexPredicateFns[] = {
908  nullptr, // GICP_Invalid
909};
910
911// Custom renderers.
912enum {
913  GICR_Invalid,
914  GICR_renderVFPF32Imm,
915  GICR_renderVFPF64Imm,
916};
917ARMInstructionSelector::CustomRendererFn
918ARMInstructionSelector::CustomRenderers[] = {
919  nullptr, // GICR_Invalid
920  &ARMInstructionSelector::renderVFPF32Imm,
921  &ARMInstructionSelector::renderVFPF64Imm,
922};
923
924bool ARMInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
925  MachineFunction &MF = *I.getParent()->getParent();
926  MachineRegisterInfo &MRI = MF.getRegInfo();
927  const PredicateBitset AvailableFeatures = getAvailableFeatures();
928  NewMIVector OutMIs;
929  State.MIs.clear();
930  State.MIs.push_back(&I);
931
932  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
933    return true;
934  }
935
936  return false;
937}
938
939const int64_t *ARMInstructionSelector::getMatchTable() const {
940  constexpr static int64_t MatchTable0[] = {
941    GIM_SwitchOpcode, /*MI*/0, /*[*/46, 216, /*)*//*default:*//*Label 65*/ 129518,
942    /*TargetOpcode::G_ADD*//*Label 0*/ 175,
943    /*TargetOpcode::G_SUB*//*Label 1*/ 8383,
944    /*TargetOpcode::G_MUL*//*Label 2*/ 11424,
945    /*TargetOpcode::G_SDIV*//*Label 3*/ 12269,
946    /*TargetOpcode::G_UDIV*//*Label 4*/ 12371, 0, 0, 0, 0,
947    /*TargetOpcode::G_AND*//*Label 5*/ 12473,
948    /*TargetOpcode::G_OR*//*Label 6*/ 15233,
949    /*TargetOpcode::G_XOR*//*Label 7*/ 20473, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
950    /*TargetOpcode::G_CONCAT_VECTORS*//*Label 8*/ 21991, 0, 0,
951    /*TargetOpcode::G_BITCAST*//*Label 9*/ 22385, 0, 0,
952    /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 10*/ 33295,
953    /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 11*/ 33551, 0, 0, 0, 0,
954    /*TargetOpcode::G_SEXTLOAD*//*Label 12*/ 33759, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
955    /*TargetOpcode::G_FENCE*//*Label 13*/ 33905, 0, 0, 0,
956    /*TargetOpcode::G_INTRINSIC*//*Label 14*/ 33927,
957    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 15*/ 94676,
958    /*TargetOpcode::G_ANYEXT*//*Label 16*/ 103121,
959    /*TargetOpcode::G_TRUNC*//*Label 17*/ 103256,
960    /*TargetOpcode::G_CONSTANT*//*Label 18*/ 103391,
961    /*TargetOpcode::G_FCONSTANT*//*Label 19*/ 103588, 0, 0,
962    /*TargetOpcode::G_SEXT*//*Label 20*/ 103667, 0,
963    /*TargetOpcode::G_ZEXT*//*Label 21*/ 103802,
964    /*TargetOpcode::G_SHL*//*Label 22*/ 104324,
965    /*TargetOpcode::G_LSHR*//*Label 23*/ 104433,
966    /*TargetOpcode::G_ASHR*//*Label 24*/ 104493, 0, 0,
967    /*TargetOpcode::G_ROTR*//*Label 25*/ 104711, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
968    /*TargetOpcode::G_UMULH*//*Label 26*/ 104979,
969    /*TargetOpcode::G_SMULH*//*Label 27*/ 105204,
970    /*TargetOpcode::G_UADDSAT*//*Label 28*/ 105534,
971    /*TargetOpcode::G_SADDSAT*//*Label 29*/ 106163,
972    /*TargetOpcode::G_USUBSAT*//*Label 30*/ 107430,
973    /*TargetOpcode::G_SSUBSAT*//*Label 31*/ 108059, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
974    /*TargetOpcode::G_FADD*//*Label 32*/ 109054,
975    /*TargetOpcode::G_FSUB*//*Label 33*/ 111200,
976    /*TargetOpcode::G_FMUL*//*Label 34*/ 112758,
977    /*TargetOpcode::G_FMA*//*Label 35*/ 113696, 0,
978    /*TargetOpcode::G_FDIV*//*Label 36*/ 115397, 0, 0, 0, 0, 0, 0, 0, 0,
979    /*TargetOpcode::G_FNEG*//*Label 37*/ 115563,
980    /*TargetOpcode::G_FPEXT*//*Label 38*/ 116881,
981    /*TargetOpcode::G_FPTRUNC*//*Label 39*/ 117085,
982    /*TargetOpcode::G_FPTOSI*//*Label 40*/ 117325,
983    /*TargetOpcode::G_FPTOUI*//*Label 41*/ 118564,
984    /*TargetOpcode::G_SITOFP*//*Label 42*/ 119803,
985    /*TargetOpcode::G_UITOFP*//*Label 43*/ 120385,
986    /*TargetOpcode::G_FABS*//*Label 44*/ 120967, 0, 0, 0,
987    /*TargetOpcode::G_FMINNUM*//*Label 45*/ 121567,
988    /*TargetOpcode::G_FMAXNUM*//*Label 46*/ 122087, 0, 0,
989    /*TargetOpcode::G_FMINIMUM*//*Label 47*/ 122607,
990    /*TargetOpcode::G_FMAXIMUM*//*Label 48*/ 123261, 0, 0,
991    /*TargetOpcode::G_SMIN*//*Label 49*/ 123915,
992    /*TargetOpcode::G_SMAX*//*Label 50*/ 124438,
993    /*TargetOpcode::G_UMIN*//*Label 51*/ 124961,
994    /*TargetOpcode::G_UMAX*//*Label 52*/ 125850,
995    /*TargetOpcode::G_ABS*//*Label 53*/ 126739, 0, 0,
996    /*TargetOpcode::G_BR*//*Label 54*/ 127168, 0, 0,
997    /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 55*/ 127232, 0, 0, 0,
998    /*TargetOpcode::G_CTLZ*//*Label 56*/ 127374, 0,
999    /*TargetOpcode::G_CTPOP*//*Label 57*/ 127882,
1000    /*TargetOpcode::G_BSWAP*//*Label 58*/ 127974,
1001    /*TargetOpcode::G_BITREVERSE*//*Label 59*/ 128222,
1002    /*TargetOpcode::G_FCEIL*//*Label 60*/ 128586, 0, 0,
1003    /*TargetOpcode::G_FSQRT*//*Label 61*/ 128794,
1004    /*TargetOpcode::G_FFLOOR*//*Label 62*/ 128924,
1005    /*TargetOpcode::G_FRINT*//*Label 63*/ 129132,
1006    /*TargetOpcode::G_FNEARBYINT*//*Label 64*/ 129388,
1007    // Label 0: @175
1008    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 16, /*)*//*default:*//*Label 75*/ 8382,
1009    /*GILLT_s32*//*Label 66*/ 196,
1010    /*GILLT_s64*//*Label 67*/ 2179, 0,
1011    /*GILLT_v2s32*//*Label 68*/ 2231,
1012    /*GILLT_v2s64*//*Label 69*/ 2698, 0,
1013    /*GILLT_v4s16*//*Label 70*/ 3726,
1014    /*GILLT_v4s32*//*Label 71*/ 4193, 0, 0,
1015    /*GILLT_v8s8*//*Label 72*/ 5778,
1016    /*GILLT_v8s16*//*Label 73*/ 6245, 0, 0,
1017    /*GILLT_v16s8*//*Label 74*/ 7830,
1018    // Label 66: @196
1019    GIM_Try, /*On fail goto*//*Label 76*/ 2178,
1020      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1021      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1022      GIM_Try, /*On fail goto*//*Label 77*/ 273, // Rule ID 5770 //
1023        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
1024        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1025        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1026        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1027        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1028        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1029        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1030        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
1031        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1032        GIM_CheckIsSafeToFold, /*InsnID*/1,
1033        // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1034        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB,
1035        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1036        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1037        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1038        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
1039        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1040        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1041        GIR_EraseFromParent, /*InsnID*/0,
1042        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1043        // GIR_Coverage, 5770,
1044        GIR_Done,
1045      // Label 77: @273
1046      GIM_Try, /*On fail goto*//*Label 78*/ 340, // Rule ID 5771 //
1047        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
1048        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1049        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1050        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1051        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1052        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1053        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1054        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
1055        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1056        GIM_CheckIsSafeToFold, /*InsnID*/1,
1057        // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1058        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAH,
1059        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1060        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1061        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1062        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
1063        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1064        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1065        GIR_EraseFromParent, /*InsnID*/0,
1066        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1067        // GIR_Coverage, 5771,
1068        GIR_Done,
1069      // Label 78: @340
1070      GIM_Try, /*On fail goto*//*Label 79*/ 407, // Rule ID 5805 //
1071        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
1072        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1073        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1074        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1075        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1076        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1077        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1078        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
1079        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1080        GIM_CheckIsSafeToFold, /*InsnID*/1,
1081        // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1082        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB,
1083        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1084        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1085        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1086        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
1087        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1088        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1089        GIR_EraseFromParent, /*InsnID*/0,
1090        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1091        // GIR_Coverage, 5805,
1092        GIR_Done,
1093      // Label 79: @407
1094      GIM_Try, /*On fail goto*//*Label 80*/ 474, // Rule ID 5806 //
1095        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
1096        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1097        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1098        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1099        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1100        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1101        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1102        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
1103        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1104        GIM_CheckIsSafeToFold, /*InsnID*/1,
1105        // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1106        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAH,
1107        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1108        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1109        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1110        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
1111        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1112        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1113        GIR_EraseFromParent, /*InsnID*/0,
1114        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1115        // GIR_Coverage, 5806,
1116        GIR_Done,
1117      // Label 80: @474
1118      GIM_Try, /*On fail goto*//*Label 81*/ 541, // Rule ID 2015 //
1119        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
1120        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1121        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1122        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1123        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1124        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1125        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1126        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1127        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
1128        GIM_CheckIsSafeToFold, /*InsnID*/1,
1129        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }))  =>  (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1130        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB,
1131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1132        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1133        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1134        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
1135        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1136        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1137        GIR_EraseFromParent, /*InsnID*/0,
1138        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1139        // GIR_Coverage, 2015,
1140        GIR_Done,
1141      // Label 81: @541
1142      GIM_Try, /*On fail goto*//*Label 82*/ 608, // Rule ID 2016 //
1143        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
1144        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1145        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1146        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1147        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1148        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1149        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1150        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1151        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
1152        GIM_CheckIsSafeToFold, /*InsnID*/1,
1153        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }))  =>  (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1154        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAH,
1155        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1156        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1157        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1158        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
1159        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1160        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1161        GIR_EraseFromParent, /*InsnID*/0,
1162        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1163        // GIR_Coverage, 2016,
1164        GIR_Done,
1165      // Label 82: @608
1166      GIM_Try, /*On fail goto*//*Label 83*/ 675, // Rule ID 2239 //
1167        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
1168        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1169        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1170        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1171        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1172        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1173        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1174        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1175        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
1176        GIM_CheckIsSafeToFold, /*InsnID*/1,
1177        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }))  =>  (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1178        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB,
1179        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1180        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1181        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1182        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
1183        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1184        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1185        GIR_EraseFromParent, /*InsnID*/0,
1186        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1187        // GIR_Coverage, 2239,
1188        GIR_Done,
1189      // Label 83: @675
1190      GIM_Try, /*On fail goto*//*Label 84*/ 742, // Rule ID 2240 //
1191        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
1192        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1193        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1194        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1195        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1196        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1197        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1198        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1199        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
1200        GIM_CheckIsSafeToFold, /*InsnID*/1,
1201        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }))  =>  (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1202        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAH,
1203        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1204        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1205        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1206        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
1207        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1208        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1209        GIR_EraseFromParent, /*InsnID*/0,
1210        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1211        // GIR_Coverage, 2240,
1212        GIR_Done,
1213      // Label 84: @742
1214      GIM_Try, /*On fail goto*//*Label 85*/ 852, // Rule ID 5549 //
1215        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM_UseMulOps,
1216        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1217        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1218        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1219        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1220        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1221        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1222        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1223        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1224        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1225        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1226        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1227        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1228        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1229        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1230        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1231        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1232        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1233        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1234        GIM_CheckIsSafeToFold, /*InsnID*/1,
1235        GIM_CheckIsSafeToFold, /*InsnID*/2,
1236        GIM_CheckIsSafeToFold, /*InsnID*/3,
1237        // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra)  =>  (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1238        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
1239        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1240        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1241        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1242        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1243        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1244        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1245        GIR_EraseFromParent, /*InsnID*/0,
1246        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1247        // GIR_Coverage, 5549,
1248        GIR_Done,
1249      // Label 85: @852
1250      GIM_Try, /*On fail goto*//*Label 86*/ 962, // Rule ID 5586 //
1251        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
1252        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1253        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1254        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1255        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1256        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1257        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1258        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1259        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1260        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1261        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1262        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1263        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1264        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1265        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1266        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1267        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1268        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1269        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1270        GIM_CheckIsSafeToFold, /*InsnID*/1,
1271        GIM_CheckIsSafeToFold, /*InsnID*/2,
1272        GIM_CheckIsSafeToFold, /*InsnID*/3,
1273        // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1274        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
1275        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1276        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1277        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1278        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1279        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1280        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1281        GIR_EraseFromParent, /*InsnID*/0,
1282        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1283        // GIR_Coverage, 5586,
1284        GIR_Done,
1285      // Label 86: @962
1286      GIM_Try, /*On fail goto*//*Label 87*/ 1072, // Rule ID 192 //
1287        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM_UseMulOps,
1288        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1289        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1290        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1291        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1292        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1293        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1294        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1295        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1296        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1297        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1298        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1299        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1300        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1301        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1302        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1303        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1304        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1305        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1306        GIM_CheckIsSafeToFold, /*InsnID*/1,
1307        GIM_CheckIsSafeToFold, /*InsnID*/2,
1308        GIM_CheckIsSafeToFold, /*InsnID*/3,
1309        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })))  =>  (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1310        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
1311        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1312        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1313        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1314        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1315        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1316        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1317        GIR_EraseFromParent, /*InsnID*/0,
1318        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1319        // GIR_Coverage, 192,
1320        GIR_Done,
1321      // Label 87: @1072
1322      GIM_Try, /*On fail goto*//*Label 88*/ 1182, // Rule ID 528 //
1323        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
1324        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1325        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1326        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1327        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1328        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1329        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1330        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1331        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1332        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1333        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1334        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1335        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1336        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1337        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1338        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1339        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1340        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1341        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1342        GIM_CheckIsSafeToFold, /*InsnID*/1,
1343        GIM_CheckIsSafeToFold, /*InsnID*/2,
1344        GIM_CheckIsSafeToFold, /*InsnID*/3,
1345        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })))  =>  (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1346        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
1347        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1348        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1349        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1350        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1351        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1352        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1353        GIR_EraseFromParent, /*InsnID*/0,
1354        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1355        // GIR_Coverage, 528,
1356        GIR_Done,
1357      // Label 88: @1182
1358      GIM_Try, /*On fail goto*//*Label 89*/ 1236, // Rule ID 72 //
1359        GIM_CheckFeatures, GIFBS_IsARM,
1360        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
1361        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1362        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1363        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1364        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
1365        // MIs[1] Operand 1
1366        // No operand predicates
1367        GIM_CheckIsSafeToFold, /*InsnID*/1,
1368        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (ADDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1369        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ADDri,
1370        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1371        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1372        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1373        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1374        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1375        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1376        GIR_EraseFromParent, /*InsnID*/0,
1377        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1378        // GIR_Coverage, 72,
1379        GIR_Done,
1380      // Label 89: @1236
1381      GIM_Try, /*On fail goto*//*Label 90*/ 1290, // Rule ID 414 //
1382        GIM_CheckFeatures, GIFBS_IsThumb2,
1383        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1384        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1385        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1386        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1387        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
1388        // MIs[1] Operand 1
1389        // No operand predicates
1390        GIM_CheckIsSafeToFold, /*InsnID*/1,
1391        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2ADDri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1392        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDri,
1393        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1394        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1395        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1396        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1397        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1398        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1399        GIR_EraseFromParent, /*InsnID*/0,
1400        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1401        // GIR_Coverage, 414,
1402        GIR_Done,
1403      // Label 90: @1290
1404      GIM_Try, /*On fail goto*//*Label 91*/ 1340, // Rule ID 415 //
1405        GIM_CheckFeatures, GIFBS_IsThumb2,
1406        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1407        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1408        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1409        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1410        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_4095,
1411        // MIs[1] Operand 1
1412        // No operand predicates
1413        GIM_CheckIsSafeToFold, /*InsnID*/1,
1414        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm)  =>  (t2ADDri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1415        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDri12,
1416        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1417        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1418        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1419        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1420        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1421        GIR_EraseFromParent, /*InsnID*/0,
1422        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1423        // GIR_Coverage, 415,
1424        GIR_Done,
1425      // Label 91: @1340
1426      GIM_Try, /*On fail goto*//*Label 92*/ 1412, // Rule ID 171 //
1427        GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
1428        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1429        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1430        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1431        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1432        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1433        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1434        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1435        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1436        GIM_CheckIsSafeToFold, /*InsnID*/1,
1437        // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra)  =>  (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1438        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLA,
1439        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1440        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1441        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1442        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1443        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1444        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1445        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1446        GIR_EraseFromParent, /*InsnID*/0,
1447        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1448        // GIR_Coverage, 171,
1449        GIR_Done,
1450      // Label 92: @1412
1451      GIM_Try, /*On fail goto*//*Label 93*/ 1484, // Rule ID 172 //
1452        GIM_CheckFeatures, GIFBS_IsARM_NoV6,
1453        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1454        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1455        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1456        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1457        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1458        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1459        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1460        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1461        GIM_CheckIsSafeToFold, /*InsnID*/1,
1462        // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra)  =>  (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1463        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLAv5,
1464        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1465        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1466        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1467        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1468        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1469        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1470        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1471        GIR_EraseFromParent, /*InsnID*/0,
1472        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1473        // GIR_Coverage, 172,
1474        GIR_Done,
1475      // Label 93: @1484
1476      GIM_Try, /*On fail goto*//*Label 94*/ 1552, // Rule ID 510 //
1477        GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
1478        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1479        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1480        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1481        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1482        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1483        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1484        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1485        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1486        GIM_CheckIsSafeToFold, /*InsnID*/1,
1487        // (add:{ *:[i32] } (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Ra)  =>  (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1488        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLA,
1489        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1490        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1491        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1492        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1493        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1494        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1495        GIR_EraseFromParent, /*InsnID*/0,
1496        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1497        // GIR_Coverage, 510,
1498        GIR_Done,
1499      // Label 94: @1552
1500      GIM_Try, /*On fail goto*//*Label 95*/ 1620, // Rule ID 180 //
1501        GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
1502        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
1503        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1504        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SMULH,
1505        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1506        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1507        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1508        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1509        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1510        GIM_CheckIsSafeToFold, /*InsnID*/1,
1511        // (add:{ *:[i32] } (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm), GPR:{ *:[i32] }:$Ra)  =>  (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1512        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMMLA,
1513        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1514        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1515        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1516        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1517        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1518        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1519        GIR_EraseFromParent, /*InsnID*/0,
1520        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1521        // GIR_Coverage, 180,
1522        GIR_Done,
1523      // Label 95: @1620
1524      GIM_Try, /*On fail goto*//*Label 96*/ 1688, // Rule ID 516 //
1525        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
1526        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1527        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1528        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SMULH,
1529        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1530        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1531        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1532        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1533        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1534        GIM_CheckIsSafeToFold, /*InsnID*/1,
1535        // (add:{ *:[i32] } (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Ra)  =>  (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1536        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMMLA,
1537        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1538        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1539        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1540        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1541        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1542        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1543        GIR_EraseFromParent, /*InsnID*/0,
1544        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1545        // GIR_Coverage, 516,
1546        GIR_Done,
1547      // Label 96: @1688
1548      GIM_Try, /*On fail goto*//*Label 97*/ 1760, // Rule ID 5543 //
1549        GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
1550        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1551        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1552        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1553        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1554        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1555        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1556        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1557        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1558        GIM_CheckIsSafeToFold, /*InsnID*/1,
1559        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm))  =>  (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1560        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLA,
1561        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1562        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1563        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1564        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1565        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1566        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1567        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1568        GIR_EraseFromParent, /*InsnID*/0,
1569        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1570        // GIR_Coverage, 5543,
1571        GIR_Done,
1572      // Label 97: @1760
1573      GIM_Try, /*On fail goto*//*Label 98*/ 1832, // Rule ID 5544 //
1574        GIM_CheckFeatures, GIFBS_IsARM_NoV6,
1575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1576        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1577        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1578        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1579        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1580        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1581        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1582        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1583        GIM_CheckIsSafeToFold, /*InsnID*/1,
1584        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm))  =>  (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1585        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLAv5,
1586        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1587        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1588        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1589        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1590        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1591        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1592        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1593        GIR_EraseFromParent, /*InsnID*/0,
1594        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1595        // GIR_Coverage, 5544,
1596        GIR_Done,
1597      // Label 98: @1832
1598      GIM_Try, /*On fail goto*//*Label 99*/ 1900, // Rule ID 5581 //
1599        GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
1600        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1601        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1602        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1603        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1604        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1605        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1606        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1607        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1608        GIM_CheckIsSafeToFold, /*InsnID*/1,
1609        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm))  =>  (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1610        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLA,
1611        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1612        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1613        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1614        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1615        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1616        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1617        GIR_EraseFromParent, /*InsnID*/0,
1618        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1619        // GIR_Coverage, 5581,
1620        GIR_Done,
1621      // Label 99: @1900
1622      GIM_Try, /*On fail goto*//*Label 100*/ 1968, // Rule ID 5545 //
1623        GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
1624        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
1625        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1626        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1627        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SMULH,
1628        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1629        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1630        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1631        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1632        GIM_CheckIsSafeToFold, /*InsnID*/1,
1633        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm))  =>  (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1634        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMMLA,
1635        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1636        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1637        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1638        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1639        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1640        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1641        GIR_EraseFromParent, /*InsnID*/0,
1642        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1643        // GIR_Coverage, 5545,
1644        GIR_Done,
1645      // Label 100: @1968
1646      GIM_Try, /*On fail goto*//*Label 101*/ 2036, // Rule ID 5582 //
1647        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
1648        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1649        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1650        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1651        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SMULH,
1652        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1653        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1654        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1655        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1656        GIM_CheckIsSafeToFold, /*InsnID*/1,
1657        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn))  =>  (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1658        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMMLA,
1659        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1660        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1661        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1662        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1663        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1664        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1665        GIR_EraseFromParent, /*InsnID*/0,
1666        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1667        // GIR_Coverage, 5582,
1668        GIR_Done,
1669      // Label 101: @2036
1670      GIM_Try, /*On fail goto*//*Label 102*/ 2083, // Rule ID 73 //
1671        GIM_CheckFeatures, GIFBS_IsARM,
1672        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
1673        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1674        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1675        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (ADDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
1676        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ADDrr,
1677        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1678        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1679        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
1680        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1681        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1682        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1683        GIR_EraseFromParent, /*InsnID*/0,
1684        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1685        // GIR_Coverage, 73,
1686        GIR_Done,
1687      // Label 102: @2083
1688      GIM_Try, /*On fail goto*//*Label 103*/ 2130, // Rule ID 416 //
1689        GIM_CheckFeatures, GIFBS_IsThumb2,
1690        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1691        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1692        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1693        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
1694        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDrr,
1695        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1696        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1697        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
1698        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1699        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1700        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1701        GIR_EraseFromParent, /*InsnID*/0,
1702        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1703        // GIR_Coverage, 416,
1704        GIR_Done,
1705      // Label 103: @2130
1706      GIM_Try, /*On fail goto*//*Label 104*/ 2177, // Rule ID 5563 //
1707        GIM_CheckFeatures, GIFBS_IsThumb2,
1708        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1709        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1710        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1711        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)  =>  (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
1712        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDrr,
1713        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1714        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1715        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
1716        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1717        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1718        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1719        GIR_EraseFromParent, /*InsnID*/0,
1720        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1721        // GIR_Coverage, 5563,
1722        GIR_Done,
1723      // Label 104: @2177
1724      GIM_Reject,
1725    // Label 76: @2178
1726    GIM_Reject,
1727    // Label 67: @2179
1728    GIM_Try, /*On fail goto*//*Label 105*/ 2230, // Rule ID 778 //
1729      GIM_CheckFeatures, GIFBS_HasNEON,
1730      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1731      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1732      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
1733      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1734      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1735      // (add:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VADDv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
1736      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv1i64,
1737      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1738      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1739      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
1740      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1741      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1742      GIR_EraseFromParent, /*InsnID*/0,
1743      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1744      // GIR_Coverage, 778,
1745      GIR_Done,
1746    // Label 105: @2230
1747    GIM_Reject,
1748    // Label 68: @2231
1749    GIM_Try, /*On fail goto*//*Label 106*/ 2697,
1750      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1751      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
1752      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
1753      GIM_Try, /*On fail goto*//*Label 107*/ 2316, // Rule ID 5702 //
1754        GIM_CheckFeatures, GIFBS_HasNEON,
1755        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1756        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1757        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1758        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
1759        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1760        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1761        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1762        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1763        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1764        GIM_CheckIsSafeToFold, /*InsnID*/1,
1765        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 2574:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1)  =>  (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1766        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv2i32,
1767        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1768        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1769        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1770        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1771        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1772        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1773        GIR_EraseFromParent, /*InsnID*/0,
1774        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1775        // GIR_Coverage, 5702,
1776        GIR_Done,
1777      // Label 107: @2316
1778      GIM_Try, /*On fail goto*//*Label 108*/ 2387, // Rule ID 5708 //
1779        GIM_CheckFeatures, GIFBS_HasNEON,
1780        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1781        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1782        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1783        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
1784        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1785        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1786        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1787        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1788        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1789        GIM_CheckIsSafeToFold, /*InsnID*/1,
1790        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 2575:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1)  =>  (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1791        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv2i32,
1792        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1793        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1794        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1795        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1796        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1797        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1798        GIR_EraseFromParent, /*InsnID*/0,
1799        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1800        // GIR_Coverage, 5708,
1801        GIR_Done,
1802      // Label 108: @2387
1803      GIM_Try, /*On fail goto*//*Label 109*/ 2458, // Rule ID 1199 //
1804        GIM_CheckFeatures, GIFBS_HasNEON,
1805        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1806        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1807        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1808        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1809        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
1810        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1811        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1812        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1813        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1814        GIM_CheckIsSafeToFold, /*InsnID*/1,
1815        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 2574:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1816        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv2i32,
1817        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1818        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1819        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1820        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1821        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1822        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1823        GIR_EraseFromParent, /*InsnID*/0,
1824        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1825        // GIR_Coverage, 1199,
1826        GIR_Done,
1827      // Label 109: @2458
1828      GIM_Try, /*On fail goto*//*Label 110*/ 2529, // Rule ID 1205 //
1829        GIM_CheckFeatures, GIFBS_HasNEON,
1830        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1831        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1832        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1833        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1834        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
1835        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1836        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1837        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1838        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1839        GIM_CheckIsSafeToFold, /*InsnID*/1,
1840        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 2575:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1841        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv2i32,
1842        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1843        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1844        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1845        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1846        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1847        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1848        GIR_EraseFromParent, /*InsnID*/0,
1849        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1850        // GIR_Coverage, 1205,
1851        GIR_Done,
1852      // Label 110: @2529
1853      GIM_Try, /*On fail goto*//*Label 111*/ 2593, // Rule ID 5632 //
1854        GIM_CheckFeatures, GIFBS_HasNEON,
1855        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1856        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1857        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1858        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1859        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1860        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1861        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1862        GIM_CheckIsSafeToFold, /*InsnID*/1,
1863        // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1)  =>  (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1864        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv2i32,
1865        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1866        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1867        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1868        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1869        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1870        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1871        GIR_EraseFromParent, /*InsnID*/0,
1872        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1873        // GIR_Coverage, 5632,
1874        GIR_Done,
1875      // Label 111: @2593
1876      GIM_Try, /*On fail goto*//*Label 112*/ 2657, // Rule ID 905 //
1877        GIM_CheckFeatures, GIFBS_HasNEON,
1878        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1879        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1880        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1881        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1882        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1883        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1884        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1885        GIM_CheckIsSafeToFold, /*InsnID*/1,
1886        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1887        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv2i32,
1888        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1889        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1890        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1891        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1892        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1893        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1894        GIR_EraseFromParent, /*InsnID*/0,
1895        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1896        // GIR_Coverage, 905,
1897        GIR_Done,
1898      // Label 112: @2657
1899      GIM_Try, /*On fail goto*//*Label 113*/ 2696, // Rule ID 774 //
1900        GIM_CheckFeatures, GIFBS_HasNEON,
1901        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1902        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1903        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VADDv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1904        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv2i32,
1905        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1906        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1907        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
1908        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1909        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1910        GIR_EraseFromParent, /*InsnID*/0,
1911        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1912        // GIR_Coverage, 774,
1913        GIR_Done,
1914      // Label 113: @2696
1915      GIM_Reject,
1916    // Label 106: @2697
1917    GIM_Reject,
1918    // Label 69: @2698
1919    GIM_Try, /*On fail goto*//*Label 114*/ 3725,
1920      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1921      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1922      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
1923      GIM_Try, /*On fail goto*//*Label 115*/ 2796, // Rule ID 5714 //
1924        GIM_CheckFeatures, GIFBS_HasNEON,
1925        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1926        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1927        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1928        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1929        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1930        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1931        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
1932        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1933        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1934        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1935        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1936        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1937        GIM_CheckIsSafeToFold, /*InsnID*/1,
1938        GIM_CheckIsSafeToFold, /*InsnID*/2,
1939        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 2574:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1)  =>  (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1940        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv2i64,
1941        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1942        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1943        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1944        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1945        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1946        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1947        GIR_EraseFromParent, /*InsnID*/0,
1948        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1949        // GIR_Coverage, 5714,
1950        GIR_Done,
1951      // Label 115: @2796
1952      GIM_Try, /*On fail goto*//*Label 116*/ 2880, // Rule ID 5717 //
1953        GIM_CheckFeatures, GIFBS_HasNEON,
1954        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1955        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1956        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1957        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1958        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1959        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1960        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
1961        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1962        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1963        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1964        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1965        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1966        GIM_CheckIsSafeToFold, /*InsnID*/1,
1967        GIM_CheckIsSafeToFold, /*InsnID*/2,
1968        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 2575:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1)  =>  (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1969        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv2i64,
1970        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1971        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1972        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1973        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1974        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1975        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1976        GIR_EraseFromParent, /*InsnID*/0,
1977        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1978        // GIR_Coverage, 5717,
1979        GIR_Done,
1980      // Label 116: @2880
1981      GIM_Try, /*On fail goto*//*Label 117*/ 2964, // Rule ID 1211 //
1982        GIM_CheckFeatures, GIFBS_HasNEON,
1983        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1984        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1985        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1986        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1987        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1988        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1989        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1990        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
1991        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1992        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1993        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1994        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1995        GIM_CheckIsSafeToFold, /*InsnID*/1,
1996        GIM_CheckIsSafeToFold, /*InsnID*/2,
1997        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 2574:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)))  =>  (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1998        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv2i64,
1999        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2000        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2001        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2002        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2003        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2004        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2005        GIR_EraseFromParent, /*InsnID*/0,
2006        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2007        // GIR_Coverage, 1211,
2008        GIR_Done,
2009      // Label 117: @2964
2010      GIM_Try, /*On fail goto*//*Label 118*/ 3048, // Rule ID 1214 //
2011        GIM_CheckFeatures, GIFBS_HasNEON,
2012        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2013        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2014        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2015        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2016        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2017        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2018        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2019        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2020        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
2021        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
2022        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2023        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2024        GIM_CheckIsSafeToFold, /*InsnID*/1,
2025        GIM_CheckIsSafeToFold, /*InsnID*/2,
2026        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 2575:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)))  =>  (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2027        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv2i64,
2028        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2029        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2030        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2031        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2032        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2033        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2034        GIR_EraseFromParent, /*InsnID*/0,
2035        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2036        // GIR_Coverage, 1214,
2037        GIR_Done,
2038      // Label 118: @3048
2039      GIM_Try, /*On fail goto*//*Label 119*/ 3113, // Rule ID 798 //
2040        GIM_CheckFeatures, GIFBS_HasNEON,
2041        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2042        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
2043        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2044        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2045        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2046        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
2047        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
2048        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2049        GIM_CheckIsSafeToFold, /*InsnID*/1,
2050        GIM_CheckIsSafeToFold, /*InsnID*/2,
2051        // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2052        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv2i64,
2053        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2054        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2055        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2056        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2057        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2058        GIR_EraseFromParent, /*InsnID*/0,
2059        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2060        // GIR_Coverage, 798,
2061        GIR_Done,
2062      // Label 119: @3113
2063      GIM_Try, /*On fail goto*//*Label 120*/ 3178, // Rule ID 797 //
2064        GIM_CheckFeatures, GIFBS_HasNEON,
2065        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2066        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
2067        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2068        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2069        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2070        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
2071        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
2072        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2073        GIM_CheckIsSafeToFold, /*InsnID*/1,
2074        GIM_CheckIsSafeToFold, /*InsnID*/2,
2075        // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2076        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv2i64,
2077        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2078        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2079        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2080        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2081        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2082        GIR_EraseFromParent, /*InsnID*/0,
2083        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2084        // GIR_Coverage, 797,
2085        GIR_Done,
2086      // Label 120: @3178
2087      GIM_Try, /*On fail goto*//*Label 121*/ 3243, // Rule ID 786 //
2088        GIM_CheckFeatures, GIFBS_HasNEON,
2089        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2090        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2091        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2092        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2093        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2094        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
2095        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
2096        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2097        GIM_CheckIsSafeToFold, /*InsnID*/1,
2098        GIM_CheckIsSafeToFold, /*InsnID*/2,
2099        // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2100        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv2i64,
2101        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2102        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2103        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2104        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2105        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2106        GIR_EraseFromParent, /*InsnID*/0,
2107        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2108        // GIR_Coverage, 786,
2109        GIR_Done,
2110      // Label 121: @3243
2111      GIM_Try, /*On fail goto*//*Label 122*/ 3308, // Rule ID 796 //
2112        GIM_CheckFeatures, GIFBS_HasNEON,
2113        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2114        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2115        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2116        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2117        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2118        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
2119        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
2120        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2121        GIM_CheckIsSafeToFold, /*InsnID*/1,
2122        GIM_CheckIsSafeToFold, /*InsnID*/2,
2123        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2124        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv2i64,
2125        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2126        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2127        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2128        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2129        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2130        GIR_EraseFromParent, /*InsnID*/0,
2131        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2132        // GIR_Coverage, 796,
2133        GIR_Done,
2134      // Label 122: @3308
2135      GIM_Try, /*On fail goto*//*Label 123*/ 3373, // Rule ID 795 //
2136        GIM_CheckFeatures, GIFBS_HasNEON,
2137        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2138        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2139        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2140        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2141        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2142        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
2143        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
2144        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2145        GIM_CheckIsSafeToFold, /*InsnID*/1,
2146        GIM_CheckIsSafeToFold, /*InsnID*/2,
2147        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2148        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv2i64,
2149        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2150        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2151        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2152        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2153        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2154        GIR_EraseFromParent, /*InsnID*/0,
2155        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2156        // GIR_Coverage, 795,
2157        GIR_Done,
2158      // Label 123: @3373
2159      GIM_Try, /*On fail goto*//*Label 124*/ 3425, // Rule ID 5611 //
2160        GIM_CheckFeatures, GIFBS_HasNEON,
2161        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2162        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
2163        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2164        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2165        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2166        GIM_CheckIsSafeToFold, /*InsnID*/1,
2167        // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn)  =>  (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2168        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
2169        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2170        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2171        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2172        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2173        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2174        GIR_EraseFromParent, /*InsnID*/0,
2175        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2176        // GIR_Coverage, 5611,
2177        GIR_Done,
2178      // Label 124: @3425
2179      GIM_Try, /*On fail goto*//*Label 125*/ 3477, // Rule ID 5605 //
2180        GIM_CheckFeatures, GIFBS_HasNEON,
2181        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2182        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2183        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2184        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2185        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2186        GIM_CheckIsSafeToFold, /*InsnID*/1,
2187        // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn)  =>  (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2188        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv2i64,
2189        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2190        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2191        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2192        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2193        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2194        GIR_EraseFromParent, /*InsnID*/0,
2195        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2196        // GIR_Coverage, 5605,
2197        GIR_Done,
2198      // Label 125: @3477
2199      GIM_Try, /*On fail goto*//*Label 126*/ 3529, // Rule ID 5610 //
2200        GIM_CheckFeatures, GIFBS_HasNEON,
2201        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2202        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2203        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2204        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2205        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2206        GIM_CheckIsSafeToFold, /*InsnID*/1,
2207        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn)  =>  (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2208        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
2209        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2212        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2213        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2214        GIR_EraseFromParent, /*InsnID*/0,
2215        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2216        // GIR_Coverage, 5610,
2217        GIR_Done,
2218      // Label 126: @3529
2219      GIM_Try, /*On fail goto*//*Label 127*/ 3581, // Rule ID 807 //
2220        GIM_CheckFeatures, GIFBS_HasNEON,
2221        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2222        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2223        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
2224        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2225        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2226        GIM_CheckIsSafeToFold, /*InsnID*/1,
2227        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2228        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
2229        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2230        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2231        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2232        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2233        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2234        GIR_EraseFromParent, /*InsnID*/0,
2235        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2236        // GIR_Coverage, 807,
2237        GIR_Done,
2238      // Label 127: @3581
2239      GIM_Try, /*On fail goto*//*Label 128*/ 3633, // Rule ID 801 //
2240        GIM_CheckFeatures, GIFBS_HasNEON,
2241        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2242        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2243        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2244        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2245        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2246        GIM_CheckIsSafeToFold, /*InsnID*/1,
2247        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2248        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv2i64,
2249        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2250        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2251        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2252        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2253        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2254        GIR_EraseFromParent, /*InsnID*/0,
2255        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2256        // GIR_Coverage, 801,
2257        GIR_Done,
2258      // Label 128: @3633
2259      GIM_Try, /*On fail goto*//*Label 129*/ 3685, // Rule ID 806 //
2260        GIM_CheckFeatures, GIFBS_HasNEON,
2261        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2262        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2263        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2264        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2265        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2266        GIM_CheckIsSafeToFold, /*InsnID*/1,
2267        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2268        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
2269        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2270        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2271        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2272        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2273        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2274        GIR_EraseFromParent, /*InsnID*/0,
2275        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2276        // GIR_Coverage, 806,
2277        GIR_Done,
2278      // Label 129: @3685
2279      GIM_Try, /*On fail goto*//*Label 130*/ 3724, // Rule ID 779 //
2280        GIM_CheckFeatures, GIFBS_HasNEON,
2281        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2282        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2283        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VADDv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
2284        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv2i64,
2285        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2286        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2287        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2288        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2289        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2290        GIR_EraseFromParent, /*InsnID*/0,
2291        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2292        // GIR_Coverage, 779,
2293        GIR_Done,
2294      // Label 130: @3724
2295      GIM_Reject,
2296    // Label 114: @3725
2297    GIM_Reject,
2298    // Label 70: @3726
2299    GIM_Try, /*On fail goto*//*Label 131*/ 4192,
2300      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
2301      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
2302      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
2303      GIM_Try, /*On fail goto*//*Label 132*/ 3811, // Rule ID 5701 //
2304        GIM_CheckFeatures, GIFBS_HasNEON,
2305        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2306        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2307        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2308        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2309        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2310        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2311        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2312        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2313        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2314        GIM_CheckIsSafeToFold, /*InsnID*/1,
2315        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 2574:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1)  =>  (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2316        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i16,
2317        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2318        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2319        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2321        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2322        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2323        GIR_EraseFromParent, /*InsnID*/0,
2324        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2325        // GIR_Coverage, 5701,
2326        GIR_Done,
2327      // Label 132: @3811
2328      GIM_Try, /*On fail goto*//*Label 133*/ 3882, // Rule ID 5707 //
2329        GIM_CheckFeatures, GIFBS_HasNEON,
2330        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2331        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2332        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2333        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2334        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2335        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2336        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2337        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2338        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2339        GIM_CheckIsSafeToFold, /*InsnID*/1,
2340        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 2575:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1)  =>  (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2341        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i16,
2342        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2343        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2344        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2345        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2346        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2347        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2348        GIR_EraseFromParent, /*InsnID*/0,
2349        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2350        // GIR_Coverage, 5707,
2351        GIR_Done,
2352      // Label 133: @3882
2353      GIM_Try, /*On fail goto*//*Label 134*/ 3953, // Rule ID 1198 //
2354        GIM_CheckFeatures, GIFBS_HasNEON,
2355        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2356        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2357        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2358        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2359        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2360        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2361        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2362        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2363        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2364        GIM_CheckIsSafeToFold, /*InsnID*/1,
2365        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (intrinsic_wo_chain:{ *:[v4i16] } 2574:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2366        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i16,
2367        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2368        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2369        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2370        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2371        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2372        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2373        GIR_EraseFromParent, /*InsnID*/0,
2374        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2375        // GIR_Coverage, 1198,
2376        GIR_Done,
2377      // Label 134: @3953
2378      GIM_Try, /*On fail goto*//*Label 135*/ 4024, // Rule ID 1204 //
2379        GIM_CheckFeatures, GIFBS_HasNEON,
2380        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2381        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2382        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2383        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2384        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2385        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2386        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2387        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2388        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2389        GIM_CheckIsSafeToFold, /*InsnID*/1,
2390        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (intrinsic_wo_chain:{ *:[v4i16] } 2575:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2391        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i16,
2392        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2393        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2394        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2396        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2397        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2398        GIR_EraseFromParent, /*InsnID*/0,
2399        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2400        // GIR_Coverage, 1204,
2401        GIR_Done,
2402      // Label 135: @4024
2403      GIM_Try, /*On fail goto*//*Label 136*/ 4088, // Rule ID 5631 //
2404        GIM_CheckFeatures, GIFBS_HasNEON,
2405        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2406        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2407        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2408        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2409        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2410        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2411        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2412        GIM_CheckIsSafeToFold, /*InsnID*/1,
2413        // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1)  =>  (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2414        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i16,
2415        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2416        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2417        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2418        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2419        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2420        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2421        GIR_EraseFromParent, /*InsnID*/0,
2422        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2423        // GIR_Coverage, 5631,
2424        GIR_Done,
2425      // Label 136: @4088
2426      GIM_Try, /*On fail goto*//*Label 137*/ 4152, // Rule ID 904 //
2427        GIM_CheckFeatures, GIFBS_HasNEON,
2428        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2429        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2430        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2431        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2432        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2433        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2434        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2435        GIM_CheckIsSafeToFold, /*InsnID*/1,
2436        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2437        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i16,
2438        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2439        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2440        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2441        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2442        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2443        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2444        GIR_EraseFromParent, /*InsnID*/0,
2445        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2446        // GIR_Coverage, 904,
2447        GIR_Done,
2448      // Label 137: @4152
2449      GIM_Try, /*On fail goto*//*Label 138*/ 4191, // Rule ID 773 //
2450        GIM_CheckFeatures, GIFBS_HasNEON,
2451        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2452        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2453        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VADDv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2454        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv4i16,
2455        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2456        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2457        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2458        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2459        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2460        GIR_EraseFromParent, /*InsnID*/0,
2461        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2462        // GIR_Coverage, 773,
2463        GIR_Done,
2464      // Label 138: @4191
2465      GIM_Reject,
2466    // Label 131: @4192
2467    GIM_Reject,
2468    // Label 71: @4193
2469    GIM_Try, /*On fail goto*//*Label 139*/ 5777,
2470      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2471      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2472      GIM_Try, /*On fail goto*//*Label 140*/ 4291, // Rule ID 5713 //
2473        GIM_CheckFeatures, GIFBS_HasNEON,
2474        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2475        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2476        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2477        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2478        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2479        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2480        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2481        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2482        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2483        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2484        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2485        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2486        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2487        GIM_CheckIsSafeToFold, /*InsnID*/1,
2488        GIM_CheckIsSafeToFold, /*InsnID*/2,
2489        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 2574:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1)  =>  (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2490        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv4i32,
2491        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2492        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2493        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2494        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2495        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2496        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2497        GIR_EraseFromParent, /*InsnID*/0,
2498        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2499        // GIR_Coverage, 5713,
2500        GIR_Done,
2501      // Label 140: @4291
2502      GIM_Try, /*On fail goto*//*Label 141*/ 4379, // Rule ID 5716 //
2503        GIM_CheckFeatures, GIFBS_HasNEON,
2504        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2505        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2506        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2507        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2508        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2509        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2510        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2511        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2512        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2513        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2514        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2515        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2516        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2517        GIM_CheckIsSafeToFold, /*InsnID*/1,
2518        GIM_CheckIsSafeToFold, /*InsnID*/2,
2519        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 2575:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1)  =>  (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2520        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv4i32,
2521        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2522        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2523        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2524        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2525        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2526        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2527        GIR_EraseFromParent, /*InsnID*/0,
2528        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2529        // GIR_Coverage, 5716,
2530        GIR_Done,
2531      // Label 141: @4379
2532      GIM_Try, /*On fail goto*//*Label 142*/ 4467, // Rule ID 1210 //
2533        GIM_CheckFeatures, GIFBS_HasNEON,
2534        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2535        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2536        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2537        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2538        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2539        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2540        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2541        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2542        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2543        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2544        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2545        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2546        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2547        GIM_CheckIsSafeToFold, /*InsnID*/1,
2548        GIM_CheckIsSafeToFold, /*InsnID*/2,
2549        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 2574:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)))  =>  (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2550        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv4i32,
2551        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2552        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2553        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2554        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2555        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2556        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2557        GIR_EraseFromParent, /*InsnID*/0,
2558        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2559        // GIR_Coverage, 1210,
2560        GIR_Done,
2561      // Label 142: @4467
2562      GIM_Try, /*On fail goto*//*Label 143*/ 4555, // Rule ID 1213 //
2563        GIM_CheckFeatures, GIFBS_HasNEON,
2564        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2565        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2566        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2567        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2568        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2569        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2570        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2571        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2572        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2573        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2574        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2575        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2576        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2577        GIM_CheckIsSafeToFold, /*InsnID*/1,
2578        GIM_CheckIsSafeToFold, /*InsnID*/2,
2579        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 2575:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)))  =>  (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2580        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv4i32,
2581        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2582        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2583        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2584        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2585        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2586        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2587        GIR_EraseFromParent, /*InsnID*/0,
2588        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2589        // GIR_Coverage, 1213,
2590        GIR_Done,
2591      // Label 143: @4555
2592      GIM_Try, /*On fail goto*//*Label 144*/ 4630, // Rule ID 5705 //
2593        GIM_CheckFeatures, GIFBS_HasNEON,
2594        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2595        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2596        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2597        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2598        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2599        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2600        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2601        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2602        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2603        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2604        GIM_CheckIsSafeToFold, /*InsnID*/1,
2605        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 2574:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2606        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i32,
2607        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2608        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2609        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2610        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2611        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2612        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2613        GIR_EraseFromParent, /*InsnID*/0,
2614        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2615        // GIR_Coverage, 5705,
2616        GIR_Done,
2617      // Label 144: @4630
2618      GIM_Try, /*On fail goto*//*Label 145*/ 4705, // Rule ID 5711 //
2619        GIM_CheckFeatures, GIFBS_HasNEON,
2620        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2621        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2622        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2623        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2624        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2625        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2626        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2627        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2628        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2629        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2630        GIM_CheckIsSafeToFold, /*InsnID*/1,
2631        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 2575:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2632        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i32,
2633        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2634        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2635        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2636        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2637        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2638        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2639        GIR_EraseFromParent, /*InsnID*/0,
2640        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2641        // GIR_Coverage, 5711,
2642        GIR_Done,
2643      // Label 145: @4705
2644      GIM_Try, /*On fail goto*//*Label 146*/ 4780, // Rule ID 1202 //
2645        GIM_CheckFeatures, GIFBS_HasNEON,
2646        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2647        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2648        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2649        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2650        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2651        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2652        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2653        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2654        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2655        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2656        GIM_CheckIsSafeToFold, /*InsnID*/1,
2657        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 2574:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2658        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i32,
2659        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2660        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2661        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2662        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2663        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2664        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2665        GIR_EraseFromParent, /*InsnID*/0,
2666        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2667        // GIR_Coverage, 1202,
2668        GIR_Done,
2669      // Label 146: @4780
2670      GIM_Try, /*On fail goto*//*Label 147*/ 4855, // Rule ID 1208 //
2671        GIM_CheckFeatures, GIFBS_HasNEON,
2672        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2673        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2674        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2675        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2676        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2677        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2678        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2679        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2680        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2681        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2682        GIM_CheckIsSafeToFold, /*InsnID*/1,
2683        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 2575:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2684        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i32,
2685        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2686        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2687        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2688        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2689        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2690        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2691        GIR_EraseFromParent, /*InsnID*/0,
2692        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2693        // GIR_Coverage, 1208,
2694        GIR_Done,
2695      // Label 147: @4855
2696      GIM_Try, /*On fail goto*//*Label 148*/ 4924, // Rule ID 794 //
2697        GIM_CheckFeatures, GIFBS_HasNEON,
2698        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2699        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2700        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
2701        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2702        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2703        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2704        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
2705        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2706        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2707        GIM_CheckIsSafeToFold, /*InsnID*/1,
2708        GIM_CheckIsSafeToFold, /*InsnID*/2,
2709        // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2710        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv4i32,
2711        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2712        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2713        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2714        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2715        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2716        GIR_EraseFromParent, /*InsnID*/0,
2717        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2718        // GIR_Coverage, 794,
2719        GIR_Done,
2720      // Label 148: @4924
2721      GIM_Try, /*On fail goto*//*Label 149*/ 4993, // Rule ID 793 //
2722        GIM_CheckFeatures, GIFBS_HasNEON,
2723        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2724        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2725        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
2726        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2727        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2728        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2729        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
2730        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2731        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2732        GIM_CheckIsSafeToFold, /*InsnID*/1,
2733        GIM_CheckIsSafeToFold, /*InsnID*/2,
2734        // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2735        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv4i32,
2736        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2737        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2738        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2739        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2740        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2741        GIR_EraseFromParent, /*InsnID*/0,
2742        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2743        // GIR_Coverage, 793,
2744        GIR_Done,
2745      // Label 149: @4993
2746      GIM_Try, /*On fail goto*//*Label 150*/ 5062, // Rule ID 785 //
2747        GIM_CheckFeatures, GIFBS_HasNEON,
2748        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2749        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2750        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2751        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2752        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2753        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2754        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
2755        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2756        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2757        GIM_CheckIsSafeToFold, /*InsnID*/1,
2758        GIM_CheckIsSafeToFold, /*InsnID*/2,
2759        // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2760        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv4i32,
2761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2762        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2763        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2764        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2765        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2766        GIR_EraseFromParent, /*InsnID*/0,
2767        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2768        // GIR_Coverage, 785,
2769        GIR_Done,
2770      // Label 150: @5062
2771      GIM_Try, /*On fail goto*//*Label 151*/ 5131, // Rule ID 792 //
2772        GIM_CheckFeatures, GIFBS_HasNEON,
2773        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2774        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2775        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2776        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2777        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2778        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2779        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
2780        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2781        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2782        GIM_CheckIsSafeToFold, /*InsnID*/1,
2783        GIM_CheckIsSafeToFold, /*InsnID*/2,
2784        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2785        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv4i32,
2786        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2787        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2788        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2789        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2790        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2791        GIR_EraseFromParent, /*InsnID*/0,
2792        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2793        // GIR_Coverage, 792,
2794        GIR_Done,
2795      // Label 151: @5131
2796      GIM_Try, /*On fail goto*//*Label 152*/ 5200, // Rule ID 791 //
2797        GIM_CheckFeatures, GIFBS_HasNEON,
2798        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2799        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2800        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2801        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2802        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2803        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2804        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
2805        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2806        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2807        GIM_CheckIsSafeToFold, /*InsnID*/1,
2808        GIM_CheckIsSafeToFold, /*InsnID*/2,
2809        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2810        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv4i32,
2811        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2812        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2813        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2814        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2815        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2816        GIR_EraseFromParent, /*InsnID*/0,
2817        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2818        // GIR_Coverage, 791,
2819        GIR_Done,
2820      // Label 152: @5200
2821      GIM_Try, /*On fail goto*//*Label 153*/ 5268, // Rule ID 5635 //
2822        GIM_CheckFeatures, GIFBS_HasNEON,
2823        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2824        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2825        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2826        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2827        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2828        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2829        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2830        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2831        GIM_CheckIsSafeToFold, /*InsnID*/1,
2832        // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2833        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i32,
2834        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2835        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2836        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2837        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2838        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2839        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2840        GIR_EraseFromParent, /*InsnID*/0,
2841        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2842        // GIR_Coverage, 5635,
2843        GIR_Done,
2844      // Label 153: @5268
2845      GIM_Try, /*On fail goto*//*Label 154*/ 5324, // Rule ID 5609 //
2846        GIM_CheckFeatures, GIFBS_HasNEON,
2847        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2848        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2849        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
2850        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2851        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2852        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2853        GIM_CheckIsSafeToFold, /*InsnID*/1,
2854        // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn)  =>  (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2855        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv4i32,
2856        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2857        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2858        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2859        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2860        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2861        GIR_EraseFromParent, /*InsnID*/0,
2862        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2863        // GIR_Coverage, 5609,
2864        GIR_Done,
2865      // Label 154: @5324
2866      GIM_Try, /*On fail goto*//*Label 155*/ 5380, // Rule ID 5604 //
2867        GIM_CheckFeatures, GIFBS_HasNEON,
2868        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2869        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2870        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2871        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2872        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2873        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2874        GIM_CheckIsSafeToFold, /*InsnID*/1,
2875        // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn)  =>  (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2876        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv4i32,
2877        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2878        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2879        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2880        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2881        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2882        GIR_EraseFromParent, /*InsnID*/0,
2883        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2884        // GIR_Coverage, 5604,
2885        GIR_Done,
2886      // Label 155: @5380
2887      GIM_Try, /*On fail goto*//*Label 156*/ 5436, // Rule ID 5608 //
2888        GIM_CheckFeatures, GIFBS_HasNEON,
2889        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2890        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2891        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2892        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2893        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2894        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2895        GIM_CheckIsSafeToFold, /*InsnID*/1,
2896        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn)  =>  (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2897        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv4i32,
2898        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2899        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2900        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2901        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2902        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2903        GIR_EraseFromParent, /*InsnID*/0,
2904        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2905        // GIR_Coverage, 5608,
2906        GIR_Done,
2907      // Label 156: @5436
2908      GIM_Try, /*On fail goto*//*Label 157*/ 5504, // Rule ID 908 //
2909        GIM_CheckFeatures, GIFBS_HasNEON,
2910        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2911        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2912        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2913        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2914        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2915        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2916        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2917        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2918        GIM_CheckIsSafeToFold, /*InsnID*/1,
2919        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2920        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i32,
2921        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2922        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2923        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2924        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2925        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2926        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2927        GIR_EraseFromParent, /*InsnID*/0,
2928        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2929        // GIR_Coverage, 908,
2930        GIR_Done,
2931      // Label 157: @5504
2932      GIM_Try, /*On fail goto*//*Label 158*/ 5560, // Rule ID 805 //
2933        GIM_CheckFeatures, GIFBS_HasNEON,
2934        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2935        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2936        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2937        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
2938        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2939        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2940        GIM_CheckIsSafeToFold, /*InsnID*/1,
2941        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2942        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv4i32,
2943        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2944        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2945        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2946        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2947        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2948        GIR_EraseFromParent, /*InsnID*/0,
2949        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2950        // GIR_Coverage, 805,
2951        GIR_Done,
2952      // Label 158: @5560
2953      GIM_Try, /*On fail goto*//*Label 159*/ 5616, // Rule ID 800 //
2954        GIM_CheckFeatures, GIFBS_HasNEON,
2955        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2956        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2957        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2958        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2959        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2960        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2961        GIM_CheckIsSafeToFold, /*InsnID*/1,
2962        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2963        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv4i32,
2964        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2965        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2966        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2967        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2968        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2969        GIR_EraseFromParent, /*InsnID*/0,
2970        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2971        // GIR_Coverage, 800,
2972        GIR_Done,
2973      // Label 159: @5616
2974      GIM_Try, /*On fail goto*//*Label 160*/ 5672, // Rule ID 804 //
2975        GIM_CheckFeatures, GIFBS_HasNEON,
2976        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2977        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2978        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2979        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2980        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2981        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2982        GIM_CheckIsSafeToFold, /*InsnID*/1,
2983        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2984        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv4i32,
2985        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2986        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2987        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2988        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2989        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2990        GIR_EraseFromParent, /*InsnID*/0,
2991        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2992        // GIR_Coverage, 804,
2993        GIR_Done,
2994      // Label 160: @5672
2995      GIM_Try, /*On fail goto*//*Label 161*/ 5715, // Rule ID 777 //
2996        GIM_CheckFeatures, GIFBS_HasNEON,
2997        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2998        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2999        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3000        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VADDv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
3001        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv4i32,
3002        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3003        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3005        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3006        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3007        GIR_EraseFromParent, /*InsnID*/0,
3008        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3009        // GIR_Coverage, 777,
3010        GIR_Done,
3011      // Label 161: @5715
3012      GIM_Try, /*On fail goto*//*Label 162*/ 5776, // Rule ID 3590 //
3013        GIM_CheckFeatures, GIFBS_HasMVEInt,
3014        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
3015        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
3016        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
3017        // (add:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
3018        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3019        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
3020        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
3021        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDi32,
3022        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
3023        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
3024        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
3025        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3026        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3027        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3028        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3029        GIR_EraseFromParent, /*InsnID*/0,
3030        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3031        // GIR_Coverage, 3590,
3032        GIR_Done,
3033      // Label 162: @5776
3034      GIM_Reject,
3035    // Label 139: @5777
3036    GIM_Reject,
3037    // Label 72: @5778
3038    GIM_Try, /*On fail goto*//*Label 163*/ 6244,
3039      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
3040      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
3041      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
3042      GIM_Try, /*On fail goto*//*Label 164*/ 5863, // Rule ID 5700 //
3043        GIM_CheckFeatures, GIFBS_HasNEON,
3044        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3045        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3046        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3047        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3048        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3049        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3050        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3051        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
3052        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3053        GIM_CheckIsSafeToFold, /*InsnID*/1,
3054        // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 2574:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1)  =>  (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3055        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i8,
3056        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3057        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3058        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3059        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3060        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3061        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3062        GIR_EraseFromParent, /*InsnID*/0,
3063        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3064        // GIR_Coverage, 5700,
3065        GIR_Done,
3066      // Label 164: @5863
3067      GIM_Try, /*On fail goto*//*Label 165*/ 5934, // Rule ID 5706 //
3068        GIM_CheckFeatures, GIFBS_HasNEON,
3069        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3070        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3071        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3072        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3073        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3074        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3075        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3076        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
3077        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3078        GIM_CheckIsSafeToFold, /*InsnID*/1,
3079        // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 2575:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1)  =>  (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3080        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i8,
3081        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3082        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3083        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3084        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3085        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3086        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3087        GIR_EraseFromParent, /*InsnID*/0,
3088        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3089        // GIR_Coverage, 5706,
3090        GIR_Done,
3091      // Label 165: @5934
3092      GIM_Try, /*On fail goto*//*Label 166*/ 6005, // Rule ID 1197 //
3093        GIM_CheckFeatures, GIFBS_HasNEON,
3094        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3095        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3096        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3097        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3098        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3099        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3100        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3101        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3102        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
3103        GIM_CheckIsSafeToFold, /*InsnID*/1,
3104        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (intrinsic_wo_chain:{ *:[v8i8] } 2574:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3105        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i8,
3106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3107        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3108        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3109        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3110        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3111        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3112        GIR_EraseFromParent, /*InsnID*/0,
3113        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3114        // GIR_Coverage, 1197,
3115        GIR_Done,
3116      // Label 166: @6005
3117      GIM_Try, /*On fail goto*//*Label 167*/ 6076, // Rule ID 1203 //
3118        GIM_CheckFeatures, GIFBS_HasNEON,
3119        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3120        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3121        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3122        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3123        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3124        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3125        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3126        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3127        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
3128        GIM_CheckIsSafeToFold, /*InsnID*/1,
3129        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (intrinsic_wo_chain:{ *:[v8i8] } 2575:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3130        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i8,
3131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3132        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3133        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3134        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3135        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3136        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3137        GIR_EraseFromParent, /*InsnID*/0,
3138        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3139        // GIR_Coverage, 1203,
3140        GIR_Done,
3141      // Label 167: @6076
3142      GIM_Try, /*On fail goto*//*Label 168*/ 6140, // Rule ID 5630 //
3143        GIM_CheckFeatures, GIFBS_HasNEON,
3144        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3145        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3146        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3147        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3148        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3149        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3150        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3151        GIM_CheckIsSafeToFold, /*InsnID*/1,
3152        // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1)  =>  (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3153        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i8,
3154        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3155        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3156        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3157        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3158        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3159        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3160        GIR_EraseFromParent, /*InsnID*/0,
3161        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3162        // GIR_Coverage, 5630,
3163        GIR_Done,
3164      // Label 168: @6140
3165      GIM_Try, /*On fail goto*//*Label 169*/ 6204, // Rule ID 903 //
3166        GIM_CheckFeatures, GIFBS_HasNEON,
3167        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3168        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3169        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3170        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3171        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3172        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3173        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3174        GIM_CheckIsSafeToFold, /*InsnID*/1,
3175        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3176        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i8,
3177        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3178        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3179        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3180        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3181        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3182        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3183        GIR_EraseFromParent, /*InsnID*/0,
3184        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3185        // GIR_Coverage, 903,
3186        GIR_Done,
3187      // Label 169: @6204
3188      GIM_Try, /*On fail goto*//*Label 170*/ 6243, // Rule ID 772 //
3189        GIM_CheckFeatures, GIFBS_HasNEON,
3190        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3191        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3192        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VADDv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3193        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv8i8,
3194        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3195        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3196        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3197        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3198        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3199        GIR_EraseFromParent, /*InsnID*/0,
3200        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3201        // GIR_Coverage, 772,
3202        GIR_Done,
3203      // Label 170: @6243
3204      GIM_Reject,
3205    // Label 163: @6244
3206    GIM_Reject,
3207    // Label 73: @6245
3208    GIM_Try, /*On fail goto*//*Label 171*/ 7829,
3209      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3210      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
3211      GIM_Try, /*On fail goto*//*Label 172*/ 6343, // Rule ID 5712 //
3212        GIM_CheckFeatures, GIFBS_HasNEON,
3213        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3214        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3215        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3216        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3217        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3218        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
3219        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3220        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
3221        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3222        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
3223        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3224        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
3225        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3226        GIM_CheckIsSafeToFold, /*InsnID*/1,
3227        GIM_CheckIsSafeToFold, /*InsnID*/2,
3228        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 2574:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1)  =>  (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3229        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv8i16,
3230        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3231        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3232        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
3233        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
3234        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3235        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3236        GIR_EraseFromParent, /*InsnID*/0,
3237        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3238        // GIR_Coverage, 5712,
3239        GIR_Done,
3240      // Label 172: @6343
3241      GIM_Try, /*On fail goto*//*Label 173*/ 6431, // Rule ID 5715 //
3242        GIM_CheckFeatures, GIFBS_HasNEON,
3243        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3244        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3245        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3246        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3247        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3248        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
3249        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3250        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
3251        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3252        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
3253        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3254        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
3255        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3256        GIM_CheckIsSafeToFold, /*InsnID*/1,
3257        GIM_CheckIsSafeToFold, /*InsnID*/2,
3258        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 2575:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1)  =>  (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3259        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv8i16,
3260        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3261        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3262        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
3263        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
3264        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3265        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3266        GIR_EraseFromParent, /*InsnID*/0,
3267        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3268        // GIR_Coverage, 5715,
3269        GIR_Done,
3270      // Label 173: @6431
3271      GIM_Try, /*On fail goto*//*Label 174*/ 6519, // Rule ID 1209 //
3272        GIM_CheckFeatures, GIFBS_HasNEON,
3273        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3274        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3275        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3276        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3277        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3278        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3279        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
3280        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3281        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
3282        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3283        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
3284        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3285        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
3286        GIM_CheckIsSafeToFold, /*InsnID*/1,
3287        GIM_CheckIsSafeToFold, /*InsnID*/2,
3288        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 2574:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)))  =>  (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3289        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv8i16,
3290        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3291        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3292        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
3293        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
3294        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3295        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3296        GIR_EraseFromParent, /*InsnID*/0,
3297        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3298        // GIR_Coverage, 1209,
3299        GIR_Done,
3300      // Label 174: @6519
3301      GIM_Try, /*On fail goto*//*Label 175*/ 6607, // Rule ID 1212 //
3302        GIM_CheckFeatures, GIFBS_HasNEON,
3303        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3304        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3305        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3306        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3307        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3308        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3309        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
3310        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3311        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
3312        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3313        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
3314        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3315        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
3316        GIM_CheckIsSafeToFold, /*InsnID*/1,
3317        GIM_CheckIsSafeToFold, /*InsnID*/2,
3318        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 2575:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)))  =>  (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3319        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv8i16,
3320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
3323        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
3324        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3325        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3326        GIR_EraseFromParent, /*InsnID*/0,
3327        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3328        // GIR_Coverage, 1212,
3329        GIR_Done,
3330      // Label 175: @6607
3331      GIM_Try, /*On fail goto*//*Label 176*/ 6682, // Rule ID 5704 //
3332        GIM_CheckFeatures, GIFBS_HasNEON,
3333        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3334        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3335        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3336        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3337        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3338        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3339        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3340        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3341        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3342        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3343        GIM_CheckIsSafeToFold, /*InsnID*/1,
3344        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 2574:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1)  =>  (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3345        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i16,
3346        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3347        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3348        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3349        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3350        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3351        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3352        GIR_EraseFromParent, /*InsnID*/0,
3353        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3354        // GIR_Coverage, 5704,
3355        GIR_Done,
3356      // Label 176: @6682
3357      GIM_Try, /*On fail goto*//*Label 177*/ 6757, // Rule ID 5710 //
3358        GIM_CheckFeatures, GIFBS_HasNEON,
3359        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3360        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3361        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3362        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3363        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3364        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3365        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3366        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3367        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3368        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3369        GIM_CheckIsSafeToFold, /*InsnID*/1,
3370        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 2575:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1)  =>  (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3371        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i16,
3372        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3373        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3374        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3375        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3376        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3377        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3378        GIR_EraseFromParent, /*InsnID*/0,
3379        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3380        // GIR_Coverage, 5710,
3381        GIR_Done,
3382      // Label 177: @6757
3383      GIM_Try, /*On fail goto*//*Label 178*/ 6832, // Rule ID 1201 //
3384        GIM_CheckFeatures, GIFBS_HasNEON,
3385        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3386        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3387        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3388        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3389        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3390        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3391        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3392        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3393        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3394        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3395        GIM_CheckIsSafeToFold, /*InsnID*/1,
3396        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (intrinsic_wo_chain:{ *:[v8i16] } 2574:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3397        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i16,
3398        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3399        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3400        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3401        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3402        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3403        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3404        GIR_EraseFromParent, /*InsnID*/0,
3405        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3406        // GIR_Coverage, 1201,
3407        GIR_Done,
3408      // Label 178: @6832
3409      GIM_Try, /*On fail goto*//*Label 179*/ 6907, // Rule ID 1207 //
3410        GIM_CheckFeatures, GIFBS_HasNEON,
3411        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3412        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3413        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3414        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3415        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3416        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3417        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3418        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3419        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3420        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3421        GIM_CheckIsSafeToFold, /*InsnID*/1,
3422        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (intrinsic_wo_chain:{ *:[v8i16] } 2575:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3423        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i16,
3424        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3425        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3426        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3427        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3428        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3429        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3430        GIR_EraseFromParent, /*InsnID*/0,
3431        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3432        // GIR_Coverage, 1207,
3433        GIR_Done,
3434      // Label 179: @6907
3435      GIM_Try, /*On fail goto*//*Label 180*/ 6976, // Rule ID 790 //
3436        GIM_CheckFeatures, GIFBS_HasNEON,
3437        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3438        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3439        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
3440        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3441        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3442        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3443        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
3444        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3445        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3446        GIM_CheckIsSafeToFold, /*InsnID*/1,
3447        GIM_CheckIsSafeToFold, /*InsnID*/2,
3448        // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3449        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv8i16,
3450        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3451        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3452        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3453        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3454        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3455        GIR_EraseFromParent, /*InsnID*/0,
3456        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3457        // GIR_Coverage, 790,
3458        GIR_Done,
3459      // Label 180: @6976
3460      GIM_Try, /*On fail goto*//*Label 181*/ 7045, // Rule ID 789 //
3461        GIM_CheckFeatures, GIFBS_HasNEON,
3462        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3463        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3464        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
3465        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3466        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3467        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3468        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3469        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3470        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3471        GIM_CheckIsSafeToFold, /*InsnID*/1,
3472        GIM_CheckIsSafeToFold, /*InsnID*/2,
3473        // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3474        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv8i16,
3475        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3476        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3477        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3478        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3479        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3480        GIR_EraseFromParent, /*InsnID*/0,
3481        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3482        // GIR_Coverage, 789,
3483        GIR_Done,
3484      // Label 181: @7045
3485      GIM_Try, /*On fail goto*//*Label 182*/ 7114, // Rule ID 784 //
3486        GIM_CheckFeatures, GIFBS_HasNEON,
3487        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3488        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3489        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3490        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3491        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3492        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3493        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3494        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3495        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3496        GIM_CheckIsSafeToFold, /*InsnID*/1,
3497        GIM_CheckIsSafeToFold, /*InsnID*/2,
3498        // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3499        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv8i16,
3500        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3501        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3502        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3503        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3504        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3505        GIR_EraseFromParent, /*InsnID*/0,
3506        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3507        // GIR_Coverage, 784,
3508        GIR_Done,
3509      // Label 182: @7114
3510      GIM_Try, /*On fail goto*//*Label 183*/ 7183, // Rule ID 788 //
3511        GIM_CheckFeatures, GIFBS_HasNEON,
3512        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3513        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3514        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3515        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3516        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3517        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3518        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
3519        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3520        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3521        GIM_CheckIsSafeToFold, /*InsnID*/1,
3522        GIM_CheckIsSafeToFold, /*InsnID*/2,
3523        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3524        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv8i16,
3525        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3526        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3527        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3528        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3529        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3530        GIR_EraseFromParent, /*InsnID*/0,
3531        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3532        // GIR_Coverage, 788,
3533        GIR_Done,
3534      // Label 183: @7183
3535      GIM_Try, /*On fail goto*//*Label 184*/ 7252, // Rule ID 787 //
3536        GIM_CheckFeatures, GIFBS_HasNEON,
3537        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3538        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3539        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3540        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3541        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3542        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3543        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3544        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3545        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3546        GIM_CheckIsSafeToFold, /*InsnID*/1,
3547        GIM_CheckIsSafeToFold, /*InsnID*/2,
3548        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3549        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv8i16,
3550        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3551        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3552        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3553        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3554        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3555        GIR_EraseFromParent, /*InsnID*/0,
3556        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3557        // GIR_Coverage, 787,
3558        GIR_Done,
3559      // Label 184: @7252
3560      GIM_Try, /*On fail goto*//*Label 185*/ 7320, // Rule ID 5634 //
3561        GIM_CheckFeatures, GIFBS_HasNEON,
3562        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3563        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3564        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3565        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3566        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3567        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3568        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3569        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3570        GIM_CheckIsSafeToFold, /*InsnID*/1,
3571        // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1)  =>  (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3572        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i16,
3573        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3574        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3575        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3576        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3577        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3578        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3579        GIR_EraseFromParent, /*InsnID*/0,
3580        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3581        // GIR_Coverage, 5634,
3582        GIR_Done,
3583      // Label 185: @7320
3584      GIM_Try, /*On fail goto*//*Label 186*/ 7376, // Rule ID 5607 //
3585        GIM_CheckFeatures, GIFBS_HasNEON,
3586        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3587        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3588        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
3589        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3590        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3591        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3592        GIM_CheckIsSafeToFold, /*InsnID*/1,
3593        // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn)  =>  (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3594        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv8i16,
3595        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3596        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
3597        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3598        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3599        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3600        GIR_EraseFromParent, /*InsnID*/0,
3601        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3602        // GIR_Coverage, 5607,
3603        GIR_Done,
3604      // Label 186: @7376
3605      GIM_Try, /*On fail goto*//*Label 187*/ 7432, // Rule ID 5603 //
3606        GIM_CheckFeatures, GIFBS_HasNEON,
3607        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3608        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3609        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3610        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3611        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3612        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3613        GIM_CheckIsSafeToFold, /*InsnID*/1,
3614        // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn)  =>  (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3615        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv8i16,
3616        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3617        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
3618        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3619        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3620        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3621        GIR_EraseFromParent, /*InsnID*/0,
3622        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3623        // GIR_Coverage, 5603,
3624        GIR_Done,
3625      // Label 187: @7432
3626      GIM_Try, /*On fail goto*//*Label 188*/ 7488, // Rule ID 5606 //
3627        GIM_CheckFeatures, GIFBS_HasNEON,
3628        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3629        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3630        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3631        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3632        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3633        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3634        GIM_CheckIsSafeToFold, /*InsnID*/1,
3635        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn)  =>  (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3636        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv8i16,
3637        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3638        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
3639        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3640        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3641        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3642        GIR_EraseFromParent, /*InsnID*/0,
3643        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3644        // GIR_Coverage, 5606,
3645        GIR_Done,
3646      // Label 188: @7488
3647      GIM_Try, /*On fail goto*//*Label 189*/ 7556, // Rule ID 907 //
3648        GIM_CheckFeatures, GIFBS_HasNEON,
3649        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3650        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3651        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3652        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3653        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3654        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3655        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3656        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3657        GIM_CheckIsSafeToFold, /*InsnID*/1,
3658        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3659        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i16,
3660        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3661        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3662        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3663        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3664        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3665        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3666        GIR_EraseFromParent, /*InsnID*/0,
3667        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3668        // GIR_Coverage, 907,
3669        GIR_Done,
3670      // Label 189: @7556
3671      GIM_Try, /*On fail goto*//*Label 190*/ 7612, // Rule ID 803 //
3672        GIM_CheckFeatures, GIFBS_HasNEON,
3673        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3674        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3675        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3676        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
3677        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3678        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3679        GIM_CheckIsSafeToFold, /*InsnID*/1,
3680        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3681        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv8i16,
3682        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3683        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3684        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3685        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3686        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3687        GIR_EraseFromParent, /*InsnID*/0,
3688        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3689        // GIR_Coverage, 803,
3690        GIR_Done,
3691      // Label 190: @7612
3692      GIM_Try, /*On fail goto*//*Label 191*/ 7668, // Rule ID 799 //
3693        GIM_CheckFeatures, GIFBS_HasNEON,
3694        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3695        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3696        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3697        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3698        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3699        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3700        GIM_CheckIsSafeToFold, /*InsnID*/1,
3701        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3702        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv8i16,
3703        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3704        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3705        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3706        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3707        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3708        GIR_EraseFromParent, /*InsnID*/0,
3709        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3710        // GIR_Coverage, 799,
3711        GIR_Done,
3712      // Label 191: @7668
3713      GIM_Try, /*On fail goto*//*Label 192*/ 7724, // Rule ID 802 //
3714        GIM_CheckFeatures, GIFBS_HasNEON,
3715        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3716        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3717        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3718        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3719        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3720        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3721        GIM_CheckIsSafeToFold, /*InsnID*/1,
3722        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3723        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv8i16,
3724        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3725        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3726        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3727        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3728        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3729        GIR_EraseFromParent, /*InsnID*/0,
3730        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3731        // GIR_Coverage, 802,
3732        GIR_Done,
3733      // Label 192: @7724
3734      GIM_Try, /*On fail goto*//*Label 193*/ 7767, // Rule ID 776 //
3735        GIM_CheckFeatures, GIFBS_HasNEON,
3736        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3737        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3738        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3739        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VADDv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3740        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv8i16,
3741        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3742        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3743        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3744        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3745        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3746        GIR_EraseFromParent, /*InsnID*/0,
3747        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3748        // GIR_Coverage, 776,
3749        GIR_Done,
3750      // Label 193: @7767
3751      GIM_Try, /*On fail goto*//*Label 194*/ 7828, // Rule ID 3586 //
3752        GIM_CheckFeatures, GIFBS_HasMVEInt,
3753        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
3754        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
3755        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
3756        // (add:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
3757        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3758        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
3759        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
3760        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDi16,
3761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
3762        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
3763        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
3764        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3765        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3766        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3767        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3768        GIR_EraseFromParent, /*InsnID*/0,
3769        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3770        // GIR_Coverage, 3586,
3771        GIR_Done,
3772      // Label 194: @7828
3773      GIM_Reject,
3774    // Label 171: @7829
3775    GIM_Reject,
3776    // Label 74: @7830
3777    GIM_Try, /*On fail goto*//*Label 195*/ 8381,
3778      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3779      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
3780      GIM_Try, /*On fail goto*//*Label 196*/ 7915, // Rule ID 5703 //
3781        GIM_CheckFeatures, GIFBS_HasNEON,
3782        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3783        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3784        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3785        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3786        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3787        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3788        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3789        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3790        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3791        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3792        GIM_CheckIsSafeToFold, /*InsnID*/1,
3793        // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 2574:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1)  =>  (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3794        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv16i8,
3795        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3796        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3797        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3798        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3799        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3800        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3801        GIR_EraseFromParent, /*InsnID*/0,
3802        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3803        // GIR_Coverage, 5703,
3804        GIR_Done,
3805      // Label 196: @7915
3806      GIM_Try, /*On fail goto*//*Label 197*/ 7990, // Rule ID 5709 //
3807        GIM_CheckFeatures, GIFBS_HasNEON,
3808        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3809        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3810        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3811        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3812        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3813        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3814        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3815        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3816        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3817        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3818        GIM_CheckIsSafeToFold, /*InsnID*/1,
3819        // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 2575:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1)  =>  (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3820        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv16i8,
3821        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3822        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3823        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3824        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3825        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3826        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3827        GIR_EraseFromParent, /*InsnID*/0,
3828        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3829        // GIR_Coverage, 5709,
3830        GIR_Done,
3831      // Label 197: @7990
3832      GIM_Try, /*On fail goto*//*Label 198*/ 8065, // Rule ID 1200 //
3833        GIM_CheckFeatures, GIFBS_HasNEON,
3834        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3835        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3836        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3837        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3838        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3839        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3840        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3841        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3842        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3843        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3844        GIM_CheckIsSafeToFold, /*InsnID*/1,
3845        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (intrinsic_wo_chain:{ *:[v16i8] } 2574:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3846        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv16i8,
3847        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3848        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3849        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3850        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3851        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3852        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3853        GIR_EraseFromParent, /*InsnID*/0,
3854        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3855        // GIR_Coverage, 1200,
3856        GIR_Done,
3857      // Label 198: @8065
3858      GIM_Try, /*On fail goto*//*Label 199*/ 8140, // Rule ID 1206 //
3859        GIM_CheckFeatures, GIFBS_HasNEON,
3860        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3861        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3862        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3863        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3864        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3865        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3866        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3867        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3868        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3869        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3870        GIM_CheckIsSafeToFold, /*InsnID*/1,
3871        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (intrinsic_wo_chain:{ *:[v16i8] } 2575:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3872        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv16i8,
3873        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3874        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3875        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3876        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3877        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3878        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3879        GIR_EraseFromParent, /*InsnID*/0,
3880        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3881        // GIR_Coverage, 1206,
3882        GIR_Done,
3883      // Label 199: @8140
3884      GIM_Try, /*On fail goto*//*Label 200*/ 8208, // Rule ID 5633 //
3885        GIM_CheckFeatures, GIFBS_HasNEON,
3886        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3887        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3888        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3889        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3890        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3891        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3892        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3893        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3894        GIM_CheckIsSafeToFold, /*InsnID*/1,
3895        // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1)  =>  (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3896        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv16i8,
3897        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3898        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3899        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3900        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3901        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3902        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3903        GIR_EraseFromParent, /*InsnID*/0,
3904        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3905        // GIR_Coverage, 5633,
3906        GIR_Done,
3907      // Label 200: @8208
3908      GIM_Try, /*On fail goto*//*Label 201*/ 8276, // Rule ID 906 //
3909        GIM_CheckFeatures, GIFBS_HasNEON,
3910        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3911        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3912        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3913        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3914        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3915        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3916        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3917        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3918        GIM_CheckIsSafeToFold, /*InsnID*/1,
3919        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3920        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv16i8,
3921        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3922        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3923        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3924        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3925        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3926        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3927        GIR_EraseFromParent, /*InsnID*/0,
3928        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3929        // GIR_Coverage, 906,
3930        GIR_Done,
3931      // Label 201: @8276
3932      GIM_Try, /*On fail goto*//*Label 202*/ 8319, // Rule ID 775 //
3933        GIM_CheckFeatures, GIFBS_HasNEON,
3934        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3935        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3936        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3937        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VADDv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3938        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv16i8,
3939        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3940        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3941        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3942        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3943        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3944        GIR_EraseFromParent, /*InsnID*/0,
3945        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3946        // GIR_Coverage, 775,
3947        GIR_Done,
3948      // Label 202: @8319
3949      GIM_Try, /*On fail goto*//*Label 203*/ 8380, // Rule ID 3582 //
3950        GIM_CheckFeatures, GIFBS_HasMVEInt,
3951        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
3952        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
3953        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
3954        // (add:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
3955        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3956        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
3957        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
3958        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDi8,
3959        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
3960        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
3961        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
3962        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3963        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3964        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3965        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3966        GIR_EraseFromParent, /*InsnID*/0,
3967        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3968        // GIR_Coverage, 3582,
3969        GIR_Done,
3970      // Label 203: @8380
3971      GIM_Reject,
3972    // Label 195: @8381
3973    GIM_Reject,
3974    // Label 75: @8382
3975    GIM_Reject,
3976    // Label 1: @8383
3977    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 16, /*)*//*default:*//*Label 213*/ 11423,
3978    /*GILLT_s32*//*Label 204*/ 8404,
3979    /*GILLT_s64*//*Label 205*/ 8912, 0,
3980    /*GILLT_v2s32*//*Label 206*/ 8964,
3981    /*GILLT_v2s64*//*Label 207*/ 9079, 0,
3982    /*GILLT_v4s16*//*Label 208*/ 9615,
3983    /*GILLT_v4s32*//*Label 209*/ 9730, 0, 0,
3984    /*GILLT_v8s8*//*Label 210*/ 10427,
3985    /*GILLT_v8s16*//*Label 211*/ 10542, 0, 0,
3986    /*GILLT_v16s8*//*Label 212*/ 11239,
3987    // Label 204: @8404
3988    GIM_Try, /*On fail goto*//*Label 214*/ 8911,
3989      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3990      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3991      GIM_Try, /*On fail goto*//*Label 215*/ 8468, // Rule ID 96 //
3992        GIM_CheckFeatures, GIFBS_IsARM,
3993        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
3994        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3995        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3996        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
3997        // MIs[1] Operand 1
3998        // No operand predicates
3999        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4000        GIM_CheckIsSafeToFold, /*InsnID*/1,
4001        // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, GPR:{ *:[i32] }:$Rn)  =>  (RSBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4002        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::RSBri,
4003        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4005        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4006        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4007        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4008        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4009        GIR_EraseFromParent, /*InsnID*/0,
4010        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4011        // GIR_Coverage, 96,
4012        GIR_Done,
4013      // Label 215: @8468
4014      GIM_Try, /*On fail goto*//*Label 216*/ 8522, // Rule ID 434 //
4015        GIM_CheckFeatures, GIFBS_IsThumb2,
4016        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4017        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4018        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4019        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
4020        // MIs[1] Operand 1
4021        // No operand predicates
4022        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4023        GIM_CheckIsSafeToFold, /*InsnID*/1,
4024        // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, rGPR:{ *:[i32] }:$Rn)  =>  (t2RSBri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4025        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2RSBri,
4026        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4027        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4028        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4029        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4030        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4031        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4032        GIR_EraseFromParent, /*InsnID*/0,
4033        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4034        // GIR_Coverage, 434,
4035        GIR_Done,
4036      // Label 216: @8522
4037      GIM_Try, /*On fail goto*//*Label 217*/ 8576, // Rule ID 76 //
4038        GIM_CheckFeatures, GIFBS_IsARM,
4039        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4040        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4041        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4042        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4043        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
4044        // MIs[1] Operand 1
4045        // No operand predicates
4046        GIM_CheckIsSafeToFold, /*InsnID*/1,
4047        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (SUBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4048        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SUBri,
4049        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4050        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4051        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4052        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4053        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4054        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4055        GIR_EraseFromParent, /*InsnID*/0,
4056        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4057        // GIR_Coverage, 76,
4058        GIR_Done,
4059      // Label 217: @8576
4060      GIM_Try, /*On fail goto*//*Label 218*/ 8630, // Rule ID 418 //
4061        GIM_CheckFeatures, GIFBS_IsThumb2,
4062        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4063        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
4064        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4065        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4066        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
4067        // MIs[1] Operand 1
4068        // No operand predicates
4069        GIM_CheckIsSafeToFold, /*InsnID*/1,
4070        // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2SUBri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4071        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBri,
4072        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4073        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4074        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4075        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4076        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4077        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4078        GIR_EraseFromParent, /*InsnID*/0,
4079        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4080        // GIR_Coverage, 418,
4081        GIR_Done,
4082      // Label 218: @8630
4083      GIM_Try, /*On fail goto*//*Label 219*/ 8680, // Rule ID 419 //
4084        GIM_CheckFeatures, GIFBS_IsThumb2,
4085        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4086        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4087        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4088        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4089        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_4095,
4090        // MIs[1] Operand 1
4091        // No operand predicates
4092        GIM_CheckIsSafeToFold, /*InsnID*/1,
4093        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm)  =>  (t2SUBri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4094        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBri12,
4095        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4096        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4097        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4098        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4099        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4100        GIR_EraseFromParent, /*InsnID*/0,
4101        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4102        // GIR_Coverage, 419,
4103        GIR_Done,
4104      // Label 219: @8680
4105      GIM_Try, /*On fail goto*//*Label 220*/ 8748, // Rule ID 173 //
4106        GIM_CheckFeatures, GIFBS_HasV6T2_IsARM_UseMulOps,
4107        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4108        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4109        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4110        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4111        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4112        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4113        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4114        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4115        GIM_CheckIsSafeToFold, /*InsnID*/1,
4116        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm))  =>  (MLS:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
4117        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLS,
4118        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4119        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4120        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4121        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
4122        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4123        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4124        GIR_EraseFromParent, /*InsnID*/0,
4125        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4126        // GIR_Coverage, 173,
4127        GIR_Done,
4128      // Label 220: @8748
4129      GIM_Try, /*On fail goto*//*Label 221*/ 8816, // Rule ID 511 //
4130        GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
4131        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4132        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4133        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4134        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4135        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4136        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4137        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4138        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4139        GIM_CheckIsSafeToFold, /*InsnID*/1,
4140        // (sub:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm))  =>  (t2MLS:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
4141        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLS,
4142        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4143        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4144        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4145        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
4146        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4147        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4148        GIR_EraseFromParent, /*InsnID*/0,
4149        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4150        // GIR_Coverage, 511,
4151        GIR_Done,
4152      // Label 221: @8816
4153      GIM_Try, /*On fail goto*//*Label 222*/ 8863, // Rule ID 77 //
4154        GIM_CheckFeatures, GIFBS_IsARM,
4155        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4156        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4157        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4158        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (SUBrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4159        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SUBrr,
4160        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4161        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4162        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4163        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4164        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4165        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4166        GIR_EraseFromParent, /*InsnID*/0,
4167        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4168        // GIR_Coverage, 77,
4169        GIR_Done,
4170      // Label 222: @8863
4171      GIM_Try, /*On fail goto*//*Label 223*/ 8910, // Rule ID 420 //
4172        GIM_CheckFeatures, GIFBS_IsThumb2,
4173        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4174        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
4175        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4176        // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SUBrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4177        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBrr,
4178        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4179        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4180        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4181        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4182        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4183        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4184        GIR_EraseFromParent, /*InsnID*/0,
4185        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4186        // GIR_Coverage, 420,
4187        GIR_Done,
4188      // Label 223: @8910
4189      GIM_Reject,
4190    // Label 214: @8911
4191    GIM_Reject,
4192    // Label 205: @8912
4193    GIM_Try, /*On fail goto*//*Label 224*/ 8963, // Rule ID 982 //
4194      GIM_CheckFeatures, GIFBS_HasNEON,
4195      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
4196      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4197      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4198      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4199      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4200      // (sub:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VSUBv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
4201      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv1i64,
4202      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4203      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4204      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4205      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4206      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4207      GIR_EraseFromParent, /*InsnID*/0,
4208      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4209      // GIR_Coverage, 982,
4210      GIR_Done,
4211    // Label 224: @8963
4212    GIM_Reject,
4213    // Label 206: @8964
4214    GIM_Try, /*On fail goto*//*Label 225*/ 9078,
4215      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
4216      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
4217      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4218      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4219      GIM_Try, /*On fail goto*//*Label 226*/ 9042, // Rule ID 933 //
4220        GIM_CheckFeatures, GIFBS_HasNEON,
4221        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4222        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4223        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4224        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
4225        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4226        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4227        GIM_CheckIsSafeToFold, /*InsnID*/1,
4228        // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VMLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4229        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv2i32,
4230        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4231        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4232        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4233        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4234        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4235        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4236        GIR_EraseFromParent, /*InsnID*/0,
4237        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4238        // GIR_Coverage, 933,
4239        GIR_Done,
4240      // Label 226: @9042
4241      GIM_Try, /*On fail goto*//*Label 227*/ 9077, // Rule ID 978 //
4242        GIM_CheckFeatures, GIFBS_HasNEON,
4243        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4244        // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VSUBv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4245        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv2i32,
4246        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4247        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4248        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4249        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4250        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4251        GIR_EraseFromParent, /*InsnID*/0,
4252        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4253        // GIR_Coverage, 978,
4254        GIR_Done,
4255      // Label 227: @9077
4256      GIM_Reject,
4257    // Label 225: @9078
4258    GIM_Reject,
4259    // Label 207: @9079
4260    GIM_Try, /*On fail goto*//*Label 228*/ 9614,
4261      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4262      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4263      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4264      GIM_Try, /*On fail goto*//*Label 229*/ 9158, // Rule ID 1002 //
4265        GIM_CheckFeatures, GIFBS_HasNEON,
4266        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4267        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
4268        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4269        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4270        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4271        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
4272        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4273        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4274        GIM_CheckIsSafeToFold, /*InsnID*/1,
4275        GIM_CheckIsSafeToFold, /*InsnID*/2,
4276        // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4277        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv2i64,
4278        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4279        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4280        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4281        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4282        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4283        GIR_EraseFromParent, /*InsnID*/0,
4284        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4285        // GIR_Coverage, 1002,
4286        GIR_Done,
4287      // Label 229: @9158
4288      GIM_Try, /*On fail goto*//*Label 230*/ 9223, // Rule ID 1001 //
4289        GIM_CheckFeatures, GIFBS_HasNEON,
4290        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4291        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
4292        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4293        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4294        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4295        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4296        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4297        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4298        GIM_CheckIsSafeToFold, /*InsnID*/1,
4299        GIM_CheckIsSafeToFold, /*InsnID*/2,
4300        // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4301        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv2i64,
4302        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4303        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4304        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4305        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4306        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4307        GIR_EraseFromParent, /*InsnID*/0,
4308        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4309        // GIR_Coverage, 1001,
4310        GIR_Done,
4311      // Label 230: @9223
4312      GIM_Try, /*On fail goto*//*Label 231*/ 9288, // Rule ID 990 //
4313        GIM_CheckFeatures, GIFBS_HasNEON,
4314        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4315        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4316        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4317        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4318        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4319        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4320        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4321        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4322        GIM_CheckIsSafeToFold, /*InsnID*/1,
4323        GIM_CheckIsSafeToFold, /*InsnID*/2,
4324        // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4325        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv2i64,
4326        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4327        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4328        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4329        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4330        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4331        GIR_EraseFromParent, /*InsnID*/0,
4332        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4333        // GIR_Coverage, 990,
4334        GIR_Done,
4335      // Label 231: @9288
4336      GIM_Try, /*On fail goto*//*Label 232*/ 9353, // Rule ID 1000 //
4337        GIM_CheckFeatures, GIFBS_HasNEON,
4338        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4339        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4340        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4341        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4342        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4343        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
4344        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4345        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4346        GIM_CheckIsSafeToFold, /*InsnID*/1,
4347        GIM_CheckIsSafeToFold, /*InsnID*/2,
4348        // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4349        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv2i64,
4350        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4351        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4352        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4353        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4354        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4355        GIR_EraseFromParent, /*InsnID*/0,
4356        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4357        // GIR_Coverage, 1000,
4358        GIR_Done,
4359      // Label 232: @9353
4360      GIM_Try, /*On fail goto*//*Label 233*/ 9418, // Rule ID 999 //
4361        GIM_CheckFeatures, GIFBS_HasNEON,
4362        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4363        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4364        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4365        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4366        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4367        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4368        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4369        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4370        GIM_CheckIsSafeToFold, /*InsnID*/1,
4371        GIM_CheckIsSafeToFold, /*InsnID*/2,
4372        // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4373        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv2i64,
4374        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4375        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4376        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4377        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4378        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4379        GIR_EraseFromParent, /*InsnID*/0,
4380        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4381        // GIR_Coverage, 999,
4382        GIR_Done,
4383      // Label 233: @9418
4384      GIM_Try, /*On fail goto*//*Label 234*/ 9470, // Rule ID 1011 //
4385        GIM_CheckFeatures, GIFBS_HasNEON,
4386        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4387        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4388        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
4389        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4390        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4391        GIM_CheckIsSafeToFold, /*InsnID*/1,
4392        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4393        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv2i64,
4394        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4396        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4397        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4398        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4399        GIR_EraseFromParent, /*InsnID*/0,
4400        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4401        // GIR_Coverage, 1011,
4402        GIR_Done,
4403      // Label 234: @9470
4404      GIM_Try, /*On fail goto*//*Label 235*/ 9522, // Rule ID 1005 //
4405        GIM_CheckFeatures, GIFBS_HasNEON,
4406        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4407        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4408        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4409        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4410        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4411        GIM_CheckIsSafeToFold, /*InsnID*/1,
4412        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4413        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv2i64,
4414        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4415        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4416        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4417        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4418        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4419        GIR_EraseFromParent, /*InsnID*/0,
4420        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4421        // GIR_Coverage, 1005,
4422        GIR_Done,
4423      // Label 235: @9522
4424      GIM_Try, /*On fail goto*//*Label 236*/ 9574, // Rule ID 1010 //
4425        GIM_CheckFeatures, GIFBS_HasNEON,
4426        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4427        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4428        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4429        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4430        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4431        GIM_CheckIsSafeToFold, /*InsnID*/1,
4432        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4433        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv2i64,
4434        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4435        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4436        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4437        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4438        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4439        GIR_EraseFromParent, /*InsnID*/0,
4440        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4441        // GIR_Coverage, 1010,
4442        GIR_Done,
4443      // Label 236: @9574
4444      GIM_Try, /*On fail goto*//*Label 237*/ 9613, // Rule ID 983 //
4445        GIM_CheckFeatures, GIFBS_HasNEON,
4446        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4447        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4448        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VSUBv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
4449        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv2i64,
4450        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4451        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4452        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4453        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4454        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4455        GIR_EraseFromParent, /*InsnID*/0,
4456        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4457        // GIR_Coverage, 983,
4458        GIR_Done,
4459      // Label 237: @9613
4460      GIM_Reject,
4461    // Label 228: @9614
4462    GIM_Reject,
4463    // Label 208: @9615
4464    GIM_Try, /*On fail goto*//*Label 238*/ 9729,
4465      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
4466      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
4467      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4468      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4469      GIM_Try, /*On fail goto*//*Label 239*/ 9693, // Rule ID 932 //
4470        GIM_CheckFeatures, GIFBS_HasNEON,
4471        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4472        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4473        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4474        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
4475        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4476        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4477        GIM_CheckIsSafeToFold, /*InsnID*/1,
4478        // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VMLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4479        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv4i16,
4480        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4481        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4482        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4483        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4484        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4485        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4486        GIR_EraseFromParent, /*InsnID*/0,
4487        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4488        // GIR_Coverage, 932,
4489        GIR_Done,
4490      // Label 239: @9693
4491      GIM_Try, /*On fail goto*//*Label 240*/ 9728, // Rule ID 977 //
4492        GIM_CheckFeatures, GIFBS_HasNEON,
4493        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4494        // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VSUBv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4495        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv4i16,
4496        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4497        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4498        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4499        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4500        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4501        GIR_EraseFromParent, /*InsnID*/0,
4502        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4503        // GIR_Coverage, 977,
4504        GIR_Done,
4505      // Label 240: @9728
4506      GIM_Reject,
4507    // Label 238: @9729
4508    GIM_Reject,
4509    // Label 209: @9730
4510    GIM_Try, /*On fail goto*//*Label 241*/ 10426,
4511      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4512      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4513      GIM_Try, /*On fail goto*//*Label 242*/ 9809, // Rule ID 998 //
4514        GIM_CheckFeatures, GIFBS_HasNEON,
4515        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4516        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4517        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
4518        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4519        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4520        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4521        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
4522        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4523        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4524        GIM_CheckIsSafeToFold, /*InsnID*/1,
4525        GIM_CheckIsSafeToFold, /*InsnID*/2,
4526        // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4527        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv4i32,
4528        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4529        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4530        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4531        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4532        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4533        GIR_EraseFromParent, /*InsnID*/0,
4534        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4535        // GIR_Coverage, 998,
4536        GIR_Done,
4537      // Label 242: @9809
4538      GIM_Try, /*On fail goto*//*Label 243*/ 9878, // Rule ID 997 //
4539        GIM_CheckFeatures, GIFBS_HasNEON,
4540        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4541        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4542        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
4543        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4544        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4545        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4546        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4547        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4548        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4549        GIM_CheckIsSafeToFold, /*InsnID*/1,
4550        GIM_CheckIsSafeToFold, /*InsnID*/2,
4551        // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4552        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv4i32,
4553        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4554        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4555        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4556        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4557        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4558        GIR_EraseFromParent, /*InsnID*/0,
4559        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4560        // GIR_Coverage, 997,
4561        GIR_Done,
4562      // Label 243: @9878
4563      GIM_Try, /*On fail goto*//*Label 244*/ 9947, // Rule ID 989 //
4564        GIM_CheckFeatures, GIFBS_HasNEON,
4565        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4566        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4567        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4568        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4569        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4570        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4571        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4572        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4573        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4574        GIM_CheckIsSafeToFold, /*InsnID*/1,
4575        GIM_CheckIsSafeToFold, /*InsnID*/2,
4576        // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4577        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv4i32,
4578        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4579        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4580        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4581        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4582        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4583        GIR_EraseFromParent, /*InsnID*/0,
4584        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4585        // GIR_Coverage, 989,
4586        GIR_Done,
4587      // Label 244: @9947
4588      GIM_Try, /*On fail goto*//*Label 245*/ 10016, // Rule ID 996 //
4589        GIM_CheckFeatures, GIFBS_HasNEON,
4590        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4591        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4592        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4593        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4594        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4595        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4596        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
4597        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4598        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4599        GIM_CheckIsSafeToFold, /*InsnID*/1,
4600        GIM_CheckIsSafeToFold, /*InsnID*/2,
4601        // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4602        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv4i32,
4603        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4604        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4605        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4606        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4607        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4608        GIR_EraseFromParent, /*InsnID*/0,
4609        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4610        // GIR_Coverage, 996,
4611        GIR_Done,
4612      // Label 245: @10016
4613      GIM_Try, /*On fail goto*//*Label 246*/ 10085, // Rule ID 995 //
4614        GIM_CheckFeatures, GIFBS_HasNEON,
4615        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4616        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4617        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4618        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4619        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4620        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4621        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4622        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4623        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4624        GIM_CheckIsSafeToFold, /*InsnID*/1,
4625        GIM_CheckIsSafeToFold, /*InsnID*/2,
4626        // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4627        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv4i32,
4628        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4629        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4630        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4631        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4632        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4633        GIR_EraseFromParent, /*InsnID*/0,
4634        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4635        // GIR_Coverage, 995,
4636        GIR_Done,
4637      // Label 246: @10085
4638      GIM_Try, /*On fail goto*//*Label 247*/ 10153, // Rule ID 936 //
4639        GIM_CheckFeatures, GIFBS_HasNEON,
4640        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4641        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4642        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4643        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4644        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4645        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4646        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4647        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4648        GIM_CheckIsSafeToFold, /*InsnID*/1,
4649        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VMLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4650        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv4i32,
4651        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4652        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4653        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4654        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4655        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4656        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4657        GIR_EraseFromParent, /*InsnID*/0,
4658        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4659        // GIR_Coverage, 936,
4660        GIR_Done,
4661      // Label 247: @10153
4662      GIM_Try, /*On fail goto*//*Label 248*/ 10209, // Rule ID 1009 //
4663        GIM_CheckFeatures, GIFBS_HasNEON,
4664        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4665        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4666        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4667        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
4668        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4669        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4670        GIM_CheckIsSafeToFold, /*InsnID*/1,
4671        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4672        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv4i32,
4673        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4674        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4675        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4676        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4677        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4678        GIR_EraseFromParent, /*InsnID*/0,
4679        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4680        // GIR_Coverage, 1009,
4681        GIR_Done,
4682      // Label 248: @10209
4683      GIM_Try, /*On fail goto*//*Label 249*/ 10265, // Rule ID 1004 //
4684        GIM_CheckFeatures, GIFBS_HasNEON,
4685        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4686        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4687        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4688        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4689        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4690        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4691        GIM_CheckIsSafeToFold, /*InsnID*/1,
4692        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4693        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv4i32,
4694        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4695        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4696        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4697        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4698        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4699        GIR_EraseFromParent, /*InsnID*/0,
4700        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4701        // GIR_Coverage, 1004,
4702        GIR_Done,
4703      // Label 249: @10265
4704      GIM_Try, /*On fail goto*//*Label 250*/ 10321, // Rule ID 1008 //
4705        GIM_CheckFeatures, GIFBS_HasNEON,
4706        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4707        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4708        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4709        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4710        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4711        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4712        GIM_CheckIsSafeToFold, /*InsnID*/1,
4713        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4714        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv4i32,
4715        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4716        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4717        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4718        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4719        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4720        GIR_EraseFromParent, /*InsnID*/0,
4721        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4722        // GIR_Coverage, 1008,
4723        GIR_Done,
4724      // Label 250: @10321
4725      GIM_Try, /*On fail goto*//*Label 251*/ 10364, // Rule ID 981 //
4726        GIM_CheckFeatures, GIFBS_HasNEON,
4727        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4728        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4729        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4730        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VSUBv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4731        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv4i32,
4732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4733        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4734        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4735        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4736        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4737        GIR_EraseFromParent, /*InsnID*/0,
4738        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4739        // GIR_Coverage, 981,
4740        GIR_Done,
4741      // Label 251: @10364
4742      GIM_Try, /*On fail goto*//*Label 252*/ 10425, // Rule ID 3602 //
4743        GIM_CheckFeatures, GIFBS_HasMVEInt,
4744        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
4745        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
4746        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
4747        // (sub:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VSUBi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
4748        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4749        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
4750        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
4751        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBi32,
4752        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
4753        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
4754        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
4755        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4756        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4757        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4758        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4759        GIR_EraseFromParent, /*InsnID*/0,
4760        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4761        // GIR_Coverage, 3602,
4762        GIR_Done,
4763      // Label 252: @10425
4764      GIM_Reject,
4765    // Label 241: @10426
4766    GIM_Reject,
4767    // Label 210: @10427
4768    GIM_Try, /*On fail goto*//*Label 253*/ 10541,
4769      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
4770      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
4771      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4772      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4773      GIM_Try, /*On fail goto*//*Label 254*/ 10505, // Rule ID 931 //
4774        GIM_CheckFeatures, GIFBS_HasNEON,
4775        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4776        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4777        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4778        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4779        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4780        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4781        GIM_CheckIsSafeToFold, /*InsnID*/1,
4782        // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VMLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4783        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv8i8,
4784        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4785        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4786        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4787        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4788        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4789        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4790        GIR_EraseFromParent, /*InsnID*/0,
4791        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4792        // GIR_Coverage, 931,
4793        GIR_Done,
4794      // Label 254: @10505
4795      GIM_Try, /*On fail goto*//*Label 255*/ 10540, // Rule ID 976 //
4796        GIM_CheckFeatures, GIFBS_HasNEON,
4797        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4798        // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VSUBv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4799        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv8i8,
4800        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4801        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4802        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4803        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4804        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4805        GIR_EraseFromParent, /*InsnID*/0,
4806        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4807        // GIR_Coverage, 976,
4808        GIR_Done,
4809      // Label 255: @10540
4810      GIM_Reject,
4811    // Label 253: @10541
4812    GIM_Reject,
4813    // Label 211: @10542
4814    GIM_Try, /*On fail goto*//*Label 256*/ 11238,
4815      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4816      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4817      GIM_Try, /*On fail goto*//*Label 257*/ 10621, // Rule ID 994 //
4818        GIM_CheckFeatures, GIFBS_HasNEON,
4819        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4820        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4821        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
4822        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4823        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4824        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4825        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
4826        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4827        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4828        GIM_CheckIsSafeToFold, /*InsnID*/1,
4829        GIM_CheckIsSafeToFold, /*InsnID*/2,
4830        // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4831        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv8i16,
4832        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4834        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4835        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4836        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4837        GIR_EraseFromParent, /*InsnID*/0,
4838        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4839        // GIR_Coverage, 994,
4840        GIR_Done,
4841      // Label 257: @10621
4842      GIM_Try, /*On fail goto*//*Label 258*/ 10690, // Rule ID 993 //
4843        GIM_CheckFeatures, GIFBS_HasNEON,
4844        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4845        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4846        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
4847        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4848        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4849        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4850        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4851        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4852        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4853        GIM_CheckIsSafeToFold, /*InsnID*/1,
4854        GIM_CheckIsSafeToFold, /*InsnID*/2,
4855        // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4856        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv8i16,
4857        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4858        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4859        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4860        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4861        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4862        GIR_EraseFromParent, /*InsnID*/0,
4863        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4864        // GIR_Coverage, 993,
4865        GIR_Done,
4866      // Label 258: @10690
4867      GIM_Try, /*On fail goto*//*Label 259*/ 10759, // Rule ID 988 //
4868        GIM_CheckFeatures, GIFBS_HasNEON,
4869        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4870        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4871        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4872        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4873        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4874        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4875        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4876        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4877        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4878        GIM_CheckIsSafeToFold, /*InsnID*/1,
4879        GIM_CheckIsSafeToFold, /*InsnID*/2,
4880        // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4881        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv8i16,
4882        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4883        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4884        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4885        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4886        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4887        GIR_EraseFromParent, /*InsnID*/0,
4888        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4889        // GIR_Coverage, 988,
4890        GIR_Done,
4891      // Label 259: @10759
4892      GIM_Try, /*On fail goto*//*Label 260*/ 10828, // Rule ID 992 //
4893        GIM_CheckFeatures, GIFBS_HasNEON,
4894        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4895        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4896        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4897        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4898        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4899        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4900        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
4901        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4902        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4903        GIM_CheckIsSafeToFold, /*InsnID*/1,
4904        GIM_CheckIsSafeToFold, /*InsnID*/2,
4905        // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4906        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv8i16,
4907        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4908        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4909        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4910        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4911        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4912        GIR_EraseFromParent, /*InsnID*/0,
4913        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4914        // GIR_Coverage, 992,
4915        GIR_Done,
4916      // Label 260: @10828
4917      GIM_Try, /*On fail goto*//*Label 261*/ 10897, // Rule ID 991 //
4918        GIM_CheckFeatures, GIFBS_HasNEON,
4919        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4920        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4921        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4922        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4923        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4924        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4925        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4926        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4927        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4928        GIM_CheckIsSafeToFold, /*InsnID*/1,
4929        GIM_CheckIsSafeToFold, /*InsnID*/2,
4930        // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4931        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv8i16,
4932        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4933        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4934        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4935        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4936        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4937        GIR_EraseFromParent, /*InsnID*/0,
4938        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4939        // GIR_Coverage, 991,
4940        GIR_Done,
4941      // Label 261: @10897
4942      GIM_Try, /*On fail goto*//*Label 262*/ 10965, // Rule ID 935 //
4943        GIM_CheckFeatures, GIFBS_HasNEON,
4944        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4945        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4946        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4947        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4948        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
4949        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
4950        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4951        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4952        GIM_CheckIsSafeToFold, /*InsnID*/1,
4953        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VMLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
4954        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv8i16,
4955        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4956        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4957        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4958        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4959        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4960        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4961        GIR_EraseFromParent, /*InsnID*/0,
4962        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4963        // GIR_Coverage, 935,
4964        GIR_Done,
4965      // Label 262: @10965
4966      GIM_Try, /*On fail goto*//*Label 263*/ 11021, // Rule ID 1007 //
4967        GIM_CheckFeatures, GIFBS_HasNEON,
4968        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4969        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4970        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4971        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
4972        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4973        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4974        GIM_CheckIsSafeToFold, /*InsnID*/1,
4975        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4976        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv8i16,
4977        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4978        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4979        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4980        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4981        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4982        GIR_EraseFromParent, /*InsnID*/0,
4983        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4984        // GIR_Coverage, 1007,
4985        GIR_Done,
4986      // Label 263: @11021
4987      GIM_Try, /*On fail goto*//*Label 264*/ 11077, // Rule ID 1003 //
4988        GIM_CheckFeatures, GIFBS_HasNEON,
4989        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4990        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4991        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4992        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4993        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4994        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4995        GIM_CheckIsSafeToFold, /*InsnID*/1,
4996        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4997        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv8i16,
4998        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4999        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5000        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5001        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5002        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5003        GIR_EraseFromParent, /*InsnID*/0,
5004        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5005        // GIR_Coverage, 1003,
5006        GIR_Done,
5007      // Label 264: @11077
5008      GIM_Try, /*On fail goto*//*Label 265*/ 11133, // Rule ID 1006 //
5009        GIM_CheckFeatures, GIFBS_HasNEON,
5010        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
5011        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
5012        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5013        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
5014        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5015        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
5016        GIM_CheckIsSafeToFold, /*InsnID*/1,
5017        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5018        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv8i16,
5019        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5020        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5021        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5022        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5023        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5024        GIR_EraseFromParent, /*InsnID*/0,
5025        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5026        // GIR_Coverage, 1006,
5027        GIR_Done,
5028      // Label 265: @11133
5029      GIM_Try, /*On fail goto*//*Label 266*/ 11176, // Rule ID 980 //
5030        GIM_CheckFeatures, GIFBS_HasNEON,
5031        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
5032        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
5033        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
5034        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VSUBv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
5035        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv8i16,
5036        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5037        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5038        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5039        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5040        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5041        GIR_EraseFromParent, /*InsnID*/0,
5042        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5043        // GIR_Coverage, 980,
5044        GIR_Done,
5045      // Label 266: @11176
5046      GIM_Try, /*On fail goto*//*Label 267*/ 11237, // Rule ID 3598 //
5047        GIM_CheckFeatures, GIFBS_HasMVEInt,
5048        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
5049        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
5050        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
5051        // (sub:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VSUBi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
5052        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5053        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
5054        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
5055        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBi16,
5056        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
5057        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
5058        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
5059        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5060        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5061        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5062        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
5063        GIR_EraseFromParent, /*InsnID*/0,
5064        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5065        // GIR_Coverage, 3598,
5066        GIR_Done,
5067      // Label 267: @11237
5068      GIM_Reject,
5069    // Label 256: @11238
5070    GIM_Reject,
5071    // Label 212: @11239
5072    GIM_Try, /*On fail goto*//*Label 268*/ 11422,
5073      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
5074      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5075      GIM_Try, /*On fail goto*//*Label 269*/ 11317, // Rule ID 934 //
5076        GIM_CheckFeatures, GIFBS_HasNEON,
5077        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
5078        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
5079        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5080        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
5081        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
5082        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
5083        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
5084        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
5085        GIM_CheckIsSafeToFold, /*InsnID*/1,
5086        // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VMLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
5087        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv16i8,
5088        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5089        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
5090        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5091        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5092        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5093        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5094        GIR_EraseFromParent, /*InsnID*/0,
5095        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5096        // GIR_Coverage, 934,
5097        GIR_Done,
5098      // Label 269: @11317
5099      GIM_Try, /*On fail goto*//*Label 270*/ 11360, // Rule ID 979 //
5100        GIM_CheckFeatures, GIFBS_HasNEON,
5101        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
5102        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
5103        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
5104        // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VSUBv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
5105        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv16i8,
5106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5107        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5108        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5109        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5110        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5111        GIR_EraseFromParent, /*InsnID*/0,
5112        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5113        // GIR_Coverage, 979,
5114        GIR_Done,
5115      // Label 270: @11360
5116      GIM_Try, /*On fail goto*//*Label 271*/ 11421, // Rule ID 3594 //
5117        GIM_CheckFeatures, GIFBS_HasMVEInt,
5118        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
5119        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
5120        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
5121        // (sub:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VSUBi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
5122        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5123        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
5124        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
5125        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBi8,
5126        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
5127        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
5128        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
5129        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5130        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5131        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5132        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
5133        GIR_EraseFromParent, /*InsnID*/0,
5134        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5135        // GIR_Coverage, 3594,
5136        GIR_Done,
5137      // Label 271: @11421
5138      GIM_Reject,
5139    // Label 268: @11422
5140    GIM_Reject,
5141    // Label 213: @11423
5142    GIM_Reject,
5143    // Label 2: @11424
5144    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 16, /*)*//*default:*//*Label 279*/ 12268,
5145    /*GILLT_s32*//*Label 272*/ 11445, 0, 0,
5146    /*GILLT_v2s32*//*Label 273*/ 11764, 0, 0,
5147    /*GILLT_v4s16*//*Label 274*/ 11816,
5148    /*GILLT_v4s32*//*Label 275*/ 11868, 0, 0,
5149    /*GILLT_v8s8*//*Label 276*/ 11984,
5150    /*GILLT_v8s16*//*Label 277*/ 12036, 0, 0,
5151    /*GILLT_v16s8*//*Label 278*/ 12152,
5152    // Label 272: @11445
5153    GIM_Try, /*On fail goto*//*Label 280*/ 11763,
5154      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
5155      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5156      GIM_Try, /*On fail goto*//*Label 281*/ 11540, // Rule ID 186 //
5157        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
5158        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5159        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5160        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
5161        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5162        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5163        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5164        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16,
5165        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5166        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
5167        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5168        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5169        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5170        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
5171        GIM_CheckIsSafeToFold, /*InsnID*/1,
5172        GIM_CheckIsSafeToFold, /*InsnID*/2,
5173        // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))  =>  (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5174        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULTT,
5175        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5176        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5177        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5178        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5179        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5180        GIR_EraseFromParent, /*InsnID*/0,
5181        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5182        // GIR_Coverage, 186,
5183        GIR_Done,
5184      // Label 281: @11540
5185      GIM_Try, /*On fail goto*//*Label 282*/ 11625, // Rule ID 522 //
5186        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
5187        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5188        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5189        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
5190        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5191        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5192        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5193        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16,
5194        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5195        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
5196        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5197        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5198        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5199        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
5200        GIM_CheckIsSafeToFold, /*InsnID*/1,
5201        GIM_CheckIsSafeToFold, /*InsnID*/2,
5202        // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))  =>  (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5203        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULTT,
5204        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5205        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5206        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5207        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5208        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5209        GIR_EraseFromParent, /*InsnID*/0,
5210        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5211        // GIR_Coverage, 522,
5212        GIR_Done,
5213      // Label 282: @11625
5214      GIM_Try, /*On fail goto*//*Label 283*/ 11672, // Rule ID 169 //
5215        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5216        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5217        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5218        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
5219        // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (MUL:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
5220        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MUL,
5221        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5222        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5223        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5224        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5225        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5226        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5227        GIR_EraseFromParent, /*InsnID*/0,
5228        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5229        // GIR_Coverage, 169,
5230        GIR_Done,
5231      // Label 283: @11672
5232      GIM_Try, /*On fail goto*//*Label 284*/ 11719, // Rule ID 170 //
5233        GIM_CheckFeatures, GIFBS_IsARM_NoV6_UseMulOps,
5234        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5235        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5236        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
5237        // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (MULv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
5238        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MULv5,
5239        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5240        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5241        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5242        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5243        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5244        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5245        GIR_EraseFromParent, /*InsnID*/0,
5246        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5247        // GIR_Coverage, 170,
5248        GIR_Done,
5249      // Label 284: @11719
5250      GIM_Try, /*On fail goto*//*Label 285*/ 11762, // Rule ID 509 //
5251        GIM_CheckFeatures, GIFBS_IsThumb2,
5252        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5253        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5254        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
5255        // (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2MUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5256        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MUL,
5257        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5258        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5259        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5260        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5261        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5262        GIR_EraseFromParent, /*InsnID*/0,
5263        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5264        // GIR_Coverage, 509,
5265        GIR_Done,
5266      // Label 285: @11762
5267      GIM_Reject,
5268    // Label 280: @11763
5269    GIM_Reject,
5270    // Label 273: @11764
5271    GIM_Try, /*On fail goto*//*Label 286*/ 11815, // Rule ID 853 //
5272      GIM_CheckFeatures, GIFBS_HasNEON,
5273      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
5274      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
5275      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
5276      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
5277      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
5278      // (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VMULv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5279      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv2i32,
5280      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5281      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5282      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5283      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5284      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5285      GIR_EraseFromParent, /*InsnID*/0,
5286      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5287      // GIR_Coverage, 853,
5288      GIR_Done,
5289    // Label 286: @11815
5290    GIM_Reject,
5291    // Label 274: @11816
5292    GIM_Try, /*On fail goto*//*Label 287*/ 11867, // Rule ID 852 //
5293      GIM_CheckFeatures, GIFBS_HasNEON,
5294      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
5295      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
5296      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
5297      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
5298      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
5299      // (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VMULv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5300      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv4i16,
5301      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5302      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5303      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5304      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5305      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5306      GIR_EraseFromParent, /*InsnID*/0,
5307      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5308      // GIR_Coverage, 852,
5309      GIR_Done,
5310    // Label 287: @11867
5311    GIM_Reject,
5312    // Label 275: @11868
5313    GIM_Try, /*On fail goto*//*Label 288*/ 11983,
5314      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
5315      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5316      GIM_Try, /*On fail goto*//*Label 289*/ 11921, // Rule ID 856 //
5317        GIM_CheckFeatures, GIFBS_HasNEON,
5318        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
5319        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
5320        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
5321        // (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VMULv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
5322        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv4i32,
5323        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5324        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5325        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5326        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5327        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5328        GIR_EraseFromParent, /*InsnID*/0,
5329        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5330        // GIR_Coverage, 856,
5331        GIR_Done,
5332      // Label 289: @11921
5333      GIM_Try, /*On fail goto*//*Label 290*/ 11982, // Rule ID 3560 //
5334        GIM_CheckFeatures, GIFBS_HasMVEInt,
5335        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
5336        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
5337        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
5338        // (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VMULi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
5339        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5340        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
5341        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
5342        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULi32,
5343        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
5344        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
5345        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
5346        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5347        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5348        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5349        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
5350        GIR_EraseFromParent, /*InsnID*/0,
5351        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5352        // GIR_Coverage, 3560,
5353        GIR_Done,
5354      // Label 290: @11982
5355      GIM_Reject,
5356    // Label 288: @11983
5357    GIM_Reject,
5358    // Label 276: @11984
5359    GIM_Try, /*On fail goto*//*Label 291*/ 12035, // Rule ID 851 //
5360      GIM_CheckFeatures, GIFBS_HasNEON,
5361      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
5362      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
5363      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
5364      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
5365      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
5366      // (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMULv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5367      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv8i8,
5368      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5369      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5370      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5371      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5372      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5373      GIR_EraseFromParent, /*InsnID*/0,
5374      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5375      // GIR_Coverage, 851,
5376      GIR_Done,
5377    // Label 291: @12035
5378    GIM_Reject,
5379    // Label 277: @12036
5380    GIM_Try, /*On fail goto*//*Label 292*/ 12151,
5381      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
5382      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5383      GIM_Try, /*On fail goto*//*Label 293*/ 12089, // Rule ID 855 //
5384        GIM_CheckFeatures, GIFBS_HasNEON,
5385        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
5386        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
5387        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
5388        // (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VMULv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
5389        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv8i16,
5390        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5391        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5392        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5393        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5394        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5395        GIR_EraseFromParent, /*InsnID*/0,
5396        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5397        // GIR_Coverage, 855,
5398        GIR_Done,
5399      // Label 293: @12089
5400      GIM_Try, /*On fail goto*//*Label 294*/ 12150, // Rule ID 3556 //
5401        GIM_CheckFeatures, GIFBS_HasMVEInt,
5402        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
5403        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
5404        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
5405        // (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VMULi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
5406        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5407        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
5408        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
5409        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULi16,
5410        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
5411        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
5412        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
5413        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5414        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5415        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5416        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
5417        GIR_EraseFromParent, /*InsnID*/0,
5418        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5419        // GIR_Coverage, 3556,
5420        GIR_Done,
5421      // Label 294: @12150
5422      GIM_Reject,
5423    // Label 292: @12151
5424    GIM_Reject,
5425    // Label 278: @12152
5426    GIM_Try, /*On fail goto*//*Label 295*/ 12267,
5427      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
5428      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5429      GIM_Try, /*On fail goto*//*Label 296*/ 12205, // Rule ID 854 //
5430        GIM_CheckFeatures, GIFBS_HasNEON,
5431        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
5432        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
5433        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
5434        // (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMULv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
5435        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv16i8,
5436        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5437        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5438        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5439        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5440        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5441        GIR_EraseFromParent, /*InsnID*/0,
5442        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5443        // GIR_Coverage, 854,
5444        GIR_Done,
5445      // Label 296: @12205
5446      GIM_Try, /*On fail goto*//*Label 297*/ 12266, // Rule ID 3552 //
5447        GIM_CheckFeatures, GIFBS_HasMVEInt,
5448        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
5449        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
5450        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
5451        // (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VMULi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
5452        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5453        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
5454        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
5455        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULi8,
5456        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
5457        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
5458        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
5459        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5460        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5461        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5462        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
5463        GIR_EraseFromParent, /*InsnID*/0,
5464        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5465        // GIR_Coverage, 3552,
5466        GIR_Done,
5467      // Label 297: @12266
5468      GIM_Reject,
5469    // Label 295: @12267
5470    GIM_Reject,
5471    // Label 279: @12268
5472    GIM_Reject,
5473    // Label 3: @12269
5474    GIM_Try, /*On fail goto*//*Label 298*/ 12370,
5475      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5476      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
5477      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5478      GIM_Try, /*On fail goto*//*Label 299*/ 12326, // Rule ID 195 //
5479        GIM_CheckFeatures, GIFBS_HasDivideInARM_IsARM,
5480        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5481        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5482        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
5483        // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (SDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5484        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SDIV,
5485        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5486        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5487        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5488        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5489        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5490        GIR_EraseFromParent, /*InsnID*/0,
5491        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5492        // GIR_Coverage, 195,
5493        GIR_Done,
5494      // Label 299: @12326
5495      GIM_Try, /*On fail goto*//*Label 300*/ 12369, // Rule ID 539 //
5496        GIM_CheckFeatures, GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
5497        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5498        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5499        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
5500        // (sdiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5501        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SDIV,
5502        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5503        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5504        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5505        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5506        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5507        GIR_EraseFromParent, /*InsnID*/0,
5508        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5509        // GIR_Coverage, 539,
5510        GIR_Done,
5511      // Label 300: @12369
5512      GIM_Reject,
5513    // Label 298: @12370
5514    GIM_Reject,
5515    // Label 4: @12371
5516    GIM_Try, /*On fail goto*//*Label 301*/ 12472,
5517      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5518      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
5519      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5520      GIM_Try, /*On fail goto*//*Label 302*/ 12428, // Rule ID 196 //
5521        GIM_CheckFeatures, GIFBS_HasDivideInARM_IsARM,
5522        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5523        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5524        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
5525        // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (UDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5526        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UDIV,
5527        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5528        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5529        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5530        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5531        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5532        GIR_EraseFromParent, /*InsnID*/0,
5533        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5534        // GIR_Coverage, 196,
5535        GIR_Done,
5536      // Label 302: @12428
5537      GIM_Try, /*On fail goto*//*Label 303*/ 12471, // Rule ID 540 //
5538        GIM_CheckFeatures, GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
5539        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5540        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5541        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
5542        // (udiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5543        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UDIV,
5544        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5545        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5546        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5547        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5548        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5549        GIR_EraseFromParent, /*InsnID*/0,
5550        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5551        // GIR_Coverage, 540,
5552        GIR_Done,
5553      // Label 303: @12471
5554      GIM_Reject,
5555    // Label 301: @12472
5556    GIM_Reject,
5557    // Label 5: @12473
5558    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 16, /*)*//*default:*//*Label 317*/ 15232,
5559    /*GILLT_s32*//*Label 304*/ 12494,
5560    /*GILLT_s64*//*Label 305*/ 14136,
5561    /*GILLT_v2s1*//*Label 306*/ 14188,
5562    /*GILLT_v2s32*//*Label 307*/ 14294,
5563    /*GILLT_v2s64*//*Label 308*/ 14346,
5564    /*GILLT_v4s1*//*Label 309*/ 14462,
5565    /*GILLT_v4s16*//*Label 310*/ 14568,
5566    /*GILLT_v4s32*//*Label 311*/ 14620, 0,
5567    /*GILLT_v8s1*//*Label 312*/ 14736,
5568    /*GILLT_v8s8*//*Label 313*/ 14842,
5569    /*GILLT_v8s16*//*Label 314*/ 14894, 0,
5570    /*GILLT_v16s1*//*Label 315*/ 15010,
5571    /*GILLT_v16s8*//*Label 316*/ 15116,
5572    // Label 304: @12494
5573    GIM_Try, /*On fail goto*//*Label 318*/ 14135,
5574      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
5575      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5576      GIM_Try, /*On fail goto*//*Label 319*/ 12567, // Rule ID 1878 //
5577        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5578        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5579        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5580        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
5581        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5582        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5583        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5584        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 8,
5585        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
5586        GIM_CheckIsSafeToFold, /*InsnID*/1,
5587        // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] })  =>  (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
5588        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16,
5589        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5590        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
5591        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
5592        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5593        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5594        GIR_EraseFromParent, /*InsnID*/0,
5595        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5596        // GIR_Coverage, 1878,
5597        GIR_Done,
5598      // Label 319: @12567
5599      GIM_Try, /*On fail goto*//*Label 320*/ 12630, // Rule ID 2120 //
5600        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
5601        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5602        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5603        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
5604        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5605        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5606        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5607        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 8,
5608        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
5609        GIM_CheckIsSafeToFold, /*InsnID*/1,
5610        // (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] })  =>  (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
5611        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16,
5612        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5613        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
5614        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
5615        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5616        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5617        GIR_EraseFromParent, /*InsnID*/0,
5618        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5619        // GIR_Coverage, 2120,
5620        GIR_Done,
5621      // Label 320: @12630
5622      GIM_Try, /*On fail goto*//*Label 321*/ 12672, // Rule ID 2012 //
5623        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5624        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5625        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5626        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
5627        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 255:{ *:[i32] })  =>  (UXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
5628        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB,
5629        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5630        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
5631        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5632        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5633        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5634        GIR_EraseFromParent, /*InsnID*/0,
5635        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5636        // GIR_Coverage, 2012,
5637        GIR_Done,
5638      // Label 321: @12672
5639      GIM_Try, /*On fail goto*//*Label 322*/ 12714, // Rule ID 2013 //
5640        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5641        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5642        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5643        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
5644        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 65535:{ *:[i32] })  =>  (UXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
5645        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTH,
5646        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5647        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
5648        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5649        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5650        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5651        GIR_EraseFromParent, /*InsnID*/0,
5652        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5653        // GIR_Coverage, 2013,
5654        GIR_Done,
5655      // Label 322: @12714
5656      GIM_Try, /*On fail goto*//*Label 323*/ 12756, // Rule ID 2014 //
5657        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5658        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5659        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5660        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
5661        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 16711935:{ *:[i32] })  =>  (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
5662        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16,
5663        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5664        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
5665        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5666        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5667        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5668        GIR_EraseFromParent, /*InsnID*/0,
5669        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5670        // GIR_Coverage, 2014,
5671        GIR_Done,
5672      // Label 323: @12756
5673      GIM_Try, /*On fail goto*//*Label 324*/ 12798, // Rule ID 2236 //
5674        GIM_CheckFeatures, GIFBS_IsThumb2,
5675        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5676        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5677        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
5678        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })  =>  (t2UXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
5679        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB,
5680        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5681        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
5682        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5683        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5684        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5685        GIR_EraseFromParent, /*InsnID*/0,
5686        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5687        // GIR_Coverage, 2236,
5688        GIR_Done,
5689      // Label 324: @12798
5690      GIM_Try, /*On fail goto*//*Label 325*/ 12840, // Rule ID 2237 //
5691        GIM_CheckFeatures, GIFBS_IsThumb2,
5692        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5693        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5694        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
5695        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })  =>  (t2UXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
5696        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTH,
5697        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5698        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
5699        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5700        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5701        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5702        GIR_EraseFromParent, /*InsnID*/0,
5703        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5704        // GIR_Coverage, 2237,
5705        GIR_Done,
5706      // Label 325: @12840
5707      GIM_Try, /*On fail goto*//*Label 326*/ 12882, // Rule ID 2238 //
5708        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
5709        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5710        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5711        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
5712        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16711935:{ *:[i32] })  =>  (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
5713        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16,
5714        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5715        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
5716        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5717        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5718        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5719        GIR_EraseFromParent, /*InsnID*/0,
5720        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5721        // GIR_Coverage, 2238,
5722        GIR_Done,
5723      // Label 326: @12882
5724      GIM_Try, /*On fail goto*//*Label 327*/ 12957, // Rule ID 5539 //
5725        GIM_CheckFeatures, GIFBS_IsARM,
5726        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5727        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5728        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5729        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5730        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5731        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
5732        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5733        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5734        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
5735        // MIs[2] Operand 1
5736        // No operand predicates
5737        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
5738        GIM_CheckIsSafeToFold, /*InsnID*/1,
5739        GIM_CheckIsSafeToFold, /*InsnID*/2,
5740        // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm), GPR:{ *:[i32] }:$Rn)  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5741        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
5742        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5743        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5744        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5745        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5746        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5747        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5748        GIR_EraseFromParent, /*InsnID*/0,
5749        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5750        // GIR_Coverage, 5539,
5751        GIR_Done,
5752      // Label 327: @12957
5753      GIM_Try, /*On fail goto*//*Label 328*/ 13032, // Rule ID 5572 //
5754        GIM_CheckFeatures, GIFBS_IsThumb2,
5755        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5756        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5757        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5758        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5759        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5760        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
5761        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5762        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5763        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
5764        // MIs[2] Operand 1
5765        // No operand predicates
5766        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
5767        GIM_CheckIsSafeToFold, /*InsnID*/1,
5768        GIM_CheckIsSafeToFold, /*InsnID*/2,
5769        // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn)  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5770        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
5771        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5772        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5773        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5774        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5775        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5776        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5777        GIR_EraseFromParent, /*InsnID*/0,
5778        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5779        // GIR_Coverage, 5572,
5780        GIR_Done,
5781      // Label 328: @13032
5782      GIM_Try, /*On fail goto*//*Label 329*/ 13107, // Rule ID 5538 //
5783        GIM_CheckFeatures, GIFBS_IsARM,
5784        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5785        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5786        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5787        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5788        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5789        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5790        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5791        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
5792        // MIs[2] Operand 1
5793        // No operand predicates
5794        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
5795        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
5796        GIM_CheckIsSafeToFold, /*InsnID*/1,
5797        GIM_CheckIsSafeToFold, /*InsnID*/2,
5798        // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5799        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
5800        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5801        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5802        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5803        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5804        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5805        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5806        GIR_EraseFromParent, /*InsnID*/0,
5807        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5808        // GIR_Coverage, 5538,
5809        GIR_Done,
5810      // Label 329: @13107
5811      GIM_Try, /*On fail goto*//*Label 330*/ 13182, // Rule ID 5571 //
5812        GIM_CheckFeatures, GIFBS_IsThumb2,
5813        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5814        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5815        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5816        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5817        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5818        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5819        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5820        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
5821        // MIs[2] Operand 1
5822        // No operand predicates
5823        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
5824        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
5825        GIM_CheckIsSafeToFold, /*InsnID*/1,
5826        GIM_CheckIsSafeToFold, /*InsnID*/2,
5827        // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5828        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
5829        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5830        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5831        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5832        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5833        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5834        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5835        GIR_EraseFromParent, /*InsnID*/0,
5836        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5837        // GIR_Coverage, 5571,
5838        GIR_Done,
5839      // Label 330: @13182
5840      GIM_Try, /*On fail goto*//*Label 331*/ 13257, // Rule ID 5537 //
5841        GIM_CheckFeatures, GIFBS_IsARM,
5842        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5843        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5844        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5845        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5846        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5847        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5848        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
5849        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5850        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5851        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
5852        // MIs[2] Operand 1
5853        // No operand predicates
5854        GIM_CheckIsSafeToFold, /*InsnID*/1,
5855        GIM_CheckIsSafeToFold, /*InsnID*/2,
5856        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm))  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5857        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
5858        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5859        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5860        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5861        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5862        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5863        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5864        GIR_EraseFromParent, /*InsnID*/0,
5865        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5866        // GIR_Coverage, 5537,
5867        GIR_Done,
5868      // Label 331: @13257
5869      GIM_Try, /*On fail goto*//*Label 332*/ 13332, // Rule ID 5570 //
5870        GIM_CheckFeatures, GIFBS_IsThumb2,
5871        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5872        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5873        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5874        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5875        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5876        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5877        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
5878        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5879        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5880        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
5881        // MIs[2] Operand 1
5882        // No operand predicates
5883        GIM_CheckIsSafeToFold, /*InsnID*/1,
5884        GIM_CheckIsSafeToFold, /*InsnID*/2,
5885        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm))  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5886        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
5887        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5888        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5889        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5890        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5891        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5892        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5893        GIR_EraseFromParent, /*InsnID*/0,
5894        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5895        // GIR_Coverage, 5570,
5896        GIR_Done,
5897      // Label 332: @13332
5898      GIM_Try, /*On fail goto*//*Label 333*/ 13407, // Rule ID 159 //
5899        GIM_CheckFeatures, GIFBS_IsARM,
5900        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5901        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5902        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5903        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5904        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5905        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5906        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5907        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5908        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
5909        // MIs[2] Operand 1
5910        // No operand predicates
5911        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
5912        GIM_CheckIsSafeToFold, /*InsnID*/1,
5913        GIM_CheckIsSafeToFold, /*InsnID*/2,
5914        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }))  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5915        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
5916        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5917        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5918        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5919        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5920        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5921        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5922        GIR_EraseFromParent, /*InsnID*/0,
5923        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5924        // GIR_Coverage, 159,
5925        GIR_Done,
5926      // Label 333: @13407
5927      GIM_Try, /*On fail goto*//*Label 334*/ 13482, // Rule ID 497 //
5928        GIM_CheckFeatures, GIFBS_IsThumb2,
5929        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5930        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5931        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5932        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5933        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5934        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5935        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5936        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5937        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
5938        // MIs[2] Operand 1
5939        // No operand predicates
5940        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
5941        GIM_CheckIsSafeToFold, /*InsnID*/1,
5942        GIM_CheckIsSafeToFold, /*InsnID*/2,
5943        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }))  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5944        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
5945        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5946        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5947        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5948        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5949        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5950        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5951        GIR_EraseFromParent, /*InsnID*/0,
5952        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5953        // GIR_Coverage, 497,
5954        GIR_Done,
5955      // Label 334: @13482
5956      GIM_Try, /*On fail goto*//*Label 335*/ 13550, // Rule ID 5540 //
5957        GIM_CheckFeatures, GIFBS_IsARM,
5958        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5959        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5960        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5961        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5962        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5963        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5964        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
5965        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
5966        GIM_CheckIsSafeToFold, /*InsnID*/1,
5967        // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5968        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICrr,
5969        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5970        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5971        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
5972        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5973        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5974        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5975        GIR_EraseFromParent, /*InsnID*/0,
5976        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5977        // GIR_Coverage, 5540,
5978        GIR_Done,
5979      // Label 335: @13550
5980      GIM_Try, /*On fail goto*//*Label 336*/ 13618, // Rule ID 5573 //
5981        GIM_CheckFeatures, GIFBS_IsThumb2,
5982        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5983        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5984        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5985        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5986        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5987        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5988        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
5989        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
5990        GIM_CheckIsSafeToFold, /*InsnID*/1,
5991        // (and:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5992        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICrr,
5993        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5994        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5995        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
5996        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5997        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5998        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5999        GIR_EraseFromParent, /*InsnID*/0,
6000        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6001        // GIR_Coverage, 5573,
6002        GIR_Done,
6003      // Label 336: @13618
6004      GIM_Try, /*On fail goto*//*Label 337*/ 13686, // Rule ID 160 //
6005        GIM_CheckFeatures, GIFBS_IsARM,
6006        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
6007        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
6008        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6009        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
6010        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6011        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6012        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
6013        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
6014        GIM_CheckIsSafeToFold, /*InsnID*/1,
6015        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }))  =>  (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6016        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICrr,
6017        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6018        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6019        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6020        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6021        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6022        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6023        GIR_EraseFromParent, /*InsnID*/0,
6024        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6025        // GIR_Coverage, 160,
6026        GIR_Done,
6027      // Label 337: @13686
6028      GIM_Try, /*On fail goto*//*Label 338*/ 13754, // Rule ID 498 //
6029        GIM_CheckFeatures, GIFBS_IsThumb2,
6030        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6031        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6032        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6033        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
6034        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6035        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6036        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6037        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
6038        GIM_CheckIsSafeToFold, /*InsnID*/1,
6039        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }))  =>  (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6040        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICrr,
6041        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6042        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6044        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6045        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6046        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6047        GIR_EraseFromParent, /*InsnID*/0,
6048        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6049        // GIR_Coverage, 498,
6050        GIR_Done,
6051      // Label 338: @13754
6052      GIM_Try, /*On fail goto*//*Label 339*/ 13793, // Rule ID 352 //
6053        GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only,
6054        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID,
6055        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::tGPRRegClassID,
6056        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
6057        // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })  =>  (tUXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
6058        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tUXTB,
6059        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6060        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
6061        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6062        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6063        GIR_EraseFromParent, /*InsnID*/0,
6064        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6065        // GIR_Coverage, 352,
6066        GIR_Done,
6067      // Label 339: @13793
6068      GIM_Try, /*On fail goto*//*Label 340*/ 13832, // Rule ID 353 //
6069        GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only,
6070        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID,
6071        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::tGPRRegClassID,
6072        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
6073        // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })  =>  (tUXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
6074        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tUXTH,
6075        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6076        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
6077        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6078        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6079        GIR_EraseFromParent, /*InsnID*/0,
6080        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6081        // GIR_Coverage, 353,
6082        GIR_Done,
6083      // Label 340: @13832
6084      GIM_Try, /*On fail goto*//*Label 341*/ 13886, // Rule ID 147 //
6085        GIM_CheckFeatures, GIFBS_IsARM,
6086        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
6087        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
6088        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6089        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6090        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
6091        // MIs[1] Operand 1
6092        // No operand predicates
6093        GIM_CheckIsSafeToFold, /*InsnID*/1,
6094        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (ANDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6095        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ANDri,
6096        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6097        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6098        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6099        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6100        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6101        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6102        GIR_EraseFromParent, /*InsnID*/0,
6103        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6104        // GIR_Coverage, 147,
6105        GIR_Done,
6106      // Label 341: @13886
6107      GIM_Try, /*On fail goto*//*Label 342*/ 13940, // Rule ID 488 //
6108        GIM_CheckFeatures, GIFBS_IsThumb2,
6109        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6110        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6111        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6112        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6113        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
6114        // MIs[1] Operand 1
6115        // No operand predicates
6116        GIM_CheckIsSafeToFold, /*InsnID*/1,
6117        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2ANDri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6118        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ANDri,
6119        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6120        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6121        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6122        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6123        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6124        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6125        GIR_EraseFromParent, /*InsnID*/0,
6126        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6127        // GIR_Coverage, 488,
6128        GIR_Done,
6129      // Label 342: @13940
6130      GIM_Try, /*On fail goto*//*Label 343*/ 13990, // Rule ID 163 //
6131        GIM_CheckFeatures, GIFBS_HasV6T2_IsARM,
6132        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
6133        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
6134        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6135        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6136        // MIs[1] Operand 1
6137        // No operand predicates
6138        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_bf_inv_mask_imm,
6139        GIM_CheckIsSafeToFold, /*InsnID*/1,
6140        // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm)  =>  (BFC:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm)
6141        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BFC,
6142        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6143        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
6144        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6145        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6146        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6147        GIR_EraseFromParent, /*InsnID*/0,
6148        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6149        // GIR_Coverage, 163,
6150        GIR_Done,
6151      // Label 343: @13990
6152      GIM_Try, /*On fail goto*//*Label 344*/ 14040, // Rule ID 500 //
6153        GIM_CheckFeatures, GIFBS_IsThumb2,
6154        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6155        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6156        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6157        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6158        // MIs[1] Operand 1
6159        // No operand predicates
6160        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_bf_inv_mask_imm,
6161        GIM_CheckIsSafeToFold, /*InsnID*/1,
6162        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm)  =>  (t2BFC:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm)
6163        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BFC,
6164        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6165        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
6166        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6167        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6168        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6169        GIR_EraseFromParent, /*InsnID*/0,
6170        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6171        // GIR_Coverage, 500,
6172        GIR_Done,
6173      // Label 344: @14040
6174      GIM_Try, /*On fail goto*//*Label 345*/ 14087, // Rule ID 148 //
6175        GIM_CheckFeatures, GIFBS_IsARM,
6176        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
6177        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
6178        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
6179        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (ANDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6180        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ANDrr,
6181        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6182        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6183        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
6184        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6185        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6186        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6187        GIR_EraseFromParent, /*InsnID*/0,
6188        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6189        // GIR_Coverage, 148,
6190        GIR_Done,
6191      // Label 345: @14087
6192      GIM_Try, /*On fail goto*//*Label 346*/ 14134, // Rule ID 489 //
6193        GIM_CheckFeatures, GIFBS_IsThumb2,
6194        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6195        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6196        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
6197        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2ANDrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6198        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ANDrr,
6199        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6200        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6201        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
6202        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6203        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6204        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6205        GIR_EraseFromParent, /*InsnID*/0,
6206        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6207        // GIR_Coverage, 489,
6208        GIR_Done,
6209      // Label 346: @14134
6210      GIM_Reject,
6211    // Label 318: @14135
6212    GIM_Reject,
6213    // Label 305: @14136
6214    GIM_Try, /*On fail goto*//*Label 347*/ 14187, // Rule ID 2520 //
6215      GIM_CheckFeatures, GIFBS_HasNEON,
6216      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
6217      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
6218      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
6219      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
6220      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
6221      // (and:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)  =>  (VANDd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)
6222      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VANDd,
6223      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
6224      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
6225      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
6226      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6227      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6228      GIR_EraseFromParent, /*InsnID*/0,
6229      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6230      // GIR_Coverage, 2520,
6231      GIR_Done,
6232    // Label 347: @14187
6233    GIM_Reject,
6234    // Label 306: @14188
6235    GIM_Try, /*On fail goto*//*Label 348*/ 14293, // Rule ID 1850 //
6236      GIM_CheckFeatures, GIFBS_HasMVEInt,
6237      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s1,
6238      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s1,
6239      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
6240      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
6241      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
6242      // (and:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
6243      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6244      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
6245      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
6246      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
6247      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
6248      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
6249      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
6250      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
6251      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
6252      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
6253      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
6254      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ANDrr,
6255      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
6256      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
6257      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
6258      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
6259      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6260      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6261      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6262      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6263      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
6264      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
6265      GIR_EraseFromParent, /*InsnID*/0,
6266      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::VCCRRegClassID,
6267      // GIR_Coverage, 1850,
6268      GIR_Done,
6269    // Label 348: @14293
6270    GIM_Reject,
6271    // Label 307: @14294
6272    GIM_Try, /*On fail goto*//*Label 349*/ 14345, // Rule ID 1149 //
6273      GIM_CheckFeatures, GIFBS_HasNEON,
6274      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
6275      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
6276      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
6277      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
6278      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
6279      // (and:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VANDd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
6280      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VANDd,
6281      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
6282      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
6283      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
6284      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6285      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6286      GIR_EraseFromParent, /*InsnID*/0,
6287      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6288      // GIR_Coverage, 1149,
6289      GIR_Done,
6290    // Label 349: @14345
6291    GIM_Reject,
6292    // Label 308: @14346
6293    GIM_Try, /*On fail goto*//*Label 350*/ 14461,
6294      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
6295      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6296      GIM_Try, /*On fail goto*//*Label 351*/ 14399, // Rule ID 2523 //
6297        GIM_CheckFeatures, GIFBS_HasNEON,
6298        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
6299        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
6300        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
6301        // (and:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)  =>  (VANDq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)
6302        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VANDq,
6303        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
6304        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
6305        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
6306        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6307        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6308        GIR_EraseFromParent, /*InsnID*/0,
6309        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6310        // GIR_Coverage, 2523,
6311        GIR_Done,
6312      // Label 351: @14399
6313      GIM_Try, /*On fail goto*//*Label 352*/ 14460, // Rule ID 3464 //
6314        GIM_CheckFeatures, GIFBS_HasMVEInt,
6315        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
6316        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
6317        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
6318        // (and:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)  =>  (MVE_VAND:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
6319        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6320        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
6321        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
6322        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VAND,
6323        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
6324        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
6325        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
6326        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
6327        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6328        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6329        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
6330        GIR_EraseFromParent, /*InsnID*/0,
6331        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6332        // GIR_Coverage, 3464,
6333        GIR_Done,
6334      // Label 352: @14460
6335      GIM_Reject,
6336    // Label 350: @14461
6337    GIM_Reject,
6338    // Label 309: @14462
6339    GIM_Try, /*On fail goto*//*Label 353*/ 14567, // Rule ID 1851 //
6340      GIM_CheckFeatures, GIFBS_HasMVEInt,
6341      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1,
6342      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1,
6343      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
6344      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
6345      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
6346      // (and:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
6347      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6348      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
6349      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
6350      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
6351      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
6352      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
6353      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
6354      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
6355      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
6356      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
6357      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
6358      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ANDrr,
6359      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
6360      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
6361      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
6362      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
6363      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6364      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6365      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6366      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6367      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
6368      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
6369      GIR_EraseFromParent, /*InsnID*/0,
6370      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::VCCRRegClassID,
6371      // GIR_Coverage, 1851,
6372      GIR_Done,
6373    // Label 353: @14567
6374    GIM_Reject,
6375    // Label 310: @14568
6376    GIM_Try, /*On fail goto*//*Label 354*/ 14619, // Rule ID 2519 //
6377      GIM_CheckFeatures, GIFBS_HasNEON,
6378      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
6379      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
6380      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
6381      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
6382      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
6383      // (and:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)  =>  (VANDd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)
6384      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VANDd,
6385      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
6386      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
6387      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
6388      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6389      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6390      GIR_EraseFromParent, /*InsnID*/0,
6391      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6392      // GIR_Coverage, 2519,
6393      GIR_Done,
6394    // Label 354: @14619
6395    GIM_Reject,
6396    // Label 311: @14620
6397    GIM_Try, /*On fail goto*//*Label 355*/ 14735,
6398      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
6399      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6400      GIM_Try, /*On fail goto*//*Label 356*/ 14673, // Rule ID 1150 //
6401        GIM_CheckFeatures, GIFBS_HasNEON,
6402        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
6403        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
6404        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
6405        // (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VANDq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
6406        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VANDq,
6407        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
6408        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
6409        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
6410        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6411        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6412        GIR_EraseFromParent, /*InsnID*/0,
6413        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6414        // GIR_Coverage, 1150,
6415        GIR_Done,
6416      // Label 356: @14673
6417      GIM_Try, /*On fail goto*//*Label 357*/ 14734, // Rule ID 3460 //
6418        GIM_CheckFeatures, GIFBS_HasMVEInt,
6419        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
6420        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
6421        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
6422        // (and:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VAND:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
6423        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6424        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
6425        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
6426        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VAND,
6427        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
6428        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
6429        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
6430        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
6431        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6432        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6433        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
6434        GIR_EraseFromParent, /*InsnID*/0,
6435        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6436        // GIR_Coverage, 3460,
6437        GIR_Done,
6438      // Label 357: @14734
6439      GIM_Reject,
6440    // Label 355: @14735
6441    GIM_Reject,
6442    // Label 312: @14736
6443    GIM_Try, /*On fail goto*//*Label 358*/ 14841, // Rule ID 1852 //
6444      GIM_CheckFeatures, GIFBS_HasMVEInt,
6445      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1,
6446      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1,
6447      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
6448      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
6449      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
6450      // (and:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
6451      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6452      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
6453      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
6454      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
6455      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
6456      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
6457      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
6458      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
6459      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
6460      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
6461      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
6462      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ANDrr,
6463      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
6464      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
6465      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
6466      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
6467      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6468      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6469      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6470      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6471      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
6472      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
6473      GIR_EraseFromParent, /*InsnID*/0,
6474      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::VCCRRegClassID,
6475      // GIR_Coverage, 1852,
6476      GIR_Done,
6477    // Label 358: @14841
6478    GIM_Reject,
6479    // Label 313: @14842
6480    GIM_Try, /*On fail goto*//*Label 359*/ 14893, // Rule ID 2518 //
6481      GIM_CheckFeatures, GIFBS_HasNEON,
6482      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
6483      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
6484      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
6485      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
6486      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
6487      // (and:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)  =>  (VANDd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)
6488      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VANDd,
6489      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
6490      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
6491      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
6492      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6493      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6494      GIR_EraseFromParent, /*InsnID*/0,
6495      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6496      // GIR_Coverage, 2518,
6497      GIR_Done,
6498    // Label 359: @14893
6499    GIM_Reject,
6500    // Label 314: @14894
6501    GIM_Try, /*On fail goto*//*Label 360*/ 15009,
6502      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
6503      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6504      GIM_Try, /*On fail goto*//*Label 361*/ 14947, // Rule ID 2522 //
6505        GIM_CheckFeatures, GIFBS_HasNEON,
6506        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
6507        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
6508        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
6509        // (and:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)  =>  (VANDq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)
6510        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VANDq,
6511        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
6512        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
6513        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
6514        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6515        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6516        GIR_EraseFromParent, /*InsnID*/0,
6517        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6518        // GIR_Coverage, 2522,
6519        GIR_Done,
6520      // Label 361: @14947
6521      GIM_Try, /*On fail goto*//*Label 362*/ 15008, // Rule ID 3456 //
6522        GIM_CheckFeatures, GIFBS_HasMVEInt,
6523        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
6524        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
6525        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
6526        // (and:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VAND:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
6527        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6528        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
6529        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
6530        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VAND,
6531        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
6532        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
6533        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
6534        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
6535        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6536        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6537        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
6538        GIR_EraseFromParent, /*InsnID*/0,
6539        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6540        // GIR_Coverage, 3456,
6541        GIR_Done,
6542      // Label 362: @15008
6543      GIM_Reject,
6544    // Label 360: @15009
6545    GIM_Reject,
6546    // Label 315: @15010
6547    GIM_Try, /*On fail goto*//*Label 363*/ 15115, // Rule ID 1849 //
6548      GIM_CheckFeatures, GIFBS_HasMVEInt,
6549      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1,
6550      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1,
6551      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
6552      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
6553      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
6554      // (and:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
6555      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6556      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
6557      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
6558      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
6559      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
6560      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
6561      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
6562      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
6563      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
6564      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
6565      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
6566      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ANDrr,
6567      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
6568      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
6569      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
6570      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
6571      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6572      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6573      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6574      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6575      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
6576      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
6577      GIR_EraseFromParent, /*InsnID*/0,
6578      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::VCCRRegClassID,
6579      // GIR_Coverage, 1849,
6580      GIR_Done,
6581    // Label 363: @15115
6582    GIM_Reject,
6583    // Label 316: @15116
6584    GIM_Try, /*On fail goto*//*Label 364*/ 15231,
6585      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
6586      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6587      GIM_Try, /*On fail goto*//*Label 365*/ 15169, // Rule ID 2521 //
6588        GIM_CheckFeatures, GIFBS_HasNEON,
6589        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
6590        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
6591        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
6592        // (and:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)  =>  (VANDq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)
6593        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VANDq,
6594        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
6595        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
6596        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
6597        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6598        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6599        GIR_EraseFromParent, /*InsnID*/0,
6600        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6601        // GIR_Coverage, 2521,
6602        GIR_Done,
6603      // Label 365: @15169
6604      GIM_Try, /*On fail goto*//*Label 366*/ 15230, // Rule ID 3452 //
6605        GIM_CheckFeatures, GIFBS_HasMVEInt,
6606        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
6607        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
6608        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
6609        // (and:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VAND:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
6610        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6611        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
6612        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
6613        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VAND,
6614        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
6615        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
6616        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
6617        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
6618        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6619        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6620        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
6621        GIR_EraseFromParent, /*InsnID*/0,
6622        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6623        // GIR_Coverage, 3452,
6624        GIR_Done,
6625      // Label 366: @15230
6626      GIM_Reject,
6627    // Label 364: @15231
6628    GIM_Reject,
6629    // Label 317: @15232
6630    GIM_Reject,
6631    // Label 6: @15233
6632    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 16, /*)*//*default:*//*Label 380*/ 20472,
6633    /*GILLT_s32*//*Label 367*/ 15254,
6634    /*GILLT_s64*//*Label 368*/ 19376,
6635    /*GILLT_v2s1*//*Label 369*/ 19428,
6636    /*GILLT_v2s32*//*Label 370*/ 19534,
6637    /*GILLT_v2s64*//*Label 371*/ 19586,
6638    /*GILLT_v4s1*//*Label 372*/ 19702,
6639    /*GILLT_v4s16*//*Label 373*/ 19808,
6640    /*GILLT_v4s32*//*Label 374*/ 19860, 0,
6641    /*GILLT_v8s1*//*Label 375*/ 19976,
6642    /*GILLT_v8s8*//*Label 376*/ 20082,
6643    /*GILLT_v8s16*//*Label 377*/ 20134, 0,
6644    /*GILLT_v16s1*//*Label 378*/ 20250,
6645    /*GILLT_v16s8*//*Label 379*/ 20356,
6646    // Label 367: @15254
6647    GIM_Try, /*On fail goto*//*Label 381*/ 19375,
6648      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
6649      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6650      GIM_Try, /*On fail goto*//*Label 382*/ 15384, // Rule ID 5755 //
6651        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6652        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
6653        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6654        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6655        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6656        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6657        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6658        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
6659        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6660        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6661        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRRegClassID,
6662        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 8,
6663        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
6664        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6665        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
6666        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6667        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6668        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6669        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_SHL,
6670        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6671        // MIs[4] Rm
6672        GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
6673        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 24,
6674        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
6675        GIM_CheckIsSafeToFold, /*InsnID*/1,
6676        GIM_CheckIsSafeToFold, /*InsnID*/2,
6677        GIM_CheckIsSafeToFold, /*InsnID*/3,
6678        GIM_CheckIsSafeToFold, /*InsnID*/4,
6679        // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }))  =>  (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
6680        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REVSH,
6681        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6682        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6683        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6684        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6685        GIR_EraseFromParent, /*InsnID*/0,
6686        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6687        // GIR_Coverage, 5755,
6688        GIR_Done,
6689      // Label 382: @15384
6690      GIM_Try, /*On fail goto*//*Label 383*/ 15504, // Rule ID 5797 //
6691        GIM_CheckFeatures, GIFBS_IsThumb2,
6692        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6693        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6694        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6695        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6696        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6697        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6698        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
6699        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6700        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6701        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6702        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 8,
6703        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
6704        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6705        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
6706        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6707        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6708        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6709        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_SHL,
6710        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6711        // MIs[4] Rm
6712        GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
6713        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 24,
6714        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
6715        GIM_CheckIsSafeToFold, /*InsnID*/1,
6716        GIM_CheckIsSafeToFold, /*InsnID*/2,
6717        GIM_CheckIsSafeToFold, /*InsnID*/3,
6718        GIM_CheckIsSafeToFold, /*InsnID*/4,
6719        // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }))  =>  (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
6720        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REVSH,
6721        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6722        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6723        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6724        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6725        GIR_EraseFromParent, /*InsnID*/0,
6726        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6727        // GIR_Coverage, 5797,
6728        GIR_Done,
6729      // Label 383: @15504
6730      GIM_Try, /*On fail goto*//*Label 384*/ 15624, // Rule ID 1941 //
6731        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6732        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
6733        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6734        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
6735        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6736        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6737        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6738        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
6739        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6740        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6741        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRRegClassID,
6742        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 24,
6743        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16,
6744        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6745        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
6746        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6747        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6748        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6749        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_LSHR,
6750        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6751        // MIs[4] Rm
6752        GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
6753        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 8,
6754        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 255,
6755        GIM_CheckIsSafeToFold, /*InsnID*/1,
6756        GIM_CheckIsSafeToFold, /*InsnID*/2,
6757        GIM_CheckIsSafeToFold, /*InsnID*/3,
6758        GIM_CheckIsSafeToFold, /*InsnID*/4,
6759        // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }))  =>  (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
6760        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REVSH,
6761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6762        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6763        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6764        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6765        GIR_EraseFromParent, /*InsnID*/0,
6766        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6767        // GIR_Coverage, 1941,
6768        GIR_Done,
6769      // Label 384: @15624
6770      GIM_Try, /*On fail goto*//*Label 385*/ 15744, // Rule ID 2207 //
6771        GIM_CheckFeatures, GIFBS_IsThumb2,
6772        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6773        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6774        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
6775        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6776        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6777        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6778        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
6779        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6780        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6781        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6782        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 24,
6783        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16,
6784        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6785        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
6786        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6787        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6788        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6789        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_LSHR,
6790        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6791        // MIs[4] Rm
6792        GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
6793        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 8,
6794        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 255,
6795        GIM_CheckIsSafeToFold, /*InsnID*/1,
6796        GIM_CheckIsSafeToFold, /*InsnID*/2,
6797        GIM_CheckIsSafeToFold, /*InsnID*/3,
6798        GIM_CheckIsSafeToFold, /*InsnID*/4,
6799        // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }))  =>  (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
6800        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REVSH,
6801        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6802        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6803        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6804        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6805        GIR_EraseFromParent, /*InsnID*/0,
6806        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6807        // GIR_Coverage, 2207,
6808        GIR_Done,
6809      // Label 385: @15744
6810      GIM_Try, /*On fail goto*//*Label 386*/ 15861, // Rule ID 5553 //
6811        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6812        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6813        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6814        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6815        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6816        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6817        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6818        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
6819        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6820        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6821        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6822        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6823        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
6824        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_pkh_asr_amt,
6825        // MIs[3] Operand 1
6826        // No operand predicates
6827        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
6828        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
6829        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
6830        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
6831        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6832        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6833        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 4294901760,
6834        GIM_CheckIsSafeToFold, /*InsnID*/1,
6835        GIM_CheckIsSafeToFold, /*InsnID*/2,
6836        GIM_CheckIsSafeToFold, /*InsnID*/3,
6837        GIM_CheckIsSafeToFold, /*InsnID*/4,
6838        // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
6839        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
6840        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6841        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
6842        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6843        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6844        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6845        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6846        GIR_EraseFromParent, /*InsnID*/0,
6847        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6848        // GIR_Coverage, 5553,
6849        GIR_Done,
6850      // Label 386: @15861
6851      GIM_Try, /*On fail goto*//*Label 387*/ 15978, // Rule ID 5590 //
6852        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6853        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6854        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6855        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6856        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6857        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6858        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6859        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
6860        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6861        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6862        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6863        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6864        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
6865        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_pkh_asr_amt,
6866        // MIs[3] Operand 1
6867        // No operand predicates
6868        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
6869        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
6870        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
6871        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
6872        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6873        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6874        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 4294901760,
6875        GIM_CheckIsSafeToFold, /*InsnID*/1,
6876        GIM_CheckIsSafeToFold, /*InsnID*/2,
6877        GIM_CheckIsSafeToFold, /*InsnID*/3,
6878        GIM_CheckIsSafeToFold, /*InsnID*/4,
6879        // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
6880        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
6881        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6882        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
6883        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6884        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6885        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6886        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6887        GIR_EraseFromParent, /*InsnID*/0,
6888        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6889        // GIR_Coverage, 5590,
6890        GIR_Done,
6891      // Label 387: @15978
6892      GIM_Try, /*On fail goto*//*Label 388*/ 16095, // Rule ID 5760 //
6893        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6894        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6895        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6896        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6897        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6898        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6899        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6900        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
6901        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6902        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6903        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6904        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6905        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
6906        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm1_15,
6907        // MIs[3] Operand 1
6908        // No operand predicates
6909        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
6910        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
6911        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
6912        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
6913        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6914        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6915        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 4294901760,
6916        GIM_CheckIsSafeToFold, /*InsnID*/1,
6917        GIM_CheckIsSafeToFold, /*InsnID*/2,
6918        GIM_CheckIsSafeToFold, /*InsnID*/3,
6919        GIM_CheckIsSafeToFold, /*InsnID*/4,
6920        // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
6921        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
6922        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6923        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
6924        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
6925        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6926        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6927        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6928        GIR_EraseFromParent, /*InsnID*/0,
6929        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6930        // GIR_Coverage, 5760,
6931        GIR_Done,
6932      // Label 388: @16095
6933      GIM_Try, /*On fail goto*//*Label 389*/ 16212, // Rule ID 5802 //
6934        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6935        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6936        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6937        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6938        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6939        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6940        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6941        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
6942        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6943        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6944        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6945        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6946        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
6947        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm1_15,
6948        // MIs[3] Operand 1
6949        // No operand predicates
6950        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
6951        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
6952        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
6953        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
6954        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6955        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6956        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 4294901760,
6957        GIM_CheckIsSafeToFold, /*InsnID*/1,
6958        GIM_CheckIsSafeToFold, /*InsnID*/2,
6959        GIM_CheckIsSafeToFold, /*InsnID*/3,
6960        GIM_CheckIsSafeToFold, /*InsnID*/4,
6961        // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
6962        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
6963        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6964        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
6965        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
6966        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6967        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6968        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6969        GIR_EraseFromParent, /*InsnID*/0,
6970        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6971        // GIR_Coverage, 5802,
6972        GIR_Done,
6973      // Label 389: @16212
6974      GIM_Try, /*On fail goto*//*Label 390*/ 16329, // Rule ID 5552 //
6975        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6976        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6977        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6978        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6979        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6980        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6981        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6982        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
6983        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6984        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6985        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6986        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6987        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
6988        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_pkh_lsl_amt,
6989        // MIs[3] Operand 1
6990        // No operand predicates
6991        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
6992        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
6993        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
6994        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
6995        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6996        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6997        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 65535,
6998        GIM_CheckIsSafeToFold, /*InsnID*/1,
6999        GIM_CheckIsSafeToFold, /*InsnID*/2,
7000        GIM_CheckIsSafeToFold, /*InsnID*/3,
7001        GIM_CheckIsSafeToFold, /*InsnID*/4,
7002        // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7003        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
7004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7005        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
7006        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7007        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7008        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7009        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7010        GIR_EraseFromParent, /*InsnID*/0,
7011        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7012        // GIR_Coverage, 5552,
7013        GIR_Done,
7014      // Label 390: @16329
7015      GIM_Try, /*On fail goto*//*Label 391*/ 16446, // Rule ID 5589 //
7016        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
7017        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7018        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7019        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7020        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7021        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7022        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7023        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
7024        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7025        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7026        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7027        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7028        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
7029        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_pkh_lsl_amt,
7030        // MIs[3] Operand 1
7031        // No operand predicates
7032        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
7033        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
7034        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
7035        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
7036        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7037        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7038        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 65535,
7039        GIM_CheckIsSafeToFold, /*InsnID*/1,
7040        GIM_CheckIsSafeToFold, /*InsnID*/2,
7041        GIM_CheckIsSafeToFold, /*InsnID*/3,
7042        GIM_CheckIsSafeToFold, /*InsnID*/4,
7043        // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] }))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7044        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
7045        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7046        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
7047        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7048        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7049        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7050        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7051        GIR_EraseFromParent, /*InsnID*/0,
7052        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7053        // GIR_Coverage, 5589,
7054        GIR_Done,
7055      // Label 391: @16446
7056      GIM_Try, /*On fail goto*//*Label 392*/ 16563, // Rule ID 203 //
7057        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
7058        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
7059        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7060        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7061        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7062        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7063        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7064        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
7065        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7066        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
7067        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7068        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7069        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
7070        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
7071        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7072        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7073        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7074        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
7075        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
7076        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_pkh_asr_amt,
7077        // MIs[4] Operand 1
7078        // No operand predicates
7079        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
7080        GIM_CheckIsSafeToFold, /*InsnID*/1,
7081        GIM_CheckIsSafeToFold, /*InsnID*/2,
7082        GIM_CheckIsSafeToFold, /*InsnID*/3,
7083        GIM_CheckIsSafeToFold, /*InsnID*/4,
7084        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7085        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
7086        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7087        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7088        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
7089        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
7090        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7091        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7092        GIR_EraseFromParent, /*InsnID*/0,
7093        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7094        // GIR_Coverage, 203,
7095        GIR_Done,
7096      // Label 392: @16563
7097      GIM_Try, /*On fail goto*//*Label 393*/ 16680, // Rule ID 547 //
7098        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
7099        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7100        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7101        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7102        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7103        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7104        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7105        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
7106        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7107        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
7108        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7109        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7110        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
7111        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
7112        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7113        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7114        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7115        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
7116        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
7117        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_pkh_asr_amt,
7118        // MIs[4] Operand 1
7119        // No operand predicates
7120        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
7121        GIM_CheckIsSafeToFold, /*InsnID*/1,
7122        GIM_CheckIsSafeToFold, /*InsnID*/2,
7123        GIM_CheckIsSafeToFold, /*InsnID*/3,
7124        GIM_CheckIsSafeToFold, /*InsnID*/4,
7125        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7126        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
7127        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7128        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7129        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
7130        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
7131        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7132        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7133        GIR_EraseFromParent, /*InsnID*/0,
7134        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7135        // GIR_Coverage, 547,
7136        GIR_Done,
7137      // Label 393: @16680
7138      GIM_Try, /*On fail goto*//*Label 394*/ 16797, // Rule ID 1946 //
7139        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
7140        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
7141        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7142        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7143        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7144        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7145        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7146        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
7147        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7148        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
7149        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7150        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7151        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
7152        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_LSHR,
7153        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7154        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7155        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7156        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
7157        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
7158        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_imm1_15,
7159        // MIs[4] Operand 1
7160        // No operand predicates
7161        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
7162        GIM_CheckIsSafeToFold, /*InsnID*/1,
7163        GIM_CheckIsSafeToFold, /*InsnID*/2,
7164        GIM_CheckIsSafeToFold, /*InsnID*/3,
7165        GIM_CheckIsSafeToFold, /*InsnID*/4,
7166        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
7167        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
7168        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7169        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7170        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2
7171        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
7172        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7173        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7174        GIR_EraseFromParent, /*InsnID*/0,
7175        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7176        // GIR_Coverage, 1946,
7177        GIR_Done,
7178      // Label 394: @16797
7179      GIM_Try, /*On fail goto*//*Label 395*/ 16914, // Rule ID 2212 //
7180        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
7181        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7182        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7183        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7184        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7185        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7186        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7187        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
7188        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7189        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
7190        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7191        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7192        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
7193        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_LSHR,
7194        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7195        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7196        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7197        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
7198        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
7199        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_imm1_15,
7200        // MIs[4] Operand 1
7201        // No operand predicates
7202        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
7203        GIM_CheckIsSafeToFold, /*InsnID*/1,
7204        GIM_CheckIsSafeToFold, /*InsnID*/2,
7205        GIM_CheckIsSafeToFold, /*InsnID*/3,
7206        GIM_CheckIsSafeToFold, /*InsnID*/4,
7207        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
7208        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
7209        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2
7212        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
7213        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7214        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7215        GIR_EraseFromParent, /*InsnID*/0,
7216        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7217        // GIR_Coverage, 2212,
7218        GIR_Done,
7219      // Label 395: @16914
7220      GIM_Try, /*On fail goto*//*Label 396*/ 17031, // Rule ID 202 //
7221        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
7222        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
7223        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7224        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7225        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7226        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7227        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7228        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
7229        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7230        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
7231        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7232        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7233        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
7234        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SHL,
7235        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7236        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7237        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7238        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
7239        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
7240        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_pkh_lsl_amt,
7241        // MIs[4] Operand 1
7242        // No operand predicates
7243        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 4294901760,
7244        GIM_CheckIsSafeToFold, /*InsnID*/1,
7245        GIM_CheckIsSafeToFold, /*InsnID*/2,
7246        GIM_CheckIsSafeToFold, /*InsnID*/3,
7247        GIM_CheckIsSafeToFold, /*InsnID*/4,
7248        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7249        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
7250        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7251        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7252        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
7253        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
7254        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7255        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7256        GIR_EraseFromParent, /*InsnID*/0,
7257        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7258        // GIR_Coverage, 202,
7259        GIR_Done,
7260      // Label 396: @17031
7261      GIM_Try, /*On fail goto*//*Label 397*/ 17148, // Rule ID 546 //
7262        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
7263        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7264        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7265        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7266        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7267        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7268        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7269        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
7270        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7271        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
7272        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7273        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7274        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
7275        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SHL,
7276        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7277        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7278        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7279        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
7280        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
7281        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_pkh_lsl_amt,
7282        // MIs[4] Operand 1
7283        // No operand predicates
7284        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 4294901760,
7285        GIM_CheckIsSafeToFold, /*InsnID*/1,
7286        GIM_CheckIsSafeToFold, /*InsnID*/2,
7287        GIM_CheckIsSafeToFold, /*InsnID*/3,
7288        GIM_CheckIsSafeToFold, /*InsnID*/4,
7289        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7290        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
7291        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7292        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7293        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
7294        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
7295        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7296        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7297        GIR_EraseFromParent, /*InsnID*/0,
7298        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7299        // GIR_Coverage, 546,
7300        GIR_Done,
7301      // Label 397: @17148
7302      GIM_Try, /*On fail goto*//*Label 398*/ 17236, // Rule ID 1942 //
7303        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
7304        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
7305        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7306        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7307        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7308        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7309        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7310        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
7311        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7312        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
7313        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7314        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7315        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7316        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 4294901760,
7317        GIM_CheckIsSafeToFold, /*InsnID*/1,
7318        GIM_CheckIsSafeToFold, /*InsnID*/2,
7319        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] }))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
7320        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
7321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7323        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7324        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
7325        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7326        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7327        GIR_EraseFromParent, /*InsnID*/0,
7328        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7329        // GIR_Coverage, 1942,
7330        GIR_Done,
7331      // Label 398: @17236
7332      GIM_Try, /*On fail goto*//*Label 399*/ 17324, // Rule ID 2208 //
7333        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
7334        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7335        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7336        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7337        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7338        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7339        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7340        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
7341        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7342        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
7343        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7344        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7345        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7346        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 4294901760,
7347        GIM_CheckIsSafeToFold, /*InsnID*/1,
7348        GIM_CheckIsSafeToFold, /*InsnID*/2,
7349        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] }))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] })
7350        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
7351        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7352        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7353        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
7354        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
7355        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7356        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7357        GIR_EraseFromParent, /*InsnID*/0,
7358        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7359        // GIR_Coverage, 2208,
7360        GIR_Done,
7361      // Label 399: @17324
7362      GIM_Try, /*On fail goto*//*Label 400*/ 17412, // Rule ID 5756 //
7363        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
7364        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
7365        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7366        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7367        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7368        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7369        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7370        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
7371        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7372        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
7373        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7374        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7375        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7376        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
7377        GIM_CheckIsSafeToFold, /*InsnID*/1,
7378        GIM_CheckIsSafeToFold, /*InsnID*/2,
7379        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
7380        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
7381        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7382        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
7383        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7384        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
7385        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7386        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7387        GIR_EraseFromParent, /*InsnID*/0,
7388        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7389        // GIR_Coverage, 5756,
7390        GIR_Done,
7391      // Label 400: @17412
7392      GIM_Try, /*On fail goto*//*Label 401*/ 17500, // Rule ID 5798 //
7393        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
7394        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7395        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7396        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7397        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7398        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7399        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7400        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
7401        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7402        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
7403        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7404        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7405        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7406        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
7407        GIM_CheckIsSafeToFold, /*InsnID*/1,
7408        GIM_CheckIsSafeToFold, /*InsnID*/2,
7409        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] })
7410        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
7411        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7412        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
7413        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
7414        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
7415        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7416        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7417        GIR_EraseFromParent, /*InsnID*/0,
7418        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7419        // GIR_Coverage, 5798,
7420        GIR_Done,
7421      // Label 401: @17500
7422      GIM_Try, /*On fail goto*//*Label 402*/ 17596, // Rule ID 1945 //
7423        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
7424        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
7425        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7426        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7427        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7428        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7429        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7430        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
7431        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7432        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
7433        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7434        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7435        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7436        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7437        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
7438        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
7439        // MIs[3] Operand 1
7440        // No operand predicates
7441        GIM_CheckIsSafeToFold, /*InsnID*/1,
7442        GIM_CheckIsSafeToFold, /*InsnID*/2,
7443        GIM_CheckIsSafeToFold, /*InsnID*/3,
7444        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7445        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
7446        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7447        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7448        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
7449        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7450        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7451        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7452        GIR_EraseFromParent, /*InsnID*/0,
7453        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7454        // GIR_Coverage, 1945,
7455        GIR_Done,
7456      // Label 402: @17596
7457      GIM_Try, /*On fail goto*//*Label 403*/ 17692, // Rule ID 2211 //
7458        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
7459        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7460        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7461        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7462        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7463        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7464        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7465        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
7466        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7467        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
7468        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7469        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7470        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7471        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7472        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
7473        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
7474        // MIs[3] Operand 1
7475        // No operand predicates
7476        GIM_CheckIsSafeToFold, /*InsnID*/1,
7477        GIM_CheckIsSafeToFold, /*InsnID*/2,
7478        GIM_CheckIsSafeToFold, /*InsnID*/3,
7479        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7480        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
7481        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7482        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7483        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
7484        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7485        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7486        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7487        GIR_EraseFromParent, /*InsnID*/0,
7488        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7489        // GIR_Coverage, 2211,
7490        GIR_Done,
7491      // Label 403: @17692
7492      GIM_Try, /*On fail goto*//*Label 404*/ 17788, // Rule ID 1944 //
7493        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
7494        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
7495        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7496        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7497        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7498        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7499        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7500        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
7501        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7502        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
7503        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7504        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7505        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7506        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7507        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
7508        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16,
7509        // MIs[3] Operand 1
7510        // No operand predicates
7511        GIM_CheckIsSafeToFold, /*InsnID*/1,
7512        GIM_CheckIsSafeToFold, /*InsnID*/2,
7513        GIM_CheckIsSafeToFold, /*InsnID*/3,
7514        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
7515        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
7516        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7517        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7518        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
7519        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7520        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7521        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7522        GIR_EraseFromParent, /*InsnID*/0,
7523        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7524        // GIR_Coverage, 1944,
7525        GIR_Done,
7526      // Label 404: @17788
7527      GIM_Try, /*On fail goto*//*Label 405*/ 17884, // Rule ID 2210 //
7528        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
7529        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7530        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7531        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7532        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7533        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7534        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7535        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
7536        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7537        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
7538        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7539        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7540        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7541        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7542        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
7543        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16,
7544        // MIs[3] Operand 1
7545        // No operand predicates
7546        GIM_CheckIsSafeToFold, /*InsnID*/1,
7547        GIM_CheckIsSafeToFold, /*InsnID*/2,
7548        GIM_CheckIsSafeToFold, /*InsnID*/3,
7549        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
7550        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
7551        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7552        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7553        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
7554        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7555        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7556        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7557        GIR_EraseFromParent, /*InsnID*/0,
7558        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7559        // GIR_Coverage, 2210,
7560        GIR_Done,
7561      // Label 405: @17884
7562      GIM_Try, /*On fail goto*//*Label 406*/ 17980, // Rule ID 1943 //
7563        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
7564        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
7565        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7566        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7567        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7568        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7569        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7570        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
7571        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7572        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
7573        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7574        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7575        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7576        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7577        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
7578        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
7579        // MIs[3] Operand 1
7580        // No operand predicates
7581        GIM_CheckIsSafeToFold, /*InsnID*/1,
7582        GIM_CheckIsSafeToFold, /*InsnID*/2,
7583        GIM_CheckIsSafeToFold, /*InsnID*/3,
7584        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7585        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
7586        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7587        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7588        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7589        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7590        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7591        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7592        GIR_EraseFromParent, /*InsnID*/0,
7593        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7594        // GIR_Coverage, 1943,
7595        GIR_Done,
7596      // Label 406: @17980
7597      GIM_Try, /*On fail goto*//*Label 407*/ 18076, // Rule ID 2209 //
7598        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
7599        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7600        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7601        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7602        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7603        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7604        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7605        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
7606        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7607        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
7608        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7609        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7610        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7611        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7612        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
7613        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
7614        // MIs[3] Operand 1
7615        // No operand predicates
7616        GIM_CheckIsSafeToFold, /*InsnID*/1,
7617        GIM_CheckIsSafeToFold, /*InsnID*/2,
7618        GIM_CheckIsSafeToFold, /*InsnID*/3,
7619        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7620        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
7621        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7622        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7623        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
7624        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7625        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7626        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7627        GIR_EraseFromParent, /*InsnID*/0,
7628        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7629        // GIR_Coverage, 2209,
7630        GIR_Done,
7631      // Label 407: @18076
7632      GIM_Try, /*On fail goto*//*Label 408*/ 18172, // Rule ID 5759 //
7633        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
7634        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
7635        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7636        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
7637        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7638        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7639        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7640        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7641        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
7642        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
7643        // MIs[2] Operand 1
7644        // No operand predicates
7645        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7646        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
7647        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7648        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7649        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7650        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 4294901760,
7651        GIM_CheckIsSafeToFold, /*InsnID*/1,
7652        GIM_CheckIsSafeToFold, /*InsnID*/2,
7653        GIM_CheckIsSafeToFold, /*InsnID*/3,
7654        // (or:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7655        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
7656        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7657        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
7658        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
7659        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
7660        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7661        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7662        GIR_EraseFromParent, /*InsnID*/0,
7663        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7664        // GIR_Coverage, 5759,
7665        GIR_Done,
7666      // Label 408: @18172
7667      GIM_Try, /*On fail goto*//*Label 409*/ 18268, // Rule ID 5801 //
7668        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
7669        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7670        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7671        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
7672        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7673        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7674        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7675        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7676        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
7677        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
7678        // MIs[2] Operand 1
7679        // No operand predicates
7680        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7681        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
7682        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7683        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7684        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7685        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 4294901760,
7686        GIM_CheckIsSafeToFold, /*InsnID*/1,
7687        GIM_CheckIsSafeToFold, /*InsnID*/2,
7688        GIM_CheckIsSafeToFold, /*InsnID*/3,
7689        // (or:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7690        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
7691        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7692        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
7693        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
7694        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
7695        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7696        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7697        GIR_EraseFromParent, /*InsnID*/0,
7698        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7699        // GIR_Coverage, 5801,
7700        GIR_Done,
7701      // Label 409: @18268
7702      GIM_Try, /*On fail goto*//*Label 410*/ 18364, // Rule ID 5758 //
7703        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
7704        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
7705        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7706        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
7707        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7708        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7709        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7710        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7711        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
7712        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16,
7713        // MIs[2] Operand 1
7714        // No operand predicates
7715        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7716        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
7717        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7718        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7719        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7720        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 4294901760,
7721        GIM_CheckIsSafeToFold, /*InsnID*/1,
7722        GIM_CheckIsSafeToFold, /*InsnID*/2,
7723        GIM_CheckIsSafeToFold, /*InsnID*/3,
7724        // (or:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
7725        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
7726        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7727        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
7728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
7729        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
7730        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7731        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7732        GIR_EraseFromParent, /*InsnID*/0,
7733        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7734        // GIR_Coverage, 5758,
7735        GIR_Done,
7736      // Label 410: @18364
7737      GIM_Try, /*On fail goto*//*Label 411*/ 18460, // Rule ID 5800 //
7738        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
7739        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7740        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7741        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
7742        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7743        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7744        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7745        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7746        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
7747        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16,
7748        // MIs[2] Operand 1
7749        // No operand predicates
7750        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7751        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
7752        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7753        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7754        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7755        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 4294901760,
7756        GIM_CheckIsSafeToFold, /*InsnID*/1,
7757        GIM_CheckIsSafeToFold, /*InsnID*/2,
7758        GIM_CheckIsSafeToFold, /*InsnID*/3,
7759        // (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
7760        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
7761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7762        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
7763        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
7764        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
7765        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7766        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7767        GIR_EraseFromParent, /*InsnID*/0,
7768        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7769        // GIR_Coverage, 5800,
7770        GIR_Done,
7771      // Label 411: @18460
7772      GIM_Try, /*On fail goto*//*Label 412*/ 18556, // Rule ID 5757 //
7773        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
7774        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
7775        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7776        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
7777        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7778        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7779        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7780        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7781        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
7782        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
7783        // MIs[2] Operand 1
7784        // No operand predicates
7785        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7786        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
7787        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7788        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7789        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7790        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 65535,
7791        GIM_CheckIsSafeToFold, /*InsnID*/1,
7792        GIM_CheckIsSafeToFold, /*InsnID*/2,
7793        GIM_CheckIsSafeToFold, /*InsnID*/3,
7794        // (or:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7795        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
7796        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7797        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
7798        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7799        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
7800        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7801        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7802        GIR_EraseFromParent, /*InsnID*/0,
7803        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7804        // GIR_Coverage, 5757,
7805        GIR_Done,
7806      // Label 412: @18556
7807      GIM_Try, /*On fail goto*//*Label 413*/ 18652, // Rule ID 5799 //
7808        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
7809        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7810        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7811        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
7812        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7813        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7814        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7815        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7816        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
7817        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
7818        // MIs[2] Operand 1
7819        // No operand predicates
7820        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7821        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
7822        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7823        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7824        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7825        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 65535,
7826        GIM_CheckIsSafeToFold, /*InsnID*/1,
7827        GIM_CheckIsSafeToFold, /*InsnID*/2,
7828        GIM_CheckIsSafeToFold, /*InsnID*/3,
7829        // (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7830        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
7831        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7832        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
7833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
7834        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
7835        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7836        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7837        GIR_EraseFromParent, /*InsnID*/0,
7838        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7839        // GIR_Coverage, 5799,
7840        GIR_Done,
7841      // Label 413: @18652
7842      GIM_Try, /*On fail goto*//*Label 414*/ 18727, // Rule ID 5577 //
7843        GIM_CheckFeatures, GIFBS_IsThumb2,
7844        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7845        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7846        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
7847        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7848        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7849        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
7850        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7851        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
7852        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
7853        // MIs[2] Operand 1
7854        // No operand predicates
7855        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
7856        GIM_CheckIsSafeToFold, /*InsnID*/1,
7857        GIM_CheckIsSafeToFold, /*InsnID*/2,
7858        // (or:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn)  =>  (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7859        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri,
7860        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7861        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
7862        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
7863        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7864        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7865        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7866        GIR_EraseFromParent, /*InsnID*/0,
7867        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7868        // GIR_Coverage, 5577,
7869        GIR_Done,
7870      // Label 414: @18727
7871      GIM_Try, /*On fail goto*//*Label 415*/ 18802, // Rule ID 5576 //
7872        GIM_CheckFeatures, GIFBS_IsThumb2,
7873        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7874        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7875        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
7876        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7877        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7878        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7879        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
7880        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
7881        // MIs[2] Operand 1
7882        // No operand predicates
7883        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
7884        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
7885        GIM_CheckIsSafeToFold, /*InsnID*/1,
7886        GIM_CheckIsSafeToFold, /*InsnID*/2,
7887        // (or:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7888        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri,
7889        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7890        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
7891        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
7892        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7893        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7894        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7895        GIR_EraseFromParent, /*InsnID*/0,
7896        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7897        // GIR_Coverage, 5576,
7898        GIR_Done,
7899      // Label 415: @18802
7900      GIM_Try, /*On fail goto*//*Label 416*/ 18877, // Rule ID 5575 //
7901        GIM_CheckFeatures, GIFBS_IsThumb2,
7902        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7903        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7904        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7905        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
7906        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7907        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7908        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
7909        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7910        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
7911        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
7912        // MIs[2] Operand 1
7913        // No operand predicates
7914        GIM_CheckIsSafeToFold, /*InsnID*/1,
7915        GIM_CheckIsSafeToFold, /*InsnID*/2,
7916        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm))  =>  (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7917        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri,
7918        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7919        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7920        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
7921        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7922        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7923        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7924        GIR_EraseFromParent, /*InsnID*/0,
7925        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7926        // GIR_Coverage, 5575,
7927        GIR_Done,
7928      // Label 416: @18877
7929      GIM_Try, /*On fail goto*//*Label 417*/ 18952, // Rule ID 503 //
7930        GIM_CheckFeatures, GIFBS_IsThumb2,
7931        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7932        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7933        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7934        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
7935        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7936        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7937        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7938        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
7939        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
7940        // MIs[2] Operand 1
7941        // No operand predicates
7942        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
7943        GIM_CheckIsSafeToFold, /*InsnID*/1,
7944        GIM_CheckIsSafeToFold, /*InsnID*/2,
7945        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }))  =>  (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7946        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri,
7947        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7948        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7949        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
7950        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7951        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7952        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7953        GIR_EraseFromParent, /*InsnID*/0,
7954        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7955        // GIR_Coverage, 503,
7956        GIR_Done,
7957      // Label 417: @18952
7958      GIM_Try, /*On fail goto*//*Label 418*/ 19020, // Rule ID 5578 //
7959        GIM_CheckFeatures, GIFBS_IsThumb2,
7960        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7961        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7962        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
7963        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7964        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7965        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7966        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
7967        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
7968        GIM_CheckIsSafeToFold, /*InsnID*/1,
7969        // (or:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
7970        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNrr,
7971        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7972        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
7973        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7974        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7975        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7976        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7977        GIR_EraseFromParent, /*InsnID*/0,
7978        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7979        // GIR_Coverage, 5578,
7980        GIR_Done,
7981      // Label 418: @19020
7982      GIM_Try, /*On fail goto*//*Label 419*/ 19088, // Rule ID 504 //
7983        GIM_CheckFeatures, GIFBS_IsThumb2,
7984        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7985        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7986        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7987        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
7988        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7989        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7990        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7991        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
7992        GIM_CheckIsSafeToFold, /*InsnID*/1,
7993        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }))  =>  (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
7994        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNrr,
7995        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7996        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7997        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7998        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7999        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8000        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8001        GIR_EraseFromParent, /*InsnID*/0,
8002        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8003        // GIR_Coverage, 504,
8004        GIR_Done,
8005      // Label 419: @19088
8006      GIM_Try, /*On fail goto*//*Label 420*/ 19130, // Rule ID 1871 //
8007        GIM_CheckFeatures, GIFBS_HasV6T2_IsARM,
8008        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
8009        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
8010        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294901760,
8011        // (or:{ *:[i32] } GPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] })  =>  (MOVTi16:{ *:[i32] } GPR:{ *:[i32] }:$src, 65535:{ *:[i32] })
8012        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVTi16,
8013        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8014        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8015        GIR_AddImm, /*InsnID*/0, /*Imm*/65535,
8016        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8017        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8018        GIR_EraseFromParent, /*InsnID*/0,
8019        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8020        // GIR_Coverage, 1871,
8021        GIR_Done,
8022      // Label 420: @19130
8023      GIM_Try, /*On fail goto*//*Label 421*/ 19172, // Rule ID 2102 //
8024        GIM_CheckFeatures, GIFBS_IsThumb2,
8025        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
8026        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
8027        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294901760,
8028        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] })  =>  (t2MOVTi16:{ *:[i32] } rGPR:{ *:[i32] }:$src, 65535:{ *:[i32] })
8029        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVTi16,
8030        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8031        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8032        GIR_AddImm, /*InsnID*/0, /*Imm*/65535,
8033        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8034        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8035        GIR_EraseFromParent, /*InsnID*/0,
8036        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8037        // GIR_Coverage, 2102,
8038        GIR_Done,
8039      // Label 421: @19172
8040      GIM_Try, /*On fail goto*//*Label 422*/ 19226, // Rule ID 151 //
8041        GIM_CheckFeatures, GIFBS_IsARM,
8042        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
8043        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
8044        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8045        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
8046        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
8047        // MIs[1] Operand 1
8048        // No operand predicates
8049        GIM_CheckIsSafeToFold, /*InsnID*/1,
8050        // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (ORRri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8051        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ORRri,
8052        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8053        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
8054        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
8055        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8056        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8057        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8058        GIR_EraseFromParent, /*InsnID*/0,
8059        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8060        // GIR_Coverage, 151,
8061        GIR_Done,
8062      // Label 422: @19226
8063      GIM_Try, /*On fail goto*//*Label 423*/ 19280, // Rule ID 491 //
8064        GIM_CheckFeatures, GIFBS_IsThumb2,
8065        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
8066        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
8067        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8068        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
8069        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
8070        // MIs[1] Operand 1
8071        // No operand predicates
8072        GIM_CheckIsSafeToFold, /*InsnID*/1,
8073        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2ORRri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8074        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORRri,
8075        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8076        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
8077        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
8078        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8079        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8080        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8081        GIR_EraseFromParent, /*InsnID*/0,
8082        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8083        // GIR_Coverage, 491,
8084        GIR_Done,
8085      // Label 423: @19280
8086      GIM_Try, /*On fail goto*//*Label 424*/ 19327, // Rule ID 152 //
8087        GIM_CheckFeatures, GIFBS_IsARM,
8088        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
8089        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
8090        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
8091        // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (ORRrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
8092        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ORRrr,
8093        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8094        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
8095        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
8096        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8097        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8098        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8099        GIR_EraseFromParent, /*InsnID*/0,
8100        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8101        // GIR_Coverage, 152,
8102        GIR_Done,
8103      // Label 424: @19327
8104      GIM_Try, /*On fail goto*//*Label 425*/ 19374, // Rule ID 492 //
8105        GIM_CheckFeatures, GIFBS_IsThumb2,
8106        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
8107        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
8108        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
8109        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2ORRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
8110        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORRrr,
8111        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8112        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
8113        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
8114        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8115        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8116        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8117        GIR_EraseFromParent, /*InsnID*/0,
8118        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8119        // GIR_Coverage, 492,
8120        GIR_Done,
8121      // Label 425: @19374
8122      GIM_Reject,
8123    // Label 381: @19375
8124    GIM_Reject,
8125    // Label 368: @19376
8126    GIM_Try, /*On fail goto*//*Label 426*/ 19427, // Rule ID 2526 //
8127      GIM_CheckFeatures, GIFBS_HasNEON,
8128      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
8129      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
8130      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8131      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8132      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8133      // (or:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)  =>  (VORRd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)
8134      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VORRd,
8135      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8136      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
8137      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
8138      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8139      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8140      GIR_EraseFromParent, /*InsnID*/0,
8141      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8142      // GIR_Coverage, 2526,
8143      GIR_Done,
8144    // Label 426: @19427
8145    GIM_Reject,
8146    // Label 369: @19428
8147    GIM_Try, /*On fail goto*//*Label 427*/ 19533, // Rule ID 1858 //
8148      GIM_CheckFeatures, GIFBS_HasMVEInt,
8149      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s1,
8150      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s1,
8151      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
8152      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
8153      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
8154      // (or:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8155      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8156      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8157      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8158      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
8159      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
8160      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8161      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8162      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
8163      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
8164      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8165      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
8166      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ORRrr,
8167      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
8168      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
8169      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
8170      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
8171      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8172      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8173      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8174      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8175      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8176      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8177      GIR_EraseFromParent, /*InsnID*/0,
8178      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::VCCRRegClassID,
8179      // GIR_Coverage, 1858,
8180      GIR_Done,
8181    // Label 427: @19533
8182    GIM_Reject,
8183    // Label 370: @19534
8184    GIM_Try, /*On fail goto*//*Label 428*/ 19585, // Rule ID 1153 //
8185      GIM_CheckFeatures, GIFBS_HasNEON,
8186      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8187      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
8188      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8189      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8190      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8191      // (or:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VORRd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
8192      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VORRd,
8193      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8194      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
8195      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8196      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8197      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8198      GIR_EraseFromParent, /*InsnID*/0,
8199      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8200      // GIR_Coverage, 1153,
8201      GIR_Done,
8202    // Label 428: @19585
8203    GIM_Reject,
8204    // Label 371: @19586
8205    GIM_Try, /*On fail goto*//*Label 429*/ 19701,
8206      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
8207      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8208      GIM_Try, /*On fail goto*//*Label 430*/ 19639, // Rule ID 2529 //
8209        GIM_CheckFeatures, GIFBS_HasNEON,
8210        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8211        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8212        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
8213        // (or:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)  =>  (VORRq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)
8214        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VORRq,
8215        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8216        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
8217        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
8218        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8219        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8220        GIR_EraseFromParent, /*InsnID*/0,
8221        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8222        // GIR_Coverage, 2529,
8223        GIR_Done,
8224      // Label 430: @19639
8225      GIM_Try, /*On fail goto*//*Label 431*/ 19700, // Rule ID 3478 //
8226        GIM_CheckFeatures, GIFBS_HasMVEInt,
8227        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
8228        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
8229        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
8230        // (or:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)  =>  (MVE_VORR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
8231        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
8232        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8233        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
8234        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VORR,
8235        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
8236        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
8237        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
8238        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
8239        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8240        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8241        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8242        GIR_EraseFromParent, /*InsnID*/0,
8243        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8244        // GIR_Coverage, 3478,
8245        GIR_Done,
8246      // Label 431: @19700
8247      GIM_Reject,
8248    // Label 429: @19701
8249    GIM_Reject,
8250    // Label 372: @19702
8251    GIM_Try, /*On fail goto*//*Label 432*/ 19807, // Rule ID 1859 //
8252      GIM_CheckFeatures, GIFBS_HasMVEInt,
8253      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1,
8254      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1,
8255      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
8256      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
8257      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
8258      // (or:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8259      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8260      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8261      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8262      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
8263      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
8264      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8265      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8266      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
8267      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
8268      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8269      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
8270      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ORRrr,
8271      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
8272      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
8273      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
8274      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
8275      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8276      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8277      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8278      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8279      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8280      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8281      GIR_EraseFromParent, /*InsnID*/0,
8282      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::VCCRRegClassID,
8283      // GIR_Coverage, 1859,
8284      GIR_Done,
8285    // Label 432: @19807
8286    GIM_Reject,
8287    // Label 373: @19808
8288    GIM_Try, /*On fail goto*//*Label 433*/ 19859, // Rule ID 2525 //
8289      GIM_CheckFeatures, GIFBS_HasNEON,
8290      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8291      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
8292      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8293      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8294      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8295      // (or:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)  =>  (VORRd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)
8296      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VORRd,
8297      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8298      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
8299      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
8300      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8301      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8302      GIR_EraseFromParent, /*InsnID*/0,
8303      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8304      // GIR_Coverage, 2525,
8305      GIR_Done,
8306    // Label 433: @19859
8307    GIM_Reject,
8308    // Label 374: @19860
8309    GIM_Try, /*On fail goto*//*Label 434*/ 19975,
8310      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
8311      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8312      GIM_Try, /*On fail goto*//*Label 435*/ 19913, // Rule ID 1154 //
8313        GIM_CheckFeatures, GIFBS_HasNEON,
8314        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8315        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8316        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
8317        // (or:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VORRq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
8318        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VORRq,
8319        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
8321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8322        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8323        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8324        GIR_EraseFromParent, /*InsnID*/0,
8325        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8326        // GIR_Coverage, 1154,
8327        GIR_Done,
8328      // Label 435: @19913
8329      GIM_Try, /*On fail goto*//*Label 436*/ 19974, // Rule ID 3474 //
8330        GIM_CheckFeatures, GIFBS_HasMVEInt,
8331        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
8332        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
8333        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
8334        // (or:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VORR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
8335        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
8336        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8337        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
8338        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VORR,
8339        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
8340        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
8341        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
8342        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
8343        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8344        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8345        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8346        GIR_EraseFromParent, /*InsnID*/0,
8347        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8348        // GIR_Coverage, 3474,
8349        GIR_Done,
8350      // Label 436: @19974
8351      GIM_Reject,
8352    // Label 434: @19975
8353    GIM_Reject,
8354    // Label 375: @19976
8355    GIM_Try, /*On fail goto*//*Label 437*/ 20081, // Rule ID 1860 //
8356      GIM_CheckFeatures, GIFBS_HasMVEInt,
8357      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1,
8358      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1,
8359      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
8360      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
8361      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
8362      // (or:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8363      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8364      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8365      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8366      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
8367      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
8368      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8369      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8370      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
8371      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
8372      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8373      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
8374      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ORRrr,
8375      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
8376      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
8377      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
8378      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
8379      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8380      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8381      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8382      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8383      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8384      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8385      GIR_EraseFromParent, /*InsnID*/0,
8386      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::VCCRRegClassID,
8387      // GIR_Coverage, 1860,
8388      GIR_Done,
8389    // Label 437: @20081
8390    GIM_Reject,
8391    // Label 376: @20082
8392    GIM_Try, /*On fail goto*//*Label 438*/ 20133, // Rule ID 2524 //
8393      GIM_CheckFeatures, GIFBS_HasNEON,
8394      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
8395      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
8396      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8397      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8398      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8399      // (or:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)  =>  (VORRd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)
8400      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VORRd,
8401      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8402      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
8403      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
8404      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8405      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8406      GIR_EraseFromParent, /*InsnID*/0,
8407      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8408      // GIR_Coverage, 2524,
8409      GIR_Done,
8410    // Label 438: @20133
8411    GIM_Reject,
8412    // Label 377: @20134
8413    GIM_Try, /*On fail goto*//*Label 439*/ 20249,
8414      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
8415      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8416      GIM_Try, /*On fail goto*//*Label 440*/ 20187, // Rule ID 2528 //
8417        GIM_CheckFeatures, GIFBS_HasNEON,
8418        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8419        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8420        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
8421        // (or:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)  =>  (VORRq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)
8422        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VORRq,
8423        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8424        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
8425        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
8426        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8427        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8428        GIR_EraseFromParent, /*InsnID*/0,
8429        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8430        // GIR_Coverage, 2528,
8431        GIR_Done,
8432      // Label 440: @20187
8433      GIM_Try, /*On fail goto*//*Label 441*/ 20248, // Rule ID 3470 //
8434        GIM_CheckFeatures, GIFBS_HasMVEInt,
8435        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
8436        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
8437        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
8438        // (or:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VORR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
8439        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
8440        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8441        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
8442        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VORR,
8443        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
8444        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
8445        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
8446        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
8447        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8448        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8449        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8450        GIR_EraseFromParent, /*InsnID*/0,
8451        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8452        // GIR_Coverage, 3470,
8453        GIR_Done,
8454      // Label 441: @20248
8455      GIM_Reject,
8456    // Label 439: @20249
8457    GIM_Reject,
8458    // Label 378: @20250
8459    GIM_Try, /*On fail goto*//*Label 442*/ 20355, // Rule ID 1857 //
8460      GIM_CheckFeatures, GIFBS_HasMVEInt,
8461      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1,
8462      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1,
8463      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
8464      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
8465      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
8466      // (or:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8467      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8468      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8469      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8470      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
8471      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
8472      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8473      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8474      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
8475      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
8476      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8477      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
8478      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ORRrr,
8479      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
8480      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
8481      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
8482      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
8483      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8484      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8485      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8486      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8487      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8488      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8489      GIR_EraseFromParent, /*InsnID*/0,
8490      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::VCCRRegClassID,
8491      // GIR_Coverage, 1857,
8492      GIR_Done,
8493    // Label 442: @20355
8494    GIM_Reject,
8495    // Label 379: @20356
8496    GIM_Try, /*On fail goto*//*Label 443*/ 20471,
8497      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
8498      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8499      GIM_Try, /*On fail goto*//*Label 444*/ 20409, // Rule ID 2527 //
8500        GIM_CheckFeatures, GIFBS_HasNEON,
8501        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8502        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8503        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
8504        // (or:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)  =>  (VORRq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)
8505        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VORRq,
8506        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8507        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
8508        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
8509        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8510        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8511        GIR_EraseFromParent, /*InsnID*/0,
8512        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8513        // GIR_Coverage, 2527,
8514        GIR_Done,
8515      // Label 444: @20409
8516      GIM_Try, /*On fail goto*//*Label 445*/ 20470, // Rule ID 3466 //
8517        GIM_CheckFeatures, GIFBS_HasMVEInt,
8518        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
8519        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
8520        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
8521        // (or:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VORR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
8522        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
8523        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8524        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
8525        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VORR,
8526        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
8527        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
8528        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
8529        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
8530        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8531        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8532        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8533        GIR_EraseFromParent, /*InsnID*/0,
8534        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8535        // GIR_Coverage, 3466,
8536        GIR_Done,
8537      // Label 445: @20470
8538      GIM_Reject,
8539    // Label 443: @20471
8540    GIM_Reject,
8541    // Label 380: @20472
8542    GIM_Reject,
8543    // Label 7: @20473
8544    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 16, /*)*//*default:*//*Label 459*/ 21990,
8545    /*GILLT_s32*//*Label 446*/ 20494,
8546    /*GILLT_s64*//*Label 447*/ 20894,
8547    /*GILLT_v2s1*//*Label 448*/ 20946,
8548    /*GILLT_v2s32*//*Label 449*/ 21052,
8549    /*GILLT_v2s64*//*Label 450*/ 21104,
8550    /*GILLT_v4s1*//*Label 451*/ 21220,
8551    /*GILLT_v4s16*//*Label 452*/ 21326,
8552    /*GILLT_v4s32*//*Label 453*/ 21378, 0,
8553    /*GILLT_v8s1*//*Label 454*/ 21494,
8554    /*GILLT_v8s8*//*Label 455*/ 21600,
8555    /*GILLT_v8s16*//*Label 456*/ 21652, 0,
8556    /*GILLT_v16s1*//*Label 457*/ 21768,
8557    /*GILLT_v16s8*//*Label 458*/ 21874,
8558    // Label 446: @20494
8559    GIM_Try, /*On fail goto*//*Label 460*/ 20893,
8560      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
8561      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
8562      GIM_Try, /*On fail goto*//*Label 461*/ 20554, // Rule ID 5580 //
8563        GIM_CheckFeatures, GIFBS_IsThumb2,
8564        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
8565        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, -1,
8566        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8567        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
8568        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
8569        // MIs[1] Operand 1
8570        // No operand predicates
8571        GIM_CheckIsSafeToFold, /*InsnID*/1,
8572        // (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
8573        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MVNi,
8574        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8575        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
8576        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8577        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8578        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8579        GIR_EraseFromParent, /*InsnID*/0,
8580        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8581        // GIR_Coverage, 5580,
8582        GIR_Done,
8583      // Label 461: @20554
8584      GIM_Try, /*On fail goto*//*Label 462*/ 20604, // Rule ID 506 //
8585        GIM_CheckFeatures, GIFBS_IsThumb2,
8586        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
8587        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8588        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
8589        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
8590        // MIs[1] Operand 1
8591        // No operand predicates
8592        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
8593        GIM_CheckIsSafeToFold, /*InsnID*/1,
8594        // (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })  =>  (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
8595        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MVNi,
8596        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8597        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
8598        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8599        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8600        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8601        GIR_EraseFromParent, /*InsnID*/0,
8602        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8603        // GIR_Coverage, 506,
8604        GIR_Done,
8605      // Label 462: @20604
8606      GIM_Try, /*On fail goto*//*Label 463*/ 20647, // Rule ID 507 //
8607        GIM_CheckFeatures, GIFBS_IsThumb2,
8608        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
8609        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
8610        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
8611        // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })  =>  (t2MVNr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
8612        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MVNr,
8613        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8614        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
8615        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8616        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8617        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8618        GIR_EraseFromParent, /*InsnID*/0,
8619        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8620        // GIR_Coverage, 507,
8621        GIR_Done,
8622      // Label 463: @20647
8623      GIM_Try, /*On fail goto*//*Label 464*/ 20690, // Rule ID 165 //
8624        GIM_CheckFeatures, GIFBS_IsARM,
8625        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
8626        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
8627        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
8628        // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })  =>  (MVNr:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
8629        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVNr,
8630        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8631        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
8632        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8633        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8634        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8635        GIR_EraseFromParent, /*InsnID*/0,
8636        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8637        // GIR_Coverage, 165,
8638        GIR_Done,
8639      // Label 464: @20690
8640      GIM_Try, /*On fail goto*//*Label 465*/ 20744, // Rule ID 155 //
8641        GIM_CheckFeatures, GIFBS_IsARM,
8642        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
8643        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
8644        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8645        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
8646        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
8647        // MIs[1] Operand 1
8648        // No operand predicates
8649        GIM_CheckIsSafeToFold, /*InsnID*/1,
8650        // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (EORri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8651        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::EORri,
8652        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8653        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
8654        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
8655        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8656        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8657        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8658        GIR_EraseFromParent, /*InsnID*/0,
8659        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8660        // GIR_Coverage, 155,
8661        GIR_Done,
8662      // Label 465: @20744
8663      GIM_Try, /*On fail goto*//*Label 466*/ 20798, // Rule ID 494 //
8664        GIM_CheckFeatures, GIFBS_IsThumb2,
8665        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
8666        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
8667        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8668        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
8669        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
8670        // MIs[1] Operand 1
8671        // No operand predicates
8672        GIM_CheckIsSafeToFold, /*InsnID*/1,
8673        // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2EORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8674        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2EORri,
8675        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8676        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
8677        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
8678        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8679        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8680        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8681        GIR_EraseFromParent, /*InsnID*/0,
8682        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8683        // GIR_Coverage, 494,
8684        GIR_Done,
8685      // Label 466: @20798
8686      GIM_Try, /*On fail goto*//*Label 467*/ 20845, // Rule ID 156 //
8687        GIM_CheckFeatures, GIFBS_IsARM,
8688        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
8689        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
8690        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
8691        // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (EORrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
8692        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::EORrr,
8693        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8694        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
8695        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
8696        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8697        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8698        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8699        GIR_EraseFromParent, /*InsnID*/0,
8700        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8701        // GIR_Coverage, 156,
8702        GIR_Done,
8703      // Label 467: @20845
8704      GIM_Try, /*On fail goto*//*Label 468*/ 20892, // Rule ID 495 //
8705        GIM_CheckFeatures, GIFBS_IsThumb2,
8706        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
8707        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
8708        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
8709        // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2EORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
8710        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2EORrr,
8711        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8712        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
8713        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
8714        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8715        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8716        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8717        GIR_EraseFromParent, /*InsnID*/0,
8718        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8719        // GIR_Coverage, 495,
8720        GIR_Done,
8721      // Label 468: @20892
8722      GIM_Reject,
8723    // Label 460: @20893
8724    GIM_Reject,
8725    // Label 447: @20894
8726    GIM_Try, /*On fail goto*//*Label 469*/ 20945, // Rule ID 2532 //
8727      GIM_CheckFeatures, GIFBS_HasNEON,
8728      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
8729      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
8730      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8731      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8732      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8733      // (xor:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)  =>  (VEORd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)
8734      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VEORd,
8735      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8736      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
8737      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
8738      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8739      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8740      GIR_EraseFromParent, /*InsnID*/0,
8741      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8742      // GIR_Coverage, 2532,
8743      GIR_Done,
8744    // Label 469: @20945
8745    GIM_Reject,
8746    // Label 448: @20946
8747    GIM_Try, /*On fail goto*//*Label 470*/ 21051, // Rule ID 1854 //
8748      GIM_CheckFeatures, GIFBS_HasMVEInt,
8749      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s1,
8750      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s1,
8751      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
8752      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
8753      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
8754      // (xor:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v2i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8755      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8756      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8757      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8758      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
8759      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
8760      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8761      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8762      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
8763      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
8764      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8765      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
8766      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2EORrr,
8767      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
8768      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
8769      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
8770      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
8771      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8772      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8773      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8774      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8775      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8776      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8777      GIR_EraseFromParent, /*InsnID*/0,
8778      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::VCCRRegClassID,
8779      // GIR_Coverage, 1854,
8780      GIR_Done,
8781    // Label 470: @21051
8782    GIM_Reject,
8783    // Label 449: @21052
8784    GIM_Try, /*On fail goto*//*Label 471*/ 21103, // Rule ID 1151 //
8785      GIM_CheckFeatures, GIFBS_HasNEON,
8786      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8787      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
8788      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8789      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8790      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8791      // (xor:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VEORd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
8792      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VEORd,
8793      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8794      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
8795      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8796      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8797      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8798      GIR_EraseFromParent, /*InsnID*/0,
8799      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8800      // GIR_Coverage, 1151,
8801      GIR_Done,
8802    // Label 471: @21103
8803    GIM_Reject,
8804    // Label 450: @21104
8805    GIM_Try, /*On fail goto*//*Label 472*/ 21219,
8806      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
8807      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8808      GIM_Try, /*On fail goto*//*Label 473*/ 21157, // Rule ID 2535 //
8809        GIM_CheckFeatures, GIFBS_HasNEON,
8810        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8811        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8812        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
8813        // (xor:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)  =>  (VEORq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)
8814        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VEORq,
8815        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8816        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
8817        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
8818        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8819        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8820        GIR_EraseFromParent, /*InsnID*/0,
8821        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8822        // GIR_Coverage, 2535,
8823        GIR_Done,
8824      // Label 473: @21157
8825      GIM_Try, /*On fail goto*//*Label 474*/ 21218, // Rule ID 3492 //
8826        GIM_CheckFeatures, GIFBS_HasMVEInt,
8827        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
8828        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
8829        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
8830        // (xor:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)  =>  (MVE_VEOR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
8831        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
8832        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8833        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
8834        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VEOR,
8835        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
8836        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
8837        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
8838        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
8839        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8840        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8841        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8842        GIR_EraseFromParent, /*InsnID*/0,
8843        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8844        // GIR_Coverage, 3492,
8845        GIR_Done,
8846      // Label 474: @21218
8847      GIM_Reject,
8848    // Label 472: @21219
8849    GIM_Reject,
8850    // Label 451: @21220
8851    GIM_Try, /*On fail goto*//*Label 475*/ 21325, // Rule ID 1855 //
8852      GIM_CheckFeatures, GIFBS_HasMVEInt,
8853      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1,
8854      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1,
8855      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
8856      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
8857      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
8858      // (xor:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v4i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8859      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8860      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8861      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8862      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
8863      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
8864      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8865      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8866      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
8867      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
8868      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8869      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
8870      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2EORrr,
8871      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
8872      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
8873      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
8874      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
8875      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8876      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8877      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8878      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8879      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8880      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8881      GIR_EraseFromParent, /*InsnID*/0,
8882      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::VCCRRegClassID,
8883      // GIR_Coverage, 1855,
8884      GIR_Done,
8885    // Label 475: @21325
8886    GIM_Reject,
8887    // Label 452: @21326
8888    GIM_Try, /*On fail goto*//*Label 476*/ 21377, // Rule ID 2531 //
8889      GIM_CheckFeatures, GIFBS_HasNEON,
8890      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8891      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
8892      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8893      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8894      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8895      // (xor:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)  =>  (VEORd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)
8896      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VEORd,
8897      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8898      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
8899      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
8900      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8901      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8902      GIR_EraseFromParent, /*InsnID*/0,
8903      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8904      // GIR_Coverage, 2531,
8905      GIR_Done,
8906    // Label 476: @21377
8907    GIM_Reject,
8908    // Label 453: @21378
8909    GIM_Try, /*On fail goto*//*Label 477*/ 21493,
8910      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
8911      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8912      GIM_Try, /*On fail goto*//*Label 478*/ 21431, // Rule ID 1152 //
8913        GIM_CheckFeatures, GIFBS_HasNEON,
8914        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8915        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8916        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
8917        // (xor:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VEORq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
8918        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VEORq,
8919        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8920        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
8921        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8922        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8923        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8924        GIR_EraseFromParent, /*InsnID*/0,
8925        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8926        // GIR_Coverage, 1152,
8927        GIR_Done,
8928      // Label 478: @21431
8929      GIM_Try, /*On fail goto*//*Label 479*/ 21492, // Rule ID 3488 //
8930        GIM_CheckFeatures, GIFBS_HasMVEInt,
8931        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
8932        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
8933        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
8934        // (xor:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VEOR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
8935        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
8936        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8937        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
8938        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VEOR,
8939        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
8940        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
8941        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
8942        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
8943        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8944        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8945        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8946        GIR_EraseFromParent, /*InsnID*/0,
8947        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8948        // GIR_Coverage, 3488,
8949        GIR_Done,
8950      // Label 479: @21492
8951      GIM_Reject,
8952    // Label 477: @21493
8953    GIM_Reject,
8954    // Label 454: @21494
8955    GIM_Try, /*On fail goto*//*Label 480*/ 21599, // Rule ID 1856 //
8956      GIM_CheckFeatures, GIFBS_HasMVEInt,
8957      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1,
8958      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1,
8959      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
8960      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
8961      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
8962      // (xor:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v8i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8963      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8964      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8965      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8966      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
8967      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
8968      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8969      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8970      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
8971      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
8972      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8973      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
8974      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2EORrr,
8975      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
8976      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
8977      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
8978      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
8979      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8980      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8981      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8982      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8983      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8984      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8985      GIR_EraseFromParent, /*InsnID*/0,
8986      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::VCCRRegClassID,
8987      // GIR_Coverage, 1856,
8988      GIR_Done,
8989    // Label 480: @21599
8990    GIM_Reject,
8991    // Label 455: @21600
8992    GIM_Try, /*On fail goto*//*Label 481*/ 21651, // Rule ID 2530 //
8993      GIM_CheckFeatures, GIFBS_HasNEON,
8994      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
8995      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
8996      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8997      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8998      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8999      // (xor:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)  =>  (VEORd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)
9000      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VEORd,
9001      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9002      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
9003      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
9004      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9005      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9006      GIR_EraseFromParent, /*InsnID*/0,
9007      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9008      // GIR_Coverage, 2530,
9009      GIR_Done,
9010    // Label 481: @21651
9011    GIM_Reject,
9012    // Label 456: @21652
9013    GIM_Try, /*On fail goto*//*Label 482*/ 21767,
9014      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9015      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9016      GIM_Try, /*On fail goto*//*Label 483*/ 21705, // Rule ID 2534 //
9017        GIM_CheckFeatures, GIFBS_HasNEON,
9018        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9019        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9020        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9021        // (xor:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)  =>  (VEORq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)
9022        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VEORq,
9023        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9024        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
9025        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
9026        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9027        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9028        GIR_EraseFromParent, /*InsnID*/0,
9029        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9030        // GIR_Coverage, 2534,
9031        GIR_Done,
9032      // Label 483: @21705
9033      GIM_Try, /*On fail goto*//*Label 484*/ 21766, // Rule ID 3484 //
9034        GIM_CheckFeatures, GIFBS_HasMVEInt,
9035        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9036        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9037        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
9038        // (xor:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VEOR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
9039        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9040        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9041        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
9042        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VEOR,
9043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
9044        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
9045        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
9046        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
9047        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9048        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9049        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
9050        GIR_EraseFromParent, /*InsnID*/0,
9051        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9052        // GIR_Coverage, 3484,
9053        GIR_Done,
9054      // Label 484: @21766
9055      GIM_Reject,
9056    // Label 482: @21767
9057    GIM_Reject,
9058    // Label 457: @21768
9059    GIM_Try, /*On fail goto*//*Label 485*/ 21873, // Rule ID 1853 //
9060      GIM_CheckFeatures, GIFBS_HasMVEInt,
9061      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1,
9062      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1,
9063      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
9064      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
9065      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
9066      // (xor:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2)  =>  (COPY_TO_REGCLASS:{ *:[v16i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9067      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9068      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9069      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9070      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
9071      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
9072      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9073      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
9074      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
9075      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
9076      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9077      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
9078      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2EORrr,
9079      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
9080      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
9081      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
9082      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
9083      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9084      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9085      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9086      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9087      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9088      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
9089      GIR_EraseFromParent, /*InsnID*/0,
9090      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::VCCRRegClassID,
9091      // GIR_Coverage, 1853,
9092      GIR_Done,
9093    // Label 485: @21873
9094    GIM_Reject,
9095    // Label 458: @21874
9096    GIM_Try, /*On fail goto*//*Label 486*/ 21989,
9097      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
9098      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
9099      GIM_Try, /*On fail goto*//*Label 487*/ 21927, // Rule ID 2533 //
9100        GIM_CheckFeatures, GIFBS_HasNEON,
9101        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9102        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9103        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9104        // (xor:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)  =>  (VEORq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)
9105        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VEORq,
9106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9107        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS
9108        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RHS
9109        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9110        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9111        GIR_EraseFromParent, /*InsnID*/0,
9112        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9113        // GIR_Coverage, 2533,
9114        GIR_Done,
9115      // Label 487: @21927
9116      GIM_Try, /*On fail goto*//*Label 488*/ 21988, // Rule ID 3480 //
9117        GIM_CheckFeatures, GIFBS_HasMVEInt,
9118        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9119        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9120        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
9121        // (xor:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VEOR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
9122        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9123        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
9124        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
9125        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VEOR,
9126        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
9127        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
9128        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
9129        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
9130        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9131        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9132        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
9133        GIR_EraseFromParent, /*InsnID*/0,
9134        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9135        // GIR_Coverage, 3480,
9136        GIR_Done,
9137      // Label 488: @21988
9138      GIM_Reject,
9139    // Label 486: @21989
9140    GIM_Reject,
9141    // Label 459: @21990
9142    GIM_Reject,
9143    // Label 8: @21991
9144    GIM_Try, /*On fail goto*//*Label 489*/ 22384,
9145      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
9146      GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 16, /*)*//*default:*//*Label 494*/ 22383,
9147      /*GILLT_v2s64*//*Label 490*/ 22013, 0, 0,
9148      /*GILLT_v4s32*//*Label 491*/ 22074, 0, 0, 0,
9149      /*GILLT_v8s16*//*Label 492*/ 22178, 0, 0,
9150      /*GILLT_v16s8*//*Label 493*/ 22322,
9151      // Label 490: @22013
9152      GIM_Try, /*On fail goto*//*Label 495*/ 22073, // Rule ID 3113 //
9153        GIM_CheckFeatures, GIFBS_HasNEON,
9154        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9155        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
9156        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9157        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9158        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9159        // (concat_vectors:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Dn, DPR:{ *:[v1i64] }:$Dm)  =>  (REG_SEQUENCE:{ *:[v2i64] } QPR:{ *:[i32] }, DPR:{ *:[v1i64] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v1i64] }:$Dm, dsub_1:{ *:[i32] })
9160        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
9161        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9162        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
9163        GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
9164        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
9165        GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
9166        GIR_EraseFromParent, /*InsnID*/0,
9167        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
9168        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPRRegClassID,
9169        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, ARM::DPRRegClassID,
9170        // GIR_Coverage, 3113,
9171        GIR_Done,
9172      // Label 495: @22073
9173      GIM_Reject,
9174      // Label 491: @22074
9175      GIM_Try, /*On fail goto*//*Label 496*/ 22177,
9176        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9177        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
9178        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9179        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9180        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9181        GIM_Try, /*On fail goto*//*Label 497*/ 22136, // Rule ID 3114 //
9182          GIM_CheckFeatures, GIFBS_HasNEON,
9183          // (concat_vectors:{ *:[v4i32] } DPR:{ *:[v2i32] }:$Dn, DPR:{ *:[v2i32] }:$Dm)  =>  (REG_SEQUENCE:{ *:[v4i32] } QPR:{ *:[i32] }, DPR:{ *:[v2i32] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v2i32] }:$Dm, dsub_1:{ *:[i32] })
9184          GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
9185          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9186          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
9187          GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
9188          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
9189          GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
9190          GIR_EraseFromParent, /*InsnID*/0,
9191          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
9192          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPRRegClassID,
9193          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, ARM::DPRRegClassID,
9194          // GIR_Coverage, 3114,
9195          GIR_Done,
9196        // Label 497: @22136
9197        GIM_Try, /*On fail goto*//*Label 498*/ 22176, // Rule ID 3117 //
9198          GIM_CheckFeatures, GIFBS_HasNEON,
9199          // (concat_vectors:{ *:[v4f32] } DPR:{ *:[v2f32] }:$Dn, DPR:{ *:[v2f32] }:$Dm)  =>  (REG_SEQUENCE:{ *:[v4f32] } QPR:{ *:[i32] }, DPR:{ *:[v2f32] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v2f32] }:$Dm, dsub_1:{ *:[i32] })
9200          GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
9201          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9202          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
9203          GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
9204          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
9205          GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
9206          GIR_EraseFromParent, /*InsnID*/0,
9207          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
9208          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPRRegClassID,
9209          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, ARM::DPRRegClassID,
9210          // GIR_Coverage, 3117,
9211          GIR_Done,
9212        // Label 498: @22176
9213        GIM_Reject,
9214      // Label 496: @22177
9215      GIM_Reject,
9216      // Label 492: @22178
9217      GIM_Try, /*On fail goto*//*Label 499*/ 22321,
9218        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9219        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
9220        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9221        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9222        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9223        GIM_Try, /*On fail goto*//*Label 500*/ 22240, // Rule ID 3115 //
9224          GIM_CheckFeatures, GIFBS_HasNEON,
9225          // (concat_vectors:{ *:[v8i16] } DPR:{ *:[v4i16] }:$Dn, DPR:{ *:[v4i16] }:$Dm)  =>  (REG_SEQUENCE:{ *:[v8i16] } QPR:{ *:[i32] }, DPR:{ *:[v4i16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4i16] }:$Dm, dsub_1:{ *:[i32] })
9226          GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
9227          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9228          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
9229          GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
9230          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
9231          GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
9232          GIR_EraseFromParent, /*InsnID*/0,
9233          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
9234          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPRRegClassID,
9235          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, ARM::DPRRegClassID,
9236          // GIR_Coverage, 3115,
9237          GIR_Done,
9238        // Label 500: @22240
9239        GIM_Try, /*On fail goto*//*Label 501*/ 22280, // Rule ID 3118 //
9240          GIM_CheckFeatures, GIFBS_HasNEON,
9241          // (concat_vectors:{ *:[v8f16] } DPR:{ *:[v4f16] }:$Dn, DPR:{ *:[v4f16] }:$Dm)  =>  (REG_SEQUENCE:{ *:[v8f16] } QPR:{ *:[i32] }, DPR:{ *:[v4f16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4f16] }:$Dm, dsub_1:{ *:[i32] })
9242          GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
9243          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9244          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
9245          GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
9246          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
9247          GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
9248          GIR_EraseFromParent, /*InsnID*/0,
9249          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
9250          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPRRegClassID,
9251          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, ARM::DPRRegClassID,
9252          // GIR_Coverage, 3118,
9253          GIR_Done,
9254        // Label 501: @22280
9255        GIM_Try, /*On fail goto*//*Label 502*/ 22320, // Rule ID 3119 //
9256          GIM_CheckFeatures, GIFBS_HasNEON,
9257          // (concat_vectors:{ *:[v8bf16] } DPR:{ *:[v4bf16] }:$Dn, DPR:{ *:[v4bf16] }:$Dm)  =>  (REG_SEQUENCE:{ *:[v8bf16] } QPR:{ *:[i32] }, DPR:{ *:[v4bf16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4bf16] }:$Dm, dsub_1:{ *:[i32] })
9258          GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
9259          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9260          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
9261          GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
9262          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
9263          GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
9264          GIR_EraseFromParent, /*InsnID*/0,
9265          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
9266          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPRRegClassID,
9267          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, ARM::DPRRegClassID,
9268          // GIR_Coverage, 3119,
9269          GIR_Done,
9270        // Label 502: @22320
9271        GIM_Reject,
9272      // Label 499: @22321
9273      GIM_Reject,
9274      // Label 493: @22322
9275      GIM_Try, /*On fail goto*//*Label 503*/ 22382, // Rule ID 3116 //
9276        GIM_CheckFeatures, GIFBS_HasNEON,
9277        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9278        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
9279        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9280        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9281        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9282        // (concat_vectors:{ *:[v16i8] } DPR:{ *:[v8i8] }:$Dn, DPR:{ *:[v8i8] }:$Dm)  =>  (REG_SEQUENCE:{ *:[v16i8] } QPR:{ *:[i32] }, DPR:{ *:[v8i8] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v8i8] }:$Dm, dsub_1:{ *:[i32] })
9283        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
9284        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9285        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
9286        GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
9287        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
9288        GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
9289        GIR_EraseFromParent, /*InsnID*/0,
9290        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
9291        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPRRegClassID,
9292        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, ARM::DPRRegClassID,
9293        // GIR_Coverage, 3116,
9294        GIR_Done,
9295      // Label 503: @22382
9296      GIM_Reject,
9297      // Label 494: @22383
9298      GIM_Reject,
9299    // Label 489: @22384
9300    GIM_Reject,
9301    // Label 9: @22385
9302    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 16, /*)*//*default:*//*Label 513*/ 33294,
9303    /*GILLT_s32*//*Label 504*/ 22406,
9304    /*GILLT_s64*//*Label 505*/ 22546, 0,
9305    /*GILLT_v2s32*//*Label 506*/ 23491,
9306    /*GILLT_v2s64*//*Label 507*/ 24436, 0,
9307    /*GILLT_v4s16*//*Label 508*/ 26359,
9308    /*GILLT_v4s32*//*Label 509*/ 27591, 0, 0,
9309    /*GILLT_v8s8*//*Label 510*/ 29514,
9310    /*GILLT_v8s16*//*Label 511*/ 30026, 0, 0,
9311    /*GILLT_v16s8*//*Label 512*/ 32236,
9312    // Label 504: @22406
9313    GIM_Try, /*On fail goto*//*Label 514*/ 22545,
9314      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
9315      GIM_Try, /*On fail goto*//*Label 515*/ 22447, // Rule ID 705 //
9316        GIM_CheckFeatures, GIFBS_HasFPRegs,
9317        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
9318        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
9319        // (bitconvert:{ *:[i32] } SPR:{ *:[f32] }:$Sn)  =>  (VMOVRS:{ *:[i32] } SPR:{ *:[f32] }:$Sn)
9320        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVRS,
9321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
9322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
9323        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9324        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9325        GIR_EraseFromParent, /*InsnID*/0,
9326        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9327        // GIR_Coverage, 705,
9328        GIR_Done,
9329      // Label 515: @22447
9330      GIM_Try, /*On fail goto*//*Label 516*/ 22482, // Rule ID 706 //
9331        GIM_CheckFeatures, GIFBS_HasFPRegs_UseVMOVSR,
9332        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
9333        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
9334        // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$Rt)  =>  (VMOVSR:{ *:[f32] } GPR:{ *:[i32] }:$Rt)
9335        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVSR,
9336        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sn
9337        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rt
9338        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9339        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9340        GIR_EraseFromParent, /*InsnID*/0,
9341        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9342        // GIR_Coverage, 706,
9343        GIR_Done,
9344      // Label 516: @22482
9345      GIM_Try, /*On fail goto*//*Label 517*/ 22544, // Rule ID 2733 //
9346        GIM_CheckFeatures, GIFBS_DontUseVMOVSR_HasNEON,
9347        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9348        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
9349        // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$a)  =>  (EXTRACT_SUBREG:{ *:[f32] } (VMOVDRR:{ *:[f64] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$a), ssub_0:{ *:[i32] })
9350        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
9351        GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VMOVDRR,
9352        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
9353        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
9354        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
9355        GIR_AddImm, /*InsnID*/1, /*Imm*/14,
9356        GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9357        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9358        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9359        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9360        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
9361        GIR_EraseFromParent, /*InsnID*/0,
9362        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
9363        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
9364        // GIR_Coverage, 2733,
9365        GIR_Done,
9366      // Label 517: @22544
9367      GIM_Reject,
9368    // Label 514: @22545
9369    GIM_Reject,
9370    // Label 505: @22546
9371    GIM_Try, /*On fail goto*//*Label 518*/ 22580, // Rule ID 2735 //
9372      GIM_CheckFeatures, GIFBS_HasNEON,
9373      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9374      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9375      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9376      // (bitconvert:{ *:[f64] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[f64] }:$src
9377      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9378      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9379      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9380      GIR_EraseFromParent, /*InsnID*/0,
9381      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9382      // GIR_Coverage, 2735,
9383      GIR_Done,
9384    // Label 518: @22580
9385    GIM_Try, /*On fail goto*//*Label 519*/ 22614, // Rule ID 2736 //
9386      GIM_CheckFeatures, GIFBS_HasNEON,
9387      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9388      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9389      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9390      // (bitconvert:{ *:[v1i64] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v1i64] }:$src
9391      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9392      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9393      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9394      GIR_EraseFromParent, /*InsnID*/0,
9395      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9396      // GIR_Coverage, 2736,
9397      GIR_Done,
9398    // Label 519: @22614
9399    GIM_Try, /*On fail goto*//*Label 520*/ 22648, // Rule ID 2751 //
9400      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9401      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9402      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9403      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9404      // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[f64] }:$src
9405      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9406      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9407      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9408      GIR_EraseFromParent, /*InsnID*/0,
9409      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9410      // GIR_Coverage, 2751,
9411      GIR_Done,
9412    // Label 520: @22648
9413    GIM_Try, /*On fail goto*//*Label 521*/ 22682, // Rule ID 2752 //
9414      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9415      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9416      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9417      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9418      // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[f64] }:$src
9419      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9420      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9421      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9422      GIR_EraseFromParent, /*InsnID*/0,
9423      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9424      // GIR_Coverage, 2752,
9425      GIR_Done,
9426    // Label 521: @22682
9427    GIM_Try, /*On fail goto*//*Label 522*/ 22716, // Rule ID 2753 //
9428      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9429      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9430      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9431      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9432      // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src)  =>  DPR:{ *:[f64] }:$src
9433      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9434      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9435      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9436      GIR_EraseFromParent, /*InsnID*/0,
9437      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9438      // GIR_Coverage, 2753,
9439      GIR_Done,
9440    // Label 522: @22716
9441    GIM_Try, /*On fail goto*//*Label 523*/ 22750, // Rule ID 2754 //
9442      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9443      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9444      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9445      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9446      // (bitconvert:{ *:[f64] } DPR:{ *:[v4bf16] }:$src)  =>  DPR:{ *:[f64] }:$src
9447      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9448      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9449      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9450      GIR_EraseFromParent, /*InsnID*/0,
9451      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9452      // GIR_Coverage, 2754,
9453      GIR_Done,
9454    // Label 523: @22750
9455    GIM_Try, /*On fail goto*//*Label 524*/ 22784, // Rule ID 2755 //
9456      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9457      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9458      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9459      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9460      // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[f64] }:$src
9461      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9462      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9463      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9464      GIR_EraseFromParent, /*InsnID*/0,
9465      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9466      // GIR_Coverage, 2755,
9467      GIR_Done,
9468    // Label 524: @22784
9469    GIM_Try, /*On fail goto*//*Label 525*/ 22818, // Rule ID 2756 //
9470      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9471      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9472      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9473      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9474      // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[f64] }:$src
9475      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9476      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9477      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9478      GIR_EraseFromParent, /*InsnID*/0,
9479      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9480      // GIR_Coverage, 2756,
9481      GIR_Done,
9482    // Label 525: @22818
9483    GIM_Try, /*On fail goto*//*Label 526*/ 22852, // Rule ID 2757 //
9484      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9485      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9486      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9487      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9488      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[v1i64] }:$src
9489      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9490      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9491      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9492      GIR_EraseFromParent, /*InsnID*/0,
9493      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9494      // GIR_Coverage, 2757,
9495      GIR_Done,
9496    // Label 526: @22852
9497    GIM_Try, /*On fail goto*//*Label 527*/ 22886, // Rule ID 2758 //
9498      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9499      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9500      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9501      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9502      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[v1i64] }:$src
9503      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9504      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9505      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9506      GIR_EraseFromParent, /*InsnID*/0,
9507      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9508      // GIR_Coverage, 2758,
9509      GIR_Done,
9510    // Label 527: @22886
9511    GIM_Try, /*On fail goto*//*Label 528*/ 22920, // Rule ID 2759 //
9512      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9513      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9514      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9515      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9516      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src)  =>  DPR:{ *:[v1i64] }:$src
9517      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9518      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9519      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9520      GIR_EraseFromParent, /*InsnID*/0,
9521      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9522      // GIR_Coverage, 2759,
9523      GIR_Done,
9524    // Label 528: @22920
9525    GIM_Try, /*On fail goto*//*Label 529*/ 22954, // Rule ID 2760 //
9526      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9527      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9528      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9529      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9530      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4bf16] }:$src)  =>  DPR:{ *:[v1i64] }:$src
9531      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9532      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9533      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9534      GIR_EraseFromParent, /*InsnID*/0,
9535      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9536      // GIR_Coverage, 2760,
9537      GIR_Done,
9538    // Label 529: @22954
9539    GIM_Try, /*On fail goto*//*Label 530*/ 22988, // Rule ID 2761 //
9540      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9541      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9542      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9543      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9544      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[v1i64] }:$src
9545      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9546      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9547      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9548      GIR_EraseFromParent, /*InsnID*/0,
9549      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9550      // GIR_Coverage, 2761,
9551      GIR_Done,
9552    // Label 530: @22988
9553    GIM_Try, /*On fail goto*//*Label 531*/ 23022, // Rule ID 2762 //
9554      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9555      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9556      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9557      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9558      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[v1i64] }:$src
9559      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9560      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9561      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9562      GIR_EraseFromParent, /*InsnID*/0,
9563      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9564      // GIR_Coverage, 2762,
9565      GIR_Done,
9566    // Label 531: @23022
9567    GIM_Try, /*On fail goto*//*Label 532*/ 23061, // Rule ID 2843 //
9568      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9569      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9570      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9571      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9572      // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src)  =>  (VREV64d32:{ *:[f64] } DPR:{ *:[v2f32] }:$src)
9573      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
9574      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9575      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9576      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9577      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9578      GIR_EraseFromParent, /*InsnID*/0,
9579      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9580      // GIR_Coverage, 2843,
9581      GIR_Done,
9582    // Label 532: @23061
9583    GIM_Try, /*On fail goto*//*Label 533*/ 23100, // Rule ID 2844 //
9584      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9585      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9586      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9587      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9588      // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src)  =>  (VREV64d32:{ *:[f64] } DPR:{ *:[v2i32] }:$src)
9589      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
9590      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9591      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9592      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9593      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9594      GIR_EraseFromParent, /*InsnID*/0,
9595      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9596      // GIR_Coverage, 2844,
9597      GIR_Done,
9598    // Label 533: @23100
9599    GIM_Try, /*On fail goto*//*Label 534*/ 23139, // Rule ID 2845 //
9600      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9601      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9602      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9603      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9604      // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src)  =>  (VREV64d16:{ *:[f64] } DPR:{ *:[v4f16] }:$src)
9605      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9606      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9607      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9608      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9609      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9610      GIR_EraseFromParent, /*InsnID*/0,
9611      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9612      // GIR_Coverage, 2845,
9613      GIR_Done,
9614    // Label 534: @23139
9615    GIM_Try, /*On fail goto*//*Label 535*/ 23178, // Rule ID 2846 //
9616      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9617      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9618      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9619      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9620      // (bitconvert:{ *:[f64] } DPR:{ *:[v4bf16] }:$src)  =>  (VREV64d16:{ *:[f64] } DPR:{ *:[v4bf16] }:$src)
9621      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9622      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9623      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9624      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9625      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9626      GIR_EraseFromParent, /*InsnID*/0,
9627      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9628      // GIR_Coverage, 2846,
9629      GIR_Done,
9630    // Label 535: @23178
9631    GIM_Try, /*On fail goto*//*Label 536*/ 23217, // Rule ID 2847 //
9632      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9633      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9634      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9635      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9636      // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src)  =>  (VREV64d16:{ *:[f64] } DPR:{ *:[v4i16] }:$src)
9637      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9638      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9639      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9640      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9641      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9642      GIR_EraseFromParent, /*InsnID*/0,
9643      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9644      // GIR_Coverage, 2847,
9645      GIR_Done,
9646    // Label 536: @23217
9647    GIM_Try, /*On fail goto*//*Label 537*/ 23256, // Rule ID 2848 //
9648      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9649      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9650      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9651      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9652      // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src)  =>  (VREV64d8:{ *:[f64] } DPR:{ *:[v8i8] }:$src)
9653      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8,
9654      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9655      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9656      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9657      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9658      GIR_EraseFromParent, /*InsnID*/0,
9659      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9660      // GIR_Coverage, 2848,
9661      GIR_Done,
9662    // Label 537: @23256
9663    GIM_Try, /*On fail goto*//*Label 538*/ 23295, // Rule ID 2849 //
9664      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9665      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9666      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9667      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9668      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src)  =>  (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src)
9669      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
9670      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9671      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9672      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9673      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9674      GIR_EraseFromParent, /*InsnID*/0,
9675      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9676      // GIR_Coverage, 2849,
9677      GIR_Done,
9678    // Label 538: @23295
9679    GIM_Try, /*On fail goto*//*Label 539*/ 23334, // Rule ID 2850 //
9680      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9681      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9682      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9683      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9684      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src)  =>  (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src)
9685      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
9686      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9687      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9688      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9689      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9690      GIR_EraseFromParent, /*InsnID*/0,
9691      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9692      // GIR_Coverage, 2850,
9693      GIR_Done,
9694    // Label 539: @23334
9695    GIM_Try, /*On fail goto*//*Label 540*/ 23373, // Rule ID 2851 //
9696      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9697      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9698      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9699      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9700      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src)  =>  (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src)
9701      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9702      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9703      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9704      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9705      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9706      GIR_EraseFromParent, /*InsnID*/0,
9707      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9708      // GIR_Coverage, 2851,
9709      GIR_Done,
9710    // Label 540: @23373
9711    GIM_Try, /*On fail goto*//*Label 541*/ 23412, // Rule ID 2852 //
9712      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9713      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9714      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9715      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9716      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4bf16] }:$src)  =>  (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4bf16] }:$src)
9717      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9718      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9719      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9720      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9721      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9722      GIR_EraseFromParent, /*InsnID*/0,
9723      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9724      // GIR_Coverage, 2852,
9725      GIR_Done,
9726    // Label 541: @23412
9727    GIM_Try, /*On fail goto*//*Label 542*/ 23451, // Rule ID 2853 //
9728      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9729      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9730      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9731      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9732      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src)  =>  (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src)
9733      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9734      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9735      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9736      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9737      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9738      GIR_EraseFromParent, /*InsnID*/0,
9739      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9740      // GIR_Coverage, 2853,
9741      GIR_Done,
9742    // Label 542: @23451
9743    GIM_Try, /*On fail goto*//*Label 543*/ 23490, // Rule ID 2854 //
9744      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9745      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9746      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9747      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9748      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src)  =>  (VREV64d8:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src)
9749      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8,
9750      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9751      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9752      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9753      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9754      GIR_EraseFromParent, /*InsnID*/0,
9755      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9756      // GIR_Coverage, 2854,
9757      GIR_Done,
9758    // Label 543: @23490
9759    GIM_Reject,
9760    // Label 506: @23491
9761    GIM_Try, /*On fail goto*//*Label 544*/ 23525, // Rule ID 2737 //
9762      GIM_CheckFeatures, GIFBS_HasNEON,
9763      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9764      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9765      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9766      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[v2f32] }:$src
9767      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9768      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9769      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9770      GIR_EraseFromParent, /*InsnID*/0,
9771      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9772      // GIR_Coverage, 2737,
9773      GIR_Done,
9774    // Label 544: @23525
9775    GIM_Try, /*On fail goto*//*Label 545*/ 23559, // Rule ID 2738 //
9776      GIM_CheckFeatures, GIFBS_HasNEON,
9777      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9778      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9779      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9780      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[v2i32] }:$src
9781      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9782      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9783      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9784      GIR_EraseFromParent, /*InsnID*/0,
9785      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9786      // GIR_Coverage, 2738,
9787      GIR_Done,
9788    // Label 545: @23559
9789    GIM_Try, /*On fail goto*//*Label 546*/ 23593, // Rule ID 2763 //
9790      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9791      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9792      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9793      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9794      // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v2f32] }:$src
9795      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9796      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9797      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9798      GIR_EraseFromParent, /*InsnID*/0,
9799      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9800      // GIR_Coverage, 2763,
9801      GIR_Done,
9802    // Label 546: @23593
9803    GIM_Try, /*On fail goto*//*Label 547*/ 23627, // Rule ID 2764 //
9804      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9805      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9806      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9807      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9808      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[v2f32] }:$src
9809      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9810      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9811      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9812      GIR_EraseFromParent, /*InsnID*/0,
9813      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9814      // GIR_Coverage, 2764,
9815      GIR_Done,
9816    // Label 547: @23627
9817    GIM_Try, /*On fail goto*//*Label 548*/ 23661, // Rule ID 2765 //
9818      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9819      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9820      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9821      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9822      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src)  =>  DPR:{ *:[v2f32] }:$src
9823      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9824      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9825      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9826      GIR_EraseFromParent, /*InsnID*/0,
9827      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9828      // GIR_Coverage, 2765,
9829      GIR_Done,
9830    // Label 548: @23661
9831    GIM_Try, /*On fail goto*//*Label 549*/ 23695, // Rule ID 2766 //
9832      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9833      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9834      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9835      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9836      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4bf16] }:$src)  =>  DPR:{ *:[v2f32] }:$src
9837      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9838      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9839      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9840      GIR_EraseFromParent, /*InsnID*/0,
9841      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9842      // GIR_Coverage, 2766,
9843      GIR_Done,
9844    // Label 549: @23695
9845    GIM_Try, /*On fail goto*//*Label 550*/ 23729, // Rule ID 2767 //
9846      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9847      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9848      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9849      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9850      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[v2f32] }:$src
9851      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9852      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9853      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9854      GIR_EraseFromParent, /*InsnID*/0,
9855      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9856      // GIR_Coverage, 2767,
9857      GIR_Done,
9858    // Label 550: @23729
9859    GIM_Try, /*On fail goto*//*Label 551*/ 23763, // Rule ID 2768 //
9860      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9861      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9862      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9863      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9864      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[v2f32] }:$src
9865      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9866      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9867      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9868      GIR_EraseFromParent, /*InsnID*/0,
9869      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9870      // GIR_Coverage, 2768,
9871      GIR_Done,
9872    // Label 551: @23763
9873    GIM_Try, /*On fail goto*//*Label 552*/ 23797, // Rule ID 2769 //
9874      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9875      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9876      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9877      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9878      // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v2i32] }:$src
9879      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9880      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9881      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9882      GIR_EraseFromParent, /*InsnID*/0,
9883      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9884      // GIR_Coverage, 2769,
9885      GIR_Done,
9886    // Label 552: @23797
9887    GIM_Try, /*On fail goto*//*Label 553*/ 23831, // Rule ID 2770 //
9888      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9889      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9890      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9891      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9892      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[v2i32] }:$src
9893      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9894      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9895      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9896      GIR_EraseFromParent, /*InsnID*/0,
9897      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9898      // GIR_Coverage, 2770,
9899      GIR_Done,
9900    // Label 553: @23831
9901    GIM_Try, /*On fail goto*//*Label 554*/ 23865, // Rule ID 2771 //
9902      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9903      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9904      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9905      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9906      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src)  =>  DPR:{ *:[v2i32] }:$src
9907      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9908      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9909      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9910      GIR_EraseFromParent, /*InsnID*/0,
9911      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9912      // GIR_Coverage, 2771,
9913      GIR_Done,
9914    // Label 554: @23865
9915    GIM_Try, /*On fail goto*//*Label 555*/ 23899, // Rule ID 2772 //
9916      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9917      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9918      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9919      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9920      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4bf16] }:$src)  =>  DPR:{ *:[v2i32] }:$src
9921      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9922      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9923      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9924      GIR_EraseFromParent, /*InsnID*/0,
9925      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9926      // GIR_Coverage, 2772,
9927      GIR_Done,
9928    // Label 555: @23899
9929    GIM_Try, /*On fail goto*//*Label 556*/ 23933, // Rule ID 2773 //
9930      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9931      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9932      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9933      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9934      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[v2i32] }:$src
9935      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9936      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9937      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9938      GIR_EraseFromParent, /*InsnID*/0,
9939      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9940      // GIR_Coverage, 2773,
9941      GIR_Done,
9942    // Label 556: @23933
9943    GIM_Try, /*On fail goto*//*Label 557*/ 23967, // Rule ID 2774 //
9944      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9945      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9946      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9947      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9948      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[v2i32] }:$src
9949      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9950      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9951      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9952      GIR_EraseFromParent, /*InsnID*/0,
9953      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9954      // GIR_Coverage, 2774,
9955      GIR_Done,
9956    // Label 557: @23967
9957    GIM_Try, /*On fail goto*//*Label 558*/ 24006, // Rule ID 2855 //
9958      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9959      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9960      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9961      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9962      // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src)  =>  (VREV64d32:{ *:[v2f32] } DPR:{ *:[f64] }:$src)
9963      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
9964      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9965      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9966      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9967      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9968      GIR_EraseFromParent, /*InsnID*/0,
9969      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9970      // GIR_Coverage, 2855,
9971      GIR_Done,
9972    // Label 558: @24006
9973    GIM_Try, /*On fail goto*//*Label 559*/ 24045, // Rule ID 2856 //
9974      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9975      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9976      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9977      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9978      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src)  =>  (VREV64d32:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src)
9979      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
9980      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9981      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9982      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9983      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9984      GIR_EraseFromParent, /*InsnID*/0,
9985      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9986      // GIR_Coverage, 2856,
9987      GIR_Done,
9988    // Label 559: @24045
9989    GIM_Try, /*On fail goto*//*Label 560*/ 24084, // Rule ID 2857 //
9990      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9991      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9992      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9993      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9994      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src)  =>  (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src)
9995      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
9996      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9997      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9998      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9999      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10000      GIR_EraseFromParent, /*InsnID*/0,
10001      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10002      // GIR_Coverage, 2857,
10003      GIR_Done,
10004    // Label 560: @24084
10005    GIM_Try, /*On fail goto*//*Label 561*/ 24123, // Rule ID 2858 //
10006      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10007      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10008      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10009      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10010      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4bf16] }:$src)  =>  (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4bf16] }:$src)
10011      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
10012      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10013      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10014      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10015      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10016      GIR_EraseFromParent, /*InsnID*/0,
10017      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10018      // GIR_Coverage, 2858,
10019      GIR_Done,
10020    // Label 561: @24123
10021    GIM_Try, /*On fail goto*//*Label 562*/ 24162, // Rule ID 2859 //
10022      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10023      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10024      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10025      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10026      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src)  =>  (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src)
10027      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
10028      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10029      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10030      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10031      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10032      GIR_EraseFromParent, /*InsnID*/0,
10033      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10034      // GIR_Coverage, 2859,
10035      GIR_Done,
10036    // Label 562: @24162
10037    GIM_Try, /*On fail goto*//*Label 563*/ 24201, // Rule ID 2860 //
10038      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10039      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
10040      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10041      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10042      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src)  =>  (VREV32d8:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src)
10043      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8,
10044      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10045      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10046      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10047      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10048      GIR_EraseFromParent, /*InsnID*/0,
10049      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10050      // GIR_Coverage, 2860,
10051      GIR_Done,
10052    // Label 563: @24201
10053    GIM_Try, /*On fail goto*//*Label 564*/ 24240, // Rule ID 2861 //
10054      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10055      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10056      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10057      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10058      // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src)  =>  (VREV64d32:{ *:[v2i32] } DPR:{ *:[f64] }:$src)
10059      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
10060      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10061      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10062      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10063      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10064      GIR_EraseFromParent, /*InsnID*/0,
10065      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10066      // GIR_Coverage, 2861,
10067      GIR_Done,
10068    // Label 564: @24240
10069    GIM_Try, /*On fail goto*//*Label 565*/ 24279, // Rule ID 2862 //
10070      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10071      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10072      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10073      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10074      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src)  =>  (VREV64d32:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src)
10075      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
10076      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10077      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10078      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10079      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10080      GIR_EraseFromParent, /*InsnID*/0,
10081      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10082      // GIR_Coverage, 2862,
10083      GIR_Done,
10084    // Label 565: @24279
10085    GIM_Try, /*On fail goto*//*Label 566*/ 24318, // Rule ID 2863 //
10086      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10087      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10088      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10089      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10090      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src)  =>  (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src)
10091      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
10092      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10093      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10094      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10095      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10096      GIR_EraseFromParent, /*InsnID*/0,
10097      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10098      // GIR_Coverage, 2863,
10099      GIR_Done,
10100    // Label 566: @24318
10101    GIM_Try, /*On fail goto*//*Label 567*/ 24357, // Rule ID 2864 //
10102      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10103      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10104      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10105      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10106      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4bf16] }:$src)  =>  (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4bf16] }:$src)
10107      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
10108      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10109      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10110      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10111      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10112      GIR_EraseFromParent, /*InsnID*/0,
10113      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10114      // GIR_Coverage, 2864,
10115      GIR_Done,
10116    // Label 567: @24357
10117    GIM_Try, /*On fail goto*//*Label 568*/ 24396, // Rule ID 2865 //
10118      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10119      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10120      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10121      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10122      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src)  =>  (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src)
10123      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
10124      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10125      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10126      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10127      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10128      GIR_EraseFromParent, /*InsnID*/0,
10129      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10130      // GIR_Coverage, 2865,
10131      GIR_Done,
10132    // Label 568: @24396
10133    GIM_Try, /*On fail goto*//*Label 569*/ 24435, // Rule ID 2866 //
10134      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10135      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
10136      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10137      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10138      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src)  =>  (VREV32d8:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src)
10139      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8,
10140      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10141      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10142      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10143      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10144      GIR_EraseFromParent, /*InsnID*/0,
10145      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10146      // GIR_Coverage, 2866,
10147      GIR_Done,
10148    // Label 569: @24435
10149    GIM_Reject,
10150    // Label 507: @24436
10151    GIM_Try, /*On fail goto*//*Label 570*/ 24470, // Rule ID 2743 //
10152      GIM_CheckFeatures, GIFBS_HasNEON,
10153      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10154      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10155      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10156      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v2f64] }:$src
10157      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10158      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10159      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10160      GIR_EraseFromParent, /*InsnID*/0,
10161      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
10162      // GIR_Coverage, 2743,
10163      GIR_Done,
10164    // Label 570: @24470
10165    GIM_Try, /*On fail goto*//*Label 571*/ 24504, // Rule ID 2744 //
10166      GIM_CheckFeatures, GIFBS_HasNEON,
10167      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10168      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10169      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10170      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v2i64] }:$src
10171      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10172      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10173      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10174      GIR_EraseFromParent, /*InsnID*/0,
10175      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
10176      // GIR_Coverage, 2744,
10177      GIR_Done,
10178    // Label 571: @24504
10179    GIM_Try, /*On fail goto*//*Label 572*/ 24538, // Rule ID 2797 //
10180      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10181      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10182      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10183      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10184      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v2f64] }:$src
10185      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10186      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10187      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10188      GIR_EraseFromParent, /*InsnID*/0,
10189      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
10190      // GIR_Coverage, 2797,
10191      GIR_Done,
10192    // Label 572: @24538
10193    GIM_Try, /*On fail goto*//*Label 573*/ 24572, // Rule ID 2798 //
10194      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10195      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10196      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10197      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10198      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v2f64] }:$src
10199      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10200      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10201      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10202      GIR_EraseFromParent, /*InsnID*/0,
10203      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
10204      // GIR_Coverage, 2798,
10205      GIR_Done,
10206    // Label 573: @24572
10207    GIM_Try, /*On fail goto*//*Label 574*/ 24606, // Rule ID 2799 //
10208      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10209      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10210      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10211      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10212      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src)  =>  QPR:{ *:[v2f64] }:$src
10213      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10214      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10215      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10216      GIR_EraseFromParent, /*InsnID*/0,
10217      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
10218      // GIR_Coverage, 2799,
10219      GIR_Done,
10220    // Label 574: @24606
10221    GIM_Try, /*On fail goto*//*Label 575*/ 24640, // Rule ID 2800 //
10222      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10223      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10224      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10225      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10226      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8bf16] }:$src)  =>  QPR:{ *:[v2f64] }:$src
10227      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10228      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10229      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10230      GIR_EraseFromParent, /*InsnID*/0,
10231      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
10232      // GIR_Coverage, 2800,
10233      GIR_Done,
10234    // Label 575: @24640
10235    GIM_Try, /*On fail goto*//*Label 576*/ 24674, // Rule ID 2801 //
10236      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10237      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10238      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10239      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10240      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v2f64] }:$src
10241      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10242      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10243      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10244      GIR_EraseFromParent, /*InsnID*/0,
10245      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
10246      // GIR_Coverage, 2801,
10247      GIR_Done,
10248    // Label 576: @24674
10249    GIM_Try, /*On fail goto*//*Label 577*/ 24708, // Rule ID 2802 //
10250      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10251      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10252      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10253      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10254      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v2f64] }:$src
10255      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10256      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10257      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10258      GIR_EraseFromParent, /*InsnID*/0,
10259      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
10260      // GIR_Coverage, 2802,
10261      GIR_Done,
10262    // Label 577: @24708
10263    GIM_Try, /*On fail goto*//*Label 578*/ 24742, // Rule ID 2803 //
10264      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10265      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10266      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10267      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10268      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v2i64] }:$src
10269      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10270      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10271      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10272      GIR_EraseFromParent, /*InsnID*/0,
10273      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
10274      // GIR_Coverage, 2803,
10275      GIR_Done,
10276    // Label 578: @24742
10277    GIM_Try, /*On fail goto*//*Label 579*/ 24776, // Rule ID 2804 //
10278      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10279      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10280      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10281      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10282      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v2i64] }:$src
10283      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10284      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10285      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10286      GIR_EraseFromParent, /*InsnID*/0,
10287      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
10288      // GIR_Coverage, 2804,
10289      GIR_Done,
10290    // Label 579: @24776
10291    GIM_Try, /*On fail goto*//*Label 580*/ 24810, // Rule ID 2805 //
10292      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10293      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10294      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10295      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10296      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src)  =>  QPR:{ *:[v2i64] }:$src
10297      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10298      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10299      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10300      GIR_EraseFromParent, /*InsnID*/0,
10301      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
10302      // GIR_Coverage, 2805,
10303      GIR_Done,
10304    // Label 580: @24810
10305    GIM_Try, /*On fail goto*//*Label 581*/ 24844, // Rule ID 2806 //
10306      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10307      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10308      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10309      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10310      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8bf16] }:$src)  =>  QPR:{ *:[v2i64] }:$src
10311      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10312      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10313      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10314      GIR_EraseFromParent, /*InsnID*/0,
10315      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
10316      // GIR_Coverage, 2806,
10317      GIR_Done,
10318    // Label 581: @24844
10319    GIM_Try, /*On fail goto*//*Label 582*/ 24878, // Rule ID 2807 //
10320      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10321      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10322      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10323      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10324      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v2i64] }:$src
10325      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10326      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10327      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10328      GIR_EraseFromParent, /*InsnID*/0,
10329      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
10330      // GIR_Coverage, 2807,
10331      GIR_Done,
10332    // Label 582: @24878
10333    GIM_Try, /*On fail goto*//*Label 583*/ 24912, // Rule ID 2808 //
10334      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10335      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10336      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10337      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10338      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v2i64] }:$src
10339      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10340      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10341      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10342      GIR_EraseFromParent, /*InsnID*/0,
10343      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
10344      // GIR_Coverage, 2808,
10345      GIR_Done,
10346    // Label 583: @24912
10347    GIM_Try, /*On fail goto*//*Label 584*/ 24951, // Rule ID 2889 //
10348      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10349      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10350      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10351      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10352      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src)  =>  (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src)
10353      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
10354      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10355      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10356      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10357      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10358      GIR_EraseFromParent, /*InsnID*/0,
10359      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10360      // GIR_Coverage, 2889,
10361      GIR_Done,
10362    // Label 584: @24951
10363    GIM_Try, /*On fail goto*//*Label 585*/ 24990, // Rule ID 2890 //
10364      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10365      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10366      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10367      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10368      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src)  =>  (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src)
10369      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
10370      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10371      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10372      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10373      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10374      GIR_EraseFromParent, /*InsnID*/0,
10375      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10376      // GIR_Coverage, 2890,
10377      GIR_Done,
10378    // Label 585: @24990
10379    GIM_Try, /*On fail goto*//*Label 586*/ 25029, // Rule ID 2891 //
10380      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10381      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10382      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10383      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10384      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src)  =>  (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src)
10385      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
10386      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10387      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10388      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10389      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10390      GIR_EraseFromParent, /*InsnID*/0,
10391      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10392      // GIR_Coverage, 2891,
10393      GIR_Done,
10394    // Label 586: @25029
10395    GIM_Try, /*On fail goto*//*Label 587*/ 25068, // Rule ID 2892 //
10396      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10397      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10398      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10399      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10400      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8bf16] }:$src)  =>  (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8bf16] }:$src)
10401      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
10402      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10403      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10404      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10405      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10406      GIR_EraseFromParent, /*InsnID*/0,
10407      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10408      // GIR_Coverage, 2892,
10409      GIR_Done,
10410    // Label 587: @25068
10411    GIM_Try, /*On fail goto*//*Label 588*/ 25107, // Rule ID 2893 //
10412      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10413      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10414      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10415      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10416      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src)  =>  (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src)
10417      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
10418      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10419      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10420      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10421      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10422      GIR_EraseFromParent, /*InsnID*/0,
10423      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10424      // GIR_Coverage, 2893,
10425      GIR_Done,
10426    // Label 588: @25107
10427    GIM_Try, /*On fail goto*//*Label 589*/ 25146, // Rule ID 2894 //
10428      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10429      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10430      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10431      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10432      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src)  =>  (VREV64q8:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src)
10433      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8,
10434      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10435      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10436      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10437      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10438      GIR_EraseFromParent, /*InsnID*/0,
10439      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10440      // GIR_Coverage, 2894,
10441      GIR_Done,
10442    // Label 589: @25146
10443    GIM_Try, /*On fail goto*//*Label 590*/ 25185, // Rule ID 2895 //
10444      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10445      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10446      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10447      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10448      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src)  =>  (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src)
10449      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
10450      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10451      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10452      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10453      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10454      GIR_EraseFromParent, /*InsnID*/0,
10455      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10456      // GIR_Coverage, 2895,
10457      GIR_Done,
10458    // Label 590: @25185
10459    GIM_Try, /*On fail goto*//*Label 591*/ 25224, // Rule ID 2896 //
10460      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10461      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10462      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10463      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10464      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src)  =>  (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src)
10465      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
10466      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10467      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10468      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10469      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10470      GIR_EraseFromParent, /*InsnID*/0,
10471      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10472      // GIR_Coverage, 2896,
10473      GIR_Done,
10474    // Label 591: @25224
10475    GIM_Try, /*On fail goto*//*Label 592*/ 25263, // Rule ID 2897 //
10476      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10477      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10478      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10479      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10480      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src)  =>  (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src)
10481      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
10482      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10483      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10484      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10485      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10486      GIR_EraseFromParent, /*InsnID*/0,
10487      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10488      // GIR_Coverage, 2897,
10489      GIR_Done,
10490    // Label 592: @25263
10491    GIM_Try, /*On fail goto*//*Label 593*/ 25302, // Rule ID 2898 //
10492      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10493      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10494      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10495      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10496      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8bf16] }:$src)  =>  (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8bf16] }:$src)
10497      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
10498      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10499      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10500      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10501      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10502      GIR_EraseFromParent, /*InsnID*/0,
10503      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10504      // GIR_Coverage, 2898,
10505      GIR_Done,
10506    // Label 593: @25302
10507    GIM_Try, /*On fail goto*//*Label 594*/ 25341, // Rule ID 2899 //
10508      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10509      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10510      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10511      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10512      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src)  =>  (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src)
10513      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
10514      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10515      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10516      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10517      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10518      GIR_EraseFromParent, /*InsnID*/0,
10519      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10520      // GIR_Coverage, 2899,
10521      GIR_Done,
10522    // Label 594: @25341
10523    GIM_Try, /*On fail goto*//*Label 595*/ 25380, // Rule ID 2900 //
10524      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10525      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10526      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10527      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10528      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src)  =>  (VREV64q8:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src)
10529      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8,
10530      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10531      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10532      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10533      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10534      GIR_EraseFromParent, /*InsnID*/0,
10535      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10536      // GIR_Coverage, 2900,
10537      GIR_Done,
10538    // Label 595: @25380
10539    GIM_Try, /*On fail goto*//*Label 596*/ 25414, // Rule ID 5383 //
10540      GIM_CheckFeatures, GIFBS_HasMVEInt,
10541      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10542      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10543      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10544      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$src)  =>  MQPR:{ *:[v2f64] }:$src
10545      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10546      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10547      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10548      GIR_EraseFromParent, /*InsnID*/0,
10549      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10550      // GIR_Coverage, 5383,
10551      GIR_Done,
10552    // Label 596: @25414
10553    GIM_Try, /*On fail goto*//*Label 597*/ 25448, // Rule ID 5384 //
10554      GIM_CheckFeatures, GIFBS_HasMVEInt,
10555      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10556      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10557      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10558      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$src)  =>  MQPR:{ *:[v2i64] }:$src
10559      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10560      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10561      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10562      GIR_EraseFromParent, /*InsnID*/0,
10563      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10564      // GIR_Coverage, 5384,
10565      GIR_Done,
10566    // Label 597: @25448
10567    GIM_Try, /*On fail goto*//*Label 598*/ 25482, // Rule ID 5389 //
10568      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10569      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10570      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10571      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10572      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src)  =>  MQPR:{ *:[v2f64] }:$src
10573      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10574      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10575      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10576      GIR_EraseFromParent, /*InsnID*/0,
10577      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10578      // GIR_Coverage, 5389,
10579      GIR_Done,
10580    // Label 598: @25482
10581    GIM_Try, /*On fail goto*//*Label 599*/ 25516, // Rule ID 5390 //
10582      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10583      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10584      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10585      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10586      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src)  =>  MQPR:{ *:[v2f64] }:$src
10587      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10588      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10589      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10590      GIR_EraseFromParent, /*InsnID*/0,
10591      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10592      // GIR_Coverage, 5390,
10593      GIR_Done,
10594    // Label 599: @25516
10595    GIM_Try, /*On fail goto*//*Label 600*/ 25550, // Rule ID 5391 //
10596      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10597      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10598      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10599      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10600      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src)  =>  MQPR:{ *:[v2f64] }:$src
10601      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10602      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10603      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10604      GIR_EraseFromParent, /*InsnID*/0,
10605      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10606      // GIR_Coverage, 5391,
10607      GIR_Done,
10608    // Label 600: @25550
10609    GIM_Try, /*On fail goto*//*Label 601*/ 25584, // Rule ID 5392 //
10610      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10611      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10612      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10613      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10614      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src)  =>  MQPR:{ *:[v2f64] }:$src
10615      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10616      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10617      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10618      GIR_EraseFromParent, /*InsnID*/0,
10619      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10620      // GIR_Coverage, 5392,
10621      GIR_Done,
10622    // Label 601: @25584
10623    GIM_Try, /*On fail goto*//*Label 602*/ 25618, // Rule ID 5393 //
10624      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10625      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10626      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10627      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10628      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src)  =>  MQPR:{ *:[v2f64] }:$src
10629      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10630      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10631      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10632      GIR_EraseFromParent, /*InsnID*/0,
10633      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10634      // GIR_Coverage, 5393,
10635      GIR_Done,
10636    // Label 602: @25618
10637    GIM_Try, /*On fail goto*//*Label 603*/ 25652, // Rule ID 5394 //
10638      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10639      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10640      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10641      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10642      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src)  =>  MQPR:{ *:[v2i64] }:$src
10643      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10644      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10645      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10646      GIR_EraseFromParent, /*InsnID*/0,
10647      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10648      // GIR_Coverage, 5394,
10649      GIR_Done,
10650    // Label 603: @25652
10651    GIM_Try, /*On fail goto*//*Label 604*/ 25686, // Rule ID 5395 //
10652      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10653      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10654      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10655      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10656      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src)  =>  MQPR:{ *:[v2i64] }:$src
10657      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10658      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10659      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10660      GIR_EraseFromParent, /*InsnID*/0,
10661      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10662      // GIR_Coverage, 5395,
10663      GIR_Done,
10664    // Label 604: @25686
10665    GIM_Try, /*On fail goto*//*Label 605*/ 25720, // Rule ID 5396 //
10666      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10667      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10668      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10669      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10670      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src)  =>  MQPR:{ *:[v2i64] }:$src
10671      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10672      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10673      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10674      GIR_EraseFromParent, /*InsnID*/0,
10675      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10676      // GIR_Coverage, 5396,
10677      GIR_Done,
10678    // Label 605: @25720
10679    GIM_Try, /*On fail goto*//*Label 606*/ 25754, // Rule ID 5397 //
10680      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10681      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10682      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10683      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10684      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src)  =>  MQPR:{ *:[v2i64] }:$src
10685      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10686      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10687      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10688      GIR_EraseFromParent, /*InsnID*/0,
10689      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10690      // GIR_Coverage, 5397,
10691      GIR_Done,
10692    // Label 606: @25754
10693    GIM_Try, /*On fail goto*//*Label 607*/ 25788, // Rule ID 5398 //
10694      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10695      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10696      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10697      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10698      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src)  =>  MQPR:{ *:[v2i64] }:$src
10699      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10700      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10701      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10702      GIR_EraseFromParent, /*InsnID*/0,
10703      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10704      // GIR_Coverage, 5398,
10705      GIR_Done,
10706    // Label 607: @25788
10707    GIM_Try, /*On fail goto*//*Label 608*/ 25845, // Rule ID 5425 //
10708      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10709      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10710      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10711      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10712      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src)
10713      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10714      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10715      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10716      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
10717      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10718      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10719      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10720      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10721      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10722      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10723      GIR_EraseFromParent, /*InsnID*/0,
10724      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10725      // GIR_Coverage, 5425,
10726      GIR_Done,
10727    // Label 608: @25845
10728    GIM_Try, /*On fail goto*//*Label 609*/ 25902, // Rule ID 5426 //
10729      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10730      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10731      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10732      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10733      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src)
10734      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10735      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10736      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10737      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
10738      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10739      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10740      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10741      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10742      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10743      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10744      GIR_EraseFromParent, /*InsnID*/0,
10745      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10746      // GIR_Coverage, 5426,
10747      GIR_Done,
10748    // Label 609: @25902
10749    GIM_Try, /*On fail goto*//*Label 610*/ 25959, // Rule ID 5427 //
10750      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10751      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10752      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10753      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10754      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src)
10755      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10756      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10757      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10758      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
10759      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10760      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10761      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10762      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10763      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10764      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10765      GIR_EraseFromParent, /*InsnID*/0,
10766      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10767      // GIR_Coverage, 5427,
10768      GIR_Done,
10769    // Label 610: @25959
10770    GIM_Try, /*On fail goto*//*Label 611*/ 26016, // Rule ID 5428 //
10771      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10772      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10773      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10774      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10775      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src)
10776      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10777      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10778      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10779      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
10780      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10781      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10782      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10783      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10784      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10785      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10786      GIR_EraseFromParent, /*InsnID*/0,
10787      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10788      // GIR_Coverage, 5428,
10789      GIR_Done,
10790    // Label 611: @26016
10791    GIM_Try, /*On fail goto*//*Label 612*/ 26073, // Rule ID 5429 //
10792      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10793      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10794      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10795      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10796      // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src)  =>  (MVE_VREV64_8:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src)
10797      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10798      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10799      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10800      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_8,
10801      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10802      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10803      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10804      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10805      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10806      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10807      GIR_EraseFromParent, /*InsnID*/0,
10808      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10809      // GIR_Coverage, 5429,
10810      GIR_Done,
10811    // Label 612: @26073
10812    GIM_Try, /*On fail goto*//*Label 613*/ 26130, // Rule ID 5430 //
10813      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10814      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10815      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10816      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10817      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src)
10818      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10819      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10820      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10821      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
10822      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10823      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10824      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10825      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10826      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10827      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10828      GIR_EraseFromParent, /*InsnID*/0,
10829      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10830      // GIR_Coverage, 5430,
10831      GIR_Done,
10832    // Label 613: @26130
10833    GIM_Try, /*On fail goto*//*Label 614*/ 26187, // Rule ID 5431 //
10834      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10835      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10836      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10837      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10838      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src)
10839      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10840      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10841      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10842      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
10843      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10844      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10845      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10846      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10847      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10848      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10849      GIR_EraseFromParent, /*InsnID*/0,
10850      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10851      // GIR_Coverage, 5431,
10852      GIR_Done,
10853    // Label 614: @26187
10854    GIM_Try, /*On fail goto*//*Label 615*/ 26244, // Rule ID 5432 //
10855      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10856      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10857      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10858      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10859      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src)
10860      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10861      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10862      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10863      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
10864      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10865      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10866      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10867      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10868      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10869      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10870      GIR_EraseFromParent, /*InsnID*/0,
10871      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10872      // GIR_Coverage, 5432,
10873      GIR_Done,
10874    // Label 615: @26244
10875    GIM_Try, /*On fail goto*//*Label 616*/ 26301, // Rule ID 5433 //
10876      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10877      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10878      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10879      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10880      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src)
10881      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10882      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10883      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10884      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
10885      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10886      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10887      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10888      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10889      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10890      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10891      GIR_EraseFromParent, /*InsnID*/0,
10892      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10893      // GIR_Coverage, 5433,
10894      GIR_Done,
10895    // Label 616: @26301
10896    GIM_Try, /*On fail goto*//*Label 617*/ 26358, // Rule ID 5434 //
10897      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10898      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10899      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10900      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10901      // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src)  =>  (MVE_VREV64_8:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src)
10902      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10903      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10904      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10905      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_8,
10906      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10907      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10908      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10909      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10910      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10911      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10912      GIR_EraseFromParent, /*InsnID*/0,
10913      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10914      // GIR_Coverage, 5434,
10915      GIR_Done,
10916    // Label 617: @26358
10917    GIM_Reject,
10918    // Label 508: @26359
10919    GIM_Try, /*On fail goto*//*Label 618*/ 26393, // Rule ID 2739 //
10920      GIM_CheckFeatures, GIFBS_HasNEON,
10921      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10922      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10923      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10924      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v4f16] }:$src)  =>  DPR:{ *:[v4i16] }:$src
10925      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10926      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10927      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10928      GIR_EraseFromParent, /*InsnID*/0,
10929      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10930      // GIR_Coverage, 2739,
10931      GIR_Done,
10932    // Label 618: @26393
10933    GIM_Try, /*On fail goto*//*Label 619*/ 26427, // Rule ID 2740 //
10934      GIM_CheckFeatures, GIFBS_HasNEON,
10935      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10936      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10937      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10938      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[v4f16] }:$src
10939      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10940      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10941      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10942      GIR_EraseFromParent, /*InsnID*/0,
10943      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10944      // GIR_Coverage, 2740,
10945      GIR_Done,
10946    // Label 619: @26427
10947    GIM_Try, /*On fail goto*//*Label 620*/ 26461, // Rule ID 2741 //
10948      GIM_CheckFeatures, GIFBS_HasNEON,
10949      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10950      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10951      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10952      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v4bf16] }:$src)  =>  DPR:{ *:[v4i16] }:$src
10953      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10954      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10955      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10956      GIR_EraseFromParent, /*InsnID*/0,
10957      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10958      // GIR_Coverage, 2741,
10959      GIR_Done,
10960    // Label 620: @26461
10961    GIM_Try, /*On fail goto*//*Label 621*/ 26495, // Rule ID 2742 //
10962      GIM_CheckFeatures, GIFBS_HasNEON,
10963      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10964      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10965      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10966      // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[v4bf16] }:$src
10967      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10968      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10969      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10970      GIR_EraseFromParent, /*InsnID*/0,
10971      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10972      // GIR_Coverage, 2742,
10973      GIR_Done,
10974    // Label 621: @26495
10975    GIM_Try, /*On fail goto*//*Label 622*/ 26529, // Rule ID 2775 //
10976      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10977      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10978      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10979      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10980      // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v4f16] }:$src
10981      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10982      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10983      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10984      GIR_EraseFromParent, /*InsnID*/0,
10985      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10986      // GIR_Coverage, 2775,
10987      GIR_Done,
10988    // Label 622: @26529
10989    GIM_Try, /*On fail goto*//*Label 623*/ 26563, // Rule ID 2776 //
10990      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10991      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10992      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10993      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10994      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[v4f16] }:$src
10995      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10996      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10997      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10998      GIR_EraseFromParent, /*InsnID*/0,
10999      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
11000      // GIR_Coverage, 2776,
11001      GIR_Done,
11002    // Label 623: @26563
11003    GIM_Try, /*On fail goto*//*Label 624*/ 26597, // Rule ID 2777 //
11004      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11005      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11006      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11007      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11008      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[v4f16] }:$src
11009      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11010      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11011      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11012      GIR_EraseFromParent, /*InsnID*/0,
11013      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
11014      // GIR_Coverage, 2777,
11015      GIR_Done,
11016    // Label 624: @26597
11017    GIM_Try, /*On fail goto*//*Label 625*/ 26631, // Rule ID 2778 //
11018      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11019      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11020      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11021      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11022      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[v4f16] }:$src
11023      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11024      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11025      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11026      GIR_EraseFromParent, /*InsnID*/0,
11027      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
11028      // GIR_Coverage, 2778,
11029      GIR_Done,
11030    // Label 625: @26631
11031    GIM_Try, /*On fail goto*//*Label 626*/ 26665, // Rule ID 2779 //
11032      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11033      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
11034      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11035      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11036      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[v4f16] }:$src
11037      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11038      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11039      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11040      GIR_EraseFromParent, /*InsnID*/0,
11041      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
11042      // GIR_Coverage, 2779,
11043      GIR_Done,
11044    // Label 626: @26665
11045    GIM_Try, /*On fail goto*//*Label 627*/ 26699, // Rule ID 2780 //
11046      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11047      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11048      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11049      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11050      // (bitconvert:{ *:[v4bf16] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v4bf16] }:$src
11051      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11052      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11053      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11054      GIR_EraseFromParent, /*InsnID*/0,
11055      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
11056      // GIR_Coverage, 2780,
11057      GIR_Done,
11058    // Label 627: @26699
11059    GIM_Try, /*On fail goto*//*Label 628*/ 26733, // Rule ID 2781 //
11060      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11061      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11062      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11063      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11064      // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[v4bf16] }:$src
11065      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11066      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11067      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11068      GIR_EraseFromParent, /*InsnID*/0,
11069      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
11070      // GIR_Coverage, 2781,
11071      GIR_Done,
11072    // Label 628: @26733
11073    GIM_Try, /*On fail goto*//*Label 629*/ 26767, // Rule ID 2782 //
11074      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11075      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11076      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11077      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11078      // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[v4bf16] }:$src
11079      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11080      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11081      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11082      GIR_EraseFromParent, /*InsnID*/0,
11083      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
11084      // GIR_Coverage, 2782,
11085      GIR_Done,
11086    // Label 629: @26767
11087    GIM_Try, /*On fail goto*//*Label 630*/ 26801, // Rule ID 2783 //
11088      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11089      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11090      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11091      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11092      // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[v4bf16] }:$src
11093      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11094      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11095      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11096      GIR_EraseFromParent, /*InsnID*/0,
11097      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
11098      // GIR_Coverage, 2783,
11099      GIR_Done,
11100    // Label 630: @26801
11101    GIM_Try, /*On fail goto*//*Label 631*/ 26835, // Rule ID 2784 //
11102      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11103      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
11104      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11105      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11106      // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[v4bf16] }:$src
11107      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11108      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11109      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11110      GIR_EraseFromParent, /*InsnID*/0,
11111      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
11112      // GIR_Coverage, 2784,
11113      GIR_Done,
11114    // Label 631: @26835
11115    GIM_Try, /*On fail goto*//*Label 632*/ 26869, // Rule ID 2785 //
11116      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11117      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11118      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11119      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11120      // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v4i16] }:$src
11121      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11122      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11123      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11124      GIR_EraseFromParent, /*InsnID*/0,
11125      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
11126      // GIR_Coverage, 2785,
11127      GIR_Done,
11128    // Label 632: @26869
11129    GIM_Try, /*On fail goto*//*Label 633*/ 26903, // Rule ID 2786 //
11130      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11131      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11132      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11133      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11134      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[v4i16] }:$src
11135      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11136      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11137      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11138      GIR_EraseFromParent, /*InsnID*/0,
11139      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
11140      // GIR_Coverage, 2786,
11141      GIR_Done,
11142    // Label 633: @26903
11143    GIM_Try, /*On fail goto*//*Label 634*/ 26937, // Rule ID 2787 //
11144      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11145      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11146      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11147      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11148      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[v4i16] }:$src
11149      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11150      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11151      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11152      GIR_EraseFromParent, /*InsnID*/0,
11153      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
11154      // GIR_Coverage, 2787,
11155      GIR_Done,
11156    // Label 634: @26937
11157    GIM_Try, /*On fail goto*//*Label 635*/ 26971, // Rule ID 2788 //
11158      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11159      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11160      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11161      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11162      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[v4i16] }:$src
11163      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11164      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11165      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11166      GIR_EraseFromParent, /*InsnID*/0,
11167      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
11168      // GIR_Coverage, 2788,
11169      GIR_Done,
11170    // Label 635: @26971
11171    GIM_Try, /*On fail goto*//*Label 636*/ 27005, // Rule ID 2789 //
11172      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11173      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
11174      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11175      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11176      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[v4i16] }:$src
11177      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11178      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11179      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11180      GIR_EraseFromParent, /*InsnID*/0,
11181      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
11182      // GIR_Coverage, 2789,
11183      GIR_Done,
11184    // Label 636: @27005
11185    GIM_Try, /*On fail goto*//*Label 637*/ 27044, // Rule ID 2867 //
11186      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11187      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11188      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11189      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11190      // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src)  =>  (VREV64d16:{ *:[v4f16] } DPR:{ *:[f64] }:$src)
11191      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
11192      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11193      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11194      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11195      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11196      GIR_EraseFromParent, /*InsnID*/0,
11197      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11198      // GIR_Coverage, 2867,
11199      GIR_Done,
11200    // Label 637: @27044
11201    GIM_Try, /*On fail goto*//*Label 638*/ 27083, // Rule ID 2868 //
11202      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11203      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11204      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11205      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11206      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src)  =>  (VREV64d16:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src)
11207      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
11208      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11209      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11210      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11211      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11212      GIR_EraseFromParent, /*InsnID*/0,
11213      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11214      // GIR_Coverage, 2868,
11215      GIR_Done,
11216    // Label 638: @27083
11217    GIM_Try, /*On fail goto*//*Label 639*/ 27122, // Rule ID 2869 //
11218      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11219      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11220      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11221      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11222      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src)  =>  (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src)
11223      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
11224      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11225      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11226      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11227      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11228      GIR_EraseFromParent, /*InsnID*/0,
11229      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11230      // GIR_Coverage, 2869,
11231      GIR_Done,
11232    // Label 639: @27122
11233    GIM_Try, /*On fail goto*//*Label 640*/ 27161, // Rule ID 2870 //
11234      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11235      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11236      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11237      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11238      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src)  =>  (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src)
11239      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
11240      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11241      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11242      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11243      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11244      GIR_EraseFromParent, /*InsnID*/0,
11245      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11246      // GIR_Coverage, 2870,
11247      GIR_Done,
11248    // Label 640: @27161
11249    GIM_Try, /*On fail goto*//*Label 641*/ 27200, // Rule ID 2871 //
11250      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11251      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
11252      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11253      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11254      // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src)  =>  (VREV16d8:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src)
11255      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8,
11256      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11257      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11258      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11259      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11260      GIR_EraseFromParent, /*InsnID*/0,
11261      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11262      // GIR_Coverage, 2871,
11263      GIR_Done,
11264    // Label 641: @27200
11265    GIM_Try, /*On fail goto*//*Label 642*/ 27239, // Rule ID 2872 //
11266      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11267      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11268      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11269      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11270      // (bitconvert:{ *:[v4bf16] } DPR:{ *:[f64] }:$src)  =>  (VREV64d16:{ *:[v4bf16] } DPR:{ *:[f64] }:$src)
11271      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
11272      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11273      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11274      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11275      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11276      GIR_EraseFromParent, /*InsnID*/0,
11277      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11278      // GIR_Coverage, 2872,
11279      GIR_Done,
11280    // Label 642: @27239
11281    GIM_Try, /*On fail goto*//*Label 643*/ 27278, // Rule ID 2873 //
11282      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11283      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11284      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11285      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11286      // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v1i64] }:$src)  =>  (VREV64d16:{ *:[v4bf16] } DPR:{ *:[v1i64] }:$src)
11287      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
11288      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11289      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11290      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11291      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11292      GIR_EraseFromParent, /*InsnID*/0,
11293      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11294      // GIR_Coverage, 2873,
11295      GIR_Done,
11296    // Label 643: @27278
11297    GIM_Try, /*On fail goto*//*Label 644*/ 27317, // Rule ID 2874 //
11298      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11299      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11300      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11301      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11302      // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v2f32] }:$src)  =>  (VREV32d16:{ *:[v4bf16] } DPR:{ *:[v2f32] }:$src)
11303      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
11304      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11305      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11306      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11307      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11308      GIR_EraseFromParent, /*InsnID*/0,
11309      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11310      // GIR_Coverage, 2874,
11311      GIR_Done,
11312    // Label 644: @27317
11313    GIM_Try, /*On fail goto*//*Label 645*/ 27356, // Rule ID 2875 //
11314      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11315      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11316      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11317      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11318      // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v2i32] }:$src)  =>  (VREV32d16:{ *:[v4bf16] } DPR:{ *:[v2i32] }:$src)
11319      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
11320      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11321      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11322      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11323      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11324      GIR_EraseFromParent, /*InsnID*/0,
11325      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11326      // GIR_Coverage, 2875,
11327      GIR_Done,
11328    // Label 645: @27356
11329    GIM_Try, /*On fail goto*//*Label 646*/ 27395, // Rule ID 2876 //
11330      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11331      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
11332      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11333      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11334      // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v8i8] }:$src)  =>  (VREV16d8:{ *:[v4bf16] } DPR:{ *:[v8i8] }:$src)
11335      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8,
11336      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11337      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11338      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11339      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11340      GIR_EraseFromParent, /*InsnID*/0,
11341      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11342      // GIR_Coverage, 2876,
11343      GIR_Done,
11344    // Label 646: @27395
11345    GIM_Try, /*On fail goto*//*Label 647*/ 27434, // Rule ID 2877 //
11346      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11347      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11348      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11349      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11350      // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src)  =>  (VREV64d16:{ *:[v4i16] } DPR:{ *:[f64] }:$src)
11351      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
11352      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11353      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11354      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11355      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11356      GIR_EraseFromParent, /*InsnID*/0,
11357      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11358      // GIR_Coverage, 2877,
11359      GIR_Done,
11360    // Label 647: @27434
11361    GIM_Try, /*On fail goto*//*Label 648*/ 27473, // Rule ID 2878 //
11362      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11363      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11364      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11365      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11366      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src)  =>  (VREV64d16:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src)
11367      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
11368      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11369      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11370      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11371      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11372      GIR_EraseFromParent, /*InsnID*/0,
11373      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11374      // GIR_Coverage, 2878,
11375      GIR_Done,
11376    // Label 648: @27473
11377    GIM_Try, /*On fail goto*//*Label 649*/ 27512, // Rule ID 2879 //
11378      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11379      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11380      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11381      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11382      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src)  =>  (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src)
11383      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
11384      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11385      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11386      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11387      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11388      GIR_EraseFromParent, /*InsnID*/0,
11389      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11390      // GIR_Coverage, 2879,
11391      GIR_Done,
11392    // Label 649: @27512
11393    GIM_Try, /*On fail goto*//*Label 650*/ 27551, // Rule ID 2880 //
11394      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11395      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11396      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11397      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11398      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src)  =>  (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src)
11399      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
11400      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11401      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11402      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11403      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11404      GIR_EraseFromParent, /*InsnID*/0,
11405      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11406      // GIR_Coverage, 2880,
11407      GIR_Done,
11408    // Label 650: @27551
11409    GIM_Try, /*On fail goto*//*Label 651*/ 27590, // Rule ID 2881 //
11410      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11411      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
11412      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11413      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11414      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src)  =>  (VREV16d8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src)
11415      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8,
11416      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11417      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11418      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11419      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11420      GIR_EraseFromParent, /*InsnID*/0,
11421      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11422      // GIR_Coverage, 2881,
11423      GIR_Done,
11424    // Label 651: @27590
11425    GIM_Reject,
11426    // Label 509: @27591
11427    GIM_Try, /*On fail goto*//*Label 652*/ 27625, // Rule ID 2745 //
11428      GIM_CheckFeatures, GIFBS_HasNEON,
11429      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11430      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11431      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11432      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v4i32] }:$src
11433      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11434      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11435      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11436      GIR_EraseFromParent, /*InsnID*/0,
11437      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11438      // GIR_Coverage, 2745,
11439      GIR_Done,
11440    // Label 652: @27625
11441    GIM_Try, /*On fail goto*//*Label 653*/ 27659, // Rule ID 2746 //
11442      GIM_CheckFeatures, GIFBS_HasNEON,
11443      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11444      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11445      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11446      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v4f32] }:$src
11447      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11448      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11449      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11450      GIR_EraseFromParent, /*InsnID*/0,
11451      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11452      // GIR_Coverage, 2746,
11453      GIR_Done,
11454    // Label 653: @27659
11455    GIM_Try, /*On fail goto*//*Label 654*/ 27693, // Rule ID 2809 //
11456      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11457      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11458      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11459      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11460      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v4f32] }:$src
11461      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11462      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11463      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11464      GIR_EraseFromParent, /*InsnID*/0,
11465      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11466      // GIR_Coverage, 2809,
11467      GIR_Done,
11468    // Label 654: @27693
11469    GIM_Try, /*On fail goto*//*Label 655*/ 27727, // Rule ID 2810 //
11470      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11471      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11472      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11473      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11474      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v4f32] }:$src
11475      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11476      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11477      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11478      GIR_EraseFromParent, /*InsnID*/0,
11479      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11480      // GIR_Coverage, 2810,
11481      GIR_Done,
11482    // Label 655: @27727
11483    GIM_Try, /*On fail goto*//*Label 656*/ 27761, // Rule ID 2811 //
11484      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11485      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11486      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11487      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11488      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src)  =>  QPR:{ *:[v4f32] }:$src
11489      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11490      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11491      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11492      GIR_EraseFromParent, /*InsnID*/0,
11493      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11494      // GIR_Coverage, 2811,
11495      GIR_Done,
11496    // Label 656: @27761
11497    GIM_Try, /*On fail goto*//*Label 657*/ 27795, // Rule ID 2812 //
11498      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11499      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11500      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11501      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11502      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8bf16] }:$src)  =>  QPR:{ *:[v4f32] }:$src
11503      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11504      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11505      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11506      GIR_EraseFromParent, /*InsnID*/0,
11507      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11508      // GIR_Coverage, 2812,
11509      GIR_Done,
11510    // Label 657: @27795
11511    GIM_Try, /*On fail goto*//*Label 658*/ 27829, // Rule ID 2813 //
11512      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11513      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11514      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11515      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11516      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v4f32] }:$src
11517      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11518      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11519      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11520      GIR_EraseFromParent, /*InsnID*/0,
11521      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11522      // GIR_Coverage, 2813,
11523      GIR_Done,
11524    // Label 658: @27829
11525    GIM_Try, /*On fail goto*//*Label 659*/ 27863, // Rule ID 2814 //
11526      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11527      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11528      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11529      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11530      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v4f32] }:$src
11531      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11532      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11533      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11534      GIR_EraseFromParent, /*InsnID*/0,
11535      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11536      // GIR_Coverage, 2814,
11537      GIR_Done,
11538    // Label 659: @27863
11539    GIM_Try, /*On fail goto*//*Label 660*/ 27897, // Rule ID 2815 //
11540      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11541      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11542      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11543      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11544      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v4i32] }:$src
11545      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11546      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11547      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11548      GIR_EraseFromParent, /*InsnID*/0,
11549      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11550      // GIR_Coverage, 2815,
11551      GIR_Done,
11552    // Label 660: @27897
11553    GIM_Try, /*On fail goto*//*Label 661*/ 27931, // Rule ID 2816 //
11554      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11555      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11556      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11557      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11558      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v4i32] }:$src
11559      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11560      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11561      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11562      GIR_EraseFromParent, /*InsnID*/0,
11563      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11564      // GIR_Coverage, 2816,
11565      GIR_Done,
11566    // Label 661: @27931
11567    GIM_Try, /*On fail goto*//*Label 662*/ 27965, // Rule ID 2817 //
11568      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11569      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11570      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11571      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11572      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src)  =>  QPR:{ *:[v4i32] }:$src
11573      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11574      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11575      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11576      GIR_EraseFromParent, /*InsnID*/0,
11577      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11578      // GIR_Coverage, 2817,
11579      GIR_Done,
11580    // Label 662: @27965
11581    GIM_Try, /*On fail goto*//*Label 663*/ 27999, // Rule ID 2818 //
11582      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11583      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11584      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11585      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11586      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8bf16] }:$src)  =>  QPR:{ *:[v4i32] }:$src
11587      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11588      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11589      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11590      GIR_EraseFromParent, /*InsnID*/0,
11591      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11592      // GIR_Coverage, 2818,
11593      GIR_Done,
11594    // Label 663: @27999
11595    GIM_Try, /*On fail goto*//*Label 664*/ 28033, // Rule ID 2819 //
11596      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11597      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11598      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11599      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11600      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v4i32] }:$src
11601      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11602      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11603      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11604      GIR_EraseFromParent, /*InsnID*/0,
11605      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11606      // GIR_Coverage, 2819,
11607      GIR_Done,
11608    // Label 664: @28033
11609    GIM_Try, /*On fail goto*//*Label 665*/ 28067, // Rule ID 2820 //
11610      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11611      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11612      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11613      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11614      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v4i32] }:$src
11615      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11616      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11617      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11618      GIR_EraseFromParent, /*InsnID*/0,
11619      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11620      // GIR_Coverage, 2820,
11621      GIR_Done,
11622    // Label 665: @28067
11623    GIM_Try, /*On fail goto*//*Label 666*/ 28106, // Rule ID 2901 //
11624      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11625      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11626      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11627      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11628      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src)  =>  (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src)
11629      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
11630      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11631      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11632      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11633      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11634      GIR_EraseFromParent, /*InsnID*/0,
11635      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11636      // GIR_Coverage, 2901,
11637      GIR_Done,
11638    // Label 666: @28106
11639    GIM_Try, /*On fail goto*//*Label 667*/ 28145, // Rule ID 2902 //
11640      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11641      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11642      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11643      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11644      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src)  =>  (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src)
11645      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
11646      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11647      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11648      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11649      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11650      GIR_EraseFromParent, /*InsnID*/0,
11651      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11652      // GIR_Coverage, 2902,
11653      GIR_Done,
11654    // Label 667: @28145
11655    GIM_Try, /*On fail goto*//*Label 668*/ 28184, // Rule ID 2903 //
11656      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11657      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11658      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11659      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11660      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src)  =>  (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src)
11661      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
11662      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11663      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11664      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11665      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11666      GIR_EraseFromParent, /*InsnID*/0,
11667      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11668      // GIR_Coverage, 2903,
11669      GIR_Done,
11670    // Label 668: @28184
11671    GIM_Try, /*On fail goto*//*Label 669*/ 28223, // Rule ID 2904 //
11672      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11673      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11674      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11675      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11676      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8bf16] }:$src)  =>  (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8bf16] }:$src)
11677      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
11678      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11679      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11680      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11681      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11682      GIR_EraseFromParent, /*InsnID*/0,
11683      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11684      // GIR_Coverage, 2904,
11685      GIR_Done,
11686    // Label 669: @28223
11687    GIM_Try, /*On fail goto*//*Label 670*/ 28262, // Rule ID 2905 //
11688      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11689      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11690      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11691      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11692      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src)  =>  (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src)
11693      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
11694      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11695      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11696      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11697      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11698      GIR_EraseFromParent, /*InsnID*/0,
11699      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11700      // GIR_Coverage, 2905,
11701      GIR_Done,
11702    // Label 670: @28262
11703    GIM_Try, /*On fail goto*//*Label 671*/ 28301, // Rule ID 2906 //
11704      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11705      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11706      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11707      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11708      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src)  =>  (VREV32q8:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src)
11709      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8,
11710      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11711      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11712      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11713      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11714      GIR_EraseFromParent, /*InsnID*/0,
11715      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11716      // GIR_Coverage, 2906,
11717      GIR_Done,
11718    // Label 671: @28301
11719    GIM_Try, /*On fail goto*//*Label 672*/ 28340, // Rule ID 2907 //
11720      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11721      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11722      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11723      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11724      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src)  =>  (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src)
11725      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
11726      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11727      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11728      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11729      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11730      GIR_EraseFromParent, /*InsnID*/0,
11731      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11732      // GIR_Coverage, 2907,
11733      GIR_Done,
11734    // Label 672: @28340
11735    GIM_Try, /*On fail goto*//*Label 673*/ 28379, // Rule ID 2908 //
11736      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11737      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11738      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11739      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11740      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src)  =>  (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src)
11741      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
11742      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11743      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11744      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11745      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11746      GIR_EraseFromParent, /*InsnID*/0,
11747      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11748      // GIR_Coverage, 2908,
11749      GIR_Done,
11750    // Label 673: @28379
11751    GIM_Try, /*On fail goto*//*Label 674*/ 28418, // Rule ID 2909 //
11752      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11753      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11754      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11755      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11756      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src)  =>  (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src)
11757      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
11758      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11759      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11760      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11761      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11762      GIR_EraseFromParent, /*InsnID*/0,
11763      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11764      // GIR_Coverage, 2909,
11765      GIR_Done,
11766    // Label 674: @28418
11767    GIM_Try, /*On fail goto*//*Label 675*/ 28457, // Rule ID 2910 //
11768      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11769      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11770      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11771      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11772      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8bf16] }:$src)  =>  (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8bf16] }:$src)
11773      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
11774      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11775      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11776      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11777      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11778      GIR_EraseFromParent, /*InsnID*/0,
11779      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11780      // GIR_Coverage, 2910,
11781      GIR_Done,
11782    // Label 675: @28457
11783    GIM_Try, /*On fail goto*//*Label 676*/ 28496, // Rule ID 2911 //
11784      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11785      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11786      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11787      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11788      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src)  =>  (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src)
11789      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
11790      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11791      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11792      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11793      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11794      GIR_EraseFromParent, /*InsnID*/0,
11795      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11796      // GIR_Coverage, 2911,
11797      GIR_Done,
11798    // Label 676: @28496
11799    GIM_Try, /*On fail goto*//*Label 677*/ 28535, // Rule ID 2912 //
11800      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11801      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11802      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11803      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11804      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src)  =>  (VREV32q8:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src)
11805      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8,
11806      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11807      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11808      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11809      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11810      GIR_EraseFromParent, /*InsnID*/0,
11811      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11812      // GIR_Coverage, 2912,
11813      GIR_Done,
11814    // Label 677: @28535
11815    GIM_Try, /*On fail goto*//*Label 678*/ 28569, // Rule ID 5385 //
11816      GIM_CheckFeatures, GIFBS_HasMVEInt,
11817      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11818      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11819      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11820      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)  =>  MQPR:{ *:[v4i32] }:$src
11821      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11822      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11823      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11824      GIR_EraseFromParent, /*InsnID*/0,
11825      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11826      // GIR_Coverage, 5385,
11827      GIR_Done,
11828    // Label 678: @28569
11829    GIM_Try, /*On fail goto*//*Label 679*/ 28603, // Rule ID 5386 //
11830      GIM_CheckFeatures, GIFBS_HasMVEInt,
11831      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11832      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11833      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11834      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)  =>  MQPR:{ *:[v4f32] }:$src
11835      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11836      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11837      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11838      GIR_EraseFromParent, /*InsnID*/0,
11839      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11840      // GIR_Coverage, 5386,
11841      GIR_Done,
11842    // Label 679: @28603
11843    GIM_Try, /*On fail goto*//*Label 680*/ 28637, // Rule ID 5399 //
11844      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11845      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11846      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11847      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11848      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src)  =>  MQPR:{ *:[v4f32] }:$src
11849      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11850      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11851      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11852      GIR_EraseFromParent, /*InsnID*/0,
11853      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11854      // GIR_Coverage, 5399,
11855      GIR_Done,
11856    // Label 680: @28637
11857    GIM_Try, /*On fail goto*//*Label 681*/ 28671, // Rule ID 5400 //
11858      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11859      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11860      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11861      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11862      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src)  =>  MQPR:{ *:[v4f32] }:$src
11863      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11864      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11865      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11866      GIR_EraseFromParent, /*InsnID*/0,
11867      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11868      // GIR_Coverage, 5400,
11869      GIR_Done,
11870    // Label 681: @28671
11871    GIM_Try, /*On fail goto*//*Label 682*/ 28705, // Rule ID 5401 //
11872      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11873      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11874      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11875      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11876      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src)  =>  MQPR:{ *:[v4f32] }:$src
11877      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11878      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11879      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11880      GIR_EraseFromParent, /*InsnID*/0,
11881      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11882      // GIR_Coverage, 5401,
11883      GIR_Done,
11884    // Label 682: @28705
11885    GIM_Try, /*On fail goto*//*Label 683*/ 28739, // Rule ID 5402 //
11886      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11887      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11888      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11889      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11890      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src)  =>  MQPR:{ *:[v4f32] }:$src
11891      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11892      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11893      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11894      GIR_EraseFromParent, /*InsnID*/0,
11895      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11896      // GIR_Coverage, 5402,
11897      GIR_Done,
11898    // Label 683: @28739
11899    GIM_Try, /*On fail goto*//*Label 684*/ 28773, // Rule ID 5403 //
11900      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11901      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11902      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11903      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11904      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src)  =>  MQPR:{ *:[v4f32] }:$src
11905      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11906      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11907      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11908      GIR_EraseFromParent, /*InsnID*/0,
11909      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11910      // GIR_Coverage, 5403,
11911      GIR_Done,
11912    // Label 684: @28773
11913    GIM_Try, /*On fail goto*//*Label 685*/ 28807, // Rule ID 5404 //
11914      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11915      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11916      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11917      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11918      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src)  =>  MQPR:{ *:[v4i32] }:$src
11919      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11920      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11921      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11922      GIR_EraseFromParent, /*InsnID*/0,
11923      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11924      // GIR_Coverage, 5404,
11925      GIR_Done,
11926    // Label 685: @28807
11927    GIM_Try, /*On fail goto*//*Label 686*/ 28841, // Rule ID 5405 //
11928      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11929      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11930      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11931      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11932      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src)  =>  MQPR:{ *:[v4i32] }:$src
11933      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11934      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11935      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11936      GIR_EraseFromParent, /*InsnID*/0,
11937      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11938      // GIR_Coverage, 5405,
11939      GIR_Done,
11940    // Label 686: @28841
11941    GIM_Try, /*On fail goto*//*Label 687*/ 28875, // Rule ID 5406 //
11942      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11943      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11944      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11945      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11946      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src)  =>  MQPR:{ *:[v4i32] }:$src
11947      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11948      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11949      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11950      GIR_EraseFromParent, /*InsnID*/0,
11951      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11952      // GIR_Coverage, 5406,
11953      GIR_Done,
11954    // Label 687: @28875
11955    GIM_Try, /*On fail goto*//*Label 688*/ 28909, // Rule ID 5407 //
11956      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11957      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11958      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11959      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11960      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)  =>  MQPR:{ *:[v4i32] }:$src
11961      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11962      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11963      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11964      GIR_EraseFromParent, /*InsnID*/0,
11965      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11966      // GIR_Coverage, 5407,
11967      GIR_Done,
11968    // Label 688: @28909
11969    GIM_Try, /*On fail goto*//*Label 689*/ 28943, // Rule ID 5408 //
11970      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11971      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11972      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11973      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11974      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src)  =>  MQPR:{ *:[v4i32] }:$src
11975      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11976      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11977      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11978      GIR_EraseFromParent, /*InsnID*/0,
11979      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11980      // GIR_Coverage, 5408,
11981      GIR_Done,
11982    // Label 689: @28943
11983    GIM_Try, /*On fail goto*//*Label 690*/ 29000, // Rule ID 5435 //
11984      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11985      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11986      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11987      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11988      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src)  =>  (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src)
11989      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11990      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11991      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11992      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
11993      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11994      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11995      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11996      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11997      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11998      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11999      GIR_EraseFromParent, /*InsnID*/0,
12000      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12001      // GIR_Coverage, 5435,
12002      GIR_Done,
12003    // Label 690: @29000
12004    GIM_Try, /*On fail goto*//*Label 691*/ 29057, // Rule ID 5436 //
12005      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
12006      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12007      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12008      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12009      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src)  =>  (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src)
12010      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12011      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12012      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
12013      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
12014      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
12015      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12016      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12017      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12018      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12019      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12020      GIR_EraseFromParent, /*InsnID*/0,
12021      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12022      // GIR_Coverage, 5436,
12023      GIR_Done,
12024    // Label 691: @29057
12025    GIM_Try, /*On fail goto*//*Label 692*/ 29114, // Rule ID 5437 //
12026      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
12027      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12028      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12029      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12030      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src)
12031      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12032      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12033      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
12034      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
12035      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
12036      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12037      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12038      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12039      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12040      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12041      GIR_EraseFromParent, /*InsnID*/0,
12042      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12043      // GIR_Coverage, 5437,
12044      GIR_Done,
12045    // Label 692: @29114
12046    GIM_Try, /*On fail goto*//*Label 693*/ 29171, // Rule ID 5438 //
12047      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
12048      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12049      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12050      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12051      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src)
12052      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12053      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12054      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
12055      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
12056      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
12057      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12058      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12059      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12060      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12061      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12062      GIR_EraseFromParent, /*InsnID*/0,
12063      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12064      // GIR_Coverage, 5438,
12065      GIR_Done,
12066    // Label 693: @29171
12067    GIM_Try, /*On fail goto*//*Label 694*/ 29228, // Rule ID 5439 //
12068      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
12069      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12070      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12071      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12072      // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src)  =>  (MVE_VREV32_8:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src)
12073      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12074      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12075      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
12076      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8,
12077      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
12078      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12079      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12080      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12081      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12082      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12083      GIR_EraseFromParent, /*InsnID*/0,
12084      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12085      // GIR_Coverage, 5439,
12086      GIR_Done,
12087    // Label 694: @29228
12088    GIM_Try, /*On fail goto*//*Label 695*/ 29285, // Rule ID 5440 //
12089      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
12090      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12091      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12092      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12093      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src)  =>  (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src)
12094      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12095      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12096      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
12097      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
12098      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
12099      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12100      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12101      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12102      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12103      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12104      GIR_EraseFromParent, /*InsnID*/0,
12105      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12106      // GIR_Coverage, 5440,
12107      GIR_Done,
12108    // Label 695: @29285
12109    GIM_Try, /*On fail goto*//*Label 696*/ 29342, // Rule ID 5441 //
12110      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
12111      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12112      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12113      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12114      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src)  =>  (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src)
12115      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12116      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12117      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
12118      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
12119      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
12120      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12121      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12122      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12123      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12124      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12125      GIR_EraseFromParent, /*InsnID*/0,
12126      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12127      // GIR_Coverage, 5441,
12128      GIR_Done,
12129    // Label 696: @29342
12130    GIM_Try, /*On fail goto*//*Label 697*/ 29399, // Rule ID 5442 //
12131      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
12132      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12133      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12134      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12135      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src)
12136      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12137      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12138      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
12139      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
12140      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
12141      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12142      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12143      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12144      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12145      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12146      GIR_EraseFromParent, /*InsnID*/0,
12147      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12148      // GIR_Coverage, 5442,
12149      GIR_Done,
12150    // Label 697: @29399
12151    GIM_Try, /*On fail goto*//*Label 698*/ 29456, // Rule ID 5443 //
12152      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
12153      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12154      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12155      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12156      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
12157      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12158      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12159      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
12160      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
12161      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
12162      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12163      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12164      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12165      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12166      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12167      GIR_EraseFromParent, /*InsnID*/0,
12168      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12169      // GIR_Coverage, 5443,
12170      GIR_Done,
12171    // Label 698: @29456
12172    GIM_Try, /*On fail goto*//*Label 699*/ 29513, // Rule ID 5444 //
12173      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
12174      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12175      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12176      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12177      // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src)  =>  (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src)
12178      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12179      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12180      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
12181      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8,
12182      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
12183      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12184      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12185      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12186      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12187      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12188      GIR_EraseFromParent, /*InsnID*/0,
12189      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12190      // GIR_Coverage, 5444,
12191      GIR_Done,
12192    // Label 699: @29513
12193    GIM_Reject,
12194    // Label 510: @29514
12195    GIM_Try, /*On fail goto*//*Label 700*/ 29548, // Rule ID 2790 //
12196      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12197      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
12198      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12199      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
12200      // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v8i8] }:$src
12201      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12202      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12203      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12204      GIR_EraseFromParent, /*InsnID*/0,
12205      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
12206      // GIR_Coverage, 2790,
12207      GIR_Done,
12208    // Label 700: @29548
12209    GIM_Try, /*On fail goto*//*Label 701*/ 29582, // Rule ID 2791 //
12210      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12211      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
12212      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12213      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
12214      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[v8i8] }:$src
12215      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12216      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12217      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12218      GIR_EraseFromParent, /*InsnID*/0,
12219      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
12220      // GIR_Coverage, 2791,
12221      GIR_Done,
12222    // Label 701: @29582
12223    GIM_Try, /*On fail goto*//*Label 702*/ 29616, // Rule ID 2792 //
12224      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12225      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
12226      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12227      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
12228      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[v8i8] }:$src
12229      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12230      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12231      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12232      GIR_EraseFromParent, /*InsnID*/0,
12233      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
12234      // GIR_Coverage, 2792,
12235      GIR_Done,
12236    // Label 702: @29616
12237    GIM_Try, /*On fail goto*//*Label 703*/ 29650, // Rule ID 2793 //
12238      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12239      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
12240      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12241      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
12242      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[v8i8] }:$src
12243      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12244      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12245      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12246      GIR_EraseFromParent, /*InsnID*/0,
12247      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
12248      // GIR_Coverage, 2793,
12249      GIR_Done,
12250    // Label 703: @29650
12251    GIM_Try, /*On fail goto*//*Label 704*/ 29684, // Rule ID 2794 //
12252      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12253      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
12254      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12255      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
12256      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src)  =>  DPR:{ *:[v8i8] }:$src
12257      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12258      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12259      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12260      GIR_EraseFromParent, /*InsnID*/0,
12261      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
12262      // GIR_Coverage, 2794,
12263      GIR_Done,
12264    // Label 704: @29684
12265    GIM_Try, /*On fail goto*//*Label 705*/ 29718, // Rule ID 2795 //
12266      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12267      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
12268      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12269      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
12270      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4bf16] }:$src)  =>  DPR:{ *:[v8i8] }:$src
12271      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12272      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12273      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12274      GIR_EraseFromParent, /*InsnID*/0,
12275      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
12276      // GIR_Coverage, 2795,
12277      GIR_Done,
12278    // Label 705: @29718
12279    GIM_Try, /*On fail goto*//*Label 706*/ 29752, // Rule ID 2796 //
12280      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12281      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
12282      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12283      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
12284      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[v8i8] }:$src
12285      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12286      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12287      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12288      GIR_EraseFromParent, /*InsnID*/0,
12289      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
12290      // GIR_Coverage, 2796,
12291      GIR_Done,
12292    // Label 706: @29752
12293    GIM_Try, /*On fail goto*//*Label 707*/ 29791, // Rule ID 2882 //
12294      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12295      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
12296      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12297      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
12298      // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src)  =>  (VREV64d8:{ *:[v8i8] } DPR:{ *:[f64] }:$src)
12299      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8,
12300      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12301      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12302      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12303      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12304      GIR_EraseFromParent, /*InsnID*/0,
12305      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12306      // GIR_Coverage, 2882,
12307      GIR_Done,
12308    // Label 707: @29791
12309    GIM_Try, /*On fail goto*//*Label 708*/ 29830, // Rule ID 2883 //
12310      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12311      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
12312      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12313      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
12314      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src)  =>  (VREV64d8:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src)
12315      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8,
12316      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12317      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12318      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12319      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12320      GIR_EraseFromParent, /*InsnID*/0,
12321      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12322      // GIR_Coverage, 2883,
12323      GIR_Done,
12324    // Label 708: @29830
12325    GIM_Try, /*On fail goto*//*Label 709*/ 29869, // Rule ID 2884 //
12326      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12327      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
12328      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12329      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
12330      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src)  =>  (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src)
12331      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8,
12332      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12333      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12334      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12335      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12336      GIR_EraseFromParent, /*InsnID*/0,
12337      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12338      // GIR_Coverage, 2884,
12339      GIR_Done,
12340    // Label 709: @29869
12341    GIM_Try, /*On fail goto*//*Label 710*/ 29908, // Rule ID 2885 //
12342      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12343      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
12344      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12345      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
12346      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src)  =>  (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src)
12347      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8,
12348      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12349      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12350      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12351      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12352      GIR_EraseFromParent, /*InsnID*/0,
12353      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12354      // GIR_Coverage, 2885,
12355      GIR_Done,
12356    // Label 710: @29908
12357    GIM_Try, /*On fail goto*//*Label 711*/ 29947, // Rule ID 2886 //
12358      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12359      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
12360      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12361      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
12362      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src)  =>  (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src)
12363      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8,
12364      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12365      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12366      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12367      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12368      GIR_EraseFromParent, /*InsnID*/0,
12369      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12370      // GIR_Coverage, 2886,
12371      GIR_Done,
12372    // Label 711: @29947
12373    GIM_Try, /*On fail goto*//*Label 712*/ 29986, // Rule ID 2887 //
12374      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12375      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
12376      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12377      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
12378      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4bf16] }:$src)  =>  (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4bf16] }:$src)
12379      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8,
12380      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12381      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12382      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12383      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12384      GIR_EraseFromParent, /*InsnID*/0,
12385      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12386      // GIR_Coverage, 2887,
12387      GIR_Done,
12388    // Label 712: @29986
12389    GIM_Try, /*On fail goto*//*Label 713*/ 30025, // Rule ID 2888 //
12390      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12391      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
12392      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
12393      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
12394      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src)  =>  (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src)
12395      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8,
12396      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12397      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12398      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12399      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12400      GIR_EraseFromParent, /*InsnID*/0,
12401      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12402      // GIR_Coverage, 2888,
12403      GIR_Done,
12404    // Label 713: @30025
12405    GIM_Reject,
12406    // Label 511: @30026
12407    GIM_Try, /*On fail goto*//*Label 714*/ 30060, // Rule ID 2747 //
12408      GIM_CheckFeatures, GIFBS_HasNEON,
12409      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12410      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12411      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12412      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v8f16] }:$src)  =>  QPR:{ *:[v8i16] }:$src
12413      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12414      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12415      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12416      GIR_EraseFromParent, /*InsnID*/0,
12417      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12418      // GIR_Coverage, 2747,
12419      GIR_Done,
12420    // Label 714: @30060
12421    GIM_Try, /*On fail goto*//*Label 715*/ 30094, // Rule ID 2748 //
12422      GIM_CheckFeatures, GIFBS_HasNEON,
12423      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12424      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12425      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12426      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v8f16] }:$src
12427      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12428      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12429      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12430      GIR_EraseFromParent, /*InsnID*/0,
12431      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12432      // GIR_Coverage, 2748,
12433      GIR_Done,
12434    // Label 715: @30094
12435    GIM_Try, /*On fail goto*//*Label 716*/ 30128, // Rule ID 2749 //
12436      GIM_CheckFeatures, GIFBS_HasNEON,
12437      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12438      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12439      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12440      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v8bf16] }:$src)  =>  QPR:{ *:[v8i16] }:$src
12441      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12442      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12443      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12444      GIR_EraseFromParent, /*InsnID*/0,
12445      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12446      // GIR_Coverage, 2749,
12447      GIR_Done,
12448    // Label 716: @30128
12449    GIM_Try, /*On fail goto*//*Label 717*/ 30162, // Rule ID 2750 //
12450      GIM_CheckFeatures, GIFBS_HasNEON,
12451      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12452      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12453      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12454      // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v8bf16] }:$src
12455      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12456      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12457      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12458      GIR_EraseFromParent, /*InsnID*/0,
12459      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12460      // GIR_Coverage, 2750,
12461      GIR_Done,
12462    // Label 717: @30162
12463    GIM_Try, /*On fail goto*//*Label 718*/ 30196, // Rule ID 2821 //
12464      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12465      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12466      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12467      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12468      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v8f16] }:$src
12469      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12470      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12471      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12472      GIR_EraseFromParent, /*InsnID*/0,
12473      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12474      // GIR_Coverage, 2821,
12475      GIR_Done,
12476    // Label 718: @30196
12477    GIM_Try, /*On fail goto*//*Label 719*/ 30230, // Rule ID 2822 //
12478      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12479      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12480      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12481      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12482      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v8f16] }:$src
12483      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12484      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12485      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12486      GIR_EraseFromParent, /*InsnID*/0,
12487      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12488      // GIR_Coverage, 2822,
12489      GIR_Done,
12490    // Label 719: @30230
12491    GIM_Try, /*On fail goto*//*Label 720*/ 30264, // Rule ID 2823 //
12492      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12493      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12494      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12495      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12496      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v8f16] }:$src
12497      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12498      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12499      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12500      GIR_EraseFromParent, /*InsnID*/0,
12501      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12502      // GIR_Coverage, 2823,
12503      GIR_Done,
12504    // Label 720: @30264
12505    GIM_Try, /*On fail goto*//*Label 721*/ 30298, // Rule ID 2824 //
12506      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12507      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12508      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12509      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12510      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v8f16] }:$src
12511      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12512      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12513      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12514      GIR_EraseFromParent, /*InsnID*/0,
12515      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12516      // GIR_Coverage, 2824,
12517      GIR_Done,
12518    // Label 721: @30298
12519    GIM_Try, /*On fail goto*//*Label 722*/ 30332, // Rule ID 2825 //
12520      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12521      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12522      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12523      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12524      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v8f16] }:$src
12525      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12526      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12527      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12528      GIR_EraseFromParent, /*InsnID*/0,
12529      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12530      // GIR_Coverage, 2825,
12531      GIR_Done,
12532    // Label 722: @30332
12533    GIM_Try, /*On fail goto*//*Label 723*/ 30366, // Rule ID 2826 //
12534      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12535      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12536      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12537      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12538      // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v8bf16] }:$src
12539      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12540      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12541      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12542      GIR_EraseFromParent, /*InsnID*/0,
12543      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12544      // GIR_Coverage, 2826,
12545      GIR_Done,
12546    // Label 723: @30366
12547    GIM_Try, /*On fail goto*//*Label 724*/ 30400, // Rule ID 2827 //
12548      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12549      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12550      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12551      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12552      // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v8bf16] }:$src
12553      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12554      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12555      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12556      GIR_EraseFromParent, /*InsnID*/0,
12557      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12558      // GIR_Coverage, 2827,
12559      GIR_Done,
12560    // Label 724: @30400
12561    GIM_Try, /*On fail goto*//*Label 725*/ 30434, // Rule ID 2828 //
12562      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12563      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12564      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12565      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12566      // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v8bf16] }:$src
12567      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12568      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12569      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12570      GIR_EraseFromParent, /*InsnID*/0,
12571      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12572      // GIR_Coverage, 2828,
12573      GIR_Done,
12574    // Label 725: @30434
12575    GIM_Try, /*On fail goto*//*Label 726*/ 30468, // Rule ID 2829 //
12576      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12577      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12578      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12579      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12580      // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v8bf16] }:$src
12581      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12582      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12583      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12584      GIR_EraseFromParent, /*InsnID*/0,
12585      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12586      // GIR_Coverage, 2829,
12587      GIR_Done,
12588    // Label 726: @30468
12589    GIM_Try, /*On fail goto*//*Label 727*/ 30502, // Rule ID 2830 //
12590      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12591      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12592      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12593      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12594      // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v8bf16] }:$src
12595      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12596      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12597      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12598      GIR_EraseFromParent, /*InsnID*/0,
12599      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12600      // GIR_Coverage, 2830,
12601      GIR_Done,
12602    // Label 727: @30502
12603    GIM_Try, /*On fail goto*//*Label 728*/ 30536, // Rule ID 2831 //
12604      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12605      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12606      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12607      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12608      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v8i16] }:$src
12609      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12610      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12611      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12612      GIR_EraseFromParent, /*InsnID*/0,
12613      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12614      // GIR_Coverage, 2831,
12615      GIR_Done,
12616    // Label 728: @30536
12617    GIM_Try, /*On fail goto*//*Label 729*/ 30570, // Rule ID 2832 //
12618      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12619      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12620      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12621      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12622      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v8i16] }:$src
12623      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12624      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12625      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12626      GIR_EraseFromParent, /*InsnID*/0,
12627      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12628      // GIR_Coverage, 2832,
12629      GIR_Done,
12630    // Label 729: @30570
12631    GIM_Try, /*On fail goto*//*Label 730*/ 30604, // Rule ID 2833 //
12632      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12633      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12634      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12635      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12636      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v8i16] }:$src
12637      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12638      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12639      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12640      GIR_EraseFromParent, /*InsnID*/0,
12641      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12642      // GIR_Coverage, 2833,
12643      GIR_Done,
12644    // Label 730: @30604
12645    GIM_Try, /*On fail goto*//*Label 731*/ 30638, // Rule ID 2834 //
12646      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12647      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12648      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12649      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12650      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v8i16] }:$src
12651      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12652      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12653      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12654      GIR_EraseFromParent, /*InsnID*/0,
12655      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12656      // GIR_Coverage, 2834,
12657      GIR_Done,
12658    // Label 731: @30638
12659    GIM_Try, /*On fail goto*//*Label 732*/ 30672, // Rule ID 2835 //
12660      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12661      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12662      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12663      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12664      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v8i16] }:$src
12665      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12666      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12667      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12668      GIR_EraseFromParent, /*InsnID*/0,
12669      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12670      // GIR_Coverage, 2835,
12671      GIR_Done,
12672    // Label 732: @30672
12673    GIM_Try, /*On fail goto*//*Label 733*/ 30711, // Rule ID 2913 //
12674      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12675      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12676      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12677      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12678      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src)  =>  (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src)
12679      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
12680      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12681      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12682      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12683      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12684      GIR_EraseFromParent, /*InsnID*/0,
12685      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12686      // GIR_Coverage, 2913,
12687      GIR_Done,
12688    // Label 733: @30711
12689    GIM_Try, /*On fail goto*//*Label 734*/ 30750, // Rule ID 2914 //
12690      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12691      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12692      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12693      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12694      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src)  =>  (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src)
12695      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
12696      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12697      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12698      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12699      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12700      GIR_EraseFromParent, /*InsnID*/0,
12701      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12702      // GIR_Coverage, 2914,
12703      GIR_Done,
12704    // Label 734: @30750
12705    GIM_Try, /*On fail goto*//*Label 735*/ 30789, // Rule ID 2915 //
12706      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12707      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12708      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12709      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12710      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src)  =>  (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src)
12711      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
12712      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12713      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12714      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12715      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12716      GIR_EraseFromParent, /*InsnID*/0,
12717      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12718      // GIR_Coverage, 2915,
12719      GIR_Done,
12720    // Label 735: @30789
12721    GIM_Try, /*On fail goto*//*Label 736*/ 30828, // Rule ID 2916 //
12722      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12723      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12724      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12725      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12726      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src)  =>  (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src)
12727      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
12728      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12729      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12730      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12731      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12732      GIR_EraseFromParent, /*InsnID*/0,
12733      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12734      // GIR_Coverage, 2916,
12735      GIR_Done,
12736    // Label 736: @30828
12737    GIM_Try, /*On fail goto*//*Label 737*/ 30867, // Rule ID 2917 //
12738      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12739      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12740      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12741      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12742      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src)  =>  (VREV16q8:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src)
12743      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8,
12744      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12745      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12746      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12747      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12748      GIR_EraseFromParent, /*InsnID*/0,
12749      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12750      // GIR_Coverage, 2917,
12751      GIR_Done,
12752    // Label 737: @30867
12753    GIM_Try, /*On fail goto*//*Label 738*/ 30906, // Rule ID 2918 //
12754      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12755      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12756      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12757      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12758      // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v2f64] }:$src)  =>  (VREV64q16:{ *:[v8bf16] } QPR:{ *:[v2f64] }:$src)
12759      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
12760      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12761      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12762      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12763      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12764      GIR_EraseFromParent, /*InsnID*/0,
12765      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12766      // GIR_Coverage, 2918,
12767      GIR_Done,
12768    // Label 738: @30906
12769    GIM_Try, /*On fail goto*//*Label 739*/ 30945, // Rule ID 2919 //
12770      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12771      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12772      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12773      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12774      // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v2i64] }:$src)  =>  (VREV64q16:{ *:[v8bf16] } QPR:{ *:[v2i64] }:$src)
12775      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
12776      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12777      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12778      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12779      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12780      GIR_EraseFromParent, /*InsnID*/0,
12781      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12782      // GIR_Coverage, 2919,
12783      GIR_Done,
12784    // Label 739: @30945
12785    GIM_Try, /*On fail goto*//*Label 740*/ 30984, // Rule ID 2920 //
12786      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12787      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12788      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12789      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12790      // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v4f32] }:$src)  =>  (VREV32q16:{ *:[v8bf16] } QPR:{ *:[v4f32] }:$src)
12791      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
12792      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12793      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12794      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12795      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12796      GIR_EraseFromParent, /*InsnID*/0,
12797      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12798      // GIR_Coverage, 2920,
12799      GIR_Done,
12800    // Label 740: @30984
12801    GIM_Try, /*On fail goto*//*Label 741*/ 31023, // Rule ID 2921 //
12802      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12803      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12804      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12805      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12806      // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v4i32] }:$src)  =>  (VREV32q16:{ *:[v8bf16] } QPR:{ *:[v4i32] }:$src)
12807      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
12808      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12809      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12810      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12811      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12812      GIR_EraseFromParent, /*InsnID*/0,
12813      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12814      // GIR_Coverage, 2921,
12815      GIR_Done,
12816    // Label 741: @31023
12817    GIM_Try, /*On fail goto*//*Label 742*/ 31062, // Rule ID 2922 //
12818      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12819      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12820      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12821      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12822      // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v16i8] }:$src)  =>  (VREV16q8:{ *:[v8bf16] } QPR:{ *:[v16i8] }:$src)
12823      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8,
12824      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12825      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12826      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12827      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12828      GIR_EraseFromParent, /*InsnID*/0,
12829      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12830      // GIR_Coverage, 2922,
12831      GIR_Done,
12832    // Label 742: @31062
12833    GIM_Try, /*On fail goto*//*Label 743*/ 31101, // Rule ID 2923 //
12834      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12835      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12836      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12837      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12838      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src)  =>  (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src)
12839      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
12840      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12841      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12842      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12843      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12844      GIR_EraseFromParent, /*InsnID*/0,
12845      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12846      // GIR_Coverage, 2923,
12847      GIR_Done,
12848    // Label 743: @31101
12849    GIM_Try, /*On fail goto*//*Label 744*/ 31140, // Rule ID 2924 //
12850      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12851      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12852      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12853      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12854      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src)  =>  (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src)
12855      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
12856      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12857      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12858      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12859      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12860      GIR_EraseFromParent, /*InsnID*/0,
12861      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12862      // GIR_Coverage, 2924,
12863      GIR_Done,
12864    // Label 744: @31140
12865    GIM_Try, /*On fail goto*//*Label 745*/ 31179, // Rule ID 2925 //
12866      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12867      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12868      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12869      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12870      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src)  =>  (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src)
12871      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
12872      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12873      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12874      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12875      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12876      GIR_EraseFromParent, /*InsnID*/0,
12877      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12878      // GIR_Coverage, 2925,
12879      GIR_Done,
12880    // Label 745: @31179
12881    GIM_Try, /*On fail goto*//*Label 746*/ 31218, // Rule ID 2926 //
12882      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12883      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12884      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12885      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12886      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src)  =>  (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src)
12887      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
12888      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12889      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12890      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12891      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12892      GIR_EraseFromParent, /*InsnID*/0,
12893      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12894      // GIR_Coverage, 2926,
12895      GIR_Done,
12896    // Label 746: @31218
12897    GIM_Try, /*On fail goto*//*Label 747*/ 31257, // Rule ID 2927 //
12898      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12899      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12900      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12901      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12902      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src)  =>  (VREV16q8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src)
12903      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8,
12904      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12905      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12906      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12907      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12908      GIR_EraseFromParent, /*InsnID*/0,
12909      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12910      // GIR_Coverage, 2927,
12911      GIR_Done,
12912    // Label 747: @31257
12913    GIM_Try, /*On fail goto*//*Label 748*/ 31291, // Rule ID 5387 //
12914      GIM_CheckFeatures, GIFBS_HasMVEInt,
12915      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12916      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12917      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12918      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)  =>  MQPR:{ *:[v8i16] }:$src
12919      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12920      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12921      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12922      GIR_EraseFromParent, /*InsnID*/0,
12923      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
12924      // GIR_Coverage, 5387,
12925      GIR_Done,
12926    // Label 748: @31291
12927    GIM_Try, /*On fail goto*//*Label 749*/ 31325, // Rule ID 5388 //
12928      GIM_CheckFeatures, GIFBS_HasMVEInt,
12929      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12930      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12931      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12932      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)  =>  MQPR:{ *:[v8f16] }:$src
12933      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12934      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12935      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12936      GIR_EraseFromParent, /*InsnID*/0,
12937      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
12938      // GIR_Coverage, 5388,
12939      GIR_Done,
12940    // Label 749: @31325
12941    GIM_Try, /*On fail goto*//*Label 750*/ 31359, // Rule ID 5409 //
12942      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
12943      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12944      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12945      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12946      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src)  =>  MQPR:{ *:[v8f16] }:$src
12947      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12948      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12949      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12950      GIR_EraseFromParent, /*InsnID*/0,
12951      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
12952      // GIR_Coverage, 5409,
12953      GIR_Done,
12954    // Label 750: @31359
12955    GIM_Try, /*On fail goto*//*Label 751*/ 31393, // Rule ID 5410 //
12956      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
12957      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12958      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12959      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12960      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src)  =>  MQPR:{ *:[v8f16] }:$src
12961      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12962      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12963      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12964      GIR_EraseFromParent, /*InsnID*/0,
12965      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
12966      // GIR_Coverage, 5410,
12967      GIR_Done,
12968    // Label 751: @31393
12969    GIM_Try, /*On fail goto*//*Label 752*/ 31427, // Rule ID 5411 //
12970      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
12971      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12972      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12973      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12974      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src)  =>  MQPR:{ *:[v8f16] }:$src
12975      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12976      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12977      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12978      GIR_EraseFromParent, /*InsnID*/0,
12979      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
12980      // GIR_Coverage, 5411,
12981      GIR_Done,
12982    // Label 752: @31427
12983    GIM_Try, /*On fail goto*//*Label 753*/ 31461, // Rule ID 5412 //
12984      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
12985      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12986      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12987      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12988      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src)  =>  MQPR:{ *:[v8f16] }:$src
12989      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12990      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12991      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12992      GIR_EraseFromParent, /*InsnID*/0,
12993      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
12994      // GIR_Coverage, 5412,
12995      GIR_Done,
12996    // Label 753: @31461
12997    GIM_Try, /*On fail goto*//*Label 754*/ 31495, // Rule ID 5413 //
12998      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
12999      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
13000      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13001      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13002      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src)  =>  MQPR:{ *:[v8f16] }:$src
13003      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13004      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13005      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13006      GIR_EraseFromParent, /*InsnID*/0,
13007      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
13008      // GIR_Coverage, 5413,
13009      GIR_Done,
13010    // Label 754: @31495
13011    GIM_Try, /*On fail goto*//*Label 755*/ 31529, // Rule ID 5414 //
13012      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
13013      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13014      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13015      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13016      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src)  =>  MQPR:{ *:[v8i16] }:$src
13017      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13018      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13019      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13020      GIR_EraseFromParent, /*InsnID*/0,
13021      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
13022      // GIR_Coverage, 5414,
13023      GIR_Done,
13024    // Label 755: @31529
13025    GIM_Try, /*On fail goto*//*Label 756*/ 31563, // Rule ID 5415 //
13026      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
13027      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13028      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13029      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13030      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src)  =>  MQPR:{ *:[v8i16] }:$src
13031      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13032      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13033      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13034      GIR_EraseFromParent, /*InsnID*/0,
13035      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
13036      // GIR_Coverage, 5415,
13037      GIR_Done,
13038    // Label 756: @31563
13039    GIM_Try, /*On fail goto*//*Label 757*/ 31597, // Rule ID 5416 //
13040      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
13041      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13042      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13043      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13044      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src)  =>  MQPR:{ *:[v8i16] }:$src
13045      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13046      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13047      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13048      GIR_EraseFromParent, /*InsnID*/0,
13049      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
13050      // GIR_Coverage, 5416,
13051      GIR_Done,
13052    // Label 757: @31597
13053    GIM_Try, /*On fail goto*//*Label 758*/ 31631, // Rule ID 5417 //
13054      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
13055      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13056      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13057      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13058      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src)  =>  MQPR:{ *:[v8i16] }:$src
13059      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13060      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13061      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13062      GIR_EraseFromParent, /*InsnID*/0,
13063      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
13064      // GIR_Coverage, 5417,
13065      GIR_Done,
13066    // Label 758: @31631
13067    GIM_Try, /*On fail goto*//*Label 759*/ 31665, // Rule ID 5418 //
13068      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
13069      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
13070      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13071      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13072      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)  =>  MQPR:{ *:[v8i16] }:$src
13073      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13074      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13075      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13076      GIR_EraseFromParent, /*InsnID*/0,
13077      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
13078      // GIR_Coverage, 5418,
13079      GIR_Done,
13080    // Label 759: @31665
13081    GIM_Try, /*On fail goto*//*Label 760*/ 31722, // Rule ID 5445 //
13082      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
13083      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13084      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13085      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13086      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src)  =>  (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src)
13087      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13088      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13089      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13090      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
13091      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13092      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13093      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13094      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13095      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13096      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13097      GIR_EraseFromParent, /*InsnID*/0,
13098      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13099      // GIR_Coverage, 5445,
13100      GIR_Done,
13101    // Label 760: @31722
13102    GIM_Try, /*On fail goto*//*Label 761*/ 31779, // Rule ID 5446 //
13103      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
13104      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13105      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13106      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13107      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src)  =>  (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src)
13108      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13109      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13110      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13111      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
13112      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13113      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13114      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13115      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13116      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13117      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13118      GIR_EraseFromParent, /*InsnID*/0,
13119      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13120      // GIR_Coverage, 5446,
13121      GIR_Done,
13122    // Label 761: @31779
13123    GIM_Try, /*On fail goto*//*Label 762*/ 31836, // Rule ID 5447 //
13124      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
13125      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13126      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13127      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13128      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src)
13129      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13130      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13131      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13132      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
13133      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13134      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13135      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13136      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13137      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13138      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13139      GIR_EraseFromParent, /*InsnID*/0,
13140      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13141      // GIR_Coverage, 5447,
13142      GIR_Done,
13143    // Label 762: @31836
13144    GIM_Try, /*On fail goto*//*Label 763*/ 31893, // Rule ID 5448 //
13145      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
13146      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13147      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13148      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13149      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src)
13150      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13151      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13152      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13153      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
13154      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13155      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13156      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13157      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13158      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13159      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13160      GIR_EraseFromParent, /*InsnID*/0,
13161      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13162      // GIR_Coverage, 5448,
13163      GIR_Done,
13164    // Label 763: @31893
13165    GIM_Try, /*On fail goto*//*Label 764*/ 31950, // Rule ID 5449 //
13166      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
13167      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
13168      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13169      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13170      // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src)  =>  (MVE_VREV16_8:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src)
13171      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13172      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13173      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13174      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8,
13175      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13176      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13177      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13178      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13179      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13180      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13181      GIR_EraseFromParent, /*InsnID*/0,
13182      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13183      // GIR_Coverage, 5449,
13184      GIR_Done,
13185    // Label 764: @31950
13186    GIM_Try, /*On fail goto*//*Label 765*/ 32007, // Rule ID 5450 //
13187      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
13188      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13189      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13190      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13191      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src)  =>  (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src)
13192      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13193      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13194      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13195      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
13196      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13197      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13198      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13199      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13200      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13201      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13202      GIR_EraseFromParent, /*InsnID*/0,
13203      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13204      // GIR_Coverage, 5450,
13205      GIR_Done,
13206    // Label 765: @32007
13207    GIM_Try, /*On fail goto*//*Label 766*/ 32064, // Rule ID 5451 //
13208      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
13209      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13210      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13211      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13212      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src)  =>  (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src)
13213      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13214      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13215      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13216      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
13217      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13218      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13219      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13220      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13221      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13222      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13223      GIR_EraseFromParent, /*InsnID*/0,
13224      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13225      // GIR_Coverage, 5451,
13226      GIR_Done,
13227    // Label 766: @32064
13228    GIM_Try, /*On fail goto*//*Label 767*/ 32121, // Rule ID 5452 //
13229      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
13230      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13231      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13232      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13233      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src)
13234      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13235      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13236      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13237      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
13238      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13239      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13240      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13241      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13242      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13243      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13244      GIR_EraseFromParent, /*InsnID*/0,
13245      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13246      // GIR_Coverage, 5452,
13247      GIR_Done,
13248    // Label 767: @32121
13249    GIM_Try, /*On fail goto*//*Label 768*/ 32178, // Rule ID 5453 //
13250      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
13251      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13252      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13253      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13254      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src)
13255      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13256      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13257      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13258      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
13259      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13260      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13261      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13262      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13263      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13264      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13265      GIR_EraseFromParent, /*InsnID*/0,
13266      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13267      // GIR_Coverage, 5453,
13268      GIR_Done,
13269    // Label 768: @32178
13270    GIM_Try, /*On fail goto*//*Label 769*/ 32235, // Rule ID 5454 //
13271      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
13272      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
13273      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13274      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13275      // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)  =>  (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
13276      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13277      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13278      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13279      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8,
13280      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13281      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13282      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13283      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13284      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13285      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13286      GIR_EraseFromParent, /*InsnID*/0,
13287      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13288      // GIR_Coverage, 5454,
13289      GIR_Done,
13290    // Label 769: @32235
13291    GIM_Reject,
13292    // Label 512: @32236
13293    GIM_Try, /*On fail goto*//*Label 770*/ 32270, // Rule ID 2836 //
13294      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
13295      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13296      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13297      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
13298      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v16i8] }:$src
13299      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13300      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13301      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13302      GIR_EraseFromParent, /*InsnID*/0,
13303      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
13304      // GIR_Coverage, 2836,
13305      GIR_Done,
13306    // Label 770: @32270
13307    GIM_Try, /*On fail goto*//*Label 771*/ 32304, // Rule ID 2837 //
13308      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
13309      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13310      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13311      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
13312      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v16i8] }:$src
13313      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13314      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13315      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13316      GIR_EraseFromParent, /*InsnID*/0,
13317      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
13318      // GIR_Coverage, 2837,
13319      GIR_Done,
13320    // Label 771: @32304
13321    GIM_Try, /*On fail goto*//*Label 772*/ 32338, // Rule ID 2838 //
13322      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
13323      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13324      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13325      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
13326      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v16i8] }:$src
13327      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13328      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13329      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13330      GIR_EraseFromParent, /*InsnID*/0,
13331      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
13332      // GIR_Coverage, 2838,
13333      GIR_Done,
13334    // Label 772: @32338
13335    GIM_Try, /*On fail goto*//*Label 773*/ 32372, // Rule ID 2839 //
13336      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
13337      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13338      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13339      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
13340      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v16i8] }:$src
13341      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13342      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13343      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13344      GIR_EraseFromParent, /*InsnID*/0,
13345      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
13346      // GIR_Coverage, 2839,
13347      GIR_Done,
13348    // Label 773: @32372
13349    GIM_Try, /*On fail goto*//*Label 774*/ 32406, // Rule ID 2840 //
13350      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
13351      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13352      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13353      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
13354      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src)  =>  QPR:{ *:[v16i8] }:$src
13355      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13356      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13357      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13358      GIR_EraseFromParent, /*InsnID*/0,
13359      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
13360      // GIR_Coverage, 2840,
13361      GIR_Done,
13362    // Label 774: @32406
13363    GIM_Try, /*On fail goto*//*Label 775*/ 32440, // Rule ID 2841 //
13364      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
13365      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13366      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13367      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
13368      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8bf16] }:$src)  =>  QPR:{ *:[v16i8] }:$src
13369      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13370      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13371      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13372      GIR_EraseFromParent, /*InsnID*/0,
13373      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
13374      // GIR_Coverage, 2841,
13375      GIR_Done,
13376    // Label 775: @32440
13377    GIM_Try, /*On fail goto*//*Label 776*/ 32474, // Rule ID 2842 //
13378      GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
13379      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13380      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13381      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
13382      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v16i8] }:$src
13383      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13384      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13385      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13386      GIR_EraseFromParent, /*InsnID*/0,
13387      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
13388      // GIR_Coverage, 2842,
13389      GIR_Done,
13390    // Label 776: @32474
13391    GIM_Try, /*On fail goto*//*Label 777*/ 32513, // Rule ID 2928 //
13392      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
13393      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13394      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13395      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
13396      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src)  =>  (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src)
13397      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8,
13398      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13399      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13400      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13401      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13402      GIR_EraseFromParent, /*InsnID*/0,
13403      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13404      // GIR_Coverage, 2928,
13405      GIR_Done,
13406    // Label 777: @32513
13407    GIM_Try, /*On fail goto*//*Label 778*/ 32552, // Rule ID 2929 //
13408      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
13409      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13410      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13411      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
13412      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src)  =>  (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src)
13413      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8,
13414      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13415      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13416      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13417      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13418      GIR_EraseFromParent, /*InsnID*/0,
13419      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13420      // GIR_Coverage, 2929,
13421      GIR_Done,
13422    // Label 778: @32552
13423    GIM_Try, /*On fail goto*//*Label 779*/ 32591, // Rule ID 2930 //
13424      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
13425      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13426      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13427      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
13428      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src)  =>  (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src)
13429      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8,
13430      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13431      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13432      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13433      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13434      GIR_EraseFromParent, /*InsnID*/0,
13435      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13436      // GIR_Coverage, 2930,
13437      GIR_Done,
13438    // Label 779: @32591
13439    GIM_Try, /*On fail goto*//*Label 780*/ 32630, // Rule ID 2931 //
13440      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
13441      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13442      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13443      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
13444      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src)  =>  (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src)
13445      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8,
13446      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13447      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13448      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13449      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13450      GIR_EraseFromParent, /*InsnID*/0,
13451      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13452      // GIR_Coverage, 2931,
13453      GIR_Done,
13454    // Label 780: @32630
13455    GIM_Try, /*On fail goto*//*Label 781*/ 32669, // Rule ID 2932 //
13456      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
13457      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13458      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13459      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
13460      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src)  =>  (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src)
13461      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8,
13462      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13463      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13464      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13465      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13466      GIR_EraseFromParent, /*InsnID*/0,
13467      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13468      // GIR_Coverage, 2932,
13469      GIR_Done,
13470    // Label 781: @32669
13471    GIM_Try, /*On fail goto*//*Label 782*/ 32708, // Rule ID 2933 //
13472      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
13473      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13474      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13475      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
13476      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8bf16] }:$src)  =>  (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8bf16] }:$src)
13477      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8,
13478      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13479      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13480      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13481      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13482      GIR_EraseFromParent, /*InsnID*/0,
13483      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13484      // GIR_Coverage, 2933,
13485      GIR_Done,
13486    // Label 782: @32708
13487    GIM_Try, /*On fail goto*//*Label 783*/ 32747, // Rule ID 2934 //
13488      GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
13489      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13490      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13491      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
13492      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src)  =>  (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src)
13493      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8,
13494      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13495      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13496      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13497      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13498      GIR_EraseFromParent, /*InsnID*/0,
13499      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13500      // GIR_Coverage, 2934,
13501      GIR_Done,
13502    // Label 783: @32747
13503    GIM_Try, /*On fail goto*//*Label 784*/ 32781, // Rule ID 5419 //
13504      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
13505      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13506      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13507      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13508      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src)  =>  MQPR:{ *:[v16i8] }:$src
13509      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13510      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13511      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13512      GIR_EraseFromParent, /*InsnID*/0,
13513      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
13514      // GIR_Coverage, 5419,
13515      GIR_Done,
13516    // Label 784: @32781
13517    GIM_Try, /*On fail goto*//*Label 785*/ 32815, // Rule ID 5420 //
13518      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
13519      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13520      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13521      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13522      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src)  =>  MQPR:{ *:[v16i8] }:$src
13523      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13524      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13525      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13526      GIR_EraseFromParent, /*InsnID*/0,
13527      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
13528      // GIR_Coverage, 5420,
13529      GIR_Done,
13530    // Label 785: @32815
13531    GIM_Try, /*On fail goto*//*Label 786*/ 32849, // Rule ID 5421 //
13532      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
13533      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13534      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13535      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13536      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src)  =>  MQPR:{ *:[v16i8] }:$src
13537      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13538      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13539      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13540      GIR_EraseFromParent, /*InsnID*/0,
13541      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
13542      // GIR_Coverage, 5421,
13543      GIR_Done,
13544    // Label 786: @32849
13545    GIM_Try, /*On fail goto*//*Label 787*/ 32883, // Rule ID 5422 //
13546      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
13547      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13548      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13549      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13550      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src)  =>  MQPR:{ *:[v16i8] }:$src
13551      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13552      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13553      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13554      GIR_EraseFromParent, /*InsnID*/0,
13555      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
13556      // GIR_Coverage, 5422,
13557      GIR_Done,
13558    // Label 787: @32883
13559    GIM_Try, /*On fail goto*//*Label 788*/ 32917, // Rule ID 5423 //
13560      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
13561      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13562      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13563      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13564      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src)  =>  MQPR:{ *:[v16i8] }:$src
13565      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13566      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13567      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13568      GIR_EraseFromParent, /*InsnID*/0,
13569      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
13570      // GIR_Coverage, 5423,
13571      GIR_Done,
13572    // Label 788: @32917
13573    GIM_Try, /*On fail goto*//*Label 789*/ 32951, // Rule ID 5424 //
13574      GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
13575      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13576      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13577      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13578      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src)  =>  MQPR:{ *:[v16i8] }:$src
13579      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13580      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13581      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13582      GIR_EraseFromParent, /*InsnID*/0,
13583      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
13584      // GIR_Coverage, 5424,
13585      GIR_Done,
13586    // Label 789: @32951
13587    GIM_Try, /*On fail goto*//*Label 790*/ 33008, // Rule ID 5455 //
13588      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
13589      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13590      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13591      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13592      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src)  =>  (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src)
13593      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13594      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13595      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13596      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_8,
13597      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13598      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13599      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13600      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13601      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13602      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13603      GIR_EraseFromParent, /*InsnID*/0,
13604      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13605      // GIR_Coverage, 5455,
13606      GIR_Done,
13607    // Label 790: @33008
13608    GIM_Try, /*On fail goto*//*Label 791*/ 33065, // Rule ID 5456 //
13609      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
13610      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13611      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13612      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13613      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src)  =>  (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src)
13614      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13615      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13616      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13617      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_8,
13618      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13619      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13620      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13621      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13622      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13623      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13624      GIR_EraseFromParent, /*InsnID*/0,
13625      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13626      // GIR_Coverage, 5456,
13627      GIR_Done,
13628    // Label 791: @33065
13629    GIM_Try, /*On fail goto*//*Label 792*/ 33122, // Rule ID 5457 //
13630      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
13631      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13632      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13633      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13634      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src)
13635      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13636      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13637      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13638      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8,
13639      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13640      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13641      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13642      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13643      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13644      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13645      GIR_EraseFromParent, /*InsnID*/0,
13646      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13647      // GIR_Coverage, 5457,
13648      GIR_Done,
13649    // Label 792: @33122
13650    GIM_Try, /*On fail goto*//*Label 793*/ 33179, // Rule ID 5458 //
13651      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
13652      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13653      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13654      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13655      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src)
13656      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13657      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13658      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13659      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8,
13660      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13661      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13662      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13663      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13664      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13665      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13666      GIR_EraseFromParent, /*InsnID*/0,
13667      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13668      // GIR_Coverage, 5458,
13669      GIR_Done,
13670    // Label 793: @33179
13671    GIM_Try, /*On fail goto*//*Label 794*/ 33236, // Rule ID 5459 //
13672      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
13673      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13674      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13675      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13676      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src)
13677      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13678      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13679      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13680      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8,
13681      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13682      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13683      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13684      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13685      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13686      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13687      GIR_EraseFromParent, /*InsnID*/0,
13688      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13689      // GIR_Coverage, 5459,
13690      GIR_Done,
13691    // Label 794: @33236
13692    GIM_Try, /*On fail goto*//*Label 795*/ 33293, // Rule ID 5460 //
13693      GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
13694      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13695      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13696      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13697      // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src)
13698      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13699      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13700      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13701      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8,
13702      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13703      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13704      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13705      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13706      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13707      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13708      GIR_EraseFromParent, /*InsnID*/0,
13709      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13710      // GIR_Coverage, 5460,
13711      GIR_Done,
13712    // Label 795: @33293
13713    GIM_Reject,
13714    // Label 513: @33294
13715    GIM_Reject,
13716    // Label 10: @33295
13717    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 801*/ 33550,
13718    /*GILLT_s16*//*Label 796*/ 33314,
13719    /*GILLT_s32*//*Label 797*/ 33354,
13720    /*GILLT_s64*//*Label 798*/ 33394, 0, 0, 0, 0, 0,
13721    /*GILLT_v4s32*//*Label 799*/ 33434, 0, 0, 0,
13722    /*GILLT_v8s16*//*Label 800*/ 33492,
13723    // Label 796: @33314
13724    GIM_Try, /*On fail goto*//*Label 802*/ 33353, // Rule ID 681 //
13725      GIM_CheckFeatures, GIFBS_HasFullFP16,
13726      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
13727      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
13728      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
13729      // (ftrunc:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VRINTZH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
13730      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZH,
13731      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
13732      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
13733      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13734      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13735      GIR_EraseFromParent, /*InsnID*/0,
13736      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13737      // GIR_Coverage, 681,
13738      GIR_Done,
13739    // Label 802: @33353
13740    GIM_Reject,
13741    // Label 797: @33354
13742    GIM_Try, /*On fail goto*//*Label 803*/ 33393, // Rule ID 682 //
13743      GIM_CheckFeatures, GIFBS_HasFPARMv8,
13744      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13745      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
13746      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
13747      // (ftrunc:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VRINTZS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
13748      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZS,
13749      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
13750      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
13751      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13752      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13753      GIR_EraseFromParent, /*InsnID*/0,
13754      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13755      // GIR_Coverage, 682,
13756      GIR_Done,
13757    // Label 803: @33393
13758    GIM_Reject,
13759    // Label 798: @33394
13760    GIM_Try, /*On fail goto*//*Label 804*/ 33433, // Rule ID 683 //
13761      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
13762      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
13763      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13764      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
13765      // (ftrunc:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VRINTZD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
13766      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZD,
13767      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
13768      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
13769      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13770      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13771      GIR_EraseFromParent, /*InsnID*/0,
13772      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13773      // GIR_Coverage, 683,
13774      GIR_Done,
13775    // Label 804: @33433
13776    GIM_Reject,
13777    // Label 799: @33434
13778    GIM_Try, /*On fail goto*//*Label 805*/ 33491, // Rule ID 4082 //
13779      GIM_CheckFeatures, GIFBS_HasMVEFloat,
13780      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13781      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13782      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13783      // (ftrunc:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)  =>  (MVE_VRINTf32Z:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
13784      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13785      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13786      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13787      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32Z,
13788      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13789      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
13790      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13791      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13792      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13793      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13794      GIR_EraseFromParent, /*InsnID*/0,
13795      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13796      // GIR_Coverage, 4082,
13797      GIR_Done,
13798    // Label 805: @33491
13799    GIM_Reject,
13800    // Label 800: @33492
13801    GIM_Try, /*On fail goto*//*Label 806*/ 33549, // Rule ID 4070 //
13802      GIM_CheckFeatures, GIFBS_HasMVEFloat,
13803      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13804      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13805      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13806      // (ftrunc:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)  =>  (MVE_VRINTf16Z:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
13807      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13808      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13809      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13810      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16Z,
13811      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13812      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
13813      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13814      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13815      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13816      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13817      GIR_EraseFromParent, /*InsnID*/0,
13818      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13819      // GIR_Coverage, 4070,
13820      GIR_Done,
13821    // Label 806: @33549
13822    GIM_Reject,
13823    // Label 801: @33550
13824    GIM_Reject,
13825    // Label 11: @33551
13826    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 812*/ 33758,
13827    /*GILLT_s16*//*Label 807*/ 33570,
13828    /*GILLT_s32*//*Label 808*/ 33594,
13829    /*GILLT_s64*//*Label 809*/ 33618, 0, 0, 0, 0, 0,
13830    /*GILLT_v4s32*//*Label 810*/ 33642, 0, 0, 0,
13831    /*GILLT_v8s16*//*Label 811*/ 33700,
13832    // Label 807: @33570
13833    GIM_Try, /*On fail goto*//*Label 813*/ 33593, // Rule ID 690 //
13834      GIM_CheckFeatures, GIFBS_HasFullFP16,
13835      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
13836      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
13837      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
13838      // (fround:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VRINTAH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
13839      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTAH,
13840      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13841      // GIR_Coverage, 690,
13842      GIR_Done,
13843    // Label 813: @33593
13844    GIM_Reject,
13845    // Label 808: @33594
13846    GIM_Try, /*On fail goto*//*Label 814*/ 33617, // Rule ID 691 //
13847      GIM_CheckFeatures, GIFBS_HasFPARMv8,
13848      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13849      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
13850      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
13851      // (fround:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VRINTAS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
13852      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTAS,
13853      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13854      // GIR_Coverage, 691,
13855      GIR_Done,
13856    // Label 814: @33617
13857    GIM_Reject,
13858    // Label 809: @33618
13859    GIM_Try, /*On fail goto*//*Label 815*/ 33641, // Rule ID 692 //
13860      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
13861      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
13862      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13863      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
13864      // (fround:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VRINTAD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
13865      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTAD,
13866      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13867      // GIR_Coverage, 692,
13868      GIR_Done,
13869    // Label 815: @33641
13870    GIM_Reject,
13871    // Label 810: @33642
13872    GIM_Try, /*On fail goto*//*Label 816*/ 33699, // Rule ID 4080 //
13873      GIM_CheckFeatures, GIFBS_HasMVEFloat,
13874      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13875      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13876      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13877      // (fround:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)  =>  (MVE_VRINTf32A:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
13878      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13879      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13880      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13881      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32A,
13882      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13883      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
13884      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13885      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13886      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13887      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13888      GIR_EraseFromParent, /*InsnID*/0,
13889      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13890      // GIR_Coverage, 4080,
13891      GIR_Done,
13892    // Label 816: @33699
13893    GIM_Reject,
13894    // Label 811: @33700
13895    GIM_Try, /*On fail goto*//*Label 817*/ 33757, // Rule ID 4068 //
13896      GIM_CheckFeatures, GIFBS_HasMVEFloat,
13897      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13898      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13899      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13900      // (fround:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)  =>  (MVE_VRINTf16A:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
13901      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13902      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13903      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13904      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16A,
13905      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13906      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
13907      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13908      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13909      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13910      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13911      GIR_EraseFromParent, /*InsnID*/0,
13912      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13913      // GIR_Coverage, 4068,
13914      GIR_Done,
13915    // Label 817: @33757
13916    GIM_Reject,
13917    // Label 812: @33758
13918    GIM_Reject,
13919    // Label 12: @33759
13920    GIM_Try, /*On fail goto*//*Label 818*/ 33904,
13921      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13922      GIM_Try, /*On fail goto*//*Label 819*/ 33834, // Rule ID 2065 //
13923        GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only,
13924        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
13925        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
13926        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID,
13927        // MIs[0] Rn
13928        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
13929        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::tGPRRegClassID,
13930        // (ld:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>  =>  (tLDRSB:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (tMOVi8:{ *:[i32] } 0:{ *:[i32] }))
13931        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
13932        GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::tMOVi8,
13933        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
13934        GIR_AddImm, /*InsnID*/1, /*Imm*/0,
13935        GIR_AddImm, /*InsnID*/1, /*Imm*/14,
13936        GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13937        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
13938        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tLDRSB,
13939        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
13940        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
13941        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13942        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
13943        GIR_EraseFromParent, /*InsnID*/0,
13944        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13945        // GIR_Coverage, 2065,
13946        GIR_Done,
13947      // Label 819: @33834
13948      GIM_Try, /*On fail goto*//*Label 820*/ 33903, // Rule ID 2066 //
13949        GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only,
13950        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
13951        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
13952        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID,
13953        // MIs[0] Rn
13954        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
13955        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::tGPRRegClassID,
13956        // (ld:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (tLDRSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (tMOVi8:{ *:[i32] } 0:{ *:[i32] }))
13957        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
13958        GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::tMOVi8,
13959        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
13960        GIR_AddImm, /*InsnID*/1, /*Imm*/0,
13961        GIR_AddImm, /*InsnID*/1, /*Imm*/14,
13962        GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13963        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
13964        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tLDRSH,
13965        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
13966        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
13967        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13968        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
13969        GIR_EraseFromParent, /*InsnID*/0,
13970        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13971        // GIR_Coverage, 2066,
13972        GIR_Done,
13973      // Label 820: @33903
13974      GIM_Reject,
13975    // Label 818: @33904
13976    GIM_Reject,
13977    // Label 13: @33905
13978    GIM_Try, /*On fail goto*//*Label 821*/ 33926, // Rule ID 5521 //
13979      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13980      // MIs[0] Operand 0
13981      GIM_CheckIsImm, /*MI*/0, /*Op*/0,
13982      GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
13983      // (atomic_fence (timm:{ *:[i32] }), 0:{ *:[i32] })  =>  (MEMBARRIER)
13984      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::MEMBARRIER,
13985      GIR_EraseFromParent, /*InsnID*/0,
13986      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13987      // GIR_Coverage, 5521,
13988      GIR_Done,
13989    // Label 821: @33926
13990    GIM_Reject,
13991    // Label 14: @33927
13992    GIM_Try, /*On fail goto*//*Label 822*/ 40090,
13993      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
13994      GIM_Try, /*On fail goto*//*Label 823*/ 33982, // Rule ID 1879 //
13995        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
13996        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uxtb16,
13997        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13998        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13999        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
14000        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
14001        // (intrinsic_wo_chain:{ *:[i32] } 2777:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src)  =>  (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
14002        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16,
14003        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
14004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Src
14005        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
14006        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14007        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14008        GIR_EraseFromParent, /*InsnID*/0,
14009        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14010        // GIR_Coverage, 1879,
14011        GIR_Done,
14012      // Label 823: @33982
14013      GIM_Try, /*On fail goto*//*Label 824*/ 34032, // Rule ID 2118 //
14014        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
14015        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uxtb16,
14016        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14017        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14018        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
14019        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
14020        // (intrinsic_wo_chain:{ *:[i32] } 2777:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm)  =>  (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
14021        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16,
14022        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
14023        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
14024        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
14025        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14026        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14027        GIR_EraseFromParent, /*InsnID*/0,
14028        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14029        // GIR_Coverage, 2118,
14030        GIR_Done,
14031      // Label 824: @34032
14032      GIM_Try, /*On fail goto*//*Label 825*/ 34072, // Rule ID 693 //
14033        GIM_CheckFeatures, GIFBS_HasFullFP16,
14034        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
14035        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
14036        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
14037        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
14038        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
14039        // (intrinsic_wo_chain:{ *:[f16] } 2663:{ *:[iPTR] }, HPR:{ *:[f16] }:$Sm)  =>  (VRINTNH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
14040        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNH,
14041        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
14042        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
14043        GIR_EraseFromParent, /*InsnID*/0,
14044        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14045        // GIR_Coverage, 693,
14046        GIR_Done,
14047      // Label 825: @34072
14048      GIM_Try, /*On fail goto*//*Label 826*/ 34112, // Rule ID 694 //
14049        GIM_CheckFeatures, GIFBS_HasFPARMv8,
14050        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
14051        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14052        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14053        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
14054        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
14055        // (intrinsic_wo_chain:{ *:[f32] } 2663:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm)  =>  (VRINTNS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
14056        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNS,
14057        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
14058        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
14059        GIR_EraseFromParent, /*InsnID*/0,
14060        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14061        // GIR_Coverage, 694,
14062        GIR_Done,
14063      // Label 826: @34112
14064      GIM_Try, /*On fail goto*//*Label 827*/ 34152, // Rule ID 695 //
14065        GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
14066        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
14067        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
14068        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
14069        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14070        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14071        // (intrinsic_wo_chain:{ *:[f64] } 2663:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm)  =>  (VRINTND:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
14072        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTND,
14073        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
14074        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
14075        GIR_EraseFromParent, /*InsnID*/0,
14076        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14077        // GIR_Coverage, 695,
14078        GIR_Done,
14079      // Label 827: @34152
14080      GIM_Try, /*On fail goto*//*Label 828*/ 34199, // Rule ID 709 //
14081        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
14082        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_vcvtr,
14083        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14084        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
14085        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
14086        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14087        // (intrinsic_wo_chain:{ *:[f32] } 2778:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm)  =>  (VTOSIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
14088        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOSIRD,
14089        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
14090        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
14091        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14092        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14093        GIR_EraseFromParent, /*InsnID*/0,
14094        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14095        // GIR_Coverage, 709,
14096        GIR_Done,
14097      // Label 828: @34199
14098      GIM_Try, /*On fail goto*//*Label 829*/ 34246, // Rule ID 710 //
14099        GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
14100        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_vcvtr,
14101        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14102        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14103        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
14104        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
14105        // (intrinsic_wo_chain:{ *:[f32] } 2778:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm)  =>  (VTOSIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
14106        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOSIRS,
14107        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
14108        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
14109        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14110        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14111        GIR_EraseFromParent, /*InsnID*/0,
14112        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14113        // GIR_Coverage, 710,
14114        GIR_Done,
14115      // Label 829: @34246
14116      GIM_Try, /*On fail goto*//*Label 830*/ 34293, // Rule ID 711 //
14117        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
14118        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_vcvtru,
14119        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14120        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
14121        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
14122        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14123        // (intrinsic_wo_chain:{ *:[f32] } 2779:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm)  =>  (VTOUIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
14124        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOUIRD,
14125        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
14126        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
14127        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14128        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14129        GIR_EraseFromParent, /*InsnID*/0,
14130        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14131        // GIR_Coverage, 711,
14132        GIR_Done,
14133      // Label 830: @34293
14134      GIM_Try, /*On fail goto*//*Label 831*/ 34340, // Rule ID 712 //
14135        GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
14136        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_vcvtru,
14137        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
14138        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14139        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
14140        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
14141        // (intrinsic_wo_chain:{ *:[f32] } 2779:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm)  =>  (VTOUIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
14142        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOUIRS,
14143        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
14144        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
14145        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14146        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14147        GIR_EraseFromParent, /*InsnID*/0,
14148        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14149        // GIR_Coverage, 712,
14150        GIR_Done,
14151      // Label 831: @34340
14152      GIM_Try, /*On fail goto*//*Label 832*/ 34387, // Rule ID 1260 //
14153        GIM_CheckFeatures, GIFBS_HasNEON,
14154        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
14155        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14156        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
14157        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14158        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14159        // (intrinsic_wo_chain:{ *:[v4i16] } 2629:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm)  =>  (VPADDLsv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm)
14160        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv8i8,
14161        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14162        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14163        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14164        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14165        GIR_EraseFromParent, /*InsnID*/0,
14166        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14167        // GIR_Coverage, 1260,
14168        GIR_Done,
14169      // Label 832: @34387
14170      GIM_Try, /*On fail goto*//*Label 833*/ 34434, // Rule ID 1261 //
14171        GIM_CheckFeatures, GIFBS_HasNEON,
14172        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
14173        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14174        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14175        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14176        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14177        // (intrinsic_wo_chain:{ *:[v2i32] } 2629:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VPADDLsv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm)
14178        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv4i16,
14179        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14180        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14181        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14182        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14183        GIR_EraseFromParent, /*InsnID*/0,
14184        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14185        // GIR_Coverage, 1261,
14186        GIR_Done,
14187      // Label 833: @34434
14188      GIM_Try, /*On fail goto*//*Label 834*/ 34481, // Rule ID 1262 //
14189        GIM_CheckFeatures, GIFBS_HasNEON,
14190        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
14191        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
14192        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14193        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14194        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14195        // (intrinsic_wo_chain:{ *:[v1i64] } 2629:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VPADDLsv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm)
14196        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv2i32,
14197        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14198        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14199        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14200        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14201        GIR_EraseFromParent, /*InsnID*/0,
14202        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14203        // GIR_Coverage, 1262,
14204        GIR_Done,
14205      // Label 834: @34481
14206      GIM_Try, /*On fail goto*//*Label 835*/ 34528, // Rule ID 1263 //
14207        GIM_CheckFeatures, GIFBS_HasNEON,
14208        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
14209        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14210        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
14211        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14212        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14213        // (intrinsic_wo_chain:{ *:[v8i16] } 2629:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (VPADDLsv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm)
14214        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv16i8,
14215        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14216        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14217        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14218        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14219        GIR_EraseFromParent, /*InsnID*/0,
14220        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14221        // GIR_Coverage, 1263,
14222        GIR_Done,
14223      // Label 835: @34528
14224      GIM_Try, /*On fail goto*//*Label 836*/ 34575, // Rule ID 1264 //
14225        GIM_CheckFeatures, GIFBS_HasNEON,
14226        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
14227        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14228        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14229        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14230        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14231        // (intrinsic_wo_chain:{ *:[v4i32] } 2629:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VPADDLsv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm)
14232        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv8i16,
14233        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14234        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14235        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14236        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14237        GIR_EraseFromParent, /*InsnID*/0,
14238        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14239        // GIR_Coverage, 1264,
14240        GIR_Done,
14241      // Label 836: @34575
14242      GIM_Try, /*On fail goto*//*Label 837*/ 34622, // Rule ID 1265 //
14243        GIM_CheckFeatures, GIFBS_HasNEON,
14244        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
14245        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
14246        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14247        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14248        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14249        // (intrinsic_wo_chain:{ *:[v2i64] } 2629:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VPADDLsv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm)
14250        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv4i32,
14251        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14252        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14253        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14254        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14255        GIR_EraseFromParent, /*InsnID*/0,
14256        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14257        // GIR_Coverage, 1265,
14258        GIR_Done,
14259      // Label 837: @34622
14260      GIM_Try, /*On fail goto*//*Label 838*/ 34669, // Rule ID 1266 //
14261        GIM_CheckFeatures, GIFBS_HasNEON,
14262        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
14263        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14264        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
14265        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14266        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14267        // (intrinsic_wo_chain:{ *:[v4i16] } 2630:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm)  =>  (VPADDLuv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm)
14268        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv8i8,
14269        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14270        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14271        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14272        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14273        GIR_EraseFromParent, /*InsnID*/0,
14274        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14275        // GIR_Coverage, 1266,
14276        GIR_Done,
14277      // Label 838: @34669
14278      GIM_Try, /*On fail goto*//*Label 839*/ 34716, // Rule ID 1267 //
14279        GIM_CheckFeatures, GIFBS_HasNEON,
14280        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
14281        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14282        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14283        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14284        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14285        // (intrinsic_wo_chain:{ *:[v2i32] } 2630:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VPADDLuv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm)
14286        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv4i16,
14287        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14288        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14289        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14290        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14291        GIR_EraseFromParent, /*InsnID*/0,
14292        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14293        // GIR_Coverage, 1267,
14294        GIR_Done,
14295      // Label 839: @34716
14296      GIM_Try, /*On fail goto*//*Label 840*/ 34763, // Rule ID 1268 //
14297        GIM_CheckFeatures, GIFBS_HasNEON,
14298        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
14299        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
14300        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14301        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14302        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14303        // (intrinsic_wo_chain:{ *:[v1i64] } 2630:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VPADDLuv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm)
14304        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv2i32,
14305        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14306        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14307        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14308        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14309        GIR_EraseFromParent, /*InsnID*/0,
14310        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14311        // GIR_Coverage, 1268,
14312        GIR_Done,
14313      // Label 840: @34763
14314      GIM_Try, /*On fail goto*//*Label 841*/ 34810, // Rule ID 1269 //
14315        GIM_CheckFeatures, GIFBS_HasNEON,
14316        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
14317        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14318        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
14319        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14320        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14321        // (intrinsic_wo_chain:{ *:[v8i16] } 2630:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (VPADDLuv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm)
14322        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv16i8,
14323        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14324        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14325        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14326        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14327        GIR_EraseFromParent, /*InsnID*/0,
14328        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14329        // GIR_Coverage, 1269,
14330        GIR_Done,
14331      // Label 841: @34810
14332      GIM_Try, /*On fail goto*//*Label 842*/ 34857, // Rule ID 1270 //
14333        GIM_CheckFeatures, GIFBS_HasNEON,
14334        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
14335        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14336        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14337        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14338        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14339        // (intrinsic_wo_chain:{ *:[v4i32] } 2630:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VPADDLuv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm)
14340        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv8i16,
14341        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14342        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14343        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14344        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14345        GIR_EraseFromParent, /*InsnID*/0,
14346        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14347        // GIR_Coverage, 1270,
14348        GIR_Done,
14349      // Label 842: @34857
14350      GIM_Try, /*On fail goto*//*Label 843*/ 34904, // Rule ID 1271 //
14351        GIM_CheckFeatures, GIFBS_HasNEON,
14352        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
14353        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
14354        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14355        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14356        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14357        // (intrinsic_wo_chain:{ *:[v2i64] } 2630:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VPADDLuv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm)
14358        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv4i32,
14359        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14360        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14361        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14362        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14363        GIR_EraseFromParent, /*InsnID*/0,
14364        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14365        // GIR_Coverage, 1271,
14366        GIR_Done,
14367      // Label 843: @34904
14368      GIM_Try, /*On fail goto*//*Label 844*/ 34951, // Rule ID 1300 //
14369        GIM_CheckFeatures, GIFBS_HasNEON,
14370        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
14371        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14372        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14373        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14374        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14375        // (intrinsic_wo_chain:{ *:[v2i32] } 2657:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VRECPEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
14376        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEd,
14377        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14378        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14379        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14380        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14381        GIR_EraseFromParent, /*InsnID*/0,
14382        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14383        // GIR_Coverage, 1300,
14384        GIR_Done,
14385      // Label 844: @34951
14386      GIM_Try, /*On fail goto*//*Label 845*/ 34998, // Rule ID 1301 //
14387        GIM_CheckFeatures, GIFBS_HasNEON,
14388        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
14389        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14390        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14391        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14392        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14393        // (intrinsic_wo_chain:{ *:[v4i32] } 2657:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VRECPEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
14394        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEq,
14395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14396        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14397        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14398        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14399        GIR_EraseFromParent, /*InsnID*/0,
14400        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14401        // GIR_Coverage, 1301,
14402        GIR_Done,
14403      // Label 845: @34998
14404      GIM_Try, /*On fail goto*//*Label 846*/ 35045, // Rule ID 1302 //
14405        GIM_CheckFeatures, GIFBS_HasNEON,
14406        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
14407        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14408        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14409        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14410        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14411        // (intrinsic_wo_chain:{ *:[v2f32] } 2657:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRECPEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
14412        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEfd,
14413        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14414        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14415        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14416        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14417        GIR_EraseFromParent, /*InsnID*/0,
14418        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14419        // GIR_Coverage, 1302,
14420        GIR_Done,
14421      // Label 846: @35045
14422      GIM_Try, /*On fail goto*//*Label 847*/ 35092, // Rule ID 1303 //
14423        GIM_CheckFeatures, GIFBS_HasNEON,
14424        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
14425        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14426        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14427        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14428        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14429        // (intrinsic_wo_chain:{ *:[v4f32] } 2657:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRECPEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
14430        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEfq,
14431        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14432        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14433        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14434        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14435        GIR_EraseFromParent, /*InsnID*/0,
14436        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14437        // GIR_Coverage, 1303,
14438        GIR_Done,
14439      // Label 847: @35092
14440      GIM_Try, /*On fail goto*//*Label 848*/ 35139, // Rule ID 1304 //
14441        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
14442        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
14443        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14444        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14445        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14446        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14447        // (intrinsic_wo_chain:{ *:[v4f16] } 2657:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRECPEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
14448        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEhd,
14449        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14450        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14451        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14452        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14453        GIR_EraseFromParent, /*InsnID*/0,
14454        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14455        // GIR_Coverage, 1304,
14456        GIR_Done,
14457      // Label 848: @35139
14458      GIM_Try, /*On fail goto*//*Label 849*/ 35186, // Rule ID 1305 //
14459        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
14460        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
14461        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14462        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14463        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14464        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14465        // (intrinsic_wo_chain:{ *:[v8f16] } 2657:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRECPEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
14466        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEhq,
14467        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14468        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14469        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14470        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14471        GIR_EraseFromParent, /*InsnID*/0,
14472        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14473        // GIR_Coverage, 1305,
14474        GIR_Done,
14475      // Label 849: @35186
14476      GIM_Try, /*On fail goto*//*Label 850*/ 35233, // Rule ID 1310 //
14477        GIM_CheckFeatures, GIFBS_HasNEON,
14478        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
14479        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14480        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14481        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14482        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14483        // (intrinsic_wo_chain:{ *:[v2i32] } 2670:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VRSQRTEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
14484        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEd,
14485        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14486        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14487        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14488        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14489        GIR_EraseFromParent, /*InsnID*/0,
14490        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14491        // GIR_Coverage, 1310,
14492        GIR_Done,
14493      // Label 850: @35233
14494      GIM_Try, /*On fail goto*//*Label 851*/ 35280, // Rule ID 1311 //
14495        GIM_CheckFeatures, GIFBS_HasNEON,
14496        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
14497        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14498        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14499        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14500        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14501        // (intrinsic_wo_chain:{ *:[v4i32] } 2670:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VRSQRTEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
14502        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEq,
14503        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14504        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14505        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14506        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14507        GIR_EraseFromParent, /*InsnID*/0,
14508        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14509        // GIR_Coverage, 1311,
14510        GIR_Done,
14511      // Label 851: @35280
14512      GIM_Try, /*On fail goto*//*Label 852*/ 35327, // Rule ID 1312 //
14513        GIM_CheckFeatures, GIFBS_HasNEON,
14514        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
14515        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14516        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14517        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14518        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14519        // (intrinsic_wo_chain:{ *:[v2f32] } 2670:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRSQRTEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
14520        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEfd,
14521        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14522        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14523        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14524        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14525        GIR_EraseFromParent, /*InsnID*/0,
14526        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14527        // GIR_Coverage, 1312,
14528        GIR_Done,
14529      // Label 852: @35327
14530      GIM_Try, /*On fail goto*//*Label 853*/ 35374, // Rule ID 1313 //
14531        GIM_CheckFeatures, GIFBS_HasNEON,
14532        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
14533        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14534        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14535        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14536        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14537        // (intrinsic_wo_chain:{ *:[v4f32] } 2670:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRSQRTEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
14538        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEfq,
14539        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14540        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14541        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14542        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14543        GIR_EraseFromParent, /*InsnID*/0,
14544        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14545        // GIR_Coverage, 1313,
14546        GIR_Done,
14547      // Label 853: @35374
14548      GIM_Try, /*On fail goto*//*Label 854*/ 35421, // Rule ID 1314 //
14549        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
14550        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
14551        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14552        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14553        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14554        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14555        // (intrinsic_wo_chain:{ *:[v4f16] } 2670:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRSQRTEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
14556        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEhd,
14557        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14558        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14559        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14560        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14561        GIR_EraseFromParent, /*InsnID*/0,
14562        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14563        // GIR_Coverage, 1314,
14564        GIR_Done,
14565      // Label 854: @35421
14566      GIM_Try, /*On fail goto*//*Label 855*/ 35468, // Rule ID 1315 //
14567        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
14568        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
14569        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14570        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14571        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14572        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14573        // (intrinsic_wo_chain:{ *:[v8f16] } 2670:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRSQRTEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
14574        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEhq,
14575        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14576        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14577        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14578        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14579        GIR_EraseFromParent, /*InsnID*/0,
14580        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14581        // GIR_Coverage, 1315,
14582        GIR_Done,
14583      // Label 855: @35468
14584      GIM_Try, /*On fail goto*//*Label 856*/ 35515, // Rule ID 1536 //
14585        GIM_CheckFeatures, GIFBS_HasNEON,
14586        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
14587        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
14588        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
14589        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14590        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14591        // (intrinsic_wo_chain:{ *:[v8i8] } 2635:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm)  =>  (VQABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
14592        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv8i8,
14593        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14594        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14595        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14596        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14597        GIR_EraseFromParent, /*InsnID*/0,
14598        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14599        // GIR_Coverage, 1536,
14600        GIR_Done,
14601      // Label 856: @35515
14602      GIM_Try, /*On fail goto*//*Label 857*/ 35562, // Rule ID 1537 //
14603        GIM_CheckFeatures, GIFBS_HasNEON,
14604        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
14605        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14606        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14607        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14608        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14609        // (intrinsic_wo_chain:{ *:[v4i16] } 2635:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VQABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
14610        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv4i16,
14611        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14612        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14613        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14614        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14615        GIR_EraseFromParent, /*InsnID*/0,
14616        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14617        // GIR_Coverage, 1537,
14618        GIR_Done,
14619      // Label 857: @35562
14620      GIM_Try, /*On fail goto*//*Label 858*/ 35609, // Rule ID 1538 //
14621        GIM_CheckFeatures, GIFBS_HasNEON,
14622        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
14623        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14624        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14625        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14626        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14627        // (intrinsic_wo_chain:{ *:[v2i32] } 2635:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VQABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
14628        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv2i32,
14629        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14630        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14631        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14632        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14633        GIR_EraseFromParent, /*InsnID*/0,
14634        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14635        // GIR_Coverage, 1538,
14636        GIR_Done,
14637      // Label 858: @35609
14638      GIM_Try, /*On fail goto*//*Label 859*/ 35656, // Rule ID 1539 //
14639        GIM_CheckFeatures, GIFBS_HasNEON,
14640        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
14641        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
14642        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
14643        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14644        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14645        // (intrinsic_wo_chain:{ *:[v16i8] } 2635:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (VQABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
14646        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv16i8,
14647        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14648        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14649        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14650        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14651        GIR_EraseFromParent, /*InsnID*/0,
14652        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14653        // GIR_Coverage, 1539,
14654        GIR_Done,
14655      // Label 859: @35656
14656      GIM_Try, /*On fail goto*//*Label 860*/ 35703, // Rule ID 1540 //
14657        GIM_CheckFeatures, GIFBS_HasNEON,
14658        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
14659        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14660        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14661        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14662        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14663        // (intrinsic_wo_chain:{ *:[v8i16] } 2635:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VQABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
14664        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv8i16,
14665        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14666        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14667        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14668        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14669        GIR_EraseFromParent, /*InsnID*/0,
14670        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14671        // GIR_Coverage, 1540,
14672        GIR_Done,
14673      // Label 860: @35703
14674      GIM_Try, /*On fail goto*//*Label 861*/ 35750, // Rule ID 1541 //
14675        GIM_CheckFeatures, GIFBS_HasNEON,
14676        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
14677        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14678        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14679        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14680        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14681        // (intrinsic_wo_chain:{ *:[v4i32] } 2635:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VQABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
14682        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv4i32,
14683        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14684        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14685        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14686        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14687        GIR_EraseFromParent, /*InsnID*/0,
14688        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14689        // GIR_Coverage, 1541,
14690        GIR_Done,
14691      // Label 861: @35750
14692      GIM_Try, /*On fail goto*//*Label 862*/ 35797, // Rule ID 1552 //
14693        GIM_CheckFeatures, GIFBS_HasNEON,
14694        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
14695        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
14696        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
14697        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14698        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14699        // (intrinsic_wo_chain:{ *:[v8i8] } 2641:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm)  =>  (VQNEGv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
14700        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv8i8,
14701        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14702        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14703        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14704        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14705        GIR_EraseFromParent, /*InsnID*/0,
14706        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14707        // GIR_Coverage, 1552,
14708        GIR_Done,
14709      // Label 862: @35797
14710      GIM_Try, /*On fail goto*//*Label 863*/ 35844, // Rule ID 1553 //
14711        GIM_CheckFeatures, GIFBS_HasNEON,
14712        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
14713        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14714        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14715        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14716        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14717        // (intrinsic_wo_chain:{ *:[v4i16] } 2641:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VQNEGv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
14718        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv4i16,
14719        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14720        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14721        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14722        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14723        GIR_EraseFromParent, /*InsnID*/0,
14724        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14725        // GIR_Coverage, 1553,
14726        GIR_Done,
14727      // Label 863: @35844
14728      GIM_Try, /*On fail goto*//*Label 864*/ 35891, // Rule ID 1554 //
14729        GIM_CheckFeatures, GIFBS_HasNEON,
14730        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
14731        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14732        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14733        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14734        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14735        // (intrinsic_wo_chain:{ *:[v2i32] } 2641:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VQNEGv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
14736        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv2i32,
14737        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14738        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14739        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14740        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14741        GIR_EraseFromParent, /*InsnID*/0,
14742        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14743        // GIR_Coverage, 1554,
14744        GIR_Done,
14745      // Label 864: @35891
14746      GIM_Try, /*On fail goto*//*Label 865*/ 35938, // Rule ID 1555 //
14747        GIM_CheckFeatures, GIFBS_HasNEON,
14748        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
14749        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
14750        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
14751        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14752        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14753        // (intrinsic_wo_chain:{ *:[v16i8] } 2641:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (VQNEGv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
14754        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv16i8,
14755        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14756        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14757        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14758        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14759        GIR_EraseFromParent, /*InsnID*/0,
14760        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14761        // GIR_Coverage, 1555,
14762        GIR_Done,
14763      // Label 865: @35938
14764      GIM_Try, /*On fail goto*//*Label 866*/ 35985, // Rule ID 1556 //
14765        GIM_CheckFeatures, GIFBS_HasNEON,
14766        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
14767        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14768        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14769        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14770        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14771        // (intrinsic_wo_chain:{ *:[v8i16] } 2641:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VQNEGv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
14772        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv8i16,
14773        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14774        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14775        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14776        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14777        GIR_EraseFromParent, /*InsnID*/0,
14778        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14779        // GIR_Coverage, 1556,
14780        GIR_Done,
14781      // Label 866: @35985
14782      GIM_Try, /*On fail goto*//*Label 867*/ 36032, // Rule ID 1557 //
14783        GIM_CheckFeatures, GIFBS_HasNEON,
14784        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
14785        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14786        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14787        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14788        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14789        // (intrinsic_wo_chain:{ *:[v4i32] } 2641:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VQNEGv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
14790        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv4i32,
14791        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14792        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14793        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14794        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14795        GIR_EraseFromParent, /*InsnID*/0,
14796        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14797        // GIR_Coverage, 1557,
14798        GIR_Done,
14799      // Label 867: @36032
14800      GIM_Try, /*On fail goto*//*Label 868*/ 36079, // Rule ID 1558 //
14801        GIM_CheckFeatures, GIFBS_HasNEON,
14802        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
14803        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
14804        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
14805        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14806        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14807        // (intrinsic_wo_chain:{ *:[v8i8] } 2582:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm)  =>  (VCLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
14808        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv8i8,
14809        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14810        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14811        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14812        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14813        GIR_EraseFromParent, /*InsnID*/0,
14814        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14815        // GIR_Coverage, 1558,
14816        GIR_Done,
14817      // Label 868: @36079
14818      GIM_Try, /*On fail goto*//*Label 869*/ 36126, // Rule ID 1559 //
14819        GIM_CheckFeatures, GIFBS_HasNEON,
14820        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
14821        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14822        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14823        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14824        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14825        // (intrinsic_wo_chain:{ *:[v4i16] } 2582:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VCLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
14826        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv4i16,
14827        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14828        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14829        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14830        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14831        GIR_EraseFromParent, /*InsnID*/0,
14832        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14833        // GIR_Coverage, 1559,
14834        GIR_Done,
14835      // Label 869: @36126
14836      GIM_Try, /*On fail goto*//*Label 870*/ 36173, // Rule ID 1560 //
14837        GIM_CheckFeatures, GIFBS_HasNEON,
14838        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
14839        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14840        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14841        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14842        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14843        // (intrinsic_wo_chain:{ *:[v2i32] } 2582:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VCLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
14844        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv2i32,
14845        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14846        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14847        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14848        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14849        GIR_EraseFromParent, /*InsnID*/0,
14850        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14851        // GIR_Coverage, 1560,
14852        GIR_Done,
14853      // Label 870: @36173
14854      GIM_Try, /*On fail goto*//*Label 871*/ 36220, // Rule ID 1561 //
14855        GIM_CheckFeatures, GIFBS_HasNEON,
14856        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
14857        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
14858        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
14859        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14860        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14861        // (intrinsic_wo_chain:{ *:[v16i8] } 2582:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (VCLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
14862        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv16i8,
14863        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14864        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14865        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14866        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14867        GIR_EraseFromParent, /*InsnID*/0,
14868        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14869        // GIR_Coverage, 1561,
14870        GIR_Done,
14871      // Label 871: @36220
14872      GIM_Try, /*On fail goto*//*Label 872*/ 36267, // Rule ID 1562 //
14873        GIM_CheckFeatures, GIFBS_HasNEON,
14874        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
14875        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14876        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14877        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14878        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14879        // (intrinsic_wo_chain:{ *:[v8i16] } 2582:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VCLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
14880        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv8i16,
14881        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14882        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14883        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14884        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14885        GIR_EraseFromParent, /*InsnID*/0,
14886        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14887        // GIR_Coverage, 1562,
14888        GIR_Done,
14889      // Label 872: @36267
14890      GIM_Try, /*On fail goto*//*Label 873*/ 36314, // Rule ID 1563 //
14891        GIM_CheckFeatures, GIFBS_HasNEON,
14892        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
14893        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14894        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14895        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14896        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14897        // (intrinsic_wo_chain:{ *:[v4i32] } 2582:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VCLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
14898        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv4i32,
14899        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14900        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14901        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14902        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14903        GIR_EraseFromParent, /*InsnID*/0,
14904        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14905        // GIR_Coverage, 1563,
14906        GIR_Done,
14907      // Label 873: @36314
14908      GIM_Try, /*On fail goto*//*Label 874*/ 36361, // Rule ID 1607 //
14909        GIM_CheckFeatures, GIFBS_HasNEON,
14910        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovns,
14911        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
14912        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14913        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14914        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14915        // (intrinsic_wo_chain:{ *:[v8i8] } 2638:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VQMOVNsv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
14916        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsv8i8,
14917        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14918        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14919        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14920        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14921        GIR_EraseFromParent, /*InsnID*/0,
14922        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14923        // GIR_Coverage, 1607,
14924        GIR_Done,
14925      // Label 874: @36361
14926      GIM_Try, /*On fail goto*//*Label 875*/ 36408, // Rule ID 1608 //
14927        GIM_CheckFeatures, GIFBS_HasNEON,
14928        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovns,
14929        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14930        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14931        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14932        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14933        // (intrinsic_wo_chain:{ *:[v4i16] } 2638:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VQMOVNsv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
14934        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsv4i16,
14935        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14936        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14937        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14938        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14939        GIR_EraseFromParent, /*InsnID*/0,
14940        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14941        // GIR_Coverage, 1608,
14942        GIR_Done,
14943      // Label 875: @36408
14944      GIM_Try, /*On fail goto*//*Label 876*/ 36455, // Rule ID 1609 //
14945        GIM_CheckFeatures, GIFBS_HasNEON,
14946        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovns,
14947        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14948        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
14949        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14950        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14951        // (intrinsic_wo_chain:{ *:[v2i32] } 2638:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm)  =>  (VQMOVNsv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
14952        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsv2i32,
14953        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14954        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14955        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14956        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14957        GIR_EraseFromParent, /*InsnID*/0,
14958        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14959        // GIR_Coverage, 1609,
14960        GIR_Done,
14961      // Label 876: @36455
14962      GIM_Try, /*On fail goto*//*Label 877*/ 36502, // Rule ID 1610 //
14963        GIM_CheckFeatures, GIFBS_HasNEON,
14964        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnu,
14965        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
14966        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14967        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14968        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14969        // (intrinsic_wo_chain:{ *:[v8i8] } 2640:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VQMOVNuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
14970        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNuv8i8,
14971        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14972        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14973        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14974        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14975        GIR_EraseFromParent, /*InsnID*/0,
14976        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14977        // GIR_Coverage, 1610,
14978        GIR_Done,
14979      // Label 877: @36502
14980      GIM_Try, /*On fail goto*//*Label 878*/ 36549, // Rule ID 1611 //
14981        GIM_CheckFeatures, GIFBS_HasNEON,
14982        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnu,
14983        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14984        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14985        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14986        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14987        // (intrinsic_wo_chain:{ *:[v4i16] } 2640:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VQMOVNuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
14988        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNuv4i16,
14989        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14990        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14991        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14992        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14993        GIR_EraseFromParent, /*InsnID*/0,
14994        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14995        // GIR_Coverage, 1611,
14996        GIR_Done,
14997      // Label 878: @36549
14998      GIM_Try, /*On fail goto*//*Label 879*/ 36596, // Rule ID 1612 //
14999        GIM_CheckFeatures, GIFBS_HasNEON,
15000        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnu,
15001        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15002        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
15003        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15004        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15005        // (intrinsic_wo_chain:{ *:[v2i32] } 2640:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm)  =>  (VQMOVNuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
15006        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNuv2i32,
15007        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15008        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15009        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15010        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15011        GIR_EraseFromParent, /*InsnID*/0,
15012        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15013        // GIR_Coverage, 1612,
15014        GIR_Done,
15015      // Label 879: @36596
15016      GIM_Try, /*On fail goto*//*Label 880*/ 36643, // Rule ID 1613 //
15017        GIM_CheckFeatures, GIFBS_HasNEON,
15018        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnsu,
15019        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
15020        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15021        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15022        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15023        // (intrinsic_wo_chain:{ *:[v8i8] } 2639:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VQMOVNsuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
15024        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsuv8i8,
15025        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15026        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15027        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15028        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15029        GIR_EraseFromParent, /*InsnID*/0,
15030        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15031        // GIR_Coverage, 1613,
15032        GIR_Done,
15033      // Label 880: @36643
15034      GIM_Try, /*On fail goto*//*Label 881*/ 36690, // Rule ID 1614 //
15035        GIM_CheckFeatures, GIFBS_HasNEON,
15036        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnsu,
15037        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15038        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15039        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15040        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15041        // (intrinsic_wo_chain:{ *:[v4i16] } 2639:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VQMOVNsuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
15042        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsuv4i16,
15043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15044        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15045        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15046        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15047        GIR_EraseFromParent, /*InsnID*/0,
15048        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15049        // GIR_Coverage, 1614,
15050        GIR_Done,
15051      // Label 881: @36690
15052      GIM_Try, /*On fail goto*//*Label 882*/ 36737, // Rule ID 1615 //
15053        GIM_CheckFeatures, GIFBS_HasNEON,
15054        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnsu,
15055        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15056        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
15057        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15058        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15059        // (intrinsic_wo_chain:{ *:[v2i32] } 2639:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm)  =>  (VQMOVNsuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
15060        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsuv2i32,
15061        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15062        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15063        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15064        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15065        GIR_EraseFromParent, /*InsnID*/0,
15066        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15067        // GIR_Coverage, 1615,
15068        GIR_Done,
15069      // Label 882: @36737
15070      GIM_Try, /*On fail goto*//*Label 883*/ 36777, // Rule ID 1638 //
15071        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15072        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtas,
15073        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15074        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15075        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15076        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15077        // (intrinsic_wo_chain:{ *:[v2i32] } 2583:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTANSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15078        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSDf,
15079        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15080        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15081        GIR_EraseFromParent, /*InsnID*/0,
15082        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15083        // GIR_Coverage, 1638,
15084        GIR_Done,
15085      // Label 883: @36777
15086      GIM_Try, /*On fail goto*//*Label 884*/ 36817, // Rule ID 1639 //
15087        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15088        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtas,
15089        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15090        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15091        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15092        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15093        // (intrinsic_wo_chain:{ *:[v4i32] } 2583:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTANSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15094        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSQf,
15095        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15096        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15097        GIR_EraseFromParent, /*InsnID*/0,
15098        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15099        // GIR_Coverage, 1639,
15100        GIR_Done,
15101      // Label 884: @36817
15102      GIM_Try, /*On fail goto*//*Label 885*/ 36857, // Rule ID 1640 //
15103        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15104        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtau,
15105        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15106        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15107        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15108        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15109        // (intrinsic_wo_chain:{ *:[v2i32] } 2584:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTANUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15110        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUDf,
15111        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15112        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15113        GIR_EraseFromParent, /*InsnID*/0,
15114        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15115        // GIR_Coverage, 1640,
15116        GIR_Done,
15117      // Label 885: @36857
15118      GIM_Try, /*On fail goto*//*Label 886*/ 36897, // Rule ID 1641 //
15119        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15120        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtau,
15121        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15122        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15123        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15124        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15125        // (intrinsic_wo_chain:{ *:[v4i32] } 2584:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTANUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15126        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUQf,
15127        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15128        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15129        GIR_EraseFromParent, /*InsnID*/0,
15130        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15131        // GIR_Coverage, 1641,
15132        GIR_Done,
15133      // Label 886: @36897
15134      GIM_Try, /*On fail goto*//*Label 887*/ 36937, // Rule ID 1642 //
15135        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15136        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtas,
15137        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15138        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15139        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15140        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15141        // (intrinsic_wo_chain:{ *:[v4i16] } 2583:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTANSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15142        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSDh,
15143        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15144        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15145        GIR_EraseFromParent, /*InsnID*/0,
15146        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15147        // GIR_Coverage, 1642,
15148        GIR_Done,
15149      // Label 887: @36937
15150      GIM_Try, /*On fail goto*//*Label 888*/ 36977, // Rule ID 1643 //
15151        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15152        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtas,
15153        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15154        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15155        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15156        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15157        // (intrinsic_wo_chain:{ *:[v8i16] } 2583:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTANSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15158        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSQh,
15159        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15160        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15161        GIR_EraseFromParent, /*InsnID*/0,
15162        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15163        // GIR_Coverage, 1643,
15164        GIR_Done,
15165      // Label 888: @36977
15166      GIM_Try, /*On fail goto*//*Label 889*/ 37017, // Rule ID 1644 //
15167        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15168        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtau,
15169        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15170        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15171        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15172        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15173        // (intrinsic_wo_chain:{ *:[v4i16] } 2584:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTANUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15174        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUDh,
15175        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15176        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15177        GIR_EraseFromParent, /*InsnID*/0,
15178        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15179        // GIR_Coverage, 1644,
15180        GIR_Done,
15181      // Label 889: @37017
15182      GIM_Try, /*On fail goto*//*Label 890*/ 37057, // Rule ID 1645 //
15183        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15184        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtau,
15185        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15186        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15187        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15188        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15189        // (intrinsic_wo_chain:{ *:[v8i16] } 2584:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTANUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15190        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUQh,
15191        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15192        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15193        GIR_EraseFromParent, /*InsnID*/0,
15194        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15195        // GIR_Coverage, 1645,
15196        GIR_Done,
15197      // Label 890: @37057
15198      GIM_Try, /*On fail goto*//*Label 891*/ 37097, // Rule ID 1646 //
15199        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15200        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtns,
15201        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15202        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15203        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15204        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15205        // (intrinsic_wo_chain:{ *:[v2i32] } 2595:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTNNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15206        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSDf,
15207        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15208        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15209        GIR_EraseFromParent, /*InsnID*/0,
15210        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15211        // GIR_Coverage, 1646,
15212        GIR_Done,
15213      // Label 891: @37097
15214      GIM_Try, /*On fail goto*//*Label 892*/ 37137, // Rule ID 1647 //
15215        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15216        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtns,
15217        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15218        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15219        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15220        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15221        // (intrinsic_wo_chain:{ *:[v4i32] } 2595:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTNNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15222        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSQf,
15223        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15224        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15225        GIR_EraseFromParent, /*InsnID*/0,
15226        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15227        // GIR_Coverage, 1647,
15228        GIR_Done,
15229      // Label 892: @37137
15230      GIM_Try, /*On fail goto*//*Label 893*/ 37177, // Rule ID 1648 //
15231        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15232        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtnu,
15233        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15234        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15235        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15236        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15237        // (intrinsic_wo_chain:{ *:[v2i32] } 2596:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTNNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15238        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUDf,
15239        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15240        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15241        GIR_EraseFromParent, /*InsnID*/0,
15242        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15243        // GIR_Coverage, 1648,
15244        GIR_Done,
15245      // Label 893: @37177
15246      GIM_Try, /*On fail goto*//*Label 894*/ 37217, // Rule ID 1649 //
15247        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15248        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtnu,
15249        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15250        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15251        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15252        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15253        // (intrinsic_wo_chain:{ *:[v4i32] } 2596:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTNNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15254        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUQf,
15255        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15256        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15257        GIR_EraseFromParent, /*InsnID*/0,
15258        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15259        // GIR_Coverage, 1649,
15260        GIR_Done,
15261      // Label 894: @37217
15262      GIM_Try, /*On fail goto*//*Label 895*/ 37257, // Rule ID 1650 //
15263        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15264        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtns,
15265        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15266        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15267        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15268        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15269        // (intrinsic_wo_chain:{ *:[v4i16] } 2595:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTNNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15270        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSDh,
15271        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15272        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15273        GIR_EraseFromParent, /*InsnID*/0,
15274        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15275        // GIR_Coverage, 1650,
15276        GIR_Done,
15277      // Label 895: @37257
15278      GIM_Try, /*On fail goto*//*Label 896*/ 37297, // Rule ID 1651 //
15279        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15280        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtns,
15281        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15282        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15283        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15284        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15285        // (intrinsic_wo_chain:{ *:[v8i16] } 2595:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTNNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15286        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSQh,
15287        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15288        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15289        GIR_EraseFromParent, /*InsnID*/0,
15290        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15291        // GIR_Coverage, 1651,
15292        GIR_Done,
15293      // Label 896: @37297
15294      GIM_Try, /*On fail goto*//*Label 897*/ 37337, // Rule ID 1652 //
15295        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15296        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtnu,
15297        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15298        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15299        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15300        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15301        // (intrinsic_wo_chain:{ *:[v4i16] } 2596:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTNNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15302        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUDh,
15303        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15304        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15305        GIR_EraseFromParent, /*InsnID*/0,
15306        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15307        // GIR_Coverage, 1652,
15308        GIR_Done,
15309      // Label 897: @37337
15310      GIM_Try, /*On fail goto*//*Label 898*/ 37377, // Rule ID 1653 //
15311        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15312        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtnu,
15313        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15314        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15315        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15316        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15317        // (intrinsic_wo_chain:{ *:[v8i16] } 2596:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTNNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15318        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUQh,
15319        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15321        GIR_EraseFromParent, /*InsnID*/0,
15322        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15323        // GIR_Coverage, 1653,
15324        GIR_Done,
15325      // Label 898: @37377
15326      GIM_Try, /*On fail goto*//*Label 899*/ 37417, // Rule ID 1654 //
15327        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15328        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtps,
15329        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15330        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15331        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15332        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15333        // (intrinsic_wo_chain:{ *:[v2i32] } 2597:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTPNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15334        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSDf,
15335        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15336        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15337        GIR_EraseFromParent, /*InsnID*/0,
15338        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15339        // GIR_Coverage, 1654,
15340        GIR_Done,
15341      // Label 899: @37417
15342      GIM_Try, /*On fail goto*//*Label 900*/ 37457, // Rule ID 1655 //
15343        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15344        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtps,
15345        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15346        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15347        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15348        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15349        // (intrinsic_wo_chain:{ *:[v4i32] } 2597:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTPNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15350        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSQf,
15351        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15352        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15353        GIR_EraseFromParent, /*InsnID*/0,
15354        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15355        // GIR_Coverage, 1655,
15356        GIR_Done,
15357      // Label 900: @37457
15358      GIM_Try, /*On fail goto*//*Label 901*/ 37497, // Rule ID 1656 //
15359        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15360        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtpu,
15361        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15362        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15363        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15364        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15365        // (intrinsic_wo_chain:{ *:[v2i32] } 2598:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTPNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15366        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUDf,
15367        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15368        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15369        GIR_EraseFromParent, /*InsnID*/0,
15370        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15371        // GIR_Coverage, 1656,
15372        GIR_Done,
15373      // Label 901: @37497
15374      GIM_Try, /*On fail goto*//*Label 902*/ 37537, // Rule ID 1657 //
15375        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15376        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtpu,
15377        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15378        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15379        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15380        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15381        // (intrinsic_wo_chain:{ *:[v4i32] } 2598:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTPNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15382        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUQf,
15383        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15384        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15385        GIR_EraseFromParent, /*InsnID*/0,
15386        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15387        // GIR_Coverage, 1657,
15388        GIR_Done,
15389      // Label 902: @37537
15390      GIM_Try, /*On fail goto*//*Label 903*/ 37577, // Rule ID 1658 //
15391        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15392        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtps,
15393        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15394        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15395        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15396        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15397        // (intrinsic_wo_chain:{ *:[v4i16] } 2597:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTPNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15398        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSDh,
15399        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15400        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15401        GIR_EraseFromParent, /*InsnID*/0,
15402        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15403        // GIR_Coverage, 1658,
15404        GIR_Done,
15405      // Label 903: @37577
15406      GIM_Try, /*On fail goto*//*Label 904*/ 37617, // Rule ID 1659 //
15407        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15408        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtps,
15409        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15410        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15411        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15412        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15413        // (intrinsic_wo_chain:{ *:[v8i16] } 2597:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTPNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15414        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSQh,
15415        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15416        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15417        GIR_EraseFromParent, /*InsnID*/0,
15418        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15419        // GIR_Coverage, 1659,
15420        GIR_Done,
15421      // Label 904: @37617
15422      GIM_Try, /*On fail goto*//*Label 905*/ 37657, // Rule ID 1660 //
15423        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15424        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtpu,
15425        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15426        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15427        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15428        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15429        // (intrinsic_wo_chain:{ *:[v4i16] } 2598:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTPNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15430        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUDh,
15431        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15432        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15433        GIR_EraseFromParent, /*InsnID*/0,
15434        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15435        // GIR_Coverage, 1660,
15436        GIR_Done,
15437      // Label 905: @37657
15438      GIM_Try, /*On fail goto*//*Label 906*/ 37697, // Rule ID 1661 //
15439        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15440        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtpu,
15441        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15442        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15443        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15444        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15445        // (intrinsic_wo_chain:{ *:[v8i16] } 2598:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTPNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15446        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUQh,
15447        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15448        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15449        GIR_EraseFromParent, /*InsnID*/0,
15450        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15451        // GIR_Coverage, 1661,
15452        GIR_Done,
15453      // Label 906: @37697
15454      GIM_Try, /*On fail goto*//*Label 907*/ 37737, // Rule ID 1662 //
15455        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15456        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtms,
15457        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15458        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15459        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15460        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15461        // (intrinsic_wo_chain:{ *:[v2i32] } 2593:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTMNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15462        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSDf,
15463        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15464        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15465        GIR_EraseFromParent, /*InsnID*/0,
15466        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15467        // GIR_Coverage, 1662,
15468        GIR_Done,
15469      // Label 907: @37737
15470      GIM_Try, /*On fail goto*//*Label 908*/ 37777, // Rule ID 1663 //
15471        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15472        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtms,
15473        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15474        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15475        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15476        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15477        // (intrinsic_wo_chain:{ *:[v4i32] } 2593:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTMNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15478        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSQf,
15479        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15480        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15481        GIR_EraseFromParent, /*InsnID*/0,
15482        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15483        // GIR_Coverage, 1663,
15484        GIR_Done,
15485      // Label 908: @37777
15486      GIM_Try, /*On fail goto*//*Label 909*/ 37817, // Rule ID 1664 //
15487        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15488        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtmu,
15489        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15490        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15491        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15492        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15493        // (intrinsic_wo_chain:{ *:[v2i32] } 2594:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTMNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15494        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUDf,
15495        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15496        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15497        GIR_EraseFromParent, /*InsnID*/0,
15498        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15499        // GIR_Coverage, 1664,
15500        GIR_Done,
15501      // Label 909: @37817
15502      GIM_Try, /*On fail goto*//*Label 910*/ 37857, // Rule ID 1665 //
15503        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15504        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtmu,
15505        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15506        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15507        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15508        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15509        // (intrinsic_wo_chain:{ *:[v4i32] } 2594:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTMNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15510        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUQf,
15511        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15512        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15513        GIR_EraseFromParent, /*InsnID*/0,
15514        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15515        // GIR_Coverage, 1665,
15516        GIR_Done,
15517      // Label 910: @37857
15518      GIM_Try, /*On fail goto*//*Label 911*/ 37897, // Rule ID 1666 //
15519        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15520        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtms,
15521        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15522        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15523        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15524        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15525        // (intrinsic_wo_chain:{ *:[v4i16] } 2593:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTMNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15526        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSDh,
15527        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15528        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15529        GIR_EraseFromParent, /*InsnID*/0,
15530        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15531        // GIR_Coverage, 1666,
15532        GIR_Done,
15533      // Label 911: @37897
15534      GIM_Try, /*On fail goto*//*Label 912*/ 37937, // Rule ID 1667 //
15535        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15536        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtms,
15537        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15538        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15539        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15540        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15541        // (intrinsic_wo_chain:{ *:[v8i16] } 2593:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTMNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15542        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSQh,
15543        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15544        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15545        GIR_EraseFromParent, /*InsnID*/0,
15546        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15547        // GIR_Coverage, 1667,
15548        GIR_Done,
15549      // Label 912: @37937
15550      GIM_Try, /*On fail goto*//*Label 913*/ 37977, // Rule ID 1668 //
15551        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15552        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtmu,
15553        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15554        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15555        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15556        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15557        // (intrinsic_wo_chain:{ *:[v4i16] } 2594:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTMNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15558        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUDh,
15559        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15560        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15561        GIR_EraseFromParent, /*InsnID*/0,
15562        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15563        // GIR_Coverage, 1668,
15564        GIR_Done,
15565      // Label 913: @37977
15566      GIM_Try, /*On fail goto*//*Label 914*/ 38017, // Rule ID 1669 //
15567        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15568        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtmu,
15569        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15570        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15571        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15572        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15573        // (intrinsic_wo_chain:{ *:[v8i16] } 2594:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTMNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15574        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUQh,
15575        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15576        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15577        GIR_EraseFromParent, /*InsnID*/0,
15578        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15579        // GIR_Coverage, 1669,
15580        GIR_Done,
15581      // Label 914: @38017
15582      GIM_Try, /*On fail goto*//*Label 915*/ 38064, // Rule ID 1686 //
15583        GIM_CheckFeatures, GIFBS_HasFP16_HasNEON,
15584        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2hf,
15585        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15586        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15587        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15588        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15589        // (intrinsic_wo_chain:{ *:[v4i16] } 2589:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTf2h:{ *:[v4i16] } QPR:{ *:[v4f32] }:$Vm)
15590        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2h,
15591        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15592        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15593        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15594        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15595        GIR_EraseFromParent, /*InsnID*/0,
15596        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15597        // GIR_Coverage, 1686,
15598        GIR_Done,
15599      // Label 915: @38064
15600      GIM_Try, /*On fail goto*//*Label 916*/ 38111, // Rule ID 1687 //
15601        GIM_CheckFeatures, GIFBS_HasFP16_HasNEON,
15602        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvthf2fp,
15603        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15604        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15605        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15606        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15607        // (intrinsic_wo_chain:{ *:[v4f32] } 2592:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4i16] }:$Vm)
15608        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2f,
15609        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15610        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15611        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15612        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15613        GIR_EraseFromParent, /*InsnID*/0,
15614        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15615        // GIR_Coverage, 1687,
15616        GIR_Done,
15617      // Label 916: @38111
15618      GIM_Try, /*On fail goto*//*Label 917*/ 38151, // Rule ID 1709 //
15619        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15620        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
15621        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15622        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15623        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15624        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15625        // (intrinsic_wo_chain:{ *:[v2f32] } 2663:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTNNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
15626        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNDf,
15627        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15628        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15629        GIR_EraseFromParent, /*InsnID*/0,
15630        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15631        // GIR_Coverage, 1709,
15632        GIR_Done,
15633      // Label 917: @38151
15634      GIM_Try, /*On fail goto*//*Label 918*/ 38191, // Rule ID 1710 //
15635        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15636        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
15637        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15638        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15639        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15640        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15641        // (intrinsic_wo_chain:{ *:[v4f32] } 2663:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTNNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
15642        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNQf,
15643        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15644        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15645        GIR_EraseFromParent, /*InsnID*/0,
15646        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15647        // GIR_Coverage, 1710,
15648        GIR_Done,
15649      // Label 918: @38191
15650      GIM_Try, /*On fail goto*//*Label 919*/ 38231, // Rule ID 1711 //
15651        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15652        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
15653        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15654        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15655        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15656        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15657        // (intrinsic_wo_chain:{ *:[v4f16] } 2663:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTNNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15658        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNDh,
15659        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15660        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15661        GIR_EraseFromParent, /*InsnID*/0,
15662        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15663        // GIR_Coverage, 1711,
15664        GIR_Done,
15665      // Label 919: @38231
15666      GIM_Try, /*On fail goto*//*Label 920*/ 38271, // Rule ID 1712 //
15667        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15668        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
15669        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15670        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15671        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15672        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15673        // (intrinsic_wo_chain:{ *:[v8f16] } 2663:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTNNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15674        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNQh,
15675        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15676        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15677        GIR_EraseFromParent, /*InsnID*/0,
15678        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15679        // GIR_Coverage, 1712,
15680        GIR_Done,
15681      // Label 920: @38271
15682      GIM_Try, /*On fail goto*//*Label 921*/ 38311, // Rule ID 1713 //
15683        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15684        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintx,
15685        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15686        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15687        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15688        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15689        // (intrinsic_wo_chain:{ *:[v2f32] } 2665:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTXNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
15690        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNDf,
15691        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15692        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15693        GIR_EraseFromParent, /*InsnID*/0,
15694        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15695        // GIR_Coverage, 1713,
15696        GIR_Done,
15697      // Label 921: @38311
15698      GIM_Try, /*On fail goto*//*Label 922*/ 38351, // Rule ID 1714 //
15699        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15700        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintx,
15701        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15702        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15703        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15704        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15705        // (intrinsic_wo_chain:{ *:[v4f32] } 2665:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTXNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
15706        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNQf,
15707        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15708        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15709        GIR_EraseFromParent, /*InsnID*/0,
15710        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15711        // GIR_Coverage, 1714,
15712        GIR_Done,
15713      // Label 922: @38351
15714      GIM_Try, /*On fail goto*//*Label 923*/ 38391, // Rule ID 1715 //
15715        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15716        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintx,
15717        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15718        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15719        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15720        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15721        // (intrinsic_wo_chain:{ *:[v4f16] } 2665:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTXNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15722        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNDh,
15723        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15724        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15725        GIR_EraseFromParent, /*InsnID*/0,
15726        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15727        // GIR_Coverage, 1715,
15728        GIR_Done,
15729      // Label 923: @38391
15730      GIM_Try, /*On fail goto*//*Label 924*/ 38431, // Rule ID 1716 //
15731        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15732        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintx,
15733        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15734        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15735        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15736        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15737        // (intrinsic_wo_chain:{ *:[v8f16] } 2665:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTXNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15738        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNQh,
15739        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15740        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15741        GIR_EraseFromParent, /*InsnID*/0,
15742        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15743        // GIR_Coverage, 1716,
15744        GIR_Done,
15745      // Label 924: @38431
15746      GIM_Try, /*On fail goto*//*Label 925*/ 38471, // Rule ID 1717 //
15747        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15748        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrinta,
15749        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15750        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15751        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15752        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15753        // (intrinsic_wo_chain:{ *:[v2f32] } 2661:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTANDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
15754        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANDf,
15755        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15756        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15757        GIR_EraseFromParent, /*InsnID*/0,
15758        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15759        // GIR_Coverage, 1717,
15760        GIR_Done,
15761      // Label 925: @38471
15762      GIM_Try, /*On fail goto*//*Label 926*/ 38511, // Rule ID 1718 //
15763        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15764        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrinta,
15765        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15766        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15767        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15768        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15769        // (intrinsic_wo_chain:{ *:[v4f32] } 2661:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTANQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
15770        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANQf,
15771        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15772        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15773        GIR_EraseFromParent, /*InsnID*/0,
15774        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15775        // GIR_Coverage, 1718,
15776        GIR_Done,
15777      // Label 926: @38511
15778      GIM_Try, /*On fail goto*//*Label 927*/ 38551, // Rule ID 1719 //
15779        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15780        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrinta,
15781        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15782        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15783        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15784        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15785        // (intrinsic_wo_chain:{ *:[v4f16] } 2661:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTANDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15786        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANDh,
15787        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15788        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15789        GIR_EraseFromParent, /*InsnID*/0,
15790        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15791        // GIR_Coverage, 1719,
15792        GIR_Done,
15793      // Label 927: @38551
15794      GIM_Try, /*On fail goto*//*Label 928*/ 38591, // Rule ID 1720 //
15795        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15796        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrinta,
15797        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15798        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15799        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15800        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15801        // (intrinsic_wo_chain:{ *:[v8f16] } 2661:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTANQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15802        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANQh,
15803        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15804        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15805        GIR_EraseFromParent, /*InsnID*/0,
15806        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15807        // GIR_Coverage, 1720,
15808        GIR_Done,
15809      // Label 928: @38591
15810      GIM_Try, /*On fail goto*//*Label 929*/ 38631, // Rule ID 1721 //
15811        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15812        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintz,
15813        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15814        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15815        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15816        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15817        // (intrinsic_wo_chain:{ *:[v2f32] } 2666:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTZNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
15818        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNDf,
15819        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15820        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15821        GIR_EraseFromParent, /*InsnID*/0,
15822        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15823        // GIR_Coverage, 1721,
15824        GIR_Done,
15825      // Label 929: @38631
15826      GIM_Try, /*On fail goto*//*Label 930*/ 38671, // Rule ID 1722 //
15827        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15828        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintz,
15829        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15830        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15831        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15832        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15833        // (intrinsic_wo_chain:{ *:[v4f32] } 2666:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTZNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
15834        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNQf,
15835        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15836        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15837        GIR_EraseFromParent, /*InsnID*/0,
15838        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15839        // GIR_Coverage, 1722,
15840        GIR_Done,
15841      // Label 930: @38671
15842      GIM_Try, /*On fail goto*//*Label 931*/ 38711, // Rule ID 1723 //
15843        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15844        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintz,
15845        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15846        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15847        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15848        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15849        // (intrinsic_wo_chain:{ *:[v4f16] } 2666:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTZNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15850        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNDh,
15851        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15852        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15853        GIR_EraseFromParent, /*InsnID*/0,
15854        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15855        // GIR_Coverage, 1723,
15856        GIR_Done,
15857      // Label 931: @38711
15858      GIM_Try, /*On fail goto*//*Label 932*/ 38751, // Rule ID 1724 //
15859        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15860        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintz,
15861        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15862        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15863        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15864        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15865        // (intrinsic_wo_chain:{ *:[v8f16] } 2666:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTZNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15866        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNQh,
15867        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15868        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15869        GIR_EraseFromParent, /*InsnID*/0,
15870        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15871        // GIR_Coverage, 1724,
15872        GIR_Done,
15873      // Label 932: @38751
15874      GIM_Try, /*On fail goto*//*Label 933*/ 38791, // Rule ID 1725 //
15875        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15876        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintm,
15877        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15878        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15879        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15880        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15881        // (intrinsic_wo_chain:{ *:[v2f32] } 2662:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
15882        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNDf,
15883        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15884        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15885        GIR_EraseFromParent, /*InsnID*/0,
15886        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15887        // GIR_Coverage, 1725,
15888        GIR_Done,
15889      // Label 933: @38791
15890      GIM_Try, /*On fail goto*//*Label 934*/ 38831, // Rule ID 1726 //
15891        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15892        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintm,
15893        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15894        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15895        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15896        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15897        // (intrinsic_wo_chain:{ *:[v4f32] } 2662:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
15898        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNQf,
15899        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15900        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15901        GIR_EraseFromParent, /*InsnID*/0,
15902        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15903        // GIR_Coverage, 1726,
15904        GIR_Done,
15905      // Label 934: @38831
15906      GIM_Try, /*On fail goto*//*Label 935*/ 38871, // Rule ID 1727 //
15907        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15908        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintm,
15909        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15910        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15911        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15912        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15913        // (intrinsic_wo_chain:{ *:[v4f16] } 2662:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15914        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNDh,
15915        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15916        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15917        GIR_EraseFromParent, /*InsnID*/0,
15918        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15919        // GIR_Coverage, 1727,
15920        GIR_Done,
15921      // Label 935: @38871
15922      GIM_Try, /*On fail goto*//*Label 936*/ 38911, // Rule ID 1728 //
15923        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15924        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintm,
15925        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15926        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15927        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15928        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15929        // (intrinsic_wo_chain:{ *:[v8f16] } 2662:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15930        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNQh,
15931        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15932        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15933        GIR_EraseFromParent, /*InsnID*/0,
15934        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15935        // GIR_Coverage, 1728,
15936        GIR_Done,
15937      // Label 936: @38911
15938      GIM_Try, /*On fail goto*//*Label 937*/ 38951, // Rule ID 1729 //
15939        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15940        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintp,
15941        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15942        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15943        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15944        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15945        // (intrinsic_wo_chain:{ *:[v2f32] } 2664:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTPNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
15946        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNDf,
15947        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15948        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15949        GIR_EraseFromParent, /*InsnID*/0,
15950        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15951        // GIR_Coverage, 1729,
15952        GIR_Done,
15953      // Label 937: @38951
15954      GIM_Try, /*On fail goto*//*Label 938*/ 38991, // Rule ID 1730 //
15955        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15956        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintp,
15957        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15958        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15959        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15960        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15961        // (intrinsic_wo_chain:{ *:[v4f32] } 2664:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTPNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
15962        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNQf,
15963        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15964        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15965        GIR_EraseFromParent, /*InsnID*/0,
15966        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15967        // GIR_Coverage, 1730,
15968        GIR_Done,
15969      // Label 938: @38991
15970      GIM_Try, /*On fail goto*//*Label 939*/ 39031, // Rule ID 1731 //
15971        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15972        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintp,
15973        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15974        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15975        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15976        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15977        // (intrinsic_wo_chain:{ *:[v4f16] } 2664:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTPNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15978        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNDh,
15979        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15980        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15981        GIR_EraseFromParent, /*InsnID*/0,
15982        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15983        // GIR_Coverage, 1731,
15984        GIR_Done,
15985      // Label 939: @39031
15986      GIM_Try, /*On fail goto*//*Label 940*/ 39071, // Rule ID 1732 //
15987        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15988        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintp,
15989        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15990        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15991        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15992        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15993        // (intrinsic_wo_chain:{ *:[v8f16] } 2664:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTPNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15994        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNQh,
15995        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15996        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15997        GIR_EraseFromParent, /*InsnID*/0,
15998        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15999        // GIR_Coverage, 1732,
16000        GIR_Done,
16001      // Label 940: @39071
16002      GIM_Try, /*On fail goto*//*Label 941*/ 39111, // Rule ID 1735 //
16003        GIM_CheckFeatures, GIFBS_HasAES_HasV8,
16004        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_aesimc,
16005        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
16006        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
16007        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16008        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16009        // (intrinsic_wo_chain:{ *:[v16i8] } 2552:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (AESIMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
16010        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESIMC,
16011        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16012        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16013        GIR_EraseFromParent, /*InsnID*/0,
16014        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16015        // GIR_Coverage, 1735,
16016        GIR_Done,
16017      // Label 941: @39111
16018      GIM_Try, /*On fail goto*//*Label 942*/ 39151, // Rule ID 1736 //
16019        GIM_CheckFeatures, GIFBS_HasAES_HasV8,
16020        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_aesmc,
16021        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
16022        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
16023        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16024        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16025        // (intrinsic_wo_chain:{ *:[v16i8] } 2553:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (AESMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
16026        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESMC,
16027        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16028        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16029        GIR_EraseFromParent, /*InsnID*/0,
16030        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16031        // GIR_Coverage, 1736,
16032        GIR_Done,
16033      // Label 942: @39151
16034      GIM_Try, /*On fail goto*//*Label 943*/ 39201, // Rule ID 1874 //
16035        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
16036        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sxtb16,
16037        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16038        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16039        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
16040        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
16041        // (intrinsic_wo_chain:{ *:[i32] } 2752:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src)  =>  (SXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
16042        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SXTB16,
16043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16044        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Src
16045        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16046        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16047        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16048        GIR_EraseFromParent, /*InsnID*/0,
16049        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16050        // GIR_Coverage, 1874,
16051        GIR_Done,
16052      // Label 943: @39201
16053      GIM_Try, /*On fail goto*//*Label 944*/ 39251, // Rule ID 2107 //
16054        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
16055        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sxtb16,
16056        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16057        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16058        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16059        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16060        // (intrinsic_wo_chain:{ *:[i32] } 2752:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn)  =>  (t2SXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 0:{ *:[i32] })
16061        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SXTB16,
16062        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16063        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16064        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16065        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16066        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16067        GIR_EraseFromParent, /*InsnID*/0,
16068        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16069        // GIR_Coverage, 2107,
16070        GIR_Done,
16071      // Label 944: @39251
16072      GIM_Try, /*On fail goto*//*Label 945*/ 39316, // Rule ID 3760 //
16073        GIM_CheckFeatures, GIFBS_HasMVEInt,
16074        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcls,
16075        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
16076        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
16077        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16078        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
16079        // (intrinsic_wo_chain:{ *:[v16i8] } 2434:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$val)  =>  (MVE_VCLSs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val)
16080        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16081        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16082        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16083        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCLSs8,
16084        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16085        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val
16086        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16087        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16088        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16089        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16090        GIR_EraseFromParent, /*InsnID*/0,
16091        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16092        // GIR_Coverage, 3760,
16093        GIR_Done,
16094      // Label 945: @39316
16095      GIM_Try, /*On fail goto*//*Label 946*/ 39381, // Rule ID 3762 //
16096        GIM_CheckFeatures, GIFBS_HasMVEInt,
16097        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcls,
16098        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16099        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
16100        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16101        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
16102        // (intrinsic_wo_chain:{ *:[v8i16] } 2434:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$val)  =>  (MVE_VCLSs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val)
16103        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16104        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16105        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16106        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCLSs16,
16107        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16108        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val
16109        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16110        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16111        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16112        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16113        GIR_EraseFromParent, /*InsnID*/0,
16114        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16115        // GIR_Coverage, 3762,
16116        GIR_Done,
16117      // Label 946: @39381
16118      GIM_Try, /*On fail goto*//*Label 947*/ 39446, // Rule ID 3764 //
16119        GIM_CheckFeatures, GIFBS_HasMVEInt,
16120        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcls,
16121        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16122        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
16123        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16124        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
16125        // (intrinsic_wo_chain:{ *:[v4i32] } 2434:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$val)  =>  (MVE_VCLSs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val)
16126        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16127        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16128        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16129        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCLSs32,
16130        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val
16132        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16133        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16134        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16135        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16136        GIR_EraseFromParent, /*InsnID*/0,
16137        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16138        // GIR_Coverage, 3764,
16139        GIR_Done,
16140      // Label 947: @39446
16141      GIM_Try, /*On fail goto*//*Label 948*/ 39511, // Rule ID 4064 //
16142        GIM_CheckFeatures, GIFBS_HasMVEFloat,
16143        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrintn,
16144        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16145        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
16146        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16147        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
16148        // (intrinsic_wo_chain:{ *:[v8f16] } 2516:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val)  =>  (MVE_VRINTf16N:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
16149        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16150        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16151        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16152        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16N,
16153        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16154        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val
16155        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16156        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16157        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16158        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16159        GIR_EraseFromParent, /*InsnID*/0,
16160        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16161        // GIR_Coverage, 4064,
16162        GIR_Done,
16163      // Label 948: @39511
16164      GIM_Try, /*On fail goto*//*Label 949*/ 39576, // Rule ID 4076 //
16165        GIM_CheckFeatures, GIFBS_HasMVEFloat,
16166        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrintn,
16167        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16168        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
16169        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16170        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
16171        // (intrinsic_wo_chain:{ *:[v4f32] } 2516:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val)  =>  (MVE_VRINTf32N:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
16172        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16173        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16174        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16175        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32N,
16176        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16177        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val
16178        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16179        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16180        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16181        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16182        GIR_EraseFromParent, /*InsnID*/0,
16183        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16184        // GIR_Coverage, 4076,
16185        GIR_Done,
16186      // Label 949: @39576
16187      GIM_Try, /*On fail goto*//*Label 950*/ 39627, // Rule ID 4964 //
16188        GIM_CheckFeatures, GIFBS_HasMVEInt,
16189        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vctp8,
16190        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s1,
16191        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16192        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
16193        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16194        // (intrinsic_wo_chain:{ *:[v16i1] } 2442:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn)  =>  (MVE_VCTP8:{ *:[v16i1] } rGPR:{ *:[i32] }:$Rn)
16195        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCTP8,
16196        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
16197        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16198        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16199        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16200        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16201        GIR_EraseFromParent, /*InsnID*/0,
16202        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16203        // GIR_Coverage, 4964,
16204        GIR_Done,
16205      // Label 950: @39627
16206      GIM_Try, /*On fail goto*//*Label 951*/ 39678, // Rule ID 4966 //
16207        GIM_CheckFeatures, GIFBS_HasMVEInt,
16208        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vctp16,
16209        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s1,
16210        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16211        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
16212        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16213        // (intrinsic_wo_chain:{ *:[v8i1] } 2439:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn)  =>  (MVE_VCTP16:{ *:[v8i1] } rGPR:{ *:[i32] }:$Rn)
16214        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCTP16,
16215        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
16216        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16217        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16218        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16219        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16220        GIR_EraseFromParent, /*InsnID*/0,
16221        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16222        // GIR_Coverage, 4966,
16223        GIR_Done,
16224      // Label 951: @39678
16225      GIM_Try, /*On fail goto*//*Label 952*/ 39729, // Rule ID 4968 //
16226        GIM_CheckFeatures, GIFBS_HasMVEInt,
16227        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vctp32,
16228        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s1,
16229        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16230        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
16231        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16232        // (intrinsic_wo_chain:{ *:[v4i1] } 2440:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn)  =>  (MVE_VCTP32:{ *:[v4i1] } rGPR:{ *:[i32] }:$Rn)
16233        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCTP32,
16234        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
16235        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16236        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16237        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16238        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16239        GIR_EraseFromParent, /*InsnID*/0,
16240        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16241        // GIR_Coverage, 4968,
16242        GIR_Done,
16243      // Label 952: @39729
16244      GIM_Try, /*On fail goto*//*Label 953*/ 39780, // Rule ID 4970 //
16245        GIM_CheckFeatures, GIFBS_HasMVEInt,
16246        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vctp64,
16247        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s1,
16248        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16249        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
16250        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16251        // (intrinsic_wo_chain:{ *:[v2i1] } 2441:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn)  =>  (MVE_VCTP64:{ *:[v2i1] } rGPR:{ *:[i32] }:$Rn)
16252        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCTP64,
16253        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
16254        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16255        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16256        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16257        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16258        GIR_EraseFromParent, /*InsnID*/0,
16259        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16260        // GIR_Coverage, 4970,
16261        GIR_Done,
16262      // Label 953: @39780
16263      GIM_Try, /*On fail goto*//*Label 954*/ 39827, // Rule ID 616 //
16264        GIM_CheckFeatures, GIFBS_Has8MSecExt_IsThumb,
16265        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_cmse_tt,
16266        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16267        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16268        // MIs[0] Rn
16269        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
16270        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
16271        // (intrinsic_wo_chain:{ *:[i32] } 2324:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn)  =>  (t2TT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
16272        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2TT,
16273        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
16274        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16275        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16276        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16277        GIR_EraseFromParent, /*InsnID*/0,
16278        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16279        // GIR_Coverage, 616,
16280        GIR_Done,
16281      // Label 954: @39827
16282      GIM_Try, /*On fail goto*//*Label 955*/ 39874, // Rule ID 617 //
16283        GIM_CheckFeatures, GIFBS_Has8MSecExt_IsThumb,
16284        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_cmse_ttt,
16285        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16286        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16287        // MIs[0] Rn
16288        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
16289        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
16290        // (intrinsic_wo_chain:{ *:[i32] } 2327:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn)  =>  (t2TTT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
16291        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2TTT,
16292        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
16293        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16294        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16295        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16296        GIR_EraseFromParent, /*InsnID*/0,
16297        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16298        // GIR_Coverage, 617,
16299        GIR_Done,
16300      // Label 955: @39874
16301      GIM_Try, /*On fail goto*//*Label 956*/ 39921, // Rule ID 618 //
16302        GIM_CheckFeatures, GIFBS_Has8MSecExt_IsThumb,
16303        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_cmse_tta,
16304        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16305        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16306        // MIs[0] Rn
16307        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
16308        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
16309        // (intrinsic_wo_chain:{ *:[i32] } 2325:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn)  =>  (t2TTA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
16310        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2TTA,
16311        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
16312        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16313        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16314        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16315        GIR_EraseFromParent, /*InsnID*/0,
16316        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16317        // GIR_Coverage, 618,
16318        GIR_Done,
16319      // Label 956: @39921
16320      GIM_Try, /*On fail goto*//*Label 957*/ 39968, // Rule ID 619 //
16321        GIM_CheckFeatures, GIFBS_Has8MSecExt_IsThumb,
16322        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_cmse_ttat,
16323        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16324        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16325        // MIs[0] Rn
16326        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
16327        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
16328        // (intrinsic_wo_chain:{ *:[i32] } 2326:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn)  =>  (t2TTAT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
16329        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2TTAT,
16330        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
16331        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16332        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16333        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16334        GIR_EraseFromParent, /*InsnID*/0,
16335        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16336        // GIR_Coverage, 619,
16337        GIR_Done,
16338      // Label 957: @39968
16339      GIM_Try, /*On fail goto*//*Label 958*/ 40089, // Rule ID 2708 //
16340        GIM_CheckFeatures, GIFBS_HasNEON,
16341        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1h,
16342        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16343        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16344        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
16345        // (intrinsic_wo_chain:{ *:[i32] } 2560:{ *:[iPTR] }, i32:{ *:[i32] }:$Rn)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[f32] } (SHA1H:{ *:[v16i8] } (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$Rn, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }), GPR:{ *:[i32] })
16346        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16347        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
16348        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
16349        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
16350        GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
16351        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
16352        GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16353        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
16354        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
16355        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
16356        GIR_AddImm, /*InsnID*/3, /*Imm*/0,
16357        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
16358        GIR_AddImm, /*InsnID*/3, /*Imm*/17,
16359        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPair_with_ssub_0RegClassID,
16360        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
16361        GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::SHA1H,
16362        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
16363        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
16364        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
16365        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
16366        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16367        GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, ARM::ssub_0,
16368        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, ARM::SPRRegClassID,
16369        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, ARM::MQPRRegClassID,
16370        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
16371        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
16372        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16373        GIR_EraseFromParent, /*InsnID*/0,
16374        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
16375        // GIR_Coverage, 2708,
16376        GIR_Done,
16377      // Label 958: @40089
16378      GIM_Reject,
16379    // Label 822: @40090
16380    GIM_Try, /*On fail goto*//*Label 959*/ 62799,
16381      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
16382      GIM_Try, /*On fail goto*//*Label 960*/ 40157, // Rule ID 2125 //
16383        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
16384        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uxtab16,
16385        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16386        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16387        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16388        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16389        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16390        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16391        // (intrinsic_wo_chain:{ *:[i32] } 2776:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
16392        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB16,
16393        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16394        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16396        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16397        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16398        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16399        GIR_EraseFromParent, /*InsnID*/0,
16400        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16401        // GIR_Coverage, 2125,
16402        GIR_Done,
16403      // Label 960: @40157
16404      GIM_Try, /*On fail goto*//*Label 961*/ 40255, // Rule ID 1915 //
16405        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
16406        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat,
16407        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16408        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16409        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16410        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
16411        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16412        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
16413        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16414        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16415        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
16416        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16417        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
16418        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
16419        // MIs[2] Operand 1
16420        // No operand predicates
16421        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
16422        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
16423        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
16424        // MIs[3] Operand 1
16425        // No operand predicates
16426        GIM_CheckIsSafeToFold, /*InsnID*/1,
16427        GIM_CheckIsSafeToFold, /*InsnID*/2,
16428        GIM_CheckIsSafeToFold, /*InsnID*/3,
16429        // (intrinsic_wo_chain:{ *:[i32] } 2771:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos)  =>  (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft)
16430        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAT,
16431        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16432        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos
16433        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
16434        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft
16435        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16436        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16437        GIR_EraseFromParent, /*InsnID*/0,
16438        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16439        // GIR_Coverage, 1915,
16440        GIR_Done,
16441      // Label 961: @40255
16442      GIM_Try, /*On fail goto*//*Label 962*/ 40353, // Rule ID 2165 //
16443        GIM_CheckFeatures, GIFBS_IsThumb2,
16444        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat,
16445        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16446        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16447        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16448        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16449        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16450        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
16451        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16452        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16453        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
16454        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16455        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
16456        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
16457        // MIs[2] Operand 1
16458        // No operand predicates
16459        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
16460        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
16461        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
16462        // MIs[3] Operand 1
16463        // No operand predicates
16464        GIM_CheckIsSafeToFold, /*InsnID*/1,
16465        GIM_CheckIsSafeToFold, /*InsnID*/2,
16466        GIM_CheckIsSafeToFold, /*InsnID*/3,
16467        // (intrinsic_wo_chain:{ *:[i32] } 2771:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos)  =>  (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft)
16468        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAT,
16469        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16470        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos
16471        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
16472        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft
16473        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16474        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16475        GIR_EraseFromParent, /*InsnID*/0,
16476        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16477        // GIR_Coverage, 2165,
16478        GIR_Done,
16479      // Label 962: @40353
16480      GIM_Try, /*On fail goto*//*Label 963*/ 40437, // Rule ID 5530 //
16481        GIM_CheckFeatures, GIFBS_IsARM,
16482        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
16483        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16484        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16485        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16486        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
16487        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16488        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
16489        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16490        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
16491        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16492        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
16493        // MIs[1] Rn
16494        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16495        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
16496        GIM_CheckIsSafeToFold, /*InsnID*/1,
16497        // (intrinsic_wo_chain:{ *:[i32] } 2694:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 2694:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn), GPRnopc:{ *:[i32] }:$Rm)  =>  (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
16498        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDADD,
16499        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16500        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16501        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16502        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16503        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16504        GIR_EraseFromParent, /*InsnID*/0,
16505        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16506        // GIR_Coverage, 5530,
16507        GIR_Done,
16508      // Label 963: @40437
16509      GIM_Try, /*On fail goto*//*Label 964*/ 40521, // Rule ID 5787 //
16510        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
16511        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
16512        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16513        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16514        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16515        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16516        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16517        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
16518        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16519        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
16520        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16521        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16522        // MIs[1] Rn
16523        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16524        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16525        GIM_CheckIsSafeToFold, /*InsnID*/1,
16526        // (intrinsic_wo_chain:{ *:[i32] } 2694:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 2694:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm)  =>  (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
16527        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDADD,
16528        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16529        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
16530        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16531        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16532        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16533        GIR_EraseFromParent, /*InsnID*/0,
16534        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16535        // GIR_Coverage, 5787,
16536        GIR_Done,
16537      // Label 964: @40521
16538      GIM_Try, /*On fail goto*//*Label 965*/ 40605, // Rule ID 109 //
16539        GIM_CheckFeatures, GIFBS_IsARM,
16540        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
16541        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16542        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16543        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16544        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
16545        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
16546        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16547        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
16548        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16549        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
16550        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16551        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
16552        // MIs[1] Rn
16553        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16554        GIM_CheckIsSafeToFold, /*InsnID*/1,
16555        // (intrinsic_wo_chain:{ *:[i32] } 2694:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 2694:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn))  =>  (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
16556        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDADD,
16557        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16558        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
16559        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16560        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16561        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16562        GIR_EraseFromParent, /*InsnID*/0,
16563        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16564        // GIR_Coverage, 109,
16565        GIR_Done,
16566      // Label 965: @40605
16567      GIM_Try, /*On fail goto*//*Label 966*/ 40689, // Rule ID 110 //
16568        GIM_CheckFeatures, GIFBS_IsARM,
16569        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub,
16570        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16571        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16572        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16573        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
16574        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
16575        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16576        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
16577        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16578        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
16579        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16580        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
16581        // MIs[1] Rn
16582        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16583        GIM_CheckIsSafeToFold, /*InsnID*/1,
16584        // (intrinsic_wo_chain:{ *:[i32] } 2699:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 2694:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn))  =>  (QDSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
16585        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDSUB,
16586        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16587        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
16588        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16589        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16590        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16591        GIR_EraseFromParent, /*InsnID*/0,
16592        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16593        // GIR_Coverage, 110,
16594        GIR_Done,
16595      // Label 966: @40689
16596      GIM_Try, /*On fail goto*//*Label 967*/ 40773, // Rule ID 2143 //
16597        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
16598        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
16599        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16600        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16601        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16602        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16603        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16604        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16605        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
16606        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16607        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
16608        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16609        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16610        // MIs[1] Rn
16611        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16612        GIM_CheckIsSafeToFold, /*InsnID*/1,
16613        // (intrinsic_wo_chain:{ *:[i32] } 2694:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 2694:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn))  =>  (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
16614        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDADD,
16615        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16616        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
16617        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16618        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16619        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16620        GIR_EraseFromParent, /*InsnID*/0,
16621        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16622        // GIR_Coverage, 2143,
16623        GIR_Done,
16624      // Label 967: @40773
16625      GIM_Try, /*On fail goto*//*Label 968*/ 40857, // Rule ID 2144 //
16626        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
16627        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub,
16628        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16629        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16630        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16631        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16632        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16633        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16634        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
16635        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16636        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
16637        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16638        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16639        // MIs[1] Rn
16640        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16641        GIM_CheckIsSafeToFold, /*InsnID*/1,
16642        // (intrinsic_wo_chain:{ *:[i32] } 2699:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 2694:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn))  =>  (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
16643        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDSUB,
16644        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16645        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
16646        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16647        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16648        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16649        GIR_EraseFromParent, /*InsnID*/0,
16650        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16651        // GIR_Coverage, 2144,
16652        GIR_Done,
16653      // Label 968: @40857
16654      GIM_Try, /*On fail goto*//*Label 969*/ 40930, // Rule ID 4156 //
16655        GIM_CheckFeatures, GIFBS_HasMVEFloat,
16656        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvta,
16657        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16658        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16659        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16660        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16661        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
16662        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16663        // (intrinsic_wo_chain:{ *:[v8i16] } 2450:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in)  =>  (MVE_VCVTs16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16664        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16665        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16666        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16667        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs16f16a,
16668        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16669        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16670        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16671        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16672        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16673        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16674        GIR_EraseFromParent, /*InsnID*/0,
16675        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16676        // GIR_Coverage, 4156,
16677        GIR_Done,
16678      // Label 969: @40930
16679      GIM_Try, /*On fail goto*//*Label 970*/ 41003, // Rule ID 4158 //
16680        GIM_CheckFeatures, GIFBS_HasMVEFloat,
16681        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtn,
16682        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16683        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16684        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16685        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16686        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
16687        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16688        // (intrinsic_wo_chain:{ *:[v8i16] } 2454:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in)  =>  (MVE_VCVTs16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16689        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16690        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16691        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16692        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs16f16n,
16693        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16694        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16695        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16696        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16697        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16698        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16699        GIR_EraseFromParent, /*InsnID*/0,
16700        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16701        // GIR_Coverage, 4158,
16702        GIR_Done,
16703      // Label 970: @41003
16704      GIM_Try, /*On fail goto*//*Label 971*/ 41076, // Rule ID 4160 //
16705        GIM_CheckFeatures, GIFBS_HasMVEFloat,
16706        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtp,
16707        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16708        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16709        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16710        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16711        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
16712        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16713        // (intrinsic_wo_chain:{ *:[v8i16] } 2456:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in)  =>  (MVE_VCVTs16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16714        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16715        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16716        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16717        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs16f16p,
16718        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16719        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16720        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16721        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16722        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16723        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16724        GIR_EraseFromParent, /*InsnID*/0,
16725        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16726        // GIR_Coverage, 4160,
16727        GIR_Done,
16728      // Label 971: @41076
16729      GIM_Try, /*On fail goto*//*Label 972*/ 41149, // Rule ID 4162 //
16730        GIM_CheckFeatures, GIFBS_HasMVEFloat,
16731        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtm,
16732        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16733        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16734        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16735        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16736        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
16737        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16738        // (intrinsic_wo_chain:{ *:[v8i16] } 2452:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in)  =>  (MVE_VCVTs16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16739        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16740        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16741        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16742        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs16f16m,
16743        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16744        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16745        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16746        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16747        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16748        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16749        GIR_EraseFromParent, /*InsnID*/0,
16750        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16751        // GIR_Coverage, 4162,
16752        GIR_Done,
16753      // Label 972: @41149
16754      GIM_Try, /*On fail goto*//*Label 973*/ 41222, // Rule ID 4164 //
16755        GIM_CheckFeatures, GIFBS_HasMVEFloat,
16756        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvta,
16757        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16758        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16759        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16760        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16761        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
16762        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16763        // (intrinsic_wo_chain:{ *:[v8i16] } 2450:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in)  =>  (MVE_VCVTu16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16764        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16765        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16766        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16767        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu16f16a,
16768        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16769        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16770        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16771        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16772        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16773        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16774        GIR_EraseFromParent, /*InsnID*/0,
16775        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16776        // GIR_Coverage, 4164,
16777        GIR_Done,
16778      // Label 973: @41222
16779      GIM_Try, /*On fail goto*//*Label 974*/ 41295, // Rule ID 4166 //
16780        GIM_CheckFeatures, GIFBS_HasMVEFloat,
16781        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtn,
16782        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16783        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16784        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16785        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16786        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
16787        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16788        // (intrinsic_wo_chain:{ *:[v8i16] } 2454:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in)  =>  (MVE_VCVTu16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16789        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16790        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16791        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16792        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu16f16n,
16793        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16794        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16795        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16796        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16797        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16798        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16799        GIR_EraseFromParent, /*InsnID*/0,
16800        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16801        // GIR_Coverage, 4166,
16802        GIR_Done,
16803      // Label 974: @41295
16804      GIM_Try, /*On fail goto*//*Label 975*/ 41368, // Rule ID 4168 //
16805        GIM_CheckFeatures, GIFBS_HasMVEFloat,
16806        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtp,
16807        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16808        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16809        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16810        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16811        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
16812        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16813        // (intrinsic_wo_chain:{ *:[v8i16] } 2456:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in)  =>  (MVE_VCVTu16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16814        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16815        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16816        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16817        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu16f16p,
16818        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16819        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16820        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16821        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16822        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16823        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16824        GIR_EraseFromParent, /*InsnID*/0,
16825        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16826        // GIR_Coverage, 4168,
16827        GIR_Done,
16828      // Label 975: @41368
16829      GIM_Try, /*On fail goto*//*Label 976*/ 41441, // Rule ID 4170 //
16830        GIM_CheckFeatures, GIFBS_HasMVEFloat,
16831        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtm,
16832        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16833        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16834        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16835        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16836        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
16837        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16838        // (intrinsic_wo_chain:{ *:[v8i16] } 2452:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in)  =>  (MVE_VCVTu16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16839        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16840        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16841        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16842        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu16f16m,
16843        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16844        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16845        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16846        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16847        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16848        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16849        GIR_EraseFromParent, /*InsnID*/0,
16850        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16851        // GIR_Coverage, 4170,
16852        GIR_Done,
16853      // Label 976: @41441
16854      GIM_Try, /*On fail goto*//*Label 977*/ 41514, // Rule ID 4172 //
16855        GIM_CheckFeatures, GIFBS_HasMVEFloat,
16856        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvta,
16857        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16858        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16859        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16860        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16861        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
16862        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16863        // (intrinsic_wo_chain:{ *:[v4i32] } 2450:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in)  =>  (MVE_VCVTs32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16864        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16865        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16866        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16867        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs32f32a,
16868        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16869        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16870        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16871        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16872        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16873        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16874        GIR_EraseFromParent, /*InsnID*/0,
16875        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16876        // GIR_Coverage, 4172,
16877        GIR_Done,
16878      // Label 977: @41514
16879      GIM_Try, /*On fail goto*//*Label 978*/ 41587, // Rule ID 4174 //
16880        GIM_CheckFeatures, GIFBS_HasMVEFloat,
16881        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtn,
16882        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16883        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16884        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16885        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16886        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
16887        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16888        // (intrinsic_wo_chain:{ *:[v4i32] } 2454:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in)  =>  (MVE_VCVTs32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16889        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16890        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16891        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16892        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs32f32n,
16893        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16894        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16895        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16896        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16897        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16898        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16899        GIR_EraseFromParent, /*InsnID*/0,
16900        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16901        // GIR_Coverage, 4174,
16902        GIR_Done,
16903      // Label 978: @41587
16904      GIM_Try, /*On fail goto*//*Label 979*/ 41660, // Rule ID 4176 //
16905        GIM_CheckFeatures, GIFBS_HasMVEFloat,
16906        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtp,
16907        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16908        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16909        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16910        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16911        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
16912        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16913        // (intrinsic_wo_chain:{ *:[v4i32] } 2456:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in)  =>  (MVE_VCVTs32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16914        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16915        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16916        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16917        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs32f32p,
16918        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16919        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16920        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16921        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16922        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16923        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16924        GIR_EraseFromParent, /*InsnID*/0,
16925        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16926        // GIR_Coverage, 4176,
16927        GIR_Done,
16928      // Label 979: @41660
16929      GIM_Try, /*On fail goto*//*Label 980*/ 41733, // Rule ID 4178 //
16930        GIM_CheckFeatures, GIFBS_HasMVEFloat,
16931        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtm,
16932        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16933        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16934        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16935        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16936        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
16937        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16938        // (intrinsic_wo_chain:{ *:[v4i32] } 2452:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in)  =>  (MVE_VCVTs32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16939        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16940        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16941        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16942        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs32f32m,
16943        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16944        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16945        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16946        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16947        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16948        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16949        GIR_EraseFromParent, /*InsnID*/0,
16950        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16951        // GIR_Coverage, 4178,
16952        GIR_Done,
16953      // Label 980: @41733
16954      GIM_Try, /*On fail goto*//*Label 981*/ 41806, // Rule ID 4180 //
16955        GIM_CheckFeatures, GIFBS_HasMVEFloat,
16956        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvta,
16957        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16958        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16959        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16960        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16961        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
16962        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16963        // (intrinsic_wo_chain:{ *:[v4i32] } 2450:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in)  =>  (MVE_VCVTu32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16964        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16965        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16966        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16967        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu32f32a,
16968        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16969        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16970        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16971        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16972        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16973        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16974        GIR_EraseFromParent, /*InsnID*/0,
16975        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16976        // GIR_Coverage, 4180,
16977        GIR_Done,
16978      // Label 981: @41806
16979      GIM_Try, /*On fail goto*//*Label 982*/ 41879, // Rule ID 4182 //
16980        GIM_CheckFeatures, GIFBS_HasMVEFloat,
16981        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtn,
16982        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16983        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16984        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16985        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16986        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
16987        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16988        // (intrinsic_wo_chain:{ *:[v4i32] } 2454:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in)  =>  (MVE_VCVTu32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16989        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16990        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16991        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16992        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu32f32n,
16993        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16994        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16995        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16996        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16997        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16998        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16999        GIR_EraseFromParent, /*InsnID*/0,
17000        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17001        // GIR_Coverage, 4182,
17002        GIR_Done,
17003      // Label 982: @41879
17004      GIM_Try, /*On fail goto*//*Label 983*/ 41952, // Rule ID 4184 //
17005        GIM_CheckFeatures, GIFBS_HasMVEFloat,
17006        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtp,
17007        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17008        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17009        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
17010        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
17011        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
17012        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
17013        // (intrinsic_wo_chain:{ *:[v4i32] } 2456:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in)  =>  (MVE_VCVTu32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
17014        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17015        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
17016        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
17017        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu32f32p,
17018        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
17019        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
17020        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
17021        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17022        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17023        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17024        GIR_EraseFromParent, /*InsnID*/0,
17025        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17026        // GIR_Coverage, 4184,
17027        GIR_Done,
17028      // Label 983: @41952
17029      GIM_Try, /*On fail goto*//*Label 984*/ 42025, // Rule ID 4186 //
17030        GIM_CheckFeatures, GIFBS_HasMVEFloat,
17031        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtm,
17032        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17033        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17034        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
17035        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
17036        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
17037        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
17038        // (intrinsic_wo_chain:{ *:[v4i32] } 2452:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in)  =>  (MVE_VCVTu32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
17039        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17040        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
17041        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
17042        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu32f32m,
17043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
17044        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
17045        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
17046        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17047        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17048        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17049        GIR_EraseFromParent, /*InsnID*/0,
17050        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17051        // GIR_Coverage, 4186,
17052        GIR_Done,
17053      // Label 984: @42025
17054      GIM_Try, /*On fail goto*//*Label 985*/ 42098, // Rule ID 4630 //
17055        GIM_CheckFeatures, GIFBS_HasMVEFloat,
17056        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_widen,
17057        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17058        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17059        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17060        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
17061        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
17062        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
17063        // (intrinsic_wo_chain:{ *:[v4f32] } 2448:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 0:{ *:[i32] })  =>  (MVE_VCVTf32f16bh:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm)
17064        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17065        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
17066        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
17067        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf32f16bh,
17068        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
17069        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
17070        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
17071        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17072        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17073        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17074        GIR_EraseFromParent, /*InsnID*/0,
17075        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17076        // GIR_Coverage, 4630,
17077        GIR_Done,
17078      // Label 985: @42098
17079      GIM_Try, /*On fail goto*//*Label 986*/ 42171, // Rule ID 4636 //
17080        GIM_CheckFeatures, GIFBS_HasMVEFloat,
17081        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_widen,
17082        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17083        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17084        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17085        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
17086        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
17087        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
17088        // (intrinsic_wo_chain:{ *:[v4f32] } 2448:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 1:{ *:[i32] })  =>  (MVE_VCVTf32f16th:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm)
17089        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17090        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
17091        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
17092        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf32f16th,
17093        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
17094        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
17095        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
17096        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17097        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17098        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17099        GIR_EraseFromParent, /*InsnID*/0,
17100        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17101        // GIR_Coverage, 4636,
17102        GIR_Done,
17103      // Label 986: @42171
17104      GIM_Try, /*On fail goto*//*Label 987*/ 42240, // Rule ID 1908 //
17105        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
17106        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat,
17107        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17108        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17109        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17110        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17111        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17112        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17113        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17114        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
17115        // MIs[1] Operand 1
17116        // No operand predicates
17117        GIM_CheckIsSafeToFold, /*InsnID*/1,
17118        // (intrinsic_wo_chain:{ *:[i32] } 2771:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos)  =>  (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, 0:{ *:[i32] })
17119        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAT,
17120        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17121        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
17122        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
17123        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
17124        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17125        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17126        GIR_EraseFromParent, /*InsnID*/0,
17127        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17128        // GIR_Coverage, 1908,
17129        GIR_Done,
17130      // Label 987: @42240
17131      GIM_Try, /*On fail goto*//*Label 988*/ 42306, // Rule ID 1912 //
17132        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
17133        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat16,
17134        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17135        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17136        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17137        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17138        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17139        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17140        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17141        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
17142        // MIs[1] Operand 1
17143        // No operand predicates
17144        GIM_CheckIsSafeToFold, /*InsnID*/1,
17145        // (intrinsic_wo_chain:{ *:[i32] } 2772:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos)  =>  (USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPRnopc:{ *:[i32] }:$a)
17146        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAT16,
17147        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17148        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
17149        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
17150        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17151        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17152        GIR_EraseFromParent, /*InsnID*/0,
17153        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17154        // GIR_Coverage, 1912,
17155        GIR_Done,
17156      // Label 988: @42306
17157      GIM_Try, /*On fail goto*//*Label 989*/ 42375, // Rule ID 2160 //
17158        GIM_CheckFeatures, GIFBS_IsThumb2,
17159        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat,
17160        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17161        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17162        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17163        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
17164        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
17165        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17166        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17167        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
17168        // MIs[1] Operand 1
17169        // No operand predicates
17170        GIM_CheckIsSafeToFold, /*InsnID*/1,
17171        // (intrinsic_wo_chain:{ *:[i32] } 2771:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos)  =>  (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPR:{ *:[i32] }:$a, 0:{ *:[i32] })
17172        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAT,
17173        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17174        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
17175        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
17176        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
17177        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17178        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17179        GIR_EraseFromParent, /*InsnID*/0,
17180        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17181        // GIR_Coverage, 2160,
17182        GIR_Done,
17183      // Label 989: @42375
17184      GIM_Try, /*On fail goto*//*Label 990*/ 42441, // Rule ID 2162 //
17185        GIM_CheckFeatures, GIFBS_IsThumb2,
17186        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat16,
17187        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17188        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17189        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17190        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
17191        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
17192        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17193        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17194        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
17195        // MIs[1] Operand 1
17196        // No operand predicates
17197        GIM_CheckIsSafeToFold, /*InsnID*/1,
17198        // (intrinsic_wo_chain:{ *:[i32] } 2772:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos)  =>  (t2USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPR:{ *:[i32] }:$a)
17199        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAT16,
17200        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17201        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
17202        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
17203        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17204        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17205        GIR_EraseFromParent, /*InsnID*/0,
17206        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17207        // GIR_Coverage, 2162,
17208        GIR_Done,
17209      // Label 990: @42441
17210      GIM_Try, /*On fail goto*//*Label 991*/ 42523, // Rule ID 4028 //
17211        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshlu_imm,
17212        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
17213        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
17214        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17215        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
17216        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
17217        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17218        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17219        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_7,
17220        // MIs[1] Operand 1
17221        // No operand predicates
17222        GIM_CheckIsSafeToFold, /*InsnID*/1,
17223        // (intrinsic_wo_chain:{ *:[v16i8] } 2509:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)  =>  (MVE_VQSHLU_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
17224        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17225        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
17226        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
17227        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLU_imms8,
17228        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
17229        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
17230        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17231        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
17232        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17233        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17234        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17235        GIR_EraseFromParent, /*InsnID*/0,
17236        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17237        // GIR_Coverage, 4028,
17238        GIR_Done,
17239      // Label 991: @42523
17240      GIM_Try, /*On fail goto*//*Label 992*/ 42605, // Rule ID 4030 //
17241        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshlu_imm,
17242        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17243        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17244        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17245        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
17246        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
17247        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17248        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17249        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
17250        // MIs[1] Operand 1
17251        // No operand predicates
17252        GIM_CheckIsSafeToFold, /*InsnID*/1,
17253        // (intrinsic_wo_chain:{ *:[v8i16] } 2509:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)  =>  (MVE_VQSHLU_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
17254        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17255        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
17256        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
17257        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLU_imms16,
17258        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
17259        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
17260        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17261        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
17262        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17263        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17264        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17265        GIR_EraseFromParent, /*InsnID*/0,
17266        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17267        // GIR_Coverage, 4030,
17268        GIR_Done,
17269      // Label 992: @42605
17270      GIM_Try, /*On fail goto*//*Label 993*/ 42687, // Rule ID 4032 //
17271        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshlu_imm,
17272        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17273        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17274        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17275        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
17276        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
17277        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17278        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17279        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
17280        // MIs[1] Operand 1
17281        // No operand predicates
17282        GIM_CheckIsSafeToFold, /*InsnID*/1,
17283        // (intrinsic_wo_chain:{ *:[v4i32] } 2509:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)  =>  (MVE_VQSHLU_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
17284        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17285        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
17286        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
17287        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLU_imms32,
17288        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
17289        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
17290        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17291        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
17292        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17293        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17294        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17295        GIR_EraseFromParent, /*InsnID*/0,
17296        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17297        // GIR_Coverage, 4032,
17298        GIR_Done,
17299      // Label 993: @42687
17300      GIM_Try, /*On fail goto*//*Label 994*/ 42750, // Rule ID 1670 //
17301        GIM_CheckFeatures, GIFBS_HasNEON,
17302        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs,
17303        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
17304        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
17305        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17306        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17307        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17308        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17309        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17310        // MIs[1] Operand 1
17311        // No operand predicates
17312        GIM_CheckIsSafeToFold, /*InsnID*/1,
17313        // (intrinsic_wo_chain:{ *:[v2i32] } 2587:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTf2xsd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17314        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xsd,
17315        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17316        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17317        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17318        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17319        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17320        GIR_EraseFromParent, /*InsnID*/0,
17321        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17322        // GIR_Coverage, 1670,
17323        GIR_Done,
17324      // Label 994: @42750
17325      GIM_Try, /*On fail goto*//*Label 995*/ 42813, // Rule ID 1671 //
17326        GIM_CheckFeatures, GIFBS_HasNEON,
17327        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu,
17328        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
17329        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
17330        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17331        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17332        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17333        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17334        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17335        // MIs[1] Operand 1
17336        // No operand predicates
17337        GIM_CheckIsSafeToFold, /*InsnID*/1,
17338        // (intrinsic_wo_chain:{ *:[v2i32] } 2588:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTf2xud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17339        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xud,
17340        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17341        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17342        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17343        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17344        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17345        GIR_EraseFromParent, /*InsnID*/0,
17346        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17347        // GIR_Coverage, 1671,
17348        GIR_Done,
17349      // Label 995: @42813
17350      GIM_Try, /*On fail goto*//*Label 996*/ 42876, // Rule ID 1672 //
17351        GIM_CheckFeatures, GIFBS_HasNEON,
17352        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp,
17353        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
17354        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
17355        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17356        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17357        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17358        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17359        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17360        // MIs[1] Operand 1
17361        // No operand predicates
17362        GIM_CheckIsSafeToFold, /*InsnID*/1,
17363        // (intrinsic_wo_chain:{ *:[v2f32] } 2590:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17364        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2fd,
17365        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17366        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17367        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17368        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17369        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17370        GIR_EraseFromParent, /*InsnID*/0,
17371        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17372        // GIR_Coverage, 1672,
17373        GIR_Done,
17374      // Label 996: @42876
17375      GIM_Try, /*On fail goto*//*Label 997*/ 42939, // Rule ID 1673 //
17376        GIM_CheckFeatures, GIFBS_HasNEON,
17377        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp,
17378        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
17379        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
17380        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17381        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17382        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17383        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17384        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17385        // MIs[1] Operand 1
17386        // No operand predicates
17387        GIM_CheckIsSafeToFold, /*InsnID*/1,
17388        // (intrinsic_wo_chain:{ *:[v2f32] } 2591:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17389        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2fd,
17390        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17391        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17392        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17393        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17394        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17395        GIR_EraseFromParent, /*InsnID*/0,
17396        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17397        // GIR_Coverage, 1673,
17398        GIR_Done,
17399      // Label 997: @42939
17400      GIM_Try, /*On fail goto*//*Label 998*/ 43002, // Rule ID 1674 //
17401        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
17402        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs,
17403        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
17404        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
17405        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17406        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17407        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17408        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17409        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17410        // MIs[1] Operand 1
17411        // No operand predicates
17412        GIM_CheckIsSafeToFold, /*InsnID*/1,
17413        // (intrinsic_wo_chain:{ *:[v4i16] } 2587:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTh2xsd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17414        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xsd,
17415        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17416        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17417        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17418        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17419        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17420        GIR_EraseFromParent, /*InsnID*/0,
17421        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17422        // GIR_Coverage, 1674,
17423        GIR_Done,
17424      // Label 998: @43002
17425      GIM_Try, /*On fail goto*//*Label 999*/ 43065, // Rule ID 1675 //
17426        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
17427        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu,
17428        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
17429        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
17430        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17431        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17432        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17433        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17434        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17435        // MIs[1] Operand 1
17436        // No operand predicates
17437        GIM_CheckIsSafeToFold, /*InsnID*/1,
17438        // (intrinsic_wo_chain:{ *:[v4i16] } 2588:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTh2xud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17439        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xud,
17440        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17441        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17442        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17443        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17444        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17445        GIR_EraseFromParent, /*InsnID*/0,
17446        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17447        // GIR_Coverage, 1675,
17448        GIR_Done,
17449      // Label 999: @43065
17450      GIM_Try, /*On fail goto*//*Label 1000*/ 43128, // Rule ID 1676 //
17451        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
17452        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp,
17453        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
17454        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
17455        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17456        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17457        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17458        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17459        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17460        // MIs[1] Operand 1
17461        // No operand predicates
17462        GIM_CheckIsSafeToFold, /*InsnID*/1,
17463        // (intrinsic_wo_chain:{ *:[v4f16] } 2590:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17464        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2hd,
17465        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17466        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17467        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17468        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17469        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17470        GIR_EraseFromParent, /*InsnID*/0,
17471        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17472        // GIR_Coverage, 1676,
17473        GIR_Done,
17474      // Label 1000: @43128
17475      GIM_Try, /*On fail goto*//*Label 1001*/ 43191, // Rule ID 1677 //
17476        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
17477        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp,
17478        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
17479        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
17480        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17481        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17482        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17483        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17484        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17485        // MIs[1] Operand 1
17486        // No operand predicates
17487        GIM_CheckIsSafeToFold, /*InsnID*/1,
17488        // (intrinsic_wo_chain:{ *:[v4f16] } 2591:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17489        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2hd,
17490        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17491        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17492        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17493        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17494        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17495        GIR_EraseFromParent, /*InsnID*/0,
17496        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17497        // GIR_Coverage, 1677,
17498        GIR_Done,
17499      // Label 1001: @43191
17500      GIM_Try, /*On fail goto*//*Label 1002*/ 43254, // Rule ID 1678 //
17501        GIM_CheckFeatures, GIFBS_HasNEON,
17502        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs,
17503        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17504        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17505        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17506        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17507        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17508        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17509        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17510        // MIs[1] Operand 1
17511        // No operand predicates
17512        GIM_CheckIsSafeToFold, /*InsnID*/1,
17513        // (intrinsic_wo_chain:{ *:[v4i32] } 2587:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTf2xsq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17514        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xsq,
17515        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17516        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17517        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17518        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17519        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17520        GIR_EraseFromParent, /*InsnID*/0,
17521        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17522        // GIR_Coverage, 1678,
17523        GIR_Done,
17524      // Label 1002: @43254
17525      GIM_Try, /*On fail goto*//*Label 1003*/ 43317, // Rule ID 1679 //
17526        GIM_CheckFeatures, GIFBS_HasNEON,
17527        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu,
17528        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17529        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17530        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17531        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17532        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17533        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17534        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17535        // MIs[1] Operand 1
17536        // No operand predicates
17537        GIM_CheckIsSafeToFold, /*InsnID*/1,
17538        // (intrinsic_wo_chain:{ *:[v4i32] } 2588:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTf2xuq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17539        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xuq,
17540        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17541        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17542        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17543        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17544        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17545        GIR_EraseFromParent, /*InsnID*/0,
17546        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17547        // GIR_Coverage, 1679,
17548        GIR_Done,
17549      // Label 1003: @43317
17550      GIM_Try, /*On fail goto*//*Label 1004*/ 43380, // Rule ID 1680 //
17551        GIM_CheckFeatures, GIFBS_HasNEON,
17552        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp,
17553        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17554        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17555        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17556        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17557        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17558        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17559        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17560        // MIs[1] Operand 1
17561        // No operand predicates
17562        GIM_CheckIsSafeToFold, /*InsnID*/1,
17563        // (intrinsic_wo_chain:{ *:[v4f32] } 2590:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17564        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2fq,
17565        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17566        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17567        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17568        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17569        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17570        GIR_EraseFromParent, /*InsnID*/0,
17571        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17572        // GIR_Coverage, 1680,
17573        GIR_Done,
17574      // Label 1004: @43380
17575      GIM_Try, /*On fail goto*//*Label 1005*/ 43443, // Rule ID 1681 //
17576        GIM_CheckFeatures, GIFBS_HasNEON,
17577        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp,
17578        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17579        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17580        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17581        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17582        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17583        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17584        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17585        // MIs[1] Operand 1
17586        // No operand predicates
17587        GIM_CheckIsSafeToFold, /*InsnID*/1,
17588        // (intrinsic_wo_chain:{ *:[v4f32] } 2591:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17589        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2fq,
17590        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17591        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17592        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17593        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17594        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17595        GIR_EraseFromParent, /*InsnID*/0,
17596        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17597        // GIR_Coverage, 1681,
17598        GIR_Done,
17599      // Label 1005: @43443
17600      GIM_Try, /*On fail goto*//*Label 1006*/ 43506, // Rule ID 1682 //
17601        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
17602        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs,
17603        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17604        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17605        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17606        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17607        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17608        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17609        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17610        // MIs[1] Operand 1
17611        // No operand predicates
17612        GIM_CheckIsSafeToFold, /*InsnID*/1,
17613        // (intrinsic_wo_chain:{ *:[v8i16] } 2587:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTh2xsq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17614        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xsq,
17615        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17616        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17617        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17618        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17619        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17620        GIR_EraseFromParent, /*InsnID*/0,
17621        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17622        // GIR_Coverage, 1682,
17623        GIR_Done,
17624      // Label 1006: @43506
17625      GIM_Try, /*On fail goto*//*Label 1007*/ 43569, // Rule ID 1683 //
17626        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
17627        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu,
17628        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17629        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17630        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17631        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17632        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17633        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17634        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17635        // MIs[1] Operand 1
17636        // No operand predicates
17637        GIM_CheckIsSafeToFold, /*InsnID*/1,
17638        // (intrinsic_wo_chain:{ *:[v8i16] } 2588:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTh2xuq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17639        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xuq,
17640        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17641        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17642        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17643        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17644        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17645        GIR_EraseFromParent, /*InsnID*/0,
17646        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17647        // GIR_Coverage, 1683,
17648        GIR_Done,
17649      // Label 1007: @43569
17650      GIM_Try, /*On fail goto*//*Label 1008*/ 43632, // Rule ID 1684 //
17651        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
17652        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp,
17653        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17654        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17655        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17656        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17657        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17658        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17659        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17660        // MIs[1] Operand 1
17661        // No operand predicates
17662        GIM_CheckIsSafeToFold, /*InsnID*/1,
17663        // (intrinsic_wo_chain:{ *:[v8f16] } 2590:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17664        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2hq,
17665        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17666        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17667        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17668        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17669        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17670        GIR_EraseFromParent, /*InsnID*/0,
17671        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17672        // GIR_Coverage, 1684,
17673        GIR_Done,
17674      // Label 1008: @43632
17675      GIM_Try, /*On fail goto*//*Label 1009*/ 43695, // Rule ID 1685 //
17676        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
17677        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp,
17678        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17679        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17680        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17681        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17682        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17683        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17684        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17685        // MIs[1] Operand 1
17686        // No operand predicates
17687        GIM_CheckIsSafeToFold, /*InsnID*/1,
17688        // (intrinsic_wo_chain:{ *:[v8f16] } 2591:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17689        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2hq,
17690        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17691        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17692        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17693        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17694        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17695        GIR_EraseFromParent, /*InsnID*/0,
17696        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17697        // GIR_Coverage, 1685,
17698        GIR_Done,
17699      // Label 1009: @43695
17700      GIM_Try, /*On fail goto*//*Label 1010*/ 43758, // Rule ID 1748 //
17701        GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline,
17702        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_sqshl,
17703        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17704        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17705        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17706        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
17707        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
17708        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17709        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17710        // MIs[1] Operand 1
17711        // No operand predicates
17712        GIM_CheckIsSafeToFold, /*InsnID*/1,
17713        // (intrinsic_wo_chain:{ *:[i32] } 2414:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)  =>  (MVE_SQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
17714        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_SQSHL,
17715        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
17716        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
17717        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17718        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17719        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17720        GIR_EraseFromParent, /*InsnID*/0,
17721        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17722        // GIR_Coverage, 1748,
17723        GIR_Done,
17724      // Label 1010: @43758
17725      GIM_Try, /*On fail goto*//*Label 1011*/ 43821, // Rule ID 1749 //
17726        GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline,
17727        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_srshr,
17728        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17729        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17730        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17731        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
17732        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
17733        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17734        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17735        // MIs[1] Operand 1
17736        // No operand predicates
17737        GIM_CheckIsSafeToFold, /*InsnID*/1,
17738        // (intrinsic_wo_chain:{ *:[i32] } 2416:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)  =>  (MVE_SRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
17739        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_SRSHR,
17740        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
17741        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
17742        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17743        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17744        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17745        GIR_EraseFromParent, /*InsnID*/0,
17746        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17747        // GIR_Coverage, 1749,
17748        GIR_Done,
17749      // Label 1011: @43821
17750      GIM_Try, /*On fail goto*//*Label 1012*/ 43884, // Rule ID 1750 //
17751        GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline,
17752        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_uqshl,
17753        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17754        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17755        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17756        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
17757        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
17758        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17759        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17760        // MIs[1] Operand 1
17761        // No operand predicates
17762        GIM_CheckIsSafeToFold, /*InsnID*/1,
17763        // (intrinsic_wo_chain:{ *:[i32] } 2421:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)  =>  (MVE_UQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
17764        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_UQSHL,
17765        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
17766        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
17767        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17768        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17769        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17770        GIR_EraseFromParent, /*InsnID*/0,
17771        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17772        // GIR_Coverage, 1750,
17773        GIR_Done,
17774      // Label 1012: @43884
17775      GIM_Try, /*On fail goto*//*Label 1013*/ 43947, // Rule ID 1751 //
17776        GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline,
17777        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_urshr,
17778        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17779        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17780        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17781        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
17782        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
17783        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17784        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17785        // MIs[1] Operand 1
17786        // No operand predicates
17787        GIM_CheckIsSafeToFold, /*InsnID*/1,
17788        // (intrinsic_wo_chain:{ *:[i32] } 2423:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)  =>  (MVE_URSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
17789        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_URSHR,
17790        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
17791        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
17792        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17793        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17794        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17795        GIR_EraseFromParent, /*InsnID*/0,
17796        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17797        // GIR_Coverage, 1751,
17798        GIR_Done,
17799      // Label 1013: @43947
17800      GIM_Try, /*On fail goto*//*Label 1014*/ 44006, // Rule ID 105 //
17801        GIM_CheckFeatures, GIFBS_IsARM,
17802        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd8,
17803        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17804        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17805        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17806        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17807        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17808        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17809        // (intrinsic_wo_chain:{ *:[i32] } 2696:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17810        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD8,
17811        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17812        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17813        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17814        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17815        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17816        GIR_EraseFromParent, /*InsnID*/0,
17817        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17818        // GIR_Coverage, 105,
17819        GIR_Done,
17820      // Label 1014: @44006
17821      GIM_Try, /*On fail goto*//*Label 1015*/ 44065, // Rule ID 106 //
17822        GIM_CheckFeatures, GIFBS_IsARM,
17823        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd16,
17824        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17825        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17826        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17827        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17828        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17829        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17830        // (intrinsic_wo_chain:{ *:[i32] } 2695:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17831        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD16,
17832        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17834        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17835        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17836        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17837        GIR_EraseFromParent, /*InsnID*/0,
17838        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17839        // GIR_Coverage, 106,
17840        GIR_Done,
17841      // Label 1015: @44065
17842      GIM_Try, /*On fail goto*//*Label 1016*/ 44124, // Rule ID 107 //
17843        GIM_CheckFeatures, GIFBS_IsARM,
17844        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub16,
17845        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17846        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17847        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17848        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17849        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17850        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17851        // (intrinsic_wo_chain:{ *:[i32] } 2700:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17852        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB16,
17853        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17854        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17855        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17856        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17857        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17858        GIR_EraseFromParent, /*InsnID*/0,
17859        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17860        // GIR_Coverage, 107,
17861        GIR_Done,
17862      // Label 1016: @44124
17863      GIM_Try, /*On fail goto*//*Label 1017*/ 44183, // Rule ID 108 //
17864        GIM_CheckFeatures, GIFBS_IsARM,
17865        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub8,
17866        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17867        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17868        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17869        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17870        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17871        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17872        // (intrinsic_wo_chain:{ *:[i32] } 2701:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17873        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB8,
17874        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17875        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17876        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17877        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17878        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17879        GIR_EraseFromParent, /*InsnID*/0,
17880        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17881        // GIR_Coverage, 108,
17882        GIR_Done,
17883      // Label 1017: @44183
17884      GIM_Try, /*On fail goto*//*Label 1018*/ 44242, // Rule ID 111 //
17885        GIM_CheckFeatures, GIFBS_IsARM,
17886        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub,
17887        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17888        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17889        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17890        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17891        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17892        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17893        // (intrinsic_wo_chain:{ *:[i32] } 2699:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)  =>  (QSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
17894        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB,
17895        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17896        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
17897        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
17898        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17899        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17900        GIR_EraseFromParent, /*InsnID*/0,
17901        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17902        // GIR_Coverage, 111,
17903        GIR_Done,
17904      // Label 1018: @44242
17905      GIM_Try, /*On fail goto*//*Label 1019*/ 44301, // Rule ID 112 //
17906        GIM_CheckFeatures, GIFBS_IsARM,
17907        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
17908        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17909        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17910        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17911        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17912        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17913        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17914        // (intrinsic_wo_chain:{ *:[i32] } 2694:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)  =>  (QADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
17915        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD,
17916        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17917        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
17918        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
17919        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17920        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17921        GIR_EraseFromParent, /*InsnID*/0,
17922        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17923        // GIR_Coverage, 112,
17924        GIR_Done,
17925      // Label 1019: @44301
17926      GIM_Try, /*On fail goto*//*Label 1020*/ 44360, // Rule ID 113 //
17927        GIM_CheckFeatures, GIFBS_IsARM,
17928        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd16,
17929        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17930        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17931        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17932        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17933        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17934        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17935        // (intrinsic_wo_chain:{ *:[i32] } 2763:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17936        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQADD16,
17937        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17938        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17939        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17940        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17941        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17942        GIR_EraseFromParent, /*InsnID*/0,
17943        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17944        // GIR_Coverage, 113,
17945        GIR_Done,
17946      // Label 1020: @44360
17947      GIM_Try, /*On fail goto*//*Label 1021*/ 44419, // Rule ID 114 //
17948        GIM_CheckFeatures, GIFBS_IsARM,
17949        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd8,
17950        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17951        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17952        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17953        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17954        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17955        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17956        // (intrinsic_wo_chain:{ *:[i32] } 2764:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17957        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQADD8,
17958        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17959        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17960        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17961        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17962        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17963        GIR_EraseFromParent, /*InsnID*/0,
17964        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17965        // GIR_Coverage, 114,
17966        GIR_Done,
17967      // Label 1021: @44419
17968      GIM_Try, /*On fail goto*//*Label 1022*/ 44478, // Rule ID 115 //
17969        GIM_CheckFeatures, GIFBS_IsARM,
17970        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub16,
17971        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17972        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17973        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17974        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17975        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17976        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17977        // (intrinsic_wo_chain:{ *:[i32] } 2767:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17978        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQSUB16,
17979        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17980        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17981        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17982        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17983        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17984        GIR_EraseFromParent, /*InsnID*/0,
17985        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17986        // GIR_Coverage, 115,
17987        GIR_Done,
17988      // Label 1022: @44478
17989      GIM_Try, /*On fail goto*//*Label 1023*/ 44537, // Rule ID 116 //
17990        GIM_CheckFeatures, GIFBS_IsARM,
17991        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub8,
17992        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17993        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17994        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17995        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17996        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17997        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17998        // (intrinsic_wo_chain:{ *:[i32] } 2768:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17999        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQSUB8,
18000        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18001        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18002        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18003        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18004        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18005        GIR_EraseFromParent, /*InsnID*/0,
18006        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18007        // GIR_Coverage, 116,
18008        GIR_Done,
18009      // Label 1023: @44537
18010      GIM_Try, /*On fail goto*//*Label 1024*/ 44596, // Rule ID 117 //
18011        GIM_CheckFeatures, GIFBS_IsARM,
18012        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qasx,
18013        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18014        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18015        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18016        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18017        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18018        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18019        // (intrinsic_wo_chain:{ *:[i32] } 2697:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18020        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QASX,
18021        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18022        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18023        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18024        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18025        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18026        GIR_EraseFromParent, /*InsnID*/0,
18027        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18028        // GIR_Coverage, 117,
18029        GIR_Done,
18030      // Label 1024: @44596
18031      GIM_Try, /*On fail goto*//*Label 1025*/ 44655, // Rule ID 118 //
18032        GIM_CheckFeatures, GIFBS_IsARM,
18033        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsax,
18034        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18035        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18036        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18037        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18038        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18039        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18040        // (intrinsic_wo_chain:{ *:[i32] } 2698:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18041        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSAX,
18042        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18044        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18045        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18046        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18047        GIR_EraseFromParent, /*InsnID*/0,
18048        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18049        // GIR_Coverage, 118,
18050        GIR_Done,
18051      // Label 1025: @44655
18052      GIM_Try, /*On fail goto*//*Label 1026*/ 44714, // Rule ID 119 //
18053        GIM_CheckFeatures, GIFBS_IsARM,
18054        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqasx,
18055        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18056        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18057        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18058        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18059        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18060        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18061        // (intrinsic_wo_chain:{ *:[i32] } 2765:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18062        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQASX,
18063        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18064        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18065        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18066        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18067        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18068        GIR_EraseFromParent, /*InsnID*/0,
18069        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18070        // GIR_Coverage, 119,
18071        GIR_Done,
18072      // Label 1026: @44714
18073      GIM_Try, /*On fail goto*//*Label 1027*/ 44773, // Rule ID 120 //
18074        GIM_CheckFeatures, GIFBS_IsARM,
18075        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsax,
18076        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18077        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18078        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18079        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18080        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18081        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18082        // (intrinsic_wo_chain:{ *:[i32] } 2766:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18083        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQSAX,
18084        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18085        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18086        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18087        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18088        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18089        GIR_EraseFromParent, /*InsnID*/0,
18090        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18091        // GIR_Coverage, 120,
18092        GIR_Done,
18093      // Label 1027: @44773
18094      GIM_Try, /*On fail goto*//*Label 1028*/ 44832, // Rule ID 133 //
18095        GIM_CheckFeatures, GIFBS_IsARM,
18096        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shasx,
18097        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18098        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18099        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18100        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18101        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18102        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18103        // (intrinsic_wo_chain:{ *:[i32] } 2709:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18104        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHASX,
18105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18107        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18108        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18109        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18110        GIR_EraseFromParent, /*InsnID*/0,
18111        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18112        // GIR_Coverage, 133,
18113        GIR_Done,
18114      // Label 1028: @44832
18115      GIM_Try, /*On fail goto*//*Label 1029*/ 44891, // Rule ID 134 //
18116        GIM_CheckFeatures, GIFBS_IsARM,
18117        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd16,
18118        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18119        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18120        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18121        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18122        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18123        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18124        // (intrinsic_wo_chain:{ *:[i32] } 2707:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18125        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHADD16,
18126        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18127        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18128        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18129        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18130        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18131        GIR_EraseFromParent, /*InsnID*/0,
18132        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18133        // GIR_Coverage, 134,
18134        GIR_Done,
18135      // Label 1029: @44891
18136      GIM_Try, /*On fail goto*//*Label 1030*/ 44950, // Rule ID 135 //
18137        GIM_CheckFeatures, GIFBS_IsARM,
18138        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd8,
18139        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18140        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18141        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18142        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18143        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18144        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18145        // (intrinsic_wo_chain:{ *:[i32] } 2708:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18146        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHADD8,
18147        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18148        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18149        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18150        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18151        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18152        GIR_EraseFromParent, /*InsnID*/0,
18153        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18154        // GIR_Coverage, 135,
18155        GIR_Done,
18156      // Label 1030: @44950
18157      GIM_Try, /*On fail goto*//*Label 1031*/ 45009, // Rule ID 136 //
18158        GIM_CheckFeatures, GIFBS_IsARM,
18159        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsax,
18160        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18161        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18162        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18163        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18164        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18165        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18166        // (intrinsic_wo_chain:{ *:[i32] } 2710:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18167        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHSAX,
18168        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18169        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18170        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18171        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18172        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18173        GIR_EraseFromParent, /*InsnID*/0,
18174        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18175        // GIR_Coverage, 136,
18176        GIR_Done,
18177      // Label 1031: @45009
18178      GIM_Try, /*On fail goto*//*Label 1032*/ 45068, // Rule ID 137 //
18179        GIM_CheckFeatures, GIFBS_IsARM,
18180        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub16,
18181        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18182        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18183        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18184        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18185        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18186        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18187        // (intrinsic_wo_chain:{ *:[i32] } 2711:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18188        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHSUB16,
18189        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18190        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18191        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18192        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18193        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18194        GIR_EraseFromParent, /*InsnID*/0,
18195        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18196        // GIR_Coverage, 137,
18197        GIR_Done,
18198      // Label 1032: @45068
18199      GIM_Try, /*On fail goto*//*Label 1033*/ 45127, // Rule ID 138 //
18200        GIM_CheckFeatures, GIFBS_IsARM,
18201        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub8,
18202        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18203        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18204        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18205        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18206        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18207        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18208        // (intrinsic_wo_chain:{ *:[i32] } 2712:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18209        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHSUB8,
18210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18212        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18213        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18214        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18215        GIR_EraseFromParent, /*InsnID*/0,
18216        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18217        // GIR_Coverage, 138,
18218        GIR_Done,
18219      // Label 1033: @45127
18220      GIM_Try, /*On fail goto*//*Label 1034*/ 45186, // Rule ID 139 //
18221        GIM_CheckFeatures, GIFBS_IsARM,
18222        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhasx,
18223        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18224        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18225        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18226        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18227        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18228        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18229        // (intrinsic_wo_chain:{ *:[i32] } 2758:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18230        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHASX,
18231        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18232        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18233        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18234        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18235        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18236        GIR_EraseFromParent, /*InsnID*/0,
18237        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18238        // GIR_Coverage, 139,
18239        GIR_Done,
18240      // Label 1034: @45186
18241      GIM_Try, /*On fail goto*//*Label 1035*/ 45245, // Rule ID 140 //
18242        GIM_CheckFeatures, GIFBS_IsARM,
18243        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd16,
18244        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18245        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18246        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18247        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18248        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18249        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18250        // (intrinsic_wo_chain:{ *:[i32] } 2756:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18251        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHADD16,
18252        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18253        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18254        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18255        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18256        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18257        GIR_EraseFromParent, /*InsnID*/0,
18258        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18259        // GIR_Coverage, 140,
18260        GIR_Done,
18261      // Label 1035: @45245
18262      GIM_Try, /*On fail goto*//*Label 1036*/ 45304, // Rule ID 141 //
18263        GIM_CheckFeatures, GIFBS_IsARM,
18264        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd8,
18265        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18266        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18267        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18268        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18269        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18270        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18271        // (intrinsic_wo_chain:{ *:[i32] } 2757:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18272        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHADD8,
18273        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18274        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18275        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18276        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18277        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18278        GIR_EraseFromParent, /*InsnID*/0,
18279        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18280        // GIR_Coverage, 141,
18281        GIR_Done,
18282      // Label 1036: @45304
18283      GIM_Try, /*On fail goto*//*Label 1037*/ 45363, // Rule ID 142 //
18284        GIM_CheckFeatures, GIFBS_IsARM,
18285        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsax,
18286        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18287        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18288        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18289        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18290        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18291        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18292        // (intrinsic_wo_chain:{ *:[i32] } 2759:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18293        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHSAX,
18294        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18295        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18296        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18297        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18298        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18299        GIR_EraseFromParent, /*InsnID*/0,
18300        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18301        // GIR_Coverage, 142,
18302        GIR_Done,
18303      // Label 1037: @45363
18304      GIM_Try, /*On fail goto*//*Label 1038*/ 45422, // Rule ID 143 //
18305        GIM_CheckFeatures, GIFBS_IsARM,
18306        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub16,
18307        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18308        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18309        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18310        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18311        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18312        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18313        // (intrinsic_wo_chain:{ *:[i32] } 2760:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18314        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHSUB16,
18315        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18316        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18317        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18318        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18319        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18320        GIR_EraseFromParent, /*InsnID*/0,
18321        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18322        // GIR_Coverage, 143,
18323        GIR_Done,
18324      // Label 1038: @45422
18325      GIM_Try, /*On fail goto*//*Label 1039*/ 45481, // Rule ID 144 //
18326        GIM_CheckFeatures, GIFBS_IsARM,
18327        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub8,
18328        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18329        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18330        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18331        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18332        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18333        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18334        // (intrinsic_wo_chain:{ *:[i32] } 2761:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18335        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHSUB8,
18336        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18337        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18338        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18339        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18340        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18341        GIR_EraseFromParent, /*InsnID*/0,
18342        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18343        // GIR_Coverage, 144,
18344        GIR_Done,
18345      // Label 1039: @45481
18346      GIM_Try, /*On fail goto*//*Label 1040*/ 45540, // Rule ID 145 //
18347        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
18348        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usad8,
18349        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18350        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18351        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18352        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
18353        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
18354        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
18355        // (intrinsic_wo_chain:{ *:[i32] } 2769:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (USAD8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
18356        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAD8,
18357        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18358        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18359        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18360        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18361        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18362        GIR_EraseFromParent, /*InsnID*/0,
18363        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18364        // GIR_Coverage, 145,
18365        GIR_Done,
18366      // Label 1040: @45540
18367      GIM_Try, /*On fail goto*//*Label 1041*/ 45592, // Rule ID 204 //
18368        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
18369        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32b,
18370        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18371        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18372        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18373        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18374        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18375        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18376        // (intrinsic_wo_chain:{ *:[i32] } 2328:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32B:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18377        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32B,
18378        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18379        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18380        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18381        GIR_EraseFromParent, /*InsnID*/0,
18382        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18383        // GIR_Coverage, 204,
18384        GIR_Done,
18385      // Label 1041: @45592
18386      GIM_Try, /*On fail goto*//*Label 1042*/ 45644, // Rule ID 205 //
18387        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
18388        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cb,
18389        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18390        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18391        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18392        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18393        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18394        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18395        // (intrinsic_wo_chain:{ *:[i32] } 2329:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32CB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18396        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32CB,
18397        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18398        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18399        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18400        GIR_EraseFromParent, /*InsnID*/0,
18401        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18402        // GIR_Coverage, 205,
18403        GIR_Done,
18404      // Label 1042: @45644
18405      GIM_Try, /*On fail goto*//*Label 1043*/ 45696, // Rule ID 206 //
18406        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
18407        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32h,
18408        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18409        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18410        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18411        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18412        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18413        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18414        // (intrinsic_wo_chain:{ *:[i32] } 2332:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32H:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18415        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32H,
18416        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18417        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18418        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18419        GIR_EraseFromParent, /*InsnID*/0,
18420        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18421        // GIR_Coverage, 206,
18422        GIR_Done,
18423      // Label 1043: @45696
18424      GIM_Try, /*On fail goto*//*Label 1044*/ 45748, // Rule ID 207 //
18425        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
18426        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32ch,
18427        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18428        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18429        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18430        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18431        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18432        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18433        // (intrinsic_wo_chain:{ *:[i32] } 2330:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32CH:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18434        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32CH,
18435        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18436        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18437        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18438        GIR_EraseFromParent, /*InsnID*/0,
18439        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18440        // GIR_Coverage, 207,
18441        GIR_Done,
18442      // Label 1044: @45748
18443      GIM_Try, /*On fail goto*//*Label 1045*/ 45800, // Rule ID 208 //
18444        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
18445        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32w,
18446        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18447        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18448        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18449        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18450        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18451        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18452        // (intrinsic_wo_chain:{ *:[i32] } 2333:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32W:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18453        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32W,
18454        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18455        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18456        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18457        GIR_EraseFromParent, /*InsnID*/0,
18458        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18459        // GIR_Coverage, 208,
18460        GIR_Done,
18461      // Label 1045: @45800
18462      GIM_Try, /*On fail goto*//*Label 1046*/ 45852, // Rule ID 209 //
18463        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
18464        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cw,
18465        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18466        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18467        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18468        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18469        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18470        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18471        // (intrinsic_wo_chain:{ *:[i32] } 2331:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32CW:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18472        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32CW,
18473        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18474        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18475        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18476        GIR_EraseFromParent, /*InsnID*/0,
18477        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18478        // GIR_Coverage, 209,
18479        GIR_Done,
18480      // Label 1046: @45852
18481      GIM_Try, /*On fail goto*//*Label 1047*/ 45911, // Rule ID 439 //
18482        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18483        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd16,
18484        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18485        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18486        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18487        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18488        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18489        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18490        // (intrinsic_wo_chain:{ *:[i32] } 2695:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18491        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QADD16,
18492        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18493        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18494        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18495        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18496        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18497        GIR_EraseFromParent, /*InsnID*/0,
18498        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18499        // GIR_Coverage, 439,
18500        GIR_Done,
18501      // Label 1047: @45911
18502      GIM_Try, /*On fail goto*//*Label 1048*/ 45970, // Rule ID 440 //
18503        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18504        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd8,
18505        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18506        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18507        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18508        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18509        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18510        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18511        // (intrinsic_wo_chain:{ *:[i32] } 2696:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18512        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QADD8,
18513        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18514        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18515        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18516        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18517        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18518        GIR_EraseFromParent, /*InsnID*/0,
18519        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18520        // GIR_Coverage, 440,
18521        GIR_Done,
18522      // Label 1048: @45970
18523      GIM_Try, /*On fail goto*//*Label 1049*/ 46029, // Rule ID 441 //
18524        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18525        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qasx,
18526        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18527        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18528        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18529        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18530        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18531        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18532        // (intrinsic_wo_chain:{ *:[i32] } 2697:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18533        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QASX,
18534        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18535        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18536        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18537        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18538        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18539        GIR_EraseFromParent, /*InsnID*/0,
18540        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18541        // GIR_Coverage, 441,
18542        GIR_Done,
18543      // Label 1049: @46029
18544      GIM_Try, /*On fail goto*//*Label 1050*/ 46088, // Rule ID 442 //
18545        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18546        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub8,
18547        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18548        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18549        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18550        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18551        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18552        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18553        // (intrinsic_wo_chain:{ *:[i32] } 2768:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18554        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQSUB8,
18555        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18556        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18557        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18558        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18559        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18560        GIR_EraseFromParent, /*InsnID*/0,
18561        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18562        // GIR_Coverage, 442,
18563        GIR_Done,
18564      // Label 1050: @46088
18565      GIM_Try, /*On fail goto*//*Label 1051*/ 46147, // Rule ID 443 //
18566        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18567        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsax,
18568        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18569        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18570        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18571        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18572        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18573        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18574        // (intrinsic_wo_chain:{ *:[i32] } 2698:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18575        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSAX,
18576        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18577        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18578        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18579        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18580        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18581        GIR_EraseFromParent, /*InsnID*/0,
18582        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18583        // GIR_Coverage, 443,
18584        GIR_Done,
18585      // Label 1051: @46147
18586      GIM_Try, /*On fail goto*//*Label 1052*/ 46206, // Rule ID 444 //
18587        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18588        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub16,
18589        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18590        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18591        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18592        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18593        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18594        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18595        // (intrinsic_wo_chain:{ *:[i32] } 2700:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18596        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSUB16,
18597        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18598        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18599        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18600        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18601        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18602        GIR_EraseFromParent, /*InsnID*/0,
18603        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18604        // GIR_Coverage, 444,
18605        GIR_Done,
18606      // Label 1052: @46206
18607      GIM_Try, /*On fail goto*//*Label 1053*/ 46265, // Rule ID 445 //
18608        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18609        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub8,
18610        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18611        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18612        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18613        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18614        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18615        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18616        // (intrinsic_wo_chain:{ *:[i32] } 2701:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18617        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSUB8,
18618        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18619        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18620        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18621        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18622        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18623        GIR_EraseFromParent, /*InsnID*/0,
18624        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18625        // GIR_Coverage, 445,
18626        GIR_Done,
18627      // Label 1053: @46265
18628      GIM_Try, /*On fail goto*//*Label 1054*/ 46324, // Rule ID 446 //
18629        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18630        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd16,
18631        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18632        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18633        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18634        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18635        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18636        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18637        // (intrinsic_wo_chain:{ *:[i32] } 2763:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18638        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQADD16,
18639        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18640        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18641        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18642        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18643        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18644        GIR_EraseFromParent, /*InsnID*/0,
18645        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18646        // GIR_Coverage, 446,
18647        GIR_Done,
18648      // Label 1054: @46324
18649      GIM_Try, /*On fail goto*//*Label 1055*/ 46383, // Rule ID 447 //
18650        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18651        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd8,
18652        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18653        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18654        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18655        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18656        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18657        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18658        // (intrinsic_wo_chain:{ *:[i32] } 2764:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18659        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQADD8,
18660        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18661        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18662        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18663        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18664        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18665        GIR_EraseFromParent, /*InsnID*/0,
18666        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18667        // GIR_Coverage, 447,
18668        GIR_Done,
18669      // Label 1055: @46383
18670      GIM_Try, /*On fail goto*//*Label 1056*/ 46442, // Rule ID 448 //
18671        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18672        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqasx,
18673        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18674        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18675        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18676        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18677        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18678        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18679        // (intrinsic_wo_chain:{ *:[i32] } 2765:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18680        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQASX,
18681        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18682        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18683        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18684        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18685        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18686        GIR_EraseFromParent, /*InsnID*/0,
18687        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18688        // GIR_Coverage, 448,
18689        GIR_Done,
18690      // Label 1056: @46442
18691      GIM_Try, /*On fail goto*//*Label 1057*/ 46501, // Rule ID 449 //
18692        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18693        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsax,
18694        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18695        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18696        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18697        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18698        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18699        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18700        // (intrinsic_wo_chain:{ *:[i32] } 2766:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18701        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQSAX,
18702        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18703        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18704        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18705        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18706        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18707        GIR_EraseFromParent, /*InsnID*/0,
18708        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18709        // GIR_Coverage, 449,
18710        GIR_Done,
18711      // Label 1057: @46501
18712      GIM_Try, /*On fail goto*//*Label 1058*/ 46560, // Rule ID 450 //
18713        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18714        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub16,
18715        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18716        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18717        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18718        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18719        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18720        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18721        // (intrinsic_wo_chain:{ *:[i32] } 2767:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18722        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQSUB16,
18723        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18724        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18725        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18726        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18727        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18728        GIR_EraseFromParent, /*InsnID*/0,
18729        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18730        // GIR_Coverage, 450,
18731        GIR_Done,
18732      // Label 1058: @46560
18733      GIM_Try, /*On fail goto*//*Label 1059*/ 46619, // Rule ID 463 //
18734        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18735        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shasx,
18736        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18737        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18738        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18739        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18740        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18741        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18742        // (intrinsic_wo_chain:{ *:[i32] } 2709:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18743        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHASX,
18744        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18745        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18746        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18747        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18748        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18749        GIR_EraseFromParent, /*InsnID*/0,
18750        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18751        // GIR_Coverage, 463,
18752        GIR_Done,
18753      // Label 1059: @46619
18754      GIM_Try, /*On fail goto*//*Label 1060*/ 46678, // Rule ID 464 //
18755        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18756        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd16,
18757        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18758        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18759        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18760        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18761        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18762        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18763        // (intrinsic_wo_chain:{ *:[i32] } 2707:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18764        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHADD16,
18765        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18766        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18767        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18768        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18769        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18770        GIR_EraseFromParent, /*InsnID*/0,
18771        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18772        // GIR_Coverage, 464,
18773        GIR_Done,
18774      // Label 1060: @46678
18775      GIM_Try, /*On fail goto*//*Label 1061*/ 46737, // Rule ID 465 //
18776        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18777        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd8,
18778        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18779        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18780        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18781        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18782        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18783        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18784        // (intrinsic_wo_chain:{ *:[i32] } 2708:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18785        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHADD8,
18786        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18787        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18788        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18789        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18790        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18791        GIR_EraseFromParent, /*InsnID*/0,
18792        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18793        // GIR_Coverage, 465,
18794        GIR_Done,
18795      // Label 1061: @46737
18796      GIM_Try, /*On fail goto*//*Label 1062*/ 46796, // Rule ID 466 //
18797        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18798        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsax,
18799        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18800        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18801        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18802        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18803        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18804        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18805        // (intrinsic_wo_chain:{ *:[i32] } 2710:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18806        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHSAX,
18807        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18808        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18809        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18810        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18811        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18812        GIR_EraseFromParent, /*InsnID*/0,
18813        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18814        // GIR_Coverage, 466,
18815        GIR_Done,
18816      // Label 1062: @46796
18817      GIM_Try, /*On fail goto*//*Label 1063*/ 46855, // Rule ID 467 //
18818        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18819        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub16,
18820        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18821        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18822        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18823        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18824        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18825        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18826        // (intrinsic_wo_chain:{ *:[i32] } 2711:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18827        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHSUB16,
18828        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18829        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18830        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18831        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18832        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18833        GIR_EraseFromParent, /*InsnID*/0,
18834        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18835        // GIR_Coverage, 467,
18836        GIR_Done,
18837      // Label 1063: @46855
18838      GIM_Try, /*On fail goto*//*Label 1064*/ 46914, // Rule ID 468 //
18839        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18840        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub8,
18841        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18842        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18843        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18844        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18845        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18846        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18847        // (intrinsic_wo_chain:{ *:[i32] } 2712:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18848        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHSUB8,
18849        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18850        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18851        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18852        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18853        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18854        GIR_EraseFromParent, /*InsnID*/0,
18855        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18856        // GIR_Coverage, 468,
18857        GIR_Done,
18858      // Label 1064: @46914
18859      GIM_Try, /*On fail goto*//*Label 1065*/ 46973, // Rule ID 469 //
18860        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18861        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhasx,
18862        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18863        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18864        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18865        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18866        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18867        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18868        // (intrinsic_wo_chain:{ *:[i32] } 2758:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18869        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHASX,
18870        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18871        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18872        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18873        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18874        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18875        GIR_EraseFromParent, /*InsnID*/0,
18876        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18877        // GIR_Coverage, 469,
18878        GIR_Done,
18879      // Label 1065: @46973
18880      GIM_Try, /*On fail goto*//*Label 1066*/ 47032, // Rule ID 470 //
18881        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18882        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd16,
18883        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18884        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18885        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18886        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18887        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18888        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18889        // (intrinsic_wo_chain:{ *:[i32] } 2756:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18890        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHADD16,
18891        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18892        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18893        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18894        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18895        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18896        GIR_EraseFromParent, /*InsnID*/0,
18897        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18898        // GIR_Coverage, 470,
18899        GIR_Done,
18900      // Label 1066: @47032
18901      GIM_Try, /*On fail goto*//*Label 1067*/ 47091, // Rule ID 471 //
18902        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18903        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd8,
18904        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18905        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18906        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18907        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18908        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18909        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18910        // (intrinsic_wo_chain:{ *:[i32] } 2757:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18911        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHADD8,
18912        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18913        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18914        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18915        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18916        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18917        GIR_EraseFromParent, /*InsnID*/0,
18918        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18919        // GIR_Coverage, 471,
18920        GIR_Done,
18921      // Label 1067: @47091
18922      GIM_Try, /*On fail goto*//*Label 1068*/ 47150, // Rule ID 472 //
18923        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18924        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsax,
18925        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18926        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18927        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18928        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18929        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18930        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18931        // (intrinsic_wo_chain:{ *:[i32] } 2759:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18932        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHSAX,
18933        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18934        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18935        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18936        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18937        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18938        GIR_EraseFromParent, /*InsnID*/0,
18939        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18940        // GIR_Coverage, 472,
18941        GIR_Done,
18942      // Label 1068: @47150
18943      GIM_Try, /*On fail goto*//*Label 1069*/ 47209, // Rule ID 473 //
18944        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18945        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub16,
18946        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18947        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18948        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18949        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18950        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18951        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18952        // (intrinsic_wo_chain:{ *:[i32] } 2760:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18953        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHSUB16,
18954        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18955        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18956        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18957        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18958        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18959        GIR_EraseFromParent, /*InsnID*/0,
18960        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18961        // GIR_Coverage, 473,
18962        GIR_Done,
18963      // Label 1069: @47209
18964      GIM_Try, /*On fail goto*//*Label 1070*/ 47268, // Rule ID 474 //
18965        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18966        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub8,
18967        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18968        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18969        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18970        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18971        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18972        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18973        // (intrinsic_wo_chain:{ *:[i32] } 2761:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18974        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHSUB8,
18975        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18976        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18977        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18978        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18979        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18980        GIR_EraseFromParent, /*InsnID*/0,
18981        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18982        // GIR_Coverage, 474,
18983        GIR_Done,
18984      // Label 1070: @47268
18985      GIM_Try, /*On fail goto*//*Label 1071*/ 47327, // Rule ID 475 //
18986        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18987        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usad8,
18988        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18989        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18990        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18991        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18992        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18993        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18994        // (intrinsic_wo_chain:{ *:[i32] } 2769:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2USAD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18995        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAD8,
18996        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18997        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18998        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18999        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19000        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19001        GIR_EraseFromParent, /*InsnID*/0,
19002        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19003        // GIR_Coverage, 475,
19004        GIR_Done,
19005      // Label 1071: @47327
19006      GIM_Try, /*On fail goto*//*Label 1072*/ 47386, // Rule ID 531 //
19007        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
19008        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smuad,
19009        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19010        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19011        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19012        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
19013        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
19014        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
19015        // (intrinsic_wo_chain:{ *:[i32] } 2727:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMUAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19016        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUAD,
19017        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19018        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19019        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19020        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19021        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19022        GIR_EraseFromParent, /*InsnID*/0,
19023        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19024        // GIR_Coverage, 531,
19025        GIR_Done,
19026      // Label 1072: @47386
19027      GIM_Try, /*On fail goto*//*Label 1073*/ 47445, // Rule ID 532 //
19028        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
19029        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smuadx,
19030        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19031        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19032        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19033        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
19034        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
19035        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
19036        // (intrinsic_wo_chain:{ *:[i32] } 2728:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMUADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19037        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUADX,
19038        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19039        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19040        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19041        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19042        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19043        GIR_EraseFromParent, /*InsnID*/0,
19044        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19045        // GIR_Coverage, 532,
19046        GIR_Done,
19047      // Label 1073: @47445
19048      GIM_Try, /*On fail goto*//*Label 1074*/ 47504, // Rule ID 533 //
19049        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
19050        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smusd,
19051        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19052        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19053        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19054        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
19055        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
19056        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
19057        // (intrinsic_wo_chain:{ *:[i32] } 2735:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMUSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19058        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUSD,
19059        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19060        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19061        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19062        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19063        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19064        GIR_EraseFromParent, /*InsnID*/0,
19065        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19066        // GIR_Coverage, 533,
19067        GIR_Done,
19068      // Label 1074: @47504
19069      GIM_Try, /*On fail goto*//*Label 1075*/ 47563, // Rule ID 534 //
19070        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
19071        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smusdx,
19072        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19073        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19074        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19075        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
19076        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
19077        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
19078        // (intrinsic_wo_chain:{ *:[i32] } 2736:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMUSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19079        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUSDX,
19080        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19081        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19082        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19083        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19084        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19085        GIR_EraseFromParent, /*InsnID*/0,
19086        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19087        // GIR_Coverage, 534,
19088        GIR_Done,
19089      // Label 1075: @47563
19090      GIM_Try, /*On fail goto*//*Label 1076*/ 47615, // Rule ID 548 //
19091        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
19092        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32b,
19093        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19094        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19095        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19096        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
19097        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
19098        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
19099        // (intrinsic_wo_chain:{ *:[i32] } 2328:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32B:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19100        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32B,
19101        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19102        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19103        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19104        GIR_EraseFromParent, /*InsnID*/0,
19105        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19106        // GIR_Coverage, 548,
19107        GIR_Done,
19108      // Label 1076: @47615
19109      GIM_Try, /*On fail goto*//*Label 1077*/ 47667, // Rule ID 549 //
19110        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
19111        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cb,
19112        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19113        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19114        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19115        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
19116        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
19117        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
19118        // (intrinsic_wo_chain:{ *:[i32] } 2329:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32CB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19119        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32CB,
19120        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19121        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19122        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19123        GIR_EraseFromParent, /*InsnID*/0,
19124        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19125        // GIR_Coverage, 549,
19126        GIR_Done,
19127      // Label 1077: @47667
19128      GIM_Try, /*On fail goto*//*Label 1078*/ 47719, // Rule ID 550 //
19129        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
19130        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32h,
19131        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19132        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19133        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19134        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
19135        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
19136        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
19137        // (intrinsic_wo_chain:{ *:[i32] } 2332:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32H:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19138        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32H,
19139        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19140        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19141        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19142        GIR_EraseFromParent, /*InsnID*/0,
19143        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19144        // GIR_Coverage, 550,
19145        GIR_Done,
19146      // Label 1078: @47719
19147      GIM_Try, /*On fail goto*//*Label 1079*/ 47771, // Rule ID 551 //
19148        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
19149        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32ch,
19150        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19151        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19152        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19153        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
19154        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
19155        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
19156        // (intrinsic_wo_chain:{ *:[i32] } 2330:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32CH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19157        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32CH,
19158        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19159        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19160        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19161        GIR_EraseFromParent, /*InsnID*/0,
19162        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19163        // GIR_Coverage, 551,
19164        GIR_Done,
19165      // Label 1079: @47771
19166      GIM_Try, /*On fail goto*//*Label 1080*/ 47823, // Rule ID 552 //
19167        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
19168        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32w,
19169        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19170        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19171        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19172        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
19173        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
19174        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
19175        // (intrinsic_wo_chain:{ *:[i32] } 2333:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32W:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19176        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32W,
19177        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19178        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19179        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19180        GIR_EraseFromParent, /*InsnID*/0,
19181        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19182        // GIR_Coverage, 552,
19183        GIR_Done,
19184      // Label 1080: @47823
19185      GIM_Try, /*On fail goto*//*Label 1081*/ 47875, // Rule ID 553 //
19186        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
19187        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cw,
19188        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19189        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19190        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19191        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
19192        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
19193        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
19194        // (intrinsic_wo_chain:{ *:[i32] } 2331:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32CW:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19195        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32CW,
19196        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19197        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19198        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19199        GIR_EraseFromParent, /*InsnID*/0,
19200        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19201        // GIR_Coverage, 553,
19202        GIR_Done,
19203      // Label 1081: @47875
19204      GIM_Try, /*On fail goto*//*Label 1082*/ 47934, // Rule ID 808 //
19205        GIM_CheckFeatures, GIFBS_HasNEON,
19206        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
19207        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19208        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19209        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19210        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19211        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19212        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19213        // (intrinsic_wo_chain:{ *:[v4i16] } 2599:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19214        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv4i16,
19215        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19216        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19217        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19218        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19219        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19220        GIR_EraseFromParent, /*InsnID*/0,
19221        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19222        // GIR_Coverage, 808,
19223        GIR_Done,
19224      // Label 1082: @47934
19225      GIM_Try, /*On fail goto*//*Label 1083*/ 47993, // Rule ID 809 //
19226        GIM_CheckFeatures, GIFBS_HasNEON,
19227        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
19228        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19229        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19230        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19231        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19232        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19233        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19234        // (intrinsic_wo_chain:{ *:[v2i32] } 2599:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19235        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv2i32,
19236        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19237        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19238        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19239        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19240        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19241        GIR_EraseFromParent, /*InsnID*/0,
19242        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19243        // GIR_Coverage, 809,
19244        GIR_Done,
19245      // Label 1083: @47993
19246      GIM_Try, /*On fail goto*//*Label 1084*/ 48052, // Rule ID 810 //
19247        GIM_CheckFeatures, GIFBS_HasNEON,
19248        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
19249        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19250        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19251        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19252        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19253        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19254        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19255        // (intrinsic_wo_chain:{ *:[v8i16] } 2599:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19256        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv8i16,
19257        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19258        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19259        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19260        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19261        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19262        GIR_EraseFromParent, /*InsnID*/0,
19263        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19264        // GIR_Coverage, 810,
19265        GIR_Done,
19266      // Label 1084: @48052
19267      GIM_Try, /*On fail goto*//*Label 1085*/ 48111, // Rule ID 811 //
19268        GIM_CheckFeatures, GIFBS_HasNEON,
19269        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
19270        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19271        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19272        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19273        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19274        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19275        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19276        // (intrinsic_wo_chain:{ *:[v4i32] } 2599:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19277        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv4i32,
19278        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19279        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19280        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19281        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19282        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19283        GIR_EraseFromParent, /*InsnID*/0,
19284        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19285        // GIR_Coverage, 811,
19286        GIR_Done,
19287      // Label 1085: @48111
19288      GIM_Try, /*On fail goto*//*Label 1086*/ 48170, // Rule ID 812 //
19289        GIM_CheckFeatures, GIFBS_HasNEON,
19290        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
19291        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19292        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19293        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19294        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19295        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19296        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19297        // (intrinsic_wo_chain:{ *:[v8i8] } 2599:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19298        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv8i8,
19299        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19300        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19301        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19302        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19303        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19304        GIR_EraseFromParent, /*InsnID*/0,
19305        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19306        // GIR_Coverage, 812,
19307        GIR_Done,
19308      // Label 1086: @48170
19309      GIM_Try, /*On fail goto*//*Label 1087*/ 48229, // Rule ID 813 //
19310        GIM_CheckFeatures, GIFBS_HasNEON,
19311        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
19312        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
19313        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
19314        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
19315        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19316        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19317        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19318        // (intrinsic_wo_chain:{ *:[v16i8] } 2599:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19319        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv16i8,
19320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19323        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19324        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19325        GIR_EraseFromParent, /*InsnID*/0,
19326        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19327        // GIR_Coverage, 813,
19328        GIR_Done,
19329      // Label 1087: @48229
19330      GIM_Try, /*On fail goto*//*Label 1088*/ 48288, // Rule ID 814 //
19331        GIM_CheckFeatures, GIFBS_HasNEON,
19332        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
19333        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19334        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19335        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19336        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19337        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19338        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19339        // (intrinsic_wo_chain:{ *:[v4i16] } 2600:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19340        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv4i16,
19341        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19342        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19343        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19344        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19345        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19346        GIR_EraseFromParent, /*InsnID*/0,
19347        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19348        // GIR_Coverage, 814,
19349        GIR_Done,
19350      // Label 1088: @48288
19351      GIM_Try, /*On fail goto*//*Label 1089*/ 48347, // Rule ID 815 //
19352        GIM_CheckFeatures, GIFBS_HasNEON,
19353        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
19354        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19355        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19356        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19357        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19358        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19359        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19360        // (intrinsic_wo_chain:{ *:[v2i32] } 2600:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19361        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv2i32,
19362        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19363        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19364        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19365        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19366        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19367        GIR_EraseFromParent, /*InsnID*/0,
19368        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19369        // GIR_Coverage, 815,
19370        GIR_Done,
19371      // Label 1089: @48347
19372      GIM_Try, /*On fail goto*//*Label 1090*/ 48406, // Rule ID 816 //
19373        GIM_CheckFeatures, GIFBS_HasNEON,
19374        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
19375        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19376        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19377        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19378        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19379        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19380        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19381        // (intrinsic_wo_chain:{ *:[v8i16] } 2600:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19382        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv8i16,
19383        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19384        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19385        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19386        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19387        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19388        GIR_EraseFromParent, /*InsnID*/0,
19389        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19390        // GIR_Coverage, 816,
19391        GIR_Done,
19392      // Label 1090: @48406
19393      GIM_Try, /*On fail goto*//*Label 1091*/ 48465, // Rule ID 817 //
19394        GIM_CheckFeatures, GIFBS_HasNEON,
19395        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
19396        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19397        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19398        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19399        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19400        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19401        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19402        // (intrinsic_wo_chain:{ *:[v4i32] } 2600:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19403        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv4i32,
19404        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19405        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19406        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19407        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19408        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19409        GIR_EraseFromParent, /*InsnID*/0,
19410        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19411        // GIR_Coverage, 817,
19412        GIR_Done,
19413      // Label 1091: @48465
19414      GIM_Try, /*On fail goto*//*Label 1092*/ 48524, // Rule ID 818 //
19415        GIM_CheckFeatures, GIFBS_HasNEON,
19416        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
19417        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19418        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19419        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19420        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19421        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19422        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19423        // (intrinsic_wo_chain:{ *:[v8i8] } 2600:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19424        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv8i8,
19425        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19426        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19427        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19428        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19429        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19430        GIR_EraseFromParent, /*InsnID*/0,
19431        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19432        // GIR_Coverage, 818,
19433        GIR_Done,
19434      // Label 1092: @48524
19435      GIM_Try, /*On fail goto*//*Label 1093*/ 48583, // Rule ID 819 //
19436        GIM_CheckFeatures, GIFBS_HasNEON,
19437        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
19438        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
19439        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
19440        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
19441        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19442        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19443        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19444        // (intrinsic_wo_chain:{ *:[v16i8] } 2600:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19445        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv16i8,
19446        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19447        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19448        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19449        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19450        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19451        GIR_EraseFromParent, /*InsnID*/0,
19452        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19453        // GIR_Coverage, 819,
19454        GIR_Done,
19455      // Label 1093: @48583
19456      GIM_Try, /*On fail goto*//*Label 1094*/ 48642, // Rule ID 820 //
19457        GIM_CheckFeatures, GIFBS_HasNEON,
19458        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
19459        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19460        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19461        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19462        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19463        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19464        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19465        // (intrinsic_wo_chain:{ *:[v4i16] } 2659:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VRHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19466        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv4i16,
19467        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19468        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19469        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19470        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19471        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19472        GIR_EraseFromParent, /*InsnID*/0,
19473        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19474        // GIR_Coverage, 820,
19475        GIR_Done,
19476      // Label 1094: @48642
19477      GIM_Try, /*On fail goto*//*Label 1095*/ 48701, // Rule ID 821 //
19478        GIM_CheckFeatures, GIFBS_HasNEON,
19479        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
19480        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19481        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19482        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19483        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19484        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19485        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19486        // (intrinsic_wo_chain:{ *:[v2i32] } 2659:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VRHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19487        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv2i32,
19488        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19489        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19490        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19491        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19492        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19493        GIR_EraseFromParent, /*InsnID*/0,
19494        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19495        // GIR_Coverage, 821,
19496        GIR_Done,
19497      // Label 1095: @48701
19498      GIM_Try, /*On fail goto*//*Label 1096*/ 48760, // Rule ID 822 //
19499        GIM_CheckFeatures, GIFBS_HasNEON,
19500        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
19501        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19502        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19503        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19504        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19505        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19506        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19507        // (intrinsic_wo_chain:{ *:[v8i16] } 2659:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VRHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19508        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv8i16,
19509        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19510        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19511        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19512        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19513        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19514        GIR_EraseFromParent, /*InsnID*/0,
19515        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19516        // GIR_Coverage, 822,
19517        GIR_Done,
19518      // Label 1096: @48760
19519      GIM_Try, /*On fail goto*//*Label 1097*/ 48819, // Rule ID 823 //
19520        GIM_CheckFeatures, GIFBS_HasNEON,
19521        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
19522        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19523        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19524        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19525        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19526        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19527        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19528        // (intrinsic_wo_chain:{ *:[v4i32] } 2659:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VRHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19529        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv4i32,
19530        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19531        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19532        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19533        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19534        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19535        GIR_EraseFromParent, /*InsnID*/0,
19536        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19537        // GIR_Coverage, 823,
19538        GIR_Done,
19539      // Label 1097: @48819
19540      GIM_Try, /*On fail goto*//*Label 1098*/ 48878, // Rule ID 824 //
19541        GIM_CheckFeatures, GIFBS_HasNEON,
19542        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
19543        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19544        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19545        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19546        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19547        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19548        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19549        // (intrinsic_wo_chain:{ *:[v8i8] } 2659:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VRHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19550        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv8i8,
19551        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19552        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19553        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19554        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19555        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19556        GIR_EraseFromParent, /*InsnID*/0,
19557        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19558        // GIR_Coverage, 824,
19559        GIR_Done,
19560      // Label 1098: @48878
19561      GIM_Try, /*On fail goto*//*Label 1099*/ 48937, // Rule ID 825 //
19562        GIM_CheckFeatures, GIFBS_HasNEON,
19563        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
19564        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
19565        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
19566        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
19567        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19568        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19569        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19570        // (intrinsic_wo_chain:{ *:[v16i8] } 2659:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VRHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19571        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv16i8,
19572        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19573        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19574        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19575        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19576        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19577        GIR_EraseFromParent, /*InsnID*/0,
19578        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19579        // GIR_Coverage, 825,
19580        GIR_Done,
19581      // Label 1099: @48937
19582      GIM_Try, /*On fail goto*//*Label 1100*/ 48996, // Rule ID 826 //
19583        GIM_CheckFeatures, GIFBS_HasNEON,
19584        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
19585        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19586        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19587        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19588        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19589        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19590        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19591        // (intrinsic_wo_chain:{ *:[v4i16] } 2660:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VRHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19592        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv4i16,
19593        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19594        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19595        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19596        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19597        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19598        GIR_EraseFromParent, /*InsnID*/0,
19599        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19600        // GIR_Coverage, 826,
19601        GIR_Done,
19602      // Label 1100: @48996
19603      GIM_Try, /*On fail goto*//*Label 1101*/ 49055, // Rule ID 827 //
19604        GIM_CheckFeatures, GIFBS_HasNEON,
19605        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
19606        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19607        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19608        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19609        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19610        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19611        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19612        // (intrinsic_wo_chain:{ *:[v2i32] } 2660:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VRHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19613        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv2i32,
19614        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19615        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19616        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19617        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19618        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19619        GIR_EraseFromParent, /*InsnID*/0,
19620        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19621        // GIR_Coverage, 827,
19622        GIR_Done,
19623      // Label 1101: @49055
19624      GIM_Try, /*On fail goto*//*Label 1102*/ 49114, // Rule ID 828 //
19625        GIM_CheckFeatures, GIFBS_HasNEON,
19626        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
19627        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19628        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19629        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19630        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19631        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19632        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19633        // (intrinsic_wo_chain:{ *:[v8i16] } 2660:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VRHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19634        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv8i16,
19635        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19636        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19637        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19638        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19639        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19640        GIR_EraseFromParent, /*InsnID*/0,
19641        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19642        // GIR_Coverage, 828,
19643        GIR_Done,
19644      // Label 1102: @49114
19645      GIM_Try, /*On fail goto*//*Label 1103*/ 49173, // Rule ID 829 //
19646        GIM_CheckFeatures, GIFBS_HasNEON,
19647        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
19648        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19649        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19650        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19651        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19652        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19653        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19654        // (intrinsic_wo_chain:{ *:[v4i32] } 2660:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VRHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19655        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv4i32,
19656        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19657        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19658        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19659        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19660        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19661        GIR_EraseFromParent, /*InsnID*/0,
19662        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19663        // GIR_Coverage, 829,
19664        GIR_Done,
19665      // Label 1103: @49173
19666      GIM_Try, /*On fail goto*//*Label 1104*/ 49232, // Rule ID 830 //
19667        GIM_CheckFeatures, GIFBS_HasNEON,
19668        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
19669        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19670        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19671        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19672        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19673        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19674        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19675        // (intrinsic_wo_chain:{ *:[v8i8] } 2660:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VRHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19676        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv8i8,
19677        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19678        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19679        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19680        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19681        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19682        GIR_EraseFromParent, /*InsnID*/0,
19683        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19684        // GIR_Coverage, 830,
19685        GIR_Done,
19686      // Label 1104: @49232
19687      GIM_Try, /*On fail goto*//*Label 1105*/ 49291, // Rule ID 831 //
19688        GIM_CheckFeatures, GIFBS_HasNEON,
19689        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
19690        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
19691        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
19692        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
19693        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19694        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19695        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19696        // (intrinsic_wo_chain:{ *:[v16i8] } 2660:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VRHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19697        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv16i8,
19698        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19699        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19700        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19701        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19702        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19703        GIR_EraseFromParent, /*InsnID*/0,
19704        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19705        // GIR_Coverage, 831,
19706        GIR_Done,
19707      // Label 1105: @49291
19708      GIM_Try, /*On fail goto*//*Label 1106*/ 49350, // Rule ID 848 //
19709        GIM_CheckFeatures, GIFBS_HasNEON,
19710        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vraddhn,
19711        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19712        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19713        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19714        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19715        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19716        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19717        // (intrinsic_wo_chain:{ *:[v8i8] } 2656:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VRADDHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19718        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRADDHNv8i8,
19719        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19720        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19721        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19722        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19723        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19724        GIR_EraseFromParent, /*InsnID*/0,
19725        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19726        // GIR_Coverage, 848,
19727        GIR_Done,
19728      // Label 1106: @49350
19729      GIM_Try, /*On fail goto*//*Label 1107*/ 49409, // Rule ID 849 //
19730        GIM_CheckFeatures, GIFBS_HasNEON,
19731        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vraddhn,
19732        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19733        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19734        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19735        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19736        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19737        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19738        // (intrinsic_wo_chain:{ *:[v4i16] } 2656:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VRADDHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19739        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRADDHNv4i16,
19740        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19741        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19742        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19743        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19744        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19745        GIR_EraseFromParent, /*InsnID*/0,
19746        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19747        // GIR_Coverage, 849,
19748        GIR_Done,
19749      // Label 1107: @49409
19750      GIM_Try, /*On fail goto*//*Label 1108*/ 49468, // Rule ID 850 //
19751        GIM_CheckFeatures, GIFBS_HasNEON,
19752        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vraddhn,
19753        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19754        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
19755        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
19756        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19757        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19758        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19759        // (intrinsic_wo_chain:{ *:[v2i32] } 2656:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VRADDHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
19760        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRADDHNv2i32,
19761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19762        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19763        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19764        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19765        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19766        GIR_EraseFromParent, /*InsnID*/0,
19767        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19768        // GIR_Coverage, 850,
19769        GIR_Done,
19770      // Label 1108: @49468
19771      GIM_Try, /*On fail goto*//*Label 1109*/ 49527, // Rule ID 857 //
19772        GIM_CheckFeatures, GIFBS_HasNEON,
19773        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmulp,
19774        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19775        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19776        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19777        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19778        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19779        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19780        // (intrinsic_wo_chain:{ *:[v8i8] } 2625:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMULpd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19781        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULpd,
19782        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19783        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19784        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19785        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19786        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19787        GIR_EraseFromParent, /*InsnID*/0,
19788        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19789        // GIR_Coverage, 857,
19790        GIR_Done,
19791      // Label 1109: @49527
19792      GIM_Try, /*On fail goto*//*Label 1110*/ 49586, // Rule ID 858 //
19793        GIM_CheckFeatures, GIFBS_HasNEON,
19794        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmulp,
19795        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
19796        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
19797        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
19798        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19799        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19800        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19801        // (intrinsic_wo_chain:{ *:[v16i8] } 2625:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMULpq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19802        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULpq,
19803        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19804        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19805        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19806        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19807        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19808        GIR_EraseFromParent, /*InsnID*/0,
19809        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19810        // GIR_Coverage, 858,
19811        GIR_Done,
19812      // Label 1110: @49586
19813      GIM_Try, /*On fail goto*//*Label 1111*/ 49645, // Rule ID 871 //
19814        GIM_CheckFeatures, GIFBS_HasNEON,
19815        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh,
19816        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19817        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19818        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19819        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19820        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19821        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19822        // (intrinsic_wo_chain:{ *:[v4i16] } 2636:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19823        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv4i16,
19824        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19825        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19826        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19827        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19828        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19829        GIR_EraseFromParent, /*InsnID*/0,
19830        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19831        // GIR_Coverage, 871,
19832        GIR_Done,
19833      // Label 1111: @49645
19834      GIM_Try, /*On fail goto*//*Label 1112*/ 49704, // Rule ID 872 //
19835        GIM_CheckFeatures, GIFBS_HasNEON,
19836        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh,
19837        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19838        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19839        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19840        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19841        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19842        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19843        // (intrinsic_wo_chain:{ *:[v2i32] } 2636:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19844        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv2i32,
19845        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19846        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19847        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19848        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19849        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19850        GIR_EraseFromParent, /*InsnID*/0,
19851        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19852        // GIR_Coverage, 872,
19853        GIR_Done,
19854      // Label 1112: @49704
19855      GIM_Try, /*On fail goto*//*Label 1113*/ 49763, // Rule ID 873 //
19856        GIM_CheckFeatures, GIFBS_HasNEON,
19857        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh,
19858        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19859        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19860        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19861        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19862        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19863        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19864        // (intrinsic_wo_chain:{ *:[v8i16] } 2636:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19865        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv8i16,
19866        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19867        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19868        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19869        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19870        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19871        GIR_EraseFromParent, /*InsnID*/0,
19872        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19873        // GIR_Coverage, 873,
19874        GIR_Done,
19875      // Label 1113: @49763
19876      GIM_Try, /*On fail goto*//*Label 1114*/ 49822, // Rule ID 874 //
19877        GIM_CheckFeatures, GIFBS_HasNEON,
19878        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh,
19879        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19880        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19881        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19882        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19883        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19884        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19885        // (intrinsic_wo_chain:{ *:[v4i32] } 2636:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19886        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv4i32,
19887        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19888        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19889        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19890        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19891        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19892        GIR_EraseFromParent, /*InsnID*/0,
19893        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19894        // GIR_Coverage, 874,
19895        GIR_Done,
19896      // Label 1114: @49822
19897      GIM_Try, /*On fail goto*//*Label 1115*/ 49881, // Rule ID 879 //
19898        GIM_CheckFeatures, GIFBS_HasNEON,
19899        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
19900        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19901        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19902        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19903        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19904        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19905        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19906        // (intrinsic_wo_chain:{ *:[v4i16] } 2644:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQRDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19907        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv4i16,
19908        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19909        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19910        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19911        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19912        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19913        GIR_EraseFromParent, /*InsnID*/0,
19914        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19915        // GIR_Coverage, 879,
19916        GIR_Done,
19917      // Label 1115: @49881
19918      GIM_Try, /*On fail goto*//*Label 1116*/ 49940, // Rule ID 880 //
19919        GIM_CheckFeatures, GIFBS_HasNEON,
19920        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
19921        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19922        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19923        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19924        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19925        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19926        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19927        // (intrinsic_wo_chain:{ *:[v2i32] } 2644:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQRDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19928        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv2i32,
19929        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19930        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19931        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19932        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19933        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19934        GIR_EraseFromParent, /*InsnID*/0,
19935        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19936        // GIR_Coverage, 880,
19937        GIR_Done,
19938      // Label 1116: @49940
19939      GIM_Try, /*On fail goto*//*Label 1117*/ 49999, // Rule ID 881 //
19940        GIM_CheckFeatures, GIFBS_HasNEON,
19941        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
19942        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19943        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19944        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19945        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19946        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19947        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19948        // (intrinsic_wo_chain:{ *:[v8i16] } 2644:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQRDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19949        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv8i16,
19950        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19951        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19952        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19953        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19954        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19955        GIR_EraseFromParent, /*InsnID*/0,
19956        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19957        // GIR_Coverage, 881,
19958        GIR_Done,
19959      // Label 1117: @49999
19960      GIM_Try, /*On fail goto*//*Label 1118*/ 50058, // Rule ID 882 //
19961        GIM_CheckFeatures, GIFBS_HasNEON,
19962        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
19963        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19964        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19965        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19966        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19967        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19968        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19969        // (intrinsic_wo_chain:{ *:[v4i32] } 2644:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQRDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19970        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv4i32,
19971        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19972        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19973        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19974        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19975        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19976        GIR_EraseFromParent, /*InsnID*/0,
19977        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19978        // GIR_Coverage, 882,
19979        GIR_Done,
19980      // Label 1118: @50058
19981      GIM_Try, /*On fail goto*//*Label 1119*/ 50117, // Rule ID 893 //
19982        GIM_CheckFeatures, GIFBS_HasNEON,
19983        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmullp,
19984        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19985        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19986        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19987        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19988        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19989        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19990        // (intrinsic_wo_chain:{ *:[v8i16] } 2622:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMULLp8:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19991        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULLp8,
19992        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19993        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19994        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19995        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19996        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19997        GIR_EraseFromParent, /*InsnID*/0,
19998        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19999        // GIR_Coverage, 893,
20000        GIR_Done,
20001      // Label 1119: @50117
20002      GIM_Try, /*On fail goto*//*Label 1120*/ 50169, // Rule ID 894 //
20003        GIM_CheckFeatures, GIFBS_HasAES_HasV8,
20004        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmullp,
20005        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
20006        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20007        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20008        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20009        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20010        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20011        // (intrinsic_wo_chain:{ *:[v2i64] } 2622:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VMULLp64:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
20012        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULLp64,
20013        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20014        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20015        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20016        GIR_EraseFromParent, /*InsnID*/0,
20017        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20018        // GIR_Coverage, 894,
20019        GIR_Done,
20020      // Label 1120: @50169
20021      GIM_Try, /*On fail goto*//*Label 1121*/ 50228, // Rule ID 899 //
20022        GIM_CheckFeatures, GIFBS_HasNEON,
20023        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmull,
20024        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20025        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20026        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20027        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20028        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20029        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20030        // (intrinsic_wo_chain:{ *:[v4i32] } 2637:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQDMULLv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20031        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULLv4i32,
20032        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20033        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20034        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20035        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20036        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20037        GIR_EraseFromParent, /*InsnID*/0,
20038        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20039        // GIR_Coverage, 899,
20040        GIR_Done,
20041      // Label 1121: @50228
20042      GIM_Try, /*On fail goto*//*Label 1122*/ 50287, // Rule ID 900 //
20043        GIM_CheckFeatures, GIFBS_HasNEON,
20044        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmull,
20045        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
20046        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20047        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20048        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20049        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20050        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20051        // (intrinsic_wo_chain:{ *:[v2i64] } 2637:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQDMULLv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20052        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULLv2i64,
20053        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20054        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20055        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20056        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20057        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20058        GIR_EraseFromParent, /*InsnID*/0,
20059        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20060        // GIR_Coverage, 900,
20061        GIR_Done,
20062      // Label 1122: @50287
20063      GIM_Try, /*On fail goto*//*Label 1123*/ 50346, // Rule ID 1012 //
20064        GIM_CheckFeatures, GIFBS_HasNEON,
20065        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
20066        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20067        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20068        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20069        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20070        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20071        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20072        // (intrinsic_wo_chain:{ *:[v4i16] } 2601:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VHSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20073        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv4i16,
20074        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20075        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20076        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20077        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20078        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20079        GIR_EraseFromParent, /*InsnID*/0,
20080        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20081        // GIR_Coverage, 1012,
20082        GIR_Done,
20083      // Label 1123: @50346
20084      GIM_Try, /*On fail goto*//*Label 1124*/ 50405, // Rule ID 1013 //
20085        GIM_CheckFeatures, GIFBS_HasNEON,
20086        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
20087        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20088        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20089        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20090        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20091        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20092        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20093        // (intrinsic_wo_chain:{ *:[v2i32] } 2601:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VHSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20094        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv2i32,
20095        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20096        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20097        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20098        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20099        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20100        GIR_EraseFromParent, /*InsnID*/0,
20101        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20102        // GIR_Coverage, 1013,
20103        GIR_Done,
20104      // Label 1124: @50405
20105      GIM_Try, /*On fail goto*//*Label 1125*/ 50464, // Rule ID 1014 //
20106        GIM_CheckFeatures, GIFBS_HasNEON,
20107        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
20108        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
20109        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20110        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20111        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20112        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20113        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20114        // (intrinsic_wo_chain:{ *:[v8i16] } 2601:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VHSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20115        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv8i16,
20116        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20117        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20118        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20119        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20120        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20121        GIR_EraseFromParent, /*InsnID*/0,
20122        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20123        // GIR_Coverage, 1014,
20124        GIR_Done,
20125      // Label 1125: @50464
20126      GIM_Try, /*On fail goto*//*Label 1126*/ 50523, // Rule ID 1015 //
20127        GIM_CheckFeatures, GIFBS_HasNEON,
20128        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
20129        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20130        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20131        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20132        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20133        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20134        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20135        // (intrinsic_wo_chain:{ *:[v4i32] } 2601:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VHSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20136        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv4i32,
20137        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20138        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20139        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20140        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20141        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20142        GIR_EraseFromParent, /*InsnID*/0,
20143        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20144        // GIR_Coverage, 1015,
20145        GIR_Done,
20146      // Label 1126: @50523
20147      GIM_Try, /*On fail goto*//*Label 1127*/ 50582, // Rule ID 1016 //
20148        GIM_CheckFeatures, GIFBS_HasNEON,
20149        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
20150        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
20151        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
20152        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
20153        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20154        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20155        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20156        // (intrinsic_wo_chain:{ *:[v8i8] } 2601:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VHSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20157        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv8i8,
20158        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20159        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20160        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20161        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20162        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20163        GIR_EraseFromParent, /*InsnID*/0,
20164        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20165        // GIR_Coverage, 1016,
20166        GIR_Done,
20167      // Label 1127: @50582
20168      GIM_Try, /*On fail goto*//*Label 1128*/ 50641, // Rule ID 1017 //
20169        GIM_CheckFeatures, GIFBS_HasNEON,
20170        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
20171        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
20172        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
20173        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
20174        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20175        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20176        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20177        // (intrinsic_wo_chain:{ *:[v16i8] } 2601:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VHSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20178        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv16i8,
20179        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20180        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20181        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20182        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20183        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20184        GIR_EraseFromParent, /*InsnID*/0,
20185        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20186        // GIR_Coverage, 1017,
20187        GIR_Done,
20188      // Label 1128: @50641
20189      GIM_Try, /*On fail goto*//*Label 1129*/ 50700, // Rule ID 1018 //
20190        GIM_CheckFeatures, GIFBS_HasNEON,
20191        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
20192        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20193        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20194        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20195        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20196        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20197        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20198        // (intrinsic_wo_chain:{ *:[v4i16] } 2602:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VHSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20199        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv4i16,
20200        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20201        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20202        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20203        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20204        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20205        GIR_EraseFromParent, /*InsnID*/0,
20206        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20207        // GIR_Coverage, 1018,
20208        GIR_Done,
20209      // Label 1129: @50700
20210      GIM_Try, /*On fail goto*//*Label 1130*/ 50759, // Rule ID 1019 //
20211        GIM_CheckFeatures, GIFBS_HasNEON,
20212        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
20213        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20214        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20215        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20216        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20217        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20218        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20219        // (intrinsic_wo_chain:{ *:[v2i32] } 2602:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VHSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20220        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv2i32,
20221        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20222        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20223        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20224        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20225        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20226        GIR_EraseFromParent, /*InsnID*/0,
20227        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20228        // GIR_Coverage, 1019,
20229        GIR_Done,
20230      // Label 1130: @50759
20231      GIM_Try, /*On fail goto*//*Label 1131*/ 50818, // Rule ID 1020 //
20232        GIM_CheckFeatures, GIFBS_HasNEON,
20233        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
20234        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
20235        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20236        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20237        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20238        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20239        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20240        // (intrinsic_wo_chain:{ *:[v8i16] } 2602:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VHSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20241        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv8i16,
20242        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20243        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20244        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20245        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20246        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20247        GIR_EraseFromParent, /*InsnID*/0,
20248        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20249        // GIR_Coverage, 1020,
20250        GIR_Done,
20251      // Label 1131: @50818
20252      GIM_Try, /*On fail goto*//*Label 1132*/ 50877, // Rule ID 1021 //
20253        GIM_CheckFeatures, GIFBS_HasNEON,
20254        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
20255        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20256        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20257        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20258        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20259        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20260        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20261        // (intrinsic_wo_chain:{ *:[v4i32] } 2602:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VHSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20262        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv4i32,
20263        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20264        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20265        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20266        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20267        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20268        GIR_EraseFromParent, /*InsnID*/0,
20269        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20270        // GIR_Coverage, 1021,
20271        GIR_Done,
20272      // Label 1132: @50877
20273      GIM_Try, /*On fail goto*//*Label 1133*/ 50936, // Rule ID 1022 //
20274        GIM_CheckFeatures, GIFBS_HasNEON,
20275        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
20276        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
20277        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
20278        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
20279        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20280        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20281        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20282        // (intrinsic_wo_chain:{ *:[v8i8] } 2602:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VHSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20283        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv8i8,
20284        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20285        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20286        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20287        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20288        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20289        GIR_EraseFromParent, /*InsnID*/0,
20290        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20291        // GIR_Coverage, 1022,
20292        GIR_Done,
20293      // Label 1133: @50936
20294      GIM_Try, /*On fail goto*//*Label 1134*/ 50995, // Rule ID 1023 //
20295        GIM_CheckFeatures, GIFBS_HasNEON,
20296        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
20297        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
20298        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
20299        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
20300        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20301        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20302        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20303        // (intrinsic_wo_chain:{ *:[v16i8] } 2602:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VHSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20304        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv16i8,
20305        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20306        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20307        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20308        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20309        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20310        GIR_EraseFromParent, /*InsnID*/0,
20311        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20312        // GIR_Coverage, 1023,
20313        GIR_Done,
20314      // Label 1134: @50995
20315      GIM_Try, /*On fail goto*//*Label 1135*/ 51054, // Rule ID 1040 //
20316        GIM_CheckFeatures, GIFBS_HasNEON,
20317        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsubhn,
20318        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
20319        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20320        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20321        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20322        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20323        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20324        // (intrinsic_wo_chain:{ *:[v8i8] } 2672:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VRSUBHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20325        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSUBHNv8i8,
20326        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20327        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20328        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20329        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20330        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20331        GIR_EraseFromParent, /*InsnID*/0,
20332        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20333        // GIR_Coverage, 1040,
20334        GIR_Done,
20335      // Label 1135: @51054
20336      GIM_Try, /*On fail goto*//*Label 1136*/ 51113, // Rule ID 1041 //
20337        GIM_CheckFeatures, GIFBS_HasNEON,
20338        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsubhn,
20339        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20340        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20341        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20342        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20343        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20344        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20345        // (intrinsic_wo_chain:{ *:[v4i16] } 2672:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VRSUBHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20346        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSUBHNv4i16,
20347        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20348        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20349        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20350        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20351        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20352        GIR_EraseFromParent, /*InsnID*/0,
20353        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20354        // GIR_Coverage, 1041,
20355        GIR_Done,
20356      // Label 1136: @51113
20357      GIM_Try, /*On fail goto*//*Label 1137*/ 51172, // Rule ID 1042 //
20358        GIM_CheckFeatures, GIFBS_HasNEON,
20359        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsubhn,
20360        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20361        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
20362        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
20363        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20364        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20365        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20366        // (intrinsic_wo_chain:{ *:[v2i32] } 2672:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VRSUBHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
20367        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSUBHNv2i32,
20368        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20369        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20370        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20371        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20372        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20373        GIR_EraseFromParent, /*InsnID*/0,
20374        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20375        // GIR_Coverage, 1042,
20376        GIR_Done,
20377      // Label 1137: @51172
20378      GIM_Try, /*On fail goto*//*Label 1138*/ 51231, // Rule ID 1135 //
20379        GIM_CheckFeatures, GIFBS_HasNEON,
20380        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge,
20381        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20382        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20383        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20384        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20385        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20386        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20387        // (intrinsic_wo_chain:{ *:[v2i32] } 2577:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VACGEfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
20388        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEfd,
20389        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20390        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20391        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20392        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20393        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20394        GIR_EraseFromParent, /*InsnID*/0,
20395        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20396        // GIR_Coverage, 1135,
20397        GIR_Done,
20398      // Label 1138: @51231
20399      GIM_Try, /*On fail goto*//*Label 1139*/ 51290, // Rule ID 1136 //
20400        GIM_CheckFeatures, GIFBS_HasNEON,
20401        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge,
20402        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20403        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20404        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20405        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20406        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20407        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20408        // (intrinsic_wo_chain:{ *:[v4i32] } 2577:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VACGEfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
20409        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEfq,
20410        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20411        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20412        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20413        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20414        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20415        GIR_EraseFromParent, /*InsnID*/0,
20416        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20417        // GIR_Coverage, 1136,
20418        GIR_Done,
20419      // Label 1139: @51290
20420      GIM_Try, /*On fail goto*//*Label 1140*/ 51349, // Rule ID 1137 //
20421        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
20422        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge,
20423        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20424        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20425        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20426        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20427        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20428        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20429        // (intrinsic_wo_chain:{ *:[v4i16] } 2577:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VACGEhd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
20430        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEhd,
20431        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20432        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20433        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20434        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20435        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20436        GIR_EraseFromParent, /*InsnID*/0,
20437        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20438        // GIR_Coverage, 1137,
20439        GIR_Done,
20440      // Label 1140: @51349
20441      GIM_Try, /*On fail goto*//*Label 1141*/ 51408, // Rule ID 1138 //
20442        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
20443        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge,
20444        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
20445        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20446        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20447        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20448        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20449        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20450        // (intrinsic_wo_chain:{ *:[v8i16] } 2577:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VACGEhq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
20451        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEhq,
20452        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20453        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20454        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20455        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20456        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20457        GIR_EraseFromParent, /*InsnID*/0,
20458        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20459        // GIR_Coverage, 1138,
20460        GIR_Done,
20461      // Label 1141: @51408
20462      GIM_Try, /*On fail goto*//*Label 1142*/ 51467, // Rule ID 1139 //
20463        GIM_CheckFeatures, GIFBS_HasNEON,
20464        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt,
20465        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20466        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20467        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20468        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20469        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20470        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20471        // (intrinsic_wo_chain:{ *:[v2i32] } 2578:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VACGTfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
20472        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGTfd,
20473        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20474        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20475        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20476        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20477        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20478        GIR_EraseFromParent, /*InsnID*/0,
20479        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20480        // GIR_Coverage, 1139,
20481        GIR_Done,
20482      // Label 1142: @51467
20483      GIM_Try, /*On fail goto*//*Label 1143*/ 51526, // Rule ID 1140 //
20484        GIM_CheckFeatures, GIFBS_HasNEON,
20485        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt,
20486        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20487        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20488        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20489        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20490        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20491        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20492        // (intrinsic_wo_chain:{ *:[v4i32] } 2578:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VACGTfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
20493        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGTfq,
20494        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20495        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20496        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20497        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20498        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20499        GIR_EraseFromParent, /*InsnID*/0,
20500        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20501        // GIR_Coverage, 1140,
20502        GIR_Done,
20503      // Label 1143: @51526
20504      GIM_Try, /*On fail goto*//*Label 1144*/ 51585, // Rule ID 1141 //
20505        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
20506        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt,
20507        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20508        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20509        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20510        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20511        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20512        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20513        // (intrinsic_wo_chain:{ *:[v4i16] } 2578:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VACGThd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
20514        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGThd,
20515        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20516        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20517        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20518        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20519        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20520        GIR_EraseFromParent, /*InsnID*/0,
20521        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20522        // GIR_Coverage, 1141,
20523        GIR_Done,
20524      // Label 1144: @51585
20525      GIM_Try, /*On fail goto*//*Label 1145*/ 51644, // Rule ID 1142 //
20526        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
20527        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt,
20528        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
20529        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20530        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20531        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20532        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20533        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20534        // (intrinsic_wo_chain:{ *:[v8i16] } 2578:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VACGThq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
20535        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGThq,
20536        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20537        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20538        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20539        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20540        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20541        GIR_EraseFromParent, /*InsnID*/0,
20542        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20543        // GIR_Coverage, 1142,
20544        GIR_Done,
20545      // Label 1145: @51644
20546      GIM_Try, /*On fail goto*//*Label 1146*/ 51703, // Rule ID 1175 //
20547        GIM_CheckFeatures, GIFBS_HasNEON,
20548        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
20549        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20550        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20551        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20552        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20553        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20554        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20555        // (intrinsic_wo_chain:{ *:[v4i16] } 2574:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VABDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20556        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv4i16,
20557        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20558        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20559        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20560        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20561        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20562        GIR_EraseFromParent, /*InsnID*/0,
20563        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20564        // GIR_Coverage, 1175,
20565        GIR_Done,
20566      // Label 1146: @51703
20567      GIM_Try, /*On fail goto*//*Label 1147*/ 51762, // Rule ID 1176 //
20568        GIM_CheckFeatures, GIFBS_HasNEON,
20569        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
20570        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20571        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20572        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20573        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20574        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20576        // (intrinsic_wo_chain:{ *:[v2i32] } 2574:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VABDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20577        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv2i32,
20578        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20579        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20580        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20581        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20582        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20583        GIR_EraseFromParent, /*InsnID*/0,
20584        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20585        // GIR_Coverage, 1176,
20586        GIR_Done,
20587      // Label 1147: @51762
20588      GIM_Try, /*On fail goto*//*Label 1148*/ 51821, // Rule ID 1177 //
20589        GIM_CheckFeatures, GIFBS_HasNEON,
20590        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
20591        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
20592        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20593        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20594        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20595        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20596        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20597        // (intrinsic_wo_chain:{ *:[v8i16] } 2574:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VABDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20598        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv8i16,
20599        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20600        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20601        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20602        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20603        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20604        GIR_EraseFromParent, /*InsnID*/0,
20605        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20606        // GIR_Coverage, 1177,
20607        GIR_Done,
20608      // Label 1148: @51821
20609      GIM_Try, /*On fail goto*//*Label 1149*/ 51880, // Rule ID 1178 //
20610        GIM_CheckFeatures, GIFBS_HasNEON,
20611        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
20612        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20613        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20614        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20615        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20616        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20617        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20618        // (intrinsic_wo_chain:{ *:[v4i32] } 2574:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VABDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20619        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv4i32,
20620        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20621        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20622        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20623        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20624        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20625        GIR_EraseFromParent, /*InsnID*/0,
20626        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20627        // GIR_Coverage, 1178,
20628        GIR_Done,
20629      // Label 1149: @51880
20630      GIM_Try, /*On fail goto*//*Label 1150*/ 51939, // Rule ID 1179 //
20631        GIM_CheckFeatures, GIFBS_HasNEON,
20632        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
20633        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
20634        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
20635        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
20636        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20637        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20638        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20639        // (intrinsic_wo_chain:{ *:[v8i8] } 2574:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VABDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20640        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv8i8,
20641        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20642        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20643        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20644        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20645        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20646        GIR_EraseFromParent, /*InsnID*/0,
20647        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20648        // GIR_Coverage, 1179,
20649        GIR_Done,
20650      // Label 1150: @51939
20651      GIM_Try, /*On fail goto*//*Label 1151*/ 51998, // Rule ID 1180 //
20652        GIM_CheckFeatures, GIFBS_HasNEON,
20653        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
20654        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
20655        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
20656        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
20657        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20658        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20659        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20660        // (intrinsic_wo_chain:{ *:[v16i8] } 2574:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VABDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20661        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv16i8,
20662        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20663        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20664        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20665        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20666        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20667        GIR_EraseFromParent, /*InsnID*/0,
20668        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20669        // GIR_Coverage, 1180,
20670        GIR_Done,
20671      // Label 1151: @51998
20672      GIM_Try, /*On fail goto*//*Label 1152*/ 52057, // Rule ID 1181 //
20673        GIM_CheckFeatures, GIFBS_HasNEON,
20674        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
20675        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20676        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20677        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20678        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20679        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20680        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20681        // (intrinsic_wo_chain:{ *:[v4i16] } 2575:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VABDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20682        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv4i16,
20683        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20684        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20685        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20686        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20687        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20688        GIR_EraseFromParent, /*InsnID*/0,
20689        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20690        // GIR_Coverage, 1181,
20691        GIR_Done,
20692      // Label 1152: @52057
20693      GIM_Try, /*On fail goto*//*Label 1153*/ 52116, // Rule ID 1182 //
20694        GIM_CheckFeatures, GIFBS_HasNEON,
20695        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
20696        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20697        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20698        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20699        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20700        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20701        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20702        // (intrinsic_wo_chain:{ *:[v2i32] } 2575:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VABDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20703        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv2i32,
20704        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20705        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20706        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20707        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20708        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20709        GIR_EraseFromParent, /*InsnID*/0,
20710        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20711        // GIR_Coverage, 1182,
20712        GIR_Done,
20713      // Label 1153: @52116
20714      GIM_Try, /*On fail goto*//*Label 1154*/ 52175, // Rule ID 1183 //
20715        GIM_CheckFeatures, GIFBS_HasNEON,
20716        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
20717        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
20718        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20719        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20720        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20721        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20722        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20723        // (intrinsic_wo_chain:{ *:[v8i16] } 2575:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VABDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20724        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv8i16,
20725        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20726        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20727        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20728        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20729        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20730        GIR_EraseFromParent, /*InsnID*/0,
20731        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20732        // GIR_Coverage, 1183,
20733        GIR_Done,
20734      // Label 1154: @52175
20735      GIM_Try, /*On fail goto*//*Label 1155*/ 52234, // Rule ID 1184 //
20736        GIM_CheckFeatures, GIFBS_HasNEON,
20737        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
20738        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20739        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20740        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20741        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20742        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20743        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20744        // (intrinsic_wo_chain:{ *:[v4i32] } 2575:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VABDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20745        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv4i32,
20746        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20747        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20748        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20749        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20750        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20751        GIR_EraseFromParent, /*InsnID*/0,
20752        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20753        // GIR_Coverage, 1184,
20754        GIR_Done,
20755      // Label 1155: @52234
20756      GIM_Try, /*On fail goto*//*Label 1156*/ 52293, // Rule ID 1185 //
20757        GIM_CheckFeatures, GIFBS_HasNEON,
20758        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
20759        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
20760        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
20761        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
20762        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20763        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20764        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20765        // (intrinsic_wo_chain:{ *:[v8i8] } 2575:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VABDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20766        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv8i8,
20767        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20768        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20769        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20770        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20771        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20772        GIR_EraseFromParent, /*InsnID*/0,
20773        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20774        // GIR_Coverage, 1185,
20775        GIR_Done,
20776      // Label 1156: @52293
20777      GIM_Try, /*On fail goto*//*Label 1157*/ 52352, // Rule ID 1186 //
20778        GIM_CheckFeatures, GIFBS_HasNEON,
20779        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
20780        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
20781        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
20782        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
20783        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20784        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20785        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20786        // (intrinsic_wo_chain:{ *:[v16i8] } 2575:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VABDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20787        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv16i8,
20788        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20789        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20790        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20791        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20792        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20793        GIR_EraseFromParent, /*InsnID*/0,
20794        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20795        // GIR_Coverage, 1186,
20796        GIR_Done,
20797      // Label 1157: @52352
20798      GIM_Try, /*On fail goto*//*Label 1158*/ 52411, // Rule ID 1187 //
20799        GIM_CheckFeatures, GIFBS_HasNEON,
20800        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
20801        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20802        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20803        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20804        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20805        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20806        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20807        // (intrinsic_wo_chain:{ *:[v2f32] } 2574:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VABDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
20808        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDfd,
20809        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20810        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20811        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20812        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20813        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20814        GIR_EraseFromParent, /*InsnID*/0,
20815        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20816        // GIR_Coverage, 1187,
20817        GIR_Done,
20818      // Label 1158: @52411
20819      GIM_Try, /*On fail goto*//*Label 1159*/ 52470, // Rule ID 1188 //
20820        GIM_CheckFeatures, GIFBS_HasNEON,
20821        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
20822        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20823        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20824        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20825        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20826        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20827        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20828        // (intrinsic_wo_chain:{ *:[v4f32] } 2574:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VABDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
20829        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDfq,
20830        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20831        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20832        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20833        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20834        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20835        GIR_EraseFromParent, /*InsnID*/0,
20836        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20837        // GIR_Coverage, 1188,
20838        GIR_Done,
20839      // Label 1159: @52470
20840      GIM_Try, /*On fail goto*//*Label 1160*/ 52529, // Rule ID 1189 //
20841        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
20842        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
20843        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20844        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20845        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20846        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20847        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20848        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20849        // (intrinsic_wo_chain:{ *:[v4f16] } 2574:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VABDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
20850        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDhd,
20851        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20852        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20853        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20854        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20855        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20856        GIR_EraseFromParent, /*InsnID*/0,
20857        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20858        // GIR_Coverage, 1189,
20859        GIR_Done,
20860      // Label 1160: @52529
20861      GIM_Try, /*On fail goto*//*Label 1161*/ 52588, // Rule ID 1190 //
20862        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
20863        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
20864        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
20865        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20866        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20867        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20868        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20869        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20870        // (intrinsic_wo_chain:{ *:[v8f16] } 2574:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VABDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
20871        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDhq,
20872        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20873        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20874        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20875        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20876        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20877        GIR_EraseFromParent, /*InsnID*/0,
20878        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20879        // GIR_Coverage, 1190,
20880        GIR_Done,
20881      // Label 1161: @52588
20882      GIM_Try, /*On fail goto*//*Label 1162*/ 52647, // Rule ID 1255 //
20883        GIM_CheckFeatures, GIFBS_HasNEON,
20884        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
20885        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
20886        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
20887        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
20888        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20889        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20890        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20891        // (intrinsic_wo_chain:{ *:[v8i8] } 2628:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VPADDi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20892        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDi8,
20893        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20894        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20895        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20896        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20897        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20898        GIR_EraseFromParent, /*InsnID*/0,
20899        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20900        // GIR_Coverage, 1255,
20901        GIR_Done,
20902      // Label 1162: @52647
20903      GIM_Try, /*On fail goto*//*Label 1163*/ 52706, // Rule ID 1256 //
20904        GIM_CheckFeatures, GIFBS_HasNEON,
20905        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
20906        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20907        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20908        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20909        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20910        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20911        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20912        // (intrinsic_wo_chain:{ *:[v4i16] } 2628:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VPADDi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20913        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDi16,
20914        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20915        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20916        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20917        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20918        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20919        GIR_EraseFromParent, /*InsnID*/0,
20920        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20921        // GIR_Coverage, 1256,
20922        GIR_Done,
20923      // Label 1163: @52706
20924      GIM_Try, /*On fail goto*//*Label 1164*/ 52765, // Rule ID 1257 //
20925        GIM_CheckFeatures, GIFBS_HasNEON,
20926        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
20927        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20928        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20929        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20930        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20931        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20932        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20933        // (intrinsic_wo_chain:{ *:[v2i32] } 2628:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VPADDi32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20934        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDi32,
20935        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20936        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20937        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20938        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20939        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20940        GIR_EraseFromParent, /*InsnID*/0,
20941        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20942        // GIR_Coverage, 1257,
20943        GIR_Done,
20944      // Label 1164: @52765
20945      GIM_Try, /*On fail goto*//*Label 1165*/ 52824, // Rule ID 1258 //
20946        GIM_CheckFeatures, GIFBS_HasNEON,
20947        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
20948        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20949        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20950        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20951        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20952        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20953        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20954        // (intrinsic_wo_chain:{ *:[v2f32] } 2628:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VPADDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
20955        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDf,
20956        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20957        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20958        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20959        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20960        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20961        GIR_EraseFromParent, /*InsnID*/0,
20962        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20963        // GIR_Coverage, 1258,
20964        GIR_Done,
20965      // Label 1165: @52824
20966      GIM_Try, /*On fail goto*//*Label 1166*/ 52883, // Rule ID 1259 //
20967        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
20968        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
20969        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20970        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20971        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20972        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20973        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20974        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20975        // (intrinsic_wo_chain:{ *:[v4f16] } 2628:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VPADDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
20976        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDh,
20977        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20978        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20979        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20980        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20981        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20982        GIR_EraseFromParent, /*InsnID*/0,
20983        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20984        // GIR_Coverage, 1259,
20985        GIR_Done,
20986      // Label 1166: @52883
20987      GIM_Try, /*On fail goto*//*Label 1167*/ 52942, // Rule ID 1272 //
20988        GIM_CheckFeatures, GIFBS_HasNEON,
20989        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
20990        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20991        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20992        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
20993        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20994        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20995        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20996        // (intrinsic_wo_chain:{ *:[v4i16] } 2626:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)  =>  (VPADALsv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)
20997        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv8i8,
20998        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20999        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21000        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21001        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21002        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21003        GIR_EraseFromParent, /*InsnID*/0,
21004        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21005        // GIR_Coverage, 1272,
21006        GIR_Done,
21007      // Label 1167: @52942
21008      GIM_Try, /*On fail goto*//*Label 1168*/ 53001, // Rule ID 1273 //
21009        GIM_CheckFeatures, GIFBS_HasNEON,
21010        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
21011        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21012        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21013        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21014        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21015        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21016        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21017        // (intrinsic_wo_chain:{ *:[v2i32] } 2626:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)  =>  (VPADALsv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)
21018        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv4i16,
21019        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21020        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21021        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21022        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21023        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21024        GIR_EraseFromParent, /*InsnID*/0,
21025        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21026        // GIR_Coverage, 1273,
21027        GIR_Done,
21028      // Label 1168: @53001
21029      GIM_Try, /*On fail goto*//*Label 1169*/ 53060, // Rule ID 1274 //
21030        GIM_CheckFeatures, GIFBS_HasNEON,
21031        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
21032        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
21033        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21034        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21035        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21036        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21037        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21038        // (intrinsic_wo_chain:{ *:[v1i64] } 2626:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)  =>  (VPADALsv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)
21039        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv2i32,
21040        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21041        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21042        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21043        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21044        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21045        GIR_EraseFromParent, /*InsnID*/0,
21046        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21047        // GIR_Coverage, 1274,
21048        GIR_Done,
21049      // Label 1169: @53060
21050      GIM_Try, /*On fail goto*//*Label 1170*/ 53119, // Rule ID 1275 //
21051        GIM_CheckFeatures, GIFBS_HasNEON,
21052        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
21053        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21054        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21055        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
21056        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21057        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21058        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21059        // (intrinsic_wo_chain:{ *:[v8i16] } 2626:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)  =>  (VPADALsv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)
21060        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv16i8,
21061        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21062        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21063        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21064        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21065        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21066        GIR_EraseFromParent, /*InsnID*/0,
21067        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21068        // GIR_Coverage, 1275,
21069        GIR_Done,
21070      // Label 1170: @53119
21071      GIM_Try, /*On fail goto*//*Label 1171*/ 53178, // Rule ID 1276 //
21072        GIM_CheckFeatures, GIFBS_HasNEON,
21073        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
21074        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21075        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21076        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21077        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21078        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21079        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21080        // (intrinsic_wo_chain:{ *:[v4i32] } 2626:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)  =>  (VPADALsv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)
21081        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv8i16,
21082        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21083        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21084        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21085        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21086        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21087        GIR_EraseFromParent, /*InsnID*/0,
21088        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21089        // GIR_Coverage, 1276,
21090        GIR_Done,
21091      // Label 1171: @53178
21092      GIM_Try, /*On fail goto*//*Label 1172*/ 53237, // Rule ID 1277 //
21093        GIM_CheckFeatures, GIFBS_HasNEON,
21094        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
21095        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
21096        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
21097        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21098        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21099        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21100        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21101        // (intrinsic_wo_chain:{ *:[v2i64] } 2626:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)  =>  (VPADALsv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)
21102        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv4i32,
21103        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21104        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21106        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21107        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21108        GIR_EraseFromParent, /*InsnID*/0,
21109        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21110        // GIR_Coverage, 1277,
21111        GIR_Done,
21112      // Label 1172: @53237
21113      GIM_Try, /*On fail goto*//*Label 1173*/ 53296, // Rule ID 1278 //
21114        GIM_CheckFeatures, GIFBS_HasNEON,
21115        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
21116        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21117        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21118        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
21119        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21120        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21121        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21122        // (intrinsic_wo_chain:{ *:[v4i16] } 2627:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)  =>  (VPADALuv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)
21123        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv8i8,
21124        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21125        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21126        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21127        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21128        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21129        GIR_EraseFromParent, /*InsnID*/0,
21130        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21131        // GIR_Coverage, 1278,
21132        GIR_Done,
21133      // Label 1173: @53296
21134      GIM_Try, /*On fail goto*//*Label 1174*/ 53355, // Rule ID 1279 //
21135        GIM_CheckFeatures, GIFBS_HasNEON,
21136        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
21137        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21138        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21139        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21140        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21141        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21142        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21143        // (intrinsic_wo_chain:{ *:[v2i32] } 2627:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)  =>  (VPADALuv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)
21144        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv4i16,
21145        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21146        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21147        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21148        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21149        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21150        GIR_EraseFromParent, /*InsnID*/0,
21151        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21152        // GIR_Coverage, 1279,
21153        GIR_Done,
21154      // Label 1174: @53355
21155      GIM_Try, /*On fail goto*//*Label 1175*/ 53414, // Rule ID 1280 //
21156        GIM_CheckFeatures, GIFBS_HasNEON,
21157        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
21158        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
21159        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21160        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21161        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21162        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21163        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21164        // (intrinsic_wo_chain:{ *:[v1i64] } 2627:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)  =>  (VPADALuv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)
21165        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv2i32,
21166        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21167        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21168        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21169        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21170        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21171        GIR_EraseFromParent, /*InsnID*/0,
21172        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21173        // GIR_Coverage, 1280,
21174        GIR_Done,
21175      // Label 1175: @53414
21176      GIM_Try, /*On fail goto*//*Label 1176*/ 53473, // Rule ID 1281 //
21177        GIM_CheckFeatures, GIFBS_HasNEON,
21178        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
21179        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21180        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21181        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
21182        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21183        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21184        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21185        // (intrinsic_wo_chain:{ *:[v8i16] } 2627:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)  =>  (VPADALuv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)
21186        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv16i8,
21187        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21188        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21189        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21190        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21191        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21192        GIR_EraseFromParent, /*InsnID*/0,
21193        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21194        // GIR_Coverage, 1281,
21195        GIR_Done,
21196      // Label 1176: @53473
21197      GIM_Try, /*On fail goto*//*Label 1177*/ 53532, // Rule ID 1282 //
21198        GIM_CheckFeatures, GIFBS_HasNEON,
21199        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
21200        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21201        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21202        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21203        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21204        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21205        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21206        // (intrinsic_wo_chain:{ *:[v4i32] } 2627:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)  =>  (VPADALuv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)
21207        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv8i16,
21208        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21209        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21211        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21212        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21213        GIR_EraseFromParent, /*InsnID*/0,
21214        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21215        // GIR_Coverage, 1282,
21216        GIR_Done,
21217      // Label 1177: @53532
21218      GIM_Try, /*On fail goto*//*Label 1178*/ 53591, // Rule ID 1283 //
21219        GIM_CheckFeatures, GIFBS_HasNEON,
21220        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
21221        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
21222        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
21223        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21224        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21225        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21226        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21227        // (intrinsic_wo_chain:{ *:[v2i64] } 2627:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)  =>  (VPADALuv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)
21228        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv4i32,
21229        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21230        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21231        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21232        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21233        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21234        GIR_EraseFromParent, /*InsnID*/0,
21235        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21236        // GIR_Coverage, 1283,
21237        GIR_Done,
21238      // Label 1178: @53591
21239      GIM_Try, /*On fail goto*//*Label 1179*/ 53650, // Rule ID 1284 //
21240        GIM_CheckFeatures, GIFBS_HasNEON,
21241        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
21242        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
21243        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
21244        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
21245        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21246        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21247        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21248        // (intrinsic_wo_chain:{ *:[v8i8] } 2631:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VPMAXs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21249        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXs8,
21250        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21251        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21252        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21253        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21254        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21255        GIR_EraseFromParent, /*InsnID*/0,
21256        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21257        // GIR_Coverage, 1284,
21258        GIR_Done,
21259      // Label 1179: @53650
21260      GIM_Try, /*On fail goto*//*Label 1180*/ 53709, // Rule ID 1285 //
21261        GIM_CheckFeatures, GIFBS_HasNEON,
21262        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
21263        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21264        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21265        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21266        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21267        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21268        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21269        // (intrinsic_wo_chain:{ *:[v4i16] } 2631:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VPMAXs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21270        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXs16,
21271        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21272        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21273        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21274        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21275        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21276        GIR_EraseFromParent, /*InsnID*/0,
21277        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21278        // GIR_Coverage, 1285,
21279        GIR_Done,
21280      // Label 1180: @53709
21281      GIM_Try, /*On fail goto*//*Label 1181*/ 53768, // Rule ID 1286 //
21282        GIM_CheckFeatures, GIFBS_HasNEON,
21283        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
21284        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21285        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21286        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21287        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21288        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21289        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21290        // (intrinsic_wo_chain:{ *:[v2i32] } 2631:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VPMAXs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21291        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXs32,
21292        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21293        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21294        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21295        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21296        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21297        GIR_EraseFromParent, /*InsnID*/0,
21298        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21299        // GIR_Coverage, 1286,
21300        GIR_Done,
21301      // Label 1181: @53768
21302      GIM_Try, /*On fail goto*//*Label 1182*/ 53827, // Rule ID 1287 //
21303        GIM_CheckFeatures, GIFBS_HasNEON,
21304        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxu,
21305        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
21306        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
21307        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
21308        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21309        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21310        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21311        // (intrinsic_wo_chain:{ *:[v8i8] } 2632:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VPMAXu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21312        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXu8,
21313        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21314        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21315        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21316        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21317        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21318        GIR_EraseFromParent, /*InsnID*/0,
21319        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21320        // GIR_Coverage, 1287,
21321        GIR_Done,
21322      // Label 1182: @53827
21323      GIM_Try, /*On fail goto*//*Label 1183*/ 53886, // Rule ID 1288 //
21324        GIM_CheckFeatures, GIFBS_HasNEON,
21325        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxu,
21326        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21327        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21328        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21329        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21330        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21331        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21332        // (intrinsic_wo_chain:{ *:[v4i16] } 2632:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VPMAXu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21333        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXu16,
21334        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21335        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21336        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21337        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21338        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21339        GIR_EraseFromParent, /*InsnID*/0,
21340        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21341        // GIR_Coverage, 1288,
21342        GIR_Done,
21343      // Label 1183: @53886
21344      GIM_Try, /*On fail goto*//*Label 1184*/ 53945, // Rule ID 1289 //
21345        GIM_CheckFeatures, GIFBS_HasNEON,
21346        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxu,
21347        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21348        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21349        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21350        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21351        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21352        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21353        // (intrinsic_wo_chain:{ *:[v2i32] } 2632:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VPMAXu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21354        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXu32,
21355        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21356        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21357        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21358        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21359        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21360        GIR_EraseFromParent, /*InsnID*/0,
21361        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21362        // GIR_Coverage, 1289,
21363        GIR_Done,
21364      // Label 1184: @53945
21365      GIM_Try, /*On fail goto*//*Label 1185*/ 54004, // Rule ID 1290 //
21366        GIM_CheckFeatures, GIFBS_HasNEON,
21367        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
21368        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21369        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21370        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21371        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21372        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21373        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21374        // (intrinsic_wo_chain:{ *:[v2f32] } 2631:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VPMAXf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21375        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXf,
21376        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21377        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21378        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21379        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21380        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21381        GIR_EraseFromParent, /*InsnID*/0,
21382        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21383        // GIR_Coverage, 1290,
21384        GIR_Done,
21385      // Label 1185: @54004
21386      GIM_Try, /*On fail goto*//*Label 1186*/ 54063, // Rule ID 1291 //
21387        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
21388        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
21389        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21390        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21391        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21392        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21393        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21394        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21395        // (intrinsic_wo_chain:{ *:[v4f16] } 2631:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VPMAXh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21396        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXh,
21397        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21398        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21399        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21400        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21401        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21402        GIR_EraseFromParent, /*InsnID*/0,
21403        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21404        // GIR_Coverage, 1291,
21405        GIR_Done,
21406      // Label 1186: @54063
21407      GIM_Try, /*On fail goto*//*Label 1187*/ 54122, // Rule ID 1292 //
21408        GIM_CheckFeatures, GIFBS_HasNEON,
21409        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
21410        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
21411        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
21412        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
21413        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21414        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21415        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21416        // (intrinsic_wo_chain:{ *:[v8i8] } 2633:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VPMINs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21417        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINs8,
21418        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21419        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21420        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21421        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21422        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21423        GIR_EraseFromParent, /*InsnID*/0,
21424        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21425        // GIR_Coverage, 1292,
21426        GIR_Done,
21427      // Label 1187: @54122
21428      GIM_Try, /*On fail goto*//*Label 1188*/ 54181, // Rule ID 1293 //
21429        GIM_CheckFeatures, GIFBS_HasNEON,
21430        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
21431        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21432        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21433        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21434        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21435        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21436        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21437        // (intrinsic_wo_chain:{ *:[v4i16] } 2633:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VPMINs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21438        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINs16,
21439        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21440        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21441        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21442        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21443        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21444        GIR_EraseFromParent, /*InsnID*/0,
21445        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21446        // GIR_Coverage, 1293,
21447        GIR_Done,
21448      // Label 1188: @54181
21449      GIM_Try, /*On fail goto*//*Label 1189*/ 54240, // Rule ID 1294 //
21450        GIM_CheckFeatures, GIFBS_HasNEON,
21451        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
21452        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21453        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21454        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21455        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21456        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21457        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21458        // (intrinsic_wo_chain:{ *:[v2i32] } 2633:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VPMINs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21459        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINs32,
21460        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21461        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21462        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21463        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21464        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21465        GIR_EraseFromParent, /*InsnID*/0,
21466        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21467        // GIR_Coverage, 1294,
21468        GIR_Done,
21469      // Label 1189: @54240
21470      GIM_Try, /*On fail goto*//*Label 1190*/ 54299, // Rule ID 1295 //
21471        GIM_CheckFeatures, GIFBS_HasNEON,
21472        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpminu,
21473        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
21474        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
21475        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
21476        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21477        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21478        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21479        // (intrinsic_wo_chain:{ *:[v8i8] } 2634:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VPMINu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21480        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINu8,
21481        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21482        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21483        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21484        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21485        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21486        GIR_EraseFromParent, /*InsnID*/0,
21487        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21488        // GIR_Coverage, 1295,
21489        GIR_Done,
21490      // Label 1190: @54299
21491      GIM_Try, /*On fail goto*//*Label 1191*/ 54358, // Rule ID 1296 //
21492        GIM_CheckFeatures, GIFBS_HasNEON,
21493        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpminu,
21494        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21495        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21496        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21497        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21498        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21499        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21500        // (intrinsic_wo_chain:{ *:[v4i16] } 2634:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VPMINu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21501        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINu16,
21502        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21503        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21504        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21505        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21506        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21507        GIR_EraseFromParent, /*InsnID*/0,
21508        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21509        // GIR_Coverage, 1296,
21510        GIR_Done,
21511      // Label 1191: @54358
21512      GIM_Try, /*On fail goto*//*Label 1192*/ 54417, // Rule ID 1297 //
21513        GIM_CheckFeatures, GIFBS_HasNEON,
21514        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpminu,
21515        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21516        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21517        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21518        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21519        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21520        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21521        // (intrinsic_wo_chain:{ *:[v2i32] } 2634:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VPMINu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21522        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINu32,
21523        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21524        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21525        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21526        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21527        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21528        GIR_EraseFromParent, /*InsnID*/0,
21529        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21530        // GIR_Coverage, 1297,
21531        GIR_Done,
21532      // Label 1192: @54417
21533      GIM_Try, /*On fail goto*//*Label 1193*/ 54476, // Rule ID 1298 //
21534        GIM_CheckFeatures, GIFBS_HasNEON,
21535        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
21536        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21537        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21538        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21539        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21540        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21541        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21542        // (intrinsic_wo_chain:{ *:[v2f32] } 2633:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VPMINf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21543        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINf,
21544        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21545        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21546        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21547        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21548        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21549        GIR_EraseFromParent, /*InsnID*/0,
21550        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21551        // GIR_Coverage, 1298,
21552        GIR_Done,
21553      // Label 1193: @54476
21554      GIM_Try, /*On fail goto*//*Label 1194*/ 54535, // Rule ID 1299 //
21555        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
21556        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
21557        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21558        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21559        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21560        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21561        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21562        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21563        // (intrinsic_wo_chain:{ *:[v4f16] } 2633:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VPMINh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21564        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINh,
21565        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21566        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21567        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21568        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21569        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21570        GIR_EraseFromParent, /*InsnID*/0,
21571        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21572        // GIR_Coverage, 1299,
21573        GIR_Done,
21574      // Label 1194: @54535
21575      GIM_Try, /*On fail goto*//*Label 1195*/ 54594, // Rule ID 1306 //
21576        GIM_CheckFeatures, GIFBS_HasNEON,
21577        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps,
21578        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21579        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21580        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21581        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21582        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21583        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21584        // (intrinsic_wo_chain:{ *:[v2f32] } 2658:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VRECPSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21585        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPSfd,
21586        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21587        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21588        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21589        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21590        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21591        GIR_EraseFromParent, /*InsnID*/0,
21592        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21593        // GIR_Coverage, 1306,
21594        GIR_Done,
21595      // Label 1195: @54594
21596      GIM_Try, /*On fail goto*//*Label 1196*/ 54653, // Rule ID 1307 //
21597        GIM_CheckFeatures, GIFBS_HasNEON,
21598        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps,
21599        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21600        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21601        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21602        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21603        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21604        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21605        // (intrinsic_wo_chain:{ *:[v4f32] } 2658:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VRECPSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
21606        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPSfq,
21607        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21608        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21609        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21610        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21611        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21612        GIR_EraseFromParent, /*InsnID*/0,
21613        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21614        // GIR_Coverage, 1307,
21615        GIR_Done,
21616      // Label 1196: @54653
21617      GIM_Try, /*On fail goto*//*Label 1197*/ 54712, // Rule ID 1308 //
21618        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
21619        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps,
21620        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21621        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21622        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21623        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21624        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21625        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21626        // (intrinsic_wo_chain:{ *:[v4f16] } 2658:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VRECPShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21627        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPShd,
21628        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21629        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21630        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21631        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21632        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21633        GIR_EraseFromParent, /*InsnID*/0,
21634        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21635        // GIR_Coverage, 1308,
21636        GIR_Done,
21637      // Label 1197: @54712
21638      GIM_Try, /*On fail goto*//*Label 1198*/ 54771, // Rule ID 1309 //
21639        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
21640        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps,
21641        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21642        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21643        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21644        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21645        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21646        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21647        // (intrinsic_wo_chain:{ *:[v8f16] } 2658:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VRECPShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
21648        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPShq,
21649        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21650        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21651        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21652        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21653        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21654        GIR_EraseFromParent, /*InsnID*/0,
21655        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21656        // GIR_Coverage, 1309,
21657        GIR_Done,
21658      // Label 1198: @54771
21659      GIM_Try, /*On fail goto*//*Label 1199*/ 54830, // Rule ID 1316 //
21660        GIM_CheckFeatures, GIFBS_HasNEON,
21661        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts,
21662        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21663        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21664        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21665        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21666        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21667        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21668        // (intrinsic_wo_chain:{ *:[v2f32] } 2671:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VRSQRTSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21669        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTSfd,
21670        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21671        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21672        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21673        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21674        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21675        GIR_EraseFromParent, /*InsnID*/0,
21676        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21677        // GIR_Coverage, 1316,
21678        GIR_Done,
21679      // Label 1199: @54830
21680      GIM_Try, /*On fail goto*//*Label 1200*/ 54889, // Rule ID 1317 //
21681        GIM_CheckFeatures, GIFBS_HasNEON,
21682        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts,
21683        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21684        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21685        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21686        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21687        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21688        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21689        // (intrinsic_wo_chain:{ *:[v4f32] } 2671:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VRSQRTSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
21690        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTSfq,
21691        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21692        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21693        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21694        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21695        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21696        GIR_EraseFromParent, /*InsnID*/0,
21697        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21698        // GIR_Coverage, 1317,
21699        GIR_Done,
21700      // Label 1200: @54889
21701      GIM_Try, /*On fail goto*//*Label 1201*/ 54948, // Rule ID 1318 //
21702        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
21703        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts,
21704        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21705        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21706        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21707        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21708        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21709        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21710        // (intrinsic_wo_chain:{ *:[v4f16] } 2671:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VRSQRTShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21711        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTShd,
21712        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21713        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21714        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21715        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21716        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21717        GIR_EraseFromParent, /*InsnID*/0,
21718        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21719        // GIR_Coverage, 1318,
21720        GIR_Done,
21721      // Label 1201: @54948
21722      GIM_Try, /*On fail goto*//*Label 1202*/ 55007, // Rule ID 1319 //
21723        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
21724        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts,
21725        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21726        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21727        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21728        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21729        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21730        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21731        // (intrinsic_wo_chain:{ *:[v8f16] } 2671:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VRSQRTShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
21732        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTShq,
21733        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21734        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21735        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21736        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21737        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21738        GIR_EraseFromParent, /*InsnID*/0,
21739        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21740        // GIR_Coverage, 1319,
21741        GIR_Done,
21742      // Label 1202: @55007
21743      GIM_Try, /*On fail goto*//*Label 1203*/ 55066, // Rule ID 1320 //
21744        GIM_CheckFeatures, GIFBS_HasNEON,
21745        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
21746        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21747        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21748        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21749        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21750        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21751        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21752        // (intrinsic_wo_chain:{ *:[v4i16] } 2674:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
21753        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv4i16,
21754        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21755        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21756        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21757        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21758        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21759        GIR_EraseFromParent, /*InsnID*/0,
21760        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21761        // GIR_Coverage, 1320,
21762        GIR_Done,
21763      // Label 1203: @55066
21764      GIM_Try, /*On fail goto*//*Label 1204*/ 55125, // Rule ID 1321 //
21765        GIM_CheckFeatures, GIFBS_HasNEON,
21766        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
21767        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21768        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21769        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21770        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21771        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21772        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21773        // (intrinsic_wo_chain:{ *:[v2i32] } 2674:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
21774        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv2i32,
21775        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21776        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21777        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21778        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21779        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21780        GIR_EraseFromParent, /*InsnID*/0,
21781        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21782        // GIR_Coverage, 1321,
21783        GIR_Done,
21784      // Label 1204: @55125
21785      GIM_Try, /*On fail goto*//*Label 1205*/ 55184, // Rule ID 1322 //
21786        GIM_CheckFeatures, GIFBS_HasNEON,
21787        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
21788        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21789        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21790        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21791        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21792        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21793        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21794        // (intrinsic_wo_chain:{ *:[v8i16] } 2674:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
21795        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv8i16,
21796        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21797        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21798        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21799        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21800        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21801        GIR_EraseFromParent, /*InsnID*/0,
21802        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21803        // GIR_Coverage, 1322,
21804        GIR_Done,
21805      // Label 1205: @55184
21806      GIM_Try, /*On fail goto*//*Label 1206*/ 55243, // Rule ID 1323 //
21807        GIM_CheckFeatures, GIFBS_HasNEON,
21808        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
21809        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21810        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21811        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21812        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21813        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21814        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21815        // (intrinsic_wo_chain:{ *:[v4i32] } 2674:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
21816        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv4i32,
21817        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21818        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21819        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21820        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21821        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21822        GIR_EraseFromParent, /*InsnID*/0,
21823        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21824        // GIR_Coverage, 1323,
21825        GIR_Done,
21826      // Label 1206: @55243
21827      GIM_Try, /*On fail goto*//*Label 1207*/ 55302, // Rule ID 1324 //
21828        GIM_CheckFeatures, GIFBS_HasNEON,
21829        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
21830        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
21831        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
21832        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
21833        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21834        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21835        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21836        // (intrinsic_wo_chain:{ *:[v8i8] } 2674:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
21837        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv8i8,
21838        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21839        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21840        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21841        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21842        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21843        GIR_EraseFromParent, /*InsnID*/0,
21844        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21845        // GIR_Coverage, 1324,
21846        GIR_Done,
21847      // Label 1207: @55302
21848      GIM_Try, /*On fail goto*//*Label 1208*/ 55361, // Rule ID 1325 //
21849        GIM_CheckFeatures, GIFBS_HasNEON,
21850        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
21851        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
21852        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
21853        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
21854        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21855        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21856        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21857        // (intrinsic_wo_chain:{ *:[v16i8] } 2674:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
21858        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv16i8,
21859        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21860        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21861        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21862        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21863        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21864        GIR_EraseFromParent, /*InsnID*/0,
21865        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21866        // GIR_Coverage, 1325,
21867        GIR_Done,
21868      // Label 1208: @55361
21869      GIM_Try, /*On fail goto*//*Label 1209*/ 55420, // Rule ID 1326 //
21870        GIM_CheckFeatures, GIFBS_HasNEON,
21871        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
21872        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
21873        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21874        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21875        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21876        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21877        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21878        // (intrinsic_wo_chain:{ *:[v1i64] } 2674:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
21879        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv1i64,
21880        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21881        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21882        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21883        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21884        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21885        GIR_EraseFromParent, /*InsnID*/0,
21886        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21887        // GIR_Coverage, 1326,
21888        GIR_Done,
21889      // Label 1209: @55420
21890      GIM_Try, /*On fail goto*//*Label 1210*/ 55479, // Rule ID 1327 //
21891        GIM_CheckFeatures, GIFBS_HasNEON,
21892        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
21893        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
21894        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
21895        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
21896        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21897        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21898        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21899        // (intrinsic_wo_chain:{ *:[v2i64] } 2674:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
21900        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv2i64,
21901        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21902        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21903        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21904        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21905        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21906        GIR_EraseFromParent, /*InsnID*/0,
21907        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21908        // GIR_Coverage, 1327,
21909        GIR_Done,
21910      // Label 1210: @55479
21911      GIM_Try, /*On fail goto*//*Label 1211*/ 55538, // Rule ID 1328 //
21912        GIM_CheckFeatures, GIFBS_HasNEON,
21913        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
21914        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21915        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21916        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21917        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21918        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21919        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21920        // (intrinsic_wo_chain:{ *:[v4i16] } 2675:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
21921        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv4i16,
21922        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21923        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21924        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21925        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21926        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21927        GIR_EraseFromParent, /*InsnID*/0,
21928        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21929        // GIR_Coverage, 1328,
21930        GIR_Done,
21931      // Label 1211: @55538
21932      GIM_Try, /*On fail goto*//*Label 1212*/ 55597, // Rule ID 1329 //
21933        GIM_CheckFeatures, GIFBS_HasNEON,
21934        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
21935        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21936        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21937        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21938        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21939        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21940        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21941        // (intrinsic_wo_chain:{ *:[v2i32] } 2675:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
21942        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv2i32,
21943        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21944        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21945        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21946        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21947        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21948        GIR_EraseFromParent, /*InsnID*/0,
21949        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21950        // GIR_Coverage, 1329,
21951        GIR_Done,
21952      // Label 1212: @55597
21953      GIM_Try, /*On fail goto*//*Label 1213*/ 55656, // Rule ID 1330 //
21954        GIM_CheckFeatures, GIFBS_HasNEON,
21955        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
21956        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21957        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21958        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21959        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21960        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21961        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21962        // (intrinsic_wo_chain:{ *:[v8i16] } 2675:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
21963        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv8i16,
21964        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21965        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21966        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21967        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21968        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21969        GIR_EraseFromParent, /*InsnID*/0,
21970        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21971        // GIR_Coverage, 1330,
21972        GIR_Done,
21973      // Label 1213: @55656
21974      GIM_Try, /*On fail goto*//*Label 1214*/ 55715, // Rule ID 1331 //
21975        GIM_CheckFeatures, GIFBS_HasNEON,
21976        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
21977        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21978        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21979        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21980        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21981        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21982        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21983        // (intrinsic_wo_chain:{ *:[v4i32] } 2675:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
21984        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv4i32,
21985        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21986        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21987        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21988        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21989        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21990        GIR_EraseFromParent, /*InsnID*/0,
21991        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21992        // GIR_Coverage, 1331,
21993        GIR_Done,
21994      // Label 1214: @55715
21995      GIM_Try, /*On fail goto*//*Label 1215*/ 55774, // Rule ID 1332 //
21996        GIM_CheckFeatures, GIFBS_HasNEON,
21997        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
21998        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
21999        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
22000        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
22001        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22002        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22003        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22004        // (intrinsic_wo_chain:{ *:[v8i8] } 2675:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22005        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv8i8,
22006        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22007        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22008        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22009        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22010        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22011        GIR_EraseFromParent, /*InsnID*/0,
22012        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22013        // GIR_Coverage, 1332,
22014        GIR_Done,
22015      // Label 1215: @55774
22016      GIM_Try, /*On fail goto*//*Label 1216*/ 55833, // Rule ID 1333 //
22017        GIM_CheckFeatures, GIFBS_HasNEON,
22018        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
22019        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22020        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22021        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22022        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22023        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22024        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22025        // (intrinsic_wo_chain:{ *:[v16i8] } 2675:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22026        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv16i8,
22027        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22028        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22029        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22030        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22031        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22032        GIR_EraseFromParent, /*InsnID*/0,
22033        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22034        // GIR_Coverage, 1333,
22035        GIR_Done,
22036      // Label 1216: @55833
22037      GIM_Try, /*On fail goto*//*Label 1217*/ 55892, // Rule ID 1334 //
22038        GIM_CheckFeatures, GIFBS_HasNEON,
22039        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
22040        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
22041        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22042        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
22043        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22044        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22045        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22046        // (intrinsic_wo_chain:{ *:[v1i64] } 2675:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22047        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv1i64,
22048        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22049        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22050        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22051        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22052        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22053        GIR_EraseFromParent, /*InsnID*/0,
22054        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22055        // GIR_Coverage, 1334,
22056        GIR_Done,
22057      // Label 1217: @55892
22058      GIM_Try, /*On fail goto*//*Label 1218*/ 55951, // Rule ID 1335 //
22059        GIM_CheckFeatures, GIFBS_HasNEON,
22060        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
22061        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
22062        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22063        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
22064        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22065        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22066        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22067        // (intrinsic_wo_chain:{ *:[v2i64] } 2675:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22068        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv2i64,
22069        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22070        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22071        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22072        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22073        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22074        GIR_EraseFromParent, /*InsnID*/0,
22075        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22076        // GIR_Coverage, 1335,
22077        GIR_Done,
22078      // Label 1218: @55951
22079      GIM_Try, /*On fail goto*//*Label 1219*/ 56010, // Rule ID 1369 //
22080        GIM_CheckFeatures, GIFBS_HasNEON,
22081        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
22082        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
22083        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
22084        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
22085        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22086        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22087        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22088        // (intrinsic_wo_chain:{ *:[v4i16] } 2668:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22089        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv4i16,
22090        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22091        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22092        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22093        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22094        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22095        GIR_EraseFromParent, /*InsnID*/0,
22096        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22097        // GIR_Coverage, 1369,
22098        GIR_Done,
22099      // Label 1219: @56010
22100      GIM_Try, /*On fail goto*//*Label 1220*/ 56069, // Rule ID 1370 //
22101        GIM_CheckFeatures, GIFBS_HasNEON,
22102        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
22103        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
22104        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
22105        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
22106        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22107        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22108        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22109        // (intrinsic_wo_chain:{ *:[v2i32] } 2668:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22110        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv2i32,
22111        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22112        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22113        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22114        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22115        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22116        GIR_EraseFromParent, /*InsnID*/0,
22117        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22118        // GIR_Coverage, 1370,
22119        GIR_Done,
22120      // Label 1220: @56069
22121      GIM_Try, /*On fail goto*//*Label 1221*/ 56128, // Rule ID 1371 //
22122        GIM_CheckFeatures, GIFBS_HasNEON,
22123        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
22124        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22125        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22126        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22127        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22128        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22129        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22130        // (intrinsic_wo_chain:{ *:[v8i16] } 2668:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22131        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv8i16,
22132        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22133        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22134        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22135        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22136        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22137        GIR_EraseFromParent, /*InsnID*/0,
22138        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22139        // GIR_Coverage, 1371,
22140        GIR_Done,
22141      // Label 1221: @56128
22142      GIM_Try, /*On fail goto*//*Label 1222*/ 56187, // Rule ID 1372 //
22143        GIM_CheckFeatures, GIFBS_HasNEON,
22144        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
22145        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22146        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22147        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22148        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22149        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22150        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22151        // (intrinsic_wo_chain:{ *:[v4i32] } 2668:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22152        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv4i32,
22153        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22154        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22155        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22156        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22157        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22158        GIR_EraseFromParent, /*InsnID*/0,
22159        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22160        // GIR_Coverage, 1372,
22161        GIR_Done,
22162      // Label 1222: @56187
22163      GIM_Try, /*On fail goto*//*Label 1223*/ 56246, // Rule ID 1373 //
22164        GIM_CheckFeatures, GIFBS_HasNEON,
22165        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
22166        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
22167        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
22168        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
22169        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22170        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22171        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22172        // (intrinsic_wo_chain:{ *:[v8i8] } 2668:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22173        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv8i8,
22174        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22175        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22176        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22177        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22178        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22179        GIR_EraseFromParent, /*InsnID*/0,
22180        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22181        // GIR_Coverage, 1373,
22182        GIR_Done,
22183      // Label 1223: @56246
22184      GIM_Try, /*On fail goto*//*Label 1224*/ 56305, // Rule ID 1374 //
22185        GIM_CheckFeatures, GIFBS_HasNEON,
22186        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
22187        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22188        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22189        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22190        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22191        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22192        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22193        // (intrinsic_wo_chain:{ *:[v16i8] } 2668:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22194        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv16i8,
22195        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22196        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22197        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22198        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22199        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22200        GIR_EraseFromParent, /*InsnID*/0,
22201        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22202        // GIR_Coverage, 1374,
22203        GIR_Done,
22204      // Label 1224: @56305
22205      GIM_Try, /*On fail goto*//*Label 1225*/ 56364, // Rule ID 1375 //
22206        GIM_CheckFeatures, GIFBS_HasNEON,
22207        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
22208        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
22209        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22210        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
22211        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22212        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22213        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22214        // (intrinsic_wo_chain:{ *:[v1i64] } 2668:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22215        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv1i64,
22216        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22217        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22218        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22219        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22220        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22221        GIR_EraseFromParent, /*InsnID*/0,
22222        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22223        // GIR_Coverage, 1375,
22224        GIR_Done,
22225      // Label 1225: @56364
22226      GIM_Try, /*On fail goto*//*Label 1226*/ 56423, // Rule ID 1376 //
22227        GIM_CheckFeatures, GIFBS_HasNEON,
22228        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
22229        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
22230        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22231        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
22232        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22233        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22234        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22235        // (intrinsic_wo_chain:{ *:[v2i64] } 2668:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22236        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv2i64,
22237        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22238        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22239        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22240        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22241        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22242        GIR_EraseFromParent, /*InsnID*/0,
22243        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22244        // GIR_Coverage, 1376,
22245        GIR_Done,
22246      // Label 1226: @56423
22247      GIM_Try, /*On fail goto*//*Label 1227*/ 56482, // Rule ID 1377 //
22248        GIM_CheckFeatures, GIFBS_HasNEON,
22249        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
22250        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
22251        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
22252        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
22253        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22254        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22255        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22256        // (intrinsic_wo_chain:{ *:[v4i16] } 2669:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22257        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv4i16,
22258        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22259        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22260        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22261        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22262        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22263        GIR_EraseFromParent, /*InsnID*/0,
22264        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22265        // GIR_Coverage, 1377,
22266        GIR_Done,
22267      // Label 1227: @56482
22268      GIM_Try, /*On fail goto*//*Label 1228*/ 56541, // Rule ID 1378 //
22269        GIM_CheckFeatures, GIFBS_HasNEON,
22270        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
22271        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
22272        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
22273        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
22274        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22275        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22276        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22277        // (intrinsic_wo_chain:{ *:[v2i32] } 2669:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22278        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv2i32,
22279        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22280        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22281        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22282        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22283        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22284        GIR_EraseFromParent, /*InsnID*/0,
22285        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22286        // GIR_Coverage, 1378,
22287        GIR_Done,
22288      // Label 1228: @56541
22289      GIM_Try, /*On fail goto*//*Label 1229*/ 56600, // Rule ID 1379 //
22290        GIM_CheckFeatures, GIFBS_HasNEON,
22291        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
22292        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22293        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22294        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22295        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22296        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22297        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22298        // (intrinsic_wo_chain:{ *:[v8i16] } 2669:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22299        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv8i16,
22300        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22301        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22302        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22303        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22304        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22305        GIR_EraseFromParent, /*InsnID*/0,
22306        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22307        // GIR_Coverage, 1379,
22308        GIR_Done,
22309      // Label 1229: @56600
22310      GIM_Try, /*On fail goto*//*Label 1230*/ 56659, // Rule ID 1380 //
22311        GIM_CheckFeatures, GIFBS_HasNEON,
22312        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
22313        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22314        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22315        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22316        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22317        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22318        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22319        // (intrinsic_wo_chain:{ *:[v4i32] } 2669:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22320        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv4i32,
22321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22323        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22324        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22325        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22326        GIR_EraseFromParent, /*InsnID*/0,
22327        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22328        // GIR_Coverage, 1380,
22329        GIR_Done,
22330      // Label 1230: @56659
22331      GIM_Try, /*On fail goto*//*Label 1231*/ 56718, // Rule ID 1381 //
22332        GIM_CheckFeatures, GIFBS_HasNEON,
22333        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
22334        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
22335        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
22336        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
22337        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22338        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22339        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22340        // (intrinsic_wo_chain:{ *:[v8i8] } 2669:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22341        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv8i8,
22342        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22343        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22344        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22345        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22346        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22347        GIR_EraseFromParent, /*InsnID*/0,
22348        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22349        // GIR_Coverage, 1381,
22350        GIR_Done,
22351      // Label 1231: @56718
22352      GIM_Try, /*On fail goto*//*Label 1232*/ 56777, // Rule ID 1382 //
22353        GIM_CheckFeatures, GIFBS_HasNEON,
22354        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
22355        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22356        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22357        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22358        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22359        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22360        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22361        // (intrinsic_wo_chain:{ *:[v16i8] } 2669:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22362        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv16i8,
22363        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22364        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22365        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22366        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22367        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22368        GIR_EraseFromParent, /*InsnID*/0,
22369        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22370        // GIR_Coverage, 1382,
22371        GIR_Done,
22372      // Label 1232: @56777
22373      GIM_Try, /*On fail goto*//*Label 1233*/ 56836, // Rule ID 1383 //
22374        GIM_CheckFeatures, GIFBS_HasNEON,
22375        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
22376        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
22377        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22378        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
22379        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22380        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22381        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22382        // (intrinsic_wo_chain:{ *:[v1i64] } 2669:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22383        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv1i64,
22384        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22385        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22386        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22387        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22388        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22389        GIR_EraseFromParent, /*InsnID*/0,
22390        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22391        // GIR_Coverage, 1383,
22392        GIR_Done,
22393      // Label 1233: @56836
22394      GIM_Try, /*On fail goto*//*Label 1234*/ 56895, // Rule ID 1384 //
22395        GIM_CheckFeatures, GIFBS_HasNEON,
22396        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
22397        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
22398        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22399        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
22400        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22401        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22402        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22403        // (intrinsic_wo_chain:{ *:[v2i64] } 2669:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22404        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv2i64,
22405        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22406        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22407        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22408        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22409        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22410        GIR_EraseFromParent, /*InsnID*/0,
22411        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22412        // GIR_Coverage, 1384,
22413        GIR_Done,
22414      // Label 1234: @56895
22415      GIM_Try, /*On fail goto*//*Label 1235*/ 56954, // Rule ID 1404 //
22416        GIM_CheckFeatures, GIFBS_HasNEON,
22417        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
22418        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
22419        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
22420        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
22421        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22422        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22423        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22424        // (intrinsic_wo_chain:{ *:[v4i16] } 2653:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VQSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22425        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv4i16,
22426        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22427        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22428        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22429        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22430        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22431        GIR_EraseFromParent, /*InsnID*/0,
22432        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22433        // GIR_Coverage, 1404,
22434        GIR_Done,
22435      // Label 1235: @56954
22436      GIM_Try, /*On fail goto*//*Label 1236*/ 57013, // Rule ID 1405 //
22437        GIM_CheckFeatures, GIFBS_HasNEON,
22438        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
22439        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
22440        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
22441        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
22442        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22443        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22444        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22445        // (intrinsic_wo_chain:{ *:[v2i32] } 2653:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VQSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22446        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv2i32,
22447        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22448        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22449        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22450        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22451        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22452        GIR_EraseFromParent, /*InsnID*/0,
22453        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22454        // GIR_Coverage, 1405,
22455        GIR_Done,
22456      // Label 1236: @57013
22457      GIM_Try, /*On fail goto*//*Label 1237*/ 57072, // Rule ID 1406 //
22458        GIM_CheckFeatures, GIFBS_HasNEON,
22459        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
22460        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22461        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22462        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22463        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22464        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22465        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22466        // (intrinsic_wo_chain:{ *:[v8i16] } 2653:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VQSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22467        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv8i16,
22468        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22469        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22470        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22471        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22472        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22473        GIR_EraseFromParent, /*InsnID*/0,
22474        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22475        // GIR_Coverage, 1406,
22476        GIR_Done,
22477      // Label 1237: @57072
22478      GIM_Try, /*On fail goto*//*Label 1238*/ 57131, // Rule ID 1407 //
22479        GIM_CheckFeatures, GIFBS_HasNEON,
22480        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
22481        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22482        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22483        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22484        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22485        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22486        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22487        // (intrinsic_wo_chain:{ *:[v4i32] } 2653:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VQSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22488        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv4i32,
22489        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22490        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22491        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22492        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22493        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22494        GIR_EraseFromParent, /*InsnID*/0,
22495        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22496        // GIR_Coverage, 1407,
22497        GIR_Done,
22498      // Label 1238: @57131
22499      GIM_Try, /*On fail goto*//*Label 1239*/ 57190, // Rule ID 1408 //
22500        GIM_CheckFeatures, GIFBS_HasNEON,
22501        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
22502        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
22503        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
22504        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
22505        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22506        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22507        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22508        // (intrinsic_wo_chain:{ *:[v8i8] } 2653:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VQSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22509        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv8i8,
22510        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22511        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22512        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22513        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22514        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22515        GIR_EraseFromParent, /*InsnID*/0,
22516        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22517        // GIR_Coverage, 1408,
22518        GIR_Done,
22519      // Label 1239: @57190
22520      GIM_Try, /*On fail goto*//*Label 1240*/ 57249, // Rule ID 1409 //
22521        GIM_CheckFeatures, GIFBS_HasNEON,
22522        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
22523        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22524        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22525        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22526        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22527        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22528        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22529        // (intrinsic_wo_chain:{ *:[v16i8] } 2653:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VQSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22530        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv16i8,
22531        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22532        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22533        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22534        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22535        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22536        GIR_EraseFromParent, /*InsnID*/0,
22537        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22538        // GIR_Coverage, 1409,
22539        GIR_Done,
22540      // Label 1240: @57249
22541      GIM_Try, /*On fail goto*//*Label 1241*/ 57308, // Rule ID 1410 //
22542        GIM_CheckFeatures, GIFBS_HasNEON,
22543        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
22544        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
22545        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22546        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
22547        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22548        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22549        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22550        // (intrinsic_wo_chain:{ *:[v1i64] } 2653:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VQSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22551        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv1i64,
22552        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22553        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22554        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22555        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22556        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22557        GIR_EraseFromParent, /*InsnID*/0,
22558        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22559        // GIR_Coverage, 1410,
22560        GIR_Done,
22561      // Label 1241: @57308
22562      GIM_Try, /*On fail goto*//*Label 1242*/ 57367, // Rule ID 1411 //
22563        GIM_CheckFeatures, GIFBS_HasNEON,
22564        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
22565        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
22566        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22567        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
22568        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22569        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22570        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22571        // (intrinsic_wo_chain:{ *:[v2i64] } 2653:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VQSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22572        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv2i64,
22573        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22574        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22575        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22576        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22577        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22578        GIR_EraseFromParent, /*InsnID*/0,
22579        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22580        // GIR_Coverage, 1411,
22581        GIR_Done,
22582      // Label 1242: @57367
22583      GIM_Try, /*On fail goto*//*Label 1243*/ 57426, // Rule ID 1412 //
22584        GIM_CheckFeatures, GIFBS_HasNEON,
22585        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
22586        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
22587        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
22588        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
22589        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22590        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22591        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22592        // (intrinsic_wo_chain:{ *:[v4i16] } 2655:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VQSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22593        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv4i16,
22594        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22595        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22596        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22597        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22598        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22599        GIR_EraseFromParent, /*InsnID*/0,
22600        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22601        // GIR_Coverage, 1412,
22602        GIR_Done,
22603      // Label 1243: @57426
22604      GIM_Try, /*On fail goto*//*Label 1244*/ 57485, // Rule ID 1413 //
22605        GIM_CheckFeatures, GIFBS_HasNEON,
22606        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
22607        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
22608        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
22609        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
22610        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22611        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22612        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22613        // (intrinsic_wo_chain:{ *:[v2i32] } 2655:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VQSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22614        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv2i32,
22615        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22616        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22617        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22618        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22619        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22620        GIR_EraseFromParent, /*InsnID*/0,
22621        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22622        // GIR_Coverage, 1413,
22623        GIR_Done,
22624      // Label 1244: @57485
22625      GIM_Try, /*On fail goto*//*Label 1245*/ 57544, // Rule ID 1414 //
22626        GIM_CheckFeatures, GIFBS_HasNEON,
22627        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
22628        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22629        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22630        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22631        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22632        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22633        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22634        // (intrinsic_wo_chain:{ *:[v8i16] } 2655:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VQSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22635        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv8i16,
22636        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22637        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22638        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22639        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22640        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22641        GIR_EraseFromParent, /*InsnID*/0,
22642        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22643        // GIR_Coverage, 1414,
22644        GIR_Done,
22645      // Label 1245: @57544
22646      GIM_Try, /*On fail goto*//*Label 1246*/ 57603, // Rule ID 1415 //
22647        GIM_CheckFeatures, GIFBS_HasNEON,
22648        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
22649        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22650        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22651        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22652        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22653        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22654        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22655        // (intrinsic_wo_chain:{ *:[v4i32] } 2655:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VQSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22656        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv4i32,
22657        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22658        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22659        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22660        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22661        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22662        GIR_EraseFromParent, /*InsnID*/0,
22663        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22664        // GIR_Coverage, 1415,
22665        GIR_Done,
22666      // Label 1246: @57603
22667      GIM_Try, /*On fail goto*//*Label 1247*/ 57662, // Rule ID 1416 //
22668        GIM_CheckFeatures, GIFBS_HasNEON,
22669        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
22670        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
22671        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
22672        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
22673        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22674        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22675        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22676        // (intrinsic_wo_chain:{ *:[v8i8] } 2655:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VQSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22677        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv8i8,
22678        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22679        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22680        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22681        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22682        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22683        GIR_EraseFromParent, /*InsnID*/0,
22684        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22685        // GIR_Coverage, 1416,
22686        GIR_Done,
22687      // Label 1247: @57662
22688      GIM_Try, /*On fail goto*//*Label 1248*/ 57721, // Rule ID 1417 //
22689        GIM_CheckFeatures, GIFBS_HasNEON,
22690        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
22691        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22692        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22693        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22694        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22695        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22696        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22697        // (intrinsic_wo_chain:{ *:[v16i8] } 2655:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VQSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22698        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv16i8,
22699        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22700        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22701        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22702        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22703        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22704        GIR_EraseFromParent, /*InsnID*/0,
22705        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22706        // GIR_Coverage, 1417,
22707        GIR_Done,
22708      // Label 1248: @57721
22709      GIM_Try, /*On fail goto*//*Label 1249*/ 57780, // Rule ID 1418 //
22710        GIM_CheckFeatures, GIFBS_HasNEON,
22711        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
22712        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
22713        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22714        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
22715        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22716        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22717        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22718        // (intrinsic_wo_chain:{ *:[v1i64] } 2655:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VQSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22719        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv1i64,
22720        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22721        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22722        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22723        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22724        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22725        GIR_EraseFromParent, /*InsnID*/0,
22726        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22727        // GIR_Coverage, 1418,
22728        GIR_Done,
22729      // Label 1249: @57780
22730      GIM_Try, /*On fail goto*//*Label 1250*/ 57839, // Rule ID 1419 //
22731        GIM_CheckFeatures, GIFBS_HasNEON,
22732        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
22733        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
22734        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22735        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
22736        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22737        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22738        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22739        // (intrinsic_wo_chain:{ *:[v2i64] } 2655:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VQSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22740        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv2i64,
22741        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22742        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22743        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22744        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22745        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22746        GIR_EraseFromParent, /*InsnID*/0,
22747        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22748        // GIR_Coverage, 1419,
22749        GIR_Done,
22750      // Label 1250: @57839
22751      GIM_Try, /*On fail goto*//*Label 1251*/ 57898, // Rule ID 1453 //
22752        GIM_CheckFeatures, GIFBS_HasNEON,
22753        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
22754        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
22755        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
22756        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
22757        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22758        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22759        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22760        // (intrinsic_wo_chain:{ *:[v4i16] } 2648:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VQRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22761        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv4i16,
22762        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22763        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22764        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22765        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22766        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22767        GIR_EraseFromParent, /*InsnID*/0,
22768        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22769        // GIR_Coverage, 1453,
22770        GIR_Done,
22771      // Label 1251: @57898
22772      GIM_Try, /*On fail goto*//*Label 1252*/ 57957, // Rule ID 1454 //
22773        GIM_CheckFeatures, GIFBS_HasNEON,
22774        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
22775        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
22776        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
22777        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
22778        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22779        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22780        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22781        // (intrinsic_wo_chain:{ *:[v2i32] } 2648:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VQRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22782        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv2i32,
22783        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22784        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22785        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22786        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22787        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22788        GIR_EraseFromParent, /*InsnID*/0,
22789        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22790        // GIR_Coverage, 1454,
22791        GIR_Done,
22792      // Label 1252: @57957
22793      GIM_Try, /*On fail goto*//*Label 1253*/ 58016, // Rule ID 1455 //
22794        GIM_CheckFeatures, GIFBS_HasNEON,
22795        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
22796        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22797        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22798        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22799        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22800        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22801        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22802        // (intrinsic_wo_chain:{ *:[v8i16] } 2648:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VQRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22803        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv8i16,
22804        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22805        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22806        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22807        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22808        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22809        GIR_EraseFromParent, /*InsnID*/0,
22810        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22811        // GIR_Coverage, 1455,
22812        GIR_Done,
22813      // Label 1253: @58016
22814      GIM_Try, /*On fail goto*//*Label 1254*/ 58075, // Rule ID 1456 //
22815        GIM_CheckFeatures, GIFBS_HasNEON,
22816        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
22817        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22818        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22819        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22820        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22821        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22822        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22823        // (intrinsic_wo_chain:{ *:[v4i32] } 2648:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VQRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22824        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv4i32,
22825        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22826        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22827        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22828        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22829        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22830        GIR_EraseFromParent, /*InsnID*/0,
22831        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22832        // GIR_Coverage, 1456,
22833        GIR_Done,
22834      // Label 1254: @58075
22835      GIM_Try, /*On fail goto*//*Label 1255*/ 58134, // Rule ID 1457 //
22836        GIM_CheckFeatures, GIFBS_HasNEON,
22837        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
22838        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
22839        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
22840        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
22841        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22842        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22843        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22844        // (intrinsic_wo_chain:{ *:[v8i8] } 2648:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VQRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22845        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv8i8,
22846        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22847        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22848        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22849        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22850        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22851        GIR_EraseFromParent, /*InsnID*/0,
22852        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22853        // GIR_Coverage, 1457,
22854        GIR_Done,
22855      // Label 1255: @58134
22856      GIM_Try, /*On fail goto*//*Label 1256*/ 58193, // Rule ID 1458 //
22857        GIM_CheckFeatures, GIFBS_HasNEON,
22858        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
22859        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22860        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22861        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22862        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22863        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22864        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22865        // (intrinsic_wo_chain:{ *:[v16i8] } 2648:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VQRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22866        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv16i8,
22867        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22868        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22869        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22870        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22871        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22872        GIR_EraseFromParent, /*InsnID*/0,
22873        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22874        // GIR_Coverage, 1458,
22875        GIR_Done,
22876      // Label 1256: @58193
22877      GIM_Try, /*On fail goto*//*Label 1257*/ 58252, // Rule ID 1459 //
22878        GIM_CheckFeatures, GIFBS_HasNEON,
22879        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
22880        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
22881        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22882        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
22883        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22884        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22885        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22886        // (intrinsic_wo_chain:{ *:[v1i64] } 2648:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VQRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22887        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv1i64,
22888        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22889        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22890        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22891        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22892        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22893        GIR_EraseFromParent, /*InsnID*/0,
22894        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22895        // GIR_Coverage, 1459,
22896        GIR_Done,
22897      // Label 1257: @58252
22898      GIM_Try, /*On fail goto*//*Label 1258*/ 58311, // Rule ID 1460 //
22899        GIM_CheckFeatures, GIFBS_HasNEON,
22900        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
22901        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
22902        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22903        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
22904        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22905        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22906        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22907        // (intrinsic_wo_chain:{ *:[v2i64] } 2648:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VQRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22908        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv2i64,
22909        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22910        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22911        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22912        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22913        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22914        GIR_EraseFromParent, /*InsnID*/0,
22915        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22916        // GIR_Coverage, 1460,
22917        GIR_Done,
22918      // Label 1258: @58311
22919      GIM_Try, /*On fail goto*//*Label 1259*/ 58370, // Rule ID 1461 //
22920        GIM_CheckFeatures, GIFBS_HasNEON,
22921        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
22922        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
22923        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
22924        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
22925        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22926        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22927        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22928        // (intrinsic_wo_chain:{ *:[v4i16] } 2649:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VQRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22929        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv4i16,
22930        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22931        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22932        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22933        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22934        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22935        GIR_EraseFromParent, /*InsnID*/0,
22936        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22937        // GIR_Coverage, 1461,
22938        GIR_Done,
22939      // Label 1259: @58370
22940      GIM_Try, /*On fail goto*//*Label 1260*/ 58429, // Rule ID 1462 //
22941        GIM_CheckFeatures, GIFBS_HasNEON,
22942        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
22943        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
22944        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
22945        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
22946        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22947        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22948        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22949        // (intrinsic_wo_chain:{ *:[v2i32] } 2649:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VQRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22950        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv2i32,
22951        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22952        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22953        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22954        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22955        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22956        GIR_EraseFromParent, /*InsnID*/0,
22957        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22958        // GIR_Coverage, 1462,
22959        GIR_Done,
22960      // Label 1260: @58429
22961      GIM_Try, /*On fail goto*//*Label 1261*/ 58488, // Rule ID 1463 //
22962        GIM_CheckFeatures, GIFBS_HasNEON,
22963        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
22964        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22965        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22966        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22967        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22968        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22969        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22970        // (intrinsic_wo_chain:{ *:[v8i16] } 2649:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VQRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22971        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv8i16,
22972        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22973        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22974        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22975        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22976        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22977        GIR_EraseFromParent, /*InsnID*/0,
22978        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22979        // GIR_Coverage, 1463,
22980        GIR_Done,
22981      // Label 1261: @58488
22982      GIM_Try, /*On fail goto*//*Label 1262*/ 58547, // Rule ID 1464 //
22983        GIM_CheckFeatures, GIFBS_HasNEON,
22984        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
22985        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22986        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22987        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22988        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22989        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22990        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22991        // (intrinsic_wo_chain:{ *:[v4i32] } 2649:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VQRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22992        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv4i32,
22993        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22994        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22995        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22996        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22997        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22998        GIR_EraseFromParent, /*InsnID*/0,
22999        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23000        // GIR_Coverage, 1464,
23001        GIR_Done,
23002      // Label 1262: @58547
23003      GIM_Try, /*On fail goto*//*Label 1263*/ 58606, // Rule ID 1465 //
23004        GIM_CheckFeatures, GIFBS_HasNEON,
23005        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
23006        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
23007        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
23008        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
23009        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23010        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
23011        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
23012        // (intrinsic_wo_chain:{ *:[v8i8] } 2649:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VQRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
23013        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv8i8,
23014        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23015        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
23016        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
23017        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23018        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23019        GIR_EraseFromParent, /*InsnID*/0,
23020        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23021        // GIR_Coverage, 1465,
23022        GIR_Done,
23023      // Label 1263: @58606
23024      GIM_Try, /*On fail goto*//*Label 1264*/ 58665, // Rule ID 1466 //
23025        GIM_CheckFeatures, GIFBS_HasNEON,
23026        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
23027        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
23028        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
23029        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
23030        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23031        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
23032        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
23033        // (intrinsic_wo_chain:{ *:[v16i8] } 2649:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VQRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
23034        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv16i8,
23035        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23036        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
23037        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
23038        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23039        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23040        GIR_EraseFromParent, /*InsnID*/0,
23041        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23042        // GIR_Coverage, 1466,
23043        GIR_Done,
23044      // Label 1264: @58665
23045      GIM_Try, /*On fail goto*//*Label 1265*/ 58724, // Rule ID 1467 //
23046        GIM_CheckFeatures, GIFBS_HasNEON,
23047        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
23048        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
23049        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
23050        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
23051        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23052        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
23053        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
23054        // (intrinsic_wo_chain:{ *:[v1i64] } 2649:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VQRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
23055        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv1i64,
23056        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23057        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
23058        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
23059        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23060        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23061        GIR_EraseFromParent, /*InsnID*/0,
23062        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23063        // GIR_Coverage, 1467,
23064        GIR_Done,
23065      // Label 1265: @58724
23066      GIM_Try, /*On fail goto*//*Label 1266*/ 58783, // Rule ID 1468 //
23067        GIM_CheckFeatures, GIFBS_HasNEON,
23068        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
23069        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
23070        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
23071        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
23072        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23073        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
23074        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
23075        // (intrinsic_wo_chain:{ *:[v2i64] } 2649:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VQRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
23076        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv2i64,
23077        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23078        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
23079        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
23080        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23081        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23082        GIR_EraseFromParent, /*InsnID*/0,
23083        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23084        // GIR_Coverage, 1468,
23085        GIR_Done,
23086      // Label 1266: @58783
23087      GIM_Try, /*On fail goto*//*Label 1267*/ 58835, // Rule ID 1733 //
23088        GIM_CheckFeatures, GIFBS_HasAES_HasV8,
23089        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_aesd,
23090        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
23091        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
23092        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
23093        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23094        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
23095        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
23096        // (intrinsic_wo_chain:{ *:[v16i8] } 2550:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)  =>  (AESD:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)
23097        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESD,
23098        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23099        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
23100        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
23101        GIR_EraseFromParent, /*InsnID*/0,
23102        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23103        // GIR_Coverage, 1733,
23104        GIR_Done,
23105      // Label 1267: @58835
23106      GIM_Try, /*On fail goto*//*Label 1268*/ 58887, // Rule ID 1734 //
23107        GIM_CheckFeatures, GIFBS_HasAES_HasV8,
23108        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_aese,
23109        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
23110        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
23111        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
23112        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23113        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
23114        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
23115        // (intrinsic_wo_chain:{ *:[v16i8] } 2551:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)  =>  (AESE:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)
23116        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESE,
23117        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23118        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
23119        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
23120        GIR_EraseFromParent, /*InsnID*/0,
23121        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23122        // GIR_Coverage, 1734,
23123        GIR_Done,
23124      // Label 1268: @58887
23125      GIM_Try, /*On fail goto*//*Label 1269*/ 58939, // Rule ID 1737 //
23126        GIM_CheckFeatures, GIFBS_HasSHA2_HasV8,
23127        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1su1,
23128        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23129        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23130        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23131        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23132        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
23133        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
23134        // (intrinsic_wo_chain:{ *:[v4i32] } 2564:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA1SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)
23135        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1SU1,
23136        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23137        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
23138        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
23139        GIR_EraseFromParent, /*InsnID*/0,
23140        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23141        // GIR_Coverage, 1737,
23142        GIR_Done,
23143      // Label 1269: @58939
23144      GIM_Try, /*On fail goto*//*Label 1270*/ 58991, // Rule ID 1738 //
23145        GIM_CheckFeatures, GIFBS_HasSHA2_HasV8,
23146        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256su0,
23147        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23148        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23149        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23150        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23151        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
23152        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
23153        // (intrinsic_wo_chain:{ *:[v4i32] } 2567:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA256SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)
23154        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256SU0,
23155        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23156        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
23157        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
23158        GIR_EraseFromParent, /*InsnID*/0,
23159        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23160        // GIR_Coverage, 1738,
23161        GIR_Done,
23162      // Label 1270: @58991
23163      GIM_Try, /*On fail goto*//*Label 1271*/ 59050, // Rule ID 1752 //
23164        GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline,
23165        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_sqrshr,
23166        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23167        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23168        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23169        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23170        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23171        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23172        // (intrinsic_wo_chain:{ *:[i32] } 2412:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm)  =>  (MVE_SQRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm)
23173        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_SQRSHR,
23174        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
23175        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
23176        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23177        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23178        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23179        GIR_EraseFromParent, /*InsnID*/0,
23180        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23181        // GIR_Coverage, 1752,
23182        GIR_Done,
23183      // Label 1271: @59050
23184      GIM_Try, /*On fail goto*//*Label 1272*/ 59109, // Rule ID 1753 //
23185        GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline,
23186        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_uqrshl,
23187        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23188        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23189        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23190        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23191        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23192        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23193        // (intrinsic_wo_chain:{ *:[i32] } 2419:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm)  =>  (MVE_UQRSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm)
23194        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_UQRSHL,
23195        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
23196        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
23197        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23198        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23199        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23200        GIR_EraseFromParent, /*InsnID*/0,
23201        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23202        // GIR_Coverage, 1753,
23203        GIR_Done,
23204      // Label 1272: @59109
23205      GIM_Try, /*On fail goto*//*Label 1273*/ 59171, // Rule ID 1876 //
23206        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
23207        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sxtab16,
23208        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23209        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23210        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23211        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23212        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
23213        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
23214        // (intrinsic_wo_chain:{ *:[i32] } 2751:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS)  =>  (SXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] })
23215        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SXTAB16,
23216        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23217        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS
23218        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // RHS
23219        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23220        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23221        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23222        GIR_EraseFromParent, /*InsnID*/0,
23223        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23224        // GIR_Coverage, 1876,
23225        GIR_Done,
23226      // Label 1273: @59171
23227      GIM_Try, /*On fail goto*//*Label 1274*/ 59233, // Rule ID 1883 //
23228        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
23229        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uxtab16,
23230        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23231        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23232        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23233        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23234        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
23235        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
23236        // (intrinsic_wo_chain:{ *:[i32] } 2776:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS)  =>  (UXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] })
23237        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB16,
23238        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23239        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS
23240        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // RHS
23241        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23242        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23243        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23244        GIR_EraseFromParent, /*InsnID*/0,
23245        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23246        // GIR_Coverage, 1883,
23247        GIR_Done,
23248      // Label 1274: @59233
23249      GIM_Try, /*On fail goto*//*Label 1275*/ 59292, // Rule ID 1934 //
23250        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
23251        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smuad,
23252        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23253        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23254        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23255        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23256        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
23257        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
23258        // (intrinsic_wo_chain:{ *:[i32] } 2727:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SMUAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
23259        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUAD,
23260        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23261        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23262        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23263        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23264        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23265        GIR_EraseFromParent, /*InsnID*/0,
23266        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23267        // GIR_Coverage, 1934,
23268        GIR_Done,
23269      // Label 1275: @59292
23270      GIM_Try, /*On fail goto*//*Label 1276*/ 59351, // Rule ID 1935 //
23271        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
23272        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smuadx,
23273        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23274        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23275        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23276        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23277        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
23278        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
23279        // (intrinsic_wo_chain:{ *:[i32] } 2728:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SMUADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
23280        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUADX,
23281        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23282        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23283        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23284        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23285        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23286        GIR_EraseFromParent, /*InsnID*/0,
23287        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23288        // GIR_Coverage, 1935,
23289        GIR_Done,
23290      // Label 1276: @59351
23291      GIM_Try, /*On fail goto*//*Label 1277*/ 59410, // Rule ID 1936 //
23292        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
23293        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smusd,
23294        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23295        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23296        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23297        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23298        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
23299        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
23300        // (intrinsic_wo_chain:{ *:[i32] } 2735:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SMUSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
23301        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUSD,
23302        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23303        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23304        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23305        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23306        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23307        GIR_EraseFromParent, /*InsnID*/0,
23308        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23309        // GIR_Coverage, 1936,
23310        GIR_Done,
23311      // Label 1277: @59410
23312      GIM_Try, /*On fail goto*//*Label 1278*/ 59469, // Rule ID 1937 //
23313        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
23314        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smusdx,
23315        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23316        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23317        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23318        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23319        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
23320        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
23321        // (intrinsic_wo_chain:{ *:[i32] } 2736:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SMUSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
23322        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUSDX,
23323        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23324        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23325        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23326        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23327        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23328        GIR_EraseFromParent, /*InsnID*/0,
23329        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23330        // GIR_Coverage, 1937,
23331        GIR_Done,
23332      // Label 1278: @59469
23333      GIM_Try, /*On fail goto*//*Label 1279*/ 59528, // Rule ID 1999 //
23334        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
23335        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulbb,
23336        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23337        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23338        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23339        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
23340        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
23341        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
23342        // (intrinsic_wo_chain:{ *:[i32] } 2729:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23343        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULBB,
23344        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23345        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23346        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23347        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23348        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23349        GIR_EraseFromParent, /*InsnID*/0,
23350        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23351        // GIR_Coverage, 1999,
23352        GIR_Done,
23353      // Label 1279: @59528
23354      GIM_Try, /*On fail goto*//*Label 1280*/ 59587, // Rule ID 2000 //
23355        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
23356        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulbt,
23357        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23358        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23359        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23360        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
23361        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
23362        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
23363        // (intrinsic_wo_chain:{ *:[i32] } 2730:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23364        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULBT,
23365        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23366        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23367        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23368        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23369        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23370        GIR_EraseFromParent, /*InsnID*/0,
23371        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23372        // GIR_Coverage, 2000,
23373        GIR_Done,
23374      // Label 1280: @59587
23375      GIM_Try, /*On fail goto*//*Label 1281*/ 59646, // Rule ID 2001 //
23376        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
23377        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smultb,
23378        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23379        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23380        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23381        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
23382        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
23383        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
23384        // (intrinsic_wo_chain:{ *:[i32] } 2731:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23385        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULTB,
23386        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23387        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23388        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23389        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23390        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23391        GIR_EraseFromParent, /*InsnID*/0,
23392        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23393        // GIR_Coverage, 2001,
23394        GIR_Done,
23395      // Label 1281: @59646
23396      GIM_Try, /*On fail goto*//*Label 1282*/ 59705, // Rule ID 2002 //
23397        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
23398        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smultt,
23399        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23400        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23401        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23402        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
23403        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
23404        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
23405        // (intrinsic_wo_chain:{ *:[i32] } 2732:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23406        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULTT,
23407        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23408        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23409        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23410        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23411        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23412        GIR_EraseFromParent, /*InsnID*/0,
23413        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23414        // GIR_Coverage, 2002,
23415        GIR_Done,
23416      // Label 1282: @59705
23417      GIM_Try, /*On fail goto*//*Label 1283*/ 59764, // Rule ID 2003 //
23418        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
23419        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulwb,
23420        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23421        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23422        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23423        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
23424        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
23425        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
23426        // (intrinsic_wo_chain:{ *:[i32] } 2733:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23427        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULWB,
23428        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23429        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23430        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23431        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23432        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23433        GIR_EraseFromParent, /*InsnID*/0,
23434        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23435        // GIR_Coverage, 2003,
23436        GIR_Done,
23437      // Label 1283: @59764
23438      GIM_Try, /*On fail goto*//*Label 1284*/ 59823, // Rule ID 2004 //
23439        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
23440        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulwt,
23441        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23442        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23443        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23444        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
23445        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
23446        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
23447        // (intrinsic_wo_chain:{ *:[i32] } 2734:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23448        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULWT,
23449        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23450        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
23451        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
23452        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23453        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23454        GIR_EraseFromParent, /*InsnID*/0,
23455        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23456        // GIR_Coverage, 2004,
23457        GIR_Done,
23458      // Label 1284: @59823
23459      GIM_Try, /*On fail goto*//*Label 1285*/ 59885, // Rule ID 2108 //
23460        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
23461        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sxtab16,
23462        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23463        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23464        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23465        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23466        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23467        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23468        // (intrinsic_wo_chain:{ *:[i32] } 2751:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
23469        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SXTAB16,
23470        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23471        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23472        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23473        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23474        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23475        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23476        GIR_EraseFromParent, /*InsnID*/0,
23477        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23478        // GIR_Coverage, 2108,
23479        GIR_Done,
23480      // Label 1285: @59885
23481      GIM_Try, /*On fail goto*//*Label 1286*/ 59944, // Rule ID 2141 //
23482        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
23483        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
23484        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23485        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23486        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23487        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23488        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23489        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23490        // (intrinsic_wo_chain:{ *:[i32] } 2694:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)  =>  (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
23491        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QADD,
23492        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23493        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
23494        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
23495        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23496        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23497        GIR_EraseFromParent, /*InsnID*/0,
23498        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23499        // GIR_Coverage, 2141,
23500        GIR_Done,
23501      // Label 1286: @59944
23502      GIM_Try, /*On fail goto*//*Label 1287*/ 60003, // Rule ID 2142 //
23503        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
23504        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub,
23505        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23506        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23507        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23508        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23509        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23510        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23511        // (intrinsic_wo_chain:{ *:[i32] } 2699:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)  =>  (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
23512        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSUB,
23513        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23514        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
23515        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
23516        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23517        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23518        GIR_EraseFromParent, /*InsnID*/0,
23519        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23520        // GIR_Coverage, 2142,
23521        GIR_Done,
23522      // Label 1287: @60003
23523      GIM_Try, /*On fail goto*//*Label 1288*/ 60062, // Rule ID 2182 //
23524        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
23525        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulbb,
23526        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23527        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23528        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23529        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23530        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23531        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23532        // (intrinsic_wo_chain:{ *:[i32] } 2729:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23533        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULBB,
23534        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23535        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23536        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23537        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23538        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23539        GIR_EraseFromParent, /*InsnID*/0,
23540        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23541        // GIR_Coverage, 2182,
23542        GIR_Done,
23543      // Label 1288: @60062
23544      GIM_Try, /*On fail goto*//*Label 1289*/ 60121, // Rule ID 2183 //
23545        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
23546        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulbt,
23547        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23548        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23549        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23550        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23551        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23552        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23553        // (intrinsic_wo_chain:{ *:[i32] } 2730:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23554        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULBT,
23555        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23556        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23557        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23558        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23559        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23560        GIR_EraseFromParent, /*InsnID*/0,
23561        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23562        // GIR_Coverage, 2183,
23563        GIR_Done,
23564      // Label 1289: @60121
23565      GIM_Try, /*On fail goto*//*Label 1290*/ 60180, // Rule ID 2184 //
23566        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
23567        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smultb,
23568        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23569        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23570        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23571        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23572        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23573        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23574        // (intrinsic_wo_chain:{ *:[i32] } 2731:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23575        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULTB,
23576        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23577        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23578        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23579        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23580        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23581        GIR_EraseFromParent, /*InsnID*/0,
23582        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23583        // GIR_Coverage, 2184,
23584        GIR_Done,
23585      // Label 1290: @60180
23586      GIM_Try, /*On fail goto*//*Label 1291*/ 60239, // Rule ID 2185 //
23587        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
23588        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smultt,
23589        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23590        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23591        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23592        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23593        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23594        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23595        // (intrinsic_wo_chain:{ *:[i32] } 2732:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23596        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULTT,
23597        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23598        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23599        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23600        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23601        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23602        GIR_EraseFromParent, /*InsnID*/0,
23603        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23604        // GIR_Coverage, 2185,
23605        GIR_Done,
23606      // Label 1291: @60239
23607      GIM_Try, /*On fail goto*//*Label 1292*/ 60298, // Rule ID 2186 //
23608        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
23609        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulwb,
23610        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23611        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23612        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23613        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23614        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23615        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23616        // (intrinsic_wo_chain:{ *:[i32] } 2733:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULWB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23617        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULWB,
23618        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23619        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23620        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23621        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23622        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23623        GIR_EraseFromParent, /*InsnID*/0,
23624        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23625        // GIR_Coverage, 2186,
23626        GIR_Done,
23627      // Label 1292: @60298
23628      GIM_Try, /*On fail goto*//*Label 1293*/ 60357, // Rule ID 2187 //
23629        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
23630        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulwt,
23631        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23632        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23633        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23634        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23635        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23636        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23637        // (intrinsic_wo_chain:{ *:[i32] } 2734:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULWT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23638        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULWT,
23639        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
23640        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23641        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23642        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23643        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23644        GIR_EraseFromParent, /*InsnID*/0,
23645        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23646        // GIR_Coverage, 2187,
23647        GIR_Done,
23648      // Label 1293: @60357
23649      GIM_Try, /*On fail goto*//*Label 1294*/ 60412, // Rule ID 2507 //
23650        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8_3a,
23651        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot90,
23652        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
23653        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
23654        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
23655        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23656        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
23657        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
23658        // (intrinsic_wo_chain:{ *:[v4f16] } 2581:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm)  =>  (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 0:{ *:[i32] })
23659        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv4f16,
23660        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23661        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23662        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23663        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23664        GIR_EraseFromParent, /*InsnID*/0,
23665        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23666        // GIR_Coverage, 2507,
23667        GIR_Done,
23668      // Label 1294: @60412
23669      GIM_Try, /*On fail goto*//*Label 1295*/ 60467, // Rule ID 2508 //
23670        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8_3a,
23671        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot270,
23672        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
23673        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
23674        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
23675        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23676        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
23677        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
23678        // (intrinsic_wo_chain:{ *:[v4f16] } 2580:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm)  =>  (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 1:{ *:[i32] })
23679        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv4f16,
23680        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23681        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23682        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23683        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
23684        GIR_EraseFromParent, /*InsnID*/0,
23685        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23686        // GIR_Coverage, 2508,
23687        GIR_Done,
23688      // Label 1295: @60467
23689      GIM_Try, /*On fail goto*//*Label 1296*/ 60522, // Rule ID 2509 //
23690        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8_3a,
23691        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot90,
23692        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
23693        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
23694        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23695        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23696        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
23697        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
23698        // (intrinsic_wo_chain:{ *:[v8f16] } 2581:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm)  =>  (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 0:{ *:[i32] })
23699        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv8f16,
23700        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23701        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23702        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23703        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23704        GIR_EraseFromParent, /*InsnID*/0,
23705        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23706        // GIR_Coverage, 2509,
23707        GIR_Done,
23708      // Label 1296: @60522
23709      GIM_Try, /*On fail goto*//*Label 1297*/ 60577, // Rule ID 2510 //
23710        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8_3a,
23711        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot270,
23712        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
23713        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
23714        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23715        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23716        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
23717        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
23718        // (intrinsic_wo_chain:{ *:[v8f16] } 2580:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm)  =>  (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 1:{ *:[i32] })
23719        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv8f16,
23720        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23721        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23722        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23723        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
23724        GIR_EraseFromParent, /*InsnID*/0,
23725        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23726        // GIR_Coverage, 2510,
23727        GIR_Done,
23728      // Label 1297: @60577
23729      GIM_Try, /*On fail goto*//*Label 1298*/ 60632, // Rule ID 2511 //
23730        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_3a,
23731        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot90,
23732        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
23733        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
23734        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
23735        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23736        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
23737        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
23738        // (intrinsic_wo_chain:{ *:[v2f32] } 2581:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm)  =>  (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 0:{ *:[i32] })
23739        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv2f32,
23740        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23741        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23742        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23743        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23744        GIR_EraseFromParent, /*InsnID*/0,
23745        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23746        // GIR_Coverage, 2511,
23747        GIR_Done,
23748      // Label 1298: @60632
23749      GIM_Try, /*On fail goto*//*Label 1299*/ 60687, // Rule ID 2512 //
23750        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_3a,
23751        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot270,
23752        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
23753        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
23754        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
23755        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23756        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
23757        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
23758        // (intrinsic_wo_chain:{ *:[v2f32] } 2580:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm)  =>  (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 1:{ *:[i32] })
23759        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv2f32,
23760        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23762        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23763        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
23764        GIR_EraseFromParent, /*InsnID*/0,
23765        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23766        // GIR_Coverage, 2512,
23767        GIR_Done,
23768      // Label 1299: @60687
23769      GIM_Try, /*On fail goto*//*Label 1300*/ 60742, // Rule ID 2513 //
23770        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_3a,
23771        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot90,
23772        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23773        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23774        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23775        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23776        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
23777        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
23778        // (intrinsic_wo_chain:{ *:[v4f32] } 2581:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm)  =>  (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 0:{ *:[i32] })
23779        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv4f32,
23780        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23781        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23782        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23783        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23784        GIR_EraseFromParent, /*InsnID*/0,
23785        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23786        // GIR_Coverage, 2513,
23787        GIR_Done,
23788      // Label 1300: @60742
23789      GIM_Try, /*On fail goto*//*Label 1301*/ 60797, // Rule ID 2514 //
23790        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_3a,
23791        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot270,
23792        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23793        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23794        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23795        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23796        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
23797        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
23798        // (intrinsic_wo_chain:{ *:[v4f32] } 2580:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm)  =>  (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 1:{ *:[i32] })
23799        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv4f32,
23800        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23801        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23802        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23803        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
23804        GIR_EraseFromParent, /*InsnID*/0,
23805        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23806        // GIR_Coverage, 2514,
23807        GIR_Done,
23808      // Label 1301: @60797
23809      GIM_Try, /*On fail goto*//*Label 1302*/ 60894, // Rule ID 3199 //
23810        GIM_CheckFeatures, GIFBS_HasMVEFloat,
23811        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minnmv,
23812        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23813        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23814        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23815        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
23816        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
23817        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23818        // (intrinsic_wo_chain:{ *:[f32] } 2388:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec)  =>  (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
23819        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23820        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23821        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
23822        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
23823        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23824        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23825        GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::MVE_VMINNMVf32,
23826        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23827        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
23828        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23829        GIR_AddImm, /*InsnID*/1, /*Imm*/0,
23830        GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23831        GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23832        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23833        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23834        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23835        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23836        GIR_EraseFromParent, /*InsnID*/0,
23837        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
23838        // GIR_Coverage, 3199,
23839        GIR_Done,
23840      // Label 1302: @60894
23841      GIM_Try, /*On fail goto*//*Label 1303*/ 60991, // Rule ID 3201 //
23842        GIM_CheckFeatures, GIFBS_HasMVEFloat,
23843        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minnmv,
23844        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
23845        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
23846        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23847        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
23848        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
23849        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23850        // (intrinsic_wo_chain:{ *:[f16] } 2388:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec)  =>  (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
23851        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23852        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23853        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
23854        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
23855        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23856        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23857        GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::MVE_VMINNMVf16,
23858        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23859        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
23860        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23861        GIR_AddImm, /*InsnID*/1, /*Imm*/0,
23862        GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23863        GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23864        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23865        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23866        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23867        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23868        GIR_EraseFromParent, /*InsnID*/0,
23869        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::HPRRegClassID,
23870        // GIR_Coverage, 3201,
23871        GIR_Done,
23872      // Label 1303: @60991
23873      GIM_Try, /*On fail goto*//*Label 1304*/ 61088, // Rule ID 3203 //
23874        GIM_CheckFeatures, GIFBS_HasMVEFloat,
23875        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxnmv,
23876        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23877        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23878        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23879        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
23880        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
23881        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23882        // (intrinsic_wo_chain:{ *:[f32] } 2379:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec)  =>  (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
23883        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23884        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23885        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
23886        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
23887        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23888        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23889        GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::MVE_VMAXNMVf32,
23890        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23891        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
23892        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23893        GIR_AddImm, /*InsnID*/1, /*Imm*/0,
23894        GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23895        GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23896        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23897        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23898        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23899        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23900        GIR_EraseFromParent, /*InsnID*/0,
23901        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
23902        // GIR_Coverage, 3203,
23903        GIR_Done,
23904      // Label 1304: @61088
23905      GIM_Try, /*On fail goto*//*Label 1305*/ 61185, // Rule ID 3205 //
23906        GIM_CheckFeatures, GIFBS_HasMVEFloat,
23907        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxnmv,
23908        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
23909        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
23910        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23911        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
23912        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
23913        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23914        // (intrinsic_wo_chain:{ *:[f16] } 2379:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec)  =>  (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
23915        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23916        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23917        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
23918        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
23919        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23920        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23921        GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::MVE_VMAXNMVf16,
23922        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23923        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
23924        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23925        GIR_AddImm, /*InsnID*/1, /*Imm*/0,
23926        GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23927        GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23928        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23929        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23930        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23931        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23932        GIR_EraseFromParent, /*InsnID*/0,
23933        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::HPRRegClassID,
23934        // GIR_Coverage, 3205,
23935        GIR_Done,
23936      // Label 1305: @61185
23937      GIM_Try, /*On fail goto*//*Label 1306*/ 61282, // Rule ID 3207 //
23938        GIM_CheckFeatures, GIFBS_HasMVEFloat,
23939        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minnmav,
23940        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23941        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23942        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23943        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
23944        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
23945        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23946        // (intrinsic_wo_chain:{ *:[f32] } 2386:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec)  =>  (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
23947        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23948        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23949        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
23950        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
23951        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23952        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23953        GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::MVE_VMINNMAVf32,
23954        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23955        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
23956        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23957        GIR_AddImm, /*InsnID*/1, /*Imm*/0,
23958        GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23959        GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23960        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23961        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23962        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23963        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23964        GIR_EraseFromParent, /*InsnID*/0,
23965        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
23966        // GIR_Coverage, 3207,
23967        GIR_Done,
23968      // Label 1306: @61282
23969      GIM_Try, /*On fail goto*//*Label 1307*/ 61379, // Rule ID 3209 //
23970        GIM_CheckFeatures, GIFBS_HasMVEFloat,
23971        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minnmav,
23972        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
23973        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
23974        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23975        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
23976        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
23977        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23978        // (intrinsic_wo_chain:{ *:[f16] } 2386:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec)  =>  (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
23979        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23980        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23981        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
23982        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
23983        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23984        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23985        GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::MVE_VMINNMAVf16,
23986        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23987        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
23988        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23989        GIR_AddImm, /*InsnID*/1, /*Imm*/0,
23990        GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23991        GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23992        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23993        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23994        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23995        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23996        GIR_EraseFromParent, /*InsnID*/0,
23997        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::HPRRegClassID,
23998        // GIR_Coverage, 3209,
23999        GIR_Done,
24000      // Label 1307: @61379
24001      GIM_Try, /*On fail goto*//*Label 1308*/ 61476, // Rule ID 3211 //
24002        GIM_CheckFeatures, GIFBS_HasMVEFloat,
24003        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxnmav,
24004        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24005        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24006        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24007        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
24008        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
24009        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24010        // (intrinsic_wo_chain:{ *:[f32] } 2377:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec)  =>  (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
24011        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24012        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
24013        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
24014        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
24015        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
24016        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
24017        GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::MVE_VMAXNMAVf32,
24018        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
24019        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
24020        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
24021        GIR_AddImm, /*InsnID*/1, /*Imm*/0,
24022        GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24023        GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24024        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24025        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
24026        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
24027        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24028        GIR_EraseFromParent, /*InsnID*/0,
24029        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
24030        // GIR_Coverage, 3211,
24031        GIR_Done,
24032      // Label 1308: @61476
24033      GIM_Try, /*On fail goto*//*Label 1309*/ 61573, // Rule ID 3213 //
24034        GIM_CheckFeatures, GIFBS_HasMVEFloat,
24035        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxnmav,
24036        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
24037        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
24038        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24039        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
24040        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
24041        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24042        // (intrinsic_wo_chain:{ *:[f16] } 2377:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec)  =>  (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
24043        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24044        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
24045        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
24046        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
24047        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
24048        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
24049        GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::MVE_VMAXNMAVf16,
24050        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
24051        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
24052        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
24053        GIR_AddImm, /*InsnID*/1, /*Imm*/0,
24054        GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24055        GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24056        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24057        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
24058        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
24059        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24060        GIR_EraseFromParent, /*InsnID*/0,
24061        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::HPRRegClassID,
24062        // GIR_Coverage, 3213,
24063        GIR_Done,
24064      // Label 1309: @61573
24065      GIM_Try, /*On fail goto*//*Label 1310*/ 61636, // Rule ID 3263 //
24066        GIM_CheckFeatures, GIFBS_HasMVEInt,
24067        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minav,
24068        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24069        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24070        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
24071        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24072        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
24073        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24074        // (intrinsic_wo_chain:{ *:[i32] } 2384:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)  =>  (MVE_VMINAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
24075        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINAVs8,
24076        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
24077        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24078        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24079        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24080        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24081        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24082        GIR_EraseFromParent, /*InsnID*/0,
24083        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24084        // GIR_Coverage, 3263,
24085        GIR_Done,
24086      // Label 1310: @61636
24087      GIM_Try, /*On fail goto*//*Label 1311*/ 61699, // Rule ID 3265 //
24088        GIM_CheckFeatures, GIFBS_HasMVEInt,
24089        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minav,
24090        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24091        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24092        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24093        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24094        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
24095        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24096        // (intrinsic_wo_chain:{ *:[i32] } 2384:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)  =>  (MVE_VMINAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
24097        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINAVs16,
24098        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
24099        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24100        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24101        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24102        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24103        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24104        GIR_EraseFromParent, /*InsnID*/0,
24105        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24106        // GIR_Coverage, 3265,
24107        GIR_Done,
24108      // Label 1311: @61699
24109      GIM_Try, /*On fail goto*//*Label 1312*/ 61762, // Rule ID 3267 //
24110        GIM_CheckFeatures, GIFBS_HasMVEInt,
24111        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minav,
24112        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24113        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24114        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24115        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24116        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
24117        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24118        // (intrinsic_wo_chain:{ *:[i32] } 2384:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)  =>  (MVE_VMINAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
24119        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINAVs32,
24120        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
24121        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24122        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24123        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24124        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24125        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24126        GIR_EraseFromParent, /*InsnID*/0,
24127        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24128        // GIR_Coverage, 3267,
24129        GIR_Done,
24130      // Label 1312: @61762
24131      GIM_Try, /*On fail goto*//*Label 1313*/ 61825, // Rule ID 3269 //
24132        GIM_CheckFeatures, GIFBS_HasMVEInt,
24133        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxav,
24134        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24135        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24136        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
24137        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24138        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
24139        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24140        // (intrinsic_wo_chain:{ *:[i32] } 2375:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)  =>  (MVE_VMAXAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
24141        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXAVs8,
24142        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
24143        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24144        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24145        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24146        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24147        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24148        GIR_EraseFromParent, /*InsnID*/0,
24149        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24150        // GIR_Coverage, 3269,
24151        GIR_Done,
24152      // Label 1313: @61825
24153      GIM_Try, /*On fail goto*//*Label 1314*/ 61888, // Rule ID 3271 //
24154        GIM_CheckFeatures, GIFBS_HasMVEInt,
24155        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxav,
24156        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24157        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24158        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24159        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24160        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
24161        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24162        // (intrinsic_wo_chain:{ *:[i32] } 2375:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)  =>  (MVE_VMAXAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
24163        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXAVs16,
24164        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
24165        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24166        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24167        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24168        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24169        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24170        GIR_EraseFromParent, /*InsnID*/0,
24171        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24172        // GIR_Coverage, 3271,
24173        GIR_Done,
24174      // Label 1314: @61888
24175      GIM_Try, /*On fail goto*//*Label 1315*/ 61951, // Rule ID 3273 //
24176        GIM_CheckFeatures, GIFBS_HasMVEInt,
24177        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxav,
24178        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24179        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24180        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24181        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24182        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
24183        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24184        // (intrinsic_wo_chain:{ *:[i32] } 2375:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)  =>  (MVE_VMAXAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
24185        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXAVs32,
24186        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
24187        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24188        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24189        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24190        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24191        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24192        GIR_EraseFromParent, /*InsnID*/0,
24193        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24194        // GIR_Coverage, 3273,
24195        GIR_Done,
24196      // Label 1315: @61951
24197      GIM_Try, /*On fail goto*//*Label 1316*/ 62028, // Rule ID 3564 //
24198        GIM_CheckFeatures, GIFBS_HasMVEInt,
24199        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmulh,
24200        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
24201        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24202        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
24203        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24204        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24205        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24206        // (intrinsic_wo_chain:{ *:[v16i8] } 2497:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VQDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
24207        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24208        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24209        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24210        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMULHi8,
24211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24212        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24213        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24214        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24215        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24216        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24217        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24218        GIR_EraseFromParent, /*InsnID*/0,
24219        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24220        // GIR_Coverage, 3564,
24221        GIR_Done,
24222      // Label 1316: @62028
24223      GIM_Try, /*On fail goto*//*Label 1317*/ 62105, // Rule ID 3571 //
24224        GIM_CheckFeatures, GIFBS_HasMVEInt,
24225        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmulh,
24226        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24227        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24228        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24229        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24230        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24231        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24232        // (intrinsic_wo_chain:{ *:[v8i16] } 2497:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VQDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
24233        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24234        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24235        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24236        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMULHi16,
24237        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24238        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24239        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24240        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24241        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24242        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24243        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24244        GIR_EraseFromParent, /*InsnID*/0,
24245        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24246        // GIR_Coverage, 3571,
24247        GIR_Done,
24248      // Label 1317: @62105
24249      GIM_Try, /*On fail goto*//*Label 1318*/ 62182, // Rule ID 3575 //
24250        GIM_CheckFeatures, GIFBS_HasMVEInt,
24251        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmulh,
24252        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24253        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24254        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24255        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24256        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24257        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24258        // (intrinsic_wo_chain:{ *:[v4i32] } 2497:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VQDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
24259        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24260        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24261        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24262        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMULHi32,
24263        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24264        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24265        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24266        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24267        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24268        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24269        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24270        GIR_EraseFromParent, /*InsnID*/0,
24271        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24272        // GIR_Coverage, 3575,
24273        GIR_Done,
24274      // Label 1318: @62182
24275      GIM_Try, /*On fail goto*//*Label 1319*/ 62259, // Rule ID 3577 //
24276        GIM_CheckFeatures, GIFBS_HasMVEInt,
24277        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmulh,
24278        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
24279        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24280        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
24281        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24282        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24283        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24284        // (intrinsic_wo_chain:{ *:[v16i8] } 2506:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VQRDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
24285        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24286        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24287        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24288        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMULHi8,
24289        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24290        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24291        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24292        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24293        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24294        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24295        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24296        GIR_EraseFromParent, /*InsnID*/0,
24297        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24298        // GIR_Coverage, 3577,
24299        GIR_Done,
24300      // Label 1319: @62259
24301      GIM_Try, /*On fail goto*//*Label 1320*/ 62336, // Rule ID 3579 //
24302        GIM_CheckFeatures, GIFBS_HasMVEInt,
24303        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmulh,
24304        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24305        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24306        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24307        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24308        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24309        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24310        // (intrinsic_wo_chain:{ *:[v8i16] } 2506:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VQRDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
24311        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24312        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24313        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24314        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMULHi16,
24315        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24316        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24317        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24318        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24319        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24320        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24321        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24322        GIR_EraseFromParent, /*InsnID*/0,
24323        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24324        // GIR_Coverage, 3579,
24325        GIR_Done,
24326      // Label 1320: @62336
24327      GIM_Try, /*On fail goto*//*Label 1321*/ 62413, // Rule ID 3581 //
24328        GIM_CheckFeatures, GIFBS_HasMVEInt,
24329        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmulh,
24330        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24331        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24332        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24333        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24334        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24335        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24336        // (intrinsic_wo_chain:{ *:[v4i32] } 2506:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VQRDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
24337        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24338        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24339        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24340        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMULHi32,
24341        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24342        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24343        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24344        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24345        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24346        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24347        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24348        GIR_EraseFromParent, /*InsnID*/0,
24349        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24350        // GIR_Coverage, 3581,
24351        GIR_Done,
24352      // Label 1321: @62413
24353      GIM_Try, /*On fail goto*//*Label 1322*/ 62490, // Rule ID 4853 //
24354        GIM_CheckFeatures, GIFBS_HasMVEInt,
24355        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vbrsr,
24356        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
24357        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24358        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24359        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24360        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24361        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
24362        // (intrinsic_wo_chain:{ *:[v16i8] } 2430:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm)  =>  (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm)
24363        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24364        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24365        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24366        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR8,
24367        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24368        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
24369        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
24370        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24371        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24372        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24373        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24374        GIR_EraseFromParent, /*InsnID*/0,
24375        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24376        // GIR_Coverage, 4853,
24377        GIR_Done,
24378      // Label 1322: @62490
24379      GIM_Try, /*On fail goto*//*Label 1323*/ 62567, // Rule ID 4858 //
24380        GIM_CheckFeatures, GIFBS_HasMVEInt,
24381        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vbrsr,
24382        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24383        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24384        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24385        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24386        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24387        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
24388        // (intrinsic_wo_chain:{ *:[v8i16] } 2430:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm)  =>  (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm)
24389        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24390        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24391        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24392        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR16,
24393        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24394        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
24395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
24396        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24397        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24398        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24399        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24400        GIR_EraseFromParent, /*InsnID*/0,
24401        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24402        // GIR_Coverage, 4858,
24403        GIR_Done,
24404      // Label 1323: @62567
24405      GIM_Try, /*On fail goto*//*Label 1324*/ 62644, // Rule ID 4860 //
24406        GIM_CheckFeatures, GIFBS_HasMVEInt,
24407        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vbrsr,
24408        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24409        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24410        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24411        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24412        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24413        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
24414        // (intrinsic_wo_chain:{ *:[v4i32] } 2430:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm)  =>  (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm)
24415        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24416        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24417        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24418        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR32,
24419        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24420        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
24421        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
24422        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24423        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24424        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24425        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24426        GIR_EraseFromParent, /*InsnID*/0,
24427        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24428        // GIR_Coverage, 4860,
24429        GIR_Done,
24430      // Label 1324: @62644
24431      GIM_Try, /*On fail goto*//*Label 1325*/ 62721, // Rule ID 4862 //
24432        GIM_CheckFeatures, GIFBS_HasMVEFloat,
24433        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vbrsr,
24434        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24435        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24436        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24437        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24438        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24439        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
24440        // (intrinsic_wo_chain:{ *:[v8f16] } 2430:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm)  =>  (MVE_VBRSR16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm)
24441        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24442        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24443        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24444        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR16,
24445        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24446        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
24447        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
24448        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24449        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24450        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24451        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24452        GIR_EraseFromParent, /*InsnID*/0,
24453        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24454        // GIR_Coverage, 4862,
24455        GIR_Done,
24456      // Label 1325: @62721
24457      GIM_Try, /*On fail goto*//*Label 1326*/ 62798, // Rule ID 4864 //
24458        GIM_CheckFeatures, GIFBS_HasMVEFloat,
24459        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vbrsr,
24460        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24461        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24462        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24463        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24464        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24465        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
24466        // (intrinsic_wo_chain:{ *:[v4f32] } 2430:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm)  =>  (MVE_VBRSR32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm)
24467        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24468        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24469        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24470        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR32,
24471        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24472        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
24473        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
24474        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24475        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24476        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24477        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24478        GIR_EraseFromParent, /*InsnID*/0,
24479        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24480        // GIR_Coverage, 4864,
24481        GIR_Done,
24482      // Label 1326: @62798
24483      GIM_Reject,
24484    // Label 959: @62799
24485    GIM_Try, /*On fail goto*//*Label 1327*/ 75418,
24486      GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
24487      GIM_Try, /*On fail goto*//*Label 1328*/ 62894, // Rule ID 4016 //
24488        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm,
24489        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
24490        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24491        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24492        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24493        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24494        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24495        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24496        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24497        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_7,
24498        // MIs[1] Operand 1
24499        // No operand predicates
24500        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24501        GIM_CheckIsSafeToFold, /*InsnID*/1,
24502        // (intrinsic_wo_chain:{ *:[v16i8] } 2507:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 0:{ *:[i32] })  =>  (MVE_VQSHLimms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
24503        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24504        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24505        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24506        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimms8,
24507        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24508        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24509        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24510        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24511        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24512        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24513        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24514        GIR_EraseFromParent, /*InsnID*/0,
24515        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24516        // GIR_Coverage, 4016,
24517        GIR_Done,
24518      // Label 1328: @62894
24519      GIM_Try, /*On fail goto*//*Label 1329*/ 62984, // Rule ID 4018 //
24520        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm,
24521        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
24522        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24523        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24524        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24525        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24526        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24527        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24528        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24529        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_7,
24530        // MIs[1] Operand 1
24531        // No operand predicates
24532        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24533        GIM_CheckIsSafeToFold, /*InsnID*/1,
24534        // (intrinsic_wo_chain:{ *:[v16i8] } 2507:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 1:{ *:[i32] })  =>  (MVE_VQSHLimmu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
24535        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24536        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24537        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24538        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimmu8,
24539        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24540        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24541        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24542        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24543        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24544        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24545        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24546        GIR_EraseFromParent, /*InsnID*/0,
24547        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24548        // GIR_Coverage, 4018,
24549        GIR_Done,
24550      // Label 1329: @62984
24551      GIM_Try, /*On fail goto*//*Label 1330*/ 63074, // Rule ID 4020 //
24552        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm,
24553        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24554        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24555        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24556        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24557        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24558        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24559        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24560        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24561        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
24562        // MIs[1] Operand 1
24563        // No operand predicates
24564        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24565        GIM_CheckIsSafeToFold, /*InsnID*/1,
24566        // (intrinsic_wo_chain:{ *:[v8i16] } 2507:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 0:{ *:[i32] })  =>  (MVE_VQSHLimms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
24567        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24568        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24569        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24570        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimms16,
24571        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24572        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24573        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24574        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24575        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24576        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24577        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24578        GIR_EraseFromParent, /*InsnID*/0,
24579        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24580        // GIR_Coverage, 4020,
24581        GIR_Done,
24582      // Label 1330: @63074
24583      GIM_Try, /*On fail goto*//*Label 1331*/ 63164, // Rule ID 4022 //
24584        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm,
24585        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24586        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24587        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24588        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24589        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24590        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24591        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24592        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24593        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
24594        // MIs[1] Operand 1
24595        // No operand predicates
24596        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24597        GIM_CheckIsSafeToFold, /*InsnID*/1,
24598        // (intrinsic_wo_chain:{ *:[v8i16] } 2507:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 1:{ *:[i32] })  =>  (MVE_VQSHLimmu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
24599        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24600        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24601        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24602        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimmu16,
24603        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24604        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24605        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24606        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24607        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24608        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24609        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24610        GIR_EraseFromParent, /*InsnID*/0,
24611        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24612        // GIR_Coverage, 4022,
24613        GIR_Done,
24614      // Label 1331: @63164
24615      GIM_Try, /*On fail goto*//*Label 1332*/ 63254, // Rule ID 4024 //
24616        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm,
24617        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24618        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24619        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24620        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24621        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24622        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24623        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24624        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24625        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
24626        // MIs[1] Operand 1
24627        // No operand predicates
24628        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24629        GIM_CheckIsSafeToFold, /*InsnID*/1,
24630        // (intrinsic_wo_chain:{ *:[v4i32] } 2507:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 0:{ *:[i32] })  =>  (MVE_VQSHLimms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
24631        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24632        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24633        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24634        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimms32,
24635        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24636        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24637        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24638        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24639        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24640        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24641        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24642        GIR_EraseFromParent, /*InsnID*/0,
24643        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24644        // GIR_Coverage, 4024,
24645        GIR_Done,
24646      // Label 1332: @63254
24647      GIM_Try, /*On fail goto*//*Label 1333*/ 63344, // Rule ID 4026 //
24648        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm,
24649        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24650        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24651        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24652        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24653        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24654        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24655        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24656        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24657        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
24658        // MIs[1] Operand 1
24659        // No operand predicates
24660        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24661        GIM_CheckIsSafeToFold, /*InsnID*/1,
24662        // (intrinsic_wo_chain:{ *:[v4i32] } 2507:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 1:{ *:[i32] })  =>  (MVE_VQSHLimmu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
24663        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24664        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24665        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24666        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimmu32,
24667        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24668        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24669        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24670        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24671        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24672        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24673        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24674        GIR_EraseFromParent, /*InsnID*/0,
24675        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24676        // GIR_Coverage, 4026,
24677        GIR_Done,
24678      // Label 1333: @63344
24679      GIM_Try, /*On fail goto*//*Label 1334*/ 63434, // Rule ID 4034 //
24680        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm,
24681        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
24682        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24683        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24684        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24685        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24686        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24687        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24688        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24689        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
24690        // MIs[1] Operand 1
24691        // No operand predicates
24692        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24693        GIM_CheckIsSafeToFold, /*InsnID*/1,
24694        // (intrinsic_wo_chain:{ *:[v16i8] } 2524:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] })  =>  (MVE_VRSHR_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)
24695        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24696        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24697        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24698        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_imms8,
24699        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24700        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24701        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24702        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24703        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24704        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24705        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24706        GIR_EraseFromParent, /*InsnID*/0,
24707        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24708        // GIR_Coverage, 4034,
24709        GIR_Done,
24710      // Label 1334: @63434
24711      GIM_Try, /*On fail goto*//*Label 1335*/ 63524, // Rule ID 4036 //
24712        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm,
24713        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
24714        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24715        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24716        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24717        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24718        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24719        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24720        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24721        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
24722        // MIs[1] Operand 1
24723        // No operand predicates
24724        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24725        GIM_CheckIsSafeToFold, /*InsnID*/1,
24726        // (intrinsic_wo_chain:{ *:[v16i8] } 2524:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] })  =>  (MVE_VRSHR_immu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)
24727        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24728        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24729        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24730        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_immu8,
24731        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24733        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24734        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24735        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24736        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24737        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24738        GIR_EraseFromParent, /*InsnID*/0,
24739        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24740        // GIR_Coverage, 4036,
24741        GIR_Done,
24742      // Label 1335: @63524
24743      GIM_Try, /*On fail goto*//*Label 1336*/ 63614, // Rule ID 4038 //
24744        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm,
24745        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24746        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24747        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24748        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24749        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24750        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24751        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24752        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24753        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
24754        // MIs[1] Operand 1
24755        // No operand predicates
24756        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24757        GIM_CheckIsSafeToFold, /*InsnID*/1,
24758        // (intrinsic_wo_chain:{ *:[v8i16] } 2524:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] })  =>  (MVE_VRSHR_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)
24759        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24760        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24761        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24762        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_imms16,
24763        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24764        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24765        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24766        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24767        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24768        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24769        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24770        GIR_EraseFromParent, /*InsnID*/0,
24771        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24772        // GIR_Coverage, 4038,
24773        GIR_Done,
24774      // Label 1336: @63614
24775      GIM_Try, /*On fail goto*//*Label 1337*/ 63704, // Rule ID 4040 //
24776        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm,
24777        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24778        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24779        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24780        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24781        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24782        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24783        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24784        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24785        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
24786        // MIs[1] Operand 1
24787        // No operand predicates
24788        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24789        GIM_CheckIsSafeToFold, /*InsnID*/1,
24790        // (intrinsic_wo_chain:{ *:[v8i16] } 2524:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] })  =>  (MVE_VRSHR_immu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)
24791        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24792        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24793        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24794        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_immu16,
24795        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24796        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24797        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24798        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24799        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24800        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24801        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24802        GIR_EraseFromParent, /*InsnID*/0,
24803        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24804        // GIR_Coverage, 4040,
24805        GIR_Done,
24806      // Label 1337: @63704
24807      GIM_Try, /*On fail goto*//*Label 1338*/ 63794, // Rule ID 4042 //
24808        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm,
24809        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24810        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24811        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24812        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24813        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24814        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24815        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24816        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24817        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm32,
24818        // MIs[1] Operand 1
24819        // No operand predicates
24820        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24821        GIM_CheckIsSafeToFold, /*InsnID*/1,
24822        // (intrinsic_wo_chain:{ *:[v4i32] } 2524:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 0:{ *:[i32] })  =>  (MVE_VRSHR_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)
24823        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24824        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24825        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24826        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_imms32,
24827        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24828        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24829        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24830        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24831        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24832        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24833        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24834        GIR_EraseFromParent, /*InsnID*/0,
24835        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24836        // GIR_Coverage, 4042,
24837        GIR_Done,
24838      // Label 1338: @63794
24839      GIM_Try, /*On fail goto*//*Label 1339*/ 63884, // Rule ID 4044 //
24840        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm,
24841        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24842        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24843        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24844        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24845        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24846        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24847        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24848        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24849        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm32,
24850        // MIs[1] Operand 1
24851        // No operand predicates
24852        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24853        GIM_CheckIsSafeToFold, /*InsnID*/1,
24854        // (intrinsic_wo_chain:{ *:[v4i32] } 2524:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 1:{ *:[i32] })  =>  (MVE_VRSHR_immu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)
24855        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24856        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24857        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24858        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_immu32,
24859        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24860        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24861        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24862        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24863        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24864        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24865        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24866        GIR_EraseFromParent, /*InsnID*/0,
24867        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24868        // GIR_Coverage, 4044,
24869        GIR_Done,
24870      // Label 1339: @63884
24871      GIM_Try, /*On fail goto*//*Label 1340*/ 63973, // Rule ID 4140 //
24872        GIM_CheckFeatures, GIFBS_HasMVEFloat,
24873        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_fix,
24874        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24875        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24876        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24877        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24878        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24879        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
24880        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24881        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
24882        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24883        // MIs[1] Operand 1
24884        // No operand predicates
24885        GIM_CheckIsSafeToFold, /*InsnID*/1,
24886        // (intrinsic_wo_chain:{ *:[v8f16] } 2443:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale)  =>  (MVE_VCVTf16s16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale)
24887        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24888        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24889        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24890        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16s16_fix,
24891        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24892        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
24893        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
24894        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24895        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24896        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24897        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24898        GIR_EraseFromParent, /*InsnID*/0,
24899        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24900        // GIR_Coverage, 4140,
24901        GIR_Done,
24902      // Label 1340: @63973
24903      GIM_Try, /*On fail goto*//*Label 1341*/ 64062, // Rule ID 4142 //
24904        GIM_CheckFeatures, GIFBS_HasMVEFloat,
24905        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_fix,
24906        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24907        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24908        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24909        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24910        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24911        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
24912        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24913        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
24914        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24915        // MIs[1] Operand 1
24916        // No operand predicates
24917        GIM_CheckIsSafeToFold, /*InsnID*/1,
24918        // (intrinsic_wo_chain:{ *:[v8i16] } 2443:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale)  =>  (MVE_VCVTs16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale)
24919        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24920        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24921        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24922        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs16f16_fix,
24923        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24924        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
24925        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
24926        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24927        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24928        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24929        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24930        GIR_EraseFromParent, /*InsnID*/0,
24931        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24932        // GIR_Coverage, 4142,
24933        GIR_Done,
24934      // Label 1341: @64062
24935      GIM_Try, /*On fail goto*//*Label 1342*/ 64151, // Rule ID 4144 //
24936        GIM_CheckFeatures, GIFBS_HasMVEFloat,
24937        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_fix,
24938        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24939        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24940        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24941        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24942        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24943        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
24944        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24945        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
24946        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24947        // MIs[1] Operand 1
24948        // No operand predicates
24949        GIM_CheckIsSafeToFold, /*InsnID*/1,
24950        // (intrinsic_wo_chain:{ *:[v8f16] } 2443:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale)  =>  (MVE_VCVTf16u16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale)
24951        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24952        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24953        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24954        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16u16_fix,
24955        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24956        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
24957        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
24958        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24959        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24960        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24961        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24962        GIR_EraseFromParent, /*InsnID*/0,
24963        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24964        // GIR_Coverage, 4144,
24965        GIR_Done,
24966      // Label 1342: @64151
24967      GIM_Try, /*On fail goto*//*Label 1343*/ 64240, // Rule ID 4146 //
24968        GIM_CheckFeatures, GIFBS_HasMVEFloat,
24969        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_fix,
24970        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24971        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24972        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24973        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24974        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24975        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
24976        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24977        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
24978        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24979        // MIs[1] Operand 1
24980        // No operand predicates
24981        GIM_CheckIsSafeToFold, /*InsnID*/1,
24982        // (intrinsic_wo_chain:{ *:[v8i16] } 2443:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale)  =>  (MVE_VCVTu16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale)
24983        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24984        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24985        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24986        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu16f16_fix,
24987        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24988        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
24989        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
24990        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24991        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24992        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24993        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24994        GIR_EraseFromParent, /*InsnID*/0,
24995        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24996        // GIR_Coverage, 4146,
24997        GIR_Done,
24998      // Label 1343: @64240
24999      GIM_Try, /*On fail goto*//*Label 1344*/ 64329, // Rule ID 4148 //
25000        GIM_CheckFeatures, GIFBS_HasMVEFloat,
25001        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_fix,
25002        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25003        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25004        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25005        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25006        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25007        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
25008        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25009        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25010        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
25011        // MIs[1] Operand 1
25012        // No operand predicates
25013        GIM_CheckIsSafeToFold, /*InsnID*/1,
25014        // (intrinsic_wo_chain:{ *:[v4f32] } 2443:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale)  =>  (MVE_VCVTf32s32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale)
25015        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25016        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25017        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25018        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf32s32_fix,
25019        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25020        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
25021        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25022        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25023        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25024        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25025        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25026        GIR_EraseFromParent, /*InsnID*/0,
25027        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25028        // GIR_Coverage, 4148,
25029        GIR_Done,
25030      // Label 1344: @64329
25031      GIM_Try, /*On fail goto*//*Label 1345*/ 64418, // Rule ID 4150 //
25032        GIM_CheckFeatures, GIFBS_HasMVEFloat,
25033        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_fix,
25034        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25035        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25036        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25037        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25038        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25039        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
25040        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25041        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25042        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
25043        // MIs[1] Operand 1
25044        // No operand predicates
25045        GIM_CheckIsSafeToFold, /*InsnID*/1,
25046        // (intrinsic_wo_chain:{ *:[v4i32] } 2443:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale)  =>  (MVE_VCVTs32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale)
25047        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25048        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25049        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25050        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs32f32_fix,
25051        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25052        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
25053        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25054        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25055        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25056        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25057        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25058        GIR_EraseFromParent, /*InsnID*/0,
25059        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25060        // GIR_Coverage, 4150,
25061        GIR_Done,
25062      // Label 1345: @64418
25063      GIM_Try, /*On fail goto*//*Label 1346*/ 64507, // Rule ID 4152 //
25064        GIM_CheckFeatures, GIFBS_HasMVEFloat,
25065        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_fix,
25066        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25067        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25068        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25069        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25070        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25071        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
25072        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25073        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25074        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
25075        // MIs[1] Operand 1
25076        // No operand predicates
25077        GIM_CheckIsSafeToFold, /*InsnID*/1,
25078        // (intrinsic_wo_chain:{ *:[v4f32] } 2443:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale)  =>  (MVE_VCVTf32u32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale)
25079        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25080        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25081        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25082        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf32u32_fix,
25083        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25084        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
25085        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25086        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25087        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25088        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25089        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25090        GIR_EraseFromParent, /*InsnID*/0,
25091        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25092        // GIR_Coverage, 4152,
25093        GIR_Done,
25094      // Label 1346: @64507
25095      GIM_Try, /*On fail goto*//*Label 1347*/ 64596, // Rule ID 4154 //
25096        GIM_CheckFeatures, GIFBS_HasMVEFloat,
25097        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_fix,
25098        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25099        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25100        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25101        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25102        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25103        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
25104        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25105        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25106        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
25107        // MIs[1] Operand 1
25108        // No operand predicates
25109        GIM_CheckIsSafeToFold, /*InsnID*/1,
25110        // (intrinsic_wo_chain:{ *:[v4i32] } 2443:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale)  =>  (MVE_VCVTu32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale)
25111        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25112        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25113        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25114        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu32f32_fix,
25115        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25116        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
25117        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25118        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25119        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25120        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25121        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25122        GIR_EraseFromParent, /*InsnID*/0,
25123        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25124        // GIR_Coverage, 4154,
25125        GIR_Done,
25126      // Label 1347: @64596
25127      GIM_Try, /*On fail goto*//*Label 1348*/ 64667, // Rule ID 3215 //
25128        GIM_CheckFeatures, GIFBS_HasMVEInt,
25129        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv,
25130        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25131        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25132        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25133        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25134        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25135        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
25136        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25137        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25138        // (intrinsic_wo_chain:{ *:[i32] } 2390:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] })  =>  (MVE_VMINVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
25139        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVs8,
25140        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
25141        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25142        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25143        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25144        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25145        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25146        GIR_EraseFromParent, /*InsnID*/0,
25147        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25148        // GIR_Coverage, 3215,
25149        GIR_Done,
25150      // Label 1348: @64667
25151      GIM_Try, /*On fail goto*//*Label 1349*/ 64738, // Rule ID 3217 //
25152        GIM_CheckFeatures, GIFBS_HasMVEInt,
25153        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv,
25154        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25155        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25156        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25157        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25158        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25159        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
25160        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25161        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25162        // (intrinsic_wo_chain:{ *:[i32] } 2390:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] })  =>  (MVE_VMINVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
25163        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVs16,
25164        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
25165        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25166        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25167        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25168        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25169        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25170        GIR_EraseFromParent, /*InsnID*/0,
25171        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25172        // GIR_Coverage, 3217,
25173        GIR_Done,
25174      // Label 1349: @64738
25175      GIM_Try, /*On fail goto*//*Label 1350*/ 64809, // Rule ID 3219 //
25176        GIM_CheckFeatures, GIFBS_HasMVEInt,
25177        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv,
25178        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25179        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25180        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25181        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25182        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25183        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
25184        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25185        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25186        // (intrinsic_wo_chain:{ *:[i32] } 2390:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] })  =>  (MVE_VMINVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
25187        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVs32,
25188        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
25189        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25190        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25191        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25192        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25193        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25194        GIR_EraseFromParent, /*InsnID*/0,
25195        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25196        // GIR_Coverage, 3219,
25197        GIR_Done,
25198      // Label 1350: @64809
25199      GIM_Try, /*On fail goto*//*Label 1351*/ 64880, // Rule ID 3221 //
25200        GIM_CheckFeatures, GIFBS_HasMVEInt,
25201        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv,
25202        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25203        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25204        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25205        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25206        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25207        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
25208        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25209        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25210        // (intrinsic_wo_chain:{ *:[i32] } 2390:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] })  =>  (MVE_VMINVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
25211        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVu8,
25212        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
25213        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25214        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25215        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25216        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25217        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25218        GIR_EraseFromParent, /*InsnID*/0,
25219        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25220        // GIR_Coverage, 3221,
25221        GIR_Done,
25222      // Label 1351: @64880
25223      GIM_Try, /*On fail goto*//*Label 1352*/ 64951, // Rule ID 3223 //
25224        GIM_CheckFeatures, GIFBS_HasMVEInt,
25225        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv,
25226        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25227        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25228        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25229        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25230        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25231        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
25232        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25233        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25234        // (intrinsic_wo_chain:{ *:[i32] } 2390:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] })  =>  (MVE_VMINVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
25235        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVu16,
25236        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
25237        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25238        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25239        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25240        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25241        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25242        GIR_EraseFromParent, /*InsnID*/0,
25243        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25244        // GIR_Coverage, 3223,
25245        GIR_Done,
25246      // Label 1352: @64951
25247      GIM_Try, /*On fail goto*//*Label 1353*/ 65022, // Rule ID 3225 //
25248        GIM_CheckFeatures, GIFBS_HasMVEInt,
25249        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv,
25250        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25251        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25252        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25253        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25254        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25255        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
25256        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25257        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25258        // (intrinsic_wo_chain:{ *:[i32] } 2390:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] })  =>  (MVE_VMINVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
25259        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVu32,
25260        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
25261        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25262        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25263        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25264        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25265        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25266        GIR_EraseFromParent, /*InsnID*/0,
25267        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25268        // GIR_Coverage, 3225,
25269        GIR_Done,
25270      // Label 1353: @65022
25271      GIM_Try, /*On fail goto*//*Label 1354*/ 65093, // Rule ID 3227 //
25272        GIM_CheckFeatures, GIFBS_HasMVEInt,
25273        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv,
25274        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25275        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25276        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25277        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25278        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25279        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
25280        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25281        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25282        // (intrinsic_wo_chain:{ *:[i32] } 2381:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] })  =>  (MVE_VMAXVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
25283        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVs8,
25284        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
25285        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25286        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25287        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25288        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25289        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25290        GIR_EraseFromParent, /*InsnID*/0,
25291        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25292        // GIR_Coverage, 3227,
25293        GIR_Done,
25294      // Label 1354: @65093
25295      GIM_Try, /*On fail goto*//*Label 1355*/ 65164, // Rule ID 3229 //
25296        GIM_CheckFeatures, GIFBS_HasMVEInt,
25297        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv,
25298        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25299        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25300        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25301        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25302        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25303        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
25304        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25305        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25306        // (intrinsic_wo_chain:{ *:[i32] } 2381:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] })  =>  (MVE_VMAXVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
25307        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVs16,
25308        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
25309        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25310        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25311        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25312        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25313        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25314        GIR_EraseFromParent, /*InsnID*/0,
25315        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25316        // GIR_Coverage, 3229,
25317        GIR_Done,
25318      // Label 1355: @65164
25319      GIM_Try, /*On fail goto*//*Label 1356*/ 65235, // Rule ID 3231 //
25320        GIM_CheckFeatures, GIFBS_HasMVEInt,
25321        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv,
25322        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25323        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25324        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25325        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25326        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25327        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
25328        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25329        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25330        // (intrinsic_wo_chain:{ *:[i32] } 2381:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] })  =>  (MVE_VMAXVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
25331        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVs32,
25332        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
25333        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25334        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25335        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25336        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25337        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25338        GIR_EraseFromParent, /*InsnID*/0,
25339        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25340        // GIR_Coverage, 3231,
25341        GIR_Done,
25342      // Label 1356: @65235
25343      GIM_Try, /*On fail goto*//*Label 1357*/ 65306, // Rule ID 3233 //
25344        GIM_CheckFeatures, GIFBS_HasMVEInt,
25345        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv,
25346        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25347        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25348        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25349        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25350        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25351        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
25352        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25353        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25354        // (intrinsic_wo_chain:{ *:[i32] } 2381:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] })  =>  (MVE_VMAXVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
25355        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVu8,
25356        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
25357        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25358        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25359        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25360        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25361        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25362        GIR_EraseFromParent, /*InsnID*/0,
25363        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25364        // GIR_Coverage, 3233,
25365        GIR_Done,
25366      // Label 1357: @65306
25367      GIM_Try, /*On fail goto*//*Label 1358*/ 65377, // Rule ID 3235 //
25368        GIM_CheckFeatures, GIFBS_HasMVEInt,
25369        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv,
25370        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25371        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25372        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25373        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25374        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25375        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
25376        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25377        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25378        // (intrinsic_wo_chain:{ *:[i32] } 2381:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] })  =>  (MVE_VMAXVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
25379        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVu16,
25380        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
25381        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25382        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25383        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25384        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25385        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25386        GIR_EraseFromParent, /*InsnID*/0,
25387        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25388        // GIR_Coverage, 3235,
25389        GIR_Done,
25390      // Label 1358: @65377
25391      GIM_Try, /*On fail goto*//*Label 1359*/ 65448, // Rule ID 3237 //
25392        GIM_CheckFeatures, GIFBS_HasMVEInt,
25393        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv,
25394        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
25395        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
25396        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25397        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25398        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25399        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
25400        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25401        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25402        // (intrinsic_wo_chain:{ *:[i32] } 2381:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] })  =>  (MVE_VMAXVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
25403        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVu32,
25404        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
25405        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
25406        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
25407        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25408        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25409        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25410        GIR_EraseFromParent, /*InsnID*/0,
25411        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25412        // GIR_Coverage, 3237,
25413        GIR_Done,
25414      // Label 1359: @65448
25415      GIM_Try, /*On fail goto*//*Label 1360*/ 65533, // Rule ID 3642 //
25416        GIM_CheckFeatures, GIFBS_HasMVEInt,
25417        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
25418        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25419        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25420        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25421        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25422        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25423        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25424        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25425        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25426        // (intrinsic_wo_chain:{ *:[v16i8] } 2427:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VABDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25427        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25428        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25429        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25430        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDs8,
25431        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25432        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25433        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25434        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25435        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25436        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25437        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25438        GIR_EraseFromParent, /*InsnID*/0,
25439        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25440        // GIR_Coverage, 3642,
25441        GIR_Done,
25442      // Label 1360: @65533
25443      GIM_Try, /*On fail goto*//*Label 1361*/ 65618, // Rule ID 3649 //
25444        GIM_CheckFeatures, GIFBS_HasMVEInt,
25445        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
25446        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25447        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25448        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25449        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25450        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25451        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25452        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25453        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25454        // (intrinsic_wo_chain:{ *:[v8i16] } 2427:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VABDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25455        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25456        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25457        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25458        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDs16,
25459        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25460        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25461        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25462        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25463        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25464        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25465        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25466        GIR_EraseFromParent, /*InsnID*/0,
25467        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25468        // GIR_Coverage, 3649,
25469        GIR_Done,
25470      // Label 1361: @65618
25471      GIM_Try, /*On fail goto*//*Label 1362*/ 65703, // Rule ID 3653 //
25472        GIM_CheckFeatures, GIFBS_HasMVEInt,
25473        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
25474        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25475        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25476        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25477        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25478        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25479        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25480        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25481        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25482        // (intrinsic_wo_chain:{ *:[v4i32] } 2427:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VABDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25483        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25484        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25485        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25486        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDs32,
25487        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25488        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25489        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25490        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25491        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25492        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25493        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25494        GIR_EraseFromParent, /*InsnID*/0,
25495        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25496        // GIR_Coverage, 3653,
25497        GIR_Done,
25498      // Label 1362: @65703
25499      GIM_Try, /*On fail goto*//*Label 1363*/ 65788, // Rule ID 3657 //
25500        GIM_CheckFeatures, GIFBS_HasMVEInt,
25501        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
25502        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25503        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25504        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25505        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25506        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25507        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25508        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25509        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25510        // (intrinsic_wo_chain:{ *:[v16i8] } 2427:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VABDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25511        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25512        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25513        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25514        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDu8,
25515        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25516        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25517        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25518        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25519        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25520        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25521        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25522        GIR_EraseFromParent, /*InsnID*/0,
25523        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25524        // GIR_Coverage, 3657,
25525        GIR_Done,
25526      // Label 1363: @65788
25527      GIM_Try, /*On fail goto*//*Label 1364*/ 65873, // Rule ID 3661 //
25528        GIM_CheckFeatures, GIFBS_HasMVEInt,
25529        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
25530        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25531        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25532        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25533        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25534        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25535        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25536        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25537        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25538        // (intrinsic_wo_chain:{ *:[v8i16] } 2427:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VABDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25539        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25540        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25541        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25542        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDu16,
25543        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25544        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25545        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25546        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25547        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25548        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25549        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25550        GIR_EraseFromParent, /*InsnID*/0,
25551        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25552        // GIR_Coverage, 3661,
25553        GIR_Done,
25554      // Label 1364: @65873
25555      GIM_Try, /*On fail goto*//*Label 1365*/ 65958, // Rule ID 3665 //
25556        GIM_CheckFeatures, GIFBS_HasMVEInt,
25557        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
25558        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25559        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25560        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25561        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25562        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25563        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25564        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25565        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25566        // (intrinsic_wo_chain:{ *:[v4i32] } 2427:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VABDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25567        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25568        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25569        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25570        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDu32,
25571        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25572        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25573        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25574        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25575        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25576        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25577        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25578        GIR_EraseFromParent, /*InsnID*/0,
25579        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25580        // GIR_Coverage, 3665,
25581        GIR_Done,
25582      // Label 1365: @65958
25583      GIM_Try, /*On fail goto*//*Label 1366*/ 66043, // Rule ID 3666 //
25584        GIM_CheckFeatures, GIFBS_HasMVEInt,
25585        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd,
25586        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25587        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25588        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25589        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25590        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25591        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25592        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25593        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25594        // (intrinsic_wo_chain:{ *:[v16i8] } 2513:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VRHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25595        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25596        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25597        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25598        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDs8,
25599        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25600        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25601        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25602        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25603        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25604        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25605        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25606        GIR_EraseFromParent, /*InsnID*/0,
25607        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25608        // GIR_Coverage, 3666,
25609        GIR_Done,
25610      // Label 1366: @66043
25611      GIM_Try, /*On fail goto*//*Label 1367*/ 66128, // Rule ID 3673 //
25612        GIM_CheckFeatures, GIFBS_HasMVEInt,
25613        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd,
25614        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25615        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25616        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25617        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25618        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25619        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25620        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25621        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25622        // (intrinsic_wo_chain:{ *:[v8i16] } 2513:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VRHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25623        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25624        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25625        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25626        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDs16,
25627        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25628        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25629        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25630        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25631        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25632        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25633        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25634        GIR_EraseFromParent, /*InsnID*/0,
25635        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25636        // GIR_Coverage, 3673,
25637        GIR_Done,
25638      // Label 1367: @66128
25639      GIM_Try, /*On fail goto*//*Label 1368*/ 66213, // Rule ID 3677 //
25640        GIM_CheckFeatures, GIFBS_HasMVEInt,
25641        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd,
25642        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25643        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25644        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25645        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25646        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25647        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25648        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25649        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25650        // (intrinsic_wo_chain:{ *:[v4i32] } 2513:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VRHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25651        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25652        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25653        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25654        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDs32,
25655        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25656        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25657        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25658        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25659        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25660        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25661        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25662        GIR_EraseFromParent, /*InsnID*/0,
25663        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25664        // GIR_Coverage, 3677,
25665        GIR_Done,
25666      // Label 1368: @66213
25667      GIM_Try, /*On fail goto*//*Label 1369*/ 66298, // Rule ID 3681 //
25668        GIM_CheckFeatures, GIFBS_HasMVEInt,
25669        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd,
25670        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25671        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25672        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25673        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25674        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25675        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25676        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25677        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25678        // (intrinsic_wo_chain:{ *:[v16i8] } 2513:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VRHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25679        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25680        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25681        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25682        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDu8,
25683        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25684        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25685        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25686        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25687        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25688        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25689        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25690        GIR_EraseFromParent, /*InsnID*/0,
25691        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25692        // GIR_Coverage, 3681,
25693        GIR_Done,
25694      // Label 1369: @66298
25695      GIM_Try, /*On fail goto*//*Label 1370*/ 66383, // Rule ID 3685 //
25696        GIM_CheckFeatures, GIFBS_HasMVEInt,
25697        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd,
25698        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25699        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25700        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25701        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25702        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25703        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25704        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25705        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25706        // (intrinsic_wo_chain:{ *:[v8i16] } 2513:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VRHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25707        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25708        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25709        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25710        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDu16,
25711        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25712        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25713        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25714        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25715        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25716        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25717        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25718        GIR_EraseFromParent, /*InsnID*/0,
25719        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25720        // GIR_Coverage, 3685,
25721        GIR_Done,
25722      // Label 1370: @66383
25723      GIM_Try, /*On fail goto*//*Label 1371*/ 66468, // Rule ID 3689 //
25724        GIM_CheckFeatures, GIFBS_HasMVEInt,
25725        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd,
25726        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25727        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25728        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25729        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25730        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25731        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25732        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25733        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25734        // (intrinsic_wo_chain:{ *:[v4i32] } 2513:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VRHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25735        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25736        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25737        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25738        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDu32,
25739        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25740        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25741        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25742        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25743        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25744        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25745        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25746        GIR_EraseFromParent, /*InsnID*/0,
25747        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25748        // GIR_Coverage, 3689,
25749        GIR_Done,
25750      // Label 1371: @66468
25751      GIM_Try, /*On fail goto*//*Label 1372*/ 66553, // Rule ID 3702 //
25752        GIM_CheckFeatures, GIFBS_HasMVEInt,
25753        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd,
25754        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25755        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25756        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25757        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25758        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25759        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25760        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25761        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25762        // (intrinsic_wo_chain:{ *:[v16i8] } 2462:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25763        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25764        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25765        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25766        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDs8,
25767        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25768        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25769        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25770        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25771        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25772        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25773        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25774        GIR_EraseFromParent, /*InsnID*/0,
25775        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25776        // GIR_Coverage, 3702,
25777        GIR_Done,
25778      // Label 1372: @66553
25779      GIM_Try, /*On fail goto*//*Label 1373*/ 66638, // Rule ID 3710 //
25780        GIM_CheckFeatures, GIFBS_HasMVEInt,
25781        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd,
25782        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25783        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25784        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25785        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25786        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25787        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25788        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25789        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25790        // (intrinsic_wo_chain:{ *:[v8i16] } 2462:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25791        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25792        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25793        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25794        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDs16,
25795        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25796        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25797        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25798        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25799        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25800        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25801        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25802        GIR_EraseFromParent, /*InsnID*/0,
25803        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25804        // GIR_Coverage, 3710,
25805        GIR_Done,
25806      // Label 1373: @66638
25807      GIM_Try, /*On fail goto*//*Label 1374*/ 66723, // Rule ID 3715 //
25808        GIM_CheckFeatures, GIFBS_HasMVEInt,
25809        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd,
25810        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25811        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25812        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25813        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25814        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25815        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25816        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25817        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25818        // (intrinsic_wo_chain:{ *:[v4i32] } 2462:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25819        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25820        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25821        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25822        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDs32,
25823        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25824        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25825        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25826        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25827        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25828        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25829        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25830        GIR_EraseFromParent, /*InsnID*/0,
25831        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25832        // GIR_Coverage, 3715,
25833        GIR_Done,
25834      // Label 1374: @66723
25835      GIM_Try, /*On fail goto*//*Label 1375*/ 66808, // Rule ID 3720 //
25836        GIM_CheckFeatures, GIFBS_HasMVEInt,
25837        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd,
25838        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25839        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25840        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25841        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25842        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25843        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25844        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25845        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25846        // (intrinsic_wo_chain:{ *:[v16i8] } 2462:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25847        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25848        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25849        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25850        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDu8,
25851        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25852        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25853        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25854        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25855        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25856        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25857        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25858        GIR_EraseFromParent, /*InsnID*/0,
25859        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25860        // GIR_Coverage, 3720,
25861        GIR_Done,
25862      // Label 1375: @66808
25863      GIM_Try, /*On fail goto*//*Label 1376*/ 66893, // Rule ID 3725 //
25864        GIM_CheckFeatures, GIFBS_HasMVEInt,
25865        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd,
25866        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25867        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25868        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25869        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25870        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25871        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25872        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25873        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25874        // (intrinsic_wo_chain:{ *:[v8i16] } 2462:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25875        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25876        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25877        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25878        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDu16,
25879        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25880        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25881        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25882        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25883        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25884        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25885        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25886        GIR_EraseFromParent, /*InsnID*/0,
25887        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25888        // GIR_Coverage, 3725,
25889        GIR_Done,
25890      // Label 1376: @66893
25891      GIM_Try, /*On fail goto*//*Label 1377*/ 66978, // Rule ID 3730 //
25892        GIM_CheckFeatures, GIFBS_HasMVEInt,
25893        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd,
25894        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25895        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25896        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25897        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25898        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25899        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25900        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25901        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25902        // (intrinsic_wo_chain:{ *:[v4i32] } 2462:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25903        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25904        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25905        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25906        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDu32,
25907        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25908        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25909        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25910        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25911        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25912        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25913        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25914        GIR_EraseFromParent, /*InsnID*/0,
25915        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25916        // GIR_Coverage, 3730,
25917        GIR_Done,
25918      // Label 1377: @66978
25919      GIM_Try, /*On fail goto*//*Label 1378*/ 67063, // Rule ID 3732 //
25920        GIM_CheckFeatures, GIFBS_HasMVEInt,
25921        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub,
25922        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25923        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25924        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25925        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25926        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25927        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25928        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25929        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25930        // (intrinsic_wo_chain:{ *:[v16i8] } 2463:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VHSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25931        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25932        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25933        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25934        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBs8,
25935        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25936        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25937        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25938        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25939        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25940        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25941        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25942        GIR_EraseFromParent, /*InsnID*/0,
25943        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25944        // GIR_Coverage, 3732,
25945        GIR_Done,
25946      // Label 1378: @67063
25947      GIM_Try, /*On fail goto*//*Label 1379*/ 67148, // Rule ID 3735 //
25948        GIM_CheckFeatures, GIFBS_HasMVEInt,
25949        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub,
25950        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25951        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25952        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25953        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25954        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25955        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25956        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25957        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25958        // (intrinsic_wo_chain:{ *:[v8i16] } 2463:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VHSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25959        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25960        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25961        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25962        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBs16,
25963        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25964        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25965        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25966        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25967        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25968        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25969        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25970        GIR_EraseFromParent, /*InsnID*/0,
25971        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25972        // GIR_Coverage, 3735,
25973        GIR_Done,
25974      // Label 1379: @67148
25975      GIM_Try, /*On fail goto*//*Label 1380*/ 67233, // Rule ID 3738 //
25976        GIM_CheckFeatures, GIFBS_HasMVEInt,
25977        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub,
25978        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25979        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25980        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25981        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25982        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25983        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25984        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25985        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25986        // (intrinsic_wo_chain:{ *:[v4i32] } 2463:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VHSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25987        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25988        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25989        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25990        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBs32,
25991        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25992        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25993        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25994        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25995        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25996        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25997        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25998        GIR_EraseFromParent, /*InsnID*/0,
25999        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26000        // GIR_Coverage, 3738,
26001        GIR_Done,
26002      // Label 1380: @67233
26003      GIM_Try, /*On fail goto*//*Label 1381*/ 67318, // Rule ID 3741 //
26004        GIM_CheckFeatures, GIFBS_HasMVEInt,
26005        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub,
26006        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26007        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26008        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26009        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26010        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26011        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26012        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26013        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26014        // (intrinsic_wo_chain:{ *:[v16i8] } 2463:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VHSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26015        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26016        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26017        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26018        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBu8,
26019        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26020        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26021        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26022        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26023        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26024        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26025        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26026        GIR_EraseFromParent, /*InsnID*/0,
26027        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26028        // GIR_Coverage, 3741,
26029        GIR_Done,
26030      // Label 1381: @67318
26031      GIM_Try, /*On fail goto*//*Label 1382*/ 67403, // Rule ID 3744 //
26032        GIM_CheckFeatures, GIFBS_HasMVEInt,
26033        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub,
26034        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26035        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26036        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26037        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26038        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26039        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26040        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26041        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26042        // (intrinsic_wo_chain:{ *:[v8i16] } 2463:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VHSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26043        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26044        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26045        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26046        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBu16,
26047        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26048        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26049        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26050        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26051        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26052        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26053        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26054        GIR_EraseFromParent, /*InsnID*/0,
26055        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26056        // GIR_Coverage, 3744,
26057        GIR_Done,
26058      // Label 1382: @67403
26059      GIM_Try, /*On fail goto*//*Label 1383*/ 67488, // Rule ID 3747 //
26060        GIM_CheckFeatures, GIFBS_HasMVEInt,
26061        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub,
26062        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26063        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26064        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26065        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26066        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26067        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26068        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26069        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26070        // (intrinsic_wo_chain:{ *:[v4i32] } 2463:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VHSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26071        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26072        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26073        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26074        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBu32,
26075        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26076        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26077        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26078        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26079        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26080        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26081        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26082        GIR_EraseFromParent, /*InsnID*/0,
26083        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26084        // GIR_Coverage, 3747,
26085        GIR_Done,
26086      // Label 1383: @67488
26087      GIM_Try, /*On fail goto*//*Label 1384*/ 67573, // Rule ID 4134 //
26088        GIM_CheckFeatures, GIFBS_HasMVEFloat,
26089        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
26090        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26091        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26092        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26093        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26094        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26095        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26096        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26097        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26098        // (intrinsic_wo_chain:{ *:[v4f32] } 2427:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
26099        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26100        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26101        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26102        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDf32,
26103        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26104        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26106        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26107        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26108        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26109        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26110        GIR_EraseFromParent, /*InsnID*/0,
26111        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26112        // GIR_Coverage, 4134,
26113        GIR_Done,
26114      // Label 1384: @67573
26115      GIM_Try, /*On fail goto*//*Label 1385*/ 67658, // Rule ID 4136 //
26116        GIM_CheckFeatures, GIFBS_HasMVEFloat,
26117        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
26118        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26119        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26120        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26121        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26122        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26123        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26124        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26125        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26126        // (intrinsic_wo_chain:{ *:[v8f16] } 2427:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
26127        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26128        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26129        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26130        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDf16,
26131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26132        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26133        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26134        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26135        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26136        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26137        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26138        GIR_EraseFromParent, /*InsnID*/0,
26139        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26140        // GIR_Coverage, 4136,
26141        GIR_Done,
26142      // Label 1385: @67658
26143      GIM_Try, /*On fail goto*//*Label 1386*/ 67743, // Rule ID 4509 //
26144        GIM_CheckFeatures, GIFBS_HasMVEInt,
26145        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull_poly,
26146        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26147        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26148        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26149        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26150        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26151        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26152        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26153        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26154        // (intrinsic_wo_chain:{ *:[v8i16] } 2490:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VMULLBp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26155        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26156        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26157        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26158        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBp8,
26159        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26160        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26161        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26162        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26163        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26164        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26165        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26166        GIR_EraseFromParent, /*InsnID*/0,
26167        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26168        // GIR_Coverage, 4509,
26169        GIR_Done,
26170      // Label 1386: @67743
26171      GIM_Try, /*On fail goto*//*Label 1387*/ 67828, // Rule ID 4511 //
26172        GIM_CheckFeatures, GIFBS_HasMVEInt,
26173        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull_poly,
26174        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26175        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26176        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26177        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26178        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26179        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26180        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26181        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26182        // (intrinsic_wo_chain:{ *:[v8i16] } 2490:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VMULLTp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26183        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26184        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26185        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26186        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTp8,
26187        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26188        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26189        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26190        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26191        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26192        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26193        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26194        GIR_EraseFromParent, /*InsnID*/0,
26195        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26196        // GIR_Coverage, 4511,
26197        GIR_Done,
26198      // Label 1387: @67828
26199      GIM_Try, /*On fail goto*//*Label 1388*/ 67913, // Rule ID 4513 //
26200        GIM_CheckFeatures, GIFBS_HasMVEInt,
26201        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull_poly,
26202        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26203        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26204        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26205        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26206        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26207        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26208        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26209        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26210        // (intrinsic_wo_chain:{ *:[v4i32] } 2490:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VMULLBp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26211        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26212        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26213        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26214        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBp16,
26215        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26216        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26217        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26218        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26219        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26220        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26221        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26222        GIR_EraseFromParent, /*InsnID*/0,
26223        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26224        // GIR_Coverage, 4513,
26225        GIR_Done,
26226      // Label 1388: @67913
26227      GIM_Try, /*On fail goto*//*Label 1389*/ 67998, // Rule ID 4515 //
26228        GIM_CheckFeatures, GIFBS_HasMVEInt,
26229        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull_poly,
26230        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26231        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26232        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26233        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26234        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26235        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26236        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26237        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26238        // (intrinsic_wo_chain:{ *:[v4i32] } 2490:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VMULLTp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26239        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26240        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26241        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26242        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTp16,
26243        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26244        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26245        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26246        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26247        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26248        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26249        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26250        GIR_EraseFromParent, /*InsnID*/0,
26251        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26252        // GIR_Coverage, 4515,
26253        GIR_Done,
26254      // Label 1389: @67998
26255      GIM_Try, /*On fail goto*//*Label 1390*/ 68083, // Rule ID 4542 //
26256        GIM_CheckFeatures, GIFBS_HasMVEInt,
26257        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh,
26258        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26259        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26260        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26261        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26262        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26263        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26264        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26265        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26266        // (intrinsic_wo_chain:{ *:[v16i8] } 2488:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26267        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26268        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26269        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26270        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHs8,
26271        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26272        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26273        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26274        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26275        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26276        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26277        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26278        GIR_EraseFromParent, /*InsnID*/0,
26279        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26280        // GIR_Coverage, 4542,
26281        GIR_Done,
26282      // Label 1390: @68083
26283      GIM_Try, /*On fail goto*//*Label 1391*/ 68168, // Rule ID 4549 //
26284        GIM_CheckFeatures, GIFBS_HasMVEInt,
26285        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh,
26286        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26287        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26288        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26289        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26290        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26291        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26292        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26293        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26294        // (intrinsic_wo_chain:{ *:[v8i16] } 2488:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26295        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26296        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26297        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26298        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHs16,
26299        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26300        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26301        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26302        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26303        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26304        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26305        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26306        GIR_EraseFromParent, /*InsnID*/0,
26307        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26308        // GIR_Coverage, 4549,
26309        GIR_Done,
26310      // Label 1391: @68168
26311      GIM_Try, /*On fail goto*//*Label 1392*/ 68253, // Rule ID 4553 //
26312        GIM_CheckFeatures, GIFBS_HasMVEInt,
26313        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh,
26314        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26315        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26316        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26317        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26318        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26319        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26320        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26321        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26322        // (intrinsic_wo_chain:{ *:[v4i32] } 2488:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26323        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26324        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26325        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26326        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHs32,
26327        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26328        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26329        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26330        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26331        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26332        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26333        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26334        GIR_EraseFromParent, /*InsnID*/0,
26335        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26336        // GIR_Coverage, 4553,
26337        GIR_Done,
26338      // Label 1392: @68253
26339      GIM_Try, /*On fail goto*//*Label 1393*/ 68338, // Rule ID 4557 //
26340        GIM_CheckFeatures, GIFBS_HasMVEInt,
26341        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh,
26342        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26343        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26344        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26345        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26346        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26347        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26348        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26349        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26350        // (intrinsic_wo_chain:{ *:[v16i8] } 2488:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26351        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26352        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26353        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26354        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHu8,
26355        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26356        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26357        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26358        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26359        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26360        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26361        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26362        GIR_EraseFromParent, /*InsnID*/0,
26363        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26364        // GIR_Coverage, 4557,
26365        GIR_Done,
26366      // Label 1393: @68338
26367      GIM_Try, /*On fail goto*//*Label 1394*/ 68423, // Rule ID 4561 //
26368        GIM_CheckFeatures, GIFBS_HasMVEInt,
26369        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh,
26370        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26371        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26372        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26373        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26374        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26375        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26376        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26377        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26378        // (intrinsic_wo_chain:{ *:[v8i16] } 2488:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26379        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26380        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26381        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26382        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHu16,
26383        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26384        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26385        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26386        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26387        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26388        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26389        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26390        GIR_EraseFromParent, /*InsnID*/0,
26391        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26392        // GIR_Coverage, 4561,
26393        GIR_Done,
26394      // Label 1394: @68423
26395      GIM_Try, /*On fail goto*//*Label 1395*/ 68508, // Rule ID 4565 //
26396        GIM_CheckFeatures, GIFBS_HasMVEInt,
26397        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh,
26398        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26399        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26400        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26401        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26402        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26403        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26404        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26405        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26406        // (intrinsic_wo_chain:{ *:[v4i32] } 2488:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26407        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26408        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26409        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26410        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHu32,
26411        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26412        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26413        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26414        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26415        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26416        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26417        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26418        GIR_EraseFromParent, /*InsnID*/0,
26419        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26420        // GIR_Coverage, 4565,
26421        GIR_Done,
26422      // Label 1395: @68508
26423      GIM_Try, /*On fail goto*//*Label 1396*/ 68593, // Rule ID 4566 //
26424        GIM_CheckFeatures, GIFBS_HasMVEInt,
26425        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh,
26426        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26427        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26428        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26429        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26430        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26431        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26432        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26433        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26434        // (intrinsic_wo_chain:{ *:[v16i8] } 2523:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VRMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26435        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26436        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26437        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26438        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHs8,
26439        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26440        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26441        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26442        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26443        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26444        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26445        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26446        GIR_EraseFromParent, /*InsnID*/0,
26447        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26448        // GIR_Coverage, 4566,
26449        GIR_Done,
26450      // Label 1396: @68593
26451      GIM_Try, /*On fail goto*//*Label 1397*/ 68678, // Rule ID 4568 //
26452        GIM_CheckFeatures, GIFBS_HasMVEInt,
26453        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh,
26454        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26455        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26456        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26457        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26458        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26459        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26460        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26461        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26462        // (intrinsic_wo_chain:{ *:[v8i16] } 2523:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VRMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26463        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26464        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26465        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26466        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHs16,
26467        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26468        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26469        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26470        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26471        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26472        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26473        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26474        GIR_EraseFromParent, /*InsnID*/0,
26475        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26476        // GIR_Coverage, 4568,
26477        GIR_Done,
26478      // Label 1397: @68678
26479      GIM_Try, /*On fail goto*//*Label 1398*/ 68763, // Rule ID 4570 //
26480        GIM_CheckFeatures, GIFBS_HasMVEInt,
26481        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh,
26482        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26483        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26484        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26485        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26486        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26487        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26488        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26489        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26490        // (intrinsic_wo_chain:{ *:[v4i32] } 2523:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VRMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26491        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26492        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26493        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26494        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHs32,
26495        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26496        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26497        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26498        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26499        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26500        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26501        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26502        GIR_EraseFromParent, /*InsnID*/0,
26503        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26504        // GIR_Coverage, 4570,
26505        GIR_Done,
26506      // Label 1398: @68763
26507      GIM_Try, /*On fail goto*//*Label 1399*/ 68848, // Rule ID 4572 //
26508        GIM_CheckFeatures, GIFBS_HasMVEInt,
26509        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh,
26510        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26511        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26512        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26513        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26514        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26515        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26516        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26517        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26518        // (intrinsic_wo_chain:{ *:[v16i8] } 2523:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VRMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26519        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26520        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26521        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26522        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHu8,
26523        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26524        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26525        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26526        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26527        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26528        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26529        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26530        GIR_EraseFromParent, /*InsnID*/0,
26531        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26532        // GIR_Coverage, 4572,
26533        GIR_Done,
26534      // Label 1399: @68848
26535      GIM_Try, /*On fail goto*//*Label 1400*/ 68933, // Rule ID 4574 //
26536        GIM_CheckFeatures, GIFBS_HasMVEInt,
26537        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh,
26538        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26539        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26540        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26541        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26542        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26543        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26544        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26545        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26546        // (intrinsic_wo_chain:{ *:[v8i16] } 2523:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VRMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26547        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26548        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26549        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26550        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHu16,
26551        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26552        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26553        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26554        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26555        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26556        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26557        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26558        GIR_EraseFromParent, /*InsnID*/0,
26559        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26560        // GIR_Coverage, 4574,
26561        GIR_Done,
26562      // Label 1400: @68933
26563      GIM_Try, /*On fail goto*//*Label 1401*/ 69018, // Rule ID 4576 //
26564        GIM_CheckFeatures, GIFBS_HasMVEInt,
26565        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh,
26566        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26567        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26568        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26569        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26570        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26571        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26572        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26573        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26574        // (intrinsic_wo_chain:{ *:[v4i32] } 2523:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VRMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26575        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26576        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26577        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26578        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHu32,
26579        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26580        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26581        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26582        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26583        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26584        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26585        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26586        GIR_EraseFromParent, /*InsnID*/0,
26587        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26588        // GIR_Coverage, 4576,
26589        GIR_Done,
26590      // Label 1401: @69018
26591      GIM_Try, /*On fail goto*//*Label 1402*/ 69089, // Rule ID 4627 //
26592        GIM_CheckFeatures, GIFBS_HasMVEFloat,
26593        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_narrow,
26594        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26595        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26596        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26597        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26598        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26599        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26600        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26601        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26602        // (intrinsic_wo_chain:{ *:[v8f16] } 2446:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 0:{ *:[i32] })  =>  (MVE_VCVTf16f32bh:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm)
26603        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16f32bh,
26604        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26605        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
26606        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
26607        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26608        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26609        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26610        GIR_EraseFromParent, /*InsnID*/0,
26611        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26612        // GIR_Coverage, 4627,
26613        GIR_Done,
26614      // Label 1402: @69089
26615      GIM_Try, /*On fail goto*//*Label 1403*/ 69160, // Rule ID 4633 //
26616        GIM_CheckFeatures, GIFBS_HasMVEFloat,
26617        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_narrow,
26618        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26619        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26620        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26621        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26622        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26623        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26624        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26625        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26626        // (intrinsic_wo_chain:{ *:[v8f16] } 2446:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 1:{ *:[i32] })  =>  (MVE_VCVTf16f32th:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm)
26627        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16f32th,
26628        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26629        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
26630        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
26631        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26632        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26633        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26634        GIR_EraseFromParent, /*InsnID*/0,
26635        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26636        // GIR_Coverage, 4633,
26637        GIR_Done,
26638      // Label 1403: @69160
26639      GIM_Try, /*On fail goto*//*Label 1404*/ 69245, // Rule ID 4651 //
26640        GIM_CheckFeatures, GIFBS_HasMVEInt,
26641        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmull,
26642        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26643        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26644        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26645        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26646        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26647        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26648        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26649        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26650        // (intrinsic_wo_chain:{ *:[v4i32] } 2498:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VQDMULLs16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26651        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26652        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26653        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26654        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMULLs16bh,
26655        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26656        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26657        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26658        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26659        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26660        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26661        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26662        GIR_EraseFromParent, /*InsnID*/0,
26663        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26664        // GIR_Coverage, 4651,
26665        GIR_Done,
26666      // Label 1404: @69245
26667      GIM_Try, /*On fail goto*//*Label 1405*/ 69330, // Rule ID 4653 //
26668        GIM_CheckFeatures, GIFBS_HasMVEInt,
26669        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmull,
26670        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26671        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26672        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26673        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26674        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26675        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26676        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26677        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26678        // (intrinsic_wo_chain:{ *:[v4i32] } 2498:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VQDMULLs16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26679        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26680        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26681        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26682        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMULLs16th,
26683        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26684        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26685        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26686        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26687        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26688        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26689        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26690        GIR_EraseFromParent, /*InsnID*/0,
26691        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26692        // GIR_Coverage, 4653,
26693        GIR_Done,
26694      // Label 1405: @69330
26695      GIM_Try, /*On fail goto*//*Label 1406*/ 69415, // Rule ID 4655 //
26696        GIM_CheckFeatures, GIFBS_HasMVEInt,
26697        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmull,
26698        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
26699        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26700        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26701        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26702        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26703        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26704        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26705        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
26706        // (intrinsic_wo_chain:{ *:[v2i64] } 2498:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] })  =>  (MVE_VQDMULLs32bh:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26707        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26708        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26709        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26710        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMULLs32bh,
26711        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26712        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26713        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26714        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26715        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26716        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26717        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26718        GIR_EraseFromParent, /*InsnID*/0,
26719        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26720        // GIR_Coverage, 4655,
26721        GIR_Done,
26722      // Label 1406: @69415
26723      GIM_Try, /*On fail goto*//*Label 1407*/ 69500, // Rule ID 4657 //
26724        GIM_CheckFeatures, GIFBS_HasMVEInt,
26725        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmull,
26726        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
26727        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26728        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26729        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26730        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26731        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26732        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26733        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
26734        // (intrinsic_wo_chain:{ *:[v2i64] } 2498:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] })  =>  (MVE_VQDMULLs32th:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26735        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26736        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26737        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26738        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMULLs32th,
26739        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26740        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
26741        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26742        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26743        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26744        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26745        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26746        GIR_EraseFromParent, /*InsnID*/0,
26747        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26748        // GIR_Coverage, 4657,
26749        GIR_Done,
26750      // Label 1407: @69500
26751      GIM_Try, /*On fail goto*//*Label 1408*/ 69580, // Rule ID 4004 //
26752        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsli,
26753        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26754        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26755        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26756        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26757        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26758        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26759        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26760        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
26761        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
26762        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_7,
26763        // MIs[1] Operand 1
26764        // No operand predicates
26765        GIM_CheckIsSafeToFold, /*InsnID*/1,
26766        // (intrinsic_wo_chain:{ *:[v16i8] } 2538:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)  =>  (MVE_VSLIimm8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
26767        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSLIimm8,
26768        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26769        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
26770        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
26771        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
26772        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26773        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26774        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26775        GIR_EraseFromParent, /*InsnID*/0,
26776        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26777        // GIR_Coverage, 4004,
26778        GIR_Done,
26779      // Label 1408: @69580
26780      GIM_Try, /*On fail goto*//*Label 1409*/ 69660, // Rule ID 4006 //
26781        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsli,
26782        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26783        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26784        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26785        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26786        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26787        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26788        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26789        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
26790        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
26791        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
26792        // MIs[1] Operand 1
26793        // No operand predicates
26794        GIM_CheckIsSafeToFold, /*InsnID*/1,
26795        // (intrinsic_wo_chain:{ *:[v8i16] } 2538:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)  =>  (MVE_VSLIimm16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
26796        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSLIimm16,
26797        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26798        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
26799        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
26800        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
26801        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26802        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26803        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26804        GIR_EraseFromParent, /*InsnID*/0,
26805        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26806        // GIR_Coverage, 4006,
26807        GIR_Done,
26808      // Label 1409: @69660
26809      GIM_Try, /*On fail goto*//*Label 1410*/ 69740, // Rule ID 4008 //
26810        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsli,
26811        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26812        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26813        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26814        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26815        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26816        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26817        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26818        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
26819        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
26820        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
26821        // MIs[1] Operand 1
26822        // No operand predicates
26823        GIM_CheckIsSafeToFold, /*InsnID*/1,
26824        // (intrinsic_wo_chain:{ *:[v4i32] } 2538:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)  =>  (MVE_VSLIimm32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
26825        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSLIimm32,
26826        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26827        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
26828        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
26829        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
26830        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26831        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26832        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26833        GIR_EraseFromParent, /*InsnID*/0,
26834        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26835        // GIR_Coverage, 4008,
26836        GIR_Done,
26837      // Label 1410: @69740
26838      GIM_Try, /*On fail goto*//*Label 1411*/ 69820, // Rule ID 4010 //
26839        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsri,
26840        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26841        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26842        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26843        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26844        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26845        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26846        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26847        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
26848        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
26849        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
26850        // MIs[1] Operand 1
26851        // No operand predicates
26852        GIM_CheckIsSafeToFold, /*InsnID*/1,
26853        // (intrinsic_wo_chain:{ *:[v16i8] } 2540:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)  =>  (MVE_VSRIimm8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)
26854        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSRIimm8,
26855        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26856        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
26857        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
26858        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
26859        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26860        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26861        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26862        GIR_EraseFromParent, /*InsnID*/0,
26863        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26864        // GIR_Coverage, 4010,
26865        GIR_Done,
26866      // Label 1411: @69820
26867      GIM_Try, /*On fail goto*//*Label 1412*/ 69900, // Rule ID 4012 //
26868        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsri,
26869        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26870        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26871        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26872        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26873        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26874        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26875        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26876        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
26877        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
26878        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
26879        // MIs[1] Operand 1
26880        // No operand predicates
26881        GIM_CheckIsSafeToFold, /*InsnID*/1,
26882        // (intrinsic_wo_chain:{ *:[v8i16] } 2540:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)  =>  (MVE_VSRIimm16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)
26883        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSRIimm16,
26884        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26885        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
26886        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
26887        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
26888        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26889        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26890        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26891        GIR_EraseFromParent, /*InsnID*/0,
26892        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26893        // GIR_Coverage, 4012,
26894        GIR_Done,
26895      // Label 1412: @69900
26896      GIM_Try, /*On fail goto*//*Label 1413*/ 69980, // Rule ID 4014 //
26897        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsri,
26898        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26899        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26900        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26901        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26902        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26903        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26904        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26905        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
26906        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
26907        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm32,
26908        // MIs[1] Operand 1
26909        // No operand predicates
26910        GIM_CheckIsSafeToFold, /*InsnID*/1,
26911        // (intrinsic_wo_chain:{ *:[v4i32] } 2540:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)  =>  (MVE_VSRIimm32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)
26912        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSRIimm32,
26913        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26914        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
26915        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
26916        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
26917        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26918        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26919        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26920        GIR_EraseFromParent, /*InsnID*/0,
26921        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26922        // GIR_Coverage, 4014,
26923        GIR_Done,
26924      // Label 1413: @69980
26925      GIM_Try, /*On fail goto*//*Label 1414*/ 70073, // Rule ID 4481 //
26926        GIM_CheckFeatures, GIFBS_HasMVEFloat,
26927        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcmulq,
26928        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26929        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26930        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26931        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
26932        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26933        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
26934        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
26935        // MIs[1] Operand 1
26936        // No operand predicates
26937        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26938        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
26939        GIM_CheckIsSafeToFold, /*InsnID*/1,
26940        // (intrinsic_wo_chain:{ *:[v8f16] } 2437:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm)  =>  (MVE_VCMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
26941        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26942        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26943        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26944        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMULf16,
26945        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26946        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26947        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qm
26948        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
26949        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26950        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26951        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26952        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26953        GIR_EraseFromParent, /*InsnID*/0,
26954        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26955        // GIR_Coverage, 4481,
26956        GIR_Done,
26957      // Label 1414: @70073
26958      GIM_Try, /*On fail goto*//*Label 1415*/ 70166, // Rule ID 4483 //
26959        GIM_CheckFeatures, GIFBS_HasMVEFloat,
26960        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcmulq,
26961        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26962        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26963        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26964        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
26965        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26966        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
26967        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
26968        // MIs[1] Operand 1
26969        // No operand predicates
26970        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26971        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
26972        GIM_CheckIsSafeToFold, /*InsnID*/1,
26973        // (intrinsic_wo_chain:{ *:[v4f32] } 2437:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm)  =>  (MVE_VCMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
26974        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26975        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26976        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26977        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMULf32,
26978        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26979        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26980        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qm
26981        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
26982        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26983        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26984        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26985        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26986        GIR_EraseFromParent, /*InsnID*/0,
26987        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26988        // GIR_Coverage, 4483,
26989        GIR_Done,
26990      // Label 1415: @70166
26991      GIM_Try, /*On fail goto*//*Label 1416*/ 70237, // Rule ID 146 //
26992        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
26993        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usada8,
26994        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26995        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26996        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26997        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26998        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
26999        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
27000        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
27001        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27002        // (intrinsic_wo_chain:{ *:[i32] } 2770:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)  =>  (USADA8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
27003        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USADA8,
27004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27005        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
27006        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
27007        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
27008        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27009        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27010        GIR_EraseFromParent, /*InsnID*/0,
27011        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27012        // GIR_Coverage, 146,
27013        GIR_Done,
27014      // Label 1416: @70237
27015      GIM_Try, /*On fail goto*//*Label 1417*/ 70308, // Rule ID 476 //
27016        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
27017        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usada8,
27018        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27019        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27020        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27021        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27022        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
27023        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
27024        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
27025        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
27026        // (intrinsic_wo_chain:{ *:[i32] } 2770:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)  =>  (t2USADA8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
27027        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USADA8,
27028        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27029        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
27030        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
27031        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
27032        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27033        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27034        GIR_EraseFromParent, /*InsnID*/0,
27035        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27036        // GIR_Coverage, 476,
27037        GIR_Done,
27038      // Label 1417: @70308
27039      GIM_Try, /*On fail goto*//*Label 1418*/ 70379, // Rule ID 535 //
27040        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
27041        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlad,
27042        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27043        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27044        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27045        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27046        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
27047        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
27048        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
27049        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
27050        // (intrinsic_wo_chain:{ *:[i32] } 2715:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
27051        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLAD,
27052        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27053        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
27054        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
27055        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
27056        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27057        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27058        GIR_EraseFromParent, /*InsnID*/0,
27059        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27060        // GIR_Coverage, 535,
27061        GIR_Done,
27062      // Label 1418: @70379
27063      GIM_Try, /*On fail goto*//*Label 1419*/ 70450, // Rule ID 536 //
27064        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
27065        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smladx,
27066        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27067        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27068        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27069        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27070        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
27071        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
27072        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
27073        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
27074        // (intrinsic_wo_chain:{ *:[i32] } 2716:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
27075        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLADX,
27076        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27077        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
27078        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
27079        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
27080        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27081        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27082        GIR_EraseFromParent, /*InsnID*/0,
27083        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27084        // GIR_Coverage, 536,
27085        GIR_Done,
27086      // Label 1419: @70450
27087      GIM_Try, /*On fail goto*//*Label 1420*/ 70521, // Rule ID 537 //
27088        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
27089        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsd,
27090        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27091        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27092        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27093        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27094        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
27095        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
27096        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
27097        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
27098        // (intrinsic_wo_chain:{ *:[i32] } 2723:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
27099        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLSD,
27100        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27101        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
27102        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
27103        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
27104        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27105        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27106        GIR_EraseFromParent, /*InsnID*/0,
27107        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27108        // GIR_Coverage, 537,
27109        GIR_Done,
27110      // Label 1420: @70521
27111      GIM_Try, /*On fail goto*//*Label 1421*/ 70592, // Rule ID 538 //
27112        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
27113        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsdx,
27114        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27115        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27116        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27117        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27118        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
27119        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
27120        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
27121        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
27122        // (intrinsic_wo_chain:{ *:[i32] } 2724:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
27123        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLSDX,
27124        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27125        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
27126        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
27127        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
27128        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27129        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27130        GIR_EraseFromParent, /*InsnID*/0,
27131        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27132        // GIR_Coverage, 538,
27133        GIR_Done,
27134      // Label 1421: @70592
27135      GIM_Try, /*On fail goto*//*Label 1422*/ 70656, // Rule ID 967 //
27136        GIM_CheckFeatures, GIFBS_HasDotProd,
27137        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_udot,
27138        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
27139        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
27140        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
27141        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
27142        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
27143        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
27144        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
27145        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
27146        // (intrinsic_wo_chain:{ *:[v2i32] } 2570:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VUDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
27147        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUDOTD,
27148        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
27149        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27150        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27151        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27152        GIR_EraseFromParent, /*InsnID*/0,
27153        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27154        // GIR_Coverage, 967,
27155        GIR_Done,
27156      // Label 1422: @70656
27157      GIM_Try, /*On fail goto*//*Label 1423*/ 70720, // Rule ID 968 //
27158        GIM_CheckFeatures, GIFBS_HasDotProd,
27159        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sdot,
27160        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
27161        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
27162        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
27163        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
27164        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
27165        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
27166        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
27167        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
27168        // (intrinsic_wo_chain:{ *:[v2i32] } 2558:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
27169        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSDOTD,
27170        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
27171        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27172        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27173        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27174        GIR_EraseFromParent, /*InsnID*/0,
27175        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27176        // GIR_Coverage, 968,
27177        GIR_Done,
27178      // Label 1423: @70720
27179      GIM_Try, /*On fail goto*//*Label 1424*/ 70784, // Rule ID 969 //
27180        GIM_CheckFeatures, GIFBS_HasDotProd,
27181        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_udot,
27182        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27183        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27184        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
27185        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
27186        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27187        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
27188        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
27189        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
27190        // (intrinsic_wo_chain:{ *:[v4i32] } 2570:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VUDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27191        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUDOTQ,
27192        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
27193        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27194        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27195        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27196        GIR_EraseFromParent, /*InsnID*/0,
27197        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27198        // GIR_Coverage, 969,
27199        GIR_Done,
27200      // Label 1424: @70784
27201      GIM_Try, /*On fail goto*//*Label 1425*/ 70848, // Rule ID 970 //
27202        GIM_CheckFeatures, GIFBS_HasDotProd,
27203        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sdot,
27204        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27205        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27206        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
27207        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
27208        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27209        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
27210        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
27211        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
27212        // (intrinsic_wo_chain:{ *:[v4i32] } 2558:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27213        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSDOTQ,
27214        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
27215        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27216        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27217        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27218        GIR_EraseFromParent, /*InsnID*/0,
27219        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27220        // GIR_Coverage, 970,
27221        GIR_Done,
27222      // Label 1425: @70848
27223      GIM_Try, /*On fail goto*//*Label 1426*/ 70912, // Rule ID 971 //
27224        GIM_CheckFeatures, GIFBS_HasMatMulInt8,
27225        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_smmla,
27226        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27227        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27228        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
27229        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
27230        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27231        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
27232        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
27233        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
27234        // (intrinsic_wo_chain:{ *:[v4i32] } 2569:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27235        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSMMLA,
27236        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
27237        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27238        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27239        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27240        GIR_EraseFromParent, /*InsnID*/0,
27241        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27242        // GIR_Coverage, 971,
27243        GIR_Done,
27244      // Label 1426: @70912
27245      GIM_Try, /*On fail goto*//*Label 1427*/ 70976, // Rule ID 972 //
27246        GIM_CheckFeatures, GIFBS_HasMatMulInt8,
27247        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_ummla,
27248        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27249        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27250        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
27251        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
27252        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27253        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
27254        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
27255        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
27256        // (intrinsic_wo_chain:{ *:[v4i32] } 2571:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VUMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27257        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUMMLA,
27258        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
27259        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27260        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27261        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27262        GIR_EraseFromParent, /*InsnID*/0,
27263        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27264        // GIR_Coverage, 972,
27265        GIR_Done,
27266      // Label 1427: @70976
27267      GIM_Try, /*On fail goto*//*Label 1428*/ 71040, // Rule ID 973 //
27268        GIM_CheckFeatures, GIFBS_HasMatMulInt8,
27269        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_usmmla,
27270        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27271        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27272        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
27273        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
27274        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27275        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
27276        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
27277        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
27278        // (intrinsic_wo_chain:{ *:[v4i32] } 2573:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VUSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27279        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUSMMLA,
27280        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
27281        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27282        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27283        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27284        GIR_EraseFromParent, /*InsnID*/0,
27285        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27286        // GIR_Coverage, 973,
27287        GIR_Done,
27288      // Label 1428: @71040
27289      GIM_Try, /*On fail goto*//*Label 1429*/ 71104, // Rule ID 974 //
27290        GIM_CheckFeatures, GIFBS_HasMatMulInt8,
27291        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_usdot,
27292        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
27293        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
27294        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
27295        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
27296        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
27297        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
27298        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
27299        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
27300        // (intrinsic_wo_chain:{ *:[v2i32] } 2572:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VUSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
27301        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUSDOTD,
27302        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
27303        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27304        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27305        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27306        GIR_EraseFromParent, /*InsnID*/0,
27307        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27308        // GIR_Coverage, 974,
27309        GIR_Done,
27310      // Label 1429: @71104
27311      GIM_Try, /*On fail goto*//*Label 1430*/ 71168, // Rule ID 975 //
27312        GIM_CheckFeatures, GIFBS_HasMatMulInt8,
27313        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_usdot,
27314        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27315        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27316        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
27317        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
27318        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27319        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
27320        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
27321        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
27322        // (intrinsic_wo_chain:{ *:[v4i32] } 2572:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VUSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27323        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUSDOTQ,
27324        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
27325        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27326        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27327        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27328        GIR_EraseFromParent, /*InsnID*/0,
27329        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27330        // GIR_Coverage, 975,
27331        GIR_Done,
27332      // Label 1430: @71168
27333      GIM_Try, /*On fail goto*//*Label 1431*/ 71239, // Rule ID 1708 //
27334        GIM_CheckFeatures, GIFBS_HasNEON,
27335        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbx1,
27336        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
27337        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
27338        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
27339        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
27340        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
27341        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
27342        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
27343        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
27344        // (intrinsic_wo_chain:{ *:[v8i8] } 2690:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VTBX1:{ *:[v8i8] } DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
27345        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBX1,
27346        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
27347        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // orig
27348        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27349        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27350        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27351        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27352        GIR_EraseFromParent, /*InsnID*/0,
27353        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27354        // GIR_Coverage, 1708,
27355        GIR_Done,
27356      // Label 1431: @71239
27357      GIM_Try, /*On fail goto*//*Label 1432*/ 71303, // Rule ID 1739 //
27358        GIM_CheckFeatures, GIFBS_HasSHA2_HasV8,
27359        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1su0,
27360        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27361        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27362        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
27363        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
27364        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27365        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
27366        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
27367        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
27368        // (intrinsic_wo_chain:{ *:[v4i32] } 2563:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA1SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
27369        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1SU0,
27370        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
27371        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
27372        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27373        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27374        GIR_EraseFromParent, /*InsnID*/0,
27375        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27376        // GIR_Coverage, 1739,
27377        GIR_Done,
27378      // Label 1432: @71303
27379      GIM_Try, /*On fail goto*//*Label 1433*/ 71367, // Rule ID 1740 //
27380        GIM_CheckFeatures, GIFBS_HasSHA2_HasV8,
27381        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256h,
27382        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27383        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27384        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
27385        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
27386        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27387        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
27388        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
27389        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
27390        // (intrinsic_wo_chain:{ *:[v4i32] } 2565:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA256H:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
27391        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256H,
27392        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
27393        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
27394        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27396        GIR_EraseFromParent, /*InsnID*/0,
27397        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27398        // GIR_Coverage, 1740,
27399        GIR_Done,
27400      // Label 1433: @71367
27401      GIM_Try, /*On fail goto*//*Label 1434*/ 71431, // Rule ID 1741 //
27402        GIM_CheckFeatures, GIFBS_HasSHA2_HasV8,
27403        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256h2,
27404        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27405        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27406        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
27407        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
27408        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27409        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
27410        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
27411        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
27412        // (intrinsic_wo_chain:{ *:[v4i32] } 2566:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA256H2:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
27413        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256H2,
27414        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
27415        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
27416        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27417        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27418        GIR_EraseFromParent, /*InsnID*/0,
27419        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27420        // GIR_Coverage, 1741,
27421        GIR_Done,
27422      // Label 1434: @71431
27423      GIM_Try, /*On fail goto*//*Label 1435*/ 71495, // Rule ID 1742 //
27424        GIM_CheckFeatures, GIFBS_HasSHA2_HasV8,
27425        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256su1,
27426        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27427        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27428        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
27429        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
27430        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27431        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
27432        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
27433        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
27434        // (intrinsic_wo_chain:{ *:[v4i32] } 2568:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA256SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
27435        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256SU1,
27436        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
27437        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
27438        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27439        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27440        GIR_EraseFromParent, /*InsnID*/0,
27441        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27442        // GIR_Coverage, 1742,
27443        GIR_Done,
27444      // Label 1435: @71495
27445      GIM_Try, /*On fail goto*//*Label 1436*/ 71559, // Rule ID 1743 //
27446        GIM_CheckFeatures, GIFBS_HasBF16_HasNEON,
27447        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_bfdot,
27448        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
27449        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
27450        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
27451        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16,
27452        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
27453        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
27454        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
27455        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
27456        // (intrinsic_wo_chain:{ *:[v2f32] } 2554:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vd, DPR:{ *:[v4bf16] }:$Vn, DPR:{ *:[v4bf16] }:$Vm)  =>  (BF16VDOTS_VDOTD:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vd, DPR:{ *:[v4bf16] }:$Vn, DPR:{ *:[v4bf16] }:$Vm)
27457        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BF16VDOTS_VDOTD,
27458        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
27459        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27460        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27461        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27462        GIR_EraseFromParent, /*InsnID*/0,
27463        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27464        // GIR_Coverage, 1743,
27465        GIR_Done,
27466      // Label 1436: @71559
27467      GIM_Try, /*On fail goto*//*Label 1437*/ 71623, // Rule ID 1744 //
27468        GIM_CheckFeatures, GIFBS_HasBF16_HasNEON,
27469        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_bfdot,
27470        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27471        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27472        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
27473        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
27474        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27475        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
27476        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
27477        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
27478        // (intrinsic_wo_chain:{ *:[v4f32] } 2554:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm)  =>  (BF16VDOTS_VDOTQ:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm)
27479        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BF16VDOTS_VDOTQ,
27480        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
27481        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27482        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27483        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27484        GIR_EraseFromParent, /*InsnID*/0,
27485        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27486        // GIR_Coverage, 1744,
27487        GIR_Done,
27488      // Label 1437: @71623
27489      GIM_Try, /*On fail goto*//*Label 1438*/ 71687, // Rule ID 1745 //
27490        GIM_CheckFeatures, GIFBS_HasBF16_HasNEON,
27491        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_bfmmla,
27492        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27493        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27494        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
27495        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
27496        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27497        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
27498        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
27499        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
27500        // (intrinsic_wo_chain:{ *:[v4f32] } 2557:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm)  =>  (VMMLA:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm)
27501        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMMLA,
27502        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
27503        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27504        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27505        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27506        GIR_EraseFromParent, /*InsnID*/0,
27507        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27508        // GIR_Coverage, 1745,
27509        GIR_Done,
27510      // Label 1438: @71687
27511      GIM_Try, /*On fail goto*//*Label 1439*/ 71751, // Rule ID 1746 //
27512        GIM_CheckFeatures, GIFBS_HasBF16_HasNEON,
27513        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_bfmlalt,
27514        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27515        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27516        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
27517        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
27518        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27519        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
27520        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
27521        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
27522        // (intrinsic_wo_chain:{ *:[v4f32] } 2556:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm)  =>  (VBF16MALTQ:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm)
27523        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBF16MALTQ,
27524        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
27525        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27526        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27527        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27528        GIR_EraseFromParent, /*InsnID*/0,
27529        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27530        // GIR_Coverage, 1746,
27531        GIR_Done,
27532      // Label 1439: @71751
27533      GIM_Try, /*On fail goto*//*Label 1440*/ 71815, // Rule ID 1747 //
27534        GIM_CheckFeatures, GIFBS_HasBF16_HasNEON,
27535        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_bfmlalb,
27536        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27537        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27538        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
27539        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
27540        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27541        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
27542        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
27543        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
27544        // (intrinsic_wo_chain:{ *:[v4f32] } 2555:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm)  =>  (VBF16MALBQ:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm)
27545        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBF16MALBQ,
27546        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
27547        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
27548        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27549        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27550        GIR_EraseFromParent, /*InsnID*/0,
27551        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27552        // GIR_Coverage, 1747,
27553        GIR_Done,
27554      // Label 1440: @71815
27555      GIM_Try, /*On fail goto*//*Label 1441*/ 71886, // Rule ID 1926 //
27556        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
27557        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlad,
27558        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27559        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27560        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27561        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27562        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
27563        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
27564        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
27565        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27566        // (intrinsic_wo_chain:{ *:[i32] } 2715:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)  =>  (SMLAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
27567        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLAD,
27568        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27569        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
27570        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
27571        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
27572        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27573        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27574        GIR_EraseFromParent, /*InsnID*/0,
27575        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27576        // GIR_Coverage, 1926,
27577        GIR_Done,
27578      // Label 1441: @71886
27579      GIM_Try, /*On fail goto*//*Label 1442*/ 71957, // Rule ID 1927 //
27580        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
27581        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smladx,
27582        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27583        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27584        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27585        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27586        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
27587        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
27588        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
27589        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27590        // (intrinsic_wo_chain:{ *:[i32] } 2716:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)  =>  (SMLADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
27591        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLADX,
27592        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27593        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
27594        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
27595        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
27596        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27597        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27598        GIR_EraseFromParent, /*InsnID*/0,
27599        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27600        // GIR_Coverage, 1927,
27601        GIR_Done,
27602      // Label 1442: @71957
27603      GIM_Try, /*On fail goto*//*Label 1443*/ 72028, // Rule ID 1928 //
27604        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
27605        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsd,
27606        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27607        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27608        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27609        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27610        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
27611        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
27612        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
27613        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27614        // (intrinsic_wo_chain:{ *:[i32] } 2723:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)  =>  (SMLSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
27615        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLSD,
27616        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27617        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
27618        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
27619        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
27620        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27621        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27622        GIR_EraseFromParent, /*InsnID*/0,
27623        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27624        // GIR_Coverage, 1928,
27625        GIR_Done,
27626      // Label 1443: @72028
27627      GIM_Try, /*On fail goto*//*Label 1444*/ 72099, // Rule ID 1929 //
27628        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
27629        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsdx,
27630        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27631        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27632        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27633        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27634        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
27635        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
27636        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
27637        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27638        // (intrinsic_wo_chain:{ *:[i32] } 2724:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)  =>  (SMLSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
27639        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLSDX,
27640        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27641        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
27642        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
27643        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
27644        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27645        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27646        GIR_EraseFromParent, /*InsnID*/0,
27647        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27648        // GIR_Coverage, 1929,
27649        GIR_Done,
27650      // Label 1444: @72099
27651      GIM_Try, /*On fail goto*//*Label 1445*/ 72170, // Rule ID 2005 //
27652        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
27653        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabb,
27654        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27655        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27656        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27657        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27658        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
27659        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
27660        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
27661        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27662        // (intrinsic_wo_chain:{ *:[i32] } 2713:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27663        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLABB,
27664        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27665        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27666        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27667        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27668        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27669        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27670        GIR_EraseFromParent, /*InsnID*/0,
27671        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27672        // GIR_Coverage, 2005,
27673        GIR_Done,
27674      // Label 1445: @72170
27675      GIM_Try, /*On fail goto*//*Label 1446*/ 72241, // Rule ID 2006 //
27676        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
27677        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabt,
27678        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27679        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27680        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27681        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27682        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
27683        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
27684        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
27685        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27686        // (intrinsic_wo_chain:{ *:[i32] } 2714:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27687        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLABT,
27688        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27689        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27690        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27691        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27692        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27693        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27694        GIR_EraseFromParent, /*InsnID*/0,
27695        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27696        // GIR_Coverage, 2006,
27697        GIR_Done,
27698      // Label 1446: @72241
27699      GIM_Try, /*On fail goto*//*Label 1447*/ 72312, // Rule ID 2007 //
27700        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
27701        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatb,
27702        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27703        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27704        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27705        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27706        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
27707        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
27708        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
27709        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27710        // (intrinsic_wo_chain:{ *:[i32] } 2719:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27711        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATB,
27712        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27713        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27714        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27715        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27716        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27717        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27718        GIR_EraseFromParent, /*InsnID*/0,
27719        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27720        // GIR_Coverage, 2007,
27721        GIR_Done,
27722      // Label 1447: @72312
27723      GIM_Try, /*On fail goto*//*Label 1448*/ 72383, // Rule ID 2008 //
27724        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
27725        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatt,
27726        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27727        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27728        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27729        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27730        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
27731        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
27732        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
27733        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27734        // (intrinsic_wo_chain:{ *:[i32] } 2720:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27735        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
27736        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27737        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27738        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27739        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27740        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27741        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27742        GIR_EraseFromParent, /*InsnID*/0,
27743        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27744        // GIR_Coverage, 2008,
27745        GIR_Done,
27746      // Label 1448: @72383
27747      GIM_Try, /*On fail goto*//*Label 1449*/ 72454, // Rule ID 2009 //
27748        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
27749        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawb,
27750        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27751        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27752        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27753        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27754        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
27755        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
27756        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
27757        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27758        // (intrinsic_wo_chain:{ *:[i32] } 2721:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27759        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLAWB,
27760        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27762        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27763        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27764        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27765        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27766        GIR_EraseFromParent, /*InsnID*/0,
27767        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27768        // GIR_Coverage, 2009,
27769        GIR_Done,
27770      // Label 1449: @72454
27771      GIM_Try, /*On fail goto*//*Label 1450*/ 72525, // Rule ID 2010 //
27772        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
27773        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawt,
27774        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27775        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27776        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27777        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27778        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
27779        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
27780        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
27781        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27782        // (intrinsic_wo_chain:{ *:[i32] } 2722:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27783        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLAWT,
27784        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27785        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27786        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27787        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27788        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27789        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27790        GIR_EraseFromParent, /*InsnID*/0,
27791        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27792        // GIR_Coverage, 2010,
27793        GIR_Done,
27794      // Label 1450: @72525
27795      GIM_Try, /*On fail goto*//*Label 1451*/ 72596, // Rule ID 2192 //
27796        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
27797        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabb,
27798        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27799        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27800        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27801        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27802        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
27803        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
27804        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
27805        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27806        // (intrinsic_wo_chain:{ *:[i32] } 2713:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27807        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLABB,
27808        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27809        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27810        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27811        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27812        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27813        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27814        GIR_EraseFromParent, /*InsnID*/0,
27815        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27816        // GIR_Coverage, 2192,
27817        GIR_Done,
27818      // Label 1451: @72596
27819      GIM_Try, /*On fail goto*//*Label 1452*/ 72667, // Rule ID 2193 //
27820        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
27821        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabt,
27822        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27823        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27824        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27825        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27826        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
27827        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
27828        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
27829        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27830        // (intrinsic_wo_chain:{ *:[i32] } 2714:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27831        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLABT,
27832        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27834        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27835        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27836        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27837        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27838        GIR_EraseFromParent, /*InsnID*/0,
27839        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27840        // GIR_Coverage, 2193,
27841        GIR_Done,
27842      // Label 1452: @72667
27843      GIM_Try, /*On fail goto*//*Label 1453*/ 72738, // Rule ID 2194 //
27844        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
27845        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatb,
27846        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27847        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27848        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27849        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27850        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
27851        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
27852        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
27853        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27854        // (intrinsic_wo_chain:{ *:[i32] } 2719:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27855        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATB,
27856        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27857        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27858        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27859        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27860        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27861        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27862        GIR_EraseFromParent, /*InsnID*/0,
27863        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27864        // GIR_Coverage, 2194,
27865        GIR_Done,
27866      // Label 1453: @72738
27867      GIM_Try, /*On fail goto*//*Label 1454*/ 72809, // Rule ID 2195 //
27868        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
27869        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatt,
27870        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27871        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27872        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27873        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27874        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
27875        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
27876        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
27877        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27878        // (intrinsic_wo_chain:{ *:[i32] } 2720:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27879        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
27880        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27881        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27882        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27883        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27884        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27885        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27886        GIR_EraseFromParent, /*InsnID*/0,
27887        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27888        // GIR_Coverage, 2195,
27889        GIR_Done,
27890      // Label 1454: @72809
27891      GIM_Try, /*On fail goto*//*Label 1455*/ 72880, // Rule ID 2196 //
27892        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
27893        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawb,
27894        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27895        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27896        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27897        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27898        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
27899        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
27900        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
27901        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27902        // (intrinsic_wo_chain:{ *:[i32] } 2721:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27903        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLAWB,
27904        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27905        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27906        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27907        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27908        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27909        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27910        GIR_EraseFromParent, /*InsnID*/0,
27911        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27912        // GIR_Coverage, 2196,
27913        GIR_Done,
27914      // Label 1455: @72880
27915      GIM_Try, /*On fail goto*//*Label 1456*/ 72951, // Rule ID 2197 //
27916        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
27917        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawt,
27918        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27919        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27920        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27921        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27922        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
27923        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
27924        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
27925        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27926        // (intrinsic_wo_chain:{ *:[i32] } 2722:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27927        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLAWT,
27928        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27929        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27930        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27931        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27932        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27933        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27934        GIR_EraseFromParent, /*InsnID*/0,
27935        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27936        // GIR_Coverage, 2197,
27937        GIR_Done,
27938      // Label 1456: @72951
27939      GIM_Try, /*On fail goto*//*Label 1457*/ 73022, // Rule ID 2466 //
27940        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
27941        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmlah,
27942        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
27943        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
27944        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
27945        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16,
27946        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
27947        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
27948        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
27949        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
27950        // (intrinsic_wo_chain:{ *:[v4i16] } 2642:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQRDMLAHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
27951        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv4i16,
27952        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
27953        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
27954        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27955        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27956        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27957        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27958        GIR_EraseFromParent, /*InsnID*/0,
27959        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27960        // GIR_Coverage, 2466,
27961        GIR_Done,
27962      // Label 1457: @73022
27963      GIM_Try, /*On fail goto*//*Label 1458*/ 73093, // Rule ID 2467 //
27964        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
27965        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmlah,
27966        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
27967        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
27968        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
27969        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s32,
27970        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
27971        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
27972        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
27973        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
27974        // (intrinsic_wo_chain:{ *:[v2i32] } 2642:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQRDMLAHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
27975        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv2i32,
27976        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
27977        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
27978        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27979        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27980        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27981        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27982        GIR_EraseFromParent, /*InsnID*/0,
27983        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27984        // GIR_Coverage, 2467,
27985        GIR_Done,
27986      // Label 1458: @73093
27987      GIM_Try, /*On fail goto*//*Label 1459*/ 73164, // Rule ID 2468 //
27988        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
27989        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmlah,
27990        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
27991        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
27992        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
27993        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
27994        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27995        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
27996        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
27997        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
27998        // (intrinsic_wo_chain:{ *:[v8i16] } 2642:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQRDMLAHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
27999        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv8i16,
28000        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
28001        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28002        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28003        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28004        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
28005        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28006        GIR_EraseFromParent, /*InsnID*/0,
28007        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28008        // GIR_Coverage, 2468,
28009        GIR_Done,
28010      // Label 1459: @73164
28011      GIM_Try, /*On fail goto*//*Label 1460*/ 73235, // Rule ID 2469 //
28012        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
28013        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmlah,
28014        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28015        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28016        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28017        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
28018        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
28019        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
28020        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
28021        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
28022        // (intrinsic_wo_chain:{ *:[v4i32] } 2642:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQRDMLAHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
28023        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv4i32,
28024        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
28025        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28026        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28027        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28028        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
28029        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28030        GIR_EraseFromParent, /*InsnID*/0,
28031        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28032        // GIR_Coverage, 2469,
28033        GIR_Done,
28034      // Label 1460: @73235
28035      GIM_Try, /*On fail goto*//*Label 1461*/ 73306, // Rule ID 2474 //
28036        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
28037        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmlsh,
28038        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
28039        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
28040        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
28041        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16,
28042        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
28043        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
28044        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
28045        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
28046        // (intrinsic_wo_chain:{ *:[v4i16] } 2643:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQRDMLSHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
28047        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLSHv4i16,
28048        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
28049        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28050        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28051        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28052        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
28053        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28054        GIR_EraseFromParent, /*InsnID*/0,
28055        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28056        // GIR_Coverage, 2474,
28057        GIR_Done,
28058      // Label 1461: @73306
28059      GIM_Try, /*On fail goto*//*Label 1462*/ 73377, // Rule ID 2475 //
28060        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
28061        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmlsh,
28062        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
28063        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
28064        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
28065        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s32,
28066        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
28067        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
28068        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
28069        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
28070        // (intrinsic_wo_chain:{ *:[v2i32] } 2643:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQRDMLSHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
28071        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLSHv2i32,
28072        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
28073        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28074        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28075        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28076        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
28077        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28078        GIR_EraseFromParent, /*InsnID*/0,
28079        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28080        // GIR_Coverage, 2475,
28081        GIR_Done,
28082      // Label 1462: @73377
28083      GIM_Try, /*On fail goto*//*Label 1463*/ 73448, // Rule ID 2476 //
28084        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
28085        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmlsh,
28086        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28087        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28088        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28089        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
28090        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
28091        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
28092        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
28093        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
28094        // (intrinsic_wo_chain:{ *:[v8i16] } 2643:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQRDMLSHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
28095        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLSHv8i16,
28096        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
28097        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28098        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28099        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28100        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
28101        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28102        GIR_EraseFromParent, /*InsnID*/0,
28103        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28104        // GIR_Coverage, 2476,
28105        GIR_Done,
28106      // Label 1463: @73448
28107      GIM_Try, /*On fail goto*//*Label 1464*/ 73519, // Rule ID 2477 //
28108        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
28109        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmlsh,
28110        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28111        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28112        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28113        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
28114        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
28115        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
28116        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
28117        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
28118        // (intrinsic_wo_chain:{ *:[v4i32] } 2643:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQRDMLSHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
28119        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLSHv4i32,
28120        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
28121        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28122        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28123        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28124        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
28125        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28126        GIR_EraseFromParent, /*InsnID*/0,
28127        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28128        // GIR_Coverage, 2477,
28129        GIR_Done,
28130      // Label 1464: @73519
28131      GIM_Try, /*On fail goto*//*Label 1465*/ 73590, // Rule ID 2554 //
28132        GIM_CheckFeatures, GIFBS_HasNEON,
28133        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
28134        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
28135        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
28136        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
28137        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
28138        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
28139        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
28140        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
28141        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
28142        // (intrinsic_wo_chain:{ *:[v8i8] } 2579:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VBSPd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
28143        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSPd,
28144        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
28145        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28146        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28147        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28148        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
28149        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28150        GIR_EraseFromParent, /*InsnID*/0,
28151        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28152        // GIR_Coverage, 2554,
28153        GIR_Done,
28154      // Label 1465: @73590
28155      GIM_Try, /*On fail goto*//*Label 1466*/ 73661, // Rule ID 2555 //
28156        GIM_CheckFeatures, GIFBS_HasNEON,
28157        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
28158        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
28159        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
28160        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
28161        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16,
28162        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
28163        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
28164        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
28165        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
28166        // (intrinsic_wo_chain:{ *:[v4i16] } 2579:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VBSPd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
28167        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSPd,
28168        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
28169        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28170        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28171        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28172        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
28173        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28174        GIR_EraseFromParent, /*InsnID*/0,
28175        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28176        // GIR_Coverage, 2555,
28177        GIR_Done,
28178      // Label 1466: @73661
28179      GIM_Try, /*On fail goto*//*Label 1467*/ 73732, // Rule ID 2556 //
28180        GIM_CheckFeatures, GIFBS_HasNEON,
28181        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
28182        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
28183        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
28184        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
28185        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s32,
28186        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
28187        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
28188        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
28189        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
28190        // (intrinsic_wo_chain:{ *:[v2i32] } 2579:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VBSPd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
28191        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSPd,
28192        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
28193        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28194        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28195        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28196        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
28197        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28198        GIR_EraseFromParent, /*InsnID*/0,
28199        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28200        // GIR_Coverage, 2556,
28201        GIR_Done,
28202      // Label 1467: @73732
28203      GIM_Try, /*On fail goto*//*Label 1468*/ 73803, // Rule ID 2557 //
28204        GIM_CheckFeatures, GIFBS_HasNEON,
28205        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
28206        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
28207        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
28208        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
28209        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s32,
28210        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
28211        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
28212        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
28213        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
28214        // (intrinsic_wo_chain:{ *:[v2f32] } 2579:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VBSPd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
28215        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSPd,
28216        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
28217        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28218        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28219        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28220        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
28221        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28222        GIR_EraseFromParent, /*InsnID*/0,
28223        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28224        // GIR_Coverage, 2557,
28225        GIR_Done,
28226      // Label 1468: @73803
28227      GIM_Try, /*On fail goto*//*Label 1469*/ 73874, // Rule ID 2558 //
28228        GIM_CheckFeatures, GIFBS_HasNEON,
28229        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
28230        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
28231        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
28232        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
28233        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
28234        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
28235        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
28236        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
28237        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
28238        // (intrinsic_wo_chain:{ *:[v1i64] } 2579:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VBSPd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
28239        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSPd,
28240        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
28241        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28242        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28243        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28244        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
28245        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28246        GIR_EraseFromParent, /*InsnID*/0,
28247        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28248        // GIR_Coverage, 2558,
28249        GIR_Done,
28250      // Label 1469: @73874
28251      GIM_Try, /*On fail goto*//*Label 1470*/ 73945, // Rule ID 2563 //
28252        GIM_CheckFeatures, GIFBS_HasNEON,
28253        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
28254        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28255        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28256        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
28257        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
28258        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
28259        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
28260        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
28261        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
28262        // (intrinsic_wo_chain:{ *:[v16i8] } 2579:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VBSPq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
28263        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSPq,
28264        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
28265        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28266        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28267        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28268        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
28269        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28270        GIR_EraseFromParent, /*InsnID*/0,
28271        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28272        // GIR_Coverage, 2563,
28273        GIR_Done,
28274      // Label 1470: @73945
28275      GIM_Try, /*On fail goto*//*Label 1471*/ 74016, // Rule ID 2564 //
28276        GIM_CheckFeatures, GIFBS_HasNEON,
28277        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
28278        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28279        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28280        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28281        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
28282        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
28283        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
28284        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
28285        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
28286        // (intrinsic_wo_chain:{ *:[v8i16] } 2579:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VBSPq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
28287        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSPq,
28288        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
28289        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28290        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28291        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28292        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
28293        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28294        GIR_EraseFromParent, /*InsnID*/0,
28295        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28296        // GIR_Coverage, 2564,
28297        GIR_Done,
28298      // Label 1471: @74016
28299      GIM_Try, /*On fail goto*//*Label 1472*/ 74087, // Rule ID 2565 //
28300        GIM_CheckFeatures, GIFBS_HasNEON,
28301        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
28302        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28303        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28304        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28305        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
28306        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
28307        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
28308        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
28309        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
28310        // (intrinsic_wo_chain:{ *:[v4i32] } 2579:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VBSPq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
28311        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSPq,
28312        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
28313        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28314        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28315        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28316        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
28317        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28318        GIR_EraseFromParent, /*InsnID*/0,
28319        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28320        // GIR_Coverage, 2565,
28321        GIR_Done,
28322      // Label 1472: @74087
28323      GIM_Try, /*On fail goto*//*Label 1473*/ 74158, // Rule ID 2566 //
28324        GIM_CheckFeatures, GIFBS_HasNEON,
28325        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
28326        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28327        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28328        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28329        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
28330        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
28331        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
28332        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
28333        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
28334        // (intrinsic_wo_chain:{ *:[v4f32] } 2579:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VBSPq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
28335        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSPq,
28336        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
28337        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28338        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28339        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28340        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
28341        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28342        GIR_EraseFromParent, /*InsnID*/0,
28343        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28344        // GIR_Coverage, 2566,
28345        GIR_Done,
28346      // Label 1473: @74158
28347      GIM_Try, /*On fail goto*//*Label 1474*/ 74229, // Rule ID 2567 //
28348        GIM_CheckFeatures, GIFBS_HasNEON,
28349        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
28350        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
28351        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
28352        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
28353        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
28354        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
28355        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
28356        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
28357        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
28358        // (intrinsic_wo_chain:{ *:[v2i64] } 2579:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VBSPq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
28359        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSPq,
28360        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
28361        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
28362        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
28363        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
28364        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
28365        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28366        GIR_EraseFromParent, /*InsnID*/0,
28367        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28368        // GIR_Coverage, 2567,
28369        GIR_Done,
28370      // Label 1474: @74229
28371      GIM_Try, /*On fail goto*//*Label 1475*/ 74304, // Rule ID 4940 //
28372        GIM_CheckFeatures, GIFBS_HasMVEInt,
28373        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlah,
28374        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28375        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28376        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
28377        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28378        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28379        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28380        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28381        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
28382        // (intrinsic_wo_chain:{ *:[v16i8] } 2493:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
28383        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLAH_qrs8,
28384        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28385        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28386        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28387        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28388        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28389        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28390        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28391        GIR_EraseFromParent, /*InsnID*/0,
28392        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28393        // GIR_Coverage, 4940,
28394        GIR_Done,
28395      // Label 1475: @74304
28396      GIM_Try, /*On fail goto*//*Label 1476*/ 74379, // Rule ID 4942 //
28397        GIM_CheckFeatures, GIFBS_HasMVEInt,
28398        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlah,
28399        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28400        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28401        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28402        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28403        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28404        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28405        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28406        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
28407        // (intrinsic_wo_chain:{ *:[v8i16] } 2493:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
28408        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLAH_qrs16,
28409        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28410        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28411        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28412        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28413        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28414        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28415        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28416        GIR_EraseFromParent, /*InsnID*/0,
28417        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28418        // GIR_Coverage, 4942,
28419        GIR_Done,
28420      // Label 1476: @74379
28421      GIM_Try, /*On fail goto*//*Label 1477*/ 74454, // Rule ID 4944 //
28422        GIM_CheckFeatures, GIFBS_HasMVEInt,
28423        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlah,
28424        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28425        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28426        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28427        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28428        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28429        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28430        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28431        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
28432        // (intrinsic_wo_chain:{ *:[v4i32] } 2493:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
28433        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLAH_qrs32,
28434        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28435        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28436        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28437        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28438        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28439        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28440        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28441        GIR_EraseFromParent, /*InsnID*/0,
28442        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28443        // GIR_Coverage, 4944,
28444        GIR_Done,
28445      // Label 1477: @74454
28446      GIM_Try, /*On fail goto*//*Label 1478*/ 74529, // Rule ID 4946 //
28447        GIM_CheckFeatures, GIFBS_HasMVEInt,
28448        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmlah,
28449        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28450        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28451        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
28452        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28453        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28454        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28455        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28456        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
28457        // (intrinsic_wo_chain:{ *:[v16i8] } 2502:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQRDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
28458        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLAH_qrs8,
28459        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28460        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28461        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28462        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28463        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28464        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28465        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28466        GIR_EraseFromParent, /*InsnID*/0,
28467        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28468        // GIR_Coverage, 4946,
28469        GIR_Done,
28470      // Label 1478: @74529
28471      GIM_Try, /*On fail goto*//*Label 1479*/ 74604, // Rule ID 4948 //
28472        GIM_CheckFeatures, GIFBS_HasMVEInt,
28473        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmlah,
28474        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28475        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28476        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28477        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28478        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28479        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28480        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28481        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
28482        // (intrinsic_wo_chain:{ *:[v8i16] } 2502:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQRDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
28483        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLAH_qrs16,
28484        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28485        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28486        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28487        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28488        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28489        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28490        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28491        GIR_EraseFromParent, /*InsnID*/0,
28492        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28493        // GIR_Coverage, 4948,
28494        GIR_Done,
28495      // Label 1479: @74604
28496      GIM_Try, /*On fail goto*//*Label 1480*/ 74679, // Rule ID 4950 //
28497        GIM_CheckFeatures, GIFBS_HasMVEInt,
28498        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmlah,
28499        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28500        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28501        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28502        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28503        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28504        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28505        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28506        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
28507        // (intrinsic_wo_chain:{ *:[v4i32] } 2502:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQRDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
28508        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLAH_qrs32,
28509        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28510        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28511        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28512        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28513        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28514        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28515        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28516        GIR_EraseFromParent, /*InsnID*/0,
28517        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28518        // GIR_Coverage, 4950,
28519        GIR_Done,
28520      // Label 1480: @74679
28521      GIM_Try, /*On fail goto*//*Label 1481*/ 74754, // Rule ID 4952 //
28522        GIM_CheckFeatures, GIFBS_HasMVEInt,
28523        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlash,
28524        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28525        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28526        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
28527        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28528        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28529        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28530        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28531        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
28532        // (intrinsic_wo_chain:{ *:[v16i8] } 2495:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
28533        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLASH_qrs8,
28534        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28535        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28536        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28537        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28538        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28539        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28540        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28541        GIR_EraseFromParent, /*InsnID*/0,
28542        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28543        // GIR_Coverage, 4952,
28544        GIR_Done,
28545      // Label 1481: @74754
28546      GIM_Try, /*On fail goto*//*Label 1482*/ 74829, // Rule ID 4954 //
28547        GIM_CheckFeatures, GIFBS_HasMVEInt,
28548        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlash,
28549        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28550        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28551        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28552        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28553        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28554        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28555        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28556        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
28557        // (intrinsic_wo_chain:{ *:[v8i16] } 2495:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
28558        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLASH_qrs16,
28559        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28560        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28561        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28562        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28563        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28564        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28565        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28566        GIR_EraseFromParent, /*InsnID*/0,
28567        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28568        // GIR_Coverage, 4954,
28569        GIR_Done,
28570      // Label 1482: @74829
28571      GIM_Try, /*On fail goto*//*Label 1483*/ 74904, // Rule ID 4956 //
28572        GIM_CheckFeatures, GIFBS_HasMVEInt,
28573        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlash,
28574        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28575        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28576        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28577        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28578        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28579        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28580        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28581        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
28582        // (intrinsic_wo_chain:{ *:[v4i32] } 2495:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
28583        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLASH_qrs32,
28584        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28585        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28586        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28587        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28588        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28589        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28590        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28591        GIR_EraseFromParent, /*InsnID*/0,
28592        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28593        // GIR_Coverage, 4956,
28594        GIR_Done,
28595      // Label 1483: @74904
28596      GIM_Try, /*On fail goto*//*Label 1484*/ 74979, // Rule ID 4958 //
28597        GIM_CheckFeatures, GIFBS_HasMVEInt,
28598        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmlash,
28599        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28600        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28601        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
28602        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28603        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28604        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28605        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28606        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
28607        // (intrinsic_wo_chain:{ *:[v16i8] } 2504:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQRDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
28608        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLASH_qrs8,
28609        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28610        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28611        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28612        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28613        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28614        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28615        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28616        GIR_EraseFromParent, /*InsnID*/0,
28617        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28618        // GIR_Coverage, 4958,
28619        GIR_Done,
28620      // Label 1484: @74979
28621      GIM_Try, /*On fail goto*//*Label 1485*/ 75054, // Rule ID 4960 //
28622        GIM_CheckFeatures, GIFBS_HasMVEInt,
28623        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmlash,
28624        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28625        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28626        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28627        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28628        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28629        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28630        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28631        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
28632        // (intrinsic_wo_chain:{ *:[v8i16] } 2504:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQRDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
28633        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLASH_qrs16,
28634        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28635        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28636        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28637        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28638        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28639        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28640        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28641        GIR_EraseFromParent, /*InsnID*/0,
28642        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28643        // GIR_Coverage, 4960,
28644        GIR_Done,
28645      // Label 1485: @75054
28646      GIM_Try, /*On fail goto*//*Label 1486*/ 75129, // Rule ID 4962 //
28647        GIM_CheckFeatures, GIFBS_HasMVEInt,
28648        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmlash,
28649        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28650        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28651        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28652        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28653        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28654        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28655        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28656        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
28657        // (intrinsic_wo_chain:{ *:[v4i32] } 2504:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)  =>  (MVE_VQRDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
28658        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLASH_qrs32,
28659        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28660        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
28661        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
28662        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
28663        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28664        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28665        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28666        GIR_EraseFromParent, /*InsnID*/0,
28667        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28668        // GIR_Coverage, 4962,
28669        GIR_Done,
28670      // Label 1486: @75129
28671      GIM_Try, /*On fail goto*//*Label 1487*/ 75225, // Rule ID 2709 //
28672        GIM_CheckFeatures, GIFBS_HasNEON,
28673        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1c,
28674        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28675        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28676        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28677        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
28678        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
28679        // (intrinsic_wo_chain:{ *:[v4i32] } 2559:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk)  =>  (SHA1C:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
28680        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
28681        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
28682        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
28683        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
28684        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
28685        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
28686        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
28687        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
28688        GIR_AddImm, /*InsnID*/1, /*Imm*/0,
28689        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
28690        GIR_AddImm, /*InsnID*/1, /*Imm*/17,
28691        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, ARM::DPair_with_ssub_0RegClassID,
28692        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, ARM::SPRRegClassID,
28693        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1C,
28694        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
28695        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // hash_abcd
28696        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28697        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wk
28698        GIR_EraseFromParent, /*InsnID*/0,
28699        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28700        // GIR_Coverage, 2709,
28701        GIR_Done,
28702      // Label 1487: @75225
28703      GIM_Try, /*On fail goto*//*Label 1488*/ 75321, // Rule ID 2710 //
28704        GIM_CheckFeatures, GIFBS_HasNEON,
28705        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1m,
28706        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28707        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28708        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28709        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
28710        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
28711        // (intrinsic_wo_chain:{ *:[v4i32] } 2561:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk)  =>  (SHA1M:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
28712        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
28713        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
28714        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
28715        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
28716        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
28717        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
28718        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
28719        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
28720        GIR_AddImm, /*InsnID*/1, /*Imm*/0,
28721        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
28722        GIR_AddImm, /*InsnID*/1, /*Imm*/17,
28723        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, ARM::DPair_with_ssub_0RegClassID,
28724        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, ARM::SPRRegClassID,
28725        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1M,
28726        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
28727        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // hash_abcd
28728        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28729        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wk
28730        GIR_EraseFromParent, /*InsnID*/0,
28731        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28732        // GIR_Coverage, 2710,
28733        GIR_Done,
28734      // Label 1488: @75321
28735      GIM_Try, /*On fail goto*//*Label 1489*/ 75417, // Rule ID 2711 //
28736        GIM_CheckFeatures, GIFBS_HasNEON,
28737        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1p,
28738        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28739        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28740        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28741        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
28742        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
28743        // (intrinsic_wo_chain:{ *:[v4i32] } 2562:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk)  =>  (SHA1P:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
28744        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
28745        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
28746        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
28747        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
28748        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
28749        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
28750        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
28751        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
28752        GIR_AddImm, /*InsnID*/1, /*Imm*/0,
28753        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
28754        GIR_AddImm, /*InsnID*/1, /*Imm*/17,
28755        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, ARM::DPair_with_ssub_0RegClassID,
28756        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, ARM::SPRRegClassID,
28757        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1P,
28758        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
28759        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // hash_abcd
28760        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wk
28762        GIR_EraseFromParent, /*InsnID*/0,
28763        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28764        // GIR_Coverage, 2711,
28765        GIR_Done,
28766      // Label 1489: @75417
28767      GIM_Reject,
28768    // Label 1327: @75418
28769    GIM_Try, /*On fail goto*//*Label 1490*/ 78952,
28770      GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
28771      GIM_Try, /*On fail goto*//*Label 1491*/ 75510, // Rule ID 3839 //
28772        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
28773        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28774        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28775        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28776        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28777        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28778        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28779        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28780        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 8,
28781        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
28782        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28783        // (intrinsic_wo_chain:{ *:[v8i16] } 2534:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHLL_lws8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
28784        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28785        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28786        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28787        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lws8bh,
28788        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28789        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
28790        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28791        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28792        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28793        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28794        GIR_EraseFromParent, /*InsnID*/0,
28795        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28796        // GIR_Coverage, 3839,
28797        GIR_Done,
28798      // Label 1491: @75510
28799      GIM_Try, /*On fail goto*//*Label 1492*/ 75597, // Rule ID 3843 //
28800        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
28801        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28802        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28803        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28804        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28805        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28806        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28807        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28808        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 8,
28809        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
28810        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28811        // (intrinsic_wo_chain:{ *:[v8i16] } 2534:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHLL_lws8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
28812        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28813        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28814        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28815        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lws8th,
28816        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28817        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
28818        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28819        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28820        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28821        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28822        GIR_EraseFromParent, /*InsnID*/0,
28823        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28824        // GIR_Coverage, 3843,
28825        GIR_Done,
28826      // Label 1492: @75597
28827      GIM_Try, /*On fail goto*//*Label 1493*/ 75684, // Rule ID 3847 //
28828        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
28829        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28830        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28831        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28832        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28833        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28834        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28835        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28836        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 16,
28837        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
28838        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28839        // (intrinsic_wo_chain:{ *:[v4i32] } 2534:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHLL_lws16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
28840        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28841        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28842        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28843        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lws16bh,
28844        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28845        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
28846        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28847        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28848        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28849        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28850        GIR_EraseFromParent, /*InsnID*/0,
28851        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28852        // GIR_Coverage, 3847,
28853        GIR_Done,
28854      // Label 1493: @75684
28855      GIM_Try, /*On fail goto*//*Label 1494*/ 75771, // Rule ID 3851 //
28856        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
28857        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28858        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28859        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28860        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28861        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28862        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28863        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28864        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 16,
28865        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
28866        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28867        // (intrinsic_wo_chain:{ *:[v4i32] } 2534:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHLL_lws16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
28868        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28869        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28870        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28871        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lws16th,
28872        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28873        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
28874        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28875        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28876        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28877        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28878        GIR_EraseFromParent, /*InsnID*/0,
28879        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28880        // GIR_Coverage, 3851,
28881        GIR_Done,
28882      // Label 1494: @75771
28883      GIM_Try, /*On fail goto*//*Label 1495*/ 75858, // Rule ID 3855 //
28884        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
28885        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28886        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28887        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28888        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28889        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28890        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28891        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28892        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 8,
28893        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
28894        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28895        // (intrinsic_wo_chain:{ *:[v8i16] } 2534:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHLL_lwu8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
28896        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28897        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28898        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28899        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lwu8bh,
28900        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28901        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
28902        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28903        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28904        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28905        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28906        GIR_EraseFromParent, /*InsnID*/0,
28907        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28908        // GIR_Coverage, 3855,
28909        GIR_Done,
28910      // Label 1495: @75858
28911      GIM_Try, /*On fail goto*//*Label 1496*/ 75945, // Rule ID 3859 //
28912        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
28913        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28914        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28915        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28916        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28917        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28918        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28919        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28920        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 8,
28921        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
28922        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28923        // (intrinsic_wo_chain:{ *:[v8i16] } 2534:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHLL_lwu8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
28924        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28925        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28926        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28927        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lwu8th,
28928        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28929        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
28930        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28931        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28932        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28933        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28934        GIR_EraseFromParent, /*InsnID*/0,
28935        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28936        // GIR_Coverage, 3859,
28937        GIR_Done,
28938      // Label 1496: @75945
28939      GIM_Try, /*On fail goto*//*Label 1497*/ 76032, // Rule ID 3863 //
28940        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
28941        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28942        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28943        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28944        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28945        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28946        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28947        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28948        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 16,
28949        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
28950        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28951        // (intrinsic_wo_chain:{ *:[v4i32] } 2534:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHLL_lwu16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
28952        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28953        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28954        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28955        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lwu16bh,
28956        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28957        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
28958        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28959        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28960        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28961        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28962        GIR_EraseFromParent, /*InsnID*/0,
28963        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28964        // GIR_Coverage, 3863,
28965        GIR_Done,
28966      // Label 1497: @76032
28967      GIM_Try, /*On fail goto*//*Label 1498*/ 76119, // Rule ID 3867 //
28968        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
28969        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28970        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28971        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28972        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28973        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28974        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28975        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28976        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 16,
28977        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
28978        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28979        // (intrinsic_wo_chain:{ *:[v4i32] } 2534:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHLL_lwu16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
28980        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28981        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28982        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28983        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lwu16th,
28984        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28985        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
28986        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28987        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28988        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28989        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28990        GIR_EraseFromParent, /*InsnID*/0,
28991        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28992        // GIR_Coverage, 3867,
28993        GIR_Done,
28994      // Label 1498: @76119
28995      GIM_Try, /*On fail goto*//*Label 1499*/ 76212, // Rule ID 4485 //
28996        GIM_CheckFeatures, GIFBS_HasMVEInt,
28997        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
28998        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28999        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29000        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
29001        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29002        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29003        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29004        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29005        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29006        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29007        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29008        // (intrinsic_wo_chain:{ *:[v8i16] } 2489:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VMULLBs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
29009        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29010        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29011        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29012        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBs8,
29013        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29014        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29015        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29016        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29017        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29018        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29019        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29020        GIR_EraseFromParent, /*InsnID*/0,
29021        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29022        // GIR_Coverage, 4485,
29023        GIR_Done,
29024      // Label 1499: @76212
29025      GIM_Try, /*On fail goto*//*Label 1500*/ 76305, // Rule ID 4487 //
29026        GIM_CheckFeatures, GIFBS_HasMVEInt,
29027        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
29028        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29029        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29030        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
29031        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29032        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29033        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29034        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29035        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29036        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29037        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29038        // (intrinsic_wo_chain:{ *:[v8i16] } 2489:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VMULLTs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
29039        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29040        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29041        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29042        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTs8,
29043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29044        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29045        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29046        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29047        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29048        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29049        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29050        GIR_EraseFromParent, /*InsnID*/0,
29051        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29052        // GIR_Coverage, 4487,
29053        GIR_Done,
29054      // Label 1500: @76305
29055      GIM_Try, /*On fail goto*//*Label 1501*/ 76398, // Rule ID 4489 //
29056        GIM_CheckFeatures, GIFBS_HasMVEInt,
29057        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
29058        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29059        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29060        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29061        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29062        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29063        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29064        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29065        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29066        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29067        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29068        // (intrinsic_wo_chain:{ *:[v4i32] } 2489:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VMULLBs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
29069        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29070        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29071        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29072        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBs16,
29073        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29074        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29075        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29076        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29077        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29078        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29079        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29080        GIR_EraseFromParent, /*InsnID*/0,
29081        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29082        // GIR_Coverage, 4489,
29083        GIR_Done,
29084      // Label 1501: @76398
29085      GIM_Try, /*On fail goto*//*Label 1502*/ 76491, // Rule ID 4491 //
29086        GIM_CheckFeatures, GIFBS_HasMVEInt,
29087        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
29088        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29089        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29090        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29091        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29092        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29093        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29094        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29095        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29096        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29097        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29098        // (intrinsic_wo_chain:{ *:[v4i32] } 2489:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VMULLTs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
29099        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29100        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29101        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29102        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTs16,
29103        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29104        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29106        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29107        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29108        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29109        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29110        GIR_EraseFromParent, /*InsnID*/0,
29111        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29112        // GIR_Coverage, 4491,
29113        GIR_Done,
29114      // Label 1502: @76491
29115      GIM_Try, /*On fail goto*//*Label 1503*/ 76584, // Rule ID 4493 //
29116        GIM_CheckFeatures, GIFBS_HasMVEInt,
29117        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
29118        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
29119        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
29120        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29121        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29122        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29123        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29124        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29125        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29126        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29127        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29128        // (intrinsic_wo_chain:{ *:[v2i64] } 2489:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VMULLBs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
29129        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29130        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29131        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29132        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBs32,
29133        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29134        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29135        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29136        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29137        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29138        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29139        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29140        GIR_EraseFromParent, /*InsnID*/0,
29141        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29142        // GIR_Coverage, 4493,
29143        GIR_Done,
29144      // Label 1503: @76584
29145      GIM_Try, /*On fail goto*//*Label 1504*/ 76677, // Rule ID 4495 //
29146        GIM_CheckFeatures, GIFBS_HasMVEInt,
29147        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
29148        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
29149        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
29150        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29151        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29152        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29153        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29154        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29155        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29156        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29157        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29158        // (intrinsic_wo_chain:{ *:[v2i64] } 2489:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VMULLTs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
29159        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29160        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29161        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29162        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTs32,
29163        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29164        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29165        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29166        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29167        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29168        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29169        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29170        GIR_EraseFromParent, /*InsnID*/0,
29171        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29172        // GIR_Coverage, 4495,
29173        GIR_Done,
29174      // Label 1504: @76677
29175      GIM_Try, /*On fail goto*//*Label 1505*/ 76770, // Rule ID 4497 //
29176        GIM_CheckFeatures, GIFBS_HasMVEInt,
29177        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
29178        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29179        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29180        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
29181        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29182        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29183        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29184        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29185        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29186        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29187        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29188        // (intrinsic_wo_chain:{ *:[v8i16] } 2489:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VMULLBu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
29189        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29190        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29191        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29192        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBu8,
29193        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29194        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29195        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29196        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29197        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29198        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29199        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29200        GIR_EraseFromParent, /*InsnID*/0,
29201        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29202        // GIR_Coverage, 4497,
29203        GIR_Done,
29204      // Label 1505: @76770
29205      GIM_Try, /*On fail goto*//*Label 1506*/ 76863, // Rule ID 4499 //
29206        GIM_CheckFeatures, GIFBS_HasMVEInt,
29207        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
29208        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29209        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29210        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
29211        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29212        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29213        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29214        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29215        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29216        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29217        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29218        // (intrinsic_wo_chain:{ *:[v8i16] } 2489:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VMULLTu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
29219        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29220        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29221        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29222        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTu8,
29223        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29224        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29225        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29226        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29227        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29228        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29229        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29230        GIR_EraseFromParent, /*InsnID*/0,
29231        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29232        // GIR_Coverage, 4499,
29233        GIR_Done,
29234      // Label 1506: @76863
29235      GIM_Try, /*On fail goto*//*Label 1507*/ 76956, // Rule ID 4501 //
29236        GIM_CheckFeatures, GIFBS_HasMVEInt,
29237        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
29238        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29239        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29240        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29241        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29242        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29243        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29244        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29245        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29246        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29247        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29248        // (intrinsic_wo_chain:{ *:[v4i32] } 2489:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VMULLBu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
29249        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29250        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29251        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29252        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBu16,
29253        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29254        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29255        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29256        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29257        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29258        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29259        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29260        GIR_EraseFromParent, /*InsnID*/0,
29261        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29262        // GIR_Coverage, 4501,
29263        GIR_Done,
29264      // Label 1507: @76956
29265      GIM_Try, /*On fail goto*//*Label 1508*/ 77049, // Rule ID 4503 //
29266        GIM_CheckFeatures, GIFBS_HasMVEInt,
29267        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
29268        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29269        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29270        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29271        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29272        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29273        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29274        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29275        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29276        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29277        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29278        // (intrinsic_wo_chain:{ *:[v4i32] } 2489:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VMULLTu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
29279        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29280        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29281        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29282        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTu16,
29283        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29284        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29285        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29286        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29287        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29288        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29289        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29290        GIR_EraseFromParent, /*InsnID*/0,
29291        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29292        // GIR_Coverage, 4503,
29293        GIR_Done,
29294      // Label 1508: @77049
29295      GIM_Try, /*On fail goto*//*Label 1509*/ 77142, // Rule ID 4505 //
29296        GIM_CheckFeatures, GIFBS_HasMVEInt,
29297        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
29298        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
29299        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
29300        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29301        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29302        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29303        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29304        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29305        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29306        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29307        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29308        // (intrinsic_wo_chain:{ *:[v2i64] } 2489:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VMULLBu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
29309        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29310        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29311        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29312        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBu32,
29313        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29314        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29315        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29316        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29317        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29318        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29319        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29320        GIR_EraseFromParent, /*InsnID*/0,
29321        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29322        // GIR_Coverage, 4505,
29323        GIR_Done,
29324      // Label 1509: @77142
29325      GIM_Try, /*On fail goto*//*Label 1510*/ 77235, // Rule ID 4507 //
29326        GIM_CheckFeatures, GIFBS_HasMVEInt,
29327        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
29328        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
29329        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
29330        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29331        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29332        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29333        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29334        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29335        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29336        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29337        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29338        // (intrinsic_wo_chain:{ *:[v2i64] } 2489:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VMULLTu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
29339        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29340        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29341        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29342        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTu32,
29343        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29344        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
29345        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
29346        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29347        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29348        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29349        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29350        GIR_EraseFromParent, /*InsnID*/0,
29351        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29352        // GIR_Coverage, 4507,
29353        GIR_Done,
29354      // Label 1510: @77235
29355      GIM_Try, /*On fail goto*//*Label 1511*/ 77336, // Rule ID 4130 //
29356        GIM_CheckFeatures, GIFBS_HasMVEFloat,
29357        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
29358        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29359        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29360        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29361        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
29362        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
29363        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29364        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
29365        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29366        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29367        // MIs[1] Operand 1
29368        // No operand predicates
29369        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
29370        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
29371        GIM_CheckIsSafeToFold, /*InsnID*/1,
29372        // (intrinsic_wo_chain:{ *:[v8f16] } 2432:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm)  =>  (MVE_VCADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
29373        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29374        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29375        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29376        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCADDf16,
29377        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29378        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29379        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29380        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29381        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29382        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29383        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29384        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29385        GIR_EraseFromParent, /*InsnID*/0,
29386        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29387        // GIR_Coverage, 4130,
29388        GIR_Done,
29389      // Label 1511: @77336
29390      GIM_Try, /*On fail goto*//*Label 1512*/ 77437, // Rule ID 4132 //
29391        GIM_CheckFeatures, GIFBS_HasMVEFloat,
29392        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
29393        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29394        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29395        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29396        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
29397        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
29398        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29399        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
29400        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29401        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29402        // MIs[1] Operand 1
29403        // No operand predicates
29404        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
29405        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
29406        GIM_CheckIsSafeToFold, /*InsnID*/1,
29407        // (intrinsic_wo_chain:{ *:[v4f32] } 2432:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm)  =>  (MVE_VCADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
29408        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29409        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29410        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29411        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCADDf32,
29412        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29413        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29414        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29415        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29416        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29417        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29418        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29419        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29420        GIR_EraseFromParent, /*InsnID*/0,
29421        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29422        // GIR_Coverage, 4132,
29423        GIR_Done,
29424      // Label 1512: @77437
29425      GIM_Try, /*On fail goto*//*Label 1513*/ 77538, // Rule ID 4639 //
29426        GIM_CheckFeatures, GIFBS_HasMVEInt,
29427        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
29428        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29429        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29430        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29431        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
29432        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v16s8,
29433        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29434        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
29435        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29436        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29437        // MIs[1] Operand 1
29438        // No operand predicates
29439        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
29440        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
29441        GIM_CheckIsSafeToFold, /*InsnID*/1,
29442        // (intrinsic_wo_chain:{ *:[v16i8] } 2432:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VCADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot)
29443        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29444        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29445        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29446        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCADDi8,
29447        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29448        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29449        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29450        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29451        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29452        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29453        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29454        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29455        GIR_EraseFromParent, /*InsnID*/0,
29456        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29457        // GIR_Coverage, 4639,
29458        GIR_Done,
29459      // Label 1513: @77538
29460      GIM_Try, /*On fail goto*//*Label 1514*/ 77639, // Rule ID 4641 //
29461        GIM_CheckFeatures, GIFBS_HasMVEInt,
29462        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
29463        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29464        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29465        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29466        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
29467        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
29468        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29469        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
29470        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29471        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29472        // MIs[1] Operand 1
29473        // No operand predicates
29474        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
29475        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
29476        GIM_CheckIsSafeToFold, /*InsnID*/1,
29477        // (intrinsic_wo_chain:{ *:[v8i16] } 2432:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VCADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot)
29478        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29479        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29480        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29481        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCADDi16,
29482        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29483        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29484        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29485        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29486        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29487        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29488        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29489        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29490        GIR_EraseFromParent, /*InsnID*/0,
29491        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29492        // GIR_Coverage, 4641,
29493        GIR_Done,
29494      // Label 1514: @77639
29495      GIM_Try, /*On fail goto*//*Label 1515*/ 77740, // Rule ID 4643 //
29496        GIM_CheckFeatures, GIFBS_HasMVEInt,
29497        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
29498        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29499        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29500        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29501        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
29502        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
29503        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29504        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
29505        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29506        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29507        // MIs[1] Operand 1
29508        // No operand predicates
29509        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
29510        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
29511        GIM_CheckIsSafeToFold, /*InsnID*/1,
29512        // (intrinsic_wo_chain:{ *:[v4i32] } 2432:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VCADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot)
29513        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29514        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29515        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29516        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCADDi32,
29517        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29518        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29519        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29520        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29521        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29522        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29523        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29524        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29525        GIR_EraseFromParent, /*InsnID*/0,
29526        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29527        // GIR_Coverage, 4643,
29528        GIR_Done,
29529      // Label 1515: @77740
29530      GIM_Try, /*On fail goto*//*Label 1516*/ 77841, // Rule ID 4645 //
29531        GIM_CheckFeatures, GIFBS_HasMVEInt,
29532        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
29533        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29534        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29535        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29536        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
29537        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v16s8,
29538        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29539        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
29540        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29541        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29542        // MIs[1] Operand 1
29543        // No operand predicates
29544        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
29545        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
29546        GIM_CheckIsSafeToFold, /*InsnID*/1,
29547        // (intrinsic_wo_chain:{ *:[v16i8] } 2432:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VHCADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot)
29548        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29549        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29550        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29551        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHCADDs8,
29552        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29553        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29554        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29555        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29556        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29557        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29558        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29559        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29560        GIR_EraseFromParent, /*InsnID*/0,
29561        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29562        // GIR_Coverage, 4645,
29563        GIR_Done,
29564      // Label 1516: @77841
29565      GIM_Try, /*On fail goto*//*Label 1517*/ 77942, // Rule ID 4647 //
29566        GIM_CheckFeatures, GIFBS_HasMVEInt,
29567        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
29568        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29569        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29570        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29571        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
29572        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
29573        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29574        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
29575        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29576        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29577        // MIs[1] Operand 1
29578        // No operand predicates
29579        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
29580        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
29581        GIM_CheckIsSafeToFold, /*InsnID*/1,
29582        // (intrinsic_wo_chain:{ *:[v8i16] } 2432:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VHCADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot)
29583        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29584        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29585        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29586        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHCADDs16,
29587        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29588        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29589        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29590        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29591        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29592        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29593        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29594        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29595        GIR_EraseFromParent, /*InsnID*/0,
29596        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29597        // GIR_Coverage, 4647,
29598        GIR_Done,
29599      // Label 1517: @77942
29600      GIM_Try, /*On fail goto*//*Label 1518*/ 78043, // Rule ID 4649 //
29601        GIM_CheckFeatures, GIFBS_HasMVEInt,
29602        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
29603        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29604        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29605        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29606        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
29607        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
29608        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29609        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
29610        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29611        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29612        // MIs[1] Operand 1
29613        // No operand predicates
29614        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
29615        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
29616        GIM_CheckIsSafeToFold, /*InsnID*/1,
29617        // (intrinsic_wo_chain:{ *:[v4i32] } 2432:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VHCADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot)
29618        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29619        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29620        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29621        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHCADDs32,
29622        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29623        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29624        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29625        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29626        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29627        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29628        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29629        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29630        GIR_EraseFromParent, /*InsnID*/0,
29631        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29632        // GIR_Coverage, 4649,
29633        GIR_Done,
29634      // Label 1518: @78043
29635      GIM_Try, /*On fail goto*//*Label 1519*/ 78126, // Rule ID 3131 //
29636        GIM_CheckFeatures, GIFBS_HasMVEInt,
29637        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav,
29638        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
29639        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29640        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29641        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
29642        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v16s8,
29643        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
29644        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
29645        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
29646        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
29647        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
29648        // (intrinsic_wo_chain:{ *:[i32] } 2425:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VABAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
29649        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVs8,
29650        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda
29651        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
29652        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29653        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29654        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29655        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29656        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29657        GIR_EraseFromParent, /*InsnID*/0,
29658        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29659        // GIR_Coverage, 3131,
29660        GIR_Done,
29661      // Label 1519: @78126
29662      GIM_Try, /*On fail goto*//*Label 1520*/ 78209, // Rule ID 3133 //
29663        GIM_CheckFeatures, GIFBS_HasMVEInt,
29664        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav,
29665        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
29666        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29667        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29668        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
29669        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
29670        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
29671        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
29672        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
29673        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
29674        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
29675        // (intrinsic_wo_chain:{ *:[i32] } 2425:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VABAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
29676        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVs16,
29677        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda
29678        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
29679        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29680        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29681        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29682        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29683        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29684        GIR_EraseFromParent, /*InsnID*/0,
29685        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29686        // GIR_Coverage, 3133,
29687        GIR_Done,
29688      // Label 1520: @78209
29689      GIM_Try, /*On fail goto*//*Label 1521*/ 78292, // Rule ID 3135 //
29690        GIM_CheckFeatures, GIFBS_HasMVEInt,
29691        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav,
29692        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
29693        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29694        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29695        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
29696        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
29697        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
29698        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
29699        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
29700        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
29701        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
29702        // (intrinsic_wo_chain:{ *:[i32] } 2425:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VABAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
29703        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVs32,
29704        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda
29705        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
29706        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29707        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29708        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29709        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29710        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29711        GIR_EraseFromParent, /*InsnID*/0,
29712        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29713        // GIR_Coverage, 3135,
29714        GIR_Done,
29715      // Label 1521: @78292
29716      GIM_Try, /*On fail goto*//*Label 1522*/ 78375, // Rule ID 3137 //
29717        GIM_CheckFeatures, GIFBS_HasMVEInt,
29718        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav,
29719        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
29720        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29721        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29722        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
29723        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v16s8,
29724        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
29725        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
29726        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
29727        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
29728        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
29729        // (intrinsic_wo_chain:{ *:[i32] } 2425:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VABAVu8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
29730        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVu8,
29731        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda
29732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
29733        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29734        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29735        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29736        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29737        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29738        GIR_EraseFromParent, /*InsnID*/0,
29739        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29740        // GIR_Coverage, 3137,
29741        GIR_Done,
29742      // Label 1522: @78375
29743      GIM_Try, /*On fail goto*//*Label 1523*/ 78458, // Rule ID 3139 //
29744        GIM_CheckFeatures, GIFBS_HasMVEInt,
29745        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav,
29746        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
29747        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29748        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29749        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
29750        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
29751        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
29752        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
29753        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
29754        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
29755        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
29756        // (intrinsic_wo_chain:{ *:[i32] } 2425:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VABAVu16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
29757        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVu16,
29758        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda
29759        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
29760        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29762        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29763        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29764        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29765        GIR_EraseFromParent, /*InsnID*/0,
29766        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29767        // GIR_Coverage, 3139,
29768        GIR_Done,
29769      // Label 1523: @78458
29770      GIM_Try, /*On fail goto*//*Label 1524*/ 78541, // Rule ID 3141 //
29771        GIM_CheckFeatures, GIFBS_HasMVEInt,
29772        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav,
29773        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
29774        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29775        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29776        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
29777        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
29778        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
29779        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
29780        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
29781        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
29782        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
29783        // (intrinsic_wo_chain:{ *:[i32] } 2425:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VABAVu32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
29784        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVu32,
29785        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda
29786        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
29787        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29788        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29789        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29790        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29791        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29792        GIR_EraseFromParent, /*InsnID*/0,
29793        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29794        // GIR_Coverage, 3141,
29795        GIR_Done,
29796      // Label 1524: @78541
29797      GIM_Try, /*On fail goto*//*Label 1525*/ 78632, // Rule ID 4096 //
29798        GIM_CheckFeatures, GIFBS_HasMVEFloat,
29799        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcmlaq,
29800        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29801        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29802        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29803        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
29804        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
29805        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29806        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
29807        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29808        // MIs[1] Operand 1
29809        // No operand predicates
29810        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29811        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
29812        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
29813        GIM_CheckIsSafeToFold, /*InsnID*/1,
29814        // (intrinsic_wo_chain:{ *:[v8f16] } 2435:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm)  =>  (MVE_VCMLAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
29815        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMLAf16,
29816        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29817        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qd_src
29818        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29819        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29820        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29821        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29822        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29823        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29824        GIR_EraseFromParent, /*InsnID*/0,
29825        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29826        // GIR_Coverage, 4096,
29827        GIR_Done,
29828      // Label 1525: @78632
29829      GIM_Try, /*On fail goto*//*Label 1526*/ 78723, // Rule ID 4098 //
29830        GIM_CheckFeatures, GIFBS_HasMVEFloat,
29831        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcmlaq,
29832        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29833        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
29834        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29835        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
29836        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
29837        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29838        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
29839        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
29840        // MIs[1] Operand 1
29841        // No operand predicates
29842        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29843        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
29844        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
29845        GIM_CheckIsSafeToFold, /*InsnID*/1,
29846        // (intrinsic_wo_chain:{ *:[v4f32] } 2435:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm)  =>  (MVE_VCMLAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
29847        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMLAf32,
29848        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29849        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qd_src
29850        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
29851        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
29852        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29853        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29854        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29855        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29856        GIR_EraseFromParent, /*InsnID*/0,
29857        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29858        // GIR_Coverage, 4098,
29859        GIR_Done,
29860      // Label 1526: @78723
29861      GIM_Try, /*On fail goto*//*Label 1527*/ 78822, // Rule ID 2703 //
29862        GIM_CheckFeatures, GIFBS_HasNEON,
29863        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbx2,
29864        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
29865        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
29866        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
29867        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
29868        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8,
29869        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
29870        // (intrinsic_wo_chain:{ *:[v8i8] } 2691:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vm)  =>  (VTBX2:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v16i8] } DPair:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
29871        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
29872        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE,
29873        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
29874        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
29875        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1,
29876        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
29877        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2,
29878        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, ARM::DPairRegClassID,
29879        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, ARM::DPRRegClassID,
29880        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, ARM::DPRRegClassID,
29881        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBX2,
29882        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
29883        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // orig
29884        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29885        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Vm
29886        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
29887        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29888        GIR_EraseFromParent, /*InsnID*/0,
29889        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29890        // GIR_Coverage, 2703,
29891        GIR_Done,
29892      // Label 1527: @78822
29893      GIM_Try, /*On fail goto*//*Label 1528*/ 78951, // Rule ID 2704 //
29894        GIM_CheckFeatures, GIFBS_HasNEON,
29895        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbl3,
29896        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
29897        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
29898        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
29899        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
29900        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8,
29901        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
29902        // (intrinsic_wo_chain:{ *:[v8i8] } 2688:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm)  =>  (VTBL3Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
29903        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
29904        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8,
29905        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29906        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
29907        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
29908        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE,
29909        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
29910        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0
29911        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1,
29912        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1
29913        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2,
29914        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2
29915        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/3,
29916        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
29917        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/4,
29918        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, ARM::QQPRRegClassID,
29919        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, ARM::DPRRegClassID,
29920        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, ARM::DPRRegClassID,
29921        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, ARM::DPRRegClassID,
29922        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, ARM::DPRRegClassID,
29923        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBL3Pseudo,
29924        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
29925        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29926        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Vm
29927        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
29928        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29929        GIR_EraseFromParent, /*InsnID*/0,
29930        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29931        // GIR_Coverage, 2704,
29932        GIR_Done,
29933      // Label 1528: @78951
29934      GIM_Reject,
29935    // Label 1490: @78952
29936    GIM_Try, /*On fail goto*//*Label 1529*/ 84652,
29937      GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
29938      GIM_Try, /*On fail goto*//*Label 1530*/ 79056, // Rule ID 3950 //
29939        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29940        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29941        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29942        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
29943        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29944        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29945        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29946        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29947        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29948        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29949        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29950        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29951        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
29952        // (intrinsic_wo_chain:{ *:[v16i8] } 2530:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29953        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29954        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29955        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29956        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecs8,
29957        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29958        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29959        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29960        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29961        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29962        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29963        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29964        GIR_EraseFromParent, /*InsnID*/0,
29965        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29966        // GIR_Coverage, 3950,
29967        GIR_Done,
29968      // Label 1530: @79056
29969      GIM_Try, /*On fail goto*//*Label 1531*/ 79155, // Rule ID 3952 //
29970        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29971        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29972        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29973        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29974        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29975        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29976        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29977        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29978        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29979        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29980        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29981        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29982        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
29983        // (intrinsic_wo_chain:{ *:[v8i16] } 2530:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29984        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29985        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29986        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29987        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecs16,
29988        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29989        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29990        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29991        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29992        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29993        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29994        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29995        GIR_EraseFromParent, /*InsnID*/0,
29996        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29997        // GIR_Coverage, 3952,
29998        GIR_Done,
29999      // Label 1531: @79155
30000      GIM_Try, /*On fail goto*//*Label 1532*/ 79254, // Rule ID 3954 //
30001        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
30002        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30003        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30004        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30005        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30006        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30007        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30008        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30009        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30010        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30011        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30012        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30013        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30014        // (intrinsic_wo_chain:{ *:[v4i32] } 2530:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30015        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30016        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30017        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
30018        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecs32,
30019        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30020        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30021        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30022        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30023        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30024        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30025        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30026        GIR_EraseFromParent, /*InsnID*/0,
30027        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30028        // GIR_Coverage, 3954,
30029        GIR_Done,
30030      // Label 1532: @79254
30031      GIM_Try, /*On fail goto*//*Label 1533*/ 79353, // Rule ID 3956 //
30032        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
30033        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30034        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30035        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
30036        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30037        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30038        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30039        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30040        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30041        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30042        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30043        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30044        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30045        // (intrinsic_wo_chain:{ *:[v16i8] } 2530:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30046        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30047        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30048        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
30049        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecu8,
30050        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30051        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30052        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30053        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30054        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30055        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30056        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30057        GIR_EraseFromParent, /*InsnID*/0,
30058        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30059        // GIR_Coverage, 3956,
30060        GIR_Done,
30061      // Label 1533: @79353
30062      GIM_Try, /*On fail goto*//*Label 1534*/ 79452, // Rule ID 3958 //
30063        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
30064        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30065        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30066        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30067        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30068        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30069        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30070        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30071        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30072        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30073        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30074        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30075        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30076        // (intrinsic_wo_chain:{ *:[v8i16] } 2530:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30077        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30078        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30079        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
30080        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecu16,
30081        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30082        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30083        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30084        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30085        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30086        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30087        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30088        GIR_EraseFromParent, /*InsnID*/0,
30089        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30090        // GIR_Coverage, 3958,
30091        GIR_Done,
30092      // Label 1534: @79452
30093      GIM_Try, /*On fail goto*//*Label 1535*/ 79551, // Rule ID 3960 //
30094        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
30095        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30096        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30097        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30098        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30099        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30100        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30101        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30102        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30103        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30104        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30105        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30106        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30107        // (intrinsic_wo_chain:{ *:[v4i32] } 2530:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30108        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30109        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30110        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
30111        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecu32,
30112        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30113        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30114        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30115        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30116        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30117        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30118        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30119        GIR_EraseFromParent, /*InsnID*/0,
30120        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30121        // GIR_Coverage, 3960,
30122        GIR_Done,
30123      // Label 1535: @79551
30124      GIM_Try, /*On fail goto*//*Label 1536*/ 79650, // Rule ID 3962 //
30125        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
30126        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30127        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30128        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
30129        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30130        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30131        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30132        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30133        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30134        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30135        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30136        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30137        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30138        // (intrinsic_wo_chain:{ *:[v16i8] } 2530:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30139        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30140        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30141        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
30142        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecs8,
30143        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30144        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30145        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30146        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30147        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30148        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30149        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30150        GIR_EraseFromParent, /*InsnID*/0,
30151        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30152        // GIR_Coverage, 3962,
30153        GIR_Done,
30154      // Label 1536: @79650
30155      GIM_Try, /*On fail goto*//*Label 1537*/ 79749, // Rule ID 3964 //
30156        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
30157        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30158        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30159        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30160        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30161        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30162        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30163        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30164        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30165        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30166        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30167        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30168        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30169        // (intrinsic_wo_chain:{ *:[v8i16] } 2530:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30170        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30171        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30172        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
30173        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecs16,
30174        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30175        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30176        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30177        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30178        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30179        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30180        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30181        GIR_EraseFromParent, /*InsnID*/0,
30182        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30183        // GIR_Coverage, 3964,
30184        GIR_Done,
30185      // Label 1537: @79749
30186      GIM_Try, /*On fail goto*//*Label 1538*/ 79848, // Rule ID 3966 //
30187        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
30188        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30189        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30190        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30191        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30192        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30193        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30194        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30195        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30196        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30197        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30198        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30199        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30200        // (intrinsic_wo_chain:{ *:[v4i32] } 2530:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30201        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30202        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30203        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
30204        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecs32,
30205        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30206        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30207        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30208        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30209        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30210        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30211        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30212        GIR_EraseFromParent, /*InsnID*/0,
30213        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30214        // GIR_Coverage, 3966,
30215        GIR_Done,
30216      // Label 1538: @79848
30217      GIM_Try, /*On fail goto*//*Label 1539*/ 79947, // Rule ID 3968 //
30218        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
30219        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30220        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30221        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
30222        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30223        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30224        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30225        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30226        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30227        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30228        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30229        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30230        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30231        // (intrinsic_wo_chain:{ *:[v16i8] } 2530:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30232        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30233        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30234        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
30235        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecu8,
30236        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30237        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30238        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30239        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30240        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30241        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30242        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30243        GIR_EraseFromParent, /*InsnID*/0,
30244        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30245        // GIR_Coverage, 3968,
30246        GIR_Done,
30247      // Label 1539: @79947
30248      GIM_Try, /*On fail goto*//*Label 1540*/ 80046, // Rule ID 3970 //
30249        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
30250        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30251        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30252        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30253        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30254        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30255        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30256        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30257        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30258        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30259        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30260        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30261        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30262        // (intrinsic_wo_chain:{ *:[v8i16] } 2530:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30263        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30264        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30265        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
30266        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecu16,
30267        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30268        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30269        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30270        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30271        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30272        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30273        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30274        GIR_EraseFromParent, /*InsnID*/0,
30275        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30276        // GIR_Coverage, 3970,
30277        GIR_Done,
30278      // Label 1540: @80046
30279      GIM_Try, /*On fail goto*//*Label 1541*/ 80145, // Rule ID 3972 //
30280        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
30281        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30282        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30283        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30284        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30285        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30286        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30287        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30288        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30289        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30290        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30291        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30292        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30293        // (intrinsic_wo_chain:{ *:[v4i32] } 2530:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30294        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30295        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30296        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
30297        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecu32,
30298        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30299        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30300        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30301        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30302        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30303        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30304        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30305        GIR_EraseFromParent, /*InsnID*/0,
30306        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30307        // GIR_Coverage, 3972,
30308        GIR_Done,
30309      // Label 1541: @80145
30310      GIM_Try, /*On fail goto*//*Label 1542*/ 80244, // Rule ID 3974 //
30311        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
30312        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30313        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30314        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
30315        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30316        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30317        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30318        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30319        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30320        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30321        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30322        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30323        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30324        // (intrinsic_wo_chain:{ *:[v16i8] } 2530:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30325        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30326        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30327        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
30328        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecs8,
30329        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30330        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30331        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30332        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30333        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30334        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30335        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30336        GIR_EraseFromParent, /*InsnID*/0,
30337        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30338        // GIR_Coverage, 3974,
30339        GIR_Done,
30340      // Label 1542: @80244
30341      GIM_Try, /*On fail goto*//*Label 1543*/ 80343, // Rule ID 3976 //
30342        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
30343        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30344        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30345        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30346        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30347        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30348        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30349        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30350        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30351        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30352        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30353        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30354        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30355        // (intrinsic_wo_chain:{ *:[v8i16] } 2530:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30356        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30357        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30358        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
30359        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecs16,
30360        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30361        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30362        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30363        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30364        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30365        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30366        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30367        GIR_EraseFromParent, /*InsnID*/0,
30368        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30369        // GIR_Coverage, 3976,
30370        GIR_Done,
30371      // Label 1543: @80343
30372      GIM_Try, /*On fail goto*//*Label 1544*/ 80442, // Rule ID 3978 //
30373        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
30374        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30375        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30376        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30377        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30378        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30379        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30380        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30381        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30382        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30383        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30384        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30385        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30386        // (intrinsic_wo_chain:{ *:[v4i32] } 2530:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30387        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30388        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30389        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
30390        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecs32,
30391        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30392        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30393        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30394        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30395        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30396        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30397        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30398        GIR_EraseFromParent, /*InsnID*/0,
30399        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30400        // GIR_Coverage, 3978,
30401        GIR_Done,
30402      // Label 1544: @80442
30403      GIM_Try, /*On fail goto*//*Label 1545*/ 80541, // Rule ID 3980 //
30404        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
30405        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30406        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30407        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
30408        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30409        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30410        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30411        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30412        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30413        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30414        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30415        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30416        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30417        // (intrinsic_wo_chain:{ *:[v16i8] } 2530:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30418        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30419        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30420        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
30421        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecu8,
30422        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30423        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30424        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30425        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30426        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30427        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30428        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30429        GIR_EraseFromParent, /*InsnID*/0,
30430        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30431        // GIR_Coverage, 3980,
30432        GIR_Done,
30433      // Label 1545: @80541
30434      GIM_Try, /*On fail goto*//*Label 1546*/ 80640, // Rule ID 3982 //
30435        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
30436        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30437        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30438        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30439        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30440        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30441        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30442        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30443        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30444        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30445        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30446        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30447        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30448        // (intrinsic_wo_chain:{ *:[v8i16] } 2530:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30449        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30450        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30451        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
30452        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecu16,
30453        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30454        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30455        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30456        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30457        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30458        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30459        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30460        GIR_EraseFromParent, /*InsnID*/0,
30461        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30462        // GIR_Coverage, 3982,
30463        GIR_Done,
30464      // Label 1546: @80640
30465      GIM_Try, /*On fail goto*//*Label 1547*/ 80739, // Rule ID 3984 //
30466        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
30467        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30468        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30469        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30470        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30471        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30472        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30473        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30474        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30475        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30476        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30477        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30478        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30479        // (intrinsic_wo_chain:{ *:[v4i32] } 2530:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30480        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30481        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30482        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
30483        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecu32,
30484        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30485        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30486        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30487        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30488        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30489        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30490        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30491        GIR_EraseFromParent, /*InsnID*/0,
30492        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30493        // GIR_Coverage, 3984,
30494        GIR_Done,
30495      // Label 1547: @80739
30496      GIM_Try, /*On fail goto*//*Label 1548*/ 80838, // Rule ID 3986 //
30497        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
30498        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30499        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30500        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
30501        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30502        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30503        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30504        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30505        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30506        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30507        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30508        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30509        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30510        // (intrinsic_wo_chain:{ *:[v16i8] } 2530:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30511        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30512        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30513        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
30514        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecs8,
30515        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30516        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30517        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30518        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30519        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30520        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30521        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30522        GIR_EraseFromParent, /*InsnID*/0,
30523        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30524        // GIR_Coverage, 3986,
30525        GIR_Done,
30526      // Label 1548: @80838
30527      GIM_Try, /*On fail goto*//*Label 1549*/ 80937, // Rule ID 3988 //
30528        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
30529        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30530        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30531        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30532        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30533        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30534        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30535        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30536        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30537        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30538        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30539        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30540        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30541        // (intrinsic_wo_chain:{ *:[v8i16] } 2530:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30542        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30543        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30544        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
30545        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecs16,
30546        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30547        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30548        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30549        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30550        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30551        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30552        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30553        GIR_EraseFromParent, /*InsnID*/0,
30554        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30555        // GIR_Coverage, 3988,
30556        GIR_Done,
30557      // Label 1549: @80937
30558      GIM_Try, /*On fail goto*//*Label 1550*/ 81036, // Rule ID 3990 //
30559        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
30560        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30561        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30562        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30563        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30564        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30565        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30566        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30567        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30568        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30569        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30570        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30571        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30572        // (intrinsic_wo_chain:{ *:[v4i32] } 2530:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30573        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30574        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30575        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
30576        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecs32,
30577        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30578        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30579        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30580        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30581        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30582        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30583        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30584        GIR_EraseFromParent, /*InsnID*/0,
30585        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30586        // GIR_Coverage, 3990,
30587        GIR_Done,
30588      // Label 1550: @81036
30589      GIM_Try, /*On fail goto*//*Label 1551*/ 81135, // Rule ID 3992 //
30590        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
30591        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30592        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30593        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
30594        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30595        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30596        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30597        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30598        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30599        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30600        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30601        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30602        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30603        // (intrinsic_wo_chain:{ *:[v16i8] } 2530:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30604        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30605        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30606        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
30607        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecu8,
30608        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30609        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30610        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30611        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30612        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30613        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30614        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30615        GIR_EraseFromParent, /*InsnID*/0,
30616        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30617        // GIR_Coverage, 3992,
30618        GIR_Done,
30619      // Label 1551: @81135
30620      GIM_Try, /*On fail goto*//*Label 1552*/ 81234, // Rule ID 3994 //
30621        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
30622        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30623        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30624        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30625        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30626        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30627        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30628        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30629        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30630        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30631        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30632        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30633        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30634        // (intrinsic_wo_chain:{ *:[v8i16] } 2530:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30635        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30636        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30637        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
30638        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecu16,
30639        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30640        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30641        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30642        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30643        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30644        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30645        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30646        GIR_EraseFromParent, /*InsnID*/0,
30647        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30648        // GIR_Coverage, 3994,
30649        GIR_Done,
30650      // Label 1552: @81234
30651      GIM_Try, /*On fail goto*//*Label 1553*/ 81333, // Rule ID 3996 //
30652        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
30653        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30654        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30655        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30656        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30657        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30658        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30659        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30660        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30661        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30662        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30663        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30664        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30665        // (intrinsic_wo_chain:{ *:[v4i32] } 2530:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30666        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30667        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30668        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
30669        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecu32,
30670        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30671        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30672        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30673        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30674        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30675        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30676        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30677        GIR_EraseFromParent, /*InsnID*/0,
30678        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30679        // GIR_Coverage, 3996,
30680        GIR_Done,
30681      // Label 1553: @81333
30682      GIM_Try, /*On fail goto*//*Label 1554*/ 81418, // Rule ID 4587 //
30683        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
30684        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30685        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30686        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30687        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30688        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30689        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30690        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30691        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30692        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30693        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30694        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30695        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30696        // (intrinsic_wo_chain:{ *:[v8i16] } 2500:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQMOVNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30697        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVNs32bh,
30698        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30699        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30700        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30701        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30702        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30703        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30704        GIR_EraseFromParent, /*InsnID*/0,
30705        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30706        // GIR_Coverage, 4587,
30707        GIR_Done,
30708      // Label 1554: @81418
30709      GIM_Try, /*On fail goto*//*Label 1555*/ 81503, // Rule ID 4589 //
30710        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
30711        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30712        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30713        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30714        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30715        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30716        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30717        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30718        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30719        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30720        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30721        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30722        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30723        // (intrinsic_wo_chain:{ *:[v8i16] } 2500:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQMOVNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30724        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVNs32th,
30725        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30726        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30727        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30728        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30729        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30730        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30731        GIR_EraseFromParent, /*InsnID*/0,
30732        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30733        // GIR_Coverage, 4589,
30734        GIR_Done,
30735      // Label 1555: @81503
30736      GIM_Try, /*On fail goto*//*Label 1556*/ 81588, // Rule ID 4591 //
30737        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
30738        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30739        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30740        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30741        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30742        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30743        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30744        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30745        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30746        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30747        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30748        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30749        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30750        // (intrinsic_wo_chain:{ *:[v16i8] } 2500:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQMOVNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
30751        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVNs16bh,
30752        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30753        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30754        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30755        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30756        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30757        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30758        GIR_EraseFromParent, /*InsnID*/0,
30759        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30760        // GIR_Coverage, 4591,
30761        GIR_Done,
30762      // Label 1556: @81588
30763      GIM_Try, /*On fail goto*//*Label 1557*/ 81673, // Rule ID 4593 //
30764        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
30765        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30766        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30767        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30768        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30769        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30770        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30771        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30772        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30773        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30774        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30775        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30776        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30777        // (intrinsic_wo_chain:{ *:[v16i8] } 2500:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQMOVNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
30778        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVNs16th,
30779        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30780        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30781        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30782        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30783        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30784        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30785        GIR_EraseFromParent, /*InsnID*/0,
30786        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30787        // GIR_Coverage, 4593,
30788        GIR_Done,
30789      // Label 1557: @81673
30790      GIM_Try, /*On fail goto*//*Label 1558*/ 81758, // Rule ID 4595 //
30791        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
30792        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30793        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30794        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30795        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30796        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30797        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30798        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30799        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30800        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30801        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30802        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30803        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30804        // (intrinsic_wo_chain:{ *:[v8i16] } 2500:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQMOVNu32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30805        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVNu32bh,
30806        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30807        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30808        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30809        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30810        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30811        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30812        GIR_EraseFromParent, /*InsnID*/0,
30813        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30814        // GIR_Coverage, 4595,
30815        GIR_Done,
30816      // Label 1558: @81758
30817      GIM_Try, /*On fail goto*//*Label 1559*/ 81843, // Rule ID 4597 //
30818        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
30819        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30820        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30821        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30822        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30823        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30824        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30825        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30826        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30827        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30828        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30829        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30830        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30831        // (intrinsic_wo_chain:{ *:[v8i16] } 2500:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQMOVNu32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30832        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVNu32th,
30833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30834        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30835        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30836        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30837        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30838        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30839        GIR_EraseFromParent, /*InsnID*/0,
30840        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30841        // GIR_Coverage, 4597,
30842        GIR_Done,
30843      // Label 1559: @81843
30844      GIM_Try, /*On fail goto*//*Label 1560*/ 81928, // Rule ID 4599 //
30845        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
30846        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30847        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30848        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30849        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30850        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30851        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30852        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30853        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30854        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30855        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30856        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30857        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30858        // (intrinsic_wo_chain:{ *:[v16i8] } 2500:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQMOVNu16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
30859        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVNu16bh,
30860        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30861        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30862        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30863        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30864        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30865        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30866        GIR_EraseFromParent, /*InsnID*/0,
30867        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30868        // GIR_Coverage, 4599,
30869        GIR_Done,
30870      // Label 1560: @81928
30871      GIM_Try, /*On fail goto*//*Label 1561*/ 82013, // Rule ID 4601 //
30872        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
30873        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30874        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30875        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30876        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30877        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30878        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30879        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30880        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30881        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30882        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30883        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30884        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30885        // (intrinsic_wo_chain:{ *:[v16i8] } 2500:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQMOVNu16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
30886        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVNu16th,
30887        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30888        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30889        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30890        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30891        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30892        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30893        GIR_EraseFromParent, /*InsnID*/0,
30894        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30895        // GIR_Coverage, 4601,
30896        GIR_Done,
30897      // Label 1561: @82013
30898      GIM_Try, /*On fail goto*//*Label 1562*/ 82098, // Rule ID 4603 //
30899        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
30900        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30901        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30902        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30903        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30904        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30905        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30906        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30907        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30908        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30909        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30910        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30911        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30912        // (intrinsic_wo_chain:{ *:[v8i16] } 2500:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQMOVUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30913        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVUNs32bh,
30914        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30915        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30916        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30917        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30918        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30919        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30920        GIR_EraseFromParent, /*InsnID*/0,
30921        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30922        // GIR_Coverage, 4603,
30923        GIR_Done,
30924      // Label 1562: @82098
30925      GIM_Try, /*On fail goto*//*Label 1563*/ 82183, // Rule ID 4605 //
30926        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
30927        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30928        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30929        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
30930        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30931        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30932        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30933        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30934        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30935        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30936        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30937        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30938        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30939        // (intrinsic_wo_chain:{ *:[v8i16] } 2500:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQMOVUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30940        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVUNs32th,
30941        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30942        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30943        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30944        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30945        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30946        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30947        GIR_EraseFromParent, /*InsnID*/0,
30948        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30949        // GIR_Coverage, 4605,
30950        GIR_Done,
30951      // Label 1563: @82183
30952      GIM_Try, /*On fail goto*//*Label 1564*/ 82268, // Rule ID 4607 //
30953        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
30954        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30955        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30956        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30957        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30958        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30959        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30960        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30961        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30962        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30963        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30964        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30965        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30966        // (intrinsic_wo_chain:{ *:[v16i8] } 2500:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQMOVUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
30967        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVUNs16bh,
30968        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30969        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30970        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30971        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30972        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30973        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30974        GIR_EraseFromParent, /*InsnID*/0,
30975        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30976        // GIR_Coverage, 4607,
30977        GIR_Done,
30978      // Label 1564: @82268
30979      GIM_Try, /*On fail goto*//*Label 1565*/ 82353, // Rule ID 4609 //
30980        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
30981        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30982        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30983        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
30984        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30985        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30986        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30987        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30988        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30989        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
30990        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30991        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30992        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30993        // (intrinsic_wo_chain:{ *:[v16i8] } 2500:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQMOVUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
30994        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVUNs16th,
30995        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30996        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
30997        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
30998        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30999        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31000        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31001        GIR_EraseFromParent, /*InsnID*/0,
31002        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31003        // GIR_Coverage, 4609,
31004        GIR_Done,
31005      // Label 1565: @82353
31006      GIM_Try, /*On fail goto*//*Label 1566*/ 82438, // Rule ID 4799 //
31007        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31008        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31009        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
31010        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31011        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31012        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31013        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31014        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31015        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31016        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31017        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31018        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31019        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31020        // (intrinsic_wo_chain:{ *:[v16i8] } 2528:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31021        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qrs8,
31022        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31023        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31024        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31025        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31026        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31027        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31028        GIR_EraseFromParent, /*InsnID*/0,
31029        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31030        // GIR_Coverage, 4799,
31031        GIR_Done,
31032      // Label 1566: @82438
31033      GIM_Try, /*On fail goto*//*Label 1567*/ 82523, // Rule ID 4801 //
31034        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31035        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31036        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
31037        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31038        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31039        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31040        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31041        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31042        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31043        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31044        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31045        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31046        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31047        // (intrinsic_wo_chain:{ *:[v8i16] } 2528:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31048        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qrs16,
31049        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31050        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31051        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31052        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31053        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31054        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31055        GIR_EraseFromParent, /*InsnID*/0,
31056        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31057        // GIR_Coverage, 4801,
31058        GIR_Done,
31059      // Label 1567: @82523
31060      GIM_Try, /*On fail goto*//*Label 1568*/ 82608, // Rule ID 4803 //
31061        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31062        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31063        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
31064        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31065        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31066        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31067        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31068        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31069        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31070        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31071        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31072        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31073        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31074        // (intrinsic_wo_chain:{ *:[v4i32] } 2528:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31075        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qrs32,
31076        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31077        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31078        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31079        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31080        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31081        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31082        GIR_EraseFromParent, /*InsnID*/0,
31083        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31084        // GIR_Coverage, 4803,
31085        GIR_Done,
31086      // Label 1568: @82608
31087      GIM_Try, /*On fail goto*//*Label 1569*/ 82693, // Rule ID 4805 //
31088        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31089        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31090        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
31091        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31092        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31093        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31094        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31095        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31096        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31097        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31098        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31099        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31100        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31101        // (intrinsic_wo_chain:{ *:[v16i8] } 2528:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31102        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qru8,
31103        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31104        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31106        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31107        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31108        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31109        GIR_EraseFromParent, /*InsnID*/0,
31110        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31111        // GIR_Coverage, 4805,
31112        GIR_Done,
31113      // Label 1569: @82693
31114      GIM_Try, /*On fail goto*//*Label 1570*/ 82778, // Rule ID 4807 //
31115        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31116        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31117        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
31118        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31119        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31120        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31121        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31122        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31123        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31124        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31125        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31126        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31127        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31128        // (intrinsic_wo_chain:{ *:[v8i16] } 2528:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31129        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qru16,
31130        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31132        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31133        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31134        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31135        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31136        GIR_EraseFromParent, /*InsnID*/0,
31137        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31138        // GIR_Coverage, 4807,
31139        GIR_Done,
31140      // Label 1570: @82778
31141      GIM_Try, /*On fail goto*//*Label 1571*/ 82863, // Rule ID 4809 //
31142        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31143        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31144        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
31145        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31146        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31147        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31148        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31149        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31150        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31151        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31152        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31153        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31154        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31155        // (intrinsic_wo_chain:{ *:[v4i32] } 2528:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31156        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qru32,
31157        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31158        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31159        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31160        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31161        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31162        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31163        GIR_EraseFromParent, /*InsnID*/0,
31164        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31165        // GIR_Coverage, 4809,
31166        GIR_Done,
31167      // Label 1571: @82863
31168      GIM_Try, /*On fail goto*//*Label 1572*/ 82948, // Rule ID 4811 //
31169        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31170        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31171        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
31172        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31173        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31174        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31175        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31176        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31177        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31178        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31179        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31180        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31181        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31182        // (intrinsic_wo_chain:{ *:[v16i8] } 2528:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31183        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qrs8,
31184        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31185        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31186        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31187        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31188        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31189        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31190        GIR_EraseFromParent, /*InsnID*/0,
31191        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31192        // GIR_Coverage, 4811,
31193        GIR_Done,
31194      // Label 1572: @82948
31195      GIM_Try, /*On fail goto*//*Label 1573*/ 83033, // Rule ID 4813 //
31196        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31197        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31198        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
31199        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31200        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31201        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31202        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31203        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31204        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31205        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31206        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31207        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31208        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31209        // (intrinsic_wo_chain:{ *:[v8i16] } 2528:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31210        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qrs16,
31211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31212        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31213        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31214        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31215        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31216        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31217        GIR_EraseFromParent, /*InsnID*/0,
31218        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31219        // GIR_Coverage, 4813,
31220        GIR_Done,
31221      // Label 1573: @83033
31222      GIM_Try, /*On fail goto*//*Label 1574*/ 83118, // Rule ID 4815 //
31223        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31224        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31225        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
31226        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31227        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31228        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31229        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31230        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31231        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31232        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31233        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31234        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31235        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31236        // (intrinsic_wo_chain:{ *:[v4i32] } 2528:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31237        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qrs32,
31238        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31239        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31240        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31241        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31242        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31243        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31244        GIR_EraseFromParent, /*InsnID*/0,
31245        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31246        // GIR_Coverage, 4815,
31247        GIR_Done,
31248      // Label 1574: @83118
31249      GIM_Try, /*On fail goto*//*Label 1575*/ 83203, // Rule ID 4817 //
31250        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31251        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31252        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
31253        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31254        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31255        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31256        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31257        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31258        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31259        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31260        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31261        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31262        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31263        // (intrinsic_wo_chain:{ *:[v16i8] } 2528:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31264        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qru8,
31265        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31266        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31267        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31268        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31269        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31270        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31271        GIR_EraseFromParent, /*InsnID*/0,
31272        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31273        // GIR_Coverage, 4817,
31274        GIR_Done,
31275      // Label 1575: @83203
31276      GIM_Try, /*On fail goto*//*Label 1576*/ 83288, // Rule ID 4819 //
31277        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31278        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31279        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
31280        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31281        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31282        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31283        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31284        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31285        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31286        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31287        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31288        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31289        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31290        // (intrinsic_wo_chain:{ *:[v8i16] } 2528:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31291        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qru16,
31292        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31293        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31294        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31295        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31296        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31297        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31298        GIR_EraseFromParent, /*InsnID*/0,
31299        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31300        // GIR_Coverage, 4819,
31301        GIR_Done,
31302      // Label 1576: @83288
31303      GIM_Try, /*On fail goto*//*Label 1577*/ 83373, // Rule ID 4821 //
31304        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31305        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31306        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
31307        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31308        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31309        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31310        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31311        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31312        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31313        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31314        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31315        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31316        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31317        // (intrinsic_wo_chain:{ *:[v4i32] } 2528:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31318        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qru32,
31319        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31322        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31323        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31324        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31325        GIR_EraseFromParent, /*InsnID*/0,
31326        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31327        // GIR_Coverage, 4821,
31328        GIR_Done,
31329      // Label 1577: @83373
31330      GIM_Try, /*On fail goto*//*Label 1578*/ 83458, // Rule ID 4823 //
31331        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31332        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31333        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
31334        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31335        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31336        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31337        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31338        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31339        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31340        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31341        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31342        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31343        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31344        // (intrinsic_wo_chain:{ *:[v16i8] } 2528:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31345        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qrs8,
31346        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31347        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31348        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31349        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31350        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31351        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31352        GIR_EraseFromParent, /*InsnID*/0,
31353        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31354        // GIR_Coverage, 4823,
31355        GIR_Done,
31356      // Label 1578: @83458
31357      GIM_Try, /*On fail goto*//*Label 1579*/ 83543, // Rule ID 4825 //
31358        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31359        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31360        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
31361        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31362        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31363        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31364        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31365        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31366        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31367        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31368        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31369        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31370        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31371        // (intrinsic_wo_chain:{ *:[v8i16] } 2528:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31372        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qrs16,
31373        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31374        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31375        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31376        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31377        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31378        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31379        GIR_EraseFromParent, /*InsnID*/0,
31380        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31381        // GIR_Coverage, 4825,
31382        GIR_Done,
31383      // Label 1579: @83543
31384      GIM_Try, /*On fail goto*//*Label 1580*/ 83628, // Rule ID 4827 //
31385        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31386        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31387        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
31388        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31389        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31390        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31391        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31392        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31393        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31394        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31395        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31396        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31397        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31398        // (intrinsic_wo_chain:{ *:[v4i32] } 2528:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31399        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qrs32,
31400        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31401        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31402        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31403        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31404        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31405        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31406        GIR_EraseFromParent, /*InsnID*/0,
31407        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31408        // GIR_Coverage, 4827,
31409        GIR_Done,
31410      // Label 1580: @83628
31411      GIM_Try, /*On fail goto*//*Label 1581*/ 83713, // Rule ID 4829 //
31412        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31413        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31414        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
31415        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31416        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31417        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31418        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31419        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31420        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31421        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31422        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31423        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31424        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31425        // (intrinsic_wo_chain:{ *:[v16i8] } 2528:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31426        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qru8,
31427        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31428        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31429        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31430        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31431        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31432        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31433        GIR_EraseFromParent, /*InsnID*/0,
31434        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31435        // GIR_Coverage, 4829,
31436        GIR_Done,
31437      // Label 1581: @83713
31438      GIM_Try, /*On fail goto*//*Label 1582*/ 83798, // Rule ID 4831 //
31439        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31440        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31441        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
31442        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31443        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31444        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31445        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31446        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31447        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31448        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31449        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31450        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31451        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31452        // (intrinsic_wo_chain:{ *:[v8i16] } 2528:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31453        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qru16,
31454        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31455        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31456        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31457        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31458        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31459        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31460        GIR_EraseFromParent, /*InsnID*/0,
31461        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31462        // GIR_Coverage, 4831,
31463        GIR_Done,
31464      // Label 1582: @83798
31465      GIM_Try, /*On fail goto*//*Label 1583*/ 83883, // Rule ID 4833 //
31466        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31467        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31468        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
31469        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31470        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31471        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31472        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31473        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31474        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31475        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31476        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31477        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31478        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31479        // (intrinsic_wo_chain:{ *:[v4i32] } 2528:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31480        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qru32,
31481        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31482        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31483        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31484        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31485        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31486        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31487        GIR_EraseFromParent, /*InsnID*/0,
31488        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31489        // GIR_Coverage, 4833,
31490        GIR_Done,
31491      // Label 1583: @83883
31492      GIM_Try, /*On fail goto*//*Label 1584*/ 83968, // Rule ID 4835 //
31493        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31494        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31495        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
31496        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31497        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31498        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31499        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31500        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31501        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31502        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31503        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31504        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31505        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31506        // (intrinsic_wo_chain:{ *:[v16i8] } 2528:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31507        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qrs8,
31508        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31509        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31510        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31511        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31512        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31513        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31514        GIR_EraseFromParent, /*InsnID*/0,
31515        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31516        // GIR_Coverage, 4835,
31517        GIR_Done,
31518      // Label 1584: @83968
31519      GIM_Try, /*On fail goto*//*Label 1585*/ 84053, // Rule ID 4837 //
31520        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31521        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31522        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
31523        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31524        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31525        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31526        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31527        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31528        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31529        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31530        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31531        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31532        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31533        // (intrinsic_wo_chain:{ *:[v8i16] } 2528:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31534        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qrs16,
31535        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31536        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31537        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31538        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31539        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31540        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31541        GIR_EraseFromParent, /*InsnID*/0,
31542        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31543        // GIR_Coverage, 4837,
31544        GIR_Done,
31545      // Label 1585: @84053
31546      GIM_Try, /*On fail goto*//*Label 1586*/ 84138, // Rule ID 4839 //
31547        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31548        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31549        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
31550        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31551        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31552        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31553        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31554        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31555        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31556        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31557        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31558        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31559        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31560        // (intrinsic_wo_chain:{ *:[v4i32] } 2528:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31561        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qrs32,
31562        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31563        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31564        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31565        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31566        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31567        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31568        GIR_EraseFromParent, /*InsnID*/0,
31569        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31570        // GIR_Coverage, 4839,
31571        GIR_Done,
31572      // Label 1586: @84138
31573      GIM_Try, /*On fail goto*//*Label 1587*/ 84223, // Rule ID 4841 //
31574        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31575        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31576        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
31577        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31578        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31579        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31580        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31581        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31582        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31583        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31584        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31585        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31586        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31587        // (intrinsic_wo_chain:{ *:[v16i8] } 2528:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31588        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qru8,
31589        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31590        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31591        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31592        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31593        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31594        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31595        GIR_EraseFromParent, /*InsnID*/0,
31596        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31597        // GIR_Coverage, 4841,
31598        GIR_Done,
31599      // Label 1587: @84223
31600      GIM_Try, /*On fail goto*//*Label 1588*/ 84308, // Rule ID 4843 //
31601        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31602        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31603        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
31604        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31605        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31606        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31607        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31608        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31609        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31610        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31611        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31612        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31613        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31614        // (intrinsic_wo_chain:{ *:[v8i16] } 2528:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31615        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qru16,
31616        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31617        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31618        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31619        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31620        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31621        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31622        GIR_EraseFromParent, /*InsnID*/0,
31623        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31624        // GIR_Coverage, 4843,
31625        GIR_Done,
31626      // Label 1588: @84308
31627      GIM_Try, /*On fail goto*//*Label 1589*/ 84393, // Rule ID 4845 //
31628        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
31629        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31630        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
31631        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31632        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31633        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31634        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31635        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31636        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31637        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
31638        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31639        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31640        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31641        // (intrinsic_wo_chain:{ *:[v4i32] } 2528:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31642        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qru32,
31643        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31644        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
31645        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
31646        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31647        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31648        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31649        GIR_EraseFromParent, /*InsnID*/0,
31650        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31651        // GIR_Coverage, 4845,
31652        GIR_Done,
31653      // Label 1589: @84393
31654      GIM_Try, /*On fail goto*//*Label 1590*/ 84530, // Rule ID 2705 //
31655        GIM_CheckFeatures, GIFBS_HasNEON,
31656        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbx3,
31657        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
31658        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
31659        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
31660        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
31661        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8,
31662        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s8,
31663        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
31664        // (intrinsic_wo_chain:{ *:[v8i8] } 2692:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm)  =>  (VTBX3Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
31665        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
31666        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8,
31667        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
31668        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
31669        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
31670        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE,
31671        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
31672        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
31673        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1,
31674        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
31675        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2,
31676        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2
31677        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/3,
31678        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
31679        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/4,
31680        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, ARM::QQPRRegClassID,
31681        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, ARM::DPRRegClassID,
31682        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, ARM::DPRRegClassID,
31683        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, ARM::DPRRegClassID,
31684        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, ARM::DPRRegClassID,
31685        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBX3Pseudo,
31686        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
31687        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // orig
31688        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
31689        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Vm
31690        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
31691        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31692        GIR_EraseFromParent, /*InsnID*/0,
31693        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31694        // GIR_Coverage, 2705,
31695        GIR_Done,
31696      // Label 1590: @84530
31697      GIM_Try, /*On fail goto*//*Label 1591*/ 84651, // Rule ID 2706 //
31698        GIM_CheckFeatures, GIFBS_HasNEON,
31699        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbl4,
31700        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
31701        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
31702        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
31703        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
31704        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8,
31705        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s8,
31706        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
31707        // (intrinsic_wo_chain:{ *:[v8i8] } 2689:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm)  =>  (VTBL4Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
31708        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
31709        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE,
31710        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
31711        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0
31712        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1,
31713        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1
31714        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2,
31715        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2
31716        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/3,
31717        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn3
31718        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/4,
31719        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, ARM::QQPRRegClassID,
31720        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, ARM::DPRRegClassID,
31721        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, ARM::DPRRegClassID,
31722        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, ARM::DPRRegClassID,
31723        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, ARM::DPRRegClassID,
31724        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBL4Pseudo,
31725        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
31726        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
31727        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Vm
31728        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
31729        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31730        GIR_EraseFromParent, /*InsnID*/0,
31731        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31732        // GIR_Coverage, 2706,
31733        GIR_Done,
31734      // Label 1591: @84651
31735      GIM_Reject,
31736    // Label 1529: @84652
31737    GIM_Try, /*On fail goto*//*Label 1592*/ 90025,
31738      GIM_CheckNumOperands, /*MI*/0, /*Expected*/8,
31739      GIM_Try, /*On fail goto*//*Label 1593*/ 84752, // Rule ID 3275 //
31740        GIM_CheckFeatures, GIFBS_HasMVEInt,
31741        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31742        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31743        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31744        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31745        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31746        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31747        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
31748        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
31749        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31750        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
31751        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
31752        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31753        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31754        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31755        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31756        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLADAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
31757        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVs8,
31758        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31759        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31760        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31761        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31762        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31763        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31764        GIR_EraseFromParent, /*InsnID*/0,
31765        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31766        // GIR_Coverage, 3275,
31767        GIR_Done,
31768      // Label 1593: @84752
31769      GIM_Try, /*On fail goto*//*Label 1594*/ 84847, // Rule ID 3279 //
31770        GIM_CheckFeatures, GIFBS_HasMVEInt,
31771        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31772        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31773        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31774        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31775        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31776        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31777        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
31778        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
31779        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31780        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
31781        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
31782        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31783        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31784        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31785        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31786        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLADAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
31787        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVxs8,
31788        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31789        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31790        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31791        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31792        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31793        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31794        GIR_EraseFromParent, /*InsnID*/0,
31795        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31796        // GIR_Coverage, 3279,
31797        GIR_Done,
31798      // Label 1594: @84847
31799      GIM_Try, /*On fail goto*//*Label 1595*/ 84942, // Rule ID 3283 //
31800        GIM_CheckFeatures, GIFBS_HasMVEInt,
31801        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31802        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31803        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31804        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31805        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31806        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31807        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
31808        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
31809        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31810        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
31811        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
31812        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31813        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31814        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31815        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31816        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLADAVu8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
31817        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVu8,
31818        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31819        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31820        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31821        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31822        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31823        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31824        GIR_EraseFromParent, /*InsnID*/0,
31825        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31826        // GIR_Coverage, 3283,
31827        GIR_Done,
31828      // Label 1595: @84942
31829      GIM_Try, /*On fail goto*//*Label 1596*/ 85037, // Rule ID 3287 //
31830        GIM_CheckFeatures, GIFBS_HasMVEInt,
31831        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31832        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31833        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31834        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31835        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31836        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31837        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
31838        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
31839        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31840        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
31841        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
31842        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31843        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31844        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31845        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31846        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLADAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
31847        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVs16,
31848        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31849        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31850        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31851        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31852        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31853        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31854        GIR_EraseFromParent, /*InsnID*/0,
31855        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31856        // GIR_Coverage, 3287,
31857        GIR_Done,
31858      // Label 1596: @85037
31859      GIM_Try, /*On fail goto*//*Label 1597*/ 85132, // Rule ID 3291 //
31860        GIM_CheckFeatures, GIFBS_HasMVEInt,
31861        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31862        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31863        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31864        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31865        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31866        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31867        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
31868        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
31869        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31870        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
31871        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
31872        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31873        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31874        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31875        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31876        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLADAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
31877        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVxs16,
31878        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31879        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31880        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31881        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31882        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31883        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31884        GIR_EraseFromParent, /*InsnID*/0,
31885        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31886        // GIR_Coverage, 3291,
31887        GIR_Done,
31888      // Label 1597: @85132
31889      GIM_Try, /*On fail goto*//*Label 1598*/ 85227, // Rule ID 3295 //
31890        GIM_CheckFeatures, GIFBS_HasMVEInt,
31891        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31892        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31893        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31894        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31895        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31896        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31897        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
31898        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
31899        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31900        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
31901        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
31902        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31903        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31904        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31905        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31906        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLADAVu16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
31907        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVu16,
31908        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31909        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31910        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31911        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31912        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31913        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31914        GIR_EraseFromParent, /*InsnID*/0,
31915        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31916        // GIR_Coverage, 3295,
31917        GIR_Done,
31918      // Label 1598: @85227
31919      GIM_Try, /*On fail goto*//*Label 1599*/ 85322, // Rule ID 3299 //
31920        GIM_CheckFeatures, GIFBS_HasMVEInt,
31921        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31922        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31923        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31924        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31925        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31926        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31927        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
31928        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
31929        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31930        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
31931        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
31932        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31933        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31934        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31935        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31936        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLADAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31937        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVs32,
31938        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31939        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31940        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31941        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31942        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31943        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31944        GIR_EraseFromParent, /*InsnID*/0,
31945        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31946        // GIR_Coverage, 3299,
31947        GIR_Done,
31948      // Label 1599: @85322
31949      GIM_Try, /*On fail goto*//*Label 1600*/ 85417, // Rule ID 3303 //
31950        GIM_CheckFeatures, GIFBS_HasMVEInt,
31951        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31952        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31953        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31954        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31955        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31956        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31957        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
31958        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
31959        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31960        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
31961        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
31962        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31963        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31964        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31965        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31966        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLADAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31967        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVxs32,
31968        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31969        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31970        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31971        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31972        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31973        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31974        GIR_EraseFromParent, /*InsnID*/0,
31975        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31976        // GIR_Coverage, 3303,
31977        GIR_Done,
31978      // Label 1600: @85417
31979      GIM_Try, /*On fail goto*//*Label 1601*/ 85512, // Rule ID 3307 //
31980        GIM_CheckFeatures, GIFBS_HasMVEInt,
31981        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31982        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31983        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31984        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31985        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31986        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31987        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
31988        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
31989        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31990        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
31991        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
31992        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31993        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31994        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31995        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31996        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLADAVu32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31997        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVu32,
31998        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31999        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32000        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32001        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32002        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32003        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32004        GIR_EraseFromParent, /*InsnID*/0,
32005        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32006        // GIR_Coverage, 3307,
32007        GIR_Done,
32008      // Label 1601: @85512
32009      GIM_Try, /*On fail goto*//*Label 1602*/ 85607, // Rule ID 3311 //
32010        GIM_CheckFeatures, GIFBS_HasMVEInt,
32011        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
32012        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32013        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32014        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32015        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32016        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32017        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
32018        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
32019        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
32020        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
32021        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
32022        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
32023        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32024        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
32025        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
32026        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLSDAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32027        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVs8,
32028        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
32029        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32030        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32031        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32032        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32033        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32034        GIR_EraseFromParent, /*InsnID*/0,
32035        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32036        // GIR_Coverage, 3311,
32037        GIR_Done,
32038      // Label 1602: @85607
32039      GIM_Try, /*On fail goto*//*Label 1603*/ 85702, // Rule ID 3315 //
32040        GIM_CheckFeatures, GIFBS_HasMVEInt,
32041        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
32042        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32043        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32044        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32045        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32046        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32047        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
32048        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
32049        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
32050        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
32051        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
32052        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
32053        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32054        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
32055        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
32056        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLSDAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32057        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVxs8,
32058        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
32059        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32060        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32061        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32062        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32063        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32064        GIR_EraseFromParent, /*InsnID*/0,
32065        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32066        // GIR_Coverage, 3315,
32067        GIR_Done,
32068      // Label 1603: @85702
32069      GIM_Try, /*On fail goto*//*Label 1604*/ 85797, // Rule ID 3319 //
32070        GIM_CheckFeatures, GIFBS_HasMVEInt,
32071        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
32072        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32073        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32074        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32075        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32076        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32077        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
32078        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
32079        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
32080        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
32081        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
32082        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
32083        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32084        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
32085        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
32086        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLSDAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32087        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVs16,
32088        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
32089        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32090        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32091        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32092        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32093        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32094        GIR_EraseFromParent, /*InsnID*/0,
32095        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32096        // GIR_Coverage, 3319,
32097        GIR_Done,
32098      // Label 1604: @85797
32099      GIM_Try, /*On fail goto*//*Label 1605*/ 85892, // Rule ID 3323 //
32100        GIM_CheckFeatures, GIFBS_HasMVEInt,
32101        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
32102        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32103        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32104        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32105        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32106        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32107        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
32108        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
32109        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
32110        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
32111        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
32112        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
32113        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32114        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
32115        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
32116        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLSDAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32117        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVxs16,
32118        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
32119        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32120        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32121        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32122        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32123        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32124        GIR_EraseFromParent, /*InsnID*/0,
32125        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32126        // GIR_Coverage, 3323,
32127        GIR_Done,
32128      // Label 1605: @85892
32129      GIM_Try, /*On fail goto*//*Label 1606*/ 85987, // Rule ID 3327 //
32130        GIM_CheckFeatures, GIFBS_HasMVEInt,
32131        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
32132        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32133        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32134        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32135        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32136        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32137        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
32138        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
32139        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
32140        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
32141        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
32142        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
32143        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32144        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
32145        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
32146        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLSDAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32147        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVs32,
32148        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
32149        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32150        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32151        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32152        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32153        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32154        GIR_EraseFromParent, /*InsnID*/0,
32155        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32156        // GIR_Coverage, 3327,
32157        GIR_Done,
32158      // Label 1606: @85987
32159      GIM_Try, /*On fail goto*//*Label 1607*/ 86082, // Rule ID 3331 //
32160        GIM_CheckFeatures, GIFBS_HasMVEInt,
32161        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
32162        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32163        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32164        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32165        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32166        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32167        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
32168        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
32169        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
32170        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
32171        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
32172        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
32173        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32174        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
32175        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
32176        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLSDAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32177        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVxs32,
32178        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
32179        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32180        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32181        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32182        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32183        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32184        GIR_EraseFromParent, /*InsnID*/0,
32185        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32186        // GIR_Coverage, 3331,
32187        GIR_Done,
32188      // Label 1607: @86082
32189      GIM_Try, /*On fail goto*//*Label 1608*/ 86181, // Rule ID 3277 //
32190        GIM_CheckFeatures, GIFBS_HasMVEInt,
32191        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
32192        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32193        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32194        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32195        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32196        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32197        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
32198        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
32199        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
32200        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
32201        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
32202        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
32203        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
32204        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
32205        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
32206        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLADAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32207        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVas8,
32208        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
32209        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32212        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32213        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32214        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32215        GIR_EraseFromParent, /*InsnID*/0,
32216        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32217        // GIR_Coverage, 3277,
32218        GIR_Done,
32219      // Label 1608: @86181
32220      GIM_Try, /*On fail goto*//*Label 1609*/ 86280, // Rule ID 3281 //
32221        GIM_CheckFeatures, GIFBS_HasMVEInt,
32222        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
32223        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32224        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32225        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32226        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32227        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32228        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
32229        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
32230        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
32231        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
32232        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
32233        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
32234        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
32235        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
32236        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
32237        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLADAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32238        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVaxs8,
32239        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
32240        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32241        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32242        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32243        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32244        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32245        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32246        GIR_EraseFromParent, /*InsnID*/0,
32247        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32248        // GIR_Coverage, 3281,
32249        GIR_Done,
32250      // Label 1609: @86280
32251      GIM_Try, /*On fail goto*//*Label 1610*/ 86379, // Rule ID 3285 //
32252        GIM_CheckFeatures, GIFBS_HasMVEInt,
32253        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
32254        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32255        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32256        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32257        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32258        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32259        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
32260        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
32261        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
32262        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
32263        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
32264        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
32265        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
32266        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
32267        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
32268        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLADAVau8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32269        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVau8,
32270        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
32271        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32272        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32273        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32274        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32275        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32276        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32277        GIR_EraseFromParent, /*InsnID*/0,
32278        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32279        // GIR_Coverage, 3285,
32280        GIR_Done,
32281      // Label 1610: @86379
32282      GIM_Try, /*On fail goto*//*Label 1611*/ 86478, // Rule ID 3289 //
32283        GIM_CheckFeatures, GIFBS_HasMVEInt,
32284        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
32285        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32286        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32287        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32288        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32289        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32290        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
32291        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
32292        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
32293        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
32294        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
32295        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
32296        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
32297        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
32298        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
32299        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLADAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32300        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVas16,
32301        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
32302        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32303        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32304        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32305        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32306        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32307        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32308        GIR_EraseFromParent, /*InsnID*/0,
32309        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32310        // GIR_Coverage, 3289,
32311        GIR_Done,
32312      // Label 1611: @86478
32313      GIM_Try, /*On fail goto*//*Label 1612*/ 86577, // Rule ID 3293 //
32314        GIM_CheckFeatures, GIFBS_HasMVEInt,
32315        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
32316        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32317        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32318        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32319        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32320        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32321        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
32322        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
32323        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
32324        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
32325        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
32326        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
32327        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
32328        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
32329        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
32330        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLADAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32331        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVaxs16,
32332        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
32333        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32334        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32335        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32336        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32337        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32338        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32339        GIR_EraseFromParent, /*InsnID*/0,
32340        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32341        // GIR_Coverage, 3293,
32342        GIR_Done,
32343      // Label 1612: @86577
32344      GIM_Try, /*On fail goto*//*Label 1613*/ 86676, // Rule ID 3297 //
32345        GIM_CheckFeatures, GIFBS_HasMVEInt,
32346        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
32347        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32348        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32349        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32350        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32351        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32352        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
32353        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
32354        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
32355        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
32356        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
32357        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
32358        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
32359        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
32360        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
32361        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLADAVau16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32362        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVau16,
32363        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
32364        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32365        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32366        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32367        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32368        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32369        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32370        GIR_EraseFromParent, /*InsnID*/0,
32371        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32372        // GIR_Coverage, 3297,
32373        GIR_Done,
32374      // Label 1613: @86676
32375      GIM_Try, /*On fail goto*//*Label 1614*/ 86775, // Rule ID 3301 //
32376        GIM_CheckFeatures, GIFBS_HasMVEInt,
32377        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
32378        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32379        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32380        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32381        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32382        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32383        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
32384        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
32385        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
32386        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
32387        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
32388        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
32389        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
32390        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
32391        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
32392        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLADAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32393        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVas32,
32394        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
32395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32396        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32397        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32398        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32399        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32400        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32401        GIR_EraseFromParent, /*InsnID*/0,
32402        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32403        // GIR_Coverage, 3301,
32404        GIR_Done,
32405      // Label 1614: @86775
32406      GIM_Try, /*On fail goto*//*Label 1615*/ 86874, // Rule ID 3305 //
32407        GIM_CheckFeatures, GIFBS_HasMVEInt,
32408        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
32409        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32410        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32411        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32412        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32413        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32414        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
32415        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
32416        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
32417        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
32418        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
32419        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
32420        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
32421        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
32422        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
32423        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLADAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32424        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVaxs32,
32425        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
32426        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32427        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32428        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32429        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32430        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32431        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32432        GIR_EraseFromParent, /*InsnID*/0,
32433        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32434        // GIR_Coverage, 3305,
32435        GIR_Done,
32436      // Label 1615: @86874
32437      GIM_Try, /*On fail goto*//*Label 1616*/ 86973, // Rule ID 3309 //
32438        GIM_CheckFeatures, GIFBS_HasMVEInt,
32439        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
32440        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32441        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32442        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32443        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32444        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32445        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
32446        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
32447        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
32448        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
32449        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
32450        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
32451        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
32452        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
32453        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
32454        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLADAVau32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32455        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVau32,
32456        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
32457        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32458        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32459        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32460        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32461        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32462        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32463        GIR_EraseFromParent, /*InsnID*/0,
32464        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32465        // GIR_Coverage, 3309,
32466        GIR_Done,
32467      // Label 1616: @86973
32468      GIM_Try, /*On fail goto*//*Label 1617*/ 87072, // Rule ID 3313 //
32469        GIM_CheckFeatures, GIFBS_HasMVEInt,
32470        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
32471        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32472        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32473        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32474        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32475        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32476        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
32477        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
32478        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
32479        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
32480        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
32481        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
32482        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
32483        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
32484        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
32485        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLSDAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32486        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVas8,
32487        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
32488        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32489        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32490        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32491        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32492        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32493        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32494        GIR_EraseFromParent, /*InsnID*/0,
32495        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32496        // GIR_Coverage, 3313,
32497        GIR_Done,
32498      // Label 1617: @87072
32499      GIM_Try, /*On fail goto*//*Label 1618*/ 87171, // Rule ID 3317 //
32500        GIM_CheckFeatures, GIFBS_HasMVEInt,
32501        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
32502        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32503        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32504        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32505        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32506        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32507        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
32508        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
32509        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
32510        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
32511        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
32512        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
32513        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
32514        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
32515        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
32516        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)  =>  (MVE_VMLSDAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32517        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVaxs8,
32518        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
32519        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32520        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32521        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32522        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32523        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32524        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32525        GIR_EraseFromParent, /*InsnID*/0,
32526        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32527        // GIR_Coverage, 3317,
32528        GIR_Done,
32529      // Label 1618: @87171
32530      GIM_Try, /*On fail goto*//*Label 1619*/ 87270, // Rule ID 3321 //
32531        GIM_CheckFeatures, GIFBS_HasMVEInt,
32532        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
32533        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32534        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32535        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32536        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32537        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32538        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
32539        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
32540        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
32541        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
32542        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
32543        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
32544        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
32545        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
32546        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
32547        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLSDAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32548        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVas16,
32549        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
32550        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32551        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32552        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32553        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32554        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32555        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32556        GIR_EraseFromParent, /*InsnID*/0,
32557        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32558        // GIR_Coverage, 3321,
32559        GIR_Done,
32560      // Label 1619: @87270
32561      GIM_Try, /*On fail goto*//*Label 1620*/ 87369, // Rule ID 3325 //
32562        GIM_CheckFeatures, GIFBS_HasMVEInt,
32563        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
32564        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32565        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32566        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32567        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32568        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32569        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
32570        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
32571        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
32572        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
32573        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
32574        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
32575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
32576        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
32577        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
32578        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)  =>  (MVE_VMLSDAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32579        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVaxs16,
32580        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
32581        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32582        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32583        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32584        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32585        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32586        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32587        GIR_EraseFromParent, /*InsnID*/0,
32588        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32589        // GIR_Coverage, 3325,
32590        GIR_Done,
32591      // Label 1620: @87369
32592      GIM_Try, /*On fail goto*//*Label 1621*/ 87468, // Rule ID 3329 //
32593        GIM_CheckFeatures, GIFBS_HasMVEInt,
32594        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
32595        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32596        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32597        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32598        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32599        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32600        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
32601        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
32602        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
32603        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
32604        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
32605        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
32606        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
32607        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
32608        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
32609        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLSDAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32610        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVas32,
32611        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
32612        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32613        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32614        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32615        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32616        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32617        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32618        GIR_EraseFromParent, /*InsnID*/0,
32619        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32620        // GIR_Coverage, 3329,
32621        GIR_Done,
32622      // Label 1621: @87468
32623      GIM_Try, /*On fail goto*//*Label 1622*/ 87567, // Rule ID 3333 //
32624        GIM_CheckFeatures, GIFBS_HasMVEInt,
32625        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
32626        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32627        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
32628        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
32629        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32630        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32631        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
32632        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
32633        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
32634        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
32635        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
32636        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
32637        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
32638        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
32639        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
32640        // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)  =>  (MVE_VMLSDAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32641        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVaxs32,
32642        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
32643        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
32644        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
32645        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
32646        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32647        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32648        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32649        GIR_EraseFromParent, /*InsnID*/0,
32650        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32651        // GIR_Coverage, 3333,
32652        GIR_Done,
32653      // Label 1622: @87567
32654      GIM_Try, /*On fail goto*//*Label 1623*/ 87664, // Rule ID 4433 //
32655        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
32656        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
32657        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
32658        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
32659        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
32660        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32661        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32662        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32663        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32664        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32665        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32666        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
32667        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32668        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32669        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
32670        // (intrinsic_wo_chain:{ *:[v16i8] } 2491:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
32671        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLADHs8,
32672        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32673        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32674        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32675        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32676        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32677        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32678        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32679        GIR_EraseFromParent, /*InsnID*/0,
32680        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32681        // GIR_Coverage, 4433,
32682        GIR_Done,
32683      // Label 1623: @87664
32684      GIM_Try, /*On fail goto*//*Label 1624*/ 87761, // Rule ID 4435 //
32685        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
32686        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
32687        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
32688        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
32689        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
32690        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32691        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32692        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32693        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32694        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32695        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32696        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
32697        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32698        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32699        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
32700        // (intrinsic_wo_chain:{ *:[v8i16] } 2491:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
32701        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLADHs16,
32702        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32703        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32704        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32705        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32706        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32707        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32708        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32709        GIR_EraseFromParent, /*InsnID*/0,
32710        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32711        // GIR_Coverage, 4435,
32712        GIR_Done,
32713      // Label 1624: @87761
32714      GIM_Try, /*On fail goto*//*Label 1625*/ 87858, // Rule ID 4437 //
32715        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
32716        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
32717        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
32718        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
32719        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
32720        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32721        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32722        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32723        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32724        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32725        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32726        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
32727        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32728        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32729        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
32730        // (intrinsic_wo_chain:{ *:[v4i32] } 2491:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
32731        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLADHs32,
32732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32733        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32734        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32735        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32736        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32737        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32738        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32739        GIR_EraseFromParent, /*InsnID*/0,
32740        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32741        // GIR_Coverage, 4437,
32742        GIR_Done,
32743      // Label 1625: @87858
32744      GIM_Try, /*On fail goto*//*Label 1626*/ 87955, // Rule ID 4439 //
32745        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
32746        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
32747        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
32748        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
32749        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
32750        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32751        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32752        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32753        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32754        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32755        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32756        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
32757        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
32758        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32759        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
32760        // (intrinsic_wo_chain:{ *:[v16i8] } 2491:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
32761        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLADHXs8,
32762        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32763        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32764        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32765        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32766        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32767        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32768        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32769        GIR_EraseFromParent, /*InsnID*/0,
32770        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32771        // GIR_Coverage, 4439,
32772        GIR_Done,
32773      // Label 1626: @87955
32774      GIM_Try, /*On fail goto*//*Label 1627*/ 88052, // Rule ID 4441 //
32775        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
32776        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
32777        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
32778        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
32779        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
32780        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32781        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32782        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32783        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32784        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32785        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32786        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
32787        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
32788        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32789        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
32790        // (intrinsic_wo_chain:{ *:[v8i16] } 2491:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
32791        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLADHXs16,
32792        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32793        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32794        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32795        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32796        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32797        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32798        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32799        GIR_EraseFromParent, /*InsnID*/0,
32800        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32801        // GIR_Coverage, 4441,
32802        GIR_Done,
32803      // Label 1627: @88052
32804      GIM_Try, /*On fail goto*//*Label 1628*/ 88149, // Rule ID 4443 //
32805        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
32806        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
32807        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
32808        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
32809        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
32810        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32811        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32812        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32813        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32814        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32815        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32816        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
32817        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
32818        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32819        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
32820        // (intrinsic_wo_chain:{ *:[v4i32] } 2491:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
32821        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLADHXs32,
32822        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32823        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32824        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32825        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32826        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32827        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32828        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32829        GIR_EraseFromParent, /*InsnID*/0,
32830        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32831        // GIR_Coverage, 4443,
32832        GIR_Done,
32833      // Label 1628: @88149
32834      GIM_Try, /*On fail goto*//*Label 1629*/ 88246, // Rule ID 4445 //
32835        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
32836        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
32837        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
32838        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
32839        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
32840        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32841        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32842        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32843        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32844        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32845        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32846        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
32847        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32848        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32849        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
32850        // (intrinsic_wo_chain:{ *:[v16i8] } 2491:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
32851        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLADHs8,
32852        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32853        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32854        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32855        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32856        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32857        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32858        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32859        GIR_EraseFromParent, /*InsnID*/0,
32860        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32861        // GIR_Coverage, 4445,
32862        GIR_Done,
32863      // Label 1629: @88246
32864      GIM_Try, /*On fail goto*//*Label 1630*/ 88343, // Rule ID 4447 //
32865        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
32866        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
32867        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
32868        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
32869        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
32870        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32871        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32872        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32873        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32874        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32875        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32876        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
32877        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32878        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32879        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
32880        // (intrinsic_wo_chain:{ *:[v8i16] } 2491:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
32881        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLADHs16,
32882        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32883        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32884        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32885        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32886        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32887        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32888        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32889        GIR_EraseFromParent, /*InsnID*/0,
32890        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32891        // GIR_Coverage, 4447,
32892        GIR_Done,
32893      // Label 1630: @88343
32894      GIM_Try, /*On fail goto*//*Label 1631*/ 88440, // Rule ID 4449 //
32895        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
32896        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
32897        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
32898        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
32899        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
32900        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32901        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32902        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32903        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32904        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32905        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32906        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
32907        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32908        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32909        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
32910        // (intrinsic_wo_chain:{ *:[v4i32] } 2491:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
32911        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLADHs32,
32912        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32913        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32914        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32915        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32916        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32917        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32918        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32919        GIR_EraseFromParent, /*InsnID*/0,
32920        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32921        // GIR_Coverage, 4449,
32922        GIR_Done,
32923      // Label 1631: @88440
32924      GIM_Try, /*On fail goto*//*Label 1632*/ 88537, // Rule ID 4451 //
32925        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
32926        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
32927        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
32928        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
32929        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
32930        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32931        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32932        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32933        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32934        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32935        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32936        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
32937        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
32938        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32939        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
32940        // (intrinsic_wo_chain:{ *:[v16i8] } 2491:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
32941        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLADHXs8,
32942        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32943        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32944        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32945        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32946        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32947        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32948        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32949        GIR_EraseFromParent, /*InsnID*/0,
32950        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32951        // GIR_Coverage, 4451,
32952        GIR_Done,
32953      // Label 1632: @88537
32954      GIM_Try, /*On fail goto*//*Label 1633*/ 88634, // Rule ID 4453 //
32955        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
32956        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
32957        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
32958        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
32959        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
32960        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32961        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32962        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32963        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32964        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32965        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32966        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
32967        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
32968        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32969        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
32970        // (intrinsic_wo_chain:{ *:[v8i16] } 2491:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
32971        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLADHXs16,
32972        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32973        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32974        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32975        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32976        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32977        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32978        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32979        GIR_EraseFromParent, /*InsnID*/0,
32980        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32981        // GIR_Coverage, 4453,
32982        GIR_Done,
32983      // Label 1633: @88634
32984      GIM_Try, /*On fail goto*//*Label 1634*/ 88731, // Rule ID 4455 //
32985        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
32986        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
32987        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
32988        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
32989        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
32990        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32991        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32992        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32993        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32994        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32995        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32996        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
32997        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
32998        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32999        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
33000        // (intrinsic_wo_chain:{ *:[v4i32] } 2491:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33001        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLADHXs32,
33002        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33003        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33005        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33006        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33007        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33008        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33009        GIR_EraseFromParent, /*InsnID*/0,
33010        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33011        // GIR_Coverage, 4455,
33012        GIR_Done,
33013      // Label 1634: @88731
33014      GIM_Try, /*On fail goto*//*Label 1635*/ 88828, // Rule ID 4457 //
33015        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
33016        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33017        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33018        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
33019        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
33020        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33021        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33022        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33023        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33024        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33025        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33026        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
33027        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
33028        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33029        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33030        // (intrinsic_wo_chain:{ *:[v16i8] } 2491:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
33031        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLSDHs8,
33032        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33033        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33034        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33035        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33036        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33037        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33038        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33039        GIR_EraseFromParent, /*InsnID*/0,
33040        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33041        // GIR_Coverage, 4457,
33042        GIR_Done,
33043      // Label 1635: @88828
33044      GIM_Try, /*On fail goto*//*Label 1636*/ 88925, // Rule ID 4459 //
33045        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
33046        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33047        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33048        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33049        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
33050        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33051        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33052        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33053        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33054        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33055        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33056        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
33057        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
33058        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33059        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33060        // (intrinsic_wo_chain:{ *:[v8i16] } 2491:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
33061        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLSDHs16,
33062        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33063        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33064        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33065        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33066        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33067        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33068        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33069        GIR_EraseFromParent, /*InsnID*/0,
33070        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33071        // GIR_Coverage, 4459,
33072        GIR_Done,
33073      // Label 1636: @88925
33074      GIM_Try, /*On fail goto*//*Label 1637*/ 89022, // Rule ID 4461 //
33075        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
33076        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
33077        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
33078        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33079        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
33080        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33081        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33082        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33083        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33084        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33085        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33086        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
33087        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
33088        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33089        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33090        // (intrinsic_wo_chain:{ *:[v4i32] } 2491:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33091        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLSDHs32,
33092        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33093        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33094        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33095        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33096        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33097        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33098        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33099        GIR_EraseFromParent, /*InsnID*/0,
33100        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33101        // GIR_Coverage, 4461,
33102        GIR_Done,
33103      // Label 1637: @89022
33104      GIM_Try, /*On fail goto*//*Label 1638*/ 89119, // Rule ID 4463 //
33105        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
33106        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33107        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33108        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
33109        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
33110        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33111        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33112        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33113        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33114        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33115        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33116        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
33117        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33118        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33119        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33120        // (intrinsic_wo_chain:{ *:[v16i8] } 2491:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
33121        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLSDHXs8,
33122        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33123        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33124        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33125        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33126        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33127        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33128        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33129        GIR_EraseFromParent, /*InsnID*/0,
33130        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33131        // GIR_Coverage, 4463,
33132        GIR_Done,
33133      // Label 1638: @89119
33134      GIM_Try, /*On fail goto*//*Label 1639*/ 89216, // Rule ID 4465 //
33135        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
33136        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33137        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33138        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33139        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
33140        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33141        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33142        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33143        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33144        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33145        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33146        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
33147        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33148        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33149        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33150        // (intrinsic_wo_chain:{ *:[v8i16] } 2491:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
33151        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLSDHXs16,
33152        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33153        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33154        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33155        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33156        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33157        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33158        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33159        GIR_EraseFromParent, /*InsnID*/0,
33160        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33161        // GIR_Coverage, 4465,
33162        GIR_Done,
33163      // Label 1639: @89216
33164      GIM_Try, /*On fail goto*//*Label 1640*/ 89313, // Rule ID 4467 //
33165        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
33166        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
33167        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
33168        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33169        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
33170        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33171        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33172        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33173        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33174        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33175        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33176        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
33177        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33178        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33179        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33180        // (intrinsic_wo_chain:{ *:[v4i32] } 2491:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33181        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLSDHXs32,
33182        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33183        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33184        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33185        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33186        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33187        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33188        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33189        GIR_EraseFromParent, /*InsnID*/0,
33190        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33191        // GIR_Coverage, 4467,
33192        GIR_Done,
33193      // Label 1640: @89313
33194      GIM_Try, /*On fail goto*//*Label 1641*/ 89410, // Rule ID 4469 //
33195        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
33196        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33197        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33198        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
33199        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
33200        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33201        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33202        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33203        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33204        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33205        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33206        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
33207        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
33208        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33209        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33210        // (intrinsic_wo_chain:{ *:[v16i8] } 2491:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
33211        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLSDHs8,
33212        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33213        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33214        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33215        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33216        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33217        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33218        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33219        GIR_EraseFromParent, /*InsnID*/0,
33220        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33221        // GIR_Coverage, 4469,
33222        GIR_Done,
33223      // Label 1641: @89410
33224      GIM_Try, /*On fail goto*//*Label 1642*/ 89507, // Rule ID 4471 //
33225        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
33226        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33227        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33228        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33229        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
33230        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33231        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33232        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33233        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33234        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33235        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33236        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
33237        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
33238        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33239        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33240        // (intrinsic_wo_chain:{ *:[v8i16] } 2491:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
33241        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLSDHs16,
33242        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33243        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33244        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33245        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33246        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33247        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33248        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33249        GIR_EraseFromParent, /*InsnID*/0,
33250        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33251        // GIR_Coverage, 4471,
33252        GIR_Done,
33253      // Label 1642: @89507
33254      GIM_Try, /*On fail goto*//*Label 1643*/ 89604, // Rule ID 4473 //
33255        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
33256        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
33257        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
33258        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33259        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
33260        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33261        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33262        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33263        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33264        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33265        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33266        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
33267        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
33268        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33269        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33270        // (intrinsic_wo_chain:{ *:[v4i32] } 2491:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33271        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLSDHs32,
33272        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33273        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33274        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33275        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33276        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33277        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33278        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33279        GIR_EraseFromParent, /*InsnID*/0,
33280        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33281        // GIR_Coverage, 4473,
33282        GIR_Done,
33283      // Label 1643: @89604
33284      GIM_Try, /*On fail goto*//*Label 1644*/ 89701, // Rule ID 4475 //
33285        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
33286        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33287        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33288        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
33289        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
33290        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33291        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33292        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33293        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33294        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33295        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33296        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
33297        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33298        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33299        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33300        // (intrinsic_wo_chain:{ *:[v16i8] } 2491:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
33301        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLSDHXs8,
33302        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33303        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33304        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33305        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33306        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33307        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33308        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33309        GIR_EraseFromParent, /*InsnID*/0,
33310        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33311        // GIR_Coverage, 4475,
33312        GIR_Done,
33313      // Label 1644: @89701
33314      GIM_Try, /*On fail goto*//*Label 1645*/ 89798, // Rule ID 4477 //
33315        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
33316        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33317        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33318        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33319        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
33320        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33321        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33322        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33323        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33324        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33325        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33326        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
33327        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33328        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33329        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33330        // (intrinsic_wo_chain:{ *:[v8i16] } 2491:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
33331        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLSDHXs16,
33332        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33333        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33334        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33335        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33336        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33337        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33338        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33339        GIR_EraseFromParent, /*InsnID*/0,
33340        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33341        // GIR_Coverage, 4477,
33342        GIR_Done,
33343      // Label 1645: @89798
33344      GIM_Try, /*On fail goto*//*Label 1646*/ 89895, // Rule ID 4479 //
33345        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
33346        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
33347        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
33348        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33349        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
33350        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33351        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33352        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33353        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33354        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33355        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33356        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
33357        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33358        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33359        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33360        // (intrinsic_wo_chain:{ *:[v4i32] } 2491:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33361        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLSDHXs32,
33362        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33363        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
33364        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
33365        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
33366        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33367        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33368        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33369        GIR_EraseFromParent, /*InsnID*/0,
33370        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33371        // GIR_Coverage, 4479,
33372        GIR_Done,
33373      // Label 1646: @89895
33374      GIM_Try, /*On fail goto*//*Label 1647*/ 90024, // Rule ID 2707 //
33375        GIM_CheckFeatures, GIFBS_HasNEON,
33376        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbx4,
33377        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
33378        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
33379        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
33380        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
33381        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8,
33382        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s8,
33383        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s8,
33384        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
33385        // (intrinsic_wo_chain:{ *:[v8i8] } 2693:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm)  =>  (VTBX4Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
33386        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
33387        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE,
33388        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
33389        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
33390        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1,
33391        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
33392        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2,
33393        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2
33394        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/3,
33395        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/6, // Vn3
33396        GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/4,
33397        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, ARM::QQPRRegClassID,
33398        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, ARM::DPRRegClassID,
33399        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, ARM::DPRRegClassID,
33400        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, ARM::DPRRegClassID,
33401        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, ARM::DPRRegClassID,
33402        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBX4Pseudo,
33403        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
33404        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // orig
33405        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
33406        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Vm
33407        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33408        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33409        GIR_EraseFromParent, /*InsnID*/0,
33410        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33411        // GIR_Coverage, 2707,
33412        GIR_Done,
33413      // Label 1647: @90024
33414      GIM_Reject,
33415    // Label 1592: @90025
33416    GIM_Try, /*On fail goto*//*Label 1648*/ 94675,
33417      GIM_CheckNumOperands, /*MI*/0, /*Expected*/10,
33418      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshrn,
33419      GIM_Try, /*On fail goto*//*Label 1649*/ 90150, // Rule ID 3870 //
33420        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33421        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33422        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33423        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33424        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33425        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33426        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33427        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33428        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33429        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33430        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33431        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33432        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33433        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33434        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
33435        // MIs[1] Operand 1
33436        // No operand predicates
33437        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
33438        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33439        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
33440        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
33441        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
33442        GIM_CheckIsSafeToFold, /*InsnID*/1,
33443        // (intrinsic_wo_chain:{ *:[v16i8] } 2536:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33444        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi16bh,
33445        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33446        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33447        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33448        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33449        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33450        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33451        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33452        GIR_EraseFromParent, /*InsnID*/0,
33453        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33454        // GIR_Coverage, 3870,
33455        GIR_Done,
33456      // Label 1649: @90150
33457      GIM_Try, /*On fail goto*//*Label 1650*/ 90266, // Rule ID 3872 //
33458        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33459        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33460        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33461        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33462        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33463        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33464        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33465        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33466        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33467        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33468        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33469        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33470        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33471        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33472        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
33473        // MIs[1] Operand 1
33474        // No operand predicates
33475        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
33476        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33477        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
33478        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
33479        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
33480        GIM_CheckIsSafeToFold, /*InsnID*/1,
33481        // (intrinsic_wo_chain:{ *:[v16i8] } 2536:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33482        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi16th,
33483        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33484        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33485        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33486        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33487        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33488        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33489        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33490        GIR_EraseFromParent, /*InsnID*/0,
33491        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33492        // GIR_Coverage, 3872,
33493        GIR_Done,
33494      // Label 1650: @90266
33495      GIM_Try, /*On fail goto*//*Label 1651*/ 90382, // Rule ID 3874 //
33496        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33497        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33498        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33499        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33500        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33501        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33502        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33503        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33504        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33505        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33506        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33507        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33508        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33509        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33510        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
33511        // MIs[1] Operand 1
33512        // No operand predicates
33513        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
33514        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33515        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
33516        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
33517        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
33518        GIM_CheckIsSafeToFold, /*InsnID*/1,
33519        // (intrinsic_wo_chain:{ *:[v8i16] } 2536:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33520        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi32bh,
33521        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33522        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33523        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33524        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33525        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33526        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33527        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33528        GIR_EraseFromParent, /*InsnID*/0,
33529        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33530        // GIR_Coverage, 3874,
33531        GIR_Done,
33532      // Label 1651: @90382
33533      GIM_Try, /*On fail goto*//*Label 1652*/ 90498, // Rule ID 3876 //
33534        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33535        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33536        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33537        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33538        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33539        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33540        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33541        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33542        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33543        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33544        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33545        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33546        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33547        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33548        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
33549        // MIs[1] Operand 1
33550        // No operand predicates
33551        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
33552        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33553        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
33554        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
33555        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
33556        GIM_CheckIsSafeToFold, /*InsnID*/1,
33557        // (intrinsic_wo_chain:{ *:[v8i16] } 2536:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33558        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi32th,
33559        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33560        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33561        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33562        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33563        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33564        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33565        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33566        GIR_EraseFromParent, /*InsnID*/0,
33567        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33568        // GIR_Coverage, 3876,
33569        GIR_Done,
33570      // Label 1652: @90498
33571      GIM_Try, /*On fail goto*//*Label 1653*/ 90614, // Rule ID 3878 //
33572        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33573        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33574        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33575        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33576        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33577        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33578        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33579        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33580        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33581        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33582        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33583        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33584        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33585        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33586        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
33587        // MIs[1] Operand 1
33588        // No operand predicates
33589        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
33590        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33591        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33592        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
33593        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
33594        GIM_CheckIsSafeToFold, /*InsnID*/1,
33595        // (intrinsic_wo_chain:{ *:[v16i8] } 2536:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33596        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi16bh,
33597        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33598        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33599        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33600        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33601        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33602        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33603        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33604        GIR_EraseFromParent, /*InsnID*/0,
33605        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33606        // GIR_Coverage, 3878,
33607        GIR_Done,
33608      // Label 1653: @90614
33609      GIM_Try, /*On fail goto*//*Label 1654*/ 90730, // Rule ID 3880 //
33610        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33611        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33612        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33613        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33614        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33615        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33616        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33617        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33618        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33619        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33620        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33621        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33622        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33623        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33624        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
33625        // MIs[1] Operand 1
33626        // No operand predicates
33627        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
33628        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33629        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33630        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
33631        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
33632        GIM_CheckIsSafeToFold, /*InsnID*/1,
33633        // (intrinsic_wo_chain:{ *:[v16i8] } 2536:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33634        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi16th,
33635        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33636        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33637        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33638        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33639        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33640        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33641        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33642        GIR_EraseFromParent, /*InsnID*/0,
33643        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33644        // GIR_Coverage, 3880,
33645        GIR_Done,
33646      // Label 1654: @90730
33647      GIM_Try, /*On fail goto*//*Label 1655*/ 90846, // Rule ID 3882 //
33648        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33649        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33650        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33651        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33652        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33653        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33654        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33655        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33656        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33657        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33658        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33659        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33660        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33661        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33662        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
33663        // MIs[1] Operand 1
33664        // No operand predicates
33665        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
33666        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33667        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33668        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
33669        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
33670        GIM_CheckIsSafeToFold, /*InsnID*/1,
33671        // (intrinsic_wo_chain:{ *:[v8i16] } 2536:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33672        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi32bh,
33673        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33674        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33675        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33676        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33677        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33678        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33679        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33680        GIR_EraseFromParent, /*InsnID*/0,
33681        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33682        // GIR_Coverage, 3882,
33683        GIR_Done,
33684      // Label 1655: @90846
33685      GIM_Try, /*On fail goto*//*Label 1656*/ 90962, // Rule ID 3884 //
33686        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33687        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33688        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33689        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33690        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33691        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33692        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33693        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33694        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33695        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33696        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33697        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33698        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33699        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33700        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
33701        // MIs[1] Operand 1
33702        // No operand predicates
33703        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
33704        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33705        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33706        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
33707        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
33708        GIM_CheckIsSafeToFold, /*InsnID*/1,
33709        // (intrinsic_wo_chain:{ *:[v8i16] } 2536:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33710        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi32th,
33711        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33712        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33713        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33714        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33715        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33716        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33717        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33718        GIR_EraseFromParent, /*InsnID*/0,
33719        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33720        // GIR_Coverage, 3884,
33721        GIR_Done,
33722      // Label 1656: @90962
33723      GIM_Try, /*On fail goto*//*Label 1657*/ 91078, // Rule ID 3886 //
33724        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33725        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33726        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33727        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33728        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33729        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33730        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33731        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33732        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33733        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33734        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33735        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33736        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33737        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33738        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
33739        // MIs[1] Operand 1
33740        // No operand predicates
33741        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
33742        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33743        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
33744        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
33745        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
33746        GIM_CheckIsSafeToFold, /*InsnID*/1,
33747        // (intrinsic_wo_chain:{ *:[v16i8] } 2536:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33748        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi16bh,
33749        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33750        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33751        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33752        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33753        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33754        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33755        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33756        GIR_EraseFromParent, /*InsnID*/0,
33757        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33758        // GIR_Coverage, 3886,
33759        GIR_Done,
33760      // Label 1657: @91078
33761      GIM_Try, /*On fail goto*//*Label 1658*/ 91194, // Rule ID 3888 //
33762        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33763        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33764        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33765        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33766        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33767        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33768        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33769        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33770        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33771        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33772        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33773        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33774        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33775        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33776        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
33777        // MIs[1] Operand 1
33778        // No operand predicates
33779        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
33780        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33781        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
33782        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
33783        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
33784        GIM_CheckIsSafeToFold, /*InsnID*/1,
33785        // (intrinsic_wo_chain:{ *:[v16i8] } 2536:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33786        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi16th,
33787        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33788        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33789        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33790        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33791        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33792        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33793        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33794        GIR_EraseFromParent, /*InsnID*/0,
33795        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33796        // GIR_Coverage, 3888,
33797        GIR_Done,
33798      // Label 1658: @91194
33799      GIM_Try, /*On fail goto*//*Label 1659*/ 91310, // Rule ID 3890 //
33800        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33801        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33802        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33803        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33804        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33805        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33806        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33807        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33808        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33809        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33810        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33811        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33812        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33813        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33814        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
33815        // MIs[1] Operand 1
33816        // No operand predicates
33817        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
33818        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33819        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
33820        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
33821        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
33822        GIM_CheckIsSafeToFold, /*InsnID*/1,
33823        // (intrinsic_wo_chain:{ *:[v8i16] } 2536:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33824        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi32bh,
33825        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33826        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33827        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33828        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33829        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33830        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33831        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33832        GIR_EraseFromParent, /*InsnID*/0,
33833        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33834        // GIR_Coverage, 3890,
33835        GIR_Done,
33836      // Label 1659: @91310
33837      GIM_Try, /*On fail goto*//*Label 1660*/ 91426, // Rule ID 3892 //
33838        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33839        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33840        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33841        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33842        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33843        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33844        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33845        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33846        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33847        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33848        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33849        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33850        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33851        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33852        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
33853        // MIs[1] Operand 1
33854        // No operand predicates
33855        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
33856        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33857        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
33858        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
33859        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
33860        GIM_CheckIsSafeToFold, /*InsnID*/1,
33861        // (intrinsic_wo_chain:{ *:[v8i16] } 2536:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33862        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi32th,
33863        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33864        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33865        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33866        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33867        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33868        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33869        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33870        GIR_EraseFromParent, /*InsnID*/0,
33871        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33872        // GIR_Coverage, 3892,
33873        GIR_Done,
33874      // Label 1660: @91426
33875      GIM_Try, /*On fail goto*//*Label 1661*/ 91542, // Rule ID 3894 //
33876        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33877        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33878        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33879        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33880        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33881        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33882        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33883        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33884        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33885        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33886        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33887        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33888        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33889        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33890        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
33891        // MIs[1] Operand 1
33892        // No operand predicates
33893        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
33894        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33895        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33896        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
33897        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
33898        GIM_CheckIsSafeToFold, /*InsnID*/1,
33899        // (intrinsic_wo_chain:{ *:[v16i8] } 2536:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33900        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi16bh,
33901        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33902        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33903        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33904        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33905        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33906        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33907        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33908        GIR_EraseFromParent, /*InsnID*/0,
33909        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33910        // GIR_Coverage, 3894,
33911        GIR_Done,
33912      // Label 1661: @91542
33913      GIM_Try, /*On fail goto*//*Label 1662*/ 91658, // Rule ID 3896 //
33914        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33915        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33916        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33917        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33918        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33919        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33920        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33921        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33922        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33923        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33924        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33925        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33926        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33927        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33928        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
33929        // MIs[1] Operand 1
33930        // No operand predicates
33931        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
33932        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33933        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33934        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
33935        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
33936        GIM_CheckIsSafeToFold, /*InsnID*/1,
33937        // (intrinsic_wo_chain:{ *:[v16i8] } 2536:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33938        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi16th,
33939        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33940        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33941        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33942        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33943        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33944        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33945        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33946        GIR_EraseFromParent, /*InsnID*/0,
33947        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33948        // GIR_Coverage, 3896,
33949        GIR_Done,
33950      // Label 1662: @91658
33951      GIM_Try, /*On fail goto*//*Label 1663*/ 91774, // Rule ID 3898 //
33952        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33953        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33954        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33955        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33956        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33957        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33958        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33959        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33960        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33961        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33962        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33963        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33964        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33965        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33966        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
33967        // MIs[1] Operand 1
33968        // No operand predicates
33969        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
33970        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33971        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33972        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
33973        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
33974        GIM_CheckIsSafeToFold, /*InsnID*/1,
33975        // (intrinsic_wo_chain:{ *:[v8i16] } 2536:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33976        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi32bh,
33977        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33978        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33979        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33980        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33981        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33982        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33983        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33984        GIR_EraseFromParent, /*InsnID*/0,
33985        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33986        // GIR_Coverage, 3898,
33987        GIR_Done,
33988      // Label 1663: @91774
33989      GIM_Try, /*On fail goto*//*Label 1664*/ 91890, // Rule ID 3900 //
33990        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33991        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33992        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33993        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33994        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33995        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33996        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33997        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33998        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33999        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34000        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34001        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34002        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34003        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34004        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
34005        // MIs[1] Operand 1
34006        // No operand predicates
34007        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
34008        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
34009        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
34010        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
34011        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
34012        GIM_CheckIsSafeToFold, /*InsnID*/1,
34013        // (intrinsic_wo_chain:{ *:[v8i16] } 2536:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34014        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi32th,
34015        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34016        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34017        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34018        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34019        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34020        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34021        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34022        GIR_EraseFromParent, /*InsnID*/0,
34023        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34024        // GIR_Coverage, 3900,
34025        GIR_Done,
34026      // Label 1664: @91890
34027      GIM_Try, /*On fail goto*//*Label 1665*/ 92006, // Rule ID 3902 //
34028        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34029        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34030        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34031        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34032        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34033        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34034        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34035        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34036        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34037        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34038        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34039        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34040        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34041        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34042        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
34043        // MIs[1] Operand 1
34044        // No operand predicates
34045        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34046        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
34047        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
34048        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
34049        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
34050        GIM_CheckIsSafeToFold, /*InsnID*/1,
34051        // (intrinsic_wo_chain:{ *:[v16i8] } 2536:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34052        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNbhs16,
34053        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34054        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34055        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34056        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34057        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34058        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34059        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34060        GIR_EraseFromParent, /*InsnID*/0,
34061        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34062        // GIR_Coverage, 3902,
34063        GIR_Done,
34064      // Label 1665: @92006
34065      GIM_Try, /*On fail goto*//*Label 1666*/ 92122, // Rule ID 3904 //
34066        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34067        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34068        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34069        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34070        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34071        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34072        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34073        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34074        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34075        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34076        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34077        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34078        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34079        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34080        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
34081        // MIs[1] Operand 1
34082        // No operand predicates
34083        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34084        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
34085        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
34086        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
34087        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
34088        GIM_CheckIsSafeToFold, /*InsnID*/1,
34089        // (intrinsic_wo_chain:{ *:[v16i8] } 2536:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34090        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNths16,
34091        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34092        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34093        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34094        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34095        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34096        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34097        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34098        GIR_EraseFromParent, /*InsnID*/0,
34099        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34100        // GIR_Coverage, 3904,
34101        GIR_Done,
34102      // Label 1666: @92122
34103      GIM_Try, /*On fail goto*//*Label 1667*/ 92238, // Rule ID 3906 //
34104        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34105        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34106        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34107        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34108        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34109        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34110        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34111        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34112        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34113        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34114        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34115        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34116        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34117        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34118        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
34119        // MIs[1] Operand 1
34120        // No operand predicates
34121        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34122        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
34123        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
34124        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
34125        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
34126        GIM_CheckIsSafeToFold, /*InsnID*/1,
34127        // (intrinsic_wo_chain:{ *:[v8i16] } 2536:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34128        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNbhs32,
34129        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34130        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34132        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34133        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34134        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34135        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34136        GIR_EraseFromParent, /*InsnID*/0,
34137        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34138        // GIR_Coverage, 3906,
34139        GIR_Done,
34140      // Label 1667: @92238
34141      GIM_Try, /*On fail goto*//*Label 1668*/ 92354, // Rule ID 3908 //
34142        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34143        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34144        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34145        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34146        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34147        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34148        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34149        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34150        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34151        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34152        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34153        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34154        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34155        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34156        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
34157        // MIs[1] Operand 1
34158        // No operand predicates
34159        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34160        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
34161        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
34162        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
34163        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
34164        GIM_CheckIsSafeToFold, /*InsnID*/1,
34165        // (intrinsic_wo_chain:{ *:[v8i16] } 2536:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34166        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNths32,
34167        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34168        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34169        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34170        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34171        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34172        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34173        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34174        GIR_EraseFromParent, /*InsnID*/0,
34175        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34176        // GIR_Coverage, 3908,
34177        GIR_Done,
34178      // Label 1668: @92354
34179      GIM_Try, /*On fail goto*//*Label 1669*/ 92470, // Rule ID 3910 //
34180        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34181        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34182        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34183        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34184        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34185        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34186        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34187        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34188        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34189        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34190        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34191        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34192        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34193        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34194        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
34195        // MIs[1] Operand 1
34196        // No operand predicates
34197        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34198        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
34199        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
34200        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
34201        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
34202        GIM_CheckIsSafeToFold, /*InsnID*/1,
34203        // (intrinsic_wo_chain:{ *:[v16i8] } 2536:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34204        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNbhu16,
34205        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34206        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34207        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34208        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34209        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34210        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34211        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34212        GIR_EraseFromParent, /*InsnID*/0,
34213        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34214        // GIR_Coverage, 3910,
34215        GIR_Done,
34216      // Label 1669: @92470
34217      GIM_Try, /*On fail goto*//*Label 1670*/ 92586, // Rule ID 3912 //
34218        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34219        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34220        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34221        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34222        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34223        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34224        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34225        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34226        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34227        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34228        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34229        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34230        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34231        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34232        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
34233        // MIs[1] Operand 1
34234        // No operand predicates
34235        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34236        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
34237        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
34238        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
34239        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
34240        GIM_CheckIsSafeToFold, /*InsnID*/1,
34241        // (intrinsic_wo_chain:{ *:[v16i8] } 2536:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34242        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNthu16,
34243        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34244        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34245        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34246        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34247        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34248        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34249        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34250        GIR_EraseFromParent, /*InsnID*/0,
34251        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34252        // GIR_Coverage, 3912,
34253        GIR_Done,
34254      // Label 1670: @92586
34255      GIM_Try, /*On fail goto*//*Label 1671*/ 92702, // Rule ID 3914 //
34256        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34257        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34258        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34259        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34260        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34261        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34262        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34263        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34264        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34265        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34266        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34267        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34268        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34269        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34270        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
34271        // MIs[1] Operand 1
34272        // No operand predicates
34273        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34274        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
34275        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
34276        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
34277        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
34278        GIM_CheckIsSafeToFold, /*InsnID*/1,
34279        // (intrinsic_wo_chain:{ *:[v8i16] } 2536:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34280        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNbhu32,
34281        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34282        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34283        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34284        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34285        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34286        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34287        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34288        GIR_EraseFromParent, /*InsnID*/0,
34289        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34290        // GIR_Coverage, 3914,
34291        GIR_Done,
34292      // Label 1671: @92702
34293      GIM_Try, /*On fail goto*//*Label 1672*/ 92818, // Rule ID 3916 //
34294        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34295        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34296        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34297        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34298        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34299        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34300        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34301        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34302        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34303        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34304        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34305        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34306        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34307        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34308        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
34309        // MIs[1] Operand 1
34310        // No operand predicates
34311        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34312        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
34313        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
34314        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
34315        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
34316        GIM_CheckIsSafeToFold, /*InsnID*/1,
34317        // (intrinsic_wo_chain:{ *:[v8i16] } 2536:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34318        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNthu32,
34319        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34322        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34323        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34324        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34325        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34326        GIR_EraseFromParent, /*InsnID*/0,
34327        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34328        // GIR_Coverage, 3916,
34329        GIR_Done,
34330      // Label 1672: @92818
34331      GIM_Try, /*On fail goto*//*Label 1673*/ 92934, // Rule ID 3918 //
34332        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34333        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34334        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34335        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34336        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34337        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34338        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34339        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34340        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34341        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34342        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34343        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34344        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34345        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34346        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
34347        // MIs[1] Operand 1
34348        // No operand predicates
34349        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34350        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
34351        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
34352        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
34353        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
34354        GIM_CheckIsSafeToFold, /*InsnID*/1,
34355        // (intrinsic_wo_chain:{ *:[v16i8] } 2536:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34356        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNbhs16,
34357        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34358        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34359        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34360        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34361        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34362        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34363        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34364        GIR_EraseFromParent, /*InsnID*/0,
34365        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34366        // GIR_Coverage, 3918,
34367        GIR_Done,
34368      // Label 1673: @92934
34369      GIM_Try, /*On fail goto*//*Label 1674*/ 93050, // Rule ID 3920 //
34370        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34371        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34372        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34373        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34374        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34375        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34376        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34377        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34378        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34379        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34380        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34381        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34382        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34383        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34384        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
34385        // MIs[1] Operand 1
34386        // No operand predicates
34387        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34388        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
34389        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
34390        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
34391        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
34392        GIM_CheckIsSafeToFold, /*InsnID*/1,
34393        // (intrinsic_wo_chain:{ *:[v16i8] } 2536:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34394        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNths16,
34395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34396        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34397        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34398        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34399        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34400        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34401        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34402        GIR_EraseFromParent, /*InsnID*/0,
34403        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34404        // GIR_Coverage, 3920,
34405        GIR_Done,
34406      // Label 1674: @93050
34407      GIM_Try, /*On fail goto*//*Label 1675*/ 93166, // Rule ID 3922 //
34408        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34409        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34410        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34411        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34412        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34413        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34414        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34415        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34416        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34417        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34418        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34419        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34420        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34421        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34422        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
34423        // MIs[1] Operand 1
34424        // No operand predicates
34425        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34426        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
34427        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
34428        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
34429        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
34430        GIM_CheckIsSafeToFold, /*InsnID*/1,
34431        // (intrinsic_wo_chain:{ *:[v8i16] } 2536:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34432        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNbhs32,
34433        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34434        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34435        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34436        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34437        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34438        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34439        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34440        GIR_EraseFromParent, /*InsnID*/0,
34441        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34442        // GIR_Coverage, 3922,
34443        GIR_Done,
34444      // Label 1675: @93166
34445      GIM_Try, /*On fail goto*//*Label 1676*/ 93282, // Rule ID 3924 //
34446        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34447        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34448        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34449        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34450        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34451        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34452        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34453        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34454        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34455        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34456        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34457        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34458        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34459        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34460        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
34461        // MIs[1] Operand 1
34462        // No operand predicates
34463        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34464        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
34465        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
34466        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
34467        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
34468        GIM_CheckIsSafeToFold, /*InsnID*/1,
34469        // (intrinsic_wo_chain:{ *:[v8i16] } 2536:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34470        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNths32,
34471        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34472        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34473        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34474        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34475        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34476        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34477        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34478        GIR_EraseFromParent, /*InsnID*/0,
34479        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34480        // GIR_Coverage, 3924,
34481        GIR_Done,
34482      // Label 1676: @93282
34483      GIM_Try, /*On fail goto*//*Label 1677*/ 93398, // Rule ID 3926 //
34484        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34485        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34486        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34487        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34488        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34489        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34490        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34491        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34492        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34493        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34494        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34495        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34496        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34497        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34498        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
34499        // MIs[1] Operand 1
34500        // No operand predicates
34501        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34502        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
34503        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
34504        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
34505        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
34506        GIM_CheckIsSafeToFold, /*InsnID*/1,
34507        // (intrinsic_wo_chain:{ *:[v16i8] } 2536:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34508        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNbhu16,
34509        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34510        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34511        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34512        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34513        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34514        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34515        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34516        GIR_EraseFromParent, /*InsnID*/0,
34517        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34518        // GIR_Coverage, 3926,
34519        GIR_Done,
34520      // Label 1677: @93398
34521      GIM_Try, /*On fail goto*//*Label 1678*/ 93514, // Rule ID 3928 //
34522        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34523        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34524        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34525        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34526        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34527        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34528        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34529        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34530        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34531        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34532        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34533        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34534        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34535        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34536        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
34537        // MIs[1] Operand 1
34538        // No operand predicates
34539        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34540        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
34541        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
34542        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
34543        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
34544        GIM_CheckIsSafeToFold, /*InsnID*/1,
34545        // (intrinsic_wo_chain:{ *:[v16i8] } 2536:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34546        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNthu16,
34547        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34548        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34549        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34550        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34551        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34552        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34553        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34554        GIR_EraseFromParent, /*InsnID*/0,
34555        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34556        // GIR_Coverage, 3928,
34557        GIR_Done,
34558      // Label 1678: @93514
34559      GIM_Try, /*On fail goto*//*Label 1679*/ 93630, // Rule ID 3930 //
34560        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34561        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34562        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34563        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34564        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34565        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34566        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34567        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34568        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34569        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34570        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34571        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34572        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34573        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34574        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
34575        // MIs[1] Operand 1
34576        // No operand predicates
34577        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34578        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
34579        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
34580        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
34581        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
34582        GIM_CheckIsSafeToFold, /*InsnID*/1,
34583        // (intrinsic_wo_chain:{ *:[v8i16] } 2536:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34584        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNbhu32,
34585        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34586        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34587        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34588        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34589        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34590        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34591        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34592        GIR_EraseFromParent, /*InsnID*/0,
34593        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34594        // GIR_Coverage, 3930,
34595        GIR_Done,
34596      // Label 1679: @93630
34597      GIM_Try, /*On fail goto*//*Label 1680*/ 93746, // Rule ID 3932 //
34598        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34599        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34600        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34601        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34602        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34603        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34604        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34605        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34606        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34607        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34608        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34609        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34610        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34611        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34612        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
34613        // MIs[1] Operand 1
34614        // No operand predicates
34615        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34616        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
34617        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
34618        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
34619        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
34620        GIM_CheckIsSafeToFold, /*InsnID*/1,
34621        // (intrinsic_wo_chain:{ *:[v8i16] } 2536:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34622        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNthu32,
34623        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34624        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34625        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34626        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34627        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34628        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34629        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34630        GIR_EraseFromParent, /*InsnID*/0,
34631        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34632        // GIR_Coverage, 3932,
34633        GIR_Done,
34634      // Label 1680: @93746
34635      GIM_Try, /*On fail goto*//*Label 1681*/ 93862, // Rule ID 3934 //
34636        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34637        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34638        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34639        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34640        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34641        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34642        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34643        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34644        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34645        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34646        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34647        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34648        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34649        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34650        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
34651        // MIs[1] Operand 1
34652        // No operand predicates
34653        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34654        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
34655        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
34656        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
34657        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
34658        GIM_CheckIsSafeToFold, /*InsnID*/1,
34659        // (intrinsic_wo_chain:{ *:[v16i8] } 2536:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34660        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRUNs16bh,
34661        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34662        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34663        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34664        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34665        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34666        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34667        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34668        GIR_EraseFromParent, /*InsnID*/0,
34669        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34670        // GIR_Coverage, 3934,
34671        GIR_Done,
34672      // Label 1681: @93862
34673      GIM_Try, /*On fail goto*//*Label 1682*/ 93978, // Rule ID 3936 //
34674        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34675        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34676        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34677        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34678        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34679        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34680        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34681        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34682        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34683        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34684        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34685        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34686        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34687        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34688        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
34689        // MIs[1] Operand 1
34690        // No operand predicates
34691        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34692        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
34693        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
34694        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
34695        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
34696        GIM_CheckIsSafeToFold, /*InsnID*/1,
34697        // (intrinsic_wo_chain:{ *:[v16i8] } 2536:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34698        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRUNs16th,
34699        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34700        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34701        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34702        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34703        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34704        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34705        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34706        GIR_EraseFromParent, /*InsnID*/0,
34707        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34708        // GIR_Coverage, 3936,
34709        GIR_Done,
34710      // Label 1682: @93978
34711      GIM_Try, /*On fail goto*//*Label 1683*/ 94094, // Rule ID 3938 //
34712        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34713        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34714        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34715        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34716        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34717        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34718        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34719        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34720        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34721        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34722        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34723        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34724        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34725        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34726        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
34727        // MIs[1] Operand 1
34728        // No operand predicates
34729        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34730        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
34731        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
34732        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
34733        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
34734        GIM_CheckIsSafeToFold, /*InsnID*/1,
34735        // (intrinsic_wo_chain:{ *:[v8i16] } 2536:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34736        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRUNs32bh,
34737        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34738        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34739        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34740        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34741        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34742        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34743        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34744        GIR_EraseFromParent, /*InsnID*/0,
34745        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34746        // GIR_Coverage, 3938,
34747        GIR_Done,
34748      // Label 1683: @94094
34749      GIM_Try, /*On fail goto*//*Label 1684*/ 94210, // Rule ID 3940 //
34750        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34751        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34752        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34753        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34754        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34755        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34756        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34757        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34758        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34759        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34760        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34761        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34762        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34763        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34764        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
34765        // MIs[1] Operand 1
34766        // No operand predicates
34767        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34768        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
34769        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
34770        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
34771        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
34772        GIM_CheckIsSafeToFold, /*InsnID*/1,
34773        // (intrinsic_wo_chain:{ *:[v8i16] } 2536:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34774        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRUNs32th,
34775        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34776        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34777        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34778        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34779        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34780        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34781        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34782        GIR_EraseFromParent, /*InsnID*/0,
34783        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34784        // GIR_Coverage, 3940,
34785        GIR_Done,
34786      // Label 1684: @94210
34787      GIM_Try, /*On fail goto*//*Label 1685*/ 94326, // Rule ID 3942 //
34788        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34789        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34790        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34791        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34792        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34793        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34794        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34795        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34796        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34797        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34798        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34799        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34800        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34801        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34802        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
34803        // MIs[1] Operand 1
34804        // No operand predicates
34805        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34806        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
34807        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
34808        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
34809        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
34810        GIM_CheckIsSafeToFold, /*InsnID*/1,
34811        // (intrinsic_wo_chain:{ *:[v16i8] } 2536:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34812        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRUNs16bh,
34813        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34814        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34815        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34816        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34817        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34818        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34819        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34820        GIR_EraseFromParent, /*InsnID*/0,
34821        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34822        // GIR_Coverage, 3942,
34823        GIR_Done,
34824      // Label 1685: @94326
34825      GIM_Try, /*On fail goto*//*Label 1686*/ 94442, // Rule ID 3944 //
34826        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
34827        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
34828        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
34829        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34830        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34831        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34832        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34833        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34834        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34835        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34836        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34837        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34838        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34839        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34840        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
34841        // MIs[1] Operand 1
34842        // No operand predicates
34843        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34844        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
34845        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
34846        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
34847        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
34848        GIM_CheckIsSafeToFold, /*InsnID*/1,
34849        // (intrinsic_wo_chain:{ *:[v16i8] } 2536:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34850        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRUNs16th,
34851        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34852        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34853        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34854        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34855        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34856        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34857        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34858        GIR_EraseFromParent, /*InsnID*/0,
34859        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34860        // GIR_Coverage, 3944,
34861        GIR_Done,
34862      // Label 1686: @94442
34863      GIM_Try, /*On fail goto*//*Label 1687*/ 94558, // Rule ID 3946 //
34864        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34865        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34866        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34867        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34868        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34869        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34870        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34871        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34872        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34873        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34874        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34875        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34876        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34877        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34878        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
34879        // MIs[1] Operand 1
34880        // No operand predicates
34881        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34882        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
34883        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
34884        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
34885        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
34886        GIM_CheckIsSafeToFold, /*InsnID*/1,
34887        // (intrinsic_wo_chain:{ *:[v8i16] } 2536:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VQRSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34888        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRUNs32bh,
34889        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34890        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34891        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34892        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34893        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34894        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34895        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34896        GIR_EraseFromParent, /*InsnID*/0,
34897        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34898        // GIR_Coverage, 3946,
34899        GIR_Done,
34900      // Label 1687: @94558
34901      GIM_Try, /*On fail goto*//*Label 1688*/ 94674, // Rule ID 3948 //
34902        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
34903        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
34904        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34905        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
34906        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
34907        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
34908        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
34909        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
34910        GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
34911        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34912        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34913        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34914        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34915        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34916        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
34917        // MIs[1] Operand 1
34918        // No operand predicates
34919        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
34920        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
34921        GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
34922        GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
34923        GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
34924        GIM_CheckIsSafeToFold, /*InsnID*/1,
34925        // (intrinsic_wo_chain:{ *:[v8i16] } 2536:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VQRSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34926        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRUNs32th,
34927        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34928        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
34929        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
34930        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34931        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
34932        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34933        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34934        GIR_EraseFromParent, /*InsnID*/0,
34935        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34936        // GIR_Coverage, 3948,
34937        GIR_Done,
34938      // Label 1688: @94674
34939      GIM_Reject,
34940    // Label 1648: @94675
34941    GIM_Reject,
34942    // Label 15: @94676
34943    GIM_Try, /*On fail goto*//*Label 1689*/ 94725,
34944      GIM_CheckNumOperands, /*MI*/0, /*Expected*/1,
34945      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_clrex,
34946      GIM_Try, /*On fail goto*//*Label 1690*/ 94701, // Rule ID 252 //
34947        GIM_CheckFeatures, GIFBS_HasV6K_IsARM,
34948        // (intrinsic_void 2321:{ *:[iPTR] })  =>  (CLREX)
34949        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CLREX,
34950        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34951        GIR_EraseFromParent, /*InsnID*/0,
34952        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34953        // GIR_Coverage, 252,
34954        GIR_Done,
34955      // Label 1690: @94701
34956      GIM_Try, /*On fail goto*//*Label 1691*/ 94724, // Rule ID 590 //
34957        GIM_CheckFeatures, GIFBS_HasV7Clrex_IsThumb,
34958        // (intrinsic_void 2321:{ *:[iPTR] })  =>  (t2CLREX)
34959        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CLREX,
34960        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34961        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34962        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34963        GIR_EraseFromParent, /*InsnID*/0,
34964        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34965        // GIR_Coverage, 590,
34966        GIR_Done,
34967      // Label 1691: @94724
34968      GIM_Reject,
34969    // Label 1689: @94725
34970    GIM_Try, /*On fail goto*//*Label 1692*/ 95453,
34971      GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
34972      GIM_Try, /*On fail goto*//*Label 1693*/ 94758, // Rule ID 351 //
34973        GIM_CheckFeatures, GIFBS_IsThumb_IsWindows,
34974        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_undefined,
34975        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
34976        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 249,
34977        // (intrinsic_void 2762:{ *:[iPTR] }, 249:{ *:[i32] })  =>  (t__brkdiv0)
34978        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t__brkdiv0,
34979        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34980        GIR_EraseFromParent, /*InsnID*/0,
34981        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34982        // GIR_Coverage, 351,
34983        GIR_Done,
34984      // Label 1693: @94758
34985      GIM_Try, /*On fail goto*//*Label 1694*/ 94805, // Rule ID 2 //
34986        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
34987        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_hint,
34988        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
34989        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34990        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34991        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_239,
34992        // MIs[1] Operand 1
34993        // No operand predicates
34994        GIM_CheckIsSafeToFold, /*InsnID*/1,
34995        // (intrinsic_void 2339:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm)  =>  (HINT (imm:{ *:[i32] }):$imm)
34996        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::HINT,
34997        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34998        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34999        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35000        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35001        GIR_EraseFromParent, /*InsnID*/0,
35002        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35003        // GIR_Coverage, 2,
35004        GIR_Done,
35005      // Label 1694: @94805
35006      GIM_Try, /*On fail goto*//*Label 1695*/ 94852, // Rule ID 10 //
35007        GIM_CheckFeatures, GIFBS_HasV7_IsARM,
35008        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dbg,
35009        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35010        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35011        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
35012        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
35013        // MIs[1] Operand 1
35014        // No operand predicates
35015        GIM_CheckIsSafeToFold, /*InsnID*/1,
35016        // (intrinsic_void 2334:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (DBG (imm:{ *:[i32] }):$opt)
35017        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::DBG,
35018        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35019        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35020        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35021        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35022        GIR_EraseFromParent, /*InsnID*/0,
35023        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35024        // GIR_Coverage, 10,
35025        GIR_Done,
35026      // Label 1695: @94852
35027      GIM_Try, /*On fail goto*//*Label 1696*/ 94892, // Rule ID 11 //
35028        GIM_CheckFeatures, GIFBS_IsARM,
35029        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_undefined,
35030        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35031        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35032        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
35033        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_65535,
35034        // MIs[1] Operand 1
35035        // No operand predicates
35036        GIM_CheckIsSafeToFold, /*InsnID*/1,
35037        // (intrinsic_void 2762:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16)  =>  (UDF (imm:{ *:[i32] }):$imm16)
35038        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UDF,
35039        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
35040        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35041        GIR_EraseFromParent, /*InsnID*/0,
35042        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35043        // GIR_Coverage, 11,
35044        GIR_Done,
35045      // Label 1696: @94892
35046      GIM_Try, /*On fail goto*//*Label 1697*/ 94932, // Rule ID 235 //
35047        GIM_CheckFeatures, GIFBS_HasDB_IsARM,
35048        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dmb,
35049        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35050        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35051        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
35052        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
35053        // MIs[1] Operand 1
35054        // No operand predicates
35055        GIM_CheckIsSafeToFold, /*InsnID*/1,
35056        // (intrinsic_void 2335:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (DMB (imm:{ *:[i32] }):$opt)
35057        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::DMB,
35058        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35059        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35060        GIR_EraseFromParent, /*InsnID*/0,
35061        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35062        // GIR_Coverage, 235,
35063        GIR_Done,
35064      // Label 1697: @94932
35065      GIM_Try, /*On fail goto*//*Label 1698*/ 94972, // Rule ID 236 //
35066        GIM_CheckFeatures, GIFBS_HasDB_IsARM,
35067        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dsb,
35068        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35069        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35070        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
35071        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
35072        // MIs[1] Operand 1
35073        // No operand predicates
35074        GIM_CheckIsSafeToFold, /*InsnID*/1,
35075        // (intrinsic_void 2336:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (DSB (imm:{ *:[i32] }):$opt)
35076        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::DSB,
35077        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35078        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35079        GIR_EraseFromParent, /*InsnID*/0,
35080        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35081        // GIR_Coverage, 236,
35082        GIR_Done,
35083      // Label 1698: @94972
35084      GIM_Try, /*On fail goto*//*Label 1699*/ 95012, // Rule ID 237 //
35085        GIM_CheckFeatures, GIFBS_HasDB_IsARM,
35086        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_isb,
35087        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35088        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35089        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
35090        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
35091        // MIs[1] Operand 1
35092        // No operand predicates
35093        GIM_CheckIsSafeToFold, /*InsnID*/1,
35094        // (intrinsic_void 2340:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (ISB (imm:{ *:[i32] }):$opt)
35095        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ISB,
35096        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35097        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35098        GIR_EraseFromParent, /*InsnID*/0,
35099        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35100        // GIR_Coverage, 237,
35101        GIR_Done,
35102      // Label 1699: @95012
35103      GIM_Try, /*On fail goto*//*Label 1700*/ 95059, // Rule ID 283 //
35104        GIM_CheckFeatures, GIFBS_HasV6M_IsThumb,
35105        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_hint,
35106        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35107        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35108        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
35109        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
35110        // MIs[1] Operand 1
35111        // No operand predicates
35112        GIM_CheckIsSafeToFold, /*InsnID*/1,
35113        // (intrinsic_void 2339:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)  =>  (tHINT (imm:{ *:[i32] }):$imm)
35114        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tHINT,
35115        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35116        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35117        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35118        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35119        GIR_EraseFromParent, /*InsnID*/0,
35120        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35121        // GIR_Coverage, 283,
35122        GIR_Done,
35123      // Label 1700: @95059
35124      GIM_Try, /*On fail goto*//*Label 1701*/ 95099, // Rule ID 350 //
35125        GIM_CheckFeatures, GIFBS_IsThumb,
35126        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_undefined,
35127        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35128        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35129        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
35130        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_255,
35131        // MIs[1] Operand 1
35132        // No operand predicates
35133        GIM_CheckIsSafeToFold, /*InsnID*/1,
35134        // (intrinsic_void 2762:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_255>>:$imm8)  =>  (tUDF (imm:{ *:[i32] }):$imm8)
35135        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tUDF,
35136        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8
35137        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35138        GIR_EraseFromParent, /*InsnID*/0,
35139        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35140        // GIR_Coverage, 350,
35141        GIR_Done,
35142      // Label 1701: @95099
35143      GIM_Try, /*On fail goto*//*Label 1702*/ 95139, // Rule ID 501 //
35144        GIM_CheckFeatures, GIFBS_IsThumb2,
35145        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_undefined,
35146        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35147        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35148        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
35149        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_65535,
35150        // MIs[1] Operand 1
35151        // No operand predicates
35152        GIM_CheckIsSafeToFold, /*InsnID*/1,
35153        // (intrinsic_void 2762:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16)  =>  (t2UDF (imm:{ *:[i32] }):$imm16)
35154        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UDF,
35155        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
35156        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35157        GIR_EraseFromParent, /*InsnID*/0,
35158        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35159        // GIR_Coverage, 501,
35160        GIR_Done,
35161      // Label 1702: @95139
35162      GIM_Try, /*On fail goto*//*Label 1703*/ 95186, // Rule ID 575 //
35163        GIM_CheckFeatures, GIFBS_HasDB_IsThumb,
35164        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dmb,
35165        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35166        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35167        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
35168        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
35169        // MIs[1] Operand 1
35170        // No operand predicates
35171        GIM_CheckIsSafeToFold, /*InsnID*/1,
35172        // (intrinsic_void 2335:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (t2DMB (imm:{ *:[i32] }):$opt)
35173        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DMB,
35174        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35175        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35176        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35177        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35178        GIR_EraseFromParent, /*InsnID*/0,
35179        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35180        // GIR_Coverage, 575,
35181        GIR_Done,
35182      // Label 1703: @95186
35183      GIM_Try, /*On fail goto*//*Label 1704*/ 95233, // Rule ID 576 //
35184        GIM_CheckFeatures, GIFBS_HasDB_IsThumb,
35185        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dsb,
35186        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35187        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35188        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
35189        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
35190        // MIs[1] Operand 1
35191        // No operand predicates
35192        GIM_CheckIsSafeToFold, /*InsnID*/1,
35193        // (intrinsic_void 2336:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (t2DSB (imm:{ *:[i32] }):$opt)
35194        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DSB,
35195        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35196        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35197        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35198        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35199        GIR_EraseFromParent, /*InsnID*/0,
35200        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35201        // GIR_Coverage, 576,
35202        GIR_Done,
35203      // Label 1704: @95233
35204      GIM_Try, /*On fail goto*//*Label 1705*/ 95280, // Rule ID 577 //
35205        GIM_CheckFeatures, GIFBS_HasDB_IsThumb,
35206        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_isb,
35207        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35208        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35209        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
35210        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
35211        // MIs[1] Operand 1
35212        // No operand predicates
35213        GIM_CheckIsSafeToFold, /*InsnID*/1,
35214        // (intrinsic_void 2340:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (t2ISB (imm:{ *:[i32] }):$opt)
35215        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ISB,
35216        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35217        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35218        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35219        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35220        GIR_EraseFromParent, /*InsnID*/0,
35221        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35222        // GIR_Coverage, 577,
35223        GIR_Done,
35224      // Label 1705: @95280
35225      GIM_Try, /*On fail goto*//*Label 1706*/ 95327, // Rule ID 595 //
35226        GIM_CheckFeatures, GIFBS_IsThumb2,
35227        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_hint,
35228        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35229        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35230        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
35231        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_239,
35232        // MIs[1] Operand 1
35233        // No operand predicates
35234        GIM_CheckIsSafeToFold, /*InsnID*/1,
35235        // (intrinsic_void 2339:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm)  =>  (t2HINT (imm:{ *:[i32] }):$imm)
35236        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2HINT,
35237        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35238        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35239        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35240        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35241        GIR_EraseFromParent, /*InsnID*/0,
35242        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35243        // GIR_Coverage, 595,
35244        GIR_Done,
35245      // Label 1706: @95327
35246      GIM_Try, /*On fail goto*//*Label 1707*/ 95374, // Rule ID 596 //
35247        GIM_CheckFeatures, GIFBS_IsThumb2,
35248        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dbg,
35249        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35250        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35251        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
35252        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
35253        // MIs[1] Operand 1
35254        // No operand predicates
35255        GIM_CheckIsSafeToFold, /*InsnID*/1,
35256        // (intrinsic_void 2334:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (t2DBG (imm:{ *:[i32] }):$opt)
35257        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DBG,
35258        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35259        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35260        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35261        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35262        GIR_EraseFromParent, /*InsnID*/0,
35263        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35264        // GIR_Coverage, 596,
35265        GIR_Done,
35266      // Label 1707: @95374
35267      GIM_Try, /*On fail goto*//*Label 1708*/ 95413, // Rule ID 741 //
35268        GIM_CheckFeatures, GIFBS_HasFPRegs,
35269        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_get_fpscr,
35270        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35271        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
35272        // (intrinsic_w_chain:{ *:[i32] } 2337:{ *:[iPTR] })  =>  (VMRS:{ *:[i32] })
35273        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMRS,
35274        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
35275        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35276        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35277        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35278        GIR_EraseFromParent, /*InsnID*/0,
35279        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35280        // GIR_Coverage, 741,
35281        GIR_Done,
35282      // Label 1708: @95413
35283      GIM_Try, /*On fail goto*//*Label 1709*/ 95452, // Rule ID 742 //
35284        GIM_CheckFeatures, GIFBS_HasFPRegs,
35285        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_set_fpscr,
35286        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35287        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
35288        // (intrinsic_void 2706:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rt)  =>  (VMSR GPRnopc:{ *:[i32] }:$Rt)
35289        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMSR,
35290        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rt
35291        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35292        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35293        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35294        GIR_EraseFromParent, /*InsnID*/0,
35295        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35296        // GIR_Coverage, 742,
35297        GIR_Done,
35298      // Label 1709: @95452
35299      GIM_Reject,
35300    // Label 1692: @95453
35301    GIM_Try, /*On fail goto*//*Label 1710*/ 95500, // Rule ID 620 //
35302      GIM_CheckFeatures, GIFBS_HasLOB_HasV8_1MMainline_IsThumb2,
35303      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
35304      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::start_loop_iterations,
35305      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35306      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35307      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRlrRegClassID,
35308      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
35309      // (intrinsic_w_chain:{ *:[i32] } 288:{ *:[iPTR] }, rGPR:{ *:[i32] }:$tc)  =>  (t2DoLoopStart:{ *:[i32] } rGPR:{ *:[i32] }:$tc)
35310      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DoLoopStart,
35311      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // X
35312      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // tc
35313      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35314      GIR_EraseFromParent, /*InsnID*/0,
35315      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35316      // GIR_Coverage, 620,
35317      GIR_Done,
35318    // Label 1710: @95500
35319    GIM_Try, /*On fail goto*//*Label 1711*/ 97665,
35320      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
35321      GIM_Try, /*On fail goto*//*Label 1712*/ 95564, // Rule ID 5151 //
35322        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_base,
35323        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
35324        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
35325        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35326        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35327        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
35328        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
35329        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
35330        // MIs[1] Operand 1
35331        // No operand predicates
35332        GIM_CheckIsSafeToFold, /*InsnID*/1,
35333        // (intrinsic_w_chain:{ *:[v4i32] } 2470:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)  =>  (MVE_VLDRWU32_qi:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
35334        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_qi,
35335        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
35336        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
35337        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35338        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35339        GIR_EraseFromParent, /*InsnID*/0,
35340        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35341        // GIR_Coverage, 5151,
35342        GIR_Done,
35343      // Label 1712: @95564
35344      GIM_Try, /*On fail goto*//*Label 1713*/ 95623, // Rule ID 5157 //
35345        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_base,
35346        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
35347        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
35348        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35349        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35350        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
35351        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
35352        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
35353        // MIs[1] Operand 1
35354        // No operand predicates
35355        GIM_CheckIsSafeToFold, /*InsnID*/1,
35356        // (intrinsic_w_chain:{ *:[v4f32] } 2470:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)  =>  (MVE_VLDRWU32_qi:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
35357        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_qi,
35358        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
35359        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
35360        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35361        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35362        GIR_EraseFromParent, /*InsnID*/0,
35363        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35364        // GIR_Coverage, 5157,
35365        GIR_Done,
35366      // Label 1713: @95623
35367      GIM_Try, /*On fail goto*//*Label 1714*/ 95682, // Rule ID 5159 //
35368        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_base,
35369        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
35370        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
35371        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35372        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35373        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
35374        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
35375        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
35376        // MIs[1] Operand 1
35377        // No operand predicates
35378        GIM_CheckIsSafeToFold, /*InsnID*/1,
35379        // (intrinsic_w_chain:{ *:[v2i64] } 2470:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)  =>  (MVE_VLDRDU64_qi:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
35380        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_qi,
35381        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
35382        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
35383        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35384        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35385        GIR_EraseFromParent, /*InsnID*/0,
35386        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35387        // GIR_Coverage, 5159,
35388        GIR_Done,
35389      // Label 1714: @95682
35390      GIM_Try, /*On fail goto*//*Label 1715*/ 95741, // Rule ID 5161 //
35391        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_base,
35392        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
35393        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
35394        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35395        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35396        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
35397        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
35398        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
35399        // MIs[1] Operand 1
35400        // No operand predicates
35401        GIM_CheckIsSafeToFold, /*InsnID*/1,
35402        // (intrinsic_w_chain:{ *:[v2f64] } 2470:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)  =>  (MVE_VLDRDU64_qi:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
35403        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_qi,
35404        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
35405        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
35406        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35407        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35408        GIR_EraseFromParent, /*InsnID*/0,
35409        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35410        // GIR_Coverage, 5161,
35411        GIR_Done,
35412      // Label 1715: @95741
35413      GIM_Try, /*On fail goto*//*Label 1716*/ 95790, // Rule ID 1764 //
35414        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_space,
35415        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35416        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35417        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35418        // MIs[0] size
35419        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
35420        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
35421        // (intrinsic_w_chain:{ *:[i32] } 2737:{ *:[iPTR] }, (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn)  =>  (SPACE:{ *:[i32] } (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn)
35422        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SPACE,
35423        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35424        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // size
35425        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
35426        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35427        GIR_EraseFromParent, /*InsnID*/0,
35428        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35429        // GIR_Coverage, 1764,
35430        GIR_Done,
35431      // Label 1716: @95790
35432      GIM_Try, /*On fail goto*//*Label 1717*/ 95849, // Rule ID 5153 //
35433        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_base,
35434        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
35435        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35436        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
35437        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
35438        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
35439        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
35440        // MIs[1] Operand 1
35441        // No operand predicates
35442        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35443        GIM_CheckIsSafeToFold, /*InsnID*/1,
35444        // (intrinsic_void 2544:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data)  =>  (MVE_VSTRW32_qi MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
35445        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_qi,
35446        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35447        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
35448        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35449        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35450        GIR_EraseFromParent, /*InsnID*/0,
35451        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35452        // GIR_Coverage, 5153,
35453        GIR_Done,
35454      // Label 1717: @95849
35455      GIM_Try, /*On fail goto*//*Label 1718*/ 95908, // Rule ID 5163 //
35456        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_base,
35457        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
35458        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35459        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
35460        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
35461        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
35462        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
35463        // MIs[1] Operand 1
35464        // No operand predicates
35465        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35466        GIM_CheckIsSafeToFold, /*InsnID*/1,
35467        // (intrinsic_void 2544:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data)  =>  (MVE_VSTRW32_qi MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
35468        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_qi,
35469        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35470        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
35471        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35472        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35473        GIR_EraseFromParent, /*InsnID*/0,
35474        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35475        // GIR_Coverage, 5163,
35476        GIR_Done,
35477      // Label 1718: @95908
35478      GIM_Try, /*On fail goto*//*Label 1719*/ 95967, // Rule ID 5167 //
35479        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_base,
35480        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
35481        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35482        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
35483        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
35484        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
35485        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
35486        // MIs[1] Operand 1
35487        // No operand predicates
35488        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35489        GIM_CheckIsSafeToFold, /*InsnID*/1,
35490        // (intrinsic_void 2544:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data)  =>  (MVE_VSTRD64_qi MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
35491        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_qi,
35492        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35493        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
35494        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35495        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35496        GIR_EraseFromParent, /*InsnID*/0,
35497        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35498        // GIR_Coverage, 5167,
35499        GIR_Done,
35500      // Label 1719: @95967
35501      GIM_Try, /*On fail goto*//*Label 1720*/ 96026, // Rule ID 5171 //
35502        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_base,
35503        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
35504        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35505        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
35506        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
35507        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
35508        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
35509        // MIs[1] Operand 1
35510        // No operand predicates
35511        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35512        GIM_CheckIsSafeToFold, /*InsnID*/1,
35513        // (intrinsic_void 2544:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data)  =>  (MVE_VSTRD64_qi MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
35514        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_qi,
35515        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35516        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
35517        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35518        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35519        GIR_EraseFromParent, /*InsnID*/0,
35520        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35521        // GIR_Coverage, 5171,
35522        GIR_Done,
35523      // Label 1720: @96026
35524      GIM_Try, /*On fail goto*//*Label 1721*/ 96089, // Rule ID 3 //
35525        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
35526        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sel,
35527        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35528        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35529        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35530        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35531        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
35532        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
35533        // (intrinsic_w_chain:{ *:[i32] } 2705:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
35534        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SEL,
35535        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35536        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35537        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35538        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35539        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35540        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35541        GIR_EraseFromParent, /*InsnID*/0,
35542        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35543        // GIR_Coverage, 3,
35544        GIR_Done,
35545      // Label 1721: @96089
35546      GIM_Try, /*On fail goto*//*Label 1722*/ 96152, // Rule ID 121 //
35547        GIM_CheckFeatures, GIFBS_IsARM,
35548        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sasx,
35549        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35550        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35551        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35552        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
35553        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
35554        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
35555        // (intrinsic_w_chain:{ *:[i32] } 2704:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35556        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SASX,
35557        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35558        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35559        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35560        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35561        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35562        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35563        GIR_EraseFromParent, /*InsnID*/0,
35564        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35565        // GIR_Coverage, 121,
35566        GIR_Done,
35567      // Label 1722: @96152
35568      GIM_Try, /*On fail goto*//*Label 1723*/ 96215, // Rule ID 122 //
35569        GIM_CheckFeatures, GIFBS_IsARM,
35570        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sadd16,
35571        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35572        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35573        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35574        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
35575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
35576        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
35577        // (intrinsic_w_chain:{ *:[i32] } 2702:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35578        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SADD16,
35579        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35580        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35581        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35582        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35583        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35584        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35585        GIR_EraseFromParent, /*InsnID*/0,
35586        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35587        // GIR_Coverage, 122,
35588        GIR_Done,
35589      // Label 1723: @96215
35590      GIM_Try, /*On fail goto*//*Label 1724*/ 96278, // Rule ID 123 //
35591        GIM_CheckFeatures, GIFBS_IsARM,
35592        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sadd8,
35593        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35594        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35595        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35596        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
35597        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
35598        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
35599        // (intrinsic_w_chain:{ *:[i32] } 2703:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35600        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SADD8,
35601        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35602        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35603        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35604        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35605        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35606        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35607        GIR_EraseFromParent, /*InsnID*/0,
35608        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35609        // GIR_Coverage, 123,
35610        GIR_Done,
35611      // Label 1724: @96278
35612      GIM_Try, /*On fail goto*//*Label 1725*/ 96341, // Rule ID 124 //
35613        GIM_CheckFeatures, GIFBS_IsARM,
35614        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssax,
35615        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35616        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35617        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35618        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
35619        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
35620        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
35621        // (intrinsic_w_chain:{ *:[i32] } 2740:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35622        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SSAX,
35623        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35624        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35625        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35626        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35627        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35628        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35629        GIR_EraseFromParent, /*InsnID*/0,
35630        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35631        // GIR_Coverage, 124,
35632        GIR_Done,
35633      // Label 1725: @96341
35634      GIM_Try, /*On fail goto*//*Label 1726*/ 96404, // Rule ID 125 //
35635        GIM_CheckFeatures, GIFBS_IsARM,
35636        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssub16,
35637        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35638        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35639        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35640        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
35641        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
35642        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
35643        // (intrinsic_w_chain:{ *:[i32] } 2741:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35644        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SSUB16,
35645        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35646        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35647        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35648        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35649        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35650        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35651        GIR_EraseFromParent, /*InsnID*/0,
35652        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35653        // GIR_Coverage, 125,
35654        GIR_Done,
35655      // Label 1726: @96404
35656      GIM_Try, /*On fail goto*//*Label 1727*/ 96467, // Rule ID 126 //
35657        GIM_CheckFeatures, GIFBS_IsARM,
35658        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssub8,
35659        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35660        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35661        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35662        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
35663        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
35664        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
35665        // (intrinsic_w_chain:{ *:[i32] } 2742:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35666        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SSUB8,
35667        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35668        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35669        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35670        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35671        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35672        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35673        GIR_EraseFromParent, /*InsnID*/0,
35674        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35675        // GIR_Coverage, 126,
35676        GIR_Done,
35677      // Label 1727: @96467
35678      GIM_Try, /*On fail goto*//*Label 1728*/ 96530, // Rule ID 127 //
35679        GIM_CheckFeatures, GIFBS_IsARM,
35680        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uasx,
35681        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35682        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35683        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35684        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
35685        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
35686        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
35687        // (intrinsic_w_chain:{ *:[i32] } 2755:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35688        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UASX,
35689        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35690        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35691        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35692        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35693        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35694        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35695        GIR_EraseFromParent, /*InsnID*/0,
35696        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35697        // GIR_Coverage, 127,
35698        GIR_Done,
35699      // Label 1728: @96530
35700      GIM_Try, /*On fail goto*//*Label 1729*/ 96593, // Rule ID 128 //
35701        GIM_CheckFeatures, GIFBS_IsARM,
35702        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uadd16,
35703        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35704        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35705        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35706        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
35707        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
35708        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
35709        // (intrinsic_w_chain:{ *:[i32] } 2753:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35710        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UADD16,
35711        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35712        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35713        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35714        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35715        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35716        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35717        GIR_EraseFromParent, /*InsnID*/0,
35718        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35719        // GIR_Coverage, 128,
35720        GIR_Done,
35721      // Label 1729: @96593
35722      GIM_Try, /*On fail goto*//*Label 1730*/ 96656, // Rule ID 129 //
35723        GIM_CheckFeatures, GIFBS_IsARM,
35724        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uadd8,
35725        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35726        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35727        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35728        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
35729        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
35730        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
35731        // (intrinsic_w_chain:{ *:[i32] } 2754:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35732        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UADD8,
35733        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35734        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35735        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35736        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35737        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35738        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35739        GIR_EraseFromParent, /*InsnID*/0,
35740        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35741        // GIR_Coverage, 129,
35742        GIR_Done,
35743      // Label 1730: @96656
35744      GIM_Try, /*On fail goto*//*Label 1731*/ 96719, // Rule ID 130 //
35745        GIM_CheckFeatures, GIFBS_IsARM,
35746        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usax,
35747        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35748        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35749        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35750        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
35751        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
35752        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
35753        // (intrinsic_w_chain:{ *:[i32] } 2773:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (USAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35754        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAX,
35755        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35756        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35757        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35758        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35759        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35760        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35761        GIR_EraseFromParent, /*InsnID*/0,
35762        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35763        // GIR_Coverage, 130,
35764        GIR_Done,
35765      // Label 1731: @96719
35766      GIM_Try, /*On fail goto*//*Label 1732*/ 96782, // Rule ID 131 //
35767        GIM_CheckFeatures, GIFBS_IsARM,
35768        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usub16,
35769        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35770        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35771        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35772        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
35773        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
35774        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
35775        // (intrinsic_w_chain:{ *:[i32] } 2774:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (USUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35776        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USUB16,
35777        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35778        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35779        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35780        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35781        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35782        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35783        GIR_EraseFromParent, /*InsnID*/0,
35784        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35785        // GIR_Coverage, 131,
35786        GIR_Done,
35787      // Label 1732: @96782
35788      GIM_Try, /*On fail goto*//*Label 1733*/ 96845, // Rule ID 132 //
35789        GIM_CheckFeatures, GIFBS_IsARM,
35790        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usub8,
35791        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35792        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35793        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35794        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
35795        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
35796        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
35797        // (intrinsic_w_chain:{ *:[i32] } 2775:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (USUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35798        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USUB8,
35799        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35800        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35801        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35802        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35803        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35804        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35805        GIR_EraseFromParent, /*InsnID*/0,
35806        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35807        // GIR_Coverage, 132,
35808        GIR_Done,
35809      // Label 1733: @96845
35810      GIM_Try, /*On fail goto*//*Label 1734*/ 96908, // Rule ID 438 //
35811        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
35812        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sel,
35813        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35814        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35815        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35816        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
35817        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
35818        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
35819        // (intrinsic_w_chain:{ *:[i32] } 2705:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (t2SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
35820        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SEL,
35821        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35822        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35823        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35824        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35825        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35826        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35827        GIR_EraseFromParent, /*InsnID*/0,
35828        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35829        // GIR_Coverage, 438,
35830        GIR_Done,
35831      // Label 1734: @96908
35832      GIM_Try, /*On fail goto*//*Label 1735*/ 96971, // Rule ID 451 //
35833        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
35834        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sasx,
35835        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35836        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35837        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35838        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
35839        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
35840        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
35841        // (intrinsic_w_chain:{ *:[i32] } 2704:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
35842        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SASX,
35843        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35844        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35845        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35846        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35847        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35848        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35849        GIR_EraseFromParent, /*InsnID*/0,
35850        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35851        // GIR_Coverage, 451,
35852        GIR_Done,
35853      // Label 1735: @96971
35854      GIM_Try, /*On fail goto*//*Label 1736*/ 97034, // Rule ID 452 //
35855        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
35856        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sadd16,
35857        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35858        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35859        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35860        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
35861        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
35862        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
35863        // (intrinsic_w_chain:{ *:[i32] } 2702:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
35864        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SADD16,
35865        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35866        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35867        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35868        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35869        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35870        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35871        GIR_EraseFromParent, /*InsnID*/0,
35872        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35873        // GIR_Coverage, 452,
35874        GIR_Done,
35875      // Label 1736: @97034
35876      GIM_Try, /*On fail goto*//*Label 1737*/ 97097, // Rule ID 453 //
35877        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
35878        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sadd8,
35879        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35880        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35881        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35882        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
35883        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
35884        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
35885        // (intrinsic_w_chain:{ *:[i32] } 2703:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
35886        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SADD8,
35887        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35888        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35889        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35890        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35891        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35892        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35893        GIR_EraseFromParent, /*InsnID*/0,
35894        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35895        // GIR_Coverage, 453,
35896        GIR_Done,
35897      // Label 1737: @97097
35898      GIM_Try, /*On fail goto*//*Label 1738*/ 97160, // Rule ID 454 //
35899        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
35900        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssax,
35901        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35902        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35903        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35904        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
35905        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
35906        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
35907        // (intrinsic_w_chain:{ *:[i32] } 2740:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
35908        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SSAX,
35909        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35910        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35911        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35912        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35913        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35914        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35915        GIR_EraseFromParent, /*InsnID*/0,
35916        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35917        // GIR_Coverage, 454,
35918        GIR_Done,
35919      // Label 1738: @97160
35920      GIM_Try, /*On fail goto*//*Label 1739*/ 97223, // Rule ID 455 //
35921        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
35922        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssub16,
35923        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35924        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35925        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35926        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
35927        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
35928        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
35929        // (intrinsic_w_chain:{ *:[i32] } 2741:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
35930        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SSUB16,
35931        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35932        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35933        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35934        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35935        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35936        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35937        GIR_EraseFromParent, /*InsnID*/0,
35938        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35939        // GIR_Coverage, 455,
35940        GIR_Done,
35941      // Label 1739: @97223
35942      GIM_Try, /*On fail goto*//*Label 1740*/ 97286, // Rule ID 456 //
35943        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
35944        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssub8,
35945        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35946        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35947        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35948        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
35949        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
35950        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
35951        // (intrinsic_w_chain:{ *:[i32] } 2742:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
35952        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SSUB8,
35953        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35954        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35955        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35956        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35957        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35958        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35959        GIR_EraseFromParent, /*InsnID*/0,
35960        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35961        // GIR_Coverage, 456,
35962        GIR_Done,
35963      // Label 1740: @97286
35964      GIM_Try, /*On fail goto*//*Label 1741*/ 97349, // Rule ID 457 //
35965        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
35966        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uasx,
35967        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35968        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35969        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35970        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
35971        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
35972        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
35973        // (intrinsic_w_chain:{ *:[i32] } 2755:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
35974        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UASX,
35975        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35976        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35977        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
35978        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35979        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35980        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35981        GIR_EraseFromParent, /*InsnID*/0,
35982        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35983        // GIR_Coverage, 457,
35984        GIR_Done,
35985      // Label 1741: @97349
35986      GIM_Try, /*On fail goto*//*Label 1742*/ 97412, // Rule ID 458 //
35987        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
35988        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uadd16,
35989        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
35990        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
35991        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35992        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
35993        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
35994        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
35995        // (intrinsic_w_chain:{ *:[i32] } 2753:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
35996        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UADD16,
35997        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
35998        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
35999        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
36000        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36001        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36002        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36003        GIR_EraseFromParent, /*InsnID*/0,
36004        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36005        // GIR_Coverage, 458,
36006        GIR_Done,
36007      // Label 1742: @97412
36008      GIM_Try, /*On fail goto*//*Label 1743*/ 97475, // Rule ID 459 //
36009        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
36010        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uadd8,
36011        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
36012        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
36013        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36014        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
36015        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
36016        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
36017        // (intrinsic_w_chain:{ *:[i32] } 2754:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36018        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UADD8,
36019        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
36020        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
36021        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
36022        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36023        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36024        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36025        GIR_EraseFromParent, /*InsnID*/0,
36026        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36027        // GIR_Coverage, 459,
36028        GIR_Done,
36029      // Label 1743: @97475
36030      GIM_Try, /*On fail goto*//*Label 1744*/ 97538, // Rule ID 460 //
36031        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
36032        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usax,
36033        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
36034        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
36035        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36036        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
36037        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
36038        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
36039        // (intrinsic_w_chain:{ *:[i32] } 2773:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2USAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36040        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAX,
36041        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
36042        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
36043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
36044        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36045        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36046        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36047        GIR_EraseFromParent, /*InsnID*/0,
36048        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36049        // GIR_Coverage, 460,
36050        GIR_Done,
36051      // Label 1744: @97538
36052      GIM_Try, /*On fail goto*//*Label 1745*/ 97601, // Rule ID 461 //
36053        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
36054        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usub16,
36055        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
36056        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
36057        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36058        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
36059        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
36060        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
36061        // (intrinsic_w_chain:{ *:[i32] } 2774:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2USUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36062        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USUB16,
36063        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
36064        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
36065        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
36066        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36067        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36068        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36069        GIR_EraseFromParent, /*InsnID*/0,
36070        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36071        // GIR_Coverage, 461,
36072        GIR_Done,
36073      // Label 1745: @97601
36074      GIM_Try, /*On fail goto*//*Label 1746*/ 97664, // Rule ID 462 //
36075        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
36076        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usub8,
36077        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
36078        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
36079        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36080        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
36081        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
36082        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
36083        // (intrinsic_w_chain:{ *:[i32] } 2775:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2USUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36084        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USUB8,
36085        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
36086        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
36087        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
36088        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36089        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36090        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36091        GIR_EraseFromParent, /*InsnID*/0,
36092        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36093        // GIR_Coverage, 462,
36094        GIR_Done,
36095      // Label 1746: @97664
36096      GIM_Reject,
36097    // Label 1711: @97665
36098    GIM_Try, /*On fail goto*//*Label 1747*/ 97943,
36099      GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
36100      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vstr_scatter_base_wb,
36101      GIM_Try, /*On fail goto*//*Label 1748*/ 97741, // Rule ID 5155 //
36102        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36103        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
36104        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36105        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
36106        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36107        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
36108        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
36109        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
36110        // MIs[1] Operand 1
36111        // No operand predicates
36112        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
36113        GIM_CheckIsSafeToFold, /*InsnID*/1,
36114        // (intrinsic_w_chain:{ *:[v4i32] } 2546:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data)  =>  (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
36115        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_qi_pre,
36116        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wb
36117        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // data
36118        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
36119        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
36120        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
36121        GIR_EraseFromParent, /*InsnID*/0,
36122        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36123        // GIR_Coverage, 5155,
36124        GIR_Done,
36125      // Label 1748: @97741
36126      GIM_Try, /*On fail goto*//*Label 1749*/ 97808, // Rule ID 5165 //
36127        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36128        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
36129        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36130        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
36131        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36132        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
36133        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
36134        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
36135        // MIs[1] Operand 1
36136        // No operand predicates
36137        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
36138        GIM_CheckIsSafeToFold, /*InsnID*/1,
36139        // (intrinsic_w_chain:{ *:[v4i32] } 2546:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data)  =>  (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
36140        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_qi_pre,
36141        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wb
36142        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // data
36143        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
36144        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
36145        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
36146        GIR_EraseFromParent, /*InsnID*/0,
36147        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36148        // GIR_Coverage, 5165,
36149        GIR_Done,
36150      // Label 1749: @97808
36151      GIM_Try, /*On fail goto*//*Label 1750*/ 97875, // Rule ID 5169 //
36152        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
36153        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
36154        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36155        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
36156        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36157        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
36158        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
36159        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
36160        // MIs[1] Operand 1
36161        // No operand predicates
36162        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
36163        GIM_CheckIsSafeToFold, /*InsnID*/1,
36164        // (intrinsic_w_chain:{ *:[v2i64] } 2546:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data)  =>  (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
36165        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_qi_pre,
36166        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wb
36167        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // data
36168        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
36169        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
36170        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
36171        GIR_EraseFromParent, /*InsnID*/0,
36172        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36173        // GIR_Coverage, 5169,
36174        GIR_Done,
36175      // Label 1750: @97875
36176      GIM_Try, /*On fail goto*//*Label 1751*/ 97942, // Rule ID 5173 //
36177        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
36178        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
36179        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36180        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
36181        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36182        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
36183        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
36184        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
36185        // MIs[1] Operand 1
36186        // No operand predicates
36187        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
36188        GIM_CheckIsSafeToFold, /*InsnID*/1,
36189        // (intrinsic_w_chain:{ *:[v2i64] } 2546:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data)  =>  (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
36190        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_qi_pre,
36191        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wb
36192        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // data
36193        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
36194        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
36195        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
36196        GIR_EraseFromParent, /*InsnID*/0,
36197        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36198        // GIR_Coverage, 5173,
36199        GIR_Done,
36200      // Label 1751: @97942
36201      GIM_Reject,
36202    // Label 1747: @97943
36203    GIM_Try, /*On fail goto*//*Label 1752*/ 99280,
36204      GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
36205      GIM_Try, /*On fail goto*//*Label 1753*/ 98018, // Rule ID 5043 //
36206        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
36207        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
36208        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
36209        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36210        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36211        // MIs[0] base
36212        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36213        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
36214        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
36215        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36216        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
36217        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36218        // (intrinsic_void 2548:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRH16_rq_u MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36219        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH16_rq_u,
36220        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36221        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36222        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36223        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36224        GIR_EraseFromParent, /*InsnID*/0,
36225        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36226        // GIR_Coverage, 5043,
36227        GIR_Done,
36228      // Label 1753: @98018
36229      GIM_Try, /*On fail goto*//*Label 1754*/ 98088, // Rule ID 5044 //
36230        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
36231        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
36232        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
36233        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36234        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36235        // MIs[0] base
36236        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36237        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
36238        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
36239        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36240        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
36241        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
36242        // (intrinsic_void 2548:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSTRH16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36243        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH16_rq,
36244        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36245        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36246        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36247        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36248        GIR_EraseFromParent, /*InsnID*/0,
36249        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36250        // GIR_Coverage, 5044,
36251        GIR_Done,
36252      // Label 1754: @98088
36253      GIM_Try, /*On fail goto*//*Label 1755*/ 98158, // Rule ID 5047 //
36254        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
36255        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
36256        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
36257        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36258        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36259        // MIs[0] base
36260        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36261        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
36262        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
36263        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36264        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
36265        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36266        // (intrinsic_void 2548:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, MQPR:{ *:[v16i8] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRB8_rq MQPR:{ *:[v16i8] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
36267        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRB8_rq,
36268        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36269        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36270        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36271        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36272        GIR_EraseFromParent, /*InsnID*/0,
36273        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36274        // GIR_Coverage, 5047,
36275        GIR_Done,
36276      // Label 1755: @98158
36277      GIM_Try, /*On fail goto*//*Label 1756*/ 98228, // Rule ID 5127 //
36278        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
36279        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
36280        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
36281        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36282        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36283        // MIs[0] base
36284        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36285        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
36286        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
36287        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36288        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
36289        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36290        // (intrinsic_void 2548:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRB16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36291        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRB16_rq,
36292        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36293        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36294        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36295        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36296        GIR_EraseFromParent, /*InsnID*/0,
36297        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36298        // GIR_Coverage, 5127,
36299        GIR_Done,
36300      // Label 1756: @98228
36301      GIM_Try, /*On fail goto*//*Label 1757*/ 98298, // Rule ID 5129 //
36302        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
36303        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
36304        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36305        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36306        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36307        // MIs[0] base
36308        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36309        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
36310        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
36311        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36312        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
36313        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36314        // (intrinsic_void 2548:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRB32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36315        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRB32_rq,
36316        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36317        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36318        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36319        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36320        GIR_EraseFromParent, /*InsnID*/0,
36321        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36322        // GIR_Coverage, 5129,
36323        GIR_Done,
36324      // Label 1757: @98298
36325      GIM_Try, /*On fail goto*//*Label 1758*/ 98368, // Rule ID 5131 //
36326        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
36327        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
36328        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
36329        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36330        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36331        // MIs[0] base
36332        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36333        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
36334        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
36335        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36336        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
36337        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36338        // (intrinsic_void 2548:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRH16_rq_u MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36339        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH16_rq_u,
36340        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36341        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36342        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36343        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36344        GIR_EraseFromParent, /*InsnID*/0,
36345        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36346        // GIR_Coverage, 5131,
36347        GIR_Done,
36348      // Label 1758: @98368
36349      GIM_Try, /*On fail goto*//*Label 1759*/ 98438, // Rule ID 5132 //
36350        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
36351        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
36352        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
36353        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36354        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36355        // MIs[0] base
36356        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36357        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
36358        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
36359        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36360        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
36361        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
36362        // (intrinsic_void 2548:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSTRH16_rq MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36363        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH16_rq,
36364        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36365        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36366        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36367        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36368        GIR_EraseFromParent, /*InsnID*/0,
36369        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36370        // GIR_Coverage, 5132,
36371        GIR_Done,
36372      // Label 1759: @98438
36373      GIM_Try, /*On fail goto*//*Label 1760*/ 98508, // Rule ID 5135 //
36374        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
36375        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
36376        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36377        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36378        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36379        // MIs[0] base
36380        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36381        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
36382        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
36383        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36384        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
36385        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36386        // (intrinsic_void 2548:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRH32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36387        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH32_rq_u,
36388        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36389        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36390        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36391        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36392        GIR_EraseFromParent, /*InsnID*/0,
36393        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36394        // GIR_Coverage, 5135,
36395        GIR_Done,
36396      // Label 1760: @98508
36397      GIM_Try, /*On fail goto*//*Label 1761*/ 98578, // Rule ID 5136 //
36398        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
36399        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
36400        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36401        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36402        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36403        // MIs[0] base
36404        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36405        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
36406        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
36407        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36408        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
36409        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
36410        // (intrinsic_void 2548:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VSTRH32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36411        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH32_rq,
36412        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36413        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36414        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36415        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36416        GIR_EraseFromParent, /*InsnID*/0,
36417        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36418        // GIR_Coverage, 5136,
36419        GIR_Done,
36420      // Label 1761: @98578
36421      GIM_Try, /*On fail goto*//*Label 1762*/ 98648, // Rule ID 5139 //
36422        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
36423        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
36424        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36425        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36426        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36427        // MIs[0] base
36428        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36429        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
36430        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
36431        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36432        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
36433        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36434        // (intrinsic_void 2548:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRW32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36435        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_rq_u,
36436        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36437        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36438        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36439        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36440        GIR_EraseFromParent, /*InsnID*/0,
36441        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36442        // GIR_Coverage, 5139,
36443        GIR_Done,
36444      // Label 1762: @98648
36445      GIM_Try, /*On fail goto*//*Label 1763*/ 98718, // Rule ID 5140 //
36446        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
36447        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
36448        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36449        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36450        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36451        // MIs[0] base
36452        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36453        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
36454        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
36455        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36456        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
36457        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
36458        // (intrinsic_void 2548:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] })  =>  (MVE_VSTRW32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36459        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_rq,
36460        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36461        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36462        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36463        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36464        GIR_EraseFromParent, /*InsnID*/0,
36465        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36466        // GIR_Coverage, 5140,
36467        GIR_Done,
36468      // Label 1763: @98718
36469      GIM_Try, /*On fail goto*//*Label 1764*/ 98788, // Rule ID 5143 //
36470        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
36471        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
36472        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36473        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36474        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36475        // MIs[0] base
36476        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36477        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
36478        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
36479        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36480        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
36481        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36482        // (intrinsic_void 2548:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRW32_rq_u MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36483        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_rq_u,
36484        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36485        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36486        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36487        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36488        GIR_EraseFromParent, /*InsnID*/0,
36489        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36490        // GIR_Coverage, 5143,
36491        GIR_Done,
36492      // Label 1764: @98788
36493      GIM_Try, /*On fail goto*//*Label 1765*/ 98858, // Rule ID 5144 //
36494        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
36495        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
36496        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36497        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36498        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36499        // MIs[0] base
36500        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36501        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
36502        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
36503        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36504        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
36505        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
36506        // (intrinsic_void 2548:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] })  =>  (MVE_VSTRW32_rq MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36507        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_rq,
36508        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36509        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36510        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36511        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36512        GIR_EraseFromParent, /*InsnID*/0,
36513        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36514        // GIR_Coverage, 5144,
36515        GIR_Done,
36516      // Label 1765: @98858
36517      GIM_Try, /*On fail goto*//*Label 1766*/ 98928, // Rule ID 5147 //
36518        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
36519        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
36520        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
36521        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36522        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36523        // MIs[0] base
36524        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36525        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
36526        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
36527        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36528        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
36529        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36530        // (intrinsic_void 2548:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VSTRD64_rq_u MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
36531        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_rq_u,
36532        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36533        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36534        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36535        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36536        GIR_EraseFromParent, /*InsnID*/0,
36537        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36538        // GIR_Coverage, 5147,
36539        GIR_Done,
36540      // Label 1766: @98928
36541      GIM_Try, /*On fail goto*//*Label 1767*/ 98998, // Rule ID 5148 //
36542        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
36543        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
36544        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
36545        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36546        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36547        // MIs[0] base
36548        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36549        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
36550        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
36551        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36552        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
36553        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 3,
36554        // (intrinsic_void 2548:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 3:{ *:[i32] })  =>  (MVE_VSTRD64_rq MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
36555        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_rq,
36556        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
36557        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
36558        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
36559        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36560        GIR_EraseFromParent, /*InsnID*/0,
36561        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36562        // GIR_Coverage, 5148,
36563        GIR_Done,
36564      // Label 1767: @98998
36565      GIM_Try, /*On fail goto*//*Label 1768*/ 99070, // Rule ID 265 //
36566        GIM_CheckFeatures, GIFBS_IsARM,
36567        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcrr,
36568        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36569        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36570        // MIs[0] cop
36571        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36572        // MIs[0] opc1
36573        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36574        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
36575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRnopcRegClassID,
36576        // MIs[0] CRm
36577        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36578        // (intrinsic_void 2351:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)  =>  (MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
36579        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCRR,
36580        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
36581        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
36582        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
36583        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2
36584        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
36585        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36586        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36587        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36588        GIR_EraseFromParent, /*InsnID*/0,
36589        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36590        // GIR_Coverage, 265,
36591        GIR_Done,
36592      // Label 1768: @99070
36593      GIM_Try, /*On fail goto*//*Label 1769*/ 99135, // Rule ID 266 //
36594        GIM_CheckFeatures, GIFBS_IsARM_PreV8,
36595        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcrr2,
36596        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36597        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36598        // MIs[0] cop
36599        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36600        // MIs[0] opc1
36601        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36602        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
36603        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRnopcRegClassID,
36604        // MIs[0] CRm
36605        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36606        // (intrinsic_void 2352:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)  =>  (MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
36607        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCRR2,
36608        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
36609        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
36610        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
36611        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2
36612        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
36613        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36614        GIR_EraseFromParent, /*InsnID*/0,
36615        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36616        // GIR_Coverage, 266,
36617        GIR_Done,
36618      // Label 1769: @99135
36619      GIM_Try, /*On fail goto*//*Label 1770*/ 99207, // Rule ID 612 //
36620        GIM_CheckFeatures, GIFBS_IsThumb2,
36621        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcrr,
36622        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36623        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36624        // MIs[0] cop
36625        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36626        // MIs[0] opc1
36627        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36628        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
36629        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
36630        // MIs[0] CRm
36631        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36632        // (intrinsic_void 2351:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)  =>  (t2MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
36633        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCRR,
36634        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
36635        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
36636        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
36637        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2
36638        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
36639        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36640        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36641        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36642        GIR_EraseFromParent, /*InsnID*/0,
36643        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36644        // GIR_Coverage, 612,
36645        GIR_Done,
36646      // Label 1770: @99207
36647      GIM_Try, /*On fail goto*//*Label 1771*/ 99279, // Rule ID 613 //
36648        GIM_CheckFeatures, GIFBS_IsThumb2_PreV8,
36649        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcrr2,
36650        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36651        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36652        // MIs[0] cop
36653        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36654        // MIs[0] opc1
36655        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36656        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
36657        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
36658        // MIs[0] CRm
36659        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36660        // (intrinsic_void 2352:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)  =>  (t2MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
36661        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCRR2,
36662        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
36663        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
36664        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
36665        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2
36666        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
36667        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36668        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36669        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36670        GIR_EraseFromParent, /*InsnID*/0,
36671        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36672        // GIR_Coverage, 613,
36673        GIR_Done,
36674      // Label 1771: @99279
36675      GIM_Reject,
36676    // Label 1752: @99280
36677    GIM_Try, /*On fail goto*//*Label 1772*/ 103120,
36678      GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
36679      GIM_Try, /*On fail goto*//*Label 1773*/ 99354, // Rule ID 253 //
36680        GIM_CheckFeatures, GIFBS_IsARM_PreV8,
36681        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_cdp,
36682        // MIs[0] cop
36683        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36684        // MIs[0] opc1
36685        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36686        // MIs[0] CRd
36687        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
36688        // MIs[0] CRn
36689        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
36690        // MIs[0] CRm
36691        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36692        // MIs[0] opc2
36693        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
36694        // (intrinsic_void 2319:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
36695        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CDP,
36696        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
36697        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
36698        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // CRd
36699        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
36700        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
36701        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
36702        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36703        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36704        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36705        GIR_EraseFromParent, /*InsnID*/0,
36706        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36707        // GIR_Coverage, 253,
36708        GIR_Done,
36709      // Label 1773: @99354
36710      GIM_Try, /*On fail goto*//*Label 1774*/ 99416, // Rule ID 254 //
36711        GIM_CheckFeatures, GIFBS_IsARM_PreV8,
36712        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_cdp2,
36713        // MIs[0] cop
36714        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36715        // MIs[0] opc1
36716        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36717        // MIs[0] CRd
36718        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
36719        // MIs[0] CRn
36720        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
36721        // MIs[0] CRm
36722        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36723        // MIs[0] opc2
36724        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
36725        // (intrinsic_void 2320:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
36726        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CDP2,
36727        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
36728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
36729        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // CRd
36730        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
36731        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
36732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
36733        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36734        GIR_EraseFromParent, /*InsnID*/0,
36735        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36736        // GIR_Coverage, 254,
36737        GIR_Done,
36738      // Label 1774: @99416
36739      GIM_Try, /*On fail goto*//*Label 1775*/ 99485, // Rule ID 614 //
36740        GIM_CheckFeatures, GIFBS_IsThumb2_PreV8,
36741        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_cdp,
36742        // MIs[0] cop
36743        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36744        // MIs[0] opc1
36745        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36746        // MIs[0] CRd
36747        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
36748        // MIs[0] CRn
36749        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
36750        // MIs[0] CRm
36751        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36752        // MIs[0] opc2
36753        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
36754        // (intrinsic_void 2319:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (t2CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
36755        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CDP,
36756        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
36757        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
36758        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // CRd
36759        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
36760        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
36761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
36762        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36763        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36764        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36765        GIR_EraseFromParent, /*InsnID*/0,
36766        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36767        // GIR_Coverage, 614,
36768        GIR_Done,
36769      // Label 1775: @99485
36770      GIM_Try, /*On fail goto*//*Label 1776*/ 99554, // Rule ID 615 //
36771        GIM_CheckFeatures, GIFBS_IsThumb2_PreV8,
36772        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_cdp2,
36773        // MIs[0] cop
36774        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36775        // MIs[0] opc1
36776        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36777        // MIs[0] CRd
36778        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
36779        // MIs[0] CRn
36780        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
36781        // MIs[0] CRm
36782        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36783        // MIs[0] opc2
36784        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
36785        // (intrinsic_void 2320:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (t2CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
36786        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CDP2,
36787        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
36788        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
36789        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // CRd
36790        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
36791        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
36792        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
36793        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36794        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36795        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36796        GIR_EraseFromParent, /*InsnID*/0,
36797        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36798        // GIR_Coverage, 615,
36799        GIR_Done,
36800      // Label 1776: @99554
36801      GIM_Try, /*On fail goto*//*Label 1777*/ 99632, // Rule ID 5037 //
36802        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36803        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
36804        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
36805        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36806        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36807        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36808        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36809        // MIs[0] base
36810        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36811        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36812        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36813        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
36814        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36815        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
36816        // (intrinsic_w_chain:{ *:[v8i16] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36817        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u,
36818        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36819        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36820        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36821        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36822        GIR_EraseFromParent, /*InsnID*/0,
36823        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36824        // GIR_Coverage, 5037,
36825        GIR_Done,
36826      // Label 1777: @99632
36827      GIM_Try, /*On fail goto*//*Label 1778*/ 99710, // Rule ID 5038 //
36828        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36829        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
36830        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
36831        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36832        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36833        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36834        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36835        // MIs[0] base
36836        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36837        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36838        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36839        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
36840        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
36841        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
36842        // (intrinsic_w_chain:{ *:[v8i16] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36843        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq,
36844        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36845        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36846        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36847        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36848        GIR_EraseFromParent, /*InsnID*/0,
36849        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36850        // GIR_Coverage, 5038,
36851        GIR_Done,
36852      // Label 1778: @99710
36853      GIM_Try, /*On fail goto*//*Label 1779*/ 99788, // Rule ID 5041 //
36854        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36855        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
36856        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
36857        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36858        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36859        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36860        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36861        // MIs[0] base
36862        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36863        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36864        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36865        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
36866        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36867        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
36868        // (intrinsic_w_chain:{ *:[v16i8] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
36869        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBU8_rq,
36870        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36871        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36872        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36873        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36874        GIR_EraseFromParent, /*InsnID*/0,
36875        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36876        // GIR_Coverage, 5041,
36877        GIR_Done,
36878      // Label 1779: @99788
36879      GIM_Try, /*On fail goto*//*Label 1780*/ 99866, // Rule ID 5049 //
36880        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36881        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
36882        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
36883        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36884        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36885        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36886        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36887        // MIs[0] base
36888        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36889        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36890        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36891        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
36892        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36893        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
36894        // (intrinsic_w_chain:{ *:[v16i8] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
36895        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBU8_rq,
36896        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36897        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36898        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36899        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36900        GIR_EraseFromParent, /*InsnID*/0,
36901        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36902        // GIR_Coverage, 5049,
36903        GIR_Done,
36904      // Label 1780: @99866
36905      GIM_Try, /*On fail goto*//*Label 1781*/ 99944, // Rule ID 5051 //
36906        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36907        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
36908        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
36909        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36910        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36911        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36912        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36913        // MIs[0] base
36914        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36915        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36916        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36917        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
36918        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36919        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
36920        // (intrinsic_w_chain:{ *:[v8i16] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRBU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36921        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBU16_rq,
36922        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36923        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36924        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36925        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36926        GIR_EraseFromParent, /*InsnID*/0,
36927        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36928        // GIR_Coverage, 5051,
36929        GIR_Done,
36930      // Label 1781: @99944
36931      GIM_Try, /*On fail goto*//*Label 1782*/ 100022, // Rule ID 5053 //
36932        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36933        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
36934        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
36935        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36936        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36937        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36938        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36939        // MIs[0] base
36940        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36941        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36942        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36943        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
36944        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36945        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
36946        // (intrinsic_w_chain:{ *:[v8i16] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRBS16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36947        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBS16_rq,
36948        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36949        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36950        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36951        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36952        GIR_EraseFromParent, /*InsnID*/0,
36953        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36954        // GIR_Coverage, 5053,
36955        GIR_Done,
36956      // Label 1782: @100022
36957      GIM_Try, /*On fail goto*//*Label 1783*/ 100100, // Rule ID 5055 //
36958        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36959        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36960        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36961        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36962        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36963        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36964        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36965        // MIs[0] base
36966        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36967        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36968        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36969        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
36970        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36971        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
36972        // (intrinsic_w_chain:{ *:[v4i32] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRBU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36973        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBU32_rq,
36974        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36975        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36976        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36977        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36978        GIR_EraseFromParent, /*InsnID*/0,
36979        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36980        // GIR_Coverage, 5055,
36981        GIR_Done,
36982      // Label 1783: @100100
36983      GIM_Try, /*On fail goto*//*Label 1784*/ 100178, // Rule ID 5057 //
36984        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36985        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36986        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36987        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36988        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36989        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36990        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36991        // MIs[0] base
36992        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36993        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36994        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36995        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
36996        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36997        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
36998        // (intrinsic_w_chain:{ *:[v4i32] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRBS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36999        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBS32_rq,
37000        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37001        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37002        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37003        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37004        GIR_EraseFromParent, /*InsnID*/0,
37005        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37006        // GIR_Coverage, 5057,
37007        GIR_Done,
37008      // Label 1784: @100178
37009      GIM_Try, /*On fail goto*//*Label 1785*/ 100256, // Rule ID 5059 //
37010        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37011        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
37012        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
37013        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37014        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37015        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37016        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37017        // MIs[0] base
37018        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37019        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37020        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37021        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
37022        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
37023        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
37024        // (intrinsic_w_chain:{ *:[v8i16] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37025        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u,
37026        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37027        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37028        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37029        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37030        GIR_EraseFromParent, /*InsnID*/0,
37031        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37032        // GIR_Coverage, 5059,
37033        GIR_Done,
37034      // Label 1785: @100256
37035      GIM_Try, /*On fail goto*//*Label 1786*/ 100334, // Rule ID 5060 //
37036        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37037        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
37038        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
37039        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37040        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37041        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37042        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37043        // MIs[0] base
37044        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37045        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37046        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37047        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
37048        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
37049        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
37050        // (intrinsic_w_chain:{ *:[v8i16] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37051        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq,
37052        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37053        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37054        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37055        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37056        GIR_EraseFromParent, /*InsnID*/0,
37057        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37058        // GIR_Coverage, 5060,
37059        GIR_Done,
37060      // Label 1786: @100334
37061      GIM_Try, /*On fail goto*//*Label 1787*/ 100412, // Rule ID 5063 //
37062        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37063        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
37064        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
37065        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37066        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37067        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37068        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37069        // MIs[0] base
37070        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37071        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37072        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37073        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
37074        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
37075        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
37076        // (intrinsic_w_chain:{ *:[v8i16] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37077        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u,
37078        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37079        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37080        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37081        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37082        GIR_EraseFromParent, /*InsnID*/0,
37083        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37084        // GIR_Coverage, 5063,
37085        GIR_Done,
37086      // Label 1787: @100412
37087      GIM_Try, /*On fail goto*//*Label 1788*/ 100490, // Rule ID 5064 //
37088        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37089        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
37090        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
37091        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37092        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37093        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37094        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37095        // MIs[0] base
37096        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37097        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37098        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37099        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
37100        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
37101        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
37102        // (intrinsic_w_chain:{ *:[v8i16] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37103        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq,
37104        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37107        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37108        GIR_EraseFromParent, /*InsnID*/0,
37109        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37110        // GIR_Coverage, 5064,
37111        GIR_Done,
37112      // Label 1788: @100490
37113      GIM_Try, /*On fail goto*//*Label 1789*/ 100568, // Rule ID 5067 //
37114        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37115        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
37116        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
37117        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37118        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37119        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37120        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37121        // MIs[0] base
37122        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37123        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37124        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37125        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
37126        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
37127        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
37128        // (intrinsic_w_chain:{ *:[v8i16] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37129        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u,
37130        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37132        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37133        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37134        GIR_EraseFromParent, /*InsnID*/0,
37135        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37136        // GIR_Coverage, 5067,
37137        GIR_Done,
37138      // Label 1789: @100568
37139      GIM_Try, /*On fail goto*//*Label 1790*/ 100646, // Rule ID 5068 //
37140        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37141        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
37142        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
37143        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37144        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37145        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37146        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37147        // MIs[0] base
37148        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37149        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37150        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37151        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
37152        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
37153        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
37154        // (intrinsic_w_chain:{ *:[v8i16] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37155        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq,
37156        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37157        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37158        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37159        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37160        GIR_EraseFromParent, /*InsnID*/0,
37161        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37162        // GIR_Coverage, 5068,
37163        GIR_Done,
37164      // Label 1790: @100646
37165      GIM_Try, /*On fail goto*//*Label 1791*/ 100724, // Rule ID 5071 //
37166        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37167        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
37168        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
37169        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37170        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37171        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37172        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37173        // MIs[0] base
37174        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37175        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37176        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37177        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
37178        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
37179        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
37180        // (intrinsic_w_chain:{ *:[v8f16] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37181        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u,
37182        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37183        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37184        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37185        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37186        GIR_EraseFromParent, /*InsnID*/0,
37187        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37188        // GIR_Coverage, 5071,
37189        GIR_Done,
37190      // Label 1791: @100724
37191      GIM_Try, /*On fail goto*//*Label 1792*/ 100802, // Rule ID 5072 //
37192        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37193        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
37194        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
37195        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37196        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37197        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37198        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37199        // MIs[0] base
37200        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37201        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37202        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37203        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
37204        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
37205        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
37206        // (intrinsic_w_chain:{ *:[v8f16] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37207        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq,
37208        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37209        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37211        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37212        GIR_EraseFromParent, /*InsnID*/0,
37213        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37214        // GIR_Coverage, 5072,
37215        GIR_Done,
37216      // Label 1792: @100802
37217      GIM_Try, /*On fail goto*//*Label 1793*/ 100880, // Rule ID 5075 //
37218        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37219        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
37220        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
37221        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37222        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37223        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37224        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37225        // MIs[0] base
37226        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37227        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37228        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37229        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
37230        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
37231        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
37232        // (intrinsic_w_chain:{ *:[v8f16] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37233        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u,
37234        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37235        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37236        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37237        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37238        GIR_EraseFromParent, /*InsnID*/0,
37239        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37240        // GIR_Coverage, 5075,
37241        GIR_Done,
37242      // Label 1793: @100880
37243      GIM_Try, /*On fail goto*//*Label 1794*/ 100958, // Rule ID 5076 //
37244        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37245        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
37246        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
37247        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37248        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37249        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37250        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37251        // MIs[0] base
37252        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37253        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37254        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37255        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
37256        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
37257        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
37258        // (intrinsic_w_chain:{ *:[v8f16] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37259        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq,
37260        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37261        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37262        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37263        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37264        GIR_EraseFromParent, /*InsnID*/0,
37265        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37266        // GIR_Coverage, 5076,
37267        GIR_Done,
37268      // Label 1794: @100958
37269      GIM_Try, /*On fail goto*//*Label 1795*/ 101036, // Rule ID 5079 //
37270        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37271        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37272        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37273        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37274        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37275        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37276        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37277        // MIs[0] base
37278        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37279        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37280        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37281        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
37282        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
37283        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
37284        // (intrinsic_w_chain:{ *:[v4i32] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37285        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU32_rq_u,
37286        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37287        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37288        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37289        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37290        GIR_EraseFromParent, /*InsnID*/0,
37291        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37292        // GIR_Coverage, 5079,
37293        GIR_Done,
37294      // Label 1795: @101036
37295      GIM_Try, /*On fail goto*//*Label 1796*/ 101114, // Rule ID 5080 //
37296        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37297        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37298        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37299        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37300        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37301        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37302        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37303        // MIs[0] base
37304        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37305        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37306        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37307        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
37308        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
37309        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
37310        // (intrinsic_w_chain:{ *:[v4i32] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRHU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37311        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU32_rq,
37312        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37313        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37314        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37315        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37316        GIR_EraseFromParent, /*InsnID*/0,
37317        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37318        // GIR_Coverage, 5080,
37319        GIR_Done,
37320      // Label 1796: @101114
37321      GIM_Try, /*On fail goto*//*Label 1797*/ 101192, // Rule ID 5083 //
37322        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37323        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37324        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37325        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37326        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37327        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37328        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37329        // MIs[0] base
37330        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37331        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37332        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37333        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
37334        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
37335        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
37336        // (intrinsic_w_chain:{ *:[v4i32] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHS32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37337        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHS32_rq_u,
37338        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37339        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37340        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37341        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37342        GIR_EraseFromParent, /*InsnID*/0,
37343        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37344        // GIR_Coverage, 5083,
37345        GIR_Done,
37346      // Label 1797: @101192
37347      GIM_Try, /*On fail goto*//*Label 1798*/ 101270, // Rule ID 5084 //
37348        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37349        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37350        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37351        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37352        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37353        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37354        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37355        // MIs[0] base
37356        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37357        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37358        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37359        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
37360        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
37361        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
37362        // (intrinsic_w_chain:{ *:[v4i32] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRHS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37363        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHS32_rq,
37364        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37365        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37366        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37367        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37368        GIR_EraseFromParent, /*InsnID*/0,
37369        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37370        // GIR_Coverage, 5084,
37371        GIR_Done,
37372      // Label 1798: @101270
37373      GIM_Try, /*On fail goto*//*Label 1799*/ 101348, // Rule ID 5087 //
37374        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37375        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37376        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37377        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37378        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37379        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37380        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37381        // MIs[0] base
37382        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37383        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37384        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37385        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
37386        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
37387        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
37388        // (intrinsic_w_chain:{ *:[v4i32] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37389        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u,
37390        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37391        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37392        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37393        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37394        GIR_EraseFromParent, /*InsnID*/0,
37395        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37396        // GIR_Coverage, 5087,
37397        GIR_Done,
37398      // Label 1799: @101348
37399      GIM_Try, /*On fail goto*//*Label 1800*/ 101426, // Rule ID 5088 //
37400        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37401        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37402        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37403        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37404        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37405        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37406        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37407        // MIs[0] base
37408        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37409        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37410        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37411        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
37412        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
37413        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
37414        // (intrinsic_w_chain:{ *:[v4i32] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37415        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq,
37416        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37417        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37418        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37419        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37420        GIR_EraseFromParent, /*InsnID*/0,
37421        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37422        // GIR_Coverage, 5088,
37423        GIR_Done,
37424      // Label 1800: @101426
37425      GIM_Try, /*On fail goto*//*Label 1801*/ 101504, // Rule ID 5091 //
37426        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37427        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37428        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37429        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37430        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37431        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37432        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37433        // MIs[0] base
37434        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37435        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37436        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37437        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
37438        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
37439        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
37440        // (intrinsic_w_chain:{ *:[v4i32] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37441        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u,
37442        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37443        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37444        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37445        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37446        GIR_EraseFromParent, /*InsnID*/0,
37447        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37448        // GIR_Coverage, 5091,
37449        GIR_Done,
37450      // Label 1801: @101504
37451      GIM_Try, /*On fail goto*//*Label 1802*/ 101582, // Rule ID 5092 //
37452        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37453        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37454        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37455        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37456        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37457        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37458        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37459        // MIs[0] base
37460        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37461        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37462        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37463        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
37464        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
37465        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
37466        // (intrinsic_w_chain:{ *:[v4i32] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37467        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq,
37468        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37469        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37470        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37471        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37472        GIR_EraseFromParent, /*InsnID*/0,
37473        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37474        // GIR_Coverage, 5092,
37475        GIR_Done,
37476      // Label 1802: @101582
37477      GIM_Try, /*On fail goto*//*Label 1803*/ 101660, // Rule ID 5095 //
37478        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37479        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37480        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37481        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37482        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37483        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37484        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37485        // MIs[0] base
37486        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37487        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37488        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37489        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
37490        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
37491        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
37492        // (intrinsic_w_chain:{ *:[v4i32] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37493        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u,
37494        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37495        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37496        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37497        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37498        GIR_EraseFromParent, /*InsnID*/0,
37499        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37500        // GIR_Coverage, 5095,
37501        GIR_Done,
37502      // Label 1803: @101660
37503      GIM_Try, /*On fail goto*//*Label 1804*/ 101738, // Rule ID 5096 //
37504        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37505        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37506        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37507        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37508        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37509        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37510        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37511        // MIs[0] base
37512        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37513        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37514        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37515        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
37516        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
37517        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
37518        // (intrinsic_w_chain:{ *:[v4i32] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37519        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq,
37520        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37521        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37522        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37523        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37524        GIR_EraseFromParent, /*InsnID*/0,
37525        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37526        // GIR_Coverage, 5096,
37527        GIR_Done,
37528      // Label 1804: @101738
37529      GIM_Try, /*On fail goto*//*Label 1805*/ 101816, // Rule ID 5099 //
37530        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37531        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37532        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37533        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37534        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37535        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37536        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37537        // MIs[0] base
37538        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37539        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37540        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37541        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
37542        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
37543        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
37544        // (intrinsic_w_chain:{ *:[v4i32] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37545        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u,
37546        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37547        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37548        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37549        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37550        GIR_EraseFromParent, /*InsnID*/0,
37551        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37552        // GIR_Coverage, 5099,
37553        GIR_Done,
37554      // Label 1805: @101816
37555      GIM_Try, /*On fail goto*//*Label 1806*/ 101894, // Rule ID 5100 //
37556        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37557        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37558        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37559        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37560        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37561        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37562        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37563        // MIs[0] base
37564        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37565        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37566        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37567        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
37568        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
37569        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
37570        // (intrinsic_w_chain:{ *:[v4i32] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37571        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq,
37572        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37573        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37574        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37575        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37576        GIR_EraseFromParent, /*InsnID*/0,
37577        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37578        // GIR_Coverage, 5100,
37579        GIR_Done,
37580      // Label 1806: @101894
37581      GIM_Try, /*On fail goto*//*Label 1807*/ 101972, // Rule ID 5103 //
37582        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37583        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37584        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37585        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37586        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37587        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37588        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37589        // MIs[0] base
37590        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37591        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37592        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37593        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
37594        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
37595        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
37596        // (intrinsic_w_chain:{ *:[v4f32] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37597        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u,
37598        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37599        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37600        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37601        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37602        GIR_EraseFromParent, /*InsnID*/0,
37603        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37604        // GIR_Coverage, 5103,
37605        GIR_Done,
37606      // Label 1807: @101972
37607      GIM_Try, /*On fail goto*//*Label 1808*/ 102050, // Rule ID 5104 //
37608        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37609        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37610        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37611        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37612        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37613        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37614        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37615        // MIs[0] base
37616        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37617        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37618        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37619        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
37620        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
37621        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
37622        // (intrinsic_w_chain:{ *:[v4f32] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37623        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq,
37624        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37625        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37626        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37627        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37628        GIR_EraseFromParent, /*InsnID*/0,
37629        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37630        // GIR_Coverage, 5104,
37631        GIR_Done,
37632      // Label 1808: @102050
37633      GIM_Try, /*On fail goto*//*Label 1809*/ 102128, // Rule ID 5107 //
37634        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37635        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37636        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37637        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37638        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37639        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37640        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37641        // MIs[0] base
37642        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37643        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37644        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37645        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
37646        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
37647        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
37648        // (intrinsic_w_chain:{ *:[v4f32] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37649        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u,
37650        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37651        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37652        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37653        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37654        GIR_EraseFromParent, /*InsnID*/0,
37655        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37656        // GIR_Coverage, 5107,
37657        GIR_Done,
37658      // Label 1809: @102128
37659      GIM_Try, /*On fail goto*//*Label 1810*/ 102206, // Rule ID 5108 //
37660        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37661        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
37662        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
37663        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37664        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37665        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37666        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37667        // MIs[0] base
37668        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37669        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37670        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37671        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
37672        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
37673        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
37674        // (intrinsic_w_chain:{ *:[v4f32] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37675        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq,
37676        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37677        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37678        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37679        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37680        GIR_EraseFromParent, /*InsnID*/0,
37681        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37682        // GIR_Coverage, 5108,
37683        GIR_Done,
37684      // Label 1810: @102206
37685      GIM_Try, /*On fail goto*//*Label 1811*/ 102284, // Rule ID 5111 //
37686        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37687        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
37688        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
37689        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37690        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37691        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37692        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37693        // MIs[0] base
37694        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37695        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37696        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37697        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
37698        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
37699        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
37700        // (intrinsic_w_chain:{ *:[v2i64] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37701        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq_u,
37702        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37703        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37704        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37705        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37706        GIR_EraseFromParent, /*InsnID*/0,
37707        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37708        // GIR_Coverage, 5111,
37709        GIR_Done,
37710      // Label 1811: @102284
37711      GIM_Try, /*On fail goto*//*Label 1812*/ 102362, // Rule ID 5112 //
37712        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37713        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
37714        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
37715        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37716        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37717        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37718        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37719        // MIs[0] base
37720        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37721        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37722        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37723        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
37724        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 3,
37725        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
37726        // (intrinsic_w_chain:{ *:[v2i64] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37727        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq,
37728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37729        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37730        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37731        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37732        GIR_EraseFromParent, /*InsnID*/0,
37733        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37734        // GIR_Coverage, 5112,
37735        GIR_Done,
37736      // Label 1812: @102362
37737      GIM_Try, /*On fail goto*//*Label 1813*/ 102440, // Rule ID 5115 //
37738        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37739        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
37740        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
37741        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37742        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37743        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37744        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37745        // MIs[0] base
37746        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37747        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37748        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37749        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
37750        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
37751        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
37752        // (intrinsic_w_chain:{ *:[v2i64] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37753        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq_u,
37754        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37755        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37756        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37757        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37758        GIR_EraseFromParent, /*InsnID*/0,
37759        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37760        // GIR_Coverage, 5115,
37761        GIR_Done,
37762      // Label 1813: @102440
37763      GIM_Try, /*On fail goto*//*Label 1814*/ 102518, // Rule ID 5116 //
37764        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37765        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
37766        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
37767        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37768        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37769        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37770        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37771        // MIs[0] base
37772        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37773        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37774        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37775        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
37776        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 3,
37777        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
37778        // (intrinsic_w_chain:{ *:[v2i64] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37779        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq,
37780        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37781        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37782        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37783        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37784        GIR_EraseFromParent, /*InsnID*/0,
37785        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37786        // GIR_Coverage, 5116,
37787        GIR_Done,
37788      // Label 1814: @102518
37789      GIM_Try, /*On fail goto*//*Label 1815*/ 102596, // Rule ID 5119 //
37790        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37791        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
37792        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
37793        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37794        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37795        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37796        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37797        // MIs[0] base
37798        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37799        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37800        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37801        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
37802        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
37803        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
37804        // (intrinsic_w_chain:{ *:[v2i64] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37805        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq_u,
37806        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37807        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37808        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37809        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37810        GIR_EraseFromParent, /*InsnID*/0,
37811        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37812        // GIR_Coverage, 5119,
37813        GIR_Done,
37814      // Label 1815: @102596
37815      GIM_Try, /*On fail goto*//*Label 1816*/ 102674, // Rule ID 5120 //
37816        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37817        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
37818        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
37819        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37820        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37821        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37822        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37823        // MIs[0] base
37824        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37825        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37826        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37827        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
37828        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 3,
37829        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
37830        // (intrinsic_w_chain:{ *:[v2i64] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] })  =>  (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37831        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq,
37832        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37834        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37835        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37836        GIR_EraseFromParent, /*InsnID*/0,
37837        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37838        // GIR_Coverage, 5120,
37839        GIR_Done,
37840      // Label 1816: @102674
37841      GIM_Try, /*On fail goto*//*Label 1817*/ 102752, // Rule ID 5123 //
37842        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37843        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
37844        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
37845        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37846        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37847        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37848        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37849        // MIs[0] base
37850        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37851        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37852        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37853        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
37854        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
37855        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
37856        // (intrinsic_w_chain:{ *:[v2i64] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37857        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq_u,
37858        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37859        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37860        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37861        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37862        GIR_EraseFromParent, /*InsnID*/0,
37863        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37864        // GIR_Coverage, 5123,
37865        GIR_Done,
37866      // Label 1817: @102752
37867      GIM_Try, /*On fail goto*//*Label 1818*/ 102830, // Rule ID 5124 //
37868        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
37869        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
37870        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
37871        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
37872        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
37873        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
37874        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37875        // MIs[0] base
37876        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37877        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37878        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
37879        GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
37880        GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 3,
37881        GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
37882        // (intrinsic_w_chain:{ *:[v2i64] } 2474:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] })  =>  (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37883        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq,
37884        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37885        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
37886        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
37887        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37888        GIR_EraseFromParent, /*InsnID*/0,
37889        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37890        // GIR_Coverage, 5124,
37891        GIR_Done,
37892      // Label 1818: @102830
37893      GIM_Try, /*On fail goto*//*Label 1819*/ 102904, // Rule ID 263 //
37894        GIM_CheckFeatures, GIFBS_IsARM,
37895        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcr,
37896        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
37897        // MIs[0] cop
37898        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
37899        // MIs[0] opc1
37900        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
37901        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
37902        // MIs[0] CRn
37903        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
37904        // MIs[0] CRm
37905        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
37906        // MIs[0] opc2
37907        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
37908        // (intrinsic_void 2349:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
37909        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCR,
37910        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
37911        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
37912        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
37913        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
37914        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
37915        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
37916        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37917        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37918        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37919        GIR_EraseFromParent, /*InsnID*/0,
37920        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37921        // GIR_Coverage, 263,
37922        GIR_Done,
37923      // Label 1819: @102904
37924      GIM_Try, /*On fail goto*//*Label 1820*/ 102971, // Rule ID 264 //
37925        GIM_CheckFeatures, GIFBS_IsARM_PreV8,
37926        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcr2,
37927        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
37928        // MIs[0] cop
37929        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
37930        // MIs[0] opc1
37931        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
37932        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
37933        // MIs[0] CRn
37934        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
37935        // MIs[0] CRm
37936        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
37937        // MIs[0] opc2
37938        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
37939        // (intrinsic_void 2350:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
37940        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCR2,
37941        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
37942        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
37943        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
37944        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
37945        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
37946        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
37947        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37948        GIR_EraseFromParent, /*InsnID*/0,
37949        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37950        // GIR_Coverage, 264,
37951        GIR_Done,
37952      // Label 1820: @102971
37953      GIM_Try, /*On fail goto*//*Label 1821*/ 103045, // Rule ID 610 //
37954        GIM_CheckFeatures, GIFBS_IsThumb2,
37955        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcr,
37956        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
37957        // MIs[0] cop
37958        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
37959        // MIs[0] opc1
37960        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
37961        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
37962        // MIs[0] CRn
37963        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
37964        // MIs[0] CRm
37965        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
37966        // MIs[0] opc2
37967        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
37968        // (intrinsic_void 2349:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (t2MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
37969        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCR,
37970        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
37971        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
37972        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
37973        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
37974        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
37975        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
37976        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37977        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37978        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
37979        GIR_EraseFromParent, /*InsnID*/0,
37980        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37981        // GIR_Coverage, 610,
37982        GIR_Done,
37983      // Label 1821: @103045
37984      GIM_Try, /*On fail goto*//*Label 1822*/ 103119, // Rule ID 611 //
37985        GIM_CheckFeatures, GIFBS_IsThumb2_PreV8,
37986        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcr2,
37987        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
37988        // MIs[0] cop
37989        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
37990        // MIs[0] opc1
37991        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
37992        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
37993        // MIs[0] CRn
37994        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
37995        // MIs[0] CRm
37996        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
37997        // MIs[0] opc2
37998        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
37999        // (intrinsic_void 2350:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)  =>  (t2MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
38000        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCR2,
38001        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
38002        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
38003        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
38004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
38005        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
38006        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
38007        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38008        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38009        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
38010        GIR_EraseFromParent, /*InsnID*/0,
38011        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38012        // GIR_Coverage, 611,
38013        GIR_Done,
38014      // Label 1822: @103119
38015      GIM_Reject,
38016    // Label 1772: @103120
38017    GIM_Reject,
38018    // Label 16: @103121
38019    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 13, /*)*//*default:*//*Label 1826*/ 103255,
38020    /*GILLT_v2s64*//*Label 1823*/ 103135, 0, 0,
38021    /*GILLT_v4s32*//*Label 1824*/ 103175, 0, 0, 0,
38022    /*GILLT_v8s16*//*Label 1825*/ 103215,
38023    // Label 1823: @103135
38024    GIM_Try, /*On fail goto*//*Label 1827*/ 103174, // Rule ID 2676 //
38025      GIM_CheckFeatures, GIFBS_HasNEON,
38026      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
38027      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38028      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38029      // (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)  =>  (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
38030      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv2i64,
38031      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38032      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38033      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38034      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38035      GIR_EraseFromParent, /*InsnID*/0,
38036      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38037      // GIR_Coverage, 2676,
38038      GIR_Done,
38039    // Label 1827: @103174
38040    GIM_Reject,
38041    // Label 1824: @103175
38042    GIM_Try, /*On fail goto*//*Label 1828*/ 103214, // Rule ID 2675 //
38043      GIM_CheckFeatures, GIFBS_HasNEON,
38044      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
38045      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38046      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38047      // (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)  =>  (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
38048      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv4i32,
38049      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38050      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38051      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38052      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38053      GIR_EraseFromParent, /*InsnID*/0,
38054      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38055      // GIR_Coverage, 2675,
38056      GIR_Done,
38057    // Label 1828: @103214
38058    GIM_Reject,
38059    // Label 1825: @103215
38060    GIM_Try, /*On fail goto*//*Label 1829*/ 103254, // Rule ID 2674 //
38061      GIM_CheckFeatures, GIFBS_HasNEON,
38062      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
38063      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38064      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38065      // (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)  =>  (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
38066      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv8i16,
38067      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38068      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38069      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38070      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38071      GIR_EraseFromParent, /*InsnID*/0,
38072      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38073      // GIR_Coverage, 2674,
38074      GIR_Done,
38075    // Label 1829: @103254
38076    GIM_Reject,
38077    // Label 1826: @103255
38078    GIM_Reject,
38079    // Label 17: @103256
38080    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 12, /*)*//*default:*//*Label 1833*/ 103390,
38081    /*GILLT_v2s32*//*Label 1830*/ 103270, 0, 0,
38082    /*GILLT_v4s16*//*Label 1831*/ 103310, 0, 0, 0,
38083    /*GILLT_v8s8*//*Label 1832*/ 103350,
38084    // Label 1830: @103270
38085    GIM_Try, /*On fail goto*//*Label 1834*/ 103309, // Rule ID 1606 //
38086      GIM_CheckFeatures, GIFBS_HasNEON,
38087      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
38088      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
38089      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
38090      // (trunc:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)  =>  (VMOVNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
38091      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVNv2i32,
38092      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38093      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38094      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38095      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38096      GIR_EraseFromParent, /*InsnID*/0,
38097      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38098      // GIR_Coverage, 1606,
38099      GIR_Done,
38100    // Label 1834: @103309
38101    GIM_Reject,
38102    // Label 1831: @103310
38103    GIM_Try, /*On fail goto*//*Label 1835*/ 103349, // Rule ID 1605 //
38104      GIM_CheckFeatures, GIFBS_HasNEON,
38105      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
38106      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
38107      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
38108      // (trunc:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)  =>  (VMOVNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
38109      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVNv4i16,
38110      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38111      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38112      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38113      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38114      GIR_EraseFromParent, /*InsnID*/0,
38115      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38116      // GIR_Coverage, 1605,
38117      GIR_Done,
38118    // Label 1835: @103349
38119    GIM_Reject,
38120    // Label 1832: @103350
38121    GIM_Try, /*On fail goto*//*Label 1836*/ 103389, // Rule ID 1604 //
38122      GIM_CheckFeatures, GIFBS_HasNEON,
38123      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
38124      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
38125      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
38126      // (trunc:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)  =>  (VMOVNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
38127      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVNv8i8,
38128      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38129      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38130      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38131      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38132      GIR_EraseFromParent, /*InsnID*/0,
38133      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38134      // GIR_Coverage, 1604,
38135      GIR_Done,
38136    // Label 1836: @103389
38137    GIM_Reject,
38138    // Label 1833: @103390
38139    GIM_Reject,
38140    // Label 18: @103391
38141    GIM_Try, /*On fail goto*//*Label 1837*/ 103587,
38142      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
38143      GIM_Try, /*On fail goto*//*Label 1838*/ 103434, // Rule ID 411 //
38144        GIM_CheckFeatures, GIFBS_IsThumb2,
38145        GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
38146        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
38147        // MIs[0] Operand 1
38148        // No operand predicates
38149        // (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm  =>  (t2MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
38150        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVi,
38151        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38152        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
38153        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38154        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38155        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38156        GIR_EraseFromParent, /*InsnID*/0,
38157        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38158        // GIR_Coverage, 411,
38159        GIR_Done,
38160      // Label 1838: @103434
38161      GIM_Try, /*On fail goto*//*Label 1839*/ 103471, // Rule ID 57 //
38162        GIM_CheckFeatures, GIFBS_IsARM,
38163        GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
38164        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
38165        // MIs[0] Operand 1
38166        // No operand predicates
38167        // (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm  =>  (MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
38168        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVi,
38169        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38170        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
38171        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38172        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38173        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38174        GIR_EraseFromParent, /*InsnID*/0,
38175        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38176        // GIR_Coverage, 57,
38177        GIR_Done,
38178      // Label 1839: @103471
38179      GIM_Try, /*On fail goto*//*Label 1840*/ 103504, // Rule ID 58 //
38180        GIM_CheckFeatures, GIFBS_HasV6T2_IsARM,
38181        GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_imm0_65535,
38182        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
38183        // MIs[0] Operand 1
38184        // No operand predicates
38185        // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm  =>  (MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm)
38186        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVi16,
38187        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38188        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
38189        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38190        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38191        GIR_EraseFromParent, /*InsnID*/0,
38192        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38193        // GIR_Coverage, 58,
38194        GIR_Done,
38195      // Label 1840: @103504
38196      GIM_Try, /*On fail goto*//*Label 1841*/ 103530, // Rule ID 275 //
38197        GIM_CheckFeatures, GIFBS_IsARM,
38198        GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APInt_Predicate_arm_i32imm,
38199        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
38200        // MIs[0] Operand 1
38201        // No operand predicates
38202        // (imm:{ *:[i32] })<<P:Predicate_arm_i32imm>>:$src  =>  (MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src)
38203        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVi32imm,
38204        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
38205        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
38206        GIR_EraseFromParent, /*InsnID*/0,
38207        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38208        // GIR_Coverage, 275,
38209        GIR_Done,
38210      // Label 1841: @103530
38211      GIM_Try, /*On fail goto*//*Label 1842*/ 103563, // Rule ID 412 //
38212        GIM_CheckFeatures, GIFBS_HasV8MBaseline_IsThumb,
38213        GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_imm0_65535,
38214        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
38215        // MIs[0] Operand 1
38216        // No operand predicates
38217        // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm  =>  (t2MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm)
38218        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVi16,
38219        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38220        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
38221        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38222        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38223        GIR_EraseFromParent, /*InsnID*/0,
38224        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38225        // GIR_Coverage, 412,
38226        GIR_Done,
38227      // Label 1842: @103563
38228      GIM_Try, /*On fail goto*//*Label 1843*/ 103586, // Rule ID 598 //
38229        GIM_CheckFeatures, GIFBS_IsThumb_UseMovt,
38230        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
38231        // MIs[0] Operand 1
38232        // No operand predicates
38233        // (imm:{ *:[i32] }):$src  =>  (t2MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src)
38234        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVi32imm,
38235        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
38236        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
38237        GIR_EraseFromParent, /*InsnID*/0,
38238        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38239        // GIR_Coverage, 598,
38240        GIR_Done,
38241      // Label 1843: @103586
38242      GIM_Reject,
38243    // Label 1837: @103587
38244    GIM_Reject,
38245    // Label 19: @103588
38246    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1846*/ 103666,
38247    /*GILLT_s32*//*Label 1844*/ 103596,
38248    /*GILLT_s64*//*Label 1845*/ 103631,
38249    // Label 1844: @103596
38250    GIM_Try, /*On fail goto*//*Label 1847*/ 103630, // Rule ID 744 //
38251      GIM_CheckFeatures, GIFBS_HasVFP3,
38252      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
38253      // MIs[0] Operand 1
38254      // No operand predicates
38255      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_vfp_f32imm,
38256      // (fpimm:{ *:[f32] })<<P:Predicate_vfp_f32imm>><<X:vfp_f32imm_xform>>:$imm  =>  (FCONSTS:{ *:[f32] } (vfp_f32imm_xform:{ *:[f32] } (fpimm:{ *:[f32] }):$imm))
38257      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::FCONSTS,
38258      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
38259      GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GICR_renderVFPF32Imm, // imm
38260      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38261      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38262      GIR_EraseFromParent, /*InsnID*/0,
38263      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38264      // GIR_Coverage, 744,
38265      GIR_Done,
38266    // Label 1847: @103630
38267    GIM_Reject,
38268    // Label 1845: @103631
38269    GIM_Try, /*On fail goto*//*Label 1848*/ 103665, // Rule ID 743 //
38270      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP3,
38271      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
38272      // MIs[0] Operand 1
38273      // No operand predicates
38274      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_vfp_f64imm,
38275      // (fpimm:{ *:[f64] })<<P:Predicate_vfp_f64imm>><<X:vfp_f64imm_xform>>:$imm  =>  (FCONSTD:{ *:[f64] } (vfp_f64imm_xform:{ *:[f64] } (fpimm:{ *:[f64] }):$imm))
38276      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::FCONSTD,
38277      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
38278      GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GICR_renderVFPF64Imm, // imm
38279      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38280      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38281      GIR_EraseFromParent, /*InsnID*/0,
38282      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38283      // GIR_Coverage, 743,
38284      GIR_Done,
38285    // Label 1848: @103665
38286    GIM_Reject,
38287    // Label 1846: @103666
38288    GIM_Reject,
38289    // Label 20: @103667
38290    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 13, /*)*//*default:*//*Label 1852*/ 103801,
38291    /*GILLT_v2s64*//*Label 1849*/ 103681, 0, 0,
38292    /*GILLT_v4s32*//*Label 1850*/ 103721, 0, 0, 0,
38293    /*GILLT_v8s16*//*Label 1851*/ 103761,
38294    // Label 1849: @103681
38295    GIM_Try, /*On fail goto*//*Label 1853*/ 103720, // Rule ID 1618 //
38296      GIM_CheckFeatures, GIFBS_HasNEON,
38297      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
38298      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38299      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38300      // (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)  =>  (VMOVLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
38301      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLsv2i64,
38302      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38303      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38304      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38305      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38306      GIR_EraseFromParent, /*InsnID*/0,
38307      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38308      // GIR_Coverage, 1618,
38309      GIR_Done,
38310    // Label 1853: @103720
38311    GIM_Reject,
38312    // Label 1850: @103721
38313    GIM_Try, /*On fail goto*//*Label 1854*/ 103760, // Rule ID 1617 //
38314      GIM_CheckFeatures, GIFBS_HasNEON,
38315      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
38316      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38317      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38318      // (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)  =>  (VMOVLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
38319      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLsv4i32,
38320      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38321      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38322      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38323      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38324      GIR_EraseFromParent, /*InsnID*/0,
38325      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38326      // GIR_Coverage, 1617,
38327      GIR_Done,
38328    // Label 1854: @103760
38329    GIM_Reject,
38330    // Label 1851: @103761
38331    GIM_Try, /*On fail goto*//*Label 1855*/ 103800, // Rule ID 1616 //
38332      GIM_CheckFeatures, GIFBS_HasNEON,
38333      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
38334      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38335      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38336      // (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)  =>  (VMOVLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
38337      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLsv8i16,
38338      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38339      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38340      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38341      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38342      GIR_EraseFromParent, /*InsnID*/0,
38343      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38344      // GIR_Coverage, 1616,
38345      GIR_Done,
38346    // Label 1855: @103800
38347    GIM_Reject,
38348    // Label 1852: @103801
38349    GIM_Reject,
38350    // Label 21: @103802
38351    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 13, /*)*//*default:*//*Label 1859*/ 104323,
38352    /*GILLT_v2s64*//*Label 1856*/ 103816, 0, 0,
38353    /*GILLT_v4s32*//*Label 1857*/ 103985, 0, 0, 0,
38354    /*GILLT_v8s16*//*Label 1858*/ 104154,
38355    // Label 1856: @103816
38356    GIM_Try, /*On fail goto*//*Label 1860*/ 103984,
38357      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
38358      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38359      GIM_Try, /*On fail goto*//*Label 1861*/ 103889, // Rule ID 1193 //
38360        GIM_CheckFeatures, GIFBS_HasNEON,
38361        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38362        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
38363        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38364        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
38365        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
38366        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
38367        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38368        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
38369        GIM_CheckIsSafeToFold, /*InsnID*/1,
38370        // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 2574:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VABDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
38371        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLsv2i64,
38372        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38373        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38374        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38375        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38376        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38377        GIR_EraseFromParent, /*InsnID*/0,
38378        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38379        // GIR_Coverage, 1193,
38380        GIR_Done,
38381      // Label 1861: @103889
38382      GIM_Try, /*On fail goto*//*Label 1862*/ 103952, // Rule ID 1196 //
38383        GIM_CheckFeatures, GIFBS_HasNEON,
38384        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38385        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
38386        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38387        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
38388        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
38389        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
38390        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38391        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
38392        GIM_CheckIsSafeToFold, /*InsnID*/1,
38393        // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 2575:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VABDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
38394        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLuv2i64,
38395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38396        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38397        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38398        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38399        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38400        GIR_EraseFromParent, /*InsnID*/0,
38401        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38402        // GIR_Coverage, 1196,
38403        GIR_Done,
38404      // Label 1862: @103952
38405      GIM_Try, /*On fail goto*//*Label 1863*/ 103983, // Rule ID 1621 //
38406        GIM_CheckFeatures, GIFBS_HasNEON,
38407        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38408        // (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)  =>  (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
38409        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv2i64,
38410        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38411        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38412        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38413        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38414        GIR_EraseFromParent, /*InsnID*/0,
38415        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38416        // GIR_Coverage, 1621,
38417        GIR_Done,
38418      // Label 1863: @103983
38419      GIM_Reject,
38420    // Label 1860: @103984
38421    GIM_Reject,
38422    // Label 1857: @103985
38423    GIM_Try, /*On fail goto*//*Label 1864*/ 104153,
38424      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
38425      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38426      GIM_Try, /*On fail goto*//*Label 1865*/ 104058, // Rule ID 1192 //
38427        GIM_CheckFeatures, GIFBS_HasNEON,
38428        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38429        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
38430        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38431        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
38432        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
38433        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
38434        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38435        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
38436        GIM_CheckIsSafeToFold, /*InsnID*/1,
38437        // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 2574:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VABDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
38438        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLsv4i32,
38439        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38440        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38441        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38442        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38443        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38444        GIR_EraseFromParent, /*InsnID*/0,
38445        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38446        // GIR_Coverage, 1192,
38447        GIR_Done,
38448      // Label 1865: @104058
38449      GIM_Try, /*On fail goto*//*Label 1866*/ 104121, // Rule ID 1195 //
38450        GIM_CheckFeatures, GIFBS_HasNEON,
38451        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38452        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
38453        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38454        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
38455        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
38456        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
38457        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38458        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
38459        GIM_CheckIsSafeToFold, /*InsnID*/1,
38460        // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 2575:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
38461        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLuv4i32,
38462        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38463        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38464        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38465        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38466        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38467        GIR_EraseFromParent, /*InsnID*/0,
38468        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38469        // GIR_Coverage, 1195,
38470        GIR_Done,
38471      // Label 1866: @104121
38472      GIM_Try, /*On fail goto*//*Label 1867*/ 104152, // Rule ID 1620 //
38473        GIM_CheckFeatures, GIFBS_HasNEON,
38474        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38475        // (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)  =>  (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
38476        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv4i32,
38477        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38478        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38479        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38480        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38481        GIR_EraseFromParent, /*InsnID*/0,
38482        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38483        // GIR_Coverage, 1620,
38484        GIR_Done,
38485      // Label 1867: @104152
38486      GIM_Reject,
38487    // Label 1864: @104153
38488    GIM_Reject,
38489    // Label 1858: @104154
38490    GIM_Try, /*On fail goto*//*Label 1868*/ 104322,
38491      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
38492      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38493      GIM_Try, /*On fail goto*//*Label 1869*/ 104227, // Rule ID 1191 //
38494        GIM_CheckFeatures, GIFBS_HasNEON,
38495        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38496        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
38497        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38498        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
38499        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
38500        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
38501        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38502        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
38503        GIM_CheckIsSafeToFold, /*InsnID*/1,
38504        // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 2574:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VABDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
38505        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLsv8i16,
38506        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38507        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38508        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38509        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38510        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38511        GIR_EraseFromParent, /*InsnID*/0,
38512        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38513        // GIR_Coverage, 1191,
38514        GIR_Done,
38515      // Label 1869: @104227
38516      GIM_Try, /*On fail goto*//*Label 1870*/ 104290, // Rule ID 1194 //
38517        GIM_CheckFeatures, GIFBS_HasNEON,
38518        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38519        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
38520        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38521        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
38522        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
38523        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
38524        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38525        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
38526        GIM_CheckIsSafeToFold, /*InsnID*/1,
38527        // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 2575:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
38528        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLuv8i16,
38529        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38530        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38531        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38532        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38533        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38534        GIR_EraseFromParent, /*InsnID*/0,
38535        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38536        // GIR_Coverage, 1194,
38537        GIR_Done,
38538      // Label 1870: @104290
38539      GIM_Try, /*On fail goto*//*Label 1871*/ 104321, // Rule ID 1619 //
38540        GIM_CheckFeatures, GIFBS_HasNEON,
38541        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38542        // (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)  =>  (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
38543        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv8i16,
38544        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38545        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
38546        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38547        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38548        GIR_EraseFromParent, /*InsnID*/0,
38549        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38550        // GIR_Coverage, 1619,
38551        GIR_Done,
38552      // Label 1871: @104321
38553      GIM_Reject,
38554    // Label 1868: @104322
38555    GIM_Reject,
38556    // Label 1859: @104323
38557    GIM_Reject,
38558    // Label 22: @104324
38559    GIM_Try, /*On fail goto*//*Label 1872*/ 104432,
38560      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
38561      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
38562      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
38563      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
38564      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
38565      GIM_Try, /*On fail goto*//*Label 1873*/ 104392, // Rule ID 477 //
38566        GIM_CheckFeatures, GIFBS_IsThumb2,
38567        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38568        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
38569        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm1_31,
38570        // MIs[1] Operand 1
38571        // No operand predicates
38572        GIM_CheckIsSafeToFold, /*InsnID*/1,
38573        // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm)  =>  (t2LSLri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm)
38574        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2LSLri,
38575        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38576        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
38577        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
38578        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38579        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38580        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38581        GIR_EraseFromParent, /*InsnID*/0,
38582        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38583        // GIR_Coverage, 477,
38584        GIR_Done,
38585      // Label 1873: @104392
38586      GIM_Try, /*On fail goto*//*Label 1874*/ 104431, // Rule ID 478 //
38587        GIM_CheckFeatures, GIFBS_IsThumb2,
38588        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
38589        // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2LSLrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
38590        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2LSLrr,
38591        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38592        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
38593        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38594        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38595        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38596        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38597        GIR_EraseFromParent, /*InsnID*/0,
38598        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38599        // GIR_Coverage, 478,
38600        GIR_Done,
38601      // Label 1874: @104431
38602      GIM_Reject,
38603    // Label 1872: @104432
38604    GIM_Reject,
38605    // Label 23: @104433
38606    GIM_Try, /*On fail goto*//*Label 1875*/ 104492, // Rule ID 480 //
38607      GIM_CheckFeatures, GIFBS_IsThumb2,
38608      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
38609      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
38610      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
38611      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
38612      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
38613      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
38614      // (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2LSRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
38615      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2LSRrr,
38616      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38617      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
38618      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38619      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38620      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38621      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38622      GIR_EraseFromParent, /*InsnID*/0,
38623      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38624      // GIR_Coverage, 480,
38625      GIR_Done,
38626    // Label 1875: @104492
38627    GIM_Reject,
38628    // Label 24: @104493
38629    GIM_Try, /*On fail goto*//*Label 1876*/ 104710,
38630      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
38631      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
38632      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
38633      GIM_Try, /*On fail goto*//*Label 1877*/ 104559, // Rule ID 201 //
38634        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
38635        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
38636        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38637        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BSWAP,
38638        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38639        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
38640        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16,
38641        GIM_CheckIsSafeToFold, /*InsnID*/1,
38642        // (sra:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] })  =>  (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
38643        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REVSH,
38644        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38645        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
38646        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38647        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38648        GIR_EraseFromParent, /*InsnID*/0,
38649        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38650        // GIR_Coverage, 201,
38651        GIR_Done,
38652      // Label 1877: @104559
38653      GIM_Try, /*On fail goto*//*Label 1878*/ 104611, // Rule ID 335 //
38654        GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only,
38655        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID,
38656        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38657        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BSWAP,
38658        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38659        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::tGPRRegClassID,
38660        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16,
38661        GIM_CheckIsSafeToFold, /*InsnID*/1,
38662        // (sra:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] })  =>  (tREVSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
38663        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tREVSH,
38664        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38665        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
38666        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38667        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38668        GIR_EraseFromParent, /*InsnID*/0,
38669        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38670        // GIR_Coverage, 335,
38671        GIR_Done,
38672      // Label 1878: @104611
38673      GIM_Try, /*On fail goto*//*Label 1879*/ 104709,
38674        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
38675        GIM_Try, /*On fail goto*//*Label 1880*/ 104665, // Rule ID 545 //
38676          GIM_CheckFeatures, GIFBS_IsThumb2,
38677          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38678          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BSWAP,
38679          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38680          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
38681          GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16,
38682          GIM_CheckIsSafeToFold, /*InsnID*/1,
38683          // (sra:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] })  =>  (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
38684          GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REVSH,
38685          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38686          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
38687          GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38688          GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38689          GIR_EraseFromParent, /*InsnID*/0,
38690          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38691          // GIR_Coverage, 545,
38692          GIR_Done,
38693        // Label 1880: @104665
38694        GIM_Try, /*On fail goto*//*Label 1881*/ 104708, // Rule ID 482 //
38695          GIM_CheckFeatures, GIFBS_IsThumb2,
38696          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
38697          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
38698          // (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2ASRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
38699          GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ASRrr,
38700          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38701          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
38702          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38703          GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38704          GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38705          GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38706          GIR_EraseFromParent, /*InsnID*/0,
38707          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38708          // GIR_Coverage, 482,
38709          GIR_Done,
38710        // Label 1881: @104708
38711        GIM_Reject,
38712      // Label 1879: @104709
38713      GIM_Reject,
38714    // Label 1876: @104710
38715    GIM_Reject,
38716    // Label 25: @104711
38717    GIM_Try, /*On fail goto*//*Label 1882*/ 104978,
38718      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
38719      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
38720      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
38721      GIM_Try, /*On fail goto*//*Label 1883*/ 104777, // Rule ID 200 //
38722        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
38723        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
38724        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38725        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BSWAP,
38726        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38727        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
38728        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16,
38729        GIM_CheckIsSafeToFold, /*InsnID*/1,
38730        // (rotr:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] })  =>  (REV16:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
38731        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REV16,
38732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38733        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
38734        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38735        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38736        GIR_EraseFromParent, /*InsnID*/0,
38737        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38738        // GIR_Coverage, 200,
38739        GIR_Done,
38740      // Label 1883: @104777
38741      GIM_Try, /*On fail goto*//*Label 1884*/ 104829, // Rule ID 334 //
38742        GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only,
38743        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID,
38744        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38745        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BSWAP,
38746        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38747        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::tGPRRegClassID,
38748        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16,
38749        GIM_CheckIsSafeToFold, /*InsnID*/1,
38750        // (rotr:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] })  =>  (tREV16:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
38751        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tREV16,
38752        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38753        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
38754        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38755        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38756        GIR_EraseFromParent, /*InsnID*/0,
38757        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38758        // GIR_Coverage, 334,
38759        GIR_Done,
38760      // Label 1884: @104829
38761      GIM_Try, /*On fail goto*//*Label 1885*/ 104977,
38762        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
38763        GIM_Try, /*On fail goto*//*Label 1886*/ 104883, // Rule ID 544 //
38764          GIM_CheckFeatures, GIFBS_IsThumb2,
38765          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38766          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BSWAP,
38767          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38768          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
38769          GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16,
38770          GIM_CheckIsSafeToFold, /*InsnID*/1,
38771          // (rotr:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] })  =>  (t2REV16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
38772          GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REV16,
38773          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38774          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
38775          GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38776          GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38777          GIR_EraseFromParent, /*InsnID*/0,
38778          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38779          // GIR_Coverage, 544,
38780          GIR_Done,
38781        // Label 1886: @104883
38782        GIM_Try, /*On fail goto*//*Label 1887*/ 104933, // Rule ID 483 //
38783          GIM_CheckFeatures, GIFBS_IsThumb2,
38784          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
38785          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38786          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
38787          GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm1_31,
38788          // MIs[1] Operand 1
38789          // No operand predicates
38790          GIM_CheckIsSafeToFold, /*InsnID*/1,
38791          // (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm)  =>  (t2RORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm)
38792          GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2RORri,
38793          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38794          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
38795          GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
38796          GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38797          GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38798          GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38799          GIR_EraseFromParent, /*InsnID*/0,
38800          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38801          // GIR_Coverage, 483,
38802          GIR_Done,
38803        // Label 1887: @104933
38804        GIM_Try, /*On fail goto*//*Label 1888*/ 104976, // Rule ID 484 //
38805          GIM_CheckFeatures, GIFBS_IsThumb2,
38806          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
38807          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
38808          // (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2RORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
38809          GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2RORrr,
38810          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38811          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
38812          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38813          GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38814          GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38815          GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38816          GIR_EraseFromParent, /*InsnID*/0,
38817          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38818          // GIR_Coverage, 484,
38819          GIR_Done,
38820        // Label 1888: @104976
38821        GIM_Reject,
38822      // Label 1885: @104977
38823      GIM_Reject,
38824    // Label 1882: @104978
38825    GIM_Reject,
38826    // Label 26: @104979
38827    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 16, /*)*//*default:*//*Label 1892*/ 105203,
38828    /*GILLT_v4s32*//*Label 1889*/ 104993, 0, 0, 0,
38829    /*GILLT_v8s16*//*Label 1890*/ 105063, 0, 0,
38830    /*GILLT_v16s8*//*Label 1891*/ 105133,
38831    // Label 1889: @104993
38832    GIM_Try, /*On fail goto*//*Label 1893*/ 105062, // Rule ID 4562 //
38833      GIM_CheckFeatures, GIFBS_HasMVEInt,
38834      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
38835      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
38836      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38837      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38838      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
38839      // (mulhu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
38840      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38841      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38842      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
38843      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHu32,
38844      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38845      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
38846      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
38847      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38848      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38849      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38850      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38851      GIR_EraseFromParent, /*InsnID*/0,
38852      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38853      // GIR_Coverage, 4562,
38854      GIR_Done,
38855    // Label 1893: @105062
38856    GIM_Reject,
38857    // Label 1890: @105063
38858    GIM_Try, /*On fail goto*//*Label 1894*/ 105132, // Rule ID 4558 //
38859      GIM_CheckFeatures, GIFBS_HasMVEInt,
38860      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
38861      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
38862      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38863      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38864      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
38865      // (mulhu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
38866      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38867      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38868      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
38869      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHu16,
38870      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38871      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
38872      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
38873      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38874      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38875      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38876      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38877      GIR_EraseFromParent, /*InsnID*/0,
38878      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38879      // GIR_Coverage, 4558,
38880      GIR_Done,
38881    // Label 1894: @105132
38882    GIM_Reject,
38883    // Label 1891: @105133
38884    GIM_Try, /*On fail goto*//*Label 1895*/ 105202, // Rule ID 4554 //
38885      GIM_CheckFeatures, GIFBS_HasMVEInt,
38886      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
38887      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
38888      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38889      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38890      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
38891      // (mulhu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
38892      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38893      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38894      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
38895      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHu8,
38896      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38897      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
38898      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
38899      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38900      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38901      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38902      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38903      GIR_EraseFromParent, /*InsnID*/0,
38904      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38905      // GIR_Coverage, 4554,
38906      GIR_Done,
38907    // Label 1895: @105202
38908    GIM_Reject,
38909    // Label 1892: @105203
38910    GIM_Reject,
38911    // Label 27: @105204
38912    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 16, /*)*//*default:*//*Label 1900*/ 105533,
38913    /*GILLT_s32*//*Label 1896*/ 105225, 0, 0, 0, 0, 0, 0,
38914    /*GILLT_v4s32*//*Label 1897*/ 105323, 0, 0, 0,
38915    /*GILLT_v8s16*//*Label 1898*/ 105393, 0, 0,
38916    /*GILLT_v16s8*//*Label 1899*/ 105463,
38917    // Label 1896: @105225
38918    GIM_Try, /*On fail goto*//*Label 1901*/ 105322,
38919      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
38920      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
38921      GIM_Try, /*On fail goto*//*Label 1902*/ 105278, // Rule ID 178 //
38922        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
38923        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
38924        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
38925        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
38926        // (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (SMMUL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
38927        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMMUL,
38928        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38929        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
38930        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38931        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38932        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38933        GIR_EraseFromParent, /*InsnID*/0,
38934        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38935        // GIR_Coverage, 178,
38936        GIR_Done,
38937      // Label 1902: @105278
38938      GIM_Try, /*On fail goto*//*Label 1903*/ 105321, // Rule ID 514 //
38939        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
38940        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
38941        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
38942        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
38943        // (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMMUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
38944        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMMUL,
38945        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38946        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
38947        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38948        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38949        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38950        GIR_EraseFromParent, /*InsnID*/0,
38951        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38952        // GIR_Coverage, 514,
38953        GIR_Done,
38954      // Label 1903: @105321
38955      GIM_Reject,
38956    // Label 1901: @105322
38957    GIM_Reject,
38958    // Label 1897: @105323
38959    GIM_Try, /*On fail goto*//*Label 1904*/ 105392, // Rule ID 4550 //
38960      GIM_CheckFeatures, GIFBS_HasMVEInt,
38961      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
38962      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
38963      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38964      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38965      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
38966      // (mulhs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
38967      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38968      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38969      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
38970      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHs32,
38971      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38972      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
38973      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
38974      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38975      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38976      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38977      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38978      GIR_EraseFromParent, /*InsnID*/0,
38979      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38980      // GIR_Coverage, 4550,
38981      GIR_Done,
38982    // Label 1904: @105392
38983    GIM_Reject,
38984    // Label 1898: @105393
38985    GIM_Try, /*On fail goto*//*Label 1905*/ 105462, // Rule ID 4546 //
38986      GIM_CheckFeatures, GIFBS_HasMVEInt,
38987      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
38988      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
38989      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38990      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38991      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
38992      // (mulhs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
38993      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38994      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38995      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
38996      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHs16,
38997      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38998      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
38999      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39000      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
39001      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39002      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39003      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
39004      GIR_EraseFromParent, /*InsnID*/0,
39005      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39006      // GIR_Coverage, 4546,
39007      GIR_Done,
39008    // Label 1905: @105462
39009    GIM_Reject,
39010    // Label 1899: @105463
39011    GIM_Try, /*On fail goto*//*Label 1906*/ 105532, // Rule ID 4543 //
39012      GIM_CheckFeatures, GIFBS_HasMVEInt,
39013      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
39014      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
39015      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
39016      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
39017      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
39018      // (mulhs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
39019      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39020      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39021      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
39022      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHs8,
39023      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
39024      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39025      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39026      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
39027      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39028      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39029      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
39030      GIR_EraseFromParent, /*InsnID*/0,
39031      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39032      // GIR_Coverage, 4543,
39033      GIR_Done,
39034    // Label 1906: @105532
39035    GIM_Reject,
39036    // Label 1900: @105533
39037    GIM_Reject,
39038    // Label 28: @105534
39039    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 16, /*)*//*default:*//*Label 1915*/ 106162,
39040    /*GILLT_s64*//*Label 1907*/ 105554, 0,
39041    /*GILLT_v2s32*//*Label 1908*/ 105606,
39042    /*GILLT_v2s64*//*Label 1909*/ 105658, 0,
39043    /*GILLT_v4s16*//*Label 1910*/ 105710,
39044    /*GILLT_v4s32*//*Label 1911*/ 105762, 0, 0,
39045    /*GILLT_v8s8*//*Label 1912*/ 105878,
39046    /*GILLT_v8s16*//*Label 1913*/ 105930, 0, 0,
39047    /*GILLT_v16s8*//*Label 1914*/ 106046,
39048    // Label 1907: @105554
39049    GIM_Try, /*On fail goto*//*Label 1916*/ 105605, // Rule ID 846 //
39050      GIM_CheckFeatures, GIFBS_HasNEON,
39051      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
39052      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
39053      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
39054      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
39055      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39056      // (uaddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VQADDuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
39057      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv1i64,
39058      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39059      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39060      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39061      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39062      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39063      GIR_EraseFromParent, /*InsnID*/0,
39064      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39065      // GIR_Coverage, 846,
39066      GIR_Done,
39067    // Label 1916: @105605
39068    GIM_Reject,
39069    // Label 1908: @105606
39070    GIM_Try, /*On fail goto*//*Label 1917*/ 105657, // Rule ID 841 //
39071      GIM_CheckFeatures, GIFBS_HasNEON,
39072      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
39073      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
39074      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
39075      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
39076      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39077      // (uaddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
39078      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv2i32,
39079      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39080      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39081      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39082      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39083      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39084      GIR_EraseFromParent, /*InsnID*/0,
39085      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39086      // GIR_Coverage, 841,
39087      GIR_Done,
39088    // Label 1917: @105657
39089    GIM_Reject,
39090    // Label 1909: @105658
39091    GIM_Try, /*On fail goto*//*Label 1918*/ 105709, // Rule ID 847 //
39092      GIM_CheckFeatures, GIFBS_HasNEON,
39093      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
39094      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
39095      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39096      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39097      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39098      // (uaddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VQADDuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
39099      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv2i64,
39100      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39101      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39102      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39103      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39104      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39105      GIR_EraseFromParent, /*InsnID*/0,
39106      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39107      // GIR_Coverage, 847,
39108      GIR_Done,
39109    // Label 1918: @105709
39110    GIM_Reject,
39111    // Label 1910: @105710
39112    GIM_Try, /*On fail goto*//*Label 1919*/ 105761, // Rule ID 840 //
39113      GIM_CheckFeatures, GIFBS_HasNEON,
39114      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
39115      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
39116      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
39117      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
39118      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39119      // (uaddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
39120      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv4i16,
39121      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39122      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39123      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39124      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39125      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39126      GIR_EraseFromParent, /*InsnID*/0,
39127      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39128      // GIR_Coverage, 840,
39129      GIR_Done,
39130    // Label 1919: @105761
39131    GIM_Reject,
39132    // Label 1911: @105762
39133    GIM_Try, /*On fail goto*//*Label 1920*/ 105877,
39134      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
39135      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
39136      GIM_Try, /*On fail goto*//*Label 1921*/ 105815, // Rule ID 843 //
39137        GIM_CheckFeatures, GIFBS_HasNEON,
39138        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39139        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39140        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39141        // (uaddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
39142        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv4i32,
39143        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39144        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39145        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39146        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39147        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39148        GIR_EraseFromParent, /*InsnID*/0,
39149        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39150        // GIR_Coverage, 843,
39151        GIR_Done,
39152      // Label 1921: @105815
39153      GIM_Try, /*On fail goto*//*Label 1922*/ 105876, // Rule ID 3621 //
39154        GIM_CheckFeatures, GIFBS_HasMVEInt,
39155        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
39156        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
39157        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
39158        // (uaddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VQADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
39159        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39160        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39161        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
39162        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQADDu32,
39163        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
39164        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39165        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39166        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
39167        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39168        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39169        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
39170        GIR_EraseFromParent, /*InsnID*/0,
39171        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39172        // GIR_Coverage, 3621,
39173        GIR_Done,
39174      // Label 1922: @105876
39175      GIM_Reject,
39176    // Label 1920: @105877
39177    GIM_Reject,
39178    // Label 1912: @105878
39179    GIM_Try, /*On fail goto*//*Label 1923*/ 105929, // Rule ID 844 //
39180      GIM_CheckFeatures, GIFBS_HasNEON,
39181      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
39182      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
39183      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
39184      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
39185      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39186      // (uaddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VQADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
39187      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv8i8,
39188      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39189      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39190      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39191      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39192      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39193      GIR_EraseFromParent, /*InsnID*/0,
39194      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39195      // GIR_Coverage, 844,
39196      GIR_Done,
39197    // Label 1923: @105929
39198    GIM_Reject,
39199    // Label 1913: @105930
39200    GIM_Try, /*On fail goto*//*Label 1924*/ 106045,
39201      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
39202      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
39203      GIM_Try, /*On fail goto*//*Label 1925*/ 105983, // Rule ID 842 //
39204        GIM_CheckFeatures, GIFBS_HasNEON,
39205        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39206        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39207        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39208        // (uaddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
39209        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv8i16,
39210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39212        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39213        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39214        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39215        GIR_EraseFromParent, /*InsnID*/0,
39216        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39217        // GIR_Coverage, 842,
39218        GIR_Done,
39219      // Label 1925: @105983
39220      GIM_Try, /*On fail goto*//*Label 1926*/ 106044, // Rule ID 3618 //
39221        GIM_CheckFeatures, GIFBS_HasMVEInt,
39222        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
39223        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
39224        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
39225        // (uaddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VQADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
39226        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39227        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39228        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
39229        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQADDu16,
39230        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
39231        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39232        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39233        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
39234        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39235        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39236        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
39237        GIR_EraseFromParent, /*InsnID*/0,
39238        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39239        // GIR_Coverage, 3618,
39240        GIR_Done,
39241      // Label 1926: @106044
39242      GIM_Reject,
39243    // Label 1924: @106045
39244    GIM_Reject,
39245    // Label 1914: @106046
39246    GIM_Try, /*On fail goto*//*Label 1927*/ 106161,
39247      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
39248      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
39249      GIM_Try, /*On fail goto*//*Label 1928*/ 106099, // Rule ID 845 //
39250        GIM_CheckFeatures, GIFBS_HasNEON,
39251        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39252        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39253        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39254        // (uaddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VQADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
39255        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv16i8,
39256        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39257        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39258        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39259        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39260        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39261        GIR_EraseFromParent, /*InsnID*/0,
39262        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39263        // GIR_Coverage, 845,
39264        GIR_Done,
39265      // Label 1928: @106099
39266      GIM_Try, /*On fail goto*//*Label 1929*/ 106160, // Rule ID 3615 //
39267        GIM_CheckFeatures, GIFBS_HasMVEInt,
39268        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
39269        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
39270        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
39271        // (uaddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VQADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
39272        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39273        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39274        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
39275        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQADDu8,
39276        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
39277        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39278        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39279        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
39280        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39281        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39282        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
39283        GIR_EraseFromParent, /*InsnID*/0,
39284        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39285        // GIR_Coverage, 3615,
39286        GIR_Done,
39287      // Label 1929: @106160
39288      GIM_Reject,
39289    // Label 1927: @106161
39290    GIM_Reject,
39291    // Label 1915: @106162
39292    GIM_Reject,
39293    // Label 29: @106163
39294    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 16, /*)*//*default:*//*Label 1939*/ 107429,
39295    /*GILLT_s32*//*Label 1930*/ 106184,
39296    /*GILLT_s64*//*Label 1931*/ 106526, 0,
39297    /*GILLT_v2s32*//*Label 1932*/ 106578,
39298    /*GILLT_v2s64*//*Label 1933*/ 106630, 0,
39299    /*GILLT_v4s16*//*Label 1934*/ 106827,
39300    /*GILLT_v4s32*//*Label 1935*/ 106879, 0, 0,
39301    /*GILLT_v8s8*//*Label 1936*/ 107145,
39302    /*GILLT_v8s16*//*Label 1937*/ 107197, 0, 0,
39303    /*GILLT_v16s8*//*Label 1938*/ 107313,
39304    // Label 1930: @106184
39305    GIM_Try, /*On fail goto*//*Label 1940*/ 106525,
39306      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
39307      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
39308      GIM_Try, /*On fail goto*//*Label 1941*/ 106255, // Rule ID 5754 //
39309        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
39310        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
39311        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39312        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SADDSAT,
39313        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39314        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
39315        // MIs[1] Rn
39316        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
39317        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
39318        GIM_CheckIsSafeToFold, /*InsnID*/1,
39319        // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm)  =>  (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
39320        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDADD,
39321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
39322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
39323        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
39324        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39325        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39326        GIR_EraseFromParent, /*InsnID*/0,
39327        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39328        // GIR_Coverage, 5754,
39329        GIR_Done,
39330      // Label 1941: @106255
39331      GIM_Try, /*On fail goto*//*Label 1942*/ 106316, // Rule ID 5788 //
39332        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
39333        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
39334        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39335        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SADDSAT,
39336        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39337        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
39338        // MIs[1] Rn
39339        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
39340        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
39341        GIM_CheckIsSafeToFold, /*InsnID*/1,
39342        // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm)  =>  (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
39343        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDADD,
39344        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
39345        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
39346        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
39347        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39348        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39349        GIR_EraseFromParent, /*InsnID*/0,
39350        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39351        // GIR_Coverage, 5788,
39352        GIR_Done,
39353      // Label 1942: @106316
39354      GIM_Try, /*On fail goto*//*Label 1943*/ 106377, // Rule ID 1897 //
39355        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
39356        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
39357        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
39358        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39359        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SADDSAT,
39360        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39361        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
39362        // MIs[1] Rn
39363        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
39364        GIM_CheckIsSafeToFold, /*InsnID*/1,
39365        // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn))  =>  (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
39366        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDADD,
39367        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
39368        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
39369        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
39370        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39371        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39372        GIR_EraseFromParent, /*InsnID*/0,
39373        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39374        // GIR_Coverage, 1897,
39375        GIR_Done,
39376      // Label 1943: @106377
39377      GIM_Try, /*On fail goto*//*Label 1944*/ 106438, // Rule ID 2147 //
39378        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
39379        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
39380        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
39381        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39382        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SADDSAT,
39383        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39384        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
39385        // MIs[1] Rn
39386        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
39387        GIM_CheckIsSafeToFold, /*InsnID*/1,
39388        // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn))  =>  (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
39389        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDADD,
39390        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
39391        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
39392        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
39393        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39394        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39395        GIR_EraseFromParent, /*InsnID*/0,
39396        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39397        // GIR_Coverage, 2147,
39398        GIR_Done,
39399      // Label 1944: @106438
39400      GIM_Try, /*On fail goto*//*Label 1945*/ 106481, // Rule ID 1895 //
39401        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
39402        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
39403        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
39404        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
39405        // (saddsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (QADD:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
39406        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD,
39407        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
39408        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // a
39409        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b
39410        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39411        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39412        GIR_EraseFromParent, /*InsnID*/0,
39413        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39414        // GIR_Coverage, 1895,
39415        GIR_Done,
39416      // Label 1945: @106481
39417      GIM_Try, /*On fail goto*//*Label 1946*/ 106524, // Rule ID 2145 //
39418        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
39419        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
39420        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
39421        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
39422        // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)  =>  (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
39423        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QADD,
39424        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
39425        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
39426        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
39427        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39428        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39429        GIR_EraseFromParent, /*InsnID*/0,
39430        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39431        // GIR_Coverage, 2145,
39432        GIR_Done,
39433      // Label 1946: @106524
39434      GIM_Reject,
39435    // Label 1940: @106525
39436    GIM_Reject,
39437    // Label 1931: @106526
39438    GIM_Try, /*On fail goto*//*Label 1947*/ 106577, // Rule ID 838 //
39439      GIM_CheckFeatures, GIFBS_HasNEON,
39440      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
39441      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
39442      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
39443      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
39444      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39445      // (saddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VQADDsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
39446      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv1i64,
39447      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39448      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39449      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39450      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39451      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39452      GIR_EraseFromParent, /*InsnID*/0,
39453      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39454      // GIR_Coverage, 838,
39455      GIR_Done,
39456    // Label 1947: @106577
39457    GIM_Reject,
39458    // Label 1932: @106578
39459    GIM_Try, /*On fail goto*//*Label 1948*/ 106629, // Rule ID 833 //
39460      GIM_CheckFeatures, GIFBS_HasNEON,
39461      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
39462      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
39463      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
39464      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
39465      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39466      // (saddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
39467      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv2i32,
39468      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39469      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39470      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39471      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39472      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39473      GIR_EraseFromParent, /*InsnID*/0,
39474      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39475      // GIR_Coverage, 833,
39476      GIR_Done,
39477    // Label 1948: @106629
39478    GIM_Reject,
39479    // Label 1933: @106630
39480    GIM_Try, /*On fail goto*//*Label 1949*/ 106826,
39481      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
39482      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
39483      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39484      GIM_Try, /*On fail goto*//*Label 1950*/ 106715, // Rule ID 5845 //
39485        GIM_CheckFeatures, GIFBS_HasNEON,
39486        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39487        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
39488        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
39489        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
39490        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
39491        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
39492        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39493        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
39494        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39495        GIM_CheckIsSafeToFold, /*InsnID*/1,
39496        // (saddsat:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 2637:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$src1)  =>  (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
39497        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLALv2i64,
39498        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39499        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
39500        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
39501        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
39502        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39503        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39504        GIR_EraseFromParent, /*InsnID*/0,
39505        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39506        // GIR_Coverage, 5845,
39507        GIR_Done,
39508      // Label 1950: @106715
39509      GIM_Try, /*On fail goto*//*Label 1951*/ 106786, // Rule ID 2483 //
39510        GIM_CheckFeatures, GIFBS_HasNEON,
39511        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39512        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39513        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
39514        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
39515        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
39516        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
39517        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
39518        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39519        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
39520        GIM_CheckIsSafeToFold, /*InsnID*/1,
39521        // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 2637:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
39522        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLALv2i64,
39523        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39524        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
39525        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
39526        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
39527        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39528        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39529        GIR_EraseFromParent, /*InsnID*/0,
39530        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39531        // GIR_Coverage, 2483,
39532        GIR_Done,
39533      // Label 1951: @106786
39534      GIM_Try, /*On fail goto*//*Label 1952*/ 106825, // Rule ID 839 //
39535        GIM_CheckFeatures, GIFBS_HasNEON,
39536        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39537        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39538        // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VQADDsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
39539        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv2i64,
39540        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39541        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39542        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39543        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39544        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39545        GIR_EraseFromParent, /*InsnID*/0,
39546        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39547        // GIR_Coverage, 839,
39548        GIR_Done,
39549      // Label 1952: @106825
39550      GIM_Reject,
39551    // Label 1949: @106826
39552    GIM_Reject,
39553    // Label 1934: @106827
39554    GIM_Try, /*On fail goto*//*Label 1953*/ 106878, // Rule ID 832 //
39555      GIM_CheckFeatures, GIFBS_HasNEON,
39556      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
39557      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
39558      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
39559      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
39560      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39561      // (saddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
39562      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv4i16,
39563      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39564      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39565      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39566      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39567      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39568      GIR_EraseFromParent, /*InsnID*/0,
39569      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39570      // GIR_Coverage, 832,
39571      GIR_Done,
39572    // Label 1953: @106878
39573    GIM_Reject,
39574    // Label 1935: @106879
39575    GIM_Try, /*On fail goto*//*Label 1954*/ 107144,
39576      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
39577      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
39578      GIM_Try, /*On fail goto*//*Label 1955*/ 106964, // Rule ID 5844 //
39579        GIM_CheckFeatures, GIFBS_HasNEON,
39580        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39581        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39582        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
39583        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
39584        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
39585        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
39586        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
39587        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39588        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
39589        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39590        GIM_CheckIsSafeToFold, /*InsnID*/1,
39591        // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 2637:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
39592        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLALv4i32,
39593        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39594        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
39595        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
39596        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
39597        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39598        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39599        GIR_EraseFromParent, /*InsnID*/0,
39600        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39601        // GIR_Coverage, 5844,
39602        GIR_Done,
39603      // Label 1955: @106964
39604      GIM_Try, /*On fail goto*//*Label 1956*/ 107039, // Rule ID 2482 //
39605        GIM_CheckFeatures, GIFBS_HasNEON,
39606        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39607        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39608        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39609        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
39610        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
39611        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
39612        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
39613        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
39614        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39615        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
39616        GIM_CheckIsSafeToFold, /*InsnID*/1,
39617        // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 2637:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
39618        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLALv4i32,
39619        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39620        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
39621        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
39622        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
39623        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39624        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39625        GIR_EraseFromParent, /*InsnID*/0,
39626        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39627        // GIR_Coverage, 2482,
39628        GIR_Done,
39629      // Label 1956: @107039
39630      GIM_Try, /*On fail goto*//*Label 1957*/ 107082, // Rule ID 835 //
39631        GIM_CheckFeatures, GIFBS_HasNEON,
39632        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39633        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39634        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39635        // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
39636        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv4i32,
39637        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39638        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39639        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39640        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39641        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39642        GIR_EraseFromParent, /*InsnID*/0,
39643        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39644        // GIR_Coverage, 835,
39645        GIR_Done,
39646      // Label 1957: @107082
39647      GIM_Try, /*On fail goto*//*Label 1958*/ 107143, // Rule ID 3612 //
39648        GIM_CheckFeatures, GIFBS_HasMVEInt,
39649        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
39650        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
39651        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
39652        // (saddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VQADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
39653        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39654        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39655        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
39656        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQADDs32,
39657        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
39658        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39659        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39660        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
39661        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39662        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39663        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
39664        GIR_EraseFromParent, /*InsnID*/0,
39665        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39666        // GIR_Coverage, 3612,
39667        GIR_Done,
39668      // Label 1958: @107143
39669      GIM_Reject,
39670    // Label 1954: @107144
39671    GIM_Reject,
39672    // Label 1936: @107145
39673    GIM_Try, /*On fail goto*//*Label 1959*/ 107196, // Rule ID 836 //
39674      GIM_CheckFeatures, GIFBS_HasNEON,
39675      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
39676      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
39677      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
39678      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
39679      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39680      // (saddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VQADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
39681      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv8i8,
39682      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39683      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39684      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39685      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39686      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39687      GIR_EraseFromParent, /*InsnID*/0,
39688      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39689      // GIR_Coverage, 836,
39690      GIR_Done,
39691    // Label 1959: @107196
39692    GIM_Reject,
39693    // Label 1937: @107197
39694    GIM_Try, /*On fail goto*//*Label 1960*/ 107312,
39695      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
39696      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
39697      GIM_Try, /*On fail goto*//*Label 1961*/ 107250, // Rule ID 834 //
39698        GIM_CheckFeatures, GIFBS_HasNEON,
39699        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39700        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39701        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39702        // (saddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
39703        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv8i16,
39704        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39705        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39706        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39707        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39708        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39709        GIR_EraseFromParent, /*InsnID*/0,
39710        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39711        // GIR_Coverage, 834,
39712        GIR_Done,
39713      // Label 1961: @107250
39714      GIM_Try, /*On fail goto*//*Label 1962*/ 107311, // Rule ID 3609 //
39715        GIM_CheckFeatures, GIFBS_HasMVEInt,
39716        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
39717        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
39718        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
39719        // (saddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VQADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
39720        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39721        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39722        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
39723        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQADDs16,
39724        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
39725        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39726        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39727        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
39728        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39729        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39730        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
39731        GIR_EraseFromParent, /*InsnID*/0,
39732        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39733        // GIR_Coverage, 3609,
39734        GIR_Done,
39735      // Label 1962: @107311
39736      GIM_Reject,
39737    // Label 1960: @107312
39738    GIM_Reject,
39739    // Label 1938: @107313
39740    GIM_Try, /*On fail goto*//*Label 1963*/ 107428,
39741      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
39742      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
39743      GIM_Try, /*On fail goto*//*Label 1964*/ 107366, // Rule ID 837 //
39744        GIM_CheckFeatures, GIFBS_HasNEON,
39745        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39746        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39747        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39748        // (saddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VQADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
39749        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv16i8,
39750        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39751        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39752        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39753        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39754        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39755        GIR_EraseFromParent, /*InsnID*/0,
39756        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39757        // GIR_Coverage, 837,
39758        GIR_Done,
39759      // Label 1964: @107366
39760      GIM_Try, /*On fail goto*//*Label 1965*/ 107427, // Rule ID 3606 //
39761        GIM_CheckFeatures, GIFBS_HasMVEInt,
39762        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
39763        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
39764        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
39765        // (saddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VQADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
39766        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39767        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39768        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
39769        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQADDs8,
39770        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
39771        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39772        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39773        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
39774        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39775        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39776        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
39777        GIR_EraseFromParent, /*InsnID*/0,
39778        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39779        // GIR_Coverage, 3606,
39780        GIR_Done,
39781      // Label 1965: @107427
39782      GIM_Reject,
39783    // Label 1963: @107428
39784    GIM_Reject,
39785    // Label 1939: @107429
39786    GIM_Reject,
39787    // Label 30: @107430
39788    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 16, /*)*//*default:*//*Label 1974*/ 108058,
39789    /*GILLT_s64*//*Label 1966*/ 107450, 0,
39790    /*GILLT_v2s32*//*Label 1967*/ 107502,
39791    /*GILLT_v2s64*//*Label 1968*/ 107554, 0,
39792    /*GILLT_v4s16*//*Label 1969*/ 107606,
39793    /*GILLT_v4s32*//*Label 1970*/ 107658, 0, 0,
39794    /*GILLT_v8s8*//*Label 1971*/ 107774,
39795    /*GILLT_v8s16*//*Label 1972*/ 107826, 0, 0,
39796    /*GILLT_v16s8*//*Label 1973*/ 107942,
39797    // Label 1966: @107450
39798    GIM_Try, /*On fail goto*//*Label 1975*/ 107501, // Rule ID 1038 //
39799      GIM_CheckFeatures, GIFBS_HasNEON,
39800      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
39801      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
39802      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
39803      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
39804      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39805      // (usubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VQSUBuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
39806      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv1i64,
39807      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39808      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39809      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39810      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39811      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39812      GIR_EraseFromParent, /*InsnID*/0,
39813      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39814      // GIR_Coverage, 1038,
39815      GIR_Done,
39816    // Label 1975: @107501
39817    GIM_Reject,
39818    // Label 1967: @107502
39819    GIM_Try, /*On fail goto*//*Label 1976*/ 107553, // Rule ID 1033 //
39820      GIM_CheckFeatures, GIFBS_HasNEON,
39821      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
39822      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
39823      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
39824      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
39825      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39826      // (usubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
39827      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv2i32,
39828      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39829      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39830      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39831      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39832      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39833      GIR_EraseFromParent, /*InsnID*/0,
39834      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39835      // GIR_Coverage, 1033,
39836      GIR_Done,
39837    // Label 1976: @107553
39838    GIM_Reject,
39839    // Label 1968: @107554
39840    GIM_Try, /*On fail goto*//*Label 1977*/ 107605, // Rule ID 1039 //
39841      GIM_CheckFeatures, GIFBS_HasNEON,
39842      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
39843      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
39844      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39845      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39846      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39847      // (usubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VQSUBuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
39848      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv2i64,
39849      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39850      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39851      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39852      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39853      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39854      GIR_EraseFromParent, /*InsnID*/0,
39855      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39856      // GIR_Coverage, 1039,
39857      GIR_Done,
39858    // Label 1977: @107605
39859    GIM_Reject,
39860    // Label 1969: @107606
39861    GIM_Try, /*On fail goto*//*Label 1978*/ 107657, // Rule ID 1032 //
39862      GIM_CheckFeatures, GIFBS_HasNEON,
39863      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
39864      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
39865      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
39866      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
39867      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39868      // (usubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
39869      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv4i16,
39870      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39871      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39872      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39873      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39874      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39875      GIR_EraseFromParent, /*InsnID*/0,
39876      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39877      // GIR_Coverage, 1032,
39878      GIR_Done,
39879    // Label 1978: @107657
39880    GIM_Reject,
39881    // Label 1970: @107658
39882    GIM_Try, /*On fail goto*//*Label 1979*/ 107773,
39883      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
39884      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
39885      GIM_Try, /*On fail goto*//*Label 1980*/ 107711, // Rule ID 1035 //
39886        GIM_CheckFeatures, GIFBS_HasNEON,
39887        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39888        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39889        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39890        // (usubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
39891        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv4i32,
39892        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39893        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39894        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39895        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39896        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39897        GIR_EraseFromParent, /*InsnID*/0,
39898        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39899        // GIR_Coverage, 1035,
39900        GIR_Done,
39901      // Label 1980: @107711
39902      GIM_Try, /*On fail goto*//*Label 1981*/ 107772, // Rule ID 3639 //
39903        GIM_CheckFeatures, GIFBS_HasMVEInt,
39904        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
39905        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
39906        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
39907        // (usubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VQSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
39908        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39909        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39910        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
39911        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSUBu32,
39912        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
39913        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39914        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39915        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
39916        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39917        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39918        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
39919        GIR_EraseFromParent, /*InsnID*/0,
39920        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39921        // GIR_Coverage, 3639,
39922        GIR_Done,
39923      // Label 1981: @107772
39924      GIM_Reject,
39925    // Label 1979: @107773
39926    GIM_Reject,
39927    // Label 1971: @107774
39928    GIM_Try, /*On fail goto*//*Label 1982*/ 107825, // Rule ID 1036 //
39929      GIM_CheckFeatures, GIFBS_HasNEON,
39930      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
39931      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
39932      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
39933      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
39934      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39935      // (usubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VQSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
39936      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv8i8,
39937      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39938      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39939      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39940      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39941      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39942      GIR_EraseFromParent, /*InsnID*/0,
39943      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39944      // GIR_Coverage, 1036,
39945      GIR_Done,
39946    // Label 1982: @107825
39947    GIM_Reject,
39948    // Label 1972: @107826
39949    GIM_Try, /*On fail goto*//*Label 1983*/ 107941,
39950      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
39951      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
39952      GIM_Try, /*On fail goto*//*Label 1984*/ 107879, // Rule ID 1034 //
39953        GIM_CheckFeatures, GIFBS_HasNEON,
39954        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39955        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39956        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39957        // (usubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
39958        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv8i16,
39959        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39960        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39961        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39962        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39963        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39964        GIR_EraseFromParent, /*InsnID*/0,
39965        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39966        // GIR_Coverage, 1034,
39967        GIR_Done,
39968      // Label 1984: @107879
39969      GIM_Try, /*On fail goto*//*Label 1985*/ 107940, // Rule ID 3636 //
39970        GIM_CheckFeatures, GIFBS_HasMVEInt,
39971        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
39972        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
39973        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
39974        // (usubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VQSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
39975        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39976        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39977        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
39978        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSUBu16,
39979        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
39980        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39981        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39982        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
39983        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39984        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39985        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
39986        GIR_EraseFromParent, /*InsnID*/0,
39987        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39988        // GIR_Coverage, 3636,
39989        GIR_Done,
39990      // Label 1985: @107940
39991      GIM_Reject,
39992    // Label 1983: @107941
39993    GIM_Reject,
39994    // Label 1973: @107942
39995    GIM_Try, /*On fail goto*//*Label 1986*/ 108057,
39996      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
39997      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
39998      GIM_Try, /*On fail goto*//*Label 1987*/ 107995, // Rule ID 1037 //
39999        GIM_CheckFeatures, GIFBS_HasNEON,
40000        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
40001        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
40002        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
40003        // (usubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VQSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
40004        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv16i8,
40005        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40006        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40007        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40008        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40009        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40010        GIR_EraseFromParent, /*InsnID*/0,
40011        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40012        // GIR_Coverage, 1037,
40013        GIR_Done,
40014      // Label 1987: @107995
40015      GIM_Try, /*On fail goto*//*Label 1988*/ 108056, // Rule ID 3633 //
40016        GIM_CheckFeatures, GIFBS_HasMVEInt,
40017        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
40018        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
40019        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
40020        // (usubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VQSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
40021        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40022        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40023        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
40024        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSUBu8,
40025        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
40026        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
40027        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
40028        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
40029        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40030        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40031        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
40032        GIR_EraseFromParent, /*InsnID*/0,
40033        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40034        // GIR_Coverage, 3633,
40035        GIR_Done,
40036      // Label 1988: @108056
40037      GIM_Reject,
40038    // Label 1986: @108057
40039    GIM_Reject,
40040    // Label 1974: @108058
40041    GIM_Reject,
40042    // Label 31: @108059
40043    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 16, /*)*//*default:*//*Label 1998*/ 109053,
40044    /*GILLT_s32*//*Label 1989*/ 108080,
40045    /*GILLT_s64*//*Label 1990*/ 108300, 0,
40046    /*GILLT_v2s32*//*Label 1991*/ 108352,
40047    /*GILLT_v2s64*//*Label 1992*/ 108404, 0,
40048    /*GILLT_v4s16*//*Label 1993*/ 108526,
40049    /*GILLT_v4s32*//*Label 1994*/ 108578, 0, 0,
40050    /*GILLT_v8s8*//*Label 1995*/ 108769,
40051    /*GILLT_v8s16*//*Label 1996*/ 108821, 0, 0,
40052    /*GILLT_v16s8*//*Label 1997*/ 108937,
40053    // Label 1989: @108080
40054    GIM_Try, /*On fail goto*//*Label 1999*/ 108299,
40055      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
40056      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
40057      GIM_Try, /*On fail goto*//*Label 2000*/ 108151, // Rule ID 1898 //
40058        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
40059        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
40060        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
40061        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40062        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SADDSAT,
40063        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40064        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
40065        // MIs[1] Rn
40066        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
40067        GIM_CheckIsSafeToFold, /*InsnID*/1,
40068        // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn))  =>  (QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
40069        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDSUB,
40070        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
40071        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
40072        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
40073        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40074        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40075        GIR_EraseFromParent, /*InsnID*/0,
40076        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40077        // GIR_Coverage, 1898,
40078        GIR_Done,
40079      // Label 2000: @108151
40080      GIM_Try, /*On fail goto*//*Label 2001*/ 108212, // Rule ID 2148 //
40081        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
40082        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
40083        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
40084        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40085        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SADDSAT,
40086        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40087        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
40088        // MIs[1] Rn
40089        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
40090        GIM_CheckIsSafeToFold, /*InsnID*/1,
40091        // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn))  =>  (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
40092        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDSUB,
40093        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
40094        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
40095        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
40096        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40097        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40098        GIR_EraseFromParent, /*InsnID*/0,
40099        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40100        // GIR_Coverage, 2148,
40101        GIR_Done,
40102      // Label 2001: @108212
40103      GIM_Try, /*On fail goto*//*Label 2002*/ 108255, // Rule ID 1896 //
40104        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
40105        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
40106        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
40107        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
40108        // (ssubsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (QSUB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
40109        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB,
40110        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
40111        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // a
40112        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b
40113        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40114        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40115        GIR_EraseFromParent, /*InsnID*/0,
40116        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40117        // GIR_Coverage, 1896,
40118        GIR_Done,
40119      // Label 2002: @108255
40120      GIM_Try, /*On fail goto*//*Label 2003*/ 108298, // Rule ID 2146 //
40121        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
40122        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
40123        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
40124        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
40125        // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)  =>  (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
40126        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSUB,
40127        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
40128        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
40129        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
40130        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40131        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40132        GIR_EraseFromParent, /*InsnID*/0,
40133        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40134        // GIR_Coverage, 2146,
40135        GIR_Done,
40136      // Label 2003: @108298
40137      GIM_Reject,
40138    // Label 1999: @108299
40139    GIM_Reject,
40140    // Label 1990: @108300
40141    GIM_Try, /*On fail goto*//*Label 2004*/ 108351, // Rule ID 1030 //
40142      GIM_CheckFeatures, GIFBS_HasNEON,
40143      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
40144      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
40145      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
40146      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
40147      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
40148      // (ssubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VQSUBsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
40149      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv1i64,
40150      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40151      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40152      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40153      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40154      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40155      GIR_EraseFromParent, /*InsnID*/0,
40156      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40157      // GIR_Coverage, 1030,
40158      GIR_Done,
40159    // Label 2004: @108351
40160    GIM_Reject,
40161    // Label 1991: @108352
40162    GIM_Try, /*On fail goto*//*Label 2005*/ 108403, // Rule ID 1025 //
40163      GIM_CheckFeatures, GIFBS_HasNEON,
40164      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
40165      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
40166      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
40167      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
40168      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
40169      // (ssubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
40170      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv2i32,
40171      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40172      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40173      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40174      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40175      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40176      GIR_EraseFromParent, /*InsnID*/0,
40177      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40178      // GIR_Coverage, 1025,
40179      GIR_Done,
40180    // Label 2005: @108403
40181    GIM_Reject,
40182    // Label 1992: @108404
40183    GIM_Try, /*On fail goto*//*Label 2006*/ 108525,
40184      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
40185      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
40186      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
40187      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
40188      GIM_Try, /*On fail goto*//*Label 2007*/ 108489, // Rule ID 2490 //
40189        GIM_CheckFeatures, GIFBS_HasNEON,
40190        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40191        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
40192        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
40193        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
40194        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
40195        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
40196        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
40197        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
40198        GIM_CheckIsSafeToFold, /*InsnID*/1,
40199        // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 2637:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VQDMLSLv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
40200        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLSLv2i64,
40201        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40202        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
40203        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
40204        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
40205        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40206        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40207        GIR_EraseFromParent, /*InsnID*/0,
40208        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40209        // GIR_Coverage, 2490,
40210        GIR_Done,
40211      // Label 2007: @108489
40212      GIM_Try, /*On fail goto*//*Label 2008*/ 108524, // Rule ID 1031 //
40213        GIM_CheckFeatures, GIFBS_HasNEON,
40214        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
40215        // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VQSUBsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
40216        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv2i64,
40217        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40218        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40219        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40220        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40221        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40222        GIR_EraseFromParent, /*InsnID*/0,
40223        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40224        // GIR_Coverage, 1031,
40225        GIR_Done,
40226      // Label 2008: @108524
40227      GIM_Reject,
40228    // Label 2006: @108525
40229    GIM_Reject,
40230    // Label 1993: @108526
40231    GIM_Try, /*On fail goto*//*Label 2009*/ 108577, // Rule ID 1024 //
40232      GIM_CheckFeatures, GIFBS_HasNEON,
40233      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
40234      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
40235      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
40236      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
40237      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
40238      // (ssubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
40239      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv4i16,
40240      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40241      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40242      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40243      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40244      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40245      GIR_EraseFromParent, /*InsnID*/0,
40246      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40247      // GIR_Coverage, 1024,
40248      GIR_Done,
40249    // Label 2009: @108577
40250    GIM_Reject,
40251    // Label 1994: @108578
40252    GIM_Try, /*On fail goto*//*Label 2010*/ 108768,
40253      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
40254      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
40255      GIM_Try, /*On fail goto*//*Label 2011*/ 108663, // Rule ID 2489 //
40256        GIM_CheckFeatures, GIFBS_HasNEON,
40257        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
40258        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
40259        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40260        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
40261        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
40262        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
40263        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
40264        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
40265        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
40266        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
40267        GIM_CheckIsSafeToFold, /*InsnID*/1,
40268        // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 2637:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VQDMLSLv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
40269        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLSLv4i32,
40270        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40271        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
40272        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
40273        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
40274        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40275        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40276        GIR_EraseFromParent, /*InsnID*/0,
40277        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40278        // GIR_Coverage, 2489,
40279        GIR_Done,
40280      // Label 2011: @108663
40281      GIM_Try, /*On fail goto*//*Label 2012*/ 108706, // Rule ID 1027 //
40282        GIM_CheckFeatures, GIFBS_HasNEON,
40283        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
40284        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
40285        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
40286        // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
40287        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv4i32,
40288        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40289        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40290        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40291        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40292        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40293        GIR_EraseFromParent, /*InsnID*/0,
40294        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40295        // GIR_Coverage, 1027,
40296        GIR_Done,
40297      // Label 2012: @108706
40298      GIM_Try, /*On fail goto*//*Label 2013*/ 108767, // Rule ID 3630 //
40299        GIM_CheckFeatures, GIFBS_HasMVEInt,
40300        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
40301        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
40302        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
40303        // (ssubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VQSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
40304        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40305        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40306        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
40307        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSUBs32,
40308        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
40309        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
40310        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
40311        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
40312        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40313        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40314        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
40315        GIR_EraseFromParent, /*InsnID*/0,
40316        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40317        // GIR_Coverage, 3630,
40318        GIR_Done,
40319      // Label 2013: @108767
40320      GIM_Reject,
40321    // Label 2010: @108768
40322    GIM_Reject,
40323    // Label 1995: @108769
40324    GIM_Try, /*On fail goto*//*Label 2014*/ 108820, // Rule ID 1028 //
40325      GIM_CheckFeatures, GIFBS_HasNEON,
40326      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
40327      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
40328      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
40329      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
40330      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
40331      // (ssubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VQSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
40332      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv8i8,
40333      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40334      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40335      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40336      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40337      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40338      GIR_EraseFromParent, /*InsnID*/0,
40339      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40340      // GIR_Coverage, 1028,
40341      GIR_Done,
40342    // Label 2014: @108820
40343    GIM_Reject,
40344    // Label 1996: @108821
40345    GIM_Try, /*On fail goto*//*Label 2015*/ 108936,
40346      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
40347      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
40348      GIM_Try, /*On fail goto*//*Label 2016*/ 108874, // Rule ID 1026 //
40349        GIM_CheckFeatures, GIFBS_HasNEON,
40350        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
40351        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
40352        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
40353        // (ssubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
40354        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv8i16,
40355        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40356        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40357        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40358        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40359        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40360        GIR_EraseFromParent, /*InsnID*/0,
40361        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40362        // GIR_Coverage, 1026,
40363        GIR_Done,
40364      // Label 2016: @108874
40365      GIM_Try, /*On fail goto*//*Label 2017*/ 108935, // Rule ID 3627 //
40366        GIM_CheckFeatures, GIFBS_HasMVEInt,
40367        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
40368        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
40369        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
40370        // (ssubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VQSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
40371        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40372        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40373        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
40374        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSUBs16,
40375        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
40376        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
40377        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
40378        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
40379        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40380        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40381        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
40382        GIR_EraseFromParent, /*InsnID*/0,
40383        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40384        // GIR_Coverage, 3627,
40385        GIR_Done,
40386      // Label 2017: @108935
40387      GIM_Reject,
40388    // Label 2015: @108936
40389    GIM_Reject,
40390    // Label 1997: @108937
40391    GIM_Try, /*On fail goto*//*Label 2018*/ 109052,
40392      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
40393      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
40394      GIM_Try, /*On fail goto*//*Label 2019*/ 108990, // Rule ID 1029 //
40395        GIM_CheckFeatures, GIFBS_HasNEON,
40396        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
40397        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
40398        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
40399        // (ssubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VQSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
40400        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv16i8,
40401        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40402        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40403        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40404        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40405        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40406        GIR_EraseFromParent, /*InsnID*/0,
40407        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40408        // GIR_Coverage, 1029,
40409        GIR_Done,
40410      // Label 2019: @108990
40411      GIM_Try, /*On fail goto*//*Label 2020*/ 109051, // Rule ID 3624 //
40412        GIM_CheckFeatures, GIFBS_HasMVEInt,
40413        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
40414        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
40415        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
40416        // (ssubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VQSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
40417        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40418        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40419        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
40420        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSUBs8,
40421        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
40422        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
40423        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
40424        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
40425        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40426        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40427        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
40428        GIR_EraseFromParent, /*InsnID*/0,
40429        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40430        // GIR_Coverage, 3624,
40431        GIR_Done,
40432      // Label 2020: @109051
40433      GIM_Reject,
40434    // Label 2018: @109052
40435    GIM_Reject,
40436    // Label 1998: @109053
40437    GIM_Reject,
40438    // Label 32: @109054
40439    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2028*/ 111199,
40440    /*GILLT_s16*//*Label 2021*/ 109073,
40441    /*GILLT_s32*//*Label 2022*/ 109125,
40442    /*GILLT_s64*//*Label 2023*/ 110544, 0,
40443    /*GILLT_v2s32*//*Label 2024*/ 110596, 0, 0,
40444    /*GILLT_v4s16*//*Label 2025*/ 110648,
40445    /*GILLT_v4s32*//*Label 2026*/ 110831, 0, 0, 0,
40446    /*GILLT_v8s16*//*Label 2027*/ 110947,
40447    // Label 2021: @109073
40448    GIM_Try, /*On fail goto*//*Label 2029*/ 109124, // Rule ID 630 //
40449      GIM_CheckFeatures, GIFBS_HasFullFP16,
40450      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
40451      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
40452      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
40453      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
40454      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
40455      // (fadd:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)  =>  (VADDH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40456      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDH,
40457      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
40458      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
40459      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
40460      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40461      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40462      GIR_EraseFromParent, /*InsnID*/0,
40463      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40464      // GIR_Coverage, 630,
40465      GIR_Done,
40466    // Label 2029: @109124
40467    GIM_Reject,
40468    // Label 2022: @109125
40469    GIM_Try, /*On fail goto*//*Label 2030*/ 110543,
40470      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
40471      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
40472      GIM_Try, /*On fail goto*//*Label 2031*/ 109425, // Rule ID 6024 //
40473        GIM_CheckFeatures, GIFBS_HasNEON_UseFPVMLx_UseNEONForFP,
40474        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
40475        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40476        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
40477        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40478        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40479        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
40480        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
40481        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
40482        GIM_CheckIsSafeToFold, /*InsnID*/1,
40483        // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b), SPR:{ *:[f32] }:$acc)  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
40484        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
40485        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
40486        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
40487        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
40488        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
40489        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
40490        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
40491        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
40492        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
40493        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
40494        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
40495        GIR_BuildMI, /*InsnID*/11, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40496        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/RegState::Define,
40497        GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
40498        GIR_BuildMI, /*InsnID*/10, /*Opcode*/TargetOpcode::COPY,
40499        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/RegState::Define,
40500        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/10, /*TempRegFlags*/0,
40501        GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
40502        GIR_BuildMI, /*InsnID*/9, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40503        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/RegState::Define,
40504        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/9, /*TempRegFlags*/0,
40505        GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
40506        GIR_AddImm, /*InsnID*/9, /*Imm*/17,
40507        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, ARM::DPR_VFP2RegClassID,
40508        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, ARM::DPR_VFP2RegClassID,
40509        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, ARM::SPRRegClassID,
40510        GIR_BuildMI, /*InsnID*/8, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40511        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/RegState::Define,
40512        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
40513        GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::COPY,
40514        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define,
40515        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/0,
40516        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
40517        GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40518        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define,
40519        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0,
40520        GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
40521        GIR_AddImm, /*InsnID*/6, /*Imm*/17,
40522        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, ARM::DPR_VFP2RegClassID,
40523        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, ARM::DPR_VFP2RegClassID,
40524        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, ARM::SPRRegClassID,
40525        GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40526        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
40527        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
40528        GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
40529        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
40530        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
40531        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40532        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40533        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
40534        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
40535        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc
40536        GIR_AddImm, /*InsnID*/3, /*Imm*/17,
40537        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
40538        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
40539        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
40540        GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VMLAfd,
40541        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
40542        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
40543        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/5, /*TempRegFlags*/0,
40544        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/8, /*TempRegFlags*/0,
40545        GIR_AddImm, /*InsnID*/2, /*Imm*/14,
40546        GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40547        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40548        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
40549        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
40550        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
40551        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
40552        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
40553        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
40554        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
40555        GIR_EraseFromParent, /*InsnID*/0,
40556        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
40557        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
40558        // GIR_Coverage, 6024,
40559        GIR_Done,
40560      // Label 2031: @109425
40561      GIM_Try, /*On fail goto*//*Label 2032*/ 109715, // Rule ID 6025 //
40562        GIM_CheckFeatures, GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP,
40563        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
40564        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40565        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
40566        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40567        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40568        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
40569        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
40570        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
40571        GIM_CheckIsSafeToFold, /*InsnID*/1,
40572        // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b), SPR:{ *:[f32] }:$acc)  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
40573        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
40574        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
40575        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
40576        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
40577        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
40578        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
40579        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
40580        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
40581        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
40582        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
40583        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
40584        GIR_BuildMI, /*InsnID*/11, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40585        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/RegState::Define,
40586        GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
40587        GIR_BuildMI, /*InsnID*/10, /*Opcode*/TargetOpcode::COPY,
40588        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/RegState::Define,
40589        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/10, /*TempRegFlags*/0,
40590        GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
40591        GIR_BuildMI, /*InsnID*/9, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40592        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/RegState::Define,
40593        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/9, /*TempRegFlags*/0,
40594        GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
40595        GIR_AddImm, /*InsnID*/9, /*Imm*/17,
40596        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, ARM::DPR_VFP2RegClassID,
40597        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, ARM::DPR_VFP2RegClassID,
40598        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, ARM::SPRRegClassID,
40599        GIR_BuildMI, /*InsnID*/8, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40600        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/RegState::Define,
40601        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
40602        GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::COPY,
40603        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define,
40604        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/0,
40605        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
40606        GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40607        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define,
40608        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0,
40609        GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
40610        GIR_AddImm, /*InsnID*/6, /*Imm*/17,
40611        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, ARM::DPR_VFP2RegClassID,
40612        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, ARM::DPR_VFP2RegClassID,
40613        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, ARM::SPRRegClassID,
40614        GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40615        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
40616        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
40617        GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
40618        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
40619        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
40620        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40621        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40622        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
40623        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
40624        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc
40625        GIR_AddImm, /*InsnID*/3, /*Imm*/17,
40626        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
40627        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
40628        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
40629        GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VFMAfd,
40630        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
40631        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
40632        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/5, /*TempRegFlags*/0,
40633        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/8, /*TempRegFlags*/0,
40634        GIR_AddImm, /*InsnID*/2, /*Imm*/14,
40635        GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40636        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40637        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
40638        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
40639        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
40640        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
40641        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
40642        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
40643        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
40644        GIR_EraseFromParent, /*InsnID*/0,
40645        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
40646        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
40647        // GIR_Coverage, 6025,
40648        GIR_Done,
40649      // Label 2032: @109715
40650      GIM_Try, /*On fail goto*//*Label 2033*/ 110005, // Rule ID 2715 //
40651        GIM_CheckFeatures, GIFBS_HasNEON_UseFPVMLx_UseNEONForFP,
40652        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
40653        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
40654        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40655        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
40656        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40657        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40658        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
40659        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
40660        GIM_CheckIsSafeToFold, /*InsnID*/1,
40661        // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b))  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
40662        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
40663        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
40664        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
40665        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
40666        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
40667        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
40668        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
40669        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
40670        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
40671        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
40672        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
40673        GIR_BuildMI, /*InsnID*/11, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40674        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/RegState::Define,
40675        GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
40676        GIR_BuildMI, /*InsnID*/10, /*Opcode*/TargetOpcode::COPY,
40677        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/RegState::Define,
40678        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/10, /*TempRegFlags*/0,
40679        GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
40680        GIR_BuildMI, /*InsnID*/9, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40681        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/RegState::Define,
40682        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/9, /*TempRegFlags*/0,
40683        GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
40684        GIR_AddImm, /*InsnID*/9, /*Imm*/17,
40685        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, ARM::DPR_VFP2RegClassID,
40686        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, ARM::DPR_VFP2RegClassID,
40687        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, ARM::SPRRegClassID,
40688        GIR_BuildMI, /*InsnID*/8, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40689        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/RegState::Define,
40690        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
40691        GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::COPY,
40692        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define,
40693        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/0,
40694        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
40695        GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40696        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define,
40697        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0,
40698        GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
40699        GIR_AddImm, /*InsnID*/6, /*Imm*/17,
40700        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, ARM::DPR_VFP2RegClassID,
40701        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, ARM::DPR_VFP2RegClassID,
40702        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, ARM::SPRRegClassID,
40703        GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40704        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
40705        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
40706        GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
40707        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
40708        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
40709        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40710        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40711        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
40712        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
40713        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
40714        GIR_AddImm, /*InsnID*/3, /*Imm*/17,
40715        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
40716        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
40717        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
40718        GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VMLAfd,
40719        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
40720        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
40721        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/5, /*TempRegFlags*/0,
40722        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/8, /*TempRegFlags*/0,
40723        GIR_AddImm, /*InsnID*/2, /*Imm*/14,
40724        GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40725        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40726        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
40727        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
40728        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
40729        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
40730        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
40731        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
40732        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
40733        GIR_EraseFromParent, /*InsnID*/0,
40734        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
40735        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
40736        // GIR_Coverage, 2715,
40737        GIR_Done,
40738      // Label 2033: @110005
40739      GIM_Try, /*On fail goto*//*Label 2034*/ 110295, // Rule ID 2717 //
40740        GIM_CheckFeatures, GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP,
40741        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
40742        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
40743        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40744        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
40745        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40746        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40747        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
40748        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
40749        GIM_CheckIsSafeToFold, /*InsnID*/1,
40750        // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b))  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
40751        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
40752        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
40753        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
40754        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
40755        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
40756        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
40757        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
40758        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
40759        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
40760        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
40761        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
40762        GIR_BuildMI, /*InsnID*/11, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40763        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/RegState::Define,
40764        GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
40765        GIR_BuildMI, /*InsnID*/10, /*Opcode*/TargetOpcode::COPY,
40766        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/RegState::Define,
40767        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/10, /*TempRegFlags*/0,
40768        GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
40769        GIR_BuildMI, /*InsnID*/9, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40770        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/RegState::Define,
40771        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/9, /*TempRegFlags*/0,
40772        GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
40773        GIR_AddImm, /*InsnID*/9, /*Imm*/17,
40774        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, ARM::DPR_VFP2RegClassID,
40775        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, ARM::DPR_VFP2RegClassID,
40776        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, ARM::SPRRegClassID,
40777        GIR_BuildMI, /*InsnID*/8, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40778        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/RegState::Define,
40779        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
40780        GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::COPY,
40781        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define,
40782        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/0,
40783        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
40784        GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40785        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define,
40786        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0,
40787        GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
40788        GIR_AddImm, /*InsnID*/6, /*Imm*/17,
40789        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, ARM::DPR_VFP2RegClassID,
40790        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, ARM::DPR_VFP2RegClassID,
40791        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, ARM::SPRRegClassID,
40792        GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40793        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
40794        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
40795        GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
40796        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
40797        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
40798        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40799        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40800        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
40801        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
40802        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
40803        GIR_AddImm, /*InsnID*/3, /*Imm*/17,
40804        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
40805        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
40806        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
40807        GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VFMAfd,
40808        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
40809        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
40810        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/5, /*TempRegFlags*/0,
40811        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/8, /*TempRegFlags*/0,
40812        GIR_AddImm, /*InsnID*/2, /*Imm*/14,
40813        GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40814        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40815        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
40816        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
40817        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
40818        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
40819        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
40820        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
40821        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
40822        GIR_EraseFromParent, /*InsnID*/0,
40823        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
40824        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
40825        // GIR_Coverage, 2717,
40826        GIR_Done,
40827      // Label 2034: @110295
40828      GIM_Try, /*On fail goto*//*Label 2035*/ 110338, // Rule ID 629 //
40829        GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
40830        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
40831        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
40832        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
40833        // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)  =>  (VADDS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
40834        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDS,
40835        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
40836        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
40837        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
40838        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40839        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40840        GIR_EraseFromParent, /*InsnID*/0,
40841        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40842        // GIR_Coverage, 629,
40843        GIR_Done,
40844      // Label 2035: @110338
40845      GIM_Try, /*On fail goto*//*Label 2036*/ 110542, // Rule ID 2712 //
40846        GIM_CheckFeatures, GIFBS_HasNEON_UseNEONForFP,
40847        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
40848        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
40849        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
40850        // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VADDfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
40851        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
40852        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
40853        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
40854        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
40855        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
40856        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
40857        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
40858        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
40859        GIR_BuildMI, /*InsnID*/8, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40860        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/RegState::Define,
40861        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
40862        GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::COPY,
40863        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define,
40864        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/0,
40865        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
40866        GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40867        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define,
40868        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0,
40869        GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
40870        GIR_AddImm, /*InsnID*/6, /*Imm*/17,
40871        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, ARM::DPR_VFP2RegClassID,
40872        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, ARM::DPR_VFP2RegClassID,
40873        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, ARM::SPRRegClassID,
40874        GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40875        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
40876        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
40877        GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
40878        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
40879        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
40880        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40881        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40882        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
40883        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
40884        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
40885        GIR_AddImm, /*InsnID*/3, /*Imm*/17,
40886        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
40887        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
40888        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
40889        GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VADDfd,
40890        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
40891        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
40892        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/5, /*TempRegFlags*/0,
40893        GIR_AddImm, /*InsnID*/2, /*Imm*/14,
40894        GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40895        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40896        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
40897        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
40898        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
40899        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
40900        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
40901        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
40902        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
40903        GIR_EraseFromParent, /*InsnID*/0,
40904        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
40905        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
40906        // GIR_Coverage, 2712,
40907        GIR_Done,
40908      // Label 2036: @110542
40909      GIM_Reject,
40910    // Label 2030: @110543
40911    GIM_Reject,
40912    // Label 2023: @110544
40913    GIM_Try, /*On fail goto*//*Label 2037*/ 110595, // Rule ID 628 //
40914      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
40915      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
40916      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
40917      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
40918      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
40919      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
40920      // (fadd:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)  =>  (VADDD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
40921      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDD,
40922      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
40923      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
40924      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
40925      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40926      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40927      GIR_EraseFromParent, /*InsnID*/0,
40928      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40929      // GIR_Coverage, 628,
40930      GIR_Done,
40931    // Label 2037: @110595
40932    GIM_Reject,
40933    // Label 2024: @110596
40934    GIM_Try, /*On fail goto*//*Label 2038*/ 110647, // Rule ID 780 //
40935      GIM_CheckFeatures, GIFBS_HasNEON,
40936      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
40937      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
40938      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
40939      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
40940      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
40941      // (fadd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VADDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
40942      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDfd,
40943      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40944      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40945      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40946      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40947      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40948      GIR_EraseFromParent, /*InsnID*/0,
40949      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40950      // GIR_Coverage, 780,
40951      GIR_Done,
40952    // Label 2038: @110647
40953    GIM_Reject,
40954    // Label 2025: @110648
40955    GIM_Try, /*On fail goto*//*Label 2039*/ 110830,
40956      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
40957      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
40958      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
40959      GIM_Try, /*On fail goto*//*Label 2040*/ 110726, // Rule ID 5684 //
40960        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
40961        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40962        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
40963        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
40964        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
40965        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
40966        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
40967        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
40968        GIM_CheckIsSafeToFold, /*InsnID*/1,
40969        // (fadd:{ *:[v4f16] } (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm), DPR:{ *:[v4f16] }:$src1)  =>  (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
40970        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhd,
40971        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40972        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
40973        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
40974        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
40975        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40976        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40977        GIR_EraseFromParent, /*InsnID*/0,
40978        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40979        // GIR_Coverage, 5684,
40980        GIR_Done,
40981      // Label 2040: @110726
40982      GIM_Try, /*On fail goto*//*Label 2041*/ 110790, // Rule ID 961 //
40983        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
40984        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
40985        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40986        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
40987        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
40988        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
40989        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
40990        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
40991        GIM_CheckIsSafeToFold, /*InsnID*/1,
40992        // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm))  =>  (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
40993        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhd,
40994        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40995        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
40996        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
40997        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
40998        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40999        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41000        GIR_EraseFromParent, /*InsnID*/0,
41001        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41002        // GIR_Coverage, 961,
41003        GIR_Done,
41004      // Label 2041: @110790
41005      GIM_Try, /*On fail goto*//*Label 2042*/ 110829, // Rule ID 782 //
41006        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
41007        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41008        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
41009        // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VADDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
41010        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDhd,
41011        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41012        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41013        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41014        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41015        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41016        GIR_EraseFromParent, /*InsnID*/0,
41017        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41018        // GIR_Coverage, 782,
41019        GIR_Done,
41020      // Label 2042: @110829
41021      GIM_Reject,
41022    // Label 2039: @110830
41023    GIM_Reject,
41024    // Label 2026: @110831
41025    GIM_Try, /*On fail goto*//*Label 2043*/ 110946,
41026      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
41027      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
41028      GIM_Try, /*On fail goto*//*Label 2044*/ 110884, // Rule ID 781 //
41029        GIM_CheckFeatures, GIFBS_HasNEON,
41030        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
41031        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
41032        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
41033        // (fadd:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VADDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
41034        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDfq,
41035        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41036        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41037        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41038        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41039        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41040        GIR_EraseFromParent, /*InsnID*/0,
41041        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41042        // GIR_Coverage, 781,
41043        GIR_Done,
41044      // Label 2044: @110884
41045      GIM_Try, /*On fail goto*//*Label 2045*/ 110945, // Rule ID 4114 //
41046        GIM_CheckFeatures, GIFBS_HasMVEFloat,
41047        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
41048        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
41049        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
41050        // (fadd:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)  =>  (MVE_VADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
41051        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41052        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41053        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
41054        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDf32,
41055        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
41056        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
41057        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
41058        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
41059        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41060        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41061        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
41062        GIR_EraseFromParent, /*InsnID*/0,
41063        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41064        // GIR_Coverage, 4114,
41065        GIR_Done,
41066      // Label 2045: @110945
41067      GIM_Reject,
41068    // Label 2043: @110946
41069    GIM_Reject,
41070    // Label 2027: @110947
41071    GIM_Try, /*On fail goto*//*Label 2046*/ 111198,
41072      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
41073      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
41074      GIM_Try, /*On fail goto*//*Label 2047*/ 111025, // Rule ID 5685 //
41075        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
41076        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
41077        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41078        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
41079        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
41080        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
41081        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
41082        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
41083        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
41084        GIM_CheckIsSafeToFold, /*InsnID*/1,
41085        // (fadd:{ *:[v8f16] } (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm), QPR:{ *:[v8f16] }:$src1)  =>  (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
41086        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhq,
41087        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41088        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
41089        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41090        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41091        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41092        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41093        GIR_EraseFromParent, /*InsnID*/0,
41094        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41095        // GIR_Coverage, 5685,
41096        GIR_Done,
41097      // Label 2047: @111025
41098      GIM_Try, /*On fail goto*//*Label 2048*/ 111093, // Rule ID 962 //
41099        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
41100        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
41101        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
41102        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41103        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
41104        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
41105        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
41106        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
41107        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
41108        GIM_CheckIsSafeToFold, /*InsnID*/1,
41109        // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm))  =>  (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
41110        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhq,
41111        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41112        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
41113        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41114        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41115        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41116        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41117        GIR_EraseFromParent, /*InsnID*/0,
41118        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41119        // GIR_Coverage, 962,
41120        GIR_Done,
41121      // Label 2048: @111093
41122      GIM_Try, /*On fail goto*//*Label 2049*/ 111136, // Rule ID 783 //
41123        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
41124        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
41125        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
41126        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
41127        // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VADDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
41128        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDhq,
41129        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41130        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41132        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41133        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41134        GIR_EraseFromParent, /*InsnID*/0,
41135        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41136        // GIR_Coverage, 783,
41137        GIR_Done,
41138      // Label 2049: @111136
41139      GIM_Try, /*On fail goto*//*Label 2050*/ 111197, // Rule ID 4118 //
41140        GIM_CheckFeatures, GIFBS_HasMVEFloat,
41141        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
41142        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
41143        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
41144        // (fadd:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)  =>  (MVE_VADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
41145        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41146        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41147        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
41148        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDf16,
41149        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
41150        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
41151        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
41152        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
41153        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41154        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41155        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
41156        GIR_EraseFromParent, /*InsnID*/0,
41157        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41158        // GIR_Coverage, 4118,
41159        GIR_Done,
41160      // Label 2050: @111197
41161      GIM_Reject,
41162    // Label 2046: @111198
41163    GIM_Reject,
41164    // Label 2028: @111199
41165    GIM_Reject,
41166    // Label 33: @111200
41167    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2058*/ 112757,
41168    /*GILLT_s16*//*Label 2051*/ 111219,
41169    /*GILLT_s32*//*Label 2052*/ 111271,
41170    /*GILLT_s64*//*Label 2053*/ 112110, 0,
41171    /*GILLT_v2s32*//*Label 2054*/ 112162, 0, 0,
41172    /*GILLT_v4s16*//*Label 2055*/ 112214,
41173    /*GILLT_v4s32*//*Label 2056*/ 112389, 0, 0, 0,
41174    /*GILLT_v8s16*//*Label 2057*/ 112505,
41175    // Label 2051: @111219
41176    GIM_Try, /*On fail goto*//*Label 2059*/ 111270, // Rule ID 633 //
41177      GIM_CheckFeatures, GIFBS_HasFullFP16,
41178      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
41179      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
41180      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
41181      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
41182      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
41183      // (fsub:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)  =>  (VSUBH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
41184      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBH,
41185      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41186      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
41187      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
41188      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41189      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41190      GIR_EraseFromParent, /*InsnID*/0,
41191      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41192      // GIR_Coverage, 633,
41193      GIR_Done,
41194    // Label 2059: @111270
41195    GIM_Reject,
41196    // Label 2052: @111271
41197    GIM_Try, /*On fail goto*//*Label 2060*/ 112109,
41198      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
41199      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
41200      GIM_Try, /*On fail goto*//*Label 2061*/ 111571, // Rule ID 2716 //
41201        GIM_CheckFeatures, GIFBS_HasNEON_UseFPVMLx_UseNEONForFP,
41202        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
41203        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41204        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41205        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
41206        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41207        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41208        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41209        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
41210        GIM_CheckIsSafeToFold, /*InsnID*/1,
41211        // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b))  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
41212        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41213        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
41214        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41215        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
41216        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
41217        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
41218        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
41219        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
41220        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
41221        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
41222        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
41223        GIR_BuildMI, /*InsnID*/11, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41224        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/RegState::Define,
41225        GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
41226        GIR_BuildMI, /*InsnID*/10, /*Opcode*/TargetOpcode::COPY,
41227        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/RegState::Define,
41228        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/10, /*TempRegFlags*/0,
41229        GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
41230        GIR_BuildMI, /*InsnID*/9, /*Opcode*/TargetOpcode::INSERT_SUBREG,
41231        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/RegState::Define,
41232        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/9, /*TempRegFlags*/0,
41233        GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
41234        GIR_AddImm, /*InsnID*/9, /*Imm*/17,
41235        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, ARM::DPR_VFP2RegClassID,
41236        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, ARM::DPR_VFP2RegClassID,
41237        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, ARM::SPRRegClassID,
41238        GIR_BuildMI, /*InsnID*/8, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41239        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/RegState::Define,
41240        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
41241        GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::COPY,
41242        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define,
41243        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/0,
41244        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
41245        GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG,
41246        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define,
41247        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0,
41248        GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
41249        GIR_AddImm, /*InsnID*/6, /*Imm*/17,
41250        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, ARM::DPR_VFP2RegClassID,
41251        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, ARM::DPR_VFP2RegClassID,
41252        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, ARM::SPRRegClassID,
41253        GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41254        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
41255        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
41256        GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
41257        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
41258        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
41259        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41260        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
41261        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
41262        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
41263        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
41264        GIR_AddImm, /*InsnID*/3, /*Imm*/17,
41265        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
41266        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
41267        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
41268        GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VMLSfd,
41269        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
41270        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
41271        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/5, /*TempRegFlags*/0,
41272        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/8, /*TempRegFlags*/0,
41273        GIR_AddImm, /*InsnID*/2, /*Imm*/14,
41274        GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41275        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41276        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
41277        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
41278        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
41279        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41280        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
41281        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
41282        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
41283        GIR_EraseFromParent, /*InsnID*/0,
41284        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
41285        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
41286        // GIR_Coverage, 2716,
41287        GIR_Done,
41288      // Label 2061: @111571
41289      GIM_Try, /*On fail goto*//*Label 2062*/ 111861, // Rule ID 2718 //
41290        GIM_CheckFeatures, GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP,
41291        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
41292        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41293        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41294        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
41295        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41296        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41297        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41298        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
41299        GIM_CheckIsSafeToFold, /*InsnID*/1,
41300        // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b))  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
41301        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41302        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
41303        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41304        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
41305        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
41306        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
41307        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
41308        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
41309        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
41310        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
41311        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
41312        GIR_BuildMI, /*InsnID*/11, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41313        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/RegState::Define,
41314        GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
41315        GIR_BuildMI, /*InsnID*/10, /*Opcode*/TargetOpcode::COPY,
41316        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/RegState::Define,
41317        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/10, /*TempRegFlags*/0,
41318        GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
41319        GIR_BuildMI, /*InsnID*/9, /*Opcode*/TargetOpcode::INSERT_SUBREG,
41320        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/RegState::Define,
41321        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/9, /*TempRegFlags*/0,
41322        GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
41323        GIR_AddImm, /*InsnID*/9, /*Imm*/17,
41324        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, ARM::DPR_VFP2RegClassID,
41325        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, ARM::DPR_VFP2RegClassID,
41326        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, ARM::SPRRegClassID,
41327        GIR_BuildMI, /*InsnID*/8, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41328        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/RegState::Define,
41329        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
41330        GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::COPY,
41331        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define,
41332        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/0,
41333        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
41334        GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG,
41335        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define,
41336        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0,
41337        GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
41338        GIR_AddImm, /*InsnID*/6, /*Imm*/17,
41339        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, ARM::DPR_VFP2RegClassID,
41340        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, ARM::DPR_VFP2RegClassID,
41341        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, ARM::SPRRegClassID,
41342        GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41343        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
41344        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
41345        GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
41346        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
41347        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
41348        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41349        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
41350        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
41351        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
41352        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
41353        GIR_AddImm, /*InsnID*/3, /*Imm*/17,
41354        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
41355        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
41356        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
41357        GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VFMSfd,
41358        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
41359        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
41360        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/5, /*TempRegFlags*/0,
41361        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/8, /*TempRegFlags*/0,
41362        GIR_AddImm, /*InsnID*/2, /*Imm*/14,
41363        GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41364        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41365        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
41366        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
41367        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
41368        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41369        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
41370        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
41371        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
41372        GIR_EraseFromParent, /*InsnID*/0,
41373        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
41374        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
41375        // GIR_Coverage, 2718,
41376        GIR_Done,
41377      // Label 2062: @111861
41378      GIM_Try, /*On fail goto*//*Label 2063*/ 111904, // Rule ID 632 //
41379        GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
41380        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
41381        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41382        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
41383        // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)  =>  (VSUBS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
41384        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBS,
41385        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41386        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
41387        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
41388        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41389        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41390        GIR_EraseFromParent, /*InsnID*/0,
41391        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41392        // GIR_Coverage, 632,
41393        GIR_Done,
41394      // Label 2063: @111904
41395      GIM_Try, /*On fail goto*//*Label 2064*/ 112108, // Rule ID 2713 //
41396        GIM_CheckFeatures, GIFBS_HasNEON_UseNEONForFP,
41397        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
41398        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41399        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
41400        // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VSUBfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
41401        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41402        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
41403        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41404        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
41405        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
41406        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
41407        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
41408        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
41409        GIR_BuildMI, /*InsnID*/8, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41410        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/RegState::Define,
41411        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
41412        GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::COPY,
41413        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define,
41414        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/0,
41415        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
41416        GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG,
41417        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define,
41418        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0,
41419        GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
41420        GIR_AddImm, /*InsnID*/6, /*Imm*/17,
41421        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, ARM::DPR_VFP2RegClassID,
41422        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, ARM::DPR_VFP2RegClassID,
41423        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, ARM::SPRRegClassID,
41424        GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41425        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
41426        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
41427        GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
41428        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
41429        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
41430        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41431        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
41432        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
41433        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
41434        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
41435        GIR_AddImm, /*InsnID*/3, /*Imm*/17,
41436        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
41437        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
41438        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
41439        GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VSUBfd,
41440        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
41441        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
41442        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/5, /*TempRegFlags*/0,
41443        GIR_AddImm, /*InsnID*/2, /*Imm*/14,
41444        GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41445        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41446        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
41447        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
41448        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
41449        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41450        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
41451        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
41452        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
41453        GIR_EraseFromParent, /*InsnID*/0,
41454        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
41455        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
41456        // GIR_Coverage, 2713,
41457        GIR_Done,
41458      // Label 2064: @112108
41459      GIM_Reject,
41460    // Label 2060: @112109
41461    GIM_Reject,
41462    // Label 2053: @112110
41463    GIM_Try, /*On fail goto*//*Label 2065*/ 112161, // Rule ID 631 //
41464      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
41465      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
41466      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
41467      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
41468      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41469      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
41470      // (fsub:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)  =>  (VSUBD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
41471      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBD,
41472      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
41473      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
41474      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
41475      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41476      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41477      GIR_EraseFromParent, /*InsnID*/0,
41478      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41479      // GIR_Coverage, 631,
41480      GIR_Done,
41481    // Label 2065: @112161
41482    GIM_Reject,
41483    // Label 2054: @112162
41484    GIM_Try, /*On fail goto*//*Label 2066*/ 112213, // Rule ID 984 //
41485      GIM_CheckFeatures, GIFBS_HasNEON,
41486      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
41487      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
41488      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
41489      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41490      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
41491      // (fsub:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VSUBfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
41492      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBfd,
41493      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41494      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41495      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41496      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41497      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41498      GIR_EraseFromParent, /*InsnID*/0,
41499      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41500      // GIR_Coverage, 984,
41501      GIR_Done,
41502    // Label 2066: @112213
41503    GIM_Reject,
41504    // Label 2055: @112214
41505    GIM_Try, /*On fail goto*//*Label 2067*/ 112388,
41506      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
41507      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
41508      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
41509      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41510      GIM_Try, /*On fail goto*//*Label 2068*/ 112292, // Rule ID 939 //
41511        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFPVMLx,
41512        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41513        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
41514        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
41515        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
41516        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41517        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
41518        GIM_CheckIsSafeToFold, /*InsnID*/1,
41519        // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm))  =>  (VMLShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
41520        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLShd,
41521        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41522        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
41523        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41524        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41525        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41526        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41527        GIR_EraseFromParent, /*InsnID*/0,
41528        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41529        // GIR_Coverage, 939,
41530        GIR_Done,
41531      // Label 2068: @112292
41532      GIM_Try, /*On fail goto*//*Label 2069*/ 112352, // Rule ID 965 //
41533        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
41534        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41535        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
41536        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
41537        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
41538        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41539        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
41540        GIM_CheckIsSafeToFold, /*InsnID*/1,
41541        // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm))  =>  (VFMShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
41542        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMShd,
41543        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41544        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
41545        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41546        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41547        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41548        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41549        GIR_EraseFromParent, /*InsnID*/0,
41550        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41551        // GIR_Coverage, 965,
41552        GIR_Done,
41553      // Label 2069: @112352
41554      GIM_Try, /*On fail goto*//*Label 2070*/ 112387, // Rule ID 986 //
41555        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
41556        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
41557        // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VSUBhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
41558        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBhd,
41559        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41560        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41561        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41562        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41563        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41564        GIR_EraseFromParent, /*InsnID*/0,
41565        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41566        // GIR_Coverage, 986,
41567        GIR_Done,
41568      // Label 2070: @112387
41569      GIM_Reject,
41570    // Label 2067: @112388
41571    GIM_Reject,
41572    // Label 2056: @112389
41573    GIM_Try, /*On fail goto*//*Label 2071*/ 112504,
41574      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
41575      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
41576      GIM_Try, /*On fail goto*//*Label 2072*/ 112442, // Rule ID 985 //
41577        GIM_CheckFeatures, GIFBS_HasNEON,
41578        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
41579        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
41580        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
41581        // (fsub:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VSUBfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
41582        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBfq,
41583        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41584        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41585        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41586        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41587        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41588        GIR_EraseFromParent, /*InsnID*/0,
41589        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41590        // GIR_Coverage, 985,
41591        GIR_Done,
41592      // Label 2072: @112442
41593      GIM_Try, /*On fail goto*//*Label 2073*/ 112503, // Rule ID 4122 //
41594        GIM_CheckFeatures, GIFBS_HasMVEFloat,
41595        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
41596        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
41597        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
41598        // (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)  =>  (MVE_VSUBf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
41599        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41600        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41601        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
41602        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBf32,
41603        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
41604        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
41605        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
41606        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
41607        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41608        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41609        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
41610        GIR_EraseFromParent, /*InsnID*/0,
41611        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41612        // GIR_Coverage, 4122,
41613        GIR_Done,
41614      // Label 2073: @112503
41615      GIM_Reject,
41616    // Label 2071: @112504
41617    GIM_Reject,
41618    // Label 2057: @112505
41619    GIM_Try, /*On fail goto*//*Label 2074*/ 112756,
41620      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
41621      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
41622      GIM_Try, /*On fail goto*//*Label 2075*/ 112583, // Rule ID 940 //
41623        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFPVMLx,
41624        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
41625        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
41626        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41627        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
41628        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
41629        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
41630        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
41631        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
41632        GIM_CheckIsSafeToFold, /*InsnID*/1,
41633        // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm))  =>  (VMLShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
41634        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLShq,
41635        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41636        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
41637        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41638        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41639        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41640        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41641        GIR_EraseFromParent, /*InsnID*/0,
41642        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41643        // GIR_Coverage, 940,
41644        GIR_Done,
41645      // Label 2075: @112583
41646      GIM_Try, /*On fail goto*//*Label 2076*/ 112651, // Rule ID 966 //
41647        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
41648        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
41649        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
41650        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41651        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
41652        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
41653        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
41654        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
41655        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
41656        GIM_CheckIsSafeToFold, /*InsnID*/1,
41657        // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm))  =>  (VFMShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
41658        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMShq,
41659        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41660        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
41661        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41662        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41663        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41664        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41665        GIR_EraseFromParent, /*InsnID*/0,
41666        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41667        // GIR_Coverage, 966,
41668        GIR_Done,
41669      // Label 2076: @112651
41670      GIM_Try, /*On fail goto*//*Label 2077*/ 112694, // Rule ID 987 //
41671        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
41672        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
41673        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
41674        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
41675        // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VSUBhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
41676        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBhq,
41677        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41678        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41679        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41680        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41681        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41682        GIR_EraseFromParent, /*InsnID*/0,
41683        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41684        // GIR_Coverage, 987,
41685        GIR_Done,
41686      // Label 2077: @112694
41687      GIM_Try, /*On fail goto*//*Label 2078*/ 112755, // Rule ID 4126 //
41688        GIM_CheckFeatures, GIFBS_HasMVEFloat,
41689        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
41690        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
41691        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
41692        // (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)  =>  (MVE_VSUBf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
41693        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41694        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41695        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
41696        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBf16,
41697        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
41698        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
41699        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
41700        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
41701        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41702        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41703        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
41704        GIR_EraseFromParent, /*InsnID*/0,
41705        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41706        // GIR_Coverage, 4126,
41707        GIR_Done,
41708      // Label 2078: @112755
41709      GIM_Reject,
41710    // Label 2074: @112756
41711    GIM_Reject,
41712    // Label 2058: @112757
41713    GIM_Reject,
41714    // Label 34: @112758
41715    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2086*/ 113695,
41716    /*GILLT_s16*//*Label 2079*/ 112777,
41717    /*GILLT_s32*//*Label 2080*/ 112829,
41718    /*GILLT_s64*//*Label 2081*/ 113200, 0,
41719    /*GILLT_v2s32*//*Label 2082*/ 113359, 0, 0,
41720    /*GILLT_v4s16*//*Label 2083*/ 113411,
41721    /*GILLT_v4s32*//*Label 2084*/ 113463, 0, 0, 0,
41722    /*GILLT_v8s16*//*Label 2085*/ 113579,
41723    // Label 2079: @112777
41724    GIM_Try, /*On fail goto*//*Label 2087*/ 112828, // Rule ID 639 //
41725      GIM_CheckFeatures, GIFBS_HasFullFP16,
41726      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
41727      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
41728      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
41729      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
41730      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
41731      // (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)  =>  (VMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
41732      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULH,
41733      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41734      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
41735      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
41736      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41737      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41738      GIR_EraseFromParent, /*InsnID*/0,
41739      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41740      // GIR_Coverage, 639,
41741      GIR_Done,
41742    // Label 2087: @112828
41743    GIM_Reject,
41744    // Label 2080: @112829
41745    GIM_Try, /*On fail goto*//*Label 2088*/ 113199,
41746      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
41747      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
41748      GIM_Try, /*On fail goto*//*Label 2089*/ 112895, // Rule ID 2300 //
41749        GIM_CheckFeatures, GIFBS_NoHonorSignDependentRounding,
41750        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
41751        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41752        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
41753        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41754        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41755        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
41756        GIM_CheckIsSafeToFold, /*InsnID*/1,
41757        // (fmul:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a), SPR:{ *:[f32] }:$b)  =>  (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)
41758        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULS,
41759        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41760        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
41761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b
41762        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41763        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41764        GIR_EraseFromParent, /*InsnID*/0,
41765        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41766        // GIR_Coverage, 2300,
41767        GIR_Done,
41768      // Label 2089: @112895
41769      GIM_Try, /*On fail goto*//*Label 2090*/ 112951, // Rule ID 5811 //
41770        GIM_CheckFeatures, GIFBS_NoHonorSignDependentRounding,
41771        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
41772        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41773        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41774        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
41775        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41776        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41777        GIM_CheckIsSafeToFold, /*InsnID*/1,
41778        // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$b, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a))  =>  (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)
41779        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULS,
41780        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41781        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
41782        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // b
41783        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41784        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41785        GIR_EraseFromParent, /*InsnID*/0,
41786        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41787        // GIR_Coverage, 5811,
41788        GIR_Done,
41789      // Label 2090: @112951
41790      GIM_Try, /*On fail goto*//*Label 2091*/ 112994, // Rule ID 638 //
41791        GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
41792        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
41793        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41794        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
41795        // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)  =>  (VMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
41796        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULS,
41797        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41798        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
41799        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
41800        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41801        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41802        GIR_EraseFromParent, /*InsnID*/0,
41803        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41804        // GIR_Coverage, 638,
41805        GIR_Done,
41806      // Label 2091: @112994
41807      GIM_Try, /*On fail goto*//*Label 2092*/ 113198, // Rule ID 2714 //
41808        GIM_CheckFeatures, GIFBS_HasNEON_UseNEONForFP,
41809        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
41810        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41811        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
41812        // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMULfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
41813        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41814        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
41815        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41816        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
41817        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
41818        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
41819        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
41820        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
41821        GIR_BuildMI, /*InsnID*/8, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41822        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/RegState::Define,
41823        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
41824        GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::COPY,
41825        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define,
41826        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/0,
41827        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
41828        GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG,
41829        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define,
41830        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0,
41831        GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
41832        GIR_AddImm, /*InsnID*/6, /*Imm*/17,
41833        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, ARM::DPR_VFP2RegClassID,
41834        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, ARM::DPR_VFP2RegClassID,
41835        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, ARM::SPRRegClassID,
41836        GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41837        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
41838        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
41839        GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
41840        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
41841        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
41842        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41843        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
41844        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
41845        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
41846        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
41847        GIR_AddImm, /*InsnID*/3, /*Imm*/17,
41848        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
41849        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
41850        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
41851        GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VMULfd,
41852        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
41853        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
41854        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/5, /*TempRegFlags*/0,
41855        GIR_AddImm, /*InsnID*/2, /*Imm*/14,
41856        GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41857        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41858        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
41859        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
41860        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
41861        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41862        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
41863        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
41864        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
41865        GIR_EraseFromParent, /*InsnID*/0,
41866        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
41867        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
41868        // GIR_Coverage, 2714,
41869        GIR_Done,
41870      // Label 2092: @113198
41871      GIM_Reject,
41872    // Label 2088: @113199
41873    GIM_Reject,
41874    // Label 2081: @113200
41875    GIM_Try, /*On fail goto*//*Label 2093*/ 113358,
41876      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
41877      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
41878      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
41879      GIM_Try, /*On fail goto*//*Label 2094*/ 113266, // Rule ID 2299 //
41880        GIM_CheckFeatures, GIFBS_HasDPVFP_NoHonorSignDependentRounding,
41881        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41882        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
41883        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41884        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41885        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
41886        GIM_CheckIsSafeToFold, /*InsnID*/1,
41887        // (fmul:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a), DPR:{ *:[f64] }:$b)  =>  (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b)
41888        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULD,
41889        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
41890        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
41891        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b
41892        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41893        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41894        GIR_EraseFromParent, /*InsnID*/0,
41895        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41896        // GIR_Coverage, 2299,
41897        GIR_Done,
41898      // Label 2094: @113266
41899      GIM_Try, /*On fail goto*//*Label 2095*/ 113318, // Rule ID 5810 //
41900        GIM_CheckFeatures, GIFBS_HasDPVFP_NoHonorSignDependentRounding,
41901        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41902        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41903        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
41904        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41905        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41906        GIM_CheckIsSafeToFold, /*InsnID*/1,
41907        // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$b, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a))  =>  (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b)
41908        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULD,
41909        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
41910        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
41911        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // b
41912        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41913        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41914        GIR_EraseFromParent, /*InsnID*/0,
41915        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41916        // GIR_Coverage, 5810,
41917        GIR_Done,
41918      // Label 2095: @113318
41919      GIM_Try, /*On fail goto*//*Label 2096*/ 113357, // Rule ID 637 //
41920        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
41921        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41922        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
41923        // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)  =>  (VMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
41924        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULD,
41925        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
41926        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
41927        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
41928        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41929        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41930        GIR_EraseFromParent, /*InsnID*/0,
41931        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41932        // GIR_Coverage, 637,
41933        GIR_Done,
41934      // Label 2096: @113357
41935      GIM_Reject,
41936    // Label 2093: @113358
41937    GIM_Reject,
41938    // Label 2082: @113359
41939    GIM_Try, /*On fail goto*//*Label 2097*/ 113410, // Rule ID 859 //
41940      GIM_CheckFeatures, GIFBS_HasNEON,
41941      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
41942      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
41943      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
41944      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41945      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
41946      // (fmul:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VMULfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
41947      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULfd,
41948      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41949      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41950      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41951      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41952      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41953      GIR_EraseFromParent, /*InsnID*/0,
41954      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41955      // GIR_Coverage, 859,
41956      GIR_Done,
41957    // Label 2097: @113410
41958    GIM_Reject,
41959    // Label 2083: @113411
41960    GIM_Try, /*On fail goto*//*Label 2098*/ 113462, // Rule ID 861 //
41961      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
41962      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
41963      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
41964      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
41965      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41966      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
41967      // (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VMULhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
41968      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULhd,
41969      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41970      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41971      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41972      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41973      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41974      GIR_EraseFromParent, /*InsnID*/0,
41975      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41976      // GIR_Coverage, 861,
41977      GIR_Done,
41978    // Label 2098: @113462
41979    GIM_Reject,
41980    // Label 2084: @113463
41981    GIM_Try, /*On fail goto*//*Label 2099*/ 113578,
41982      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
41983      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
41984      GIM_Try, /*On fail goto*//*Label 2100*/ 113516, // Rule ID 860 //
41985        GIM_CheckFeatures, GIFBS_HasNEON,
41986        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
41987        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
41988        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
41989        // (fmul:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VMULfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
41990        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULfq,
41991        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41992        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41993        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41994        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41995        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41996        GIR_EraseFromParent, /*InsnID*/0,
41997        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41998        // GIR_Coverage, 860,
41999        GIR_Done,
42000      // Label 2100: @113516
42001      GIM_Try, /*On fail goto*//*Label 2101*/ 113577, // Rule ID 4088 //
42002        GIM_CheckFeatures, GIFBS_HasMVEFloat,
42003        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
42004        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
42005        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
42006        // (fmul:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)  =>  (MVE_VMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
42007        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42008        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
42009        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
42010        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULf32,
42011        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
42012        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
42013        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
42014        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
42015        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42016        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42017        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42018        GIR_EraseFromParent, /*InsnID*/0,
42019        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42020        // GIR_Coverage, 4088,
42021        GIR_Done,
42022      // Label 2101: @113577
42023      GIM_Reject,
42024    // Label 2099: @113578
42025    GIM_Reject,
42026    // Label 2085: @113579
42027    GIM_Try, /*On fail goto*//*Label 2102*/ 113694,
42028      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
42029      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
42030      GIM_Try, /*On fail goto*//*Label 2103*/ 113632, // Rule ID 862 //
42031        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
42032        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
42033        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
42034        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
42035        // (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VMULhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
42036        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULhq,
42037        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
42038        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
42039        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
42040        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42041        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42042        GIR_EraseFromParent, /*InsnID*/0,
42043        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42044        // GIR_Coverage, 862,
42045        GIR_Done,
42046      // Label 2103: @113632
42047      GIM_Try, /*On fail goto*//*Label 2104*/ 113693, // Rule ID 4092 //
42048        GIM_CheckFeatures, GIFBS_HasMVEFloat,
42049        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
42050        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
42051        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
42052        // (fmul:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)  =>  (MVE_VMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
42053        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42054        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
42055        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
42056        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULf16,
42057        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
42058        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
42059        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
42060        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
42061        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42062        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42063        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42064        GIR_EraseFromParent, /*InsnID*/0,
42065        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42066        // GIR_Coverage, 4092,
42067        GIR_Done,
42068      // Label 2104: @113693
42069      GIM_Reject,
42070    // Label 2102: @113694
42071    GIM_Reject,
42072    // Label 2086: @113695
42073    GIM_Reject,
42074    // Label 35: @113696
42075    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2112*/ 115396,
42076    /*GILLT_s16*//*Label 2105*/ 113715,
42077    /*GILLT_s32*//*Label 2106*/ 114108,
42078    /*GILLT_s64*//*Label 2107*/ 114501, 0,
42079    /*GILLT_v2s32*//*Label 2108*/ 114894, 0, 0,
42080    /*GILLT_v4s16*//*Label 2109*/ 115081,
42081    /*GILLT_v4s32*//*Label 2110*/ 115145, 0, 0, 0,
42082    /*GILLT_v8s16*//*Label 2111*/ 115332,
42083    // Label 2105: @113715
42084    GIM_Try, /*On fail goto*//*Label 2113*/ 114107,
42085      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
42086      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
42087      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
42088      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
42089      GIM_Try, /*On fail goto*//*Label 2114*/ 113806, // Rule ID 2406 //
42090        GIM_CheckFeatures, GIFBS_HasFullFP16,
42091        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42092        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
42093        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42094        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42095        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
42096        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42097        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
42098        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
42099        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42100        GIM_CheckIsSafeToFold, /*InsnID*/1,
42101        GIM_CheckIsSafeToFold, /*InsnID*/2,
42102        // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin))  =>  (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42103        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAH,
42104        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
42106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42107        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
42108        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42109        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42110        GIR_EraseFromParent, /*InsnID*/0,
42111        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42112        // GIR_Coverage, 2406,
42113        GIR_Done,
42114      // Label 2114: @113806
42115      GIM_Try, /*On fail goto*//*Label 2115*/ 113879, // Rule ID 5819 //
42116        GIM_CheckFeatures, GIFBS_HasFullFP16,
42117        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42118        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42119        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
42120        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42121        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42122        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42123        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
42124        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
42125        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42126        GIM_CheckIsSafeToFold, /*InsnID*/1,
42127        GIM_CheckIsSafeToFold, /*InsnID*/2,
42128        // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin))  =>  (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42129        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAH,
42130        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
42132        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42133        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
42134        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42135        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42136        GIR_EraseFromParent, /*InsnID*/0,
42137        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42138        // GIR_Coverage, 5819,
42139        GIR_Done,
42140      // Label 2115: @113879
42141      GIM_Try, /*On fail goto*//*Label 2116*/ 113939, // Rule ID 2398 //
42142        GIM_CheckFeatures, GIFBS_HasFullFP16,
42143        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42144        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
42145        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42146        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42147        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
42148        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::HPRRegClassID,
42149        GIM_CheckIsSafeToFold, /*InsnID*/1,
42150        // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)  =>  (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42151        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSH,
42152        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42153        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
42154        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42155        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
42156        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42157        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42158        GIR_EraseFromParent, /*InsnID*/0,
42159        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42160        // GIR_Coverage, 2398,
42161        GIR_Done,
42162      // Label 2116: @113939
42163      GIM_Try, /*On fail goto*//*Label 2117*/ 113999, // Rule ID 5816 //
42164        GIM_CheckFeatures, GIFBS_HasFullFP16,
42165        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42166        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42167        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
42168        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42169        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42170        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::HPRRegClassID,
42171        GIM_CheckIsSafeToFold, /*InsnID*/1,
42172        // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin)  =>  (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42173        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSH,
42174        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42175        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
42176        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42177        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
42178        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42179        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42180        GIR_EraseFromParent, /*InsnID*/0,
42181        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42182        // GIR_Coverage, 5816,
42183        GIR_Done,
42184      // Label 2117: @113999
42185      GIM_Try, /*On fail goto*//*Label 2118*/ 114059, // Rule ID 2411 //
42186        GIM_CheckFeatures, GIFBS_HasFullFP16,
42187        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42188        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
42189        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
42190        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
42191        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42192        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42193        GIM_CheckIsSafeToFold, /*InsnID*/1,
42194        // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin))  =>  (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42195        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSH,
42196        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42197        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
42198        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
42199        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
42200        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42201        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42202        GIR_EraseFromParent, /*InsnID*/0,
42203        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42204        // GIR_Coverage, 2411,
42205        GIR_Done,
42206      // Label 2118: @114059
42207      GIM_Try, /*On fail goto*//*Label 2119*/ 114106, // Rule ID 2392 //
42208        GIM_CheckFeatures, GIFBS_HasFullFP16,
42209        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42210        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
42211        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::HPRRegClassID,
42212        // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)  =>  (VFMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42213        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAH,
42214        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42215        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
42216        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
42217        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
42218        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42219        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42220        GIR_EraseFromParent, /*InsnID*/0,
42221        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42222        // GIR_Coverage, 2392,
42223        GIR_Done,
42224      // Label 2119: @114106
42225      GIM_Reject,
42226    // Label 2113: @114107
42227    GIM_Reject,
42228    // Label 2106: @114108
42229    GIM_Try, /*On fail goto*//*Label 2120*/ 114500,
42230      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
42231      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
42232      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
42233      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
42234      GIM_Try, /*On fail goto*//*Label 2121*/ 114199, // Rule ID 2405 //
42235        GIM_CheckFeatures, GIFBS_HasVFP4,
42236        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42237        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
42238        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42239        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42240        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
42241        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42242        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
42243        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
42244        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42245        GIM_CheckIsSafeToFold, /*InsnID*/1,
42246        GIM_CheckIsSafeToFold, /*InsnID*/2,
42247        // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin))  =>  (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42248        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAS,
42249        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42250        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
42251        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42252        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
42253        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42254        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42255        GIR_EraseFromParent, /*InsnID*/0,
42256        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42257        // GIR_Coverage, 2405,
42258        GIR_Done,
42259      // Label 2121: @114199
42260      GIM_Try, /*On fail goto*//*Label 2122*/ 114272, // Rule ID 5818 //
42261        GIM_CheckFeatures, GIFBS_HasVFP4,
42262        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42263        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42264        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
42265        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42266        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42267        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42268        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
42269        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
42270        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42271        GIM_CheckIsSafeToFold, /*InsnID*/1,
42272        GIM_CheckIsSafeToFold, /*InsnID*/2,
42273        // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin))  =>  (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42274        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAS,
42275        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42276        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
42277        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42278        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
42279        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42280        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42281        GIR_EraseFromParent, /*InsnID*/0,
42282        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42283        // GIR_Coverage, 5818,
42284        GIR_Done,
42285      // Label 2122: @114272
42286      GIM_Try, /*On fail goto*//*Label 2123*/ 114332, // Rule ID 2397 //
42287        GIM_CheckFeatures, GIFBS_HasVFP4,
42288        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42289        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
42290        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42291        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42292        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
42293        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::SPRRegClassID,
42294        GIM_CheckIsSafeToFold, /*InsnID*/1,
42295        // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)  =>  (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42296        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSS,
42297        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42298        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
42299        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42300        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
42301        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42302        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42303        GIR_EraseFromParent, /*InsnID*/0,
42304        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42305        // GIR_Coverage, 2397,
42306        GIR_Done,
42307      // Label 2123: @114332
42308      GIM_Try, /*On fail goto*//*Label 2124*/ 114392, // Rule ID 5815 //
42309        GIM_CheckFeatures, GIFBS_HasVFP4,
42310        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42311        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42312        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
42313        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42314        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42315        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::SPRRegClassID,
42316        GIM_CheckIsSafeToFold, /*InsnID*/1,
42317        // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin)  =>  (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42318        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSS,
42319        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
42321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
42323        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42324        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42325        GIR_EraseFromParent, /*InsnID*/0,
42326        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42327        // GIR_Coverage, 5815,
42328        GIR_Done,
42329      // Label 2124: @114392
42330      GIM_Try, /*On fail goto*//*Label 2125*/ 114452, // Rule ID 2410 //
42331        GIM_CheckFeatures, GIFBS_HasVFP4,
42332        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42333        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
42334        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
42335        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
42336        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42337        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42338        GIM_CheckIsSafeToFold, /*InsnID*/1,
42339        // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin))  =>  (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42340        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSS,
42341        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42342        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
42343        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
42344        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
42345        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42346        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42347        GIR_EraseFromParent, /*InsnID*/0,
42348        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42349        // GIR_Coverage, 2410,
42350        GIR_Done,
42351      // Label 2125: @114452
42352      GIM_Try, /*On fail goto*//*Label 2126*/ 114499, // Rule ID 2391 //
42353        GIM_CheckFeatures, GIFBS_HasVFP4,
42354        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42355        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
42356        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::SPRRegClassID,
42357        // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)  =>  (VFMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42358        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAS,
42359        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42360        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
42361        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
42362        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
42363        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42364        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42365        GIR_EraseFromParent, /*InsnID*/0,
42366        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42367        // GIR_Coverage, 2391,
42368        GIR_Done,
42369      // Label 2126: @114499
42370      GIM_Reject,
42371    // Label 2120: @114500
42372    GIM_Reject,
42373    // Label 2107: @114501
42374    GIM_Try, /*On fail goto*//*Label 2127*/ 114893,
42375      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
42376      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
42377      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
42378      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
42379      GIM_Try, /*On fail goto*//*Label 2128*/ 114592, // Rule ID 2404 //
42380        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
42381        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42382        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
42383        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42384        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42385        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
42386        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42387        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
42388        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
42389        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42390        GIM_CheckIsSafeToFold, /*InsnID*/1,
42391        GIM_CheckIsSafeToFold, /*InsnID*/2,
42392        // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin))  =>  (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42393        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAD,
42394        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
42395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
42396        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
42397        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
42398        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42399        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42400        GIR_EraseFromParent, /*InsnID*/0,
42401        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42402        // GIR_Coverage, 2404,
42403        GIR_Done,
42404      // Label 2128: @114592
42405      GIM_Try, /*On fail goto*//*Label 2129*/ 114665, // Rule ID 5817 //
42406        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
42407        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42408        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42409        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
42410        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42411        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42412        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42413        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
42414        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
42415        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42416        GIM_CheckIsSafeToFold, /*InsnID*/1,
42417        GIM_CheckIsSafeToFold, /*InsnID*/2,
42418        // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin))  =>  (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42419        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAD,
42420        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
42421        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
42422        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
42423        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
42424        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42425        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42426        GIR_EraseFromParent, /*InsnID*/0,
42427        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42428        // GIR_Coverage, 5817,
42429        GIR_Done,
42430      // Label 2129: @114665
42431      GIM_Try, /*On fail goto*//*Label 2130*/ 114725, // Rule ID 2396 //
42432        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
42433        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42434        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
42435        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42436        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42437        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
42438        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
42439        GIM_CheckIsSafeToFold, /*InsnID*/1,
42440        // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)  =>  (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42441        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSD,
42442        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
42443        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ddin
42444        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
42445        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
42446        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42447        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42448        GIR_EraseFromParent, /*InsnID*/0,
42449        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42450        // GIR_Coverage, 2396,
42451        GIR_Done,
42452      // Label 2130: @114725
42453      GIM_Try, /*On fail goto*//*Label 2131*/ 114785, // Rule ID 5814 //
42454        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
42455        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42456        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42457        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
42458        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42459        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42460        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
42461        GIM_CheckIsSafeToFold, /*InsnID*/1,
42462        // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin)  =>  (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42463        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSD,
42464        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
42465        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ddin
42466        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
42467        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
42468        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42469        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42470        GIR_EraseFromParent, /*InsnID*/0,
42471        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42472        // GIR_Coverage, 5814,
42473        GIR_Done,
42474      // Label 2131: @114785
42475      GIM_Try, /*On fail goto*//*Label 2132*/ 114845, // Rule ID 2409 //
42476        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
42477        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42478        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
42479        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
42480        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
42481        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42482        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42483        GIM_CheckIsSafeToFold, /*InsnID*/1,
42484        // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin))  =>  (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42485        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSD,
42486        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
42487        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin
42488        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
42489        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
42490        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42491        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42492        GIR_EraseFromParent, /*InsnID*/0,
42493        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42494        // GIR_Coverage, 2409,
42495        GIR_Done,
42496      // Label 2132: @114845
42497      GIM_Try, /*On fail goto*//*Label 2133*/ 114892, // Rule ID 2390 //
42498        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
42499        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42500        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
42501        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
42502        // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)  =>  (VFMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42503        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAD,
42504        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
42505        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ddin
42506        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
42507        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
42508        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42509        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42510        GIR_EraseFromParent, /*InsnID*/0,
42511        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42512        // GIR_Coverage, 2390,
42513        GIR_Done,
42514      // Label 2133: @114892
42515      GIM_Reject,
42516    // Label 2127: @114893
42517    GIM_Reject,
42518    // Label 2108: @114894
42519    GIM_Try, /*On fail goto*//*Label 2134*/ 115080,
42520      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
42521      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
42522      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
42523      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
42524      GIM_Try, /*On fail goto*//*Label 2135*/ 114972, // Rule ID 2497 //
42525        GIM_CheckFeatures, GIFBS_HasNEON_HasVFP4,
42526        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42527        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
42528        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
42529        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42530        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
42531        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
42532        GIM_CheckIsSafeToFold, /*InsnID*/1,
42533        // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1)  =>  (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
42534        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSfd,
42535        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
42536        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
42537        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
42538        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
42539        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42540        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42541        GIR_EraseFromParent, /*InsnID*/0,
42542        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42543        // GIR_Coverage, 2497,
42544        GIR_Done,
42545      // Label 2135: @114972
42546      GIM_Try, /*On fail goto*//*Label 2136*/ 115032, // Rule ID 5857 //
42547        GIM_CheckFeatures, GIFBS_HasNEON_HasVFP4,
42548        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42549        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42550        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
42551        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
42552        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42553        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
42554        GIM_CheckIsSafeToFold, /*InsnID*/1,
42555        // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm, (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$src1)  =>  (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
42556        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSfd,
42557        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
42558        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
42559        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
42560        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
42561        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42562        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42563        GIR_EraseFromParent, /*InsnID*/0,
42564        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42565        // GIR_Coverage, 5857,
42566        GIR_Done,
42567      // Label 2136: @115032
42568      GIM_Try, /*On fail goto*//*Label 2137*/ 115079, // Rule ID 2495 //
42569        GIM_CheckFeatures, GIFBS_HasNEON_HasVFP4,
42570        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42571        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
42572        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
42573        // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1)  =>  (VFMAfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
42574        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAfd,
42575        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
42576        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
42577        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
42578        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
42579        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42580        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42581        GIR_EraseFromParent, /*InsnID*/0,
42582        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42583        // GIR_Coverage, 2495,
42584        GIR_Done,
42585      // Label 2137: @115079
42586      GIM_Reject,
42587    // Label 2134: @115080
42588    GIM_Reject,
42589    // Label 2109: @115081
42590    GIM_Try, /*On fail goto*//*Label 2138*/ 115144, // Rule ID 2493 //
42591      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
42592      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
42593      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
42594      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
42595      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
42596      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42597      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
42598      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
42599      // (fma:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm, DPR:{ *:[v4f16] }:$src1)  =>  (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
42600      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhd,
42601      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
42602      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
42603      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
42604      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
42605      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42606      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42607      GIR_EraseFromParent, /*InsnID*/0,
42608      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42609      // GIR_Coverage, 2493,
42610      GIR_Done,
42611    // Label 2138: @115144
42612    GIM_Reject,
42613    // Label 2110: @115145
42614    GIM_Try, /*On fail goto*//*Label 2139*/ 115331,
42615      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
42616      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
42617      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
42618      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
42619      GIM_Try, /*On fail goto*//*Label 2140*/ 115223, // Rule ID 2498 //
42620        GIM_CheckFeatures, GIFBS_HasNEON_HasVFP4,
42621        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42622        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
42623        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
42624        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
42625        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
42626        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
42627        GIM_CheckIsSafeToFold, /*InsnID*/1,
42628        // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1)  =>  (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
42629        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSfq,
42630        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
42631        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
42632        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
42633        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
42634        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42635        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42636        GIR_EraseFromParent, /*InsnID*/0,
42637        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42638        // GIR_Coverage, 2498,
42639        GIR_Done,
42640      // Label 2140: @115223
42641      GIM_Try, /*On fail goto*//*Label 2141*/ 115283, // Rule ID 5858 //
42642        GIM_CheckFeatures, GIFBS_HasNEON_HasVFP4,
42643        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
42644        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42645        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
42646        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
42647        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
42648        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
42649        GIM_CheckIsSafeToFold, /*InsnID*/1,
42650        // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm, (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$src1)  =>  (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
42651        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSfq,
42652        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
42653        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
42654        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
42655        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
42656        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42657        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42658        GIR_EraseFromParent, /*InsnID*/0,
42659        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42660        // GIR_Coverage, 5858,
42661        GIR_Done,
42662      // Label 2141: @115283
42663      GIM_Try, /*On fail goto*//*Label 2142*/ 115330, // Rule ID 2496 //
42664        GIM_CheckFeatures, GIFBS_HasNEON_HasVFP4,
42665        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
42666        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
42667        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
42668        // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1)  =>  (VFMAfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
42669        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAfq,
42670        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
42671        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
42672        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
42673        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
42674        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42675        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42676        GIR_EraseFromParent, /*InsnID*/0,
42677        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42678        // GIR_Coverage, 2496,
42679        GIR_Done,
42680      // Label 2142: @115330
42681      GIM_Reject,
42682    // Label 2139: @115331
42683    GIM_Reject,
42684    // Label 2111: @115332
42685    GIM_Try, /*On fail goto*//*Label 2143*/ 115395, // Rule ID 2494 //
42686      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
42687      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
42688      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
42689      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
42690      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
42691      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
42692      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
42693      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
42694      // (fma:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm, QPR:{ *:[v8f16] }:$src1)  =>  (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
42695      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhq,
42696      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
42697      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
42698      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
42699      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
42700      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42701      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42702      GIR_EraseFromParent, /*InsnID*/0,
42703      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42704      // GIR_Coverage, 2494,
42705      GIR_Done,
42706    // Label 2143: @115395
42707    GIM_Reject,
42708    // Label 2112: @115396
42709    GIM_Reject,
42710    // Label 36: @115397
42711    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 2147*/ 115562,
42712    /*GILLT_s16*//*Label 2144*/ 115406,
42713    /*GILLT_s32*//*Label 2145*/ 115458,
42714    /*GILLT_s64*//*Label 2146*/ 115510,
42715    // Label 2144: @115406
42716    GIM_Try, /*On fail goto*//*Label 2148*/ 115457, // Rule ID 636 //
42717      GIM_CheckFeatures, GIFBS_HasFullFP16,
42718      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
42719      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
42720      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
42721      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42722      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
42723      // (fdiv:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)  =>  (VDIVH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42724      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VDIVH,
42725      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42726      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
42727      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
42728      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42729      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42730      GIR_EraseFromParent, /*InsnID*/0,
42731      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42732      // GIR_Coverage, 636,
42733      GIR_Done,
42734    // Label 2148: @115457
42735    GIM_Reject,
42736    // Label 2145: @115458
42737    GIM_Try, /*On fail goto*//*Label 2149*/ 115509, // Rule ID 635 //
42738      GIM_CheckFeatures, GIFBS_HasVFP2,
42739      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
42740      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
42741      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
42742      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42743      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
42744      // (fdiv:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)  =>  (VDIVS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42745      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VDIVS,
42746      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42747      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
42748      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
42749      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42750      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42751      GIR_EraseFromParent, /*InsnID*/0,
42752      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42753      // GIR_Coverage, 635,
42754      GIR_Done,
42755    // Label 2149: @115509
42756    GIM_Reject,
42757    // Label 2146: @115510
42758    GIM_Try, /*On fail goto*//*Label 2150*/ 115561, // Rule ID 634 //
42759      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
42760      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
42761      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
42762      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
42763      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42764      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
42765      // (fdiv:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)  =>  (VDIVD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42766      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VDIVD,
42767      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
42768      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
42769      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
42770      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42771      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42772      GIR_EraseFromParent, /*InsnID*/0,
42773      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42774      // GIR_Coverage, 634,
42775      GIR_Done,
42776    // Label 2150: @115561
42777    GIM_Reject,
42778    // Label 2147: @115562
42779    GIM_Reject,
42780    // Label 37: @115563
42781    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2158*/ 116880,
42782    /*GILLT_s16*//*Label 2151*/ 115582,
42783    /*GILLT_s32*//*Label 2152*/ 115911,
42784    /*GILLT_s64*//*Label 2153*/ 116391, 0,
42785    /*GILLT_v2s32*//*Label 2154*/ 116720, 0, 0,
42786    /*GILLT_v4s16*//*Label 2155*/ 116760,
42787    /*GILLT_v4s32*//*Label 2156*/ 116800, 0, 0, 0,
42788    /*GILLT_v8s16*//*Label 2157*/ 116840,
42789    // Label 2151: @115582
42790    GIM_Try, /*On fail goto*//*Label 2159*/ 115910,
42791      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
42792      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
42793      GIM_Try, /*On fail goto*//*Label 2160*/ 115673, // Rule ID 2414 //
42794        GIM_CheckFeatures, GIFBS_HasFullFP16,
42795        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42796        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
42797        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42798        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
42799        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
42800        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
42801        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
42802        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
42803        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42804        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::HPRRegClassID,
42805        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::HPRRegClassID,
42806        GIM_CheckIsSafeToFold, /*InsnID*/1,
42807        GIM_CheckIsSafeToFold, /*InsnID*/2,
42808        // (fneg:{ *:[f16] } (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin))  =>  (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42809        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSH,
42810        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42811        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
42812        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
42813        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
42814        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42815        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42816        GIR_EraseFromParent, /*InsnID*/0,
42817        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42818        // GIR_Coverage, 2414,
42819        GIR_Done,
42820      // Label 2160: @115673
42821      GIM_Try, /*On fail goto*//*Label 2161*/ 115754, // Rule ID 5822 //
42822        GIM_CheckFeatures, GIFBS_HasFullFP16,
42823        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42824        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
42825        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42826        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
42827        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
42828        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42829        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
42830        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
42831        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
42832        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42833        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::HPRRegClassID,
42834        GIM_CheckIsSafeToFold, /*InsnID*/1,
42835        GIM_CheckIsSafeToFold, /*InsnID*/2,
42836        // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin))  =>  (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42837        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSH,
42838        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42839        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
42840        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
42841        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
42842        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42843        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42844        GIR_EraseFromParent, /*InsnID*/0,
42845        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42846        // GIR_Coverage, 5822,
42847        GIR_Done,
42848      // Label 2161: @115754
42849      GIM_Try, /*On fail goto*//*Label 2162*/ 115822, // Rule ID 2403 //
42850        GIM_CheckFeatures, GIFBS_HasFullFP16,
42851        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42852        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
42853        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42854        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
42855        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
42856        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42857        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::HPRRegClassID,
42858        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::HPRRegClassID,
42859        GIM_CheckIsSafeToFold, /*InsnID*/1,
42860        // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin))  =>  (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42861        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAH,
42862        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42863        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
42864        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42865        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
42866        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42867        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42868        GIR_EraseFromParent, /*InsnID*/0,
42869        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42870        // GIR_Coverage, 2403,
42871        GIR_Done,
42872      // Label 2162: @115822
42873      GIM_Try, /*On fail goto*//*Label 2163*/ 115878, // Rule ID 642 //
42874        GIM_CheckFeatures, GIFBS_HasFullFP16,
42875        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42876        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
42877        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42878        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
42879        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42880        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::HPRRegClassID,
42881        GIM_CheckIsSafeToFold, /*InsnID*/1,
42882        // (fneg:{ *:[f16] } (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm))  =>  (VNMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42883        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULH,
42884        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42885        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42886        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
42887        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42888        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42889        GIR_EraseFromParent, /*InsnID*/0,
42890        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42891        // GIR_Coverage, 642,
42892        GIR_Done,
42893      // Label 2163: @115878
42894      GIM_Try, /*On fail goto*//*Label 2164*/ 115909, // Rule ID 680 //
42895        GIM_CheckFeatures, GIFBS_HasFullFP16,
42896        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42897        // (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VNEGH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
42898        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGH,
42899        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42900        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
42901        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42902        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42903        GIR_EraseFromParent, /*InsnID*/0,
42904        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42905        // GIR_Coverage, 680,
42906        GIR_Done,
42907      // Label 2164: @115909
42908      GIM_Reject,
42909    // Label 2159: @115910
42910    GIM_Reject,
42911    // Label 2152: @115911
42912    GIM_Try, /*On fail goto*//*Label 2165*/ 116390,
42913      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
42914      GIM_Try, /*On fail goto*//*Label 2166*/ 116002, // Rule ID 2413 //
42915        GIM_CheckFeatures, GIFBS_HasVFP4,
42916        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
42917        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42918        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
42919        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42920        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
42921        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
42922        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
42923        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
42924        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
42925        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42926        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
42927        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::SPRRegClassID,
42928        GIM_CheckIsSafeToFold, /*InsnID*/1,
42929        GIM_CheckIsSafeToFold, /*InsnID*/2,
42930        // (fneg:{ *:[f32] } (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin))  =>  (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42931        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSS,
42932        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42933        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
42934        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
42935        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
42936        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42937        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42938        GIR_EraseFromParent, /*InsnID*/0,
42939        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42940        // GIR_Coverage, 2413,
42941        GIR_Done,
42942      // Label 2166: @116002
42943      GIM_Try, /*On fail goto*//*Label 2167*/ 116087, // Rule ID 5821 //
42944        GIM_CheckFeatures, GIFBS_HasVFP4,
42945        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
42946        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42947        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
42948        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42949        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
42950        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
42951        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42952        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
42953        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
42954        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
42955        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42956        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::SPRRegClassID,
42957        GIM_CheckIsSafeToFold, /*InsnID*/1,
42958        GIM_CheckIsSafeToFold, /*InsnID*/2,
42959        // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin))  =>  (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42960        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSS,
42961        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42962        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
42963        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
42964        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
42965        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42966        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42967        GIR_EraseFromParent, /*InsnID*/0,
42968        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42969        // GIR_Coverage, 5821,
42970        GIR_Done,
42971      // Label 2167: @116087
42972      GIM_Try, /*On fail goto*//*Label 2168*/ 116159, // Rule ID 2402 //
42973        GIM_CheckFeatures, GIFBS_HasVFP4,
42974        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
42975        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42976        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
42977        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42978        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
42979        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
42980        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42981        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
42982        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::SPRRegClassID,
42983        GIM_CheckIsSafeToFold, /*InsnID*/1,
42984        // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin))  =>  (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42985        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAS,
42986        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42987        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
42988        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42989        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
42990        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42991        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42992        GIR_EraseFromParent, /*InsnID*/0,
42993        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42994        // GIR_Coverage, 2402,
42995        GIR_Done,
42996      // Label 2168: @116159
42997      GIM_Try, /*On fail goto*//*Label 2169*/ 116219, // Rule ID 641 //
42998        GIM_CheckFeatures, GIFBS_HasVFP2,
42999        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
43000        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43001        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
43002        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43003        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43004        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
43005        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
43006        GIM_CheckIsSafeToFold, /*InsnID*/1,
43007        // (fneg:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm))  =>  (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43008        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULS,
43009        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
43010        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
43011        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43012        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43013        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43014        GIR_EraseFromParent, /*InsnID*/0,
43015        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43016        // GIR_Coverage, 641,
43017        GIR_Done,
43018      // Label 2169: @116219
43019      GIM_Try, /*On fail goto*//*Label 2170*/ 116254, // Rule ID 679 //
43020        GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
43021        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
43022        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
43023        // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VNEGS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
43024        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGS,
43025        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
43026        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
43027        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43028        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43029        GIR_EraseFromParent, /*InsnID*/0,
43030        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43031        // GIR_Coverage, 679,
43032        GIR_Done,
43033      // Label 2170: @116254
43034      GIM_Try, /*On fail goto*//*Label 2171*/ 116389, // Rule ID 2720 //
43035        GIM_CheckFeatures, GIFBS_HasNEON_UseNEONForFP,
43036        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
43037        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
43038        // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a)  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VNEGfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
43039        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
43040        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
43041        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
43042        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
43043        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
43044        GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
43045        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
43046        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
43047        GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
43048        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
43049        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
43050        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
43051        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
43052        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
43053        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
43054        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
43055        GIR_AddImm, /*InsnID*/3, /*Imm*/17,
43056        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
43057        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
43058        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
43059        GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VNEGfd,
43060        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
43061        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
43062        GIR_AddImm, /*InsnID*/2, /*Imm*/14,
43063        GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43064        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43065        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
43066        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43067        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
43068        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43069        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43070        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43071        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
43072        GIR_EraseFromParent, /*InsnID*/0,
43073        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
43074        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
43075        // GIR_Coverage, 2720,
43076        GIR_Done,
43077      // Label 2171: @116389
43078      GIM_Reject,
43079    // Label 2165: @116390
43080    GIM_Reject,
43081    // Label 2153: @116391
43082    GIM_Try, /*On fail goto*//*Label 2172*/ 116719,
43083      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
43084      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43085      GIM_Try, /*On fail goto*//*Label 2173*/ 116482, // Rule ID 2412 //
43086        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
43087        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43088        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
43089        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43090        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43091        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43092        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
43093        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
43094        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
43095        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43096        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
43097        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
43098        GIM_CheckIsSafeToFold, /*InsnID*/1,
43099        GIM_CheckIsSafeToFold, /*InsnID*/2,
43100        // (fneg:{ *:[f64] } (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin))  =>  (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43101        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSD,
43102        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
43103        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
43104        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
43105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
43106        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43107        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43108        GIR_EraseFromParent, /*InsnID*/0,
43109        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43110        // GIR_Coverage, 2412,
43111        GIR_Done,
43112      // Label 2173: @116482
43113      GIM_Try, /*On fail goto*//*Label 2174*/ 116563, // Rule ID 5820 //
43114        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
43115        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43116        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
43117        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43118        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43119        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43120        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43121        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
43122        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
43123        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
43124        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43125        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
43126        GIM_CheckIsSafeToFold, /*InsnID*/1,
43127        GIM_CheckIsSafeToFold, /*InsnID*/2,
43128        // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin))  =>  (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43129        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSD,
43130        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
43131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
43132        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
43133        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm
43134        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43135        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43136        GIR_EraseFromParent, /*InsnID*/0,
43137        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43138        // GIR_Coverage, 5820,
43139        GIR_Done,
43140      // Label 2174: @116563
43141      GIM_Try, /*On fail goto*//*Label 2175*/ 116631, // Rule ID 2401 //
43142        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
43143        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43144        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
43145        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43146        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43147        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43148        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43149        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
43150        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
43151        GIM_CheckIsSafeToFold, /*InsnID*/1,
43152        // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin))  =>  (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43153        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAD,
43154        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
43155        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
43156        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
43157        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
43158        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43159        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43160        GIR_EraseFromParent, /*InsnID*/0,
43161        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43162        // GIR_Coverage, 2401,
43163        GIR_Done,
43164      // Label 2175: @116631
43165      GIM_Try, /*On fail goto*//*Label 2176*/ 116687, // Rule ID 640 //
43166        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
43167        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43168        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
43169        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43170        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43171        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43172        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
43173        GIM_CheckIsSafeToFold, /*InsnID*/1,
43174        // (fneg:{ *:[f64] } (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm))  =>  (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43175        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULD,
43176        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
43177        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
43178        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
43179        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43180        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43181        GIR_EraseFromParent, /*InsnID*/0,
43182        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43183        // GIR_Coverage, 640,
43184        GIR_Done,
43185      // Label 2176: @116687
43186      GIM_Try, /*On fail goto*//*Label 2177*/ 116718, // Rule ID 678 //
43187        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
43188        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43189        // (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VNEGD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
43190        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGD,
43191        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
43192        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
43193        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43194        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43195        GIR_EraseFromParent, /*InsnID*/0,
43196        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43197        // GIR_Coverage, 678,
43198        GIR_Done,
43199      // Label 2177: @116718
43200      GIM_Reject,
43201    // Label 2172: @116719
43202    GIM_Reject,
43203    // Label 2154: @116720
43204    GIM_Try, /*On fail goto*//*Label 2178*/ 116759, // Rule ID 1548 //
43205      GIM_CheckFeatures, GIFBS_HasNEON,
43206      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
43207      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43208      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43209      // (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)  =>  (VNEGfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
43210      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGfd,
43211      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43212      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43213      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43214      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43215      GIR_EraseFromParent, /*InsnID*/0,
43216      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43217      // GIR_Coverage, 1548,
43218      GIR_Done,
43219    // Label 2178: @116759
43220    GIM_Reject,
43221    // Label 2155: @116760
43222    GIM_Try, /*On fail goto*//*Label 2179*/ 116799, // Rule ID 1550 //
43223      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
43224      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
43225      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43226      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43227      // (fneg:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)  =>  (VNEGhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
43228      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGhd,
43229      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43230      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43231      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43232      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43233      GIR_EraseFromParent, /*InsnID*/0,
43234      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43235      // GIR_Coverage, 1550,
43236      GIR_Done,
43237    // Label 2179: @116799
43238    GIM_Reject,
43239    // Label 2156: @116800
43240    GIM_Try, /*On fail goto*//*Label 2180*/ 116839, // Rule ID 1549 //
43241      GIM_CheckFeatures, GIFBS_HasNEON,
43242      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
43243      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
43244      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
43245      // (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)  =>  (VNEGf32q:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
43246      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGf32q,
43247      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43248      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43249      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43250      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43251      GIR_EraseFromParent, /*InsnID*/0,
43252      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43253      // GIR_Coverage, 1549,
43254      GIR_Done,
43255    // Label 2180: @116839
43256    GIM_Reject,
43257    // Label 2157: @116840
43258    GIM_Try, /*On fail goto*//*Label 2181*/ 116879, // Rule ID 1551 //
43259      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
43260      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
43261      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
43262      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
43263      // (fneg:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)  =>  (VNEGhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
43264      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGhq,
43265      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43266      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43267      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43268      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43269      GIR_EraseFromParent, /*InsnID*/0,
43270      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43271      // GIR_Coverage, 1551,
43272      GIR_Done,
43273    // Label 2181: @116879
43274    GIM_Reject,
43275    // Label 2158: @116880
43276    GIM_Reject,
43277    // Label 38: @116881
43278    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 2185*/ 117084,
43279    /*GILLT_s32*//*Label 2182*/ 116895,
43280    /*GILLT_s64*//*Label 2183*/ 116951, 0, 0, 0, 0, 0,
43281    /*GILLT_v4s32*//*Label 2184*/ 117046,
43282    // Label 2182: @116895
43283    GIM_Try, /*On fail goto*//*Label 2186*/ 116950, // Rule ID 2301 //
43284      GIM_CheckFeatures, GIFBS_HasFP16,
43285      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
43286      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
43287      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
43288      // (fpextend:{ *:[f32] } HPR:{ *:[f16] }:$Sm)  =>  (VCVTBHS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] }))
43289      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43290      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
43291      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43292      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
43293      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43294      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTBHS,
43295      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
43296      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43297      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43298      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43299      GIR_EraseFromParent, /*InsnID*/0,
43300      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43301      // GIR_Coverage, 2301,
43302      GIR_Done,
43303    // Label 2186: @116950
43304    GIM_Reject,
43305    // Label 2183: @116951
43306    GIM_Try, /*On fail goto*//*Label 2187*/ 116990, // Rule ID 676 //
43307      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
43308      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43309      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43310      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
43311      // (fpextend:{ *:[f64] } SPR:{ *:[f32] }:$Sm)  =>  (VCVTDS:{ *:[f64] } SPR:{ *:[f32] }:$Sm)
43312      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTDS,
43313      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
43314      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
43315      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43316      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43317      GIR_EraseFromParent, /*InsnID*/0,
43318      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43319      // GIR_Coverage, 676,
43320      GIR_Done,
43321    // Label 2187: @116990
43322    GIM_Try, /*On fail goto*//*Label 2188*/ 117045, // Rule ID 2311 //
43323      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
43324      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
43325      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43326      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
43327      // (fpextend:{ *:[f64] } HPR:{ *:[f16] }:$Sm)  =>  (VCVTBHD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] }))
43328      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43329      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
43330      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43331      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
43332      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43333      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTBHD,
43334      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
43335      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43336      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43337      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43338      GIR_EraseFromParent, /*InsnID*/0,
43339      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43340      // GIR_Coverage, 2311,
43341      GIR_Done,
43342    // Label 2188: @117045
43343    GIM_Reject,
43344    // Label 2184: @117046
43345    GIM_Try, /*On fail goto*//*Label 2189*/ 117083, // Rule ID 2678 //
43346      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
43347      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
43348      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43349      // (fpextend:{ *:[v4f32] } DPR:{ *:[v4f16] }:$src)  =>  (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4f16] }:$src)
43350      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2f,
43351      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43352      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
43353      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43354      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43355      GIR_EraseFromParent, /*InsnID*/0,
43356      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43357      // GIR_Coverage, 2678,
43358      GIR_Done,
43359    // Label 2189: @117083
43360    GIM_Reject,
43361    // Label 2185: @117084
43362    GIM_Reject,
43363    // Label 39: @117085
43364    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 8, /*)*//*default:*//*Label 2193*/ 117324,
43365    /*GILLT_s16*//*Label 2190*/ 117099,
43366    /*GILLT_s32*//*Label 2191*/ 117246, 0, 0, 0, 0, 0,
43367    /*GILLT_v4s16*//*Label 2192*/ 117286,
43368    // Label 2190: @117099
43369    GIM_Try, /*On fail goto*//*Label 2194*/ 117172, // Rule ID 2303 //
43370      GIM_CheckFeatures, GIFBS_HasFP16,
43371      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43372      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
43373      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
43374      // (fpround:{ *:[f16] } SPR:{ *:[f32] }:$Sm)  =>  (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBSH:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), SPR:{ *:[f32] }:$Sm), HPR:{ *:[i32] })
43375      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43376      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43377      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
43378      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
43379      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43380      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTBSH,
43381      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43382      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
43383      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
43384      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
43385      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43386      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43387      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43388      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43389      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43390      GIR_EraseFromParent, /*InsnID*/0,
43391      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::HPRRegClassID,
43392      // GIR_Coverage, 2303,
43393      GIR_Done,
43394    // Label 2194: @117172
43395    GIM_Try, /*On fail goto*//*Label 2195*/ 117245, // Rule ID 2313 //
43396      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
43397      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
43398      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
43399      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43400      // (fpround:{ *:[f16] } DPR:{ *:[f64] }:$Dm)  =>  (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBDH:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), DPR:{ *:[f64] }:$Dm), HPR:{ *:[i32] })
43401      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43402      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43403      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
43404      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
43405      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43406      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTBDH,
43407      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43408      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
43409      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dm
43410      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
43411      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43412      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43413      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43414      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43415      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43416      GIR_EraseFromParent, /*InsnID*/0,
43417      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::HPRRegClassID,
43418      // GIR_Coverage, 2313,
43419      GIR_Done,
43420    // Label 2195: @117245
43421    GIM_Reject,
43422    // Label 2191: @117246
43423    GIM_Try, /*On fail goto*//*Label 2196*/ 117285, // Rule ID 677 //
43424      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
43425      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
43426      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
43427      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43428      // (fpround:{ *:[f32] } DPR:{ *:[f64] }:$Dm)  =>  (VCVTSD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
43429      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTSD,
43430      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
43431      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
43432      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43433      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43434      GIR_EraseFromParent, /*InsnID*/0,
43435      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43436      // GIR_Coverage, 677,
43437      GIR_Done,
43438    // Label 2196: @117285
43439    GIM_Reject,
43440    // Label 2192: @117286
43441    GIM_Try, /*On fail goto*//*Label 2197*/ 117323, // Rule ID 2677 //
43442      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
43443      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43444      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
43445      // (fpround:{ *:[v4f16] } QPR:{ *:[v4f32] }:$src)  =>  (VCVTf2h:{ *:[v4f16] } QPR:{ *:[v4f32] }:$src)
43446      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2h,
43447      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43448      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
43449      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43450      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43451      GIR_EraseFromParent, /*InsnID*/0,
43452      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43453      // GIR_Coverage, 2677,
43454      GIR_Done,
43455    // Label 2197: @117323
43456    GIM_Reject,
43457    // Label 2193: @117324
43458    GIM_Reject,
43459    // Label 40: @117325
43460    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 13, /*)*//*default:*//*Label 2205*/ 118563,
43461    /*GILLT_s32*//*Label 2198*/ 117343, 0, 0,
43462    /*GILLT_v2s32*//*Label 2199*/ 118189, 0,
43463    /*GILLT_v4s1*//*Label 2200*/ 118229,
43464    /*GILLT_v4s16*//*Label 2201*/ 118280,
43465    /*GILLT_v4s32*//*Label 2202*/ 118320, 0,
43466    /*GILLT_v8s1*//*Label 2203*/ 118416, 0,
43467    /*GILLT_v8s16*//*Label 2204*/ 118467,
43468    // Label 2198: @117343
43469    GIM_Try, /*On fail goto*//*Label 2206*/ 117406, // Rule ID 2321 //
43470      GIM_CheckFeatures, GIFBS_HasFullFP16,
43471      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
43472      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
43473      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43474      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL,
43475      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43476      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
43477      GIM_CheckIsSafeToFold, /*InsnID*/1,
43478      // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
43479      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43480      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPSH,
43481      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43482      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
43483      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43484      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43485      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43486      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43487      GIR_EraseFromParent, /*InsnID*/0,
43488      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
43489      // GIR_Coverage, 2321,
43490      GIR_Done,
43491    // Label 2206: @117406
43492    GIM_Try, /*On fail goto*//*Label 2207*/ 117469, // Rule ID 2323 //
43493      GIM_CheckFeatures, GIFBS_HasFPARMv8,
43494      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43495      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
43496      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43497      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL,
43498      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43499      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
43500      GIM_CheckIsSafeToFold, /*InsnID*/1,
43501      // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
43502      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43503      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPSS,
43504      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43505      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
43506      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43507      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43508      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43509      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43510      GIR_EraseFromParent, /*InsnID*/0,
43511      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
43512      // GIR_Coverage, 2323,
43513      GIR_Done,
43514    // Label 2207: @117469
43515    GIM_Try, /*On fail goto*//*Label 2208*/ 117532, // Rule ID 2325 //
43516      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
43517      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
43518      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
43519      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43520      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL,
43521      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43522      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43523      GIM_CheckIsSafeToFold, /*InsnID*/1,
43524      // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
43525      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43526      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPSD,
43527      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43528      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
43529      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43530      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43531      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43532      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43533      GIR_EraseFromParent, /*InsnID*/0,
43534      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
43535      // GIR_Coverage, 2325,
43536      GIR_Done,
43537    // Label 2208: @117532
43538    GIM_Try, /*On fail goto*//*Label 2209*/ 117595, // Rule ID 2327 //
43539      GIM_CheckFeatures, GIFBS_HasFullFP16,
43540      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
43541      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
43542      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43543      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR,
43544      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43545      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
43546      GIM_CheckIsSafeToFold, /*InsnID*/1,
43547      // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
43548      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43549      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMSH,
43550      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43551      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
43552      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43553      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43554      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43555      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43556      GIR_EraseFromParent, /*InsnID*/0,
43557      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
43558      // GIR_Coverage, 2327,
43559      GIR_Done,
43560    // Label 2209: @117595
43561    GIM_Try, /*On fail goto*//*Label 2210*/ 117658, // Rule ID 2329 //
43562      GIM_CheckFeatures, GIFBS_HasFPARMv8,
43563      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43564      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
43565      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43566      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR,
43567      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43568      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
43569      GIM_CheckIsSafeToFold, /*InsnID*/1,
43570      // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
43571      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43572      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMSS,
43573      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43574      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
43575      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43576      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43577      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43578      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43579      GIR_EraseFromParent, /*InsnID*/0,
43580      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
43581      // GIR_Coverage, 2329,
43582      GIR_Done,
43583    // Label 2210: @117658
43584    GIM_Try, /*On fail goto*//*Label 2211*/ 117721, // Rule ID 2331 //
43585      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
43586      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
43587      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
43588      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43589      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR,
43590      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43591      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43592      GIM_CheckIsSafeToFold, /*InsnID*/1,
43593      // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
43594      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43595      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMSD,
43596      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43597      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
43598      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43599      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43600      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43601      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43602      GIR_EraseFromParent, /*InsnID*/0,
43603      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
43604      // GIR_Coverage, 2331,
43605      GIR_Done,
43606    // Label 2211: @117721
43607    GIM_Try, /*On fail goto*//*Label 2212*/ 117784, // Rule ID 2315 //
43608      GIM_CheckFeatures, GIFBS_HasFullFP16,
43609      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
43610      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
43611      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43612      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND,
43613      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43614      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
43615      GIM_CheckIsSafeToFold, /*InsnID*/1,
43616      // (fp_to_sint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
43617      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43618      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTASH,
43619      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43620      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
43621      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43622      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43623      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43624      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43625      GIR_EraseFromParent, /*InsnID*/0,
43626      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
43627      // GIR_Coverage, 2315,
43628      GIR_Done,
43629    // Label 2212: @117784
43630    GIM_Try, /*On fail goto*//*Label 2213*/ 117847, // Rule ID 2317 //
43631      GIM_CheckFeatures, GIFBS_HasFPARMv8,
43632      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43633      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
43634      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43635      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND,
43636      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43637      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
43638      GIM_CheckIsSafeToFold, /*InsnID*/1,
43639      // (fp_to_sint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
43640      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43641      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTASS,
43642      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43643      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
43644      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43645      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43646      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43647      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43648      GIR_EraseFromParent, /*InsnID*/0,
43649      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
43650      // GIR_Coverage, 2317,
43651      GIR_Done,
43652    // Label 2213: @117847
43653    GIM_Try, /*On fail goto*//*Label 2214*/ 117910, // Rule ID 2319 //
43654      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
43655      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
43656      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
43657      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43658      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND,
43659      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43660      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43661      GIM_CheckIsSafeToFold, /*InsnID*/1,
43662      // (fp_to_sint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
43663      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43664      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTASD,
43665      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43666      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
43667      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43668      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43669      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43670      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43671      GIR_EraseFromParent, /*InsnID*/0,
43672      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
43673      // GIR_Coverage, 2319,
43674      GIR_Done,
43675    // Label 2214: @117910
43676    GIM_Try, /*On fail goto*//*Label 2215*/ 117967, // Rule ID 2352 //
43677      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
43678      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
43679      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
43680      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43681      // (fp_to_sint:{ *:[i32] } DPR:{ *:[f64] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
43682      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43683      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOSIZD,
43684      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43685      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
43686      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
43687      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43688      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43689      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43690      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43691      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43692      GIR_EraseFromParent, /*InsnID*/0,
43693      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
43694      // GIR_Coverage, 2352,
43695      GIR_Done,
43696    // Label 2215: @117967
43697    GIM_Try, /*On fail goto*//*Label 2216*/ 118024, // Rule ID 2356 //
43698      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
43699      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43700      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
43701      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
43702      // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
43703      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43704      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOSIZS,
43705      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43706      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
43707      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
43708      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43709      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43710      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43711      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43712      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43713      GIR_EraseFromParent, /*InsnID*/0,
43714      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
43715      // GIR_Coverage, 2356,
43716      GIR_Done,
43717    // Label 2216: @118024
43718    GIM_Try, /*On fail goto*//*Label 2217*/ 118081, // Rule ID 2360 //
43719      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
43720      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
43721      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
43722      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
43723      // (fp_to_sint:{ *:[i32] } HPR:{ *:[f16] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
43724      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43725      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOSIZH,
43726      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43727      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
43728      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
43729      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43730      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43731      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43732      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43733      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43734      GIR_EraseFromParent, /*InsnID*/0,
43735      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
43736      // GIR_Coverage, 2360,
43737      GIR_Done,
43738    // Label 2217: @118081
43739    GIM_Try, /*On fail goto*//*Label 2218*/ 118188, // Rule ID 2725 //
43740      GIM_CheckFeatures, GIFBS_HasNEON_UseNEONForFP,
43741      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43742      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43743      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
43744      // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a)  =>  (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2sd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
43745      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
43746      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
43747      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
43748      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
43749      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
43750      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
43751      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG,
43752      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
43753      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
43754      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a
43755      GIR_AddImm, /*InsnID*/2, /*Imm*/17,
43756      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, ARM::DPR_VFP2RegClassID,
43757      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, ARM::DPR_VFP2RegClassID,
43758      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, ARM::SPRRegClassID,
43759      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTf2sd,
43760      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43761      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
43762      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
43763      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43764      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43765      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43766      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43767      GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
43768      GIR_EraseFromParent, /*InsnID*/0,
43769      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
43770      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
43771      // GIR_Coverage, 2725,
43772      GIR_Done,
43773    // Label 2218: @118188
43774    GIM_Reject,
43775    // Label 2199: @118189
43776    GIM_Try, /*On fail goto*//*Label 2219*/ 118228, // Rule ID 1622 //
43777      GIM_CheckFeatures, GIFBS_HasNEON,
43778      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
43779      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43780      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43781      // (fp_to_sint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTf2sd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
43782      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2sd,
43783      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43784      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43785      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43786      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43787      GIR_EraseFromParent, /*InsnID*/0,
43788      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43789      // GIR_Coverage, 1622,
43790      GIR_Done,
43791    // Label 2219: @118228
43792    GIM_Reject,
43793    // Label 2200: @118229
43794    GIM_Try, /*On fail goto*//*Label 2220*/ 118279, // Rule ID 5205 //
43795      GIM_CheckFeatures, GIFBS_HasMVEFloat,
43796      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
43797      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
43798      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
43799      // (fp_to_sint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1)  =>  (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
43800      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPf32r,
43801      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
43802      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1
43803      GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
43804      GIR_AddImm, /*InsnID*/0, /*Imm*/1,
43805      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
43806      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43807      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43808      GIR_EraseFromParent, /*InsnID*/0,
43809      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43810      // GIR_Coverage, 5205,
43811      GIR_Done,
43812    // Label 2220: @118279
43813    GIM_Reject,
43814    // Label 2201: @118280
43815    GIM_Try, /*On fail goto*//*Label 2221*/ 118319, // Rule ID 1630 //
43816      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
43817      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
43818      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43819      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43820      // (fp_to_sint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTh2sd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
43821      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2sd,
43822      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43823      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43824      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43825      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43826      GIR_EraseFromParent, /*InsnID*/0,
43827      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43828      // GIR_Coverage, 1630,
43829      GIR_Done,
43830    // Label 2221: @118319
43831    GIM_Reject,
43832    // Label 2202: @118320
43833    GIM_Try, /*On fail goto*//*Label 2222*/ 118415,
43834      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
43835      GIM_Try, /*On fail goto*//*Label 2223*/ 118361, // Rule ID 1626 //
43836        GIM_CheckFeatures, GIFBS_HasNEON,
43837        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
43838        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
43839        // (fp_to_sint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTf2sq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
43840        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2sq,
43841        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43842        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43843        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43844        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43845        GIR_EraseFromParent, /*InsnID*/0,
43846        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43847        // GIR_Coverage, 1626,
43848        GIR_Done,
43849      // Label 2223: @118361
43850      GIM_Try, /*On fail goto*//*Label 2224*/ 118414, // Rule ID 4192 //
43851        GIM_CheckFeatures, GIFBS_HasMVEFloat,
43852        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
43853        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
43854        // (fp_to_sint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VCVTs32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
43855        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43856        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
43857        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
43858        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs32f32z,
43859        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
43860        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
43861        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
43862        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43863        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43864        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43865        GIR_EraseFromParent, /*InsnID*/0,
43866        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43867        // GIR_Coverage, 4192,
43868        GIR_Done,
43869      // Label 2224: @118414
43870      GIM_Reject,
43871    // Label 2222: @118415
43872    GIM_Reject,
43873    // Label 2203: @118416
43874    GIM_Try, /*On fail goto*//*Label 2225*/ 118466, // Rule ID 5206 //
43875      GIM_CheckFeatures, GIFBS_HasMVEFloat,
43876      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
43877      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
43878      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
43879      // (fp_to_sint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1)  =>  (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
43880      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPf16r,
43881      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
43882      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1
43883      GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
43884      GIR_AddImm, /*InsnID*/0, /*Imm*/1,
43885      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
43886      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43887      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43888      GIR_EraseFromParent, /*InsnID*/0,
43889      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43890      // GIR_Coverage, 5206,
43891      GIR_Done,
43892    // Label 2225: @118466
43893    GIM_Reject,
43894    // Label 2204: @118467
43895    GIM_Try, /*On fail goto*//*Label 2226*/ 118562,
43896      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
43897      GIM_Try, /*On fail goto*//*Label 2227*/ 118508, // Rule ID 1634 //
43898        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
43899        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
43900        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
43901        // (fp_to_sint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTh2sq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
43902        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2sq,
43903        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43904        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43905        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43906        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43907        GIR_EraseFromParent, /*InsnID*/0,
43908        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43909        // GIR_Coverage, 1634,
43910        GIR_Done,
43911      // Label 2227: @118508
43912      GIM_Try, /*On fail goto*//*Label 2228*/ 118561, // Rule ID 4188 //
43913        GIM_CheckFeatures, GIFBS_HasMVEFloat,
43914        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
43915        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
43916        // (fp_to_sint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VCVTs16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
43917        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43918        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
43919        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
43920        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs16f16z,
43921        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
43922        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
43923        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
43924        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43925        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43926        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43927        GIR_EraseFromParent, /*InsnID*/0,
43928        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43929        // GIR_Coverage, 4188,
43930        GIR_Done,
43931      // Label 2228: @118561
43932      GIM_Reject,
43933    // Label 2226: @118562
43934    GIM_Reject,
43935    // Label 2205: @118563
43936    GIM_Reject,
43937    // Label 41: @118564
43938    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 13, /*)*//*default:*//*Label 2236*/ 119802,
43939    /*GILLT_s32*//*Label 2229*/ 118582, 0, 0,
43940    /*GILLT_v2s32*//*Label 2230*/ 119428, 0,
43941    /*GILLT_v4s1*//*Label 2231*/ 119468,
43942    /*GILLT_v4s16*//*Label 2232*/ 119519,
43943    /*GILLT_v4s32*//*Label 2233*/ 119559, 0,
43944    /*GILLT_v8s1*//*Label 2234*/ 119655, 0,
43945    /*GILLT_v8s16*//*Label 2235*/ 119706,
43946    // Label 2229: @118582
43947    GIM_Try, /*On fail goto*//*Label 2237*/ 118645, // Rule ID 2322 //
43948      GIM_CheckFeatures, GIFBS_HasFullFP16,
43949      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
43950      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
43951      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43952      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL,
43953      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43954      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
43955      GIM_CheckIsSafeToFold, /*InsnID*/1,
43956      // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
43957      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43958      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPUH,
43959      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43960      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
43961      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43962      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43963      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43964      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43965      GIR_EraseFromParent, /*InsnID*/0,
43966      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
43967      // GIR_Coverage, 2322,
43968      GIR_Done,
43969    // Label 2237: @118645
43970    GIM_Try, /*On fail goto*//*Label 2238*/ 118708, // Rule ID 2324 //
43971      GIM_CheckFeatures, GIFBS_HasFPARMv8,
43972      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43973      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
43974      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43975      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL,
43976      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43977      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
43978      GIM_CheckIsSafeToFold, /*InsnID*/1,
43979      // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
43980      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43981      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPUS,
43982      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43983      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
43984      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43985      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43986      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43987      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43988      GIR_EraseFromParent, /*InsnID*/0,
43989      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
43990      // GIR_Coverage, 2324,
43991      GIR_Done,
43992    // Label 2238: @118708
43993    GIM_Try, /*On fail goto*//*Label 2239*/ 118771, // Rule ID 2326 //
43994      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
43995      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
43996      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
43997      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43998      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL,
43999      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
44000      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44001      GIM_CheckIsSafeToFold, /*InsnID*/1,
44002      // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
44003      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44004      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPUD,
44005      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
44006      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44007      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44008      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
44009      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
44010      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44011      GIR_EraseFromParent, /*InsnID*/0,
44012      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
44013      // GIR_Coverage, 2326,
44014      GIR_Done,
44015    // Label 2239: @118771
44016    GIM_Try, /*On fail goto*//*Label 2240*/ 118834, // Rule ID 2328 //
44017      GIM_CheckFeatures, GIFBS_HasFullFP16,
44018      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
44019      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
44020      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44021      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR,
44022      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
44023      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
44024      GIM_CheckIsSafeToFold, /*InsnID*/1,
44025      // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
44026      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44027      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMUH,
44028      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
44029      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44030      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44031      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
44032      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
44033      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44034      GIR_EraseFromParent, /*InsnID*/0,
44035      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
44036      // GIR_Coverage, 2328,
44037      GIR_Done,
44038    // Label 2240: @118834
44039    GIM_Try, /*On fail goto*//*Label 2241*/ 118897, // Rule ID 2330 //
44040      GIM_CheckFeatures, GIFBS_HasFPARMv8,
44041      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44042      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
44043      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44044      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR,
44045      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
44046      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
44047      GIM_CheckIsSafeToFold, /*InsnID*/1,
44048      // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
44049      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44050      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMUS,
44051      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
44052      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44053      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44054      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
44055      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
44056      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44057      GIR_EraseFromParent, /*InsnID*/0,
44058      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
44059      // GIR_Coverage, 2330,
44060      GIR_Done,
44061    // Label 2241: @118897
44062    GIM_Try, /*On fail goto*//*Label 2242*/ 118960, // Rule ID 2332 //
44063      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
44064      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
44065      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
44066      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44067      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR,
44068      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
44069      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44070      GIM_CheckIsSafeToFold, /*InsnID*/1,
44071      // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
44072      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44073      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMUD,
44074      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
44075      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44076      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44077      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
44078      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
44079      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44080      GIR_EraseFromParent, /*InsnID*/0,
44081      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
44082      // GIR_Coverage, 2332,
44083      GIR_Done,
44084    // Label 2242: @118960
44085    GIM_Try, /*On fail goto*//*Label 2243*/ 119023, // Rule ID 2316 //
44086      GIM_CheckFeatures, GIFBS_HasFullFP16,
44087      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
44088      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
44089      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44090      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND,
44091      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
44092      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
44093      GIM_CheckIsSafeToFold, /*InsnID*/1,
44094      // (fp_to_uint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
44095      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44096      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTAUH,
44097      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
44098      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44099      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44100      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
44101      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
44102      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44103      GIR_EraseFromParent, /*InsnID*/0,
44104      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
44105      // GIR_Coverage, 2316,
44106      GIR_Done,
44107    // Label 2243: @119023
44108    GIM_Try, /*On fail goto*//*Label 2244*/ 119086, // Rule ID 2318 //
44109      GIM_CheckFeatures, GIFBS_HasFPARMv8,
44110      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44111      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
44112      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44113      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND,
44114      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
44115      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
44116      GIM_CheckIsSafeToFold, /*InsnID*/1,
44117      // (fp_to_uint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
44118      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44119      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTAUS,
44120      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
44121      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44122      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44123      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
44124      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
44125      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44126      GIR_EraseFromParent, /*InsnID*/0,
44127      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
44128      // GIR_Coverage, 2318,
44129      GIR_Done,
44130    // Label 2244: @119086
44131    GIM_Try, /*On fail goto*//*Label 2245*/ 119149, // Rule ID 2320 //
44132      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
44133      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
44134      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
44135      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44136      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND,
44137      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
44138      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44139      GIM_CheckIsSafeToFold, /*InsnID*/1,
44140      // (fp_to_uint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
44141      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44142      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTAUD,
44143      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
44144      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44145      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44146      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
44147      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
44148      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44149      GIR_EraseFromParent, /*InsnID*/0,
44150      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
44151      // GIR_Coverage, 2320,
44152      GIR_Done,
44153    // Label 2245: @119149
44154    GIM_Try, /*On fail goto*//*Label 2246*/ 119206, // Rule ID 2362 //
44155      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
44156      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
44157      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
44158      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44159      // (fp_to_uint:{ *:[i32] } DPR:{ *:[f64] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
44160      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44161      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOUIZD,
44162      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
44163      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44164      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
44165      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44166      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44167      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
44168      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
44169      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44170      GIR_EraseFromParent, /*InsnID*/0,
44171      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
44172      // GIR_Coverage, 2362,
44173      GIR_Done,
44174    // Label 2246: @119206
44175    GIM_Try, /*On fail goto*//*Label 2247*/ 119263, // Rule ID 2366 //
44176      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
44177      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44178      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
44179      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
44180      // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
44181      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44182      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOUIZS,
44183      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
44184      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44185      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
44186      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44187      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44188      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
44189      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
44190      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44191      GIR_EraseFromParent, /*InsnID*/0,
44192      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
44193      // GIR_Coverage, 2366,
44194      GIR_Done,
44195    // Label 2247: @119263
44196    GIM_Try, /*On fail goto*//*Label 2248*/ 119320, // Rule ID 2370 //
44197      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
44198      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
44199      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
44200      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
44201      // (fp_to_uint:{ *:[i32] } HPR:{ *:[f16] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
44202      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44203      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOUIZH,
44204      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
44205      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44206      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
44207      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44208      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44209      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
44210      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
44211      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44212      GIR_EraseFromParent, /*InsnID*/0,
44213      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
44214      // GIR_Coverage, 2370,
44215      GIR_Done,
44216    // Label 2248: @119320
44217    GIM_Try, /*On fail goto*//*Label 2249*/ 119427, // Rule ID 2726 //
44218      GIM_CheckFeatures, GIFBS_HasNEON_UseNEONForFP,
44219      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44220      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44221      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
44222      // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a)  =>  (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2ud:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
44223      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
44224      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
44225      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
44226      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44227      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
44228      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
44229      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG,
44230      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
44231      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
44232      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a
44233      GIR_AddImm, /*InsnID*/2, /*Imm*/17,
44234      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, ARM::DPR_VFP2RegClassID,
44235      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, ARM::DPR_VFP2RegClassID,
44236      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, ARM::SPRRegClassID,
44237      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTf2ud,
44238      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
44239      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
44240      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
44241      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44242      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44243      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
44244      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
44245      GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
44246      GIR_EraseFromParent, /*InsnID*/0,
44247      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
44248      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
44249      // GIR_Coverage, 2726,
44250      GIR_Done,
44251    // Label 2249: @119427
44252    GIM_Reject,
44253    // Label 2230: @119428
44254    GIM_Try, /*On fail goto*//*Label 2250*/ 119467, // Rule ID 1623 //
44255      GIM_CheckFeatures, GIFBS_HasNEON,
44256      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
44257      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44258      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44259      // (fp_to_uint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTf2ud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
44260      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2ud,
44261      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44262      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44263      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44264      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44265      GIR_EraseFromParent, /*InsnID*/0,
44266      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44267      // GIR_Coverage, 1623,
44268      GIR_Done,
44269    // Label 2250: @119467
44270    GIM_Reject,
44271    // Label 2231: @119468
44272    GIM_Try, /*On fail goto*//*Label 2251*/ 119518, // Rule ID 5203 //
44273      GIM_CheckFeatures, GIFBS_HasMVEFloat,
44274      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
44275      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
44276      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44277      // (fp_to_uint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1)  =>  (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
44278      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPf32r,
44279      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
44280      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1
44281      GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
44282      GIR_AddImm, /*InsnID*/0, /*Imm*/1,
44283      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44284      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44285      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44286      GIR_EraseFromParent, /*InsnID*/0,
44287      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44288      // GIR_Coverage, 5203,
44289      GIR_Done,
44290    // Label 2251: @119518
44291    GIM_Reject,
44292    // Label 2232: @119519
44293    GIM_Try, /*On fail goto*//*Label 2252*/ 119558, // Rule ID 1631 //
44294      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
44295      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
44296      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44297      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44298      // (fp_to_uint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTh2ud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
44299      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2ud,
44300      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44301      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44302      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44303      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44304      GIR_EraseFromParent, /*InsnID*/0,
44305      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44306      // GIR_Coverage, 1631,
44307      GIR_Done,
44308    // Label 2252: @119558
44309    GIM_Reject,
44310    // Label 2233: @119559
44311    GIM_Try, /*On fail goto*//*Label 2253*/ 119654,
44312      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
44313      GIM_Try, /*On fail goto*//*Label 2254*/ 119600, // Rule ID 1627 //
44314        GIM_CheckFeatures, GIFBS_HasNEON,
44315        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
44316        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
44317        // (fp_to_uint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTf2uq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
44318        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2uq,
44319        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44321        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44322        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44323        GIR_EraseFromParent, /*InsnID*/0,
44324        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44325        // GIR_Coverage, 1627,
44326        GIR_Done,
44327      // Label 2254: @119600
44328      GIM_Try, /*On fail goto*//*Label 2255*/ 119653, // Rule ID 4194 //
44329        GIM_CheckFeatures, GIFBS_HasMVEFloat,
44330        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
44331        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44332        // (fp_to_uint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)  =>  (MVE_VCVTu32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
44333        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44334        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44335        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
44336        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu32f32z,
44337        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
44338        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
44339        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44340        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44341        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44342        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44343        GIR_EraseFromParent, /*InsnID*/0,
44344        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44345        // GIR_Coverage, 4194,
44346        GIR_Done,
44347      // Label 2255: @119653
44348      GIM_Reject,
44349    // Label 2253: @119654
44350    GIM_Reject,
44351    // Label 2234: @119655
44352    GIM_Try, /*On fail goto*//*Label 2256*/ 119705, // Rule ID 5204 //
44353      GIM_CheckFeatures, GIFBS_HasMVEFloat,
44354      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
44355      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
44356      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44357      // (fp_to_uint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1)  =>  (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
44358      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPf16r,
44359      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
44360      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1
44361      GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
44362      GIR_AddImm, /*InsnID*/0, /*Imm*/1,
44363      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44364      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44365      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44366      GIR_EraseFromParent, /*InsnID*/0,
44367      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44368      // GIR_Coverage, 5204,
44369      GIR_Done,
44370    // Label 2256: @119705
44371    GIM_Reject,
44372    // Label 2235: @119706
44373    GIM_Try, /*On fail goto*//*Label 2257*/ 119801,
44374      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
44375      GIM_Try, /*On fail goto*//*Label 2258*/ 119747, // Rule ID 1635 //
44376        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
44377        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
44378        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
44379        // (fp_to_uint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTh2uq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
44380        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2uq,
44381        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44382        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44383        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44384        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44385        GIR_EraseFromParent, /*InsnID*/0,
44386        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44387        // GIR_Coverage, 1635,
44388        GIR_Done,
44389      // Label 2258: @119747
44390      GIM_Try, /*On fail goto*//*Label 2259*/ 119800, // Rule ID 4190 //
44391        GIM_CheckFeatures, GIFBS_HasMVEFloat,
44392        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
44393        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44394        // (fp_to_uint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)  =>  (MVE_VCVTu16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
44395        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44396        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44397        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
44398        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu16f16z,
44399        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
44400        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
44401        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44402        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44403        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44404        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44405        GIR_EraseFromParent, /*InsnID*/0,
44406        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44407        // GIR_Coverage, 4190,
44408        GIR_Done,
44409      // Label 2259: @119800
44410      GIM_Reject,
44411    // Label 2257: @119801
44412    GIM_Reject,
44413    // Label 2236: @119802
44414    GIM_Reject,
44415    // Label 42: @119803
44416    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2267*/ 120384,
44417    /*GILLT_s16*//*Label 2260*/ 119822,
44418    /*GILLT_s32*//*Label 2261*/ 119878,
44419    /*GILLT_s64*//*Label 2262*/ 120056, 0,
44420    /*GILLT_v2s32*//*Label 2263*/ 120112, 0, 0,
44421    /*GILLT_v4s16*//*Label 2264*/ 120152,
44422    /*GILLT_v4s32*//*Label 2265*/ 120192, 0, 0, 0,
44423    /*GILLT_v8s16*//*Label 2266*/ 120288,
44424    // Label 2260: @119822
44425    GIM_Try, /*On fail goto*//*Label 2268*/ 119877, // Rule ID 2346 //
44426      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
44427      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44428      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
44429      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
44430      // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a)  =>  (VSITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
44431      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44432      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
44433      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
44434      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44435      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44436      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSITOH,
44437      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
44438      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44439      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44440      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44441      GIR_EraseFromParent, /*InsnID*/0,
44442      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44443      // GIR_Coverage, 2346,
44444      GIR_Done,
44445    // Label 2268: @119877
44446    GIM_Reject,
44447    // Label 2261: @119878
44448    GIM_Try, /*On fail goto*//*Label 2269*/ 120055,
44449      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44450      GIM_Try, /*On fail goto*//*Label 2270*/ 119935, // Rule ID 2344 //
44451        GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
44452        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
44453        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
44454        // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a)  =>  (VSITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
44455        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44456        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
44457        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
44458        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44459        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44460        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSITOS,
44461        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
44462        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44463        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44464        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44465        GIR_EraseFromParent, /*InsnID*/0,
44466        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44467        // GIR_Coverage, 2344,
44468        GIR_Done,
44469      // Label 2270: @119935
44470      GIM_Try, /*On fail goto*//*Label 2271*/ 120054, // Rule ID 2727 //
44471        GIM_CheckFeatures, GIFBS_HasNEON_UseNEONForFP,
44472        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44473        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
44474        // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a)  =>  (EXTRACT_SUBREG:{ *:[f32] } (VCVTs2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
44475        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
44476        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
44477        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
44478        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
44479        GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
44480        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
44481        GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a
44482        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
44483        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44484        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
44485        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
44486        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG,
44487        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
44488        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
44489        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/3, /*TempRegFlags*/0,
44490        GIR_AddImm, /*InsnID*/2, /*Imm*/17,
44491        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, ARM::DPR_VFP2RegClassID,
44492        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, ARM::DPR_VFP2RegClassID,
44493        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, ARM::SPRRegClassID,
44494        GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTs2fd,
44495        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
44496        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
44497        GIR_AddImm, /*InsnID*/1, /*Imm*/14,
44498        GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44499        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44500        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
44501        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
44502        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
44503        GIR_EraseFromParent, /*InsnID*/0,
44504        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
44505        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
44506        // GIR_Coverage, 2727,
44507        GIR_Done,
44508      // Label 2271: @120054
44509      GIM_Reject,
44510    // Label 2269: @120055
44511    GIM_Reject,
44512    // Label 2262: @120056
44513    GIM_Try, /*On fail goto*//*Label 2272*/ 120111, // Rule ID 2342 //
44514      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
44515      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44516      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44517      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
44518      // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a)  =>  (VSITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
44519      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44520      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
44521      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
44522      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44523      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44524      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSITOD,
44525      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
44526      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44527      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44528      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44529      GIR_EraseFromParent, /*InsnID*/0,
44530      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44531      // GIR_Coverage, 2342,
44532      GIR_Done,
44533    // Label 2272: @120111
44534    GIM_Reject,
44535    // Label 2263: @120112
44536    GIM_Try, /*On fail goto*//*Label 2273*/ 120151, // Rule ID 1624 //
44537      GIM_CheckFeatures, GIFBS_HasNEON,
44538      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
44539      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44540      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44541      // (sint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)  =>  (VCVTs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)
44542      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2fd,
44543      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44544      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44545      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44546      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44547      GIR_EraseFromParent, /*InsnID*/0,
44548      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44549      // GIR_Coverage, 1624,
44550      GIR_Done,
44551    // Label 2273: @120151
44552    GIM_Reject,
44553    // Label 2264: @120152
44554    GIM_Try, /*On fail goto*//*Label 2274*/ 120191, // Rule ID 1632 //
44555      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
44556      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
44557      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44558      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44559      // (sint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)  =>  (VCVTs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)
44560      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2hd,
44561      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44562      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44563      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44564      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44565      GIR_EraseFromParent, /*InsnID*/0,
44566      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44567      // GIR_Coverage, 1632,
44568      GIR_Done,
44569    // Label 2274: @120191
44570    GIM_Reject,
44571    // Label 2265: @120192
44572    GIM_Try, /*On fail goto*//*Label 2275*/ 120287,
44573      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
44574      GIM_Try, /*On fail goto*//*Label 2276*/ 120233, // Rule ID 1628 //
44575        GIM_CheckFeatures, GIFBS_HasNEON,
44576        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
44577        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
44578        // (sint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)  =>  (VCVTs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)
44579        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2fq,
44580        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44581        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44582        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44583        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44584        GIR_EraseFromParent, /*InsnID*/0,
44585        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44586        // GIR_Coverage, 1628,
44587        GIR_Done,
44588      // Label 2276: @120233
44589      GIM_Try, /*On fail goto*//*Label 2277*/ 120286, // Rule ID 4200 //
44590        GIM_CheckFeatures, GIFBS_HasMVEFloat,
44591        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
44592        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44593        // (sint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VCVTf32s32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
44594        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44595        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44596        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
44597        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf32s32n,
44598        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
44599        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
44600        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44601        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44602        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44603        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44604        GIR_EraseFromParent, /*InsnID*/0,
44605        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44606        // GIR_Coverage, 4200,
44607        GIR_Done,
44608      // Label 2277: @120286
44609      GIM_Reject,
44610    // Label 2275: @120287
44611    GIM_Reject,
44612    // Label 2266: @120288
44613    GIM_Try, /*On fail goto*//*Label 2278*/ 120383,
44614      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
44615      GIM_Try, /*On fail goto*//*Label 2279*/ 120329, // Rule ID 1636 //
44616        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
44617        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
44618        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
44619        // (sint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)  =>  (VCVTs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)
44620        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2hq,
44621        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44622        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44623        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44624        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44625        GIR_EraseFromParent, /*InsnID*/0,
44626        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44627        // GIR_Coverage, 1636,
44628        GIR_Done,
44629      // Label 2279: @120329
44630      GIM_Try, /*On fail goto*//*Label 2280*/ 120382, // Rule ID 4196 //
44631        GIM_CheckFeatures, GIFBS_HasMVEFloat,
44632        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
44633        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44634        // (sint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VCVTf16s16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
44635        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44636        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44637        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
44638        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16s16n,
44639        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
44640        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
44641        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44642        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44643        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44644        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44645        GIR_EraseFromParent, /*InsnID*/0,
44646        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44647        // GIR_Coverage, 4196,
44648        GIR_Done,
44649      // Label 2280: @120382
44650      GIM_Reject,
44651    // Label 2278: @120383
44652    GIM_Reject,
44653    // Label 2267: @120384
44654    GIM_Reject,
44655    // Label 43: @120385
44656    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2288*/ 120966,
44657    /*GILLT_s16*//*Label 2281*/ 120404,
44658    /*GILLT_s32*//*Label 2282*/ 120460,
44659    /*GILLT_s64*//*Label 2283*/ 120638, 0,
44660    /*GILLT_v2s32*//*Label 2284*/ 120694, 0, 0,
44661    /*GILLT_v4s16*//*Label 2285*/ 120734,
44662    /*GILLT_v4s32*//*Label 2286*/ 120774, 0, 0, 0,
44663    /*GILLT_v8s16*//*Label 2287*/ 120870,
44664    // Label 2281: @120404
44665    GIM_Try, /*On fail goto*//*Label 2289*/ 120459, // Rule ID 2351 //
44666      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
44667      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44668      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
44669      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
44670      // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a)  =>  (VUITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
44671      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44672      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
44673      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
44674      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44675      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44676      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUITOH,
44677      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
44678      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44679      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44680      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44681      GIR_EraseFromParent, /*InsnID*/0,
44682      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44683      // GIR_Coverage, 2351,
44684      GIR_Done,
44685    // Label 2289: @120459
44686    GIM_Reject,
44687    // Label 2282: @120460
44688    GIM_Try, /*On fail goto*//*Label 2290*/ 120637,
44689      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44690      GIM_Try, /*On fail goto*//*Label 2291*/ 120517, // Rule ID 2349 //
44691        GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
44692        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
44693        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
44694        // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a)  =>  (VUITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
44695        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44696        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
44697        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
44698        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44699        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44700        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUITOS,
44701        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
44702        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44703        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44704        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44705        GIR_EraseFromParent, /*InsnID*/0,
44706        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44707        // GIR_Coverage, 2349,
44708        GIR_Done,
44709      // Label 2291: @120517
44710      GIM_Try, /*On fail goto*//*Label 2292*/ 120636, // Rule ID 2728 //
44711        GIM_CheckFeatures, GIFBS_HasNEON_UseNEONForFP,
44712        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44713        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
44714        // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a)  =>  (EXTRACT_SUBREG:{ *:[f32] } (VCVTu2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
44715        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
44716        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
44717        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
44718        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
44719        GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
44720        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
44721        GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a
44722        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
44723        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44724        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
44725        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
44726        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG,
44727        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
44728        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
44729        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/3, /*TempRegFlags*/0,
44730        GIR_AddImm, /*InsnID*/2, /*Imm*/17,
44731        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, ARM::DPR_VFP2RegClassID,
44732        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, ARM::DPR_VFP2RegClassID,
44733        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, ARM::SPRRegClassID,
44734        GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTu2fd,
44735        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
44736        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
44737        GIR_AddImm, /*InsnID*/1, /*Imm*/14,
44738        GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44739        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44740        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
44741        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
44742        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
44743        GIR_EraseFromParent, /*InsnID*/0,
44744        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
44745        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
44746        // GIR_Coverage, 2728,
44747        GIR_Done,
44748      // Label 2292: @120636
44749      GIM_Reject,
44750    // Label 2290: @120637
44751    GIM_Reject,
44752    // Label 2283: @120638
44753    GIM_Try, /*On fail goto*//*Label 2293*/ 120693, // Rule ID 2347 //
44754      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
44755      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44756      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44757      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
44758      // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a)  =>  (VUITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
44759      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44760      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
44761      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
44762      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44763      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44764      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUITOD,
44765      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
44766      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44767      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44768      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44769      GIR_EraseFromParent, /*InsnID*/0,
44770      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44771      // GIR_Coverage, 2347,
44772      GIR_Done,
44773    // Label 2293: @120693
44774    GIM_Reject,
44775    // Label 2284: @120694
44776    GIM_Try, /*On fail goto*//*Label 2294*/ 120733, // Rule ID 1625 //
44777      GIM_CheckFeatures, GIFBS_HasNEON,
44778      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
44779      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44780      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44781      // (uint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)  =>  (VCVTu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)
44782      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2fd,
44783      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44784      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44785      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44786      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44787      GIR_EraseFromParent, /*InsnID*/0,
44788      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44789      // GIR_Coverage, 1625,
44790      GIR_Done,
44791    // Label 2294: @120733
44792    GIM_Reject,
44793    // Label 2285: @120734
44794    GIM_Try, /*On fail goto*//*Label 2295*/ 120773, // Rule ID 1633 //
44795      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
44796      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
44797      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44798      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44799      // (uint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)  =>  (VCVTu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)
44800      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2hd,
44801      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44802      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44803      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44804      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44805      GIR_EraseFromParent, /*InsnID*/0,
44806      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44807      // GIR_Coverage, 1633,
44808      GIR_Done,
44809    // Label 2295: @120773
44810    GIM_Reject,
44811    // Label 2286: @120774
44812    GIM_Try, /*On fail goto*//*Label 2296*/ 120869,
44813      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
44814      GIM_Try, /*On fail goto*//*Label 2297*/ 120815, // Rule ID 1629 //
44815        GIM_CheckFeatures, GIFBS_HasNEON,
44816        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
44817        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
44818        // (uint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)  =>  (VCVTu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)
44819        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2fq,
44820        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44821        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44822        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44823        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44824        GIR_EraseFromParent, /*InsnID*/0,
44825        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44826        // GIR_Coverage, 1629,
44827        GIR_Done,
44828      // Label 2297: @120815
44829      GIM_Try, /*On fail goto*//*Label 2298*/ 120868, // Rule ID 4202 //
44830        GIM_CheckFeatures, GIFBS_HasMVEFloat,
44831        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
44832        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44833        // (uint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VCVTf32u32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
44834        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44835        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44836        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
44837        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf32u32n,
44838        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
44839        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
44840        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44841        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44842        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44843        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44844        GIR_EraseFromParent, /*InsnID*/0,
44845        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44846        // GIR_Coverage, 4202,
44847        GIR_Done,
44848      // Label 2298: @120868
44849      GIM_Reject,
44850    // Label 2296: @120869
44851    GIM_Reject,
44852    // Label 2287: @120870
44853    GIM_Try, /*On fail goto*//*Label 2299*/ 120965,
44854      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
44855      GIM_Try, /*On fail goto*//*Label 2300*/ 120911, // Rule ID 1637 //
44856        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
44857        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
44858        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
44859        // (uint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)  =>  (VCVTu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)
44860        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2hq,
44861        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44862        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
44863        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44864        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44865        GIR_EraseFromParent, /*InsnID*/0,
44866        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44867        // GIR_Coverage, 1637,
44868        GIR_Done,
44869      // Label 2300: @120911
44870      GIM_Try, /*On fail goto*//*Label 2301*/ 120964, // Rule ID 4198 //
44871        GIM_CheckFeatures, GIFBS_HasMVEFloat,
44872        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
44873        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44874        // (uint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VCVTf16u16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
44875        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44876        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44877        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
44878        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16u16n,
44879        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
44880        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
44881        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44882        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44883        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44884        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44885        GIR_EraseFromParent, /*InsnID*/0,
44886        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44887        // GIR_Coverage, 4198,
44888        GIR_Done,
44889      // Label 2301: @120964
44890      GIM_Reject,
44891    // Label 2299: @120965
44892    GIM_Reject,
44893    // Label 2288: @120966
44894    GIM_Reject,
44895    // Label 44: @120967
44896    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2309*/ 121566,
44897    /*GILLT_s16*//*Label 2302*/ 120986,
44898    /*GILLT_s32*//*Label 2303*/ 121026,
44899    /*GILLT_s64*//*Label 2304*/ 121204, 0,
44900    /*GILLT_v2s32*//*Label 2305*/ 121244, 0, 0,
44901    /*GILLT_v4s16*//*Label 2306*/ 121284,
44902    /*GILLT_v4s32*//*Label 2307*/ 121324, 0, 0, 0,
44903    /*GILLT_v8s16*//*Label 2308*/ 121445,
44904    // Label 2302: @120986
44905    GIM_Try, /*On fail goto*//*Label 2310*/ 121025, // Rule ID 669 //
44906      GIM_CheckFeatures, GIFBS_HasFullFP16,
44907      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
44908      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
44909      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
44910      // (fabs:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VABSH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
44911      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSH,
44912      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
44913      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
44914      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44915      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44916      GIR_EraseFromParent, /*InsnID*/0,
44917      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44918      // GIR_Coverage, 669,
44919      GIR_Done,
44920    // Label 2310: @121025
44921    GIM_Reject,
44922    // Label 2303: @121026
44923    GIM_Try, /*On fail goto*//*Label 2311*/ 121203,
44924      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44925      GIM_Try, /*On fail goto*//*Label 2312*/ 121067, // Rule ID 668 //
44926        GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
44927        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
44928        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
44929        // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VABSS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
44930        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSS,
44931        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
44932        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
44933        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44934        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44935        GIR_EraseFromParent, /*InsnID*/0,
44936        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44937        // GIR_Coverage, 668,
44938        GIR_Done,
44939      // Label 2312: @121067
44940      GIM_Try, /*On fail goto*//*Label 2313*/ 121202, // Rule ID 2719 //
44941        GIM_CheckFeatures, GIFBS_HasNEON_UseNEONForFP,
44942        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
44943        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
44944        // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$a)  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VABSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
44945        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
44946        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
44947        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
44948        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
44949        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
44950        GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44951        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
44952        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
44953        GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
44954        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
44955        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
44956        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
44957        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
44958        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
44959        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
44960        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
44961        GIR_AddImm, /*InsnID*/3, /*Imm*/17,
44962        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
44963        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
44964        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
44965        GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VABSfd,
44966        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
44967        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
44968        GIR_AddImm, /*InsnID*/2, /*Imm*/14,
44969        GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44970        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44971        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
44972        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
44973        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
44974        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44975        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
44976        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
44977        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
44978        GIR_EraseFromParent, /*InsnID*/0,
44979        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
44980        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
44981        // GIR_Coverage, 2719,
44982        GIR_Done,
44983      // Label 2313: @121202
44984      GIM_Reject,
44985    // Label 2311: @121203
44986    GIM_Reject,
44987    // Label 2304: @121204
44988    GIM_Try, /*On fail goto*//*Label 2314*/ 121243, // Rule ID 667 //
44989      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
44990      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
44991      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44992      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44993      // (fabs:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VABSD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
44994      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSD,
44995      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
44996      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
44997      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44998      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44999      GIR_EraseFromParent, /*InsnID*/0,
45000      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45001      // GIR_Coverage, 667,
45002      GIR_Done,
45003    // Label 2314: @121243
45004    GIM_Reject,
45005    // Label 2305: @121244
45006    GIM_Try, /*On fail goto*//*Label 2315*/ 121283, // Rule ID 1532 //
45007      GIM_CheckFeatures, GIFBS_HasNEON,
45008      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
45009      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
45010      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45011      // (fabs:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)  =>  (VABSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
45012      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSfd,
45013      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45014      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
45015      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45016      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45017      GIR_EraseFromParent, /*InsnID*/0,
45018      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45019      // GIR_Coverage, 1532,
45020      GIR_Done,
45021    // Label 2315: @121283
45022    GIM_Reject,
45023    // Label 2306: @121284
45024    GIM_Try, /*On fail goto*//*Label 2316*/ 121323, // Rule ID 1534 //
45025      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
45026      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
45027      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
45028      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45029      // (fabs:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)  =>  (VABShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
45030      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABShd,
45031      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45032      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
45033      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45034      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45035      GIR_EraseFromParent, /*InsnID*/0,
45036      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45037      // GIR_Coverage, 1534,
45038      GIR_Done,
45039    // Label 2316: @121323
45040    GIM_Reject,
45041    // Label 2307: @121324
45042    GIM_Try, /*On fail goto*//*Label 2317*/ 121444,
45043      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
45044      GIM_Try, /*On fail goto*//*Label 2318*/ 121408, // Rule ID 4139 //
45045        GIM_CheckFeatures, GIFBS_HasMVEFloat,
45046        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
45047        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45048        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
45049        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
45050        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
45051        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45052        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
45053        GIM_CheckIsSafeToFold, /*InsnID*/1,
45054        // (fabs:{ *:[v4f32] } (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn))  =>  (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
45055        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45056        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
45057        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
45058        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDf32,
45059        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
45060        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
45061        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn
45062        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45063        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45064        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45065        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
45066        GIR_EraseFromParent, /*InsnID*/0,
45067        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45068        // GIR_Coverage, 4139,
45069        GIR_Done,
45070      // Label 2318: @121408
45071      GIM_Try, /*On fail goto*//*Label 2319*/ 121443, // Rule ID 1533 //
45072        GIM_CheckFeatures, GIFBS_HasNEON,
45073        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
45074        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
45075        // (fabs:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)  =>  (VABSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
45076        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSfq,
45077        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45078        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
45079        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45080        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45081        GIR_EraseFromParent, /*InsnID*/0,
45082        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45083        // GIR_Coverage, 1533,
45084        GIR_Done,
45085      // Label 2319: @121443
45086      GIM_Reject,
45087    // Label 2317: @121444
45088    GIM_Reject,
45089    // Label 2308: @121445
45090    GIM_Try, /*On fail goto*//*Label 2320*/ 121565,
45091      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
45092      GIM_Try, /*On fail goto*//*Label 2321*/ 121529, // Rule ID 4138 //
45093        GIM_CheckFeatures, GIFBS_HasMVEFloat,
45094        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
45095        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45096        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
45097        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
45098        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
45099        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45100        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
45101        GIM_CheckIsSafeToFold, /*InsnID*/1,
45102        // (fabs:{ *:[v8f16] } (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn))  =>  (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
45103        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45104        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
45105        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
45106        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDf16,
45107        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
45108        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
45109        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn
45110        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45111        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45112        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45113        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
45114        GIR_EraseFromParent, /*InsnID*/0,
45115        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45116        // GIR_Coverage, 4138,
45117        GIR_Done,
45118      // Label 2321: @121529
45119      GIM_Try, /*On fail goto*//*Label 2322*/ 121564, // Rule ID 1535 //
45120        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
45121        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
45122        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
45123        // (fabs:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)  =>  (VABShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
45124        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABShq,
45125        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45126        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
45127        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45128        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45129        GIR_EraseFromParent, /*InsnID*/0,
45130        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45131        // GIR_Coverage, 1535,
45132        GIR_Done,
45133      // Label 2322: @121564
45134      GIM_Reject,
45135    // Label 2320: @121565
45136    GIM_Reject,
45137    // Label 2309: @121566
45138    GIM_Reject,
45139    // Label 45: @121567
45140    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2330*/ 122086,
45141    /*GILLT_s16*//*Label 2323*/ 121586,
45142    /*GILLT_s32*//*Label 2324*/ 121618,
45143    /*GILLT_s64*//*Label 2325*/ 121650, 0,
45144    /*GILLT_v2s32*//*Label 2326*/ 121682, 0, 0,
45145    /*GILLT_v4s16*//*Label 2327*/ 121714,
45146    /*GILLT_v4s32*//*Label 2328*/ 121746, 0, 0, 0,
45147    /*GILLT_v8s16*//*Label 2329*/ 121916,
45148    // Label 2323: @121586
45149    GIM_Try, /*On fail goto*//*Label 2331*/ 121617, // Rule ID 658 //
45150      GIM_CheckFeatures, GIFBS_HasFullFP16,
45151      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
45152      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
45153      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
45154      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
45155      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
45156      // (fminnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)  =>  (VFP_VMINNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
45157      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMINNMH,
45158      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45159      // GIR_Coverage, 658,
45160      GIR_Done,
45161    // Label 2331: @121617
45162    GIM_Reject,
45163    // Label 2324: @121618
45164    GIM_Try, /*On fail goto*//*Label 2332*/ 121649, // Rule ID 659 //
45165      GIM_CheckFeatures, GIFBS_HasFPARMv8,
45166      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
45167      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
45168      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
45169      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
45170      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
45171      // (fminnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)  =>  (VFP_VMINNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
45172      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMINNMS,
45173      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45174      // GIR_Coverage, 659,
45175      GIR_Done,
45176    // Label 2332: @121649
45177    GIM_Reject,
45178    // Label 2325: @121650
45179    GIM_Try, /*On fail goto*//*Label 2333*/ 121681, // Rule ID 660 //
45180      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
45181      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
45182      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
45183      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
45184      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45185      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
45186      // (fminnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)  =>  (VFP_VMINNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
45187      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMINNMD,
45188      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45189      // GIR_Coverage, 660,
45190      GIR_Done,
45191    // Label 2333: @121681
45192    GIM_Reject,
45193    // Label 2326: @121682
45194    GIM_Try, /*On fail goto*//*Label 2334*/ 121713, // Rule ID 1251 //
45195      GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
45196      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
45197      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
45198      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
45199      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45200      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
45201      // (fminnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (NEON_VMINNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
45202      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMINNMNDf,
45203      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45204      // GIR_Coverage, 1251,
45205      GIR_Done,
45206    // Label 2334: @121713
45207    GIM_Reject,
45208    // Label 2327: @121714
45209    GIM_Try, /*On fail goto*//*Label 2335*/ 121745, // Rule ID 1253 //
45210      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
45211      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
45212      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
45213      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
45214      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45215      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
45216      // (fminnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (NEON_VMINNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
45217      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMINNMNDh,
45218      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45219      // GIR_Coverage, 1253,
45220      GIR_Done,
45221    // Label 2335: @121745
45222    GIM_Reject,
45223    // Label 2328: @121746
45224    GIM_Try, /*On fail goto*//*Label 2336*/ 121915,
45225      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
45226      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
45227      GIM_Try, /*On fail goto*//*Label 2337*/ 121830, // Rule ID 4220 //
45228        GIM_CheckFeatures, GIFBS_HasMVEInt,
45229        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/1, /*OtherOpIdx*/1,
45230        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45231        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FABS,
45232        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
45233        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45234        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
45235        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FABS,
45236        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
45237        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45238        GIM_CheckIsSafeToFold, /*InsnID*/1,
45239        GIM_CheckIsSafeToFold, /*InsnID*/2,
45240        // (fminnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm))  =>  (MVE_VMINNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm)
45241        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINNMAf32,
45242        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
45243        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
45244        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
45245        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45246        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45247        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45248        GIR_EraseFromParent, /*InsnID*/0,
45249        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45250        // GIR_Coverage, 4220,
45251        GIR_Done,
45252      // Label 2337: @121830
45253      GIM_Try, /*On fail goto*//*Label 2338*/ 121853, // Rule ID 1252 //
45254        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
45255        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
45256        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
45257        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
45258        // (fminnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (NEON_VMINNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
45259        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMINNMNQf,
45260        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45261        // GIR_Coverage, 1252,
45262        GIR_Done,
45263      // Label 2338: @121853
45264      GIM_Try, /*On fail goto*//*Label 2339*/ 121914, // Rule ID 3382 //
45265        GIM_CheckFeatures, GIFBS_HasMVEFloat,
45266        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
45267        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45268        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
45269        // (fminnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)  =>  (MVE_VMINNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
45270        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45271        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
45272        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
45273        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINNMf32,
45274        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
45275        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
45276        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
45277        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45278        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45279        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45280        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
45281        GIR_EraseFromParent, /*InsnID*/0,
45282        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45283        // GIR_Coverage, 3382,
45284        GIR_Done,
45285      // Label 2339: @121914
45286      GIM_Reject,
45287    // Label 2336: @121915
45288    GIM_Reject,
45289    // Label 2329: @121916
45290    GIM_Try, /*On fail goto*//*Label 2340*/ 122085,
45291      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
45292      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
45293      GIM_Try, /*On fail goto*//*Label 2341*/ 122000, // Rule ID 4222 //
45294        GIM_CheckFeatures, GIFBS_HasMVEInt,
45295        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/1, /*OtherOpIdx*/1,
45296        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45297        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FABS,
45298        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
45299        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45300        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
45301        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FABS,
45302        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
45303        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45304        GIM_CheckIsSafeToFold, /*InsnID*/1,
45305        GIM_CheckIsSafeToFold, /*InsnID*/2,
45306        // (fminnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm))  =>  (MVE_VMINNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm)
45307        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINNMAf16,
45308        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
45309        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
45310        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
45311        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45312        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45313        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45314        GIR_EraseFromParent, /*InsnID*/0,
45315        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45316        // GIR_Coverage, 4222,
45317        GIR_Done,
45318      // Label 2341: @122000
45319      GIM_Try, /*On fail goto*//*Label 2342*/ 122023, // Rule ID 1254 //
45320        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
45321        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
45322        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
45323        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
45324        // (fminnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (NEON_VMINNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
45325        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMINNMNQh,
45326        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45327        // GIR_Coverage, 1254,
45328        GIR_Done,
45329      // Label 2342: @122023
45330      GIM_Try, /*On fail goto*//*Label 2343*/ 122084, // Rule ID 3385 //
45331        GIM_CheckFeatures, GIFBS_HasMVEFloat,
45332        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
45333        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45334        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
45335        // (fminnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)  =>  (MVE_VMINNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
45336        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45337        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
45338        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
45339        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINNMf16,
45340        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
45341        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
45342        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
45343        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45344        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45345        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45346        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
45347        GIR_EraseFromParent, /*InsnID*/0,
45348        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45349        // GIR_Coverage, 3385,
45350        GIR_Done,
45351      // Label 2343: @122084
45352      GIM_Reject,
45353    // Label 2340: @122085
45354    GIM_Reject,
45355    // Label 2330: @122086
45356    GIM_Reject,
45357    // Label 46: @122087
45358    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2351*/ 122606,
45359    /*GILLT_s16*//*Label 2344*/ 122106,
45360    /*GILLT_s32*//*Label 2345*/ 122138,
45361    /*GILLT_s64*//*Label 2346*/ 122170, 0,
45362    /*GILLT_v2s32*//*Label 2347*/ 122202, 0, 0,
45363    /*GILLT_v4s16*//*Label 2348*/ 122234,
45364    /*GILLT_v4s32*//*Label 2349*/ 122266, 0, 0, 0,
45365    /*GILLT_v8s16*//*Label 2350*/ 122436,
45366    // Label 2344: @122106
45367    GIM_Try, /*On fail goto*//*Label 2352*/ 122137, // Rule ID 655 //
45368      GIM_CheckFeatures, GIFBS_HasFullFP16,
45369      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
45370      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
45371      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
45372      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
45373      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
45374      // (fmaxnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)  =>  (VFP_VMAXNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
45375      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMAXNMH,
45376      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45377      // GIR_Coverage, 655,
45378      GIR_Done,
45379    // Label 2352: @122137
45380    GIM_Reject,
45381    // Label 2345: @122138
45382    GIM_Try, /*On fail goto*//*Label 2353*/ 122169, // Rule ID 656 //
45383      GIM_CheckFeatures, GIFBS_HasFPARMv8,
45384      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
45385      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
45386      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
45387      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
45388      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
45389      // (fmaxnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)  =>  (VFP_VMAXNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
45390      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMAXNMS,
45391      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45392      // GIR_Coverage, 656,
45393      GIR_Done,
45394    // Label 2353: @122169
45395    GIM_Reject,
45396    // Label 2346: @122170
45397    GIM_Try, /*On fail goto*//*Label 2354*/ 122201, // Rule ID 657 //
45398      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
45399      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
45400      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
45401      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
45402      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45403      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
45404      // (fmaxnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)  =>  (VFP_VMAXNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
45405      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMAXNMD,
45406      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45407      // GIR_Coverage, 657,
45408      GIR_Done,
45409    // Label 2354: @122201
45410    GIM_Reject,
45411    // Label 2347: @122202
45412    GIM_Try, /*On fail goto*//*Label 2355*/ 122233, // Rule ID 1231 //
45413      GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
45414      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
45415      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
45416      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
45417      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45418      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
45419      // (fmaxnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (NEON_VMAXNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
45420      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMAXNMNDf,
45421      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45422      // GIR_Coverage, 1231,
45423      GIR_Done,
45424    // Label 2355: @122233
45425    GIM_Reject,
45426    // Label 2348: @122234
45427    GIM_Try, /*On fail goto*//*Label 2356*/ 122265, // Rule ID 1233 //
45428      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
45429      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
45430      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
45431      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
45432      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45433      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
45434      // (fmaxnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (NEON_VMAXNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
45435      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMAXNMNDh,
45436      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45437      // GIR_Coverage, 1233,
45438      GIR_Done,
45439    // Label 2356: @122265
45440    GIM_Reject,
45441    // Label 2349: @122266
45442    GIM_Try, /*On fail goto*//*Label 2357*/ 122435,
45443      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
45444      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
45445      GIM_Try, /*On fail goto*//*Label 2358*/ 122350, // Rule ID 4216 //
45446        GIM_CheckFeatures, GIFBS_HasMVEInt,
45447        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/1, /*OtherOpIdx*/1,
45448        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45449        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FABS,
45450        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
45451        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45452        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
45453        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FABS,
45454        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
45455        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45456        GIM_CheckIsSafeToFold, /*InsnID*/1,
45457        GIM_CheckIsSafeToFold, /*InsnID*/2,
45458        // (fmaxnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm))  =>  (MVE_VMAXNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm)
45459        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXNMAf32,
45460        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
45461        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
45462        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
45463        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45464        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45465        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45466        GIR_EraseFromParent, /*InsnID*/0,
45467        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45468        // GIR_Coverage, 4216,
45469        GIR_Done,
45470      // Label 2358: @122350
45471      GIM_Try, /*On fail goto*//*Label 2359*/ 122373, // Rule ID 1232 //
45472        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
45473        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
45474        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
45475        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
45476        // (fmaxnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (NEON_VMAXNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
45477        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMAXNMNQf,
45478        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45479        // GIR_Coverage, 1232,
45480        GIR_Done,
45481      // Label 2359: @122373
45482      GIM_Try, /*On fail goto*//*Label 2360*/ 122434, // Rule ID 3124 //
45483        GIM_CheckFeatures, GIFBS_HasMVEFloat,
45484        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
45485        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45486        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
45487        // (fmaxnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)  =>  (MVE_VMAXNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
45488        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45489        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
45490        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
45491        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXNMf32,
45492        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
45493        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
45494        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
45495        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45496        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45497        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45498        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
45499        GIR_EraseFromParent, /*InsnID*/0,
45500        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45501        // GIR_Coverage, 3124,
45502        GIR_Done,
45503      // Label 2360: @122434
45504      GIM_Reject,
45505    // Label 2357: @122435
45506    GIM_Reject,
45507    // Label 2350: @122436
45508    GIM_Try, /*On fail goto*//*Label 2361*/ 122605,
45509      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
45510      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
45511      GIM_Try, /*On fail goto*//*Label 2362*/ 122520, // Rule ID 4218 //
45512        GIM_CheckFeatures, GIFBS_HasMVEInt,
45513        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/1, /*OtherOpIdx*/1,
45514        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45515        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FABS,
45516        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
45517        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45518        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
45519        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FABS,
45520        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
45521        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45522        GIM_CheckIsSafeToFold, /*InsnID*/1,
45523        GIM_CheckIsSafeToFold, /*InsnID*/2,
45524        // (fmaxnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm))  =>  (MVE_VMAXNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm)
45525        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXNMAf16,
45526        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
45527        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
45528        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
45529        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45530        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45531        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45532        GIR_EraseFromParent, /*InsnID*/0,
45533        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45534        // GIR_Coverage, 4218,
45535        GIR_Done,
45536      // Label 2362: @122520
45537      GIM_Try, /*On fail goto*//*Label 2363*/ 122543, // Rule ID 1234 //
45538        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
45539        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
45540        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
45541        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
45542        // (fmaxnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (NEON_VMAXNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
45543        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMAXNMNQh,
45544        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45545        // GIR_Coverage, 1234,
45546        GIR_Done,
45547      // Label 2363: @122543
45548      GIM_Try, /*On fail goto*//*Label 2364*/ 122604, // Rule ID 3379 //
45549        GIM_CheckFeatures, GIFBS_HasMVEFloat,
45550        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
45551        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45552        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
45553        // (fmaxnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)  =>  (MVE_VMAXNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
45554        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45555        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
45556        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
45557        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXNMf16,
45558        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
45559        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
45560        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
45561        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45562        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45563        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45564        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
45565        GIR_EraseFromParent, /*InsnID*/0,
45566        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45567        // GIR_Coverage, 3379,
45568        GIR_Done,
45569      // Label 2364: @122604
45570      GIM_Reject,
45571    // Label 2361: @122605
45572    GIM_Reject,
45573    // Label 2351: @122606
45574    GIM_Reject,
45575    // Label 47: @122607
45576    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2371*/ 123260,
45577    /*GILLT_s16*//*Label 2365*/ 122626,
45578    /*GILLT_s32*//*Label 2366*/ 122839, 0, 0,
45579    /*GILLT_v2s32*//*Label 2367*/ 123052, 0, 0,
45580    /*GILLT_v4s16*//*Label 2368*/ 123104,
45581    /*GILLT_v4s32*//*Label 2369*/ 123156, 0, 0, 0,
45582    /*GILLT_v8s16*//*Label 2370*/ 123208,
45583    // Label 2365: @122626
45584    GIM_Try, /*On fail goto*//*Label 2372*/ 122838, // Rule ID 2722 //
45585      GIM_CheckFeatures, GIFBS_HasFullFP16,
45586      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
45587      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
45588      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
45589      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
45590      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
45591      // (fminimum:{ *:[f16] } HPR:{ *:[f16] }:$a, HPR:{ *:[f16] }:$b)  =>  (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (VMINhd:{ *:[f64] } (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
45592      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16,
45593      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
45594      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
45595      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
45596      GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
45597      GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
45598      GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16,
45599      GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
45600      GIR_BuildMI, /*InsnID*/8, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
45601      GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/RegState::Define,
45602      GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
45603      GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::COPY,
45604      GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define,
45605      GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/0,
45606      GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
45607      GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG,
45608      GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define,
45609      GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0,
45610      GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
45611      GIR_AddImm, /*InsnID*/6, /*Imm*/17,
45612      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, ARM::DPR_VFP2RegClassID,
45613      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, ARM::DPR_VFP2RegClassID,
45614      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, ARM::HPRRegClassID,
45615      GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
45616      GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
45617      GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
45618      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
45619      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
45620      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
45621      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
45622      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
45623      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
45624      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
45625      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
45626      GIR_AddImm, /*InsnID*/3, /*Imm*/17,
45627      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
45628      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
45629      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::HPRRegClassID,
45630      GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VMINhd,
45631      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
45632      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
45633      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/5, /*TempRegFlags*/0,
45634      GIR_AddImm, /*InsnID*/2, /*Imm*/14,
45635      GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45636      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45637      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
45638      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
45639      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
45640      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45641      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
45642      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
45643      GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
45644      GIR_EraseFromParent, /*InsnID*/0,
45645      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
45646      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
45647      // GIR_Coverage, 2722,
45648      GIR_Done,
45649    // Label 2372: @122838
45650    GIM_Reject,
45651    // Label 2366: @122839
45652    GIM_Try, /*On fail goto*//*Label 2373*/ 123051, // Rule ID 2724 //
45653      GIM_CheckFeatures, GIFBS_HasNEON,
45654      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
45655      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
45656      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
45657      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
45658      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
45659      // (fminimum:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMINfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
45660      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
45661      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
45662      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
45663      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
45664      GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
45665      GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
45666      GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
45667      GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
45668      GIR_BuildMI, /*InsnID*/8, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
45669      GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/RegState::Define,
45670      GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
45671      GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::COPY,
45672      GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define,
45673      GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/0,
45674      GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
45675      GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG,
45676      GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define,
45677      GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0,
45678      GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
45679      GIR_AddImm, /*InsnID*/6, /*Imm*/17,
45680      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, ARM::DPR_VFP2RegClassID,
45681      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, ARM::DPR_VFP2RegClassID,
45682      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, ARM::SPRRegClassID,
45683      GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
45684      GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
45685      GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
45686      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
45687      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
45688      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
45689      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
45690      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
45691      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
45692      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
45693      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
45694      GIR_AddImm, /*InsnID*/3, /*Imm*/17,
45695      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
45696      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
45697      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
45698      GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VMINfd,
45699      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
45700      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
45701      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/5, /*TempRegFlags*/0,
45702      GIR_AddImm, /*InsnID*/2, /*Imm*/14,
45703      GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45704      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45705      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
45706      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
45707      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
45708      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45709      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
45710      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
45711      GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
45712      GIR_EraseFromParent, /*InsnID*/0,
45713      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
45714      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
45715      // GIR_Coverage, 2724,
45716      GIR_Done,
45717    // Label 2373: @123051
45718    GIM_Reject,
45719    // Label 2367: @123052
45720    GIM_Try, /*On fail goto*//*Label 2374*/ 123103, // Rule ID 1247 //
45721      GIM_CheckFeatures, GIFBS_HasNEON,
45722      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
45723      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
45724      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
45725      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45726      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
45727      // (fminimum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VMINfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
45728      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINfd,
45729      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45730      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
45731      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
45732      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45733      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45734      GIR_EraseFromParent, /*InsnID*/0,
45735      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45736      // GIR_Coverage, 1247,
45737      GIR_Done,
45738    // Label 2374: @123103
45739    GIM_Reject,
45740    // Label 2368: @123104
45741    GIM_Try, /*On fail goto*//*Label 2375*/ 123155, // Rule ID 1249 //
45742      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
45743      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
45744      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
45745      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
45746      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45747      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
45748      // (fminimum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VMINhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
45749      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINhd,
45750      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45751      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
45752      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
45753      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45754      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45755      GIR_EraseFromParent, /*InsnID*/0,
45756      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45757      // GIR_Coverage, 1249,
45758      GIR_Done,
45759    // Label 2375: @123155
45760    GIM_Reject,
45761    // Label 2369: @123156
45762    GIM_Try, /*On fail goto*//*Label 2376*/ 123207, // Rule ID 1248 //
45763      GIM_CheckFeatures, GIFBS_HasNEON,
45764      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
45765      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
45766      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
45767      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
45768      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
45769      // (fminimum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VMINfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
45770      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINfq,
45771      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45772      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
45773      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
45774      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45775      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45776      GIR_EraseFromParent, /*InsnID*/0,
45777      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45778      // GIR_Coverage, 1248,
45779      GIR_Done,
45780    // Label 2376: @123207
45781    GIM_Reject,
45782    // Label 2370: @123208
45783    GIM_Try, /*On fail goto*//*Label 2377*/ 123259, // Rule ID 1250 //
45784      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
45785      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
45786      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
45787      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
45788      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
45789      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
45790      // (fminimum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VMINhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
45791      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINhq,
45792      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45793      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
45794      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
45795      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45796      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45797      GIR_EraseFromParent, /*InsnID*/0,
45798      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45799      // GIR_Coverage, 1250,
45800      GIR_Done,
45801    // Label 2377: @123259
45802    GIM_Reject,
45803    // Label 2371: @123260
45804    GIM_Reject,
45805    // Label 48: @123261
45806    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2384*/ 123914,
45807    /*GILLT_s16*//*Label 2378*/ 123280,
45808    /*GILLT_s32*//*Label 2379*/ 123493, 0, 0,
45809    /*GILLT_v2s32*//*Label 2380*/ 123706, 0, 0,
45810    /*GILLT_v4s16*//*Label 2381*/ 123758,
45811    /*GILLT_v4s32*//*Label 2382*/ 123810, 0, 0, 0,
45812    /*GILLT_v8s16*//*Label 2383*/ 123862,
45813    // Label 2378: @123280
45814    GIM_Try, /*On fail goto*//*Label 2385*/ 123492, // Rule ID 2721 //
45815      GIM_CheckFeatures, GIFBS_HasFullFP16,
45816      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
45817      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
45818      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
45819      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
45820      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
45821      // (fmaximum:{ *:[f16] } HPR:{ *:[f16] }:$a, HPR:{ *:[f16] }:$b)  =>  (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (VMAXhd:{ *:[f64] } (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
45822      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16,
45823      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
45824      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
45825      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
45826      GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
45827      GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
45828      GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16,
45829      GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
45830      GIR_BuildMI, /*InsnID*/8, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
45831      GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/RegState::Define,
45832      GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
45833      GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::COPY,
45834      GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define,
45835      GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/0,
45836      GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
45837      GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG,
45838      GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define,
45839      GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0,
45840      GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
45841      GIR_AddImm, /*InsnID*/6, /*Imm*/17,
45842      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, ARM::DPR_VFP2RegClassID,
45843      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, ARM::DPR_VFP2RegClassID,
45844      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, ARM::HPRRegClassID,
45845      GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
45846      GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
45847      GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
45848      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
45849      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
45850      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
45851      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
45852      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
45853      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
45854      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
45855      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
45856      GIR_AddImm, /*InsnID*/3, /*Imm*/17,
45857      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
45858      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
45859      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::HPRRegClassID,
45860      GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VMAXhd,
45861      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
45862      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
45863      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/5, /*TempRegFlags*/0,
45864      GIR_AddImm, /*InsnID*/2, /*Imm*/14,
45865      GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45866      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45867      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
45868      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
45869      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
45870      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45871      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
45872      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
45873      GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
45874      GIR_EraseFromParent, /*InsnID*/0,
45875      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
45876      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
45877      // GIR_Coverage, 2721,
45878      GIR_Done,
45879    // Label 2385: @123492
45880    GIM_Reject,
45881    // Label 2379: @123493
45882    GIM_Try, /*On fail goto*//*Label 2386*/ 123705, // Rule ID 2723 //
45883      GIM_CheckFeatures, GIFBS_HasNEON,
45884      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
45885      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
45886      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
45887      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
45888      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
45889      // (fmaximum:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)  =>  (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMAXfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
45890      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
45891      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
45892      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
45893      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
45894      GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
45895      GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
45896      GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
45897      GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
45898      GIR_BuildMI, /*InsnID*/8, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
45899      GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/RegState::Define,
45900      GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
45901      GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::COPY,
45902      GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define,
45903      GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/0,
45904      GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
45905      GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG,
45906      GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define,
45907      GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0,
45908      GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
45909      GIR_AddImm, /*InsnID*/6, /*Imm*/17,
45910      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, ARM::DPR_VFP2RegClassID,
45911      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, ARM::DPR_VFP2RegClassID,
45912      GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, ARM::SPRRegClassID,
45913      GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
45914      GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
45915      GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
45916      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
45917      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
45918      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
45919      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
45920      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
45921      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
45922      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
45923      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
45924      GIR_AddImm, /*InsnID*/3, /*Imm*/17,
45925      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
45926      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
45927      GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
45928      GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VMAXfd,
45929      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
45930      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
45931      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/5, /*TempRegFlags*/0,
45932      GIR_AddImm, /*InsnID*/2, /*Imm*/14,
45933      GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45934      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45935      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
45936      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
45937      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
45938      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45939      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
45940      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
45941      GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
45942      GIR_EraseFromParent, /*InsnID*/0,
45943      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
45944      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
45945      // GIR_Coverage, 2723,
45946      GIR_Done,
45947    // Label 2386: @123705
45948    GIM_Reject,
45949    // Label 2380: @123706
45950    GIM_Try, /*On fail goto*//*Label 2387*/ 123757, // Rule ID 1227 //
45951      GIM_CheckFeatures, GIFBS_HasNEON,
45952      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
45953      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
45954      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
45955      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45956      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
45957      // (fmaximum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VMAXfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
45958      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXfd,
45959      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45960      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
45961      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
45962      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45963      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45964      GIR_EraseFromParent, /*InsnID*/0,
45965      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45966      // GIR_Coverage, 1227,
45967      GIR_Done,
45968    // Label 2387: @123757
45969    GIM_Reject,
45970    // Label 2381: @123758
45971    GIM_Try, /*On fail goto*//*Label 2388*/ 123809, // Rule ID 1229 //
45972      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
45973      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
45974      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
45975      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
45976      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45977      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
45978      // (fmaximum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VMAXhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
45979      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXhd,
45980      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45981      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
45982      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
45983      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45984      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45985      GIR_EraseFromParent, /*InsnID*/0,
45986      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45987      // GIR_Coverage, 1229,
45988      GIR_Done,
45989    // Label 2388: @123809
45990    GIM_Reject,
45991    // Label 2382: @123810
45992    GIM_Try, /*On fail goto*//*Label 2389*/ 123861, // Rule ID 1228 //
45993      GIM_CheckFeatures, GIFBS_HasNEON,
45994      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
45995      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
45996      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
45997      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
45998      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
45999      // (fmaximum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VMAXfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
46000      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXfq,
46001      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46002      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46003      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46004      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46005      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46006      GIR_EraseFromParent, /*InsnID*/0,
46007      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46008      // GIR_Coverage, 1228,
46009      GIR_Done,
46010    // Label 2389: @123861
46011    GIM_Reject,
46012    // Label 2383: @123862
46013    GIM_Try, /*On fail goto*//*Label 2390*/ 123913, // Rule ID 1230 //
46014      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
46015      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
46016      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
46017      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
46018      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
46019      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
46020      // (fmaximum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VMAXhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
46021      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXhq,
46022      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46023      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46024      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46025      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46026      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46027      GIR_EraseFromParent, /*InsnID*/0,
46028      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46029      // GIR_Coverage, 1230,
46030      GIR_Done,
46031    // Label 2390: @123913
46032    GIM_Reject,
46033    // Label 2384: @123914
46034    GIM_Reject,
46035    // Label 49: @123915
46036    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 16, /*)*//*default:*//*Label 2397*/ 124437,
46037    /*GILLT_v2s32*//*Label 2391*/ 123933, 0, 0,
46038    /*GILLT_v4s16*//*Label 2392*/ 123985,
46039    /*GILLT_v4s32*//*Label 2393*/ 124037, 0, 0,
46040    /*GILLT_v8s8*//*Label 2394*/ 124153,
46041    /*GILLT_v8s16*//*Label 2395*/ 124205, 0, 0,
46042    /*GILLT_v16s8*//*Label 2396*/ 124321,
46043    // Label 2391: @123933
46044    GIM_Try, /*On fail goto*//*Label 2398*/ 123984, // Rule ID 1236 //
46045      GIM_CheckFeatures, GIFBS_HasNEON,
46046      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
46047      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
46048      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
46049      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
46050      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
46051      // (smin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VMINsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
46052      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv2i32,
46053      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46054      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46055      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46056      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46057      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46058      GIR_EraseFromParent, /*InsnID*/0,
46059      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46060      // GIR_Coverage, 1236,
46061      GIR_Done,
46062    // Label 2398: @123984
46063    GIM_Reject,
46064    // Label 2392: @123985
46065    GIM_Try, /*On fail goto*//*Label 2399*/ 124036, // Rule ID 1235 //
46066      GIM_CheckFeatures, GIFBS_HasNEON,
46067      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
46068      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
46069      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
46070      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
46071      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
46072      // (smin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VMINsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
46073      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv4i16,
46074      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46075      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46076      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46077      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46078      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46079      GIR_EraseFromParent, /*InsnID*/0,
46080      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46081      // GIR_Coverage, 1235,
46082      GIR_Done,
46083    // Label 2399: @124036
46084    GIM_Reject,
46085    // Label 2393: @124037
46086    GIM_Try, /*On fail goto*//*Label 2400*/ 124152,
46087      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
46088      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
46089      GIM_Try, /*On fail goto*//*Label 2401*/ 124090, // Rule ID 1238 //
46090        GIM_CheckFeatures, GIFBS_HasNEON,
46091        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
46092        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
46093        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
46094        // (smin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VMINsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
46095        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv4i32,
46096        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46097        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46098        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46099        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46100        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46101        GIR_EraseFromParent, /*InsnID*/0,
46102        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46103        // GIR_Coverage, 1238,
46104        GIR_Done,
46105      // Label 2401: @124090
46106      GIM_Try, /*On fail goto*//*Label 2402*/ 124151, // Rule ID 3394 //
46107        GIM_CheckFeatures, GIFBS_HasMVEInt,
46108        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
46109        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46110        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
46111        // (smin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VMINs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
46112        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46113        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
46114        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
46115        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINs32,
46116        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
46117        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
46118        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
46119        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46120        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46121        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46122        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
46123        GIR_EraseFromParent, /*InsnID*/0,
46124        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46125        // GIR_Coverage, 3394,
46126        GIR_Done,
46127      // Label 2402: @124151
46128      GIM_Reject,
46129    // Label 2400: @124152
46130    GIM_Reject,
46131    // Label 2394: @124153
46132    GIM_Try, /*On fail goto*//*Label 2403*/ 124204, // Rule ID 1239 //
46133      GIM_CheckFeatures, GIFBS_HasNEON,
46134      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
46135      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
46136      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
46137      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
46138      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
46139      // (smin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMINsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
46140      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv8i8,
46141      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46142      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46143      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46144      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46145      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46146      GIR_EraseFromParent, /*InsnID*/0,
46147      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46148      // GIR_Coverage, 1239,
46149      GIR_Done,
46150    // Label 2403: @124204
46151    GIM_Reject,
46152    // Label 2395: @124205
46153    GIM_Try, /*On fail goto*//*Label 2404*/ 124320,
46154      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
46155      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
46156      GIM_Try, /*On fail goto*//*Label 2405*/ 124258, // Rule ID 1237 //
46157        GIM_CheckFeatures, GIFBS_HasNEON,
46158        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
46159        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
46160        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
46161        // (smin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VMINsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
46162        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv8i16,
46163        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46164        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46165        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46166        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46167        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46168        GIR_EraseFromParent, /*InsnID*/0,
46169        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46170        // GIR_Coverage, 1237,
46171        GIR_Done,
46172      // Label 2405: @124258
46173      GIM_Try, /*On fail goto*//*Label 2406*/ 124319, // Rule ID 3391 //
46174        GIM_CheckFeatures, GIFBS_HasMVEInt,
46175        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
46176        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46177        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
46178        // (smin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VMINs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
46179        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46180        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
46181        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
46182        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINs16,
46183        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
46184        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
46185        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
46186        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46187        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46188        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46189        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
46190        GIR_EraseFromParent, /*InsnID*/0,
46191        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46192        // GIR_Coverage, 3391,
46193        GIR_Done,
46194      // Label 2406: @124319
46195      GIM_Reject,
46196    // Label 2404: @124320
46197    GIM_Reject,
46198    // Label 2396: @124321
46199    GIM_Try, /*On fail goto*//*Label 2407*/ 124436,
46200      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
46201      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
46202      GIM_Try, /*On fail goto*//*Label 2408*/ 124374, // Rule ID 1240 //
46203        GIM_CheckFeatures, GIFBS_HasNEON,
46204        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
46205        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
46206        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
46207        // (smin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMINsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
46208        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv16i8,
46209        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46212        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46213        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46214        GIR_EraseFromParent, /*InsnID*/0,
46215        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46216        // GIR_Coverage, 1240,
46217        GIR_Done,
46218      // Label 2408: @124374
46219      GIM_Try, /*On fail goto*//*Label 2409*/ 124435, // Rule ID 3388 //
46220        GIM_CheckFeatures, GIFBS_HasMVEInt,
46221        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
46222        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46223        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
46224        // (smin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VMINs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
46225        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46226        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
46227        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
46228        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINs8,
46229        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
46230        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
46231        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
46232        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46233        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46234        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46235        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
46236        GIR_EraseFromParent, /*InsnID*/0,
46237        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46238        // GIR_Coverage, 3388,
46239        GIR_Done,
46240      // Label 2409: @124435
46241      GIM_Reject,
46242    // Label 2407: @124436
46243    GIM_Reject,
46244    // Label 2397: @124437
46245    GIM_Reject,
46246    // Label 50: @124438
46247    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 16, /*)*//*default:*//*Label 2416*/ 124960,
46248    /*GILLT_v2s32*//*Label 2410*/ 124456, 0, 0,
46249    /*GILLT_v4s16*//*Label 2411*/ 124508,
46250    /*GILLT_v4s32*//*Label 2412*/ 124560, 0, 0,
46251    /*GILLT_v8s8*//*Label 2413*/ 124676,
46252    /*GILLT_v8s16*//*Label 2414*/ 124728, 0, 0,
46253    /*GILLT_v16s8*//*Label 2415*/ 124844,
46254    // Label 2410: @124456
46255    GIM_Try, /*On fail goto*//*Label 2417*/ 124507, // Rule ID 1216 //
46256      GIM_CheckFeatures, GIFBS_HasNEON,
46257      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
46258      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
46259      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
46260      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
46261      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
46262      // (smax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VMAXsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
46263      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv2i32,
46264      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46265      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46266      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46267      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46268      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46269      GIR_EraseFromParent, /*InsnID*/0,
46270      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46271      // GIR_Coverage, 1216,
46272      GIR_Done,
46273    // Label 2417: @124507
46274    GIM_Reject,
46275    // Label 2411: @124508
46276    GIM_Try, /*On fail goto*//*Label 2418*/ 124559, // Rule ID 1215 //
46277      GIM_CheckFeatures, GIFBS_HasNEON,
46278      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
46279      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
46280      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
46281      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
46282      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
46283      // (smax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VMAXsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
46284      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv4i16,
46285      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46286      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46287      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46288      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46289      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46290      GIR_EraseFromParent, /*InsnID*/0,
46291      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46292      // GIR_Coverage, 1215,
46293      GIR_Done,
46294    // Label 2418: @124559
46295    GIM_Reject,
46296    // Label 2412: @124560
46297    GIM_Try, /*On fail goto*//*Label 2419*/ 124675,
46298      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
46299      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
46300      GIM_Try, /*On fail goto*//*Label 2420*/ 124613, // Rule ID 1218 //
46301        GIM_CheckFeatures, GIFBS_HasNEON,
46302        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
46303        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
46304        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
46305        // (smax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VMAXsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
46306        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv4i32,
46307        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46308        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46309        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46310        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46311        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46312        GIR_EraseFromParent, /*InsnID*/0,
46313        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46314        // GIR_Coverage, 1218,
46315        GIR_Done,
46316      // Label 2420: @124613
46317      GIM_Try, /*On fail goto*//*Label 2421*/ 124674, // Rule ID 3412 //
46318        GIM_CheckFeatures, GIFBS_HasMVEInt,
46319        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
46320        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46321        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
46322        // (smax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VMAXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
46323        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46324        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
46325        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
46326        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXs32,
46327        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
46328        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
46329        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
46330        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46331        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46332        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46333        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
46334        GIR_EraseFromParent, /*InsnID*/0,
46335        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46336        // GIR_Coverage, 3412,
46337        GIR_Done,
46338      // Label 2421: @124674
46339      GIM_Reject,
46340    // Label 2419: @124675
46341    GIM_Reject,
46342    // Label 2413: @124676
46343    GIM_Try, /*On fail goto*//*Label 2422*/ 124727, // Rule ID 1219 //
46344      GIM_CheckFeatures, GIFBS_HasNEON,
46345      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
46346      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
46347      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
46348      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
46349      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
46350      // (smax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMAXsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
46351      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv8i8,
46352      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46353      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46354      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46355      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46356      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46357      GIR_EraseFromParent, /*InsnID*/0,
46358      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46359      // GIR_Coverage, 1219,
46360      GIR_Done,
46361    // Label 2422: @124727
46362    GIM_Reject,
46363    // Label 2414: @124728
46364    GIM_Try, /*On fail goto*//*Label 2423*/ 124843,
46365      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
46366      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
46367      GIM_Try, /*On fail goto*//*Label 2424*/ 124781, // Rule ID 1217 //
46368        GIM_CheckFeatures, GIFBS_HasNEON,
46369        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
46370        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
46371        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
46372        // (smax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VMAXsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
46373        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv8i16,
46374        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46375        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46376        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46377        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46378        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46379        GIR_EraseFromParent, /*InsnID*/0,
46380        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46381        // GIR_Coverage, 1217,
46382        GIR_Done,
46383      // Label 2424: @124781
46384      GIM_Try, /*On fail goto*//*Label 2425*/ 124842, // Rule ID 3409 //
46385        GIM_CheckFeatures, GIFBS_HasMVEInt,
46386        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
46387        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46388        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
46389        // (smax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VMAXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
46390        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46391        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
46392        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
46393        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXs16,
46394        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
46395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
46396        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
46397        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46398        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46399        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46400        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
46401        GIR_EraseFromParent, /*InsnID*/0,
46402        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46403        // GIR_Coverage, 3409,
46404        GIR_Done,
46405      // Label 2425: @124842
46406      GIM_Reject,
46407    // Label 2423: @124843
46408    GIM_Reject,
46409    // Label 2415: @124844
46410    GIM_Try, /*On fail goto*//*Label 2426*/ 124959,
46411      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
46412      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
46413      GIM_Try, /*On fail goto*//*Label 2427*/ 124897, // Rule ID 1220 //
46414        GIM_CheckFeatures, GIFBS_HasNEON,
46415        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
46416        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
46417        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
46418        // (smax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMAXsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
46419        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv16i8,
46420        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46421        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46422        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46423        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46424        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46425        GIR_EraseFromParent, /*InsnID*/0,
46426        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46427        // GIR_Coverage, 1220,
46428        GIR_Done,
46429      // Label 2427: @124897
46430      GIM_Try, /*On fail goto*//*Label 2428*/ 124958, // Rule ID 3406 //
46431        GIM_CheckFeatures, GIFBS_HasMVEInt,
46432        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
46433        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46434        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
46435        // (smax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VMAXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
46436        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46437        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
46438        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
46439        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXs8,
46440        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
46441        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
46442        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
46443        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46444        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46445        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46446        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
46447        GIR_EraseFromParent, /*InsnID*/0,
46448        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46449        // GIR_Coverage, 3406,
46450        GIR_Done,
46451      // Label 2428: @124958
46452      GIM_Reject,
46453    // Label 2426: @124959
46454    GIM_Reject,
46455    // Label 2416: @124960
46456    GIM_Reject,
46457    // Label 51: @124961
46458    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 16, /*)*//*default:*//*Label 2435*/ 125849,
46459    /*GILLT_v2s32*//*Label 2429*/ 124979, 0, 0,
46460    /*GILLT_v4s16*//*Label 2430*/ 125031,
46461    /*GILLT_v4s32*//*Label 2431*/ 125083, 0, 0,
46462    /*GILLT_v8s8*//*Label 2432*/ 125321,
46463    /*GILLT_v8s16*//*Label 2433*/ 125373, 0, 0,
46464    /*GILLT_v16s8*//*Label 2434*/ 125611,
46465    // Label 2429: @124979
46466    GIM_Try, /*On fail goto*//*Label 2436*/ 125030, // Rule ID 1242 //
46467      GIM_CheckFeatures, GIFBS_HasNEON,
46468      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
46469      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
46470      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
46471      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
46472      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
46473      // (umin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VMINuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
46474      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv2i32,
46475      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46476      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46477      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46478      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46479      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46480      GIR_EraseFromParent, /*InsnID*/0,
46481      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46482      // GIR_Coverage, 1242,
46483      GIR_Done,
46484    // Label 2436: @125030
46485    GIM_Reject,
46486    // Label 2430: @125031
46487    GIM_Try, /*On fail goto*//*Label 2437*/ 125082, // Rule ID 1241 //
46488      GIM_CheckFeatures, GIFBS_HasNEON,
46489      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
46490      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
46491      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
46492      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
46493      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
46494      // (umin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VMINuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
46495      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv4i16,
46496      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46497      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46498      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46499      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46500      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46501      GIR_EraseFromParent, /*InsnID*/0,
46502      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46503      // GIR_Coverage, 1241,
46504      GIR_Done,
46505    // Label 2437: @125082
46506    GIM_Reject,
46507    // Label 2431: @125083
46508    GIM_Try, /*On fail goto*//*Label 2438*/ 125320,
46509      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
46510      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
46511      GIM_Try, /*On fail goto*//*Label 2439*/ 125154, // Rule ID 6142 //
46512        GIM_CheckFeatures, GIFBS_HasMVEInt,
46513        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
46514        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46515        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
46516        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
46517        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46518        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
46519        GIM_CheckIsSafeToFold, /*InsnID*/1,
46520        // (umin:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd)  =>  (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
46521        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINAs32,
46522        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
46523        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
46524        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
46525        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46526        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46527        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46528        GIR_EraseFromParent, /*InsnID*/0,
46529        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46530        // GIR_Coverage, 6142,
46531        GIR_Done,
46532      // Label 2439: @125154
46533      GIM_Try, /*On fail goto*//*Label 2440*/ 125215, // Rule ID 3809 //
46534        GIM_CheckFeatures, GIFBS_HasMVEInt,
46535        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
46536        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46537        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
46538        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
46539        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
46540        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46541        GIM_CheckIsSafeToFold, /*InsnID*/1,
46542        // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm))  =>  (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
46543        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINAs32,
46544        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
46545        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
46546        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
46547        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46548        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46549        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46550        GIR_EraseFromParent, /*InsnID*/0,
46551        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46552        // GIR_Coverage, 3809,
46553        GIR_Done,
46554      // Label 2440: @125215
46555      GIM_Try, /*On fail goto*//*Label 2441*/ 125258, // Rule ID 1244 //
46556        GIM_CheckFeatures, GIFBS_HasNEON,
46557        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
46558        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
46559        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
46560        // (umin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VMINuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
46561        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv4i32,
46562        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46563        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46564        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46565        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46566        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46567        GIR_EraseFromParent, /*InsnID*/0,
46568        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46569        // GIR_Coverage, 1244,
46570        GIR_Done,
46571      // Label 2441: @125258
46572      GIM_Try, /*On fail goto*//*Label 2442*/ 125319, // Rule ID 3403 //
46573        GIM_CheckFeatures, GIFBS_HasMVEInt,
46574        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
46575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46576        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
46577        // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VMINu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
46578        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46579        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
46580        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
46581        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINu32,
46582        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
46583        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
46584        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
46585        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46586        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46587        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46588        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
46589        GIR_EraseFromParent, /*InsnID*/0,
46590        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46591        // GIR_Coverage, 3403,
46592        GIR_Done,
46593      // Label 2442: @125319
46594      GIM_Reject,
46595    // Label 2438: @125320
46596    GIM_Reject,
46597    // Label 2432: @125321
46598    GIM_Try, /*On fail goto*//*Label 2443*/ 125372, // Rule ID 1245 //
46599      GIM_CheckFeatures, GIFBS_HasNEON,
46600      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
46601      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
46602      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
46603      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
46604      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
46605      // (umin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMINuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
46606      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv8i8,
46607      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46608      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46609      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46610      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46611      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46612      GIR_EraseFromParent, /*InsnID*/0,
46613      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46614      // GIR_Coverage, 1245,
46615      GIR_Done,
46616    // Label 2443: @125372
46617    GIM_Reject,
46618    // Label 2433: @125373
46619    GIM_Try, /*On fail goto*//*Label 2444*/ 125610,
46620      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
46621      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
46622      GIM_Try, /*On fail goto*//*Label 2445*/ 125444, // Rule ID 6141 //
46623        GIM_CheckFeatures, GIFBS_HasMVEInt,
46624        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
46625        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46626        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
46627        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
46628        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46629        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
46630        GIM_CheckIsSafeToFold, /*InsnID*/1,
46631        // (umin:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd)  =>  (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
46632        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINAs16,
46633        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
46634        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
46635        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
46636        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46637        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46638        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46639        GIR_EraseFromParent, /*InsnID*/0,
46640        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46641        // GIR_Coverage, 6141,
46642        GIR_Done,
46643      // Label 2445: @125444
46644      GIM_Try, /*On fail goto*//*Label 2446*/ 125505, // Rule ID 3807 //
46645        GIM_CheckFeatures, GIFBS_HasMVEInt,
46646        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
46647        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46648        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
46649        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
46650        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
46651        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46652        GIM_CheckIsSafeToFold, /*InsnID*/1,
46653        // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm))  =>  (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
46654        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINAs16,
46655        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
46656        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
46657        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
46658        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46659        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46660        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46661        GIR_EraseFromParent, /*InsnID*/0,
46662        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46663        // GIR_Coverage, 3807,
46664        GIR_Done,
46665      // Label 2446: @125505
46666      GIM_Try, /*On fail goto*//*Label 2447*/ 125548, // Rule ID 1243 //
46667        GIM_CheckFeatures, GIFBS_HasNEON,
46668        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
46669        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
46670        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
46671        // (umin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VMINuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
46672        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv8i16,
46673        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46674        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46675        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46676        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46677        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46678        GIR_EraseFromParent, /*InsnID*/0,
46679        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46680        // GIR_Coverage, 1243,
46681        GIR_Done,
46682      // Label 2447: @125548
46683      GIM_Try, /*On fail goto*//*Label 2448*/ 125609, // Rule ID 3400 //
46684        GIM_CheckFeatures, GIFBS_HasMVEInt,
46685        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
46686        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46687        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
46688        // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VMINu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
46689        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46690        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
46691        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
46692        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINu16,
46693        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
46694        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
46695        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
46696        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46697        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46698        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46699        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
46700        GIR_EraseFromParent, /*InsnID*/0,
46701        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46702        // GIR_Coverage, 3400,
46703        GIR_Done,
46704      // Label 2448: @125609
46705      GIM_Reject,
46706    // Label 2444: @125610
46707    GIM_Reject,
46708    // Label 2434: @125611
46709    GIM_Try, /*On fail goto*//*Label 2449*/ 125848,
46710      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
46711      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
46712      GIM_Try, /*On fail goto*//*Label 2450*/ 125682, // Rule ID 6140 //
46713        GIM_CheckFeatures, GIFBS_HasMVEInt,
46714        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
46715        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46716        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
46717        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
46718        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46719        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
46720        GIM_CheckIsSafeToFold, /*InsnID*/1,
46721        // (umin:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd)  =>  (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
46722        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINAs8,
46723        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
46724        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
46725        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
46726        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46727        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46728        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46729        GIR_EraseFromParent, /*InsnID*/0,
46730        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46731        // GIR_Coverage, 6140,
46732        GIR_Done,
46733      // Label 2450: @125682
46734      GIM_Try, /*On fail goto*//*Label 2451*/ 125743, // Rule ID 3805 //
46735        GIM_CheckFeatures, GIFBS_HasMVEInt,
46736        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
46737        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46738        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
46739        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
46740        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
46741        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46742        GIM_CheckIsSafeToFold, /*InsnID*/1,
46743        // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm))  =>  (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
46744        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINAs8,
46745        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
46746        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
46747        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
46748        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46749        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46750        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46751        GIR_EraseFromParent, /*InsnID*/0,
46752        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46753        // GIR_Coverage, 3805,
46754        GIR_Done,
46755      // Label 2451: @125743
46756      GIM_Try, /*On fail goto*//*Label 2452*/ 125786, // Rule ID 1246 //
46757        GIM_CheckFeatures, GIFBS_HasNEON,
46758        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
46759        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
46760        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
46761        // (umin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMINuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
46762        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv16i8,
46763        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46764        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46765        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46766        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46767        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46768        GIR_EraseFromParent, /*InsnID*/0,
46769        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46770        // GIR_Coverage, 1246,
46771        GIR_Done,
46772      // Label 2452: @125786
46773      GIM_Try, /*On fail goto*//*Label 2453*/ 125847, // Rule ID 3397 //
46774        GIM_CheckFeatures, GIFBS_HasMVEInt,
46775        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
46776        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46777        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
46778        // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VMINu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
46779        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46780        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
46781        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
46782        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINu8,
46783        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
46784        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
46785        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
46786        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46787        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46788        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46789        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
46790        GIR_EraseFromParent, /*InsnID*/0,
46791        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46792        // GIR_Coverage, 3397,
46793        GIR_Done,
46794      // Label 2453: @125847
46795      GIM_Reject,
46796    // Label 2449: @125848
46797    GIM_Reject,
46798    // Label 2435: @125849
46799    GIM_Reject,
46800    // Label 52: @125850
46801    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 16, /*)*//*default:*//*Label 2460*/ 126738,
46802    /*GILLT_v2s32*//*Label 2454*/ 125868, 0, 0,
46803    /*GILLT_v4s16*//*Label 2455*/ 125920,
46804    /*GILLT_v4s32*//*Label 2456*/ 125972, 0, 0,
46805    /*GILLT_v8s8*//*Label 2457*/ 126210,
46806    /*GILLT_v8s16*//*Label 2458*/ 126262, 0, 0,
46807    /*GILLT_v16s8*//*Label 2459*/ 126500,
46808    // Label 2454: @125868
46809    GIM_Try, /*On fail goto*//*Label 2461*/ 125919, // Rule ID 1222 //
46810      GIM_CheckFeatures, GIFBS_HasNEON,
46811      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
46812      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
46813      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
46814      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
46815      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
46816      // (umax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VMAXuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
46817      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv2i32,
46818      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46819      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46820      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46821      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46822      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46823      GIR_EraseFromParent, /*InsnID*/0,
46824      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46825      // GIR_Coverage, 1222,
46826      GIR_Done,
46827    // Label 2461: @125919
46828    GIM_Reject,
46829    // Label 2455: @125920
46830    GIM_Try, /*On fail goto*//*Label 2462*/ 125971, // Rule ID 1221 //
46831      GIM_CheckFeatures, GIFBS_HasNEON,
46832      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
46833      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
46834      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
46835      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
46836      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
46837      // (umax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VMAXuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
46838      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv4i16,
46839      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46840      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46841      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46842      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46843      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46844      GIR_EraseFromParent, /*InsnID*/0,
46845      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46846      // GIR_Coverage, 1221,
46847      GIR_Done,
46848    // Label 2462: @125971
46849    GIM_Reject,
46850    // Label 2456: @125972
46851    GIM_Try, /*On fail goto*//*Label 2463*/ 126209,
46852      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
46853      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
46854      GIM_Try, /*On fail goto*//*Label 2464*/ 126043, // Rule ID 6145 //
46855        GIM_CheckFeatures, GIFBS_HasMVEInt,
46856        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
46857        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46858        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
46859        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
46860        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46861        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
46862        GIM_CheckIsSafeToFold, /*InsnID*/1,
46863        // (umax:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd)  =>  (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
46864        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXAs32,
46865        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
46866        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
46867        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
46868        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46869        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46870        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46871        GIR_EraseFromParent, /*InsnID*/0,
46872        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46873        // GIR_Coverage, 6145,
46874        GIR_Done,
46875      // Label 2464: @126043
46876      GIM_Try, /*On fail goto*//*Label 2465*/ 126104, // Rule ID 3815 //
46877        GIM_CheckFeatures, GIFBS_HasMVEInt,
46878        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
46879        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46880        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
46881        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
46882        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
46883        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46884        GIM_CheckIsSafeToFold, /*InsnID*/1,
46885        // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm))  =>  (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
46886        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXAs32,
46887        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
46888        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
46889        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
46890        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46891        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46892        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46893        GIR_EraseFromParent, /*InsnID*/0,
46894        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46895        // GIR_Coverage, 3815,
46896        GIR_Done,
46897      // Label 2465: @126104
46898      GIM_Try, /*On fail goto*//*Label 2466*/ 126147, // Rule ID 1224 //
46899        GIM_CheckFeatures, GIFBS_HasNEON,
46900        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
46901        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
46902        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
46903        // (umax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VMAXuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
46904        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv4i32,
46905        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46906        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46907        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46908        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46909        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46910        GIR_EraseFromParent, /*InsnID*/0,
46911        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46912        // GIR_Coverage, 1224,
46913        GIR_Done,
46914      // Label 2466: @126147
46915      GIM_Try, /*On fail goto*//*Label 2467*/ 126208, // Rule ID 3421 //
46916        GIM_CheckFeatures, GIFBS_HasMVEInt,
46917        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
46918        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46919        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
46920        // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)  =>  (MVE_VMAXu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
46921        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46922        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
46923        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
46924        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXu32,
46925        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
46926        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
46927        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
46928        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46929        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46930        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46931        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
46932        GIR_EraseFromParent, /*InsnID*/0,
46933        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46934        // GIR_Coverage, 3421,
46935        GIR_Done,
46936      // Label 2467: @126208
46937      GIM_Reject,
46938    // Label 2463: @126209
46939    GIM_Reject,
46940    // Label 2457: @126210
46941    GIM_Try, /*On fail goto*//*Label 2468*/ 126261, // Rule ID 1225 //
46942      GIM_CheckFeatures, GIFBS_HasNEON,
46943      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
46944      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
46945      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
46946      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
46947      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
46948      // (umax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMAXuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
46949      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv8i8,
46950      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
46951      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
46952      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
46953      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46954      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46955      GIR_EraseFromParent, /*InsnID*/0,
46956      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46957      // GIR_Coverage, 1225,
46958      GIR_Done,
46959    // Label 2468: @126261
46960    GIM_Reject,
46961    // Label 2458: @126262
46962    GIM_Try, /*On fail goto*//*Label 2469*/ 126499,
46963      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
46964      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
46965      GIM_Try, /*On fail goto*//*Label 2470*/ 126333, // Rule ID 6144 //
46966        GIM_CheckFeatures, GIFBS_HasMVEInt,
46967        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
46968        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46969        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
46970        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
46971        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46972        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
46973        GIM_CheckIsSafeToFold, /*InsnID*/1,
46974        // (umax:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd)  =>  (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
46975        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXAs16,
46976        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
46977        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
46978        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
46979        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46980        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46981        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46982        GIR_EraseFromParent, /*InsnID*/0,
46983        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46984        // GIR_Coverage, 6144,
46985        GIR_Done,
46986      // Label 2470: @126333
46987      GIM_Try, /*On fail goto*//*Label 2471*/ 126394, // Rule ID 3813 //
46988        GIM_CheckFeatures, GIFBS_HasMVEInt,
46989        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
46990        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46991        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
46992        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
46993        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
46994        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46995        GIM_CheckIsSafeToFold, /*InsnID*/1,
46996        // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm))  =>  (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
46997        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXAs16,
46998        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
46999        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
47000        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47001        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
47002        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47003        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47004        GIR_EraseFromParent, /*InsnID*/0,
47005        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47006        // GIR_Coverage, 3813,
47007        GIR_Done,
47008      // Label 2471: @126394
47009      GIM_Try, /*On fail goto*//*Label 2472*/ 126437, // Rule ID 1223 //
47010        GIM_CheckFeatures, GIFBS_HasNEON,
47011        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
47012        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
47013        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
47014        // (umax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VMAXuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
47015        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv8i16,
47016        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
47017        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
47018        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
47019        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47020        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47021        GIR_EraseFromParent, /*InsnID*/0,
47022        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47023        // GIR_Coverage, 1223,
47024        GIR_Done,
47025      // Label 2472: @126437
47026      GIM_Try, /*On fail goto*//*Label 2473*/ 126498, // Rule ID 3418 //
47027        GIM_CheckFeatures, GIFBS_HasMVEInt,
47028        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
47029        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
47030        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
47031        // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)  =>  (MVE_VMAXu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
47032        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47033        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
47034        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
47035        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXu16,
47036        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
47037        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
47038        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
47039        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
47040        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47041        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47042        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
47043        GIR_EraseFromParent, /*InsnID*/0,
47044        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47045        // GIR_Coverage, 3418,
47046        GIR_Done,
47047      // Label 2473: @126498
47048      GIM_Reject,
47049    // Label 2469: @126499
47050    GIM_Reject,
47051    // Label 2459: @126500
47052    GIM_Try, /*On fail goto*//*Label 2474*/ 126737,
47053      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
47054      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
47055      GIM_Try, /*On fail goto*//*Label 2475*/ 126571, // Rule ID 6143 //
47056        GIM_CheckFeatures, GIFBS_HasMVEInt,
47057        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
47058        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47059        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
47060        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
47061        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
47062        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
47063        GIM_CheckIsSafeToFold, /*InsnID*/1,
47064        // (umax:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd)  =>  (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
47065        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXAs8,
47066        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
47067        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
47068        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47069        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
47070        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47071        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47072        GIR_EraseFromParent, /*InsnID*/0,
47073        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47074        // GIR_Coverage, 6143,
47075        GIR_Done,
47076      // Label 2475: @126571
47077      GIM_Try, /*On fail goto*//*Label 2476*/ 126632, // Rule ID 3811 //
47078        GIM_CheckFeatures, GIFBS_HasMVEInt,
47079        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
47080        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
47081        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47082        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
47083        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
47084        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
47085        GIM_CheckIsSafeToFold, /*InsnID*/1,
47086        // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm))  =>  (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
47087        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXAs8,
47088        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
47089        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
47090        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47091        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
47092        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47093        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47094        GIR_EraseFromParent, /*InsnID*/0,
47095        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47096        // GIR_Coverage, 3811,
47097        GIR_Done,
47098      // Label 2476: @126632
47099      GIM_Try, /*On fail goto*//*Label 2477*/ 126675, // Rule ID 1226 //
47100        GIM_CheckFeatures, GIFBS_HasNEON,
47101        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
47102        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
47103        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
47104        // (umax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMAXuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
47105        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv16i8,
47106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
47107        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
47108        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
47109        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47110        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47111        GIR_EraseFromParent, /*InsnID*/0,
47112        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47113        // GIR_Coverage, 1226,
47114        GIR_Done,
47115      // Label 2477: @126675
47116      GIM_Try, /*On fail goto*//*Label 2478*/ 126736, // Rule ID 3415 //
47117        GIM_CheckFeatures, GIFBS_HasMVEInt,
47118        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
47119        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
47120        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
47121        // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)  =>  (MVE_VMAXu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
47122        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47123        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
47124        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
47125        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXu8,
47126        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
47127        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
47128        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
47129        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
47130        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47131        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47132        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
47133        GIR_EraseFromParent, /*InsnID*/0,
47134        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47135        // GIR_Coverage, 3415,
47136        GIR_Done,
47137      // Label 2478: @126736
47138      GIM_Reject,
47139    // Label 2474: @126737
47140    GIM_Reject,
47141    // Label 2460: @126738
47142    GIM_Reject,
47143    // Label 53: @126739
47144    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 16, /*)*//*default:*//*Label 2485*/ 127167,
47145    /*GILLT_v2s32*//*Label 2479*/ 126757, 0, 0,
47146    /*GILLT_v4s16*//*Label 2480*/ 126797,
47147    /*GILLT_v4s32*//*Label 2481*/ 126837, 0, 0,
47148    /*GILLT_v8s8*//*Label 2482*/ 126962,
47149    /*GILLT_v8s16*//*Label 2483*/ 127002, 0, 0,
47150    /*GILLT_v16s8*//*Label 2484*/ 127127,
47151    // Label 2479: @126757
47152    GIM_Try, /*On fail goto*//*Label 2486*/ 126796, // Rule ID 1528 //
47153      GIM_CheckFeatures, GIFBS_HasNEON,
47154      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
47155      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
47156      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
47157      // (abs:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)  =>  (VABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
47158      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSv2i32,
47159      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
47160      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47161      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47162      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47163      GIR_EraseFromParent, /*InsnID*/0,
47164      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47165      // GIR_Coverage, 1528,
47166      GIR_Done,
47167    // Label 2486: @126796
47168    GIM_Reject,
47169    // Label 2480: @126797
47170    GIM_Try, /*On fail goto*//*Label 2487*/ 126836, // Rule ID 1527 //
47171      GIM_CheckFeatures, GIFBS_HasNEON,
47172      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
47173      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
47174      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
47175      // (abs:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)  =>  (VABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
47176      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSv4i16,
47177      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
47178      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47179      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47180      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47181      GIR_EraseFromParent, /*InsnID*/0,
47182      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47183      // GIR_Coverage, 1527,
47184      GIR_Done,
47185    // Label 2487: @126836
47186    GIM_Reject,
47187    // Label 2481: @126837
47188    GIM_Try, /*On fail goto*//*Label 2488*/ 126961,
47189      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
47190      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
47191      GIM_Try, /*On fail goto*//*Label 2489*/ 126929, // Rule ID 2573 //
47192        GIM_CheckFeatures, GIFBS_HasNEON,
47193        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47194        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
47195        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
47196        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
47197        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
47198        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
47199        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
47200        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
47201        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
47202        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
47203        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s16,
47204        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::DPRRegClassID,
47205        GIM_CheckIsSafeToFold, /*InsnID*/1,
47206        GIM_CheckIsSafeToFold, /*InsnID*/2,
47207        GIM_CheckIsSafeToFold, /*InsnID*/3,
47208        // (abs:{ *:[v4i32] } (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$opA), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$opB)))  =>  (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$opA, DPR:{ *:[v4i16] }:$opB)
47209        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLuv4i32,
47210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
47211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // opA
47212        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // opB
47213        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47214        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47215        GIR_EraseFromParent, /*InsnID*/0,
47216        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47217        // GIR_Coverage, 2573,
47218        GIR_Done,
47219      // Label 2489: @126929
47220      GIM_Try, /*On fail goto*//*Label 2490*/ 126960, // Rule ID 1531 //
47221        GIM_CheckFeatures, GIFBS_HasNEON,
47222        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
47223        // (abs:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)  =>  (VABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
47224        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSv4i32,
47225        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
47226        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47227        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47228        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47229        GIR_EraseFromParent, /*InsnID*/0,
47230        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47231        // GIR_Coverage, 1531,
47232        GIR_Done,
47233      // Label 2490: @126960
47234      GIM_Reject,
47235    // Label 2488: @126961
47236    GIM_Reject,
47237    // Label 2482: @126962
47238    GIM_Try, /*On fail goto*//*Label 2491*/ 127001, // Rule ID 1526 //
47239      GIM_CheckFeatures, GIFBS_HasNEON,
47240      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
47241      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
47242      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
47243      // (abs:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)  =>  (VABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
47244      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSv8i8,
47245      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
47246      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47247      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47248      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47249      GIR_EraseFromParent, /*InsnID*/0,
47250      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47251      // GIR_Coverage, 1526,
47252      GIR_Done,
47253    // Label 2491: @127001
47254    GIM_Reject,
47255    // Label 2483: @127002
47256    GIM_Try, /*On fail goto*//*Label 2492*/ 127126,
47257      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
47258      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
47259      GIM_Try, /*On fail goto*//*Label 2493*/ 127094, // Rule ID 2572 //
47260        GIM_CheckFeatures, GIFBS_HasNEON,
47261        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47262        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
47263        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
47264        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
47265        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
47266        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
47267        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
47268        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
47269        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
47270        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
47271        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s8,
47272        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::DPRRegClassID,
47273        GIM_CheckIsSafeToFold, /*InsnID*/1,
47274        GIM_CheckIsSafeToFold, /*InsnID*/2,
47275        GIM_CheckIsSafeToFold, /*InsnID*/3,
47276        // (abs:{ *:[v8i16] } (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$opA), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$opB)))  =>  (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$opA, DPR:{ *:[v8i8] }:$opB)
47277        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLuv8i16,
47278        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
47279        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // opA
47280        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // opB
47281        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47282        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47283        GIR_EraseFromParent, /*InsnID*/0,
47284        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47285        // GIR_Coverage, 2572,
47286        GIR_Done,
47287      // Label 2493: @127094
47288      GIM_Try, /*On fail goto*//*Label 2494*/ 127125, // Rule ID 1530 //
47289        GIM_CheckFeatures, GIFBS_HasNEON,
47290        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
47291        // (abs:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)  =>  (VABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
47292        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSv8i16,
47293        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
47294        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47295        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47296        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47297        GIR_EraseFromParent, /*InsnID*/0,
47298        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47299        // GIR_Coverage, 1530,
47300        GIR_Done,
47301      // Label 2494: @127125
47302      GIM_Reject,
47303    // Label 2492: @127126
47304    GIM_Reject,
47305    // Label 2484: @127127
47306    GIM_Try, /*On fail goto*//*Label 2495*/ 127166, // Rule ID 1529 //
47307      GIM_CheckFeatures, GIFBS_HasNEON,
47308      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
47309      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
47310      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
47311      // (abs:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)  =>  (VABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
47312      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSv16i8,
47313      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
47314      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47315      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47316      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47317      GIR_EraseFromParent, /*InsnID*/0,
47318      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47319      // GIR_Coverage, 1529,
47320      GIR_Done,
47321    // Label 2495: @127166
47322    GIM_Reject,
47323    // Label 2485: @127167
47324    GIM_Reject,
47325    // Label 54: @127168
47326    GIM_Try, /*On fail goto*//*Label 2496*/ 127231,
47327      GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
47328      GIM_Try, /*On fail goto*//*Label 2497*/ 127184, // Rule ID 32 //
47329        GIM_CheckFeatures, GIFBS_IsARM,
47330        // (br (bb:{ *:[Other] }):$target)  =>  (B (bb:{ *:[Other] }):$target)
47331        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::B,
47332        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47333        // GIR_Coverage, 32,
47334        GIR_Done,
47335      // Label 2497: @127184
47336      GIM_Try, /*On fail goto*//*Label 2498*/ 127207, // Rule ID 290 //
47337        GIM_CheckFeatures, GIFBS_IsThumb_IsThumb1Only,
47338        // (br (bb:{ *:[Other] }):$target)  =>  (tB (bb:{ *:[Other] }):$target)
47339        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tB,
47340        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // target
47341        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47342        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47343        GIR_EraseFromParent, /*InsnID*/0,
47344        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47345        // GIR_Coverage, 290,
47346        GIR_Done,
47347      // Label 2498: @127207
47348      GIM_Try, /*On fail goto*//*Label 2499*/ 127230, // Rule ID 593 //
47349        GIM_CheckFeatures, GIFBS_HasV8MBaseline_IsThumb,
47350        // (br (bb:{ *:[Other] }):$target)  =>  (t2B (bb:{ *:[Other] }):$target)
47351        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2B,
47352        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // target
47353        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47354        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47355        GIR_EraseFromParent, /*InsnID*/0,
47356        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47357        // GIR_Coverage, 593,
47358        GIR_Done,
47359      // Label 2499: @127230
47360      GIM_Reject,
47361    // Label 2496: @127231
47362    GIM_Reject,
47363    // Label 55: @127232
47364    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 2502*/ 127373,
47365    /*GILLT_s16*//*Label 2500*/ 127240,
47366    /*GILLT_s32*//*Label 2501*/ 127317,
47367    // Label 2500: @127240
47368    GIM_Try, /*On fail goto*//*Label 2503*/ 127316, // Rule ID 2631 //
47369      GIM_CheckFeatures, GIFBS_HasBF16_HasNEON,
47370      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
47371      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
47372      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
47373      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
47374      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47375      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
47376      GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm_odd,
47377      // MIs[1] Operand 1
47378      // No operand predicates
47379      GIM_CheckIsSafeToFold, /*InsnID*/1,
47380      // (extractelt:{ *:[bf16] } DPR:{ *:[v4bf16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm_odd>>:$lane)  =>  (COPY_TO_REGCLASS:{ *:[bf16] } (VGETLNu16:{ *:[i32] } DPR:{ *:[v4bf16] }:$src, (imm:{ *:[i32] }):$lane), HPR:{ *:[i32] })
47381      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47382      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VGETLNu16,
47383      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
47384      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
47385      GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // lane
47386      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
47387      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47388      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47389      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
47390      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
47391      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
47392      GIR_EraseFromParent, /*InsnID*/0,
47393      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::HPRRegClassID,
47394      // GIR_Coverage, 2631,
47395      GIR_Done,
47396    // Label 2503: @127316
47397    GIM_Reject,
47398    // Label 2501: @127317
47399    GIM_Try, /*On fail goto*//*Label 2504*/ 127372, // Rule ID 1588 //
47400      GIM_CheckFeatures, GIFBS_HasFPRegs_HasFastVGETLNi32,
47401      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
47402      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
47403      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
47404      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
47405      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47406      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
47407      // MIs[1] Operand 1
47408      // No operand predicates
47409      GIM_CheckIsSafeToFold, /*InsnID*/1,
47410      // (extractelt:{ *:[i32] } DPR:{ *:[v2i32] }:$V, (imm:{ *:[i32] }):$lane)  =>  (VGETLNi32:{ *:[i32] } DPR:{ *:[v2i32] }:$V, (imm:{ *:[i32] }):$lane)
47411      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VGETLNi32,
47412      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // R
47413      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // V
47414      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane
47415      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47416      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47417      GIR_EraseFromParent, /*InsnID*/0,
47418      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47419      // GIR_Coverage, 1588,
47420      GIR_Done,
47421    // Label 2504: @127372
47422    GIM_Reject,
47423    // Label 2502: @127373
47424    GIM_Reject,
47425    // Label 56: @127374
47426    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 16, /*)*//*default:*//*Label 2512*/ 127881,
47427    /*GILLT_s32*//*Label 2505*/ 127395, 0, 0,
47428    /*GILLT_v2s32*//*Label 2506*/ 127473, 0, 0,
47429    /*GILLT_v4s16*//*Label 2507*/ 127513,
47430    /*GILLT_v4s32*//*Label 2508*/ 127553, 0, 0,
47431    /*GILLT_v8s8*//*Label 2509*/ 127649,
47432    /*GILLT_v8s16*//*Label 2510*/ 127689, 0, 0,
47433    /*GILLT_v16s8*//*Label 2511*/ 127785,
47434    // Label 2505: @127395
47435    GIM_Try, /*On fail goto*//*Label 2513*/ 127472,
47436      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
47437      GIM_Try, /*On fail goto*//*Label 2514*/ 127436, // Rule ID 197 //
47438        GIM_CheckFeatures, GIFBS_HasV5T_IsARM,
47439        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
47440        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
47441        // (ctlz:{ *:[i32] } GPR:{ *:[i32] }:$Rm)  =>  (CLZ:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
47442        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CLZ,
47443        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
47444        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
47445        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47446        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47447        GIR_EraseFromParent, /*InsnID*/0,
47448        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47449        // GIR_Coverage, 197,
47450        GIR_Done,
47451      // Label 2514: @127436
47452      GIM_Try, /*On fail goto*//*Label 2515*/ 127471, // Rule ID 541 //
47453        GIM_CheckFeatures, GIFBS_IsThumb2,
47454        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
47455        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
47456        // (ctlz:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)  =>  (t2CLZ:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
47457        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CLZ,
47458        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
47459        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
47460        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47461        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47462        GIR_EraseFromParent, /*InsnID*/0,
47463        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47464        // GIR_Coverage, 541,
47465        GIR_Done,
47466      // Label 2515: @127471
47467      GIM_Reject,
47468    // Label 2513: @127472
47469    GIM_Reject,
47470    // Label 2506: @127473
47471    GIM_Try, /*On fail goto*//*Label 2516*/ 127512, // Rule ID 1566 //
47472      GIM_CheckFeatures, GIFBS_HasNEON,
47473      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
47474      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
47475      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
47476      // (ctlz:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)  =>  (VCLZv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
47477      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv2i32,
47478      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
47479      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47480      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47481      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47482      GIR_EraseFromParent, /*InsnID*/0,
47483      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47484      // GIR_Coverage, 1566,
47485      GIR_Done,
47486    // Label 2516: @127512
47487    GIM_Reject,
47488    // Label 2507: @127513
47489    GIM_Try, /*On fail goto*//*Label 2517*/ 127552, // Rule ID 1565 //
47490      GIM_CheckFeatures, GIFBS_HasNEON,
47491      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
47492      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
47493      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
47494      // (ctlz:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)  =>  (VCLZv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
47495      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv4i16,
47496      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
47497      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47498      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47499      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47500      GIR_EraseFromParent, /*InsnID*/0,
47501      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47502      // GIR_Coverage, 1565,
47503      GIR_Done,
47504    // Label 2517: @127552
47505    GIM_Reject,
47506    // Label 2508: @127553
47507    GIM_Try, /*On fail goto*//*Label 2518*/ 127648,
47508      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
47509      GIM_Try, /*On fail goto*//*Label 2519*/ 127594, // Rule ID 1569 //
47510        GIM_CheckFeatures, GIFBS_HasNEON,
47511        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
47512        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
47513        // (ctlz:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)  =>  (VCLZv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
47514        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv4i32,
47515        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
47516        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47517        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47518        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47519        GIR_EraseFromParent, /*InsnID*/0,
47520        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47521        // GIR_Coverage, 1569,
47522        GIR_Done,
47523      // Label 2519: @127594
47524      GIM_Try, /*On fail goto*//*Label 2520*/ 127647, // Rule ID 3770 //
47525        GIM_CheckFeatures, GIFBS_HasMVEInt,
47526        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
47527        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
47528        // (ctlz:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val)  =>  (MVE_VCLZs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val)
47529        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47530        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
47531        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
47532        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCLZs32,
47533        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
47534        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
47535        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
47536        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47537        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47538        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
47539        GIR_EraseFromParent, /*InsnID*/0,
47540        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47541        // GIR_Coverage, 3770,
47542        GIR_Done,
47543      // Label 2520: @127647
47544      GIM_Reject,
47545    // Label 2518: @127648
47546    GIM_Reject,
47547    // Label 2509: @127649
47548    GIM_Try, /*On fail goto*//*Label 2521*/ 127688, // Rule ID 1564 //
47549      GIM_CheckFeatures, GIFBS_HasNEON,
47550      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
47551      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
47552      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
47553      // (ctlz:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)  =>  (VCLZv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
47554      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv8i8,
47555      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
47556      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47557      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47558      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47559      GIR_EraseFromParent, /*InsnID*/0,
47560      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47561      // GIR_Coverage, 1564,
47562      GIR_Done,
47563    // Label 2521: @127688
47564    GIM_Reject,
47565    // Label 2510: @127689
47566    GIM_Try, /*On fail goto*//*Label 2522*/ 127784,
47567      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
47568      GIM_Try, /*On fail goto*//*Label 2523*/ 127730, // Rule ID 1568 //
47569        GIM_CheckFeatures, GIFBS_HasNEON,
47570        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
47571        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
47572        // (ctlz:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)  =>  (VCLZv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
47573        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv8i16,
47574        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
47575        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47576        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47577        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47578        GIR_EraseFromParent, /*InsnID*/0,
47579        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47580        // GIR_Coverage, 1568,
47581        GIR_Done,
47582      // Label 2523: @127730
47583      GIM_Try, /*On fail goto*//*Label 2524*/ 127783, // Rule ID 3768 //
47584        GIM_CheckFeatures, GIFBS_HasMVEInt,
47585        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
47586        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
47587        // (ctlz:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val)  =>  (MVE_VCLZs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val)
47588        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47589        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
47590        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
47591        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCLZs16,
47592        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
47593        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
47594        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
47595        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47596        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47597        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
47598        GIR_EraseFromParent, /*InsnID*/0,
47599        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47600        // GIR_Coverage, 3768,
47601        GIR_Done,
47602      // Label 2524: @127783
47603      GIM_Reject,
47604    // Label 2522: @127784
47605    GIM_Reject,
47606    // Label 2511: @127785
47607    GIM_Try, /*On fail goto*//*Label 2525*/ 127880,
47608      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
47609      GIM_Try, /*On fail goto*//*Label 2526*/ 127826, // Rule ID 1567 //
47610        GIM_CheckFeatures, GIFBS_HasNEON,
47611        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
47612        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
47613        // (ctlz:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)  =>  (VCLZv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
47614        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv16i8,
47615        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
47616        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47617        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47618        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47619        GIR_EraseFromParent, /*InsnID*/0,
47620        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47621        // GIR_Coverage, 1567,
47622        GIR_Done,
47623      // Label 2526: @127826
47624      GIM_Try, /*On fail goto*//*Label 2527*/ 127879, // Rule ID 3766 //
47625        GIM_CheckFeatures, GIFBS_HasMVEInt,
47626        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
47627        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
47628        // (ctlz:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val)  =>  (MVE_VCLZs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val)
47629        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47630        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
47631        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
47632        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCLZs8,
47633        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
47634        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
47635        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
47636        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47637        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47638        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
47639        GIR_EraseFromParent, /*InsnID*/0,
47640        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47641        // GIR_Coverage, 3766,
47642        GIR_Done,
47643      // Label 2527: @127879
47644      GIM_Reject,
47645    // Label 2525: @127880
47646    GIM_Reject,
47647    // Label 2512: @127881
47648    GIM_Reject,
47649    // Label 57: @127882
47650    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/11, 16, /*)*//*default:*//*Label 2530*/ 127973,
47651    /*GILLT_v8s8*//*Label 2528*/ 127893, 0, 0, 0,
47652    /*GILLT_v16s8*//*Label 2529*/ 127933,
47653    // Label 2528: @127893
47654    GIM_Try, /*On fail goto*//*Label 2531*/ 127932, // Rule ID 1570 //
47655      GIM_CheckFeatures, GIFBS_HasNEON,
47656      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
47657      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
47658      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
47659      // (ctpop:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)  =>  (VCNTd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
47660      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCNTd,
47661      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
47662      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47663      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47664      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47665      GIR_EraseFromParent, /*InsnID*/0,
47666      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47667      // GIR_Coverage, 1570,
47668      GIR_Done,
47669    // Label 2531: @127932
47670    GIM_Reject,
47671    // Label 2529: @127933
47672    GIM_Try, /*On fail goto*//*Label 2532*/ 127972, // Rule ID 1571 //
47673      GIM_CheckFeatures, GIFBS_HasNEON,
47674      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
47675      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
47676      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
47677      // (ctpop:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)  =>  (VCNTq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
47678      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCNTq,
47679      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
47680      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
47681      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47682      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47683      GIR_EraseFromParent, /*InsnID*/0,
47684      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47685      // GIR_Coverage, 1571,
47686      GIR_Done,
47687    // Label 2532: @127972
47688    GIM_Reject,
47689    // Label 2530: @127973
47690    GIM_Reject,
47691    // Label 58: @127974
47692    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 13, /*)*//*default:*//*Label 2536*/ 128221,
47693    /*GILLT_s32*//*Label 2533*/ 127992, 0, 0, 0, 0, 0, 0,
47694    /*GILLT_v4s32*//*Label 2534*/ 128105, 0, 0, 0,
47695    /*GILLT_v8s16*//*Label 2535*/ 128163,
47696    // Label 2533: @127992
47697    GIM_Try, /*On fail goto*//*Label 2537*/ 128104,
47698      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
47699      GIM_Try, /*On fail goto*//*Label 2538*/ 128033, // Rule ID 199 //
47700        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
47701        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
47702        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
47703        // (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm)  =>  (REV:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
47704        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REV,
47705        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
47706        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
47707        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47708        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47709        GIR_EraseFromParent, /*InsnID*/0,
47710        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47711        // GIR_Coverage, 199,
47712        GIR_Done,
47713      // Label 2538: @128033
47714      GIM_Try, /*On fail goto*//*Label 2539*/ 128068, // Rule ID 333 //
47715        GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only,
47716        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID,
47717        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::tGPRRegClassID,
47718        // (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)  =>  (tREV:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
47719        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tREV,
47720        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
47721        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
47722        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47723        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47724        GIR_EraseFromParent, /*InsnID*/0,
47725        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47726        // GIR_Coverage, 333,
47727        GIR_Done,
47728      // Label 2539: @128068
47729      GIM_Try, /*On fail goto*//*Label 2540*/ 128103, // Rule ID 543 //
47730        GIM_CheckFeatures, GIFBS_IsThumb2,
47731        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
47732        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
47733        // (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)  =>  (t2REV:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
47734        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REV,
47735        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
47736        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
47737        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47738        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47739        GIR_EraseFromParent, /*InsnID*/0,
47740        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47741        // GIR_Coverage, 543,
47742        GIR_Done,
47743      // Label 2540: @128103
47744      GIM_Reject,
47745    // Label 2537: @128104
47746    GIM_Reject,
47747    // Label 2534: @128105
47748    GIM_Try, /*On fail goto*//*Label 2541*/ 128162, // Rule ID 3425 //
47749      GIM_CheckFeatures, GIFBS_HasMVEInt,
47750      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
47751      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
47752      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
47753      // (bswap:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src)  =>  (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src)
47754      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47755      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
47756      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
47757      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8,
47758      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
47759      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
47760      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
47761      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47762      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47763      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
47764      GIR_EraseFromParent, /*InsnID*/0,
47765      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47766      // GIR_Coverage, 3425,
47767      GIR_Done,
47768    // Label 2541: @128162
47769    GIM_Reject,
47770    // Label 2535: @128163
47771    GIM_Try, /*On fail goto*//*Label 2542*/ 128220, // Rule ID 3424 //
47772      GIM_CheckFeatures, GIFBS_HasMVEInt,
47773      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
47774      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
47775      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
47776      // (bswap:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src)  =>  (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src)
47777      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47778      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
47779      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
47780      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8,
47781      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
47782      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
47783      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
47784      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47785      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47786      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
47787      GIR_EraseFromParent, /*InsnID*/0,
47788      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47789      // GIR_Coverage, 3424,
47790      GIR_Done,
47791    // Label 2542: @128220
47792    GIM_Reject,
47793    // Label 2536: @128221
47794    GIM_Reject,
47795    // Label 59: @128222
47796    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 16, /*)*//*default:*//*Label 2547*/ 128585,
47797    /*GILLT_s32*//*Label 2543*/ 128243, 0, 0, 0, 0, 0, 0,
47798    /*GILLT_v4s32*//*Label 2544*/ 128321, 0, 0, 0,
47799    /*GILLT_v8s16*//*Label 2545*/ 128409, 0, 0,
47800    /*GILLT_v16s8*//*Label 2546*/ 128497,
47801    // Label 2543: @128243
47802    GIM_Try, /*On fail goto*//*Label 2548*/ 128320,
47803      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
47804      GIM_Try, /*On fail goto*//*Label 2549*/ 128284, // Rule ID 198 //
47805        GIM_CheckFeatures, GIFBS_HasV6T2_IsARM,
47806        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
47807        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
47808        // (bitreverse:{ *:[i32] } GPR:{ *:[i32] }:$Rm)  =>  (RBIT:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
47809        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::RBIT,
47810        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
47811        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
47812        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47813        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47814        GIR_EraseFromParent, /*InsnID*/0,
47815        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47816        // GIR_Coverage, 198,
47817        GIR_Done,
47818      // Label 2549: @128284
47819      GIM_Try, /*On fail goto*//*Label 2550*/ 128319, // Rule ID 542 //
47820        GIM_CheckFeatures, GIFBS_IsThumb2,
47821        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
47822        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
47823        // (bitreverse:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)  =>  (t2RBIT:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
47824        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2RBIT,
47825        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
47826        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
47827        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
47828        GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47829        GIR_EraseFromParent, /*InsnID*/0,
47830        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47831        // GIR_Coverage, 542,
47832        GIR_Done,
47833      // Label 2550: @128319
47834      GIM_Reject,
47835    // Label 2548: @128320
47836    GIM_Reject,
47837    // Label 2544: @128321
47838    GIM_Try, /*On fail goto*//*Label 2551*/ 128408, // Rule ID 4856 //
47839      GIM_CheckFeatures, GIFBS_HasMVEInt,
47840      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
47841      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
47842      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
47843      // (bitreverse:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1)  =>  (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1, (t2MOVi:{ *:[i32] } 32:{ *:[i32] }))
47844      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47845      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
47846      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
47847      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/0,
47848      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2MOVi,
47849      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
47850      GIR_AddImm, /*InsnID*/1, /*Imm*/32,
47851      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
47852      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47853      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47854      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47855      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR32,
47856      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
47857      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
47858      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
47859      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
47860      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47861      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47862      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
47863      GIR_EraseFromParent, /*InsnID*/0,
47864      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47865      // GIR_Coverage, 4856,
47866      GIR_Done,
47867    // Label 2551: @128408
47868    GIM_Reject,
47869    // Label 2545: @128409
47870    GIM_Try, /*On fail goto*//*Label 2552*/ 128496, // Rule ID 4857 //
47871      GIM_CheckFeatures, GIFBS_HasMVEInt,
47872      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
47873      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
47874      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
47875      // (bitreverse:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1)  =>  (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1, (t2MOVi:{ *:[i32] } 16:{ *:[i32] }))
47876      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47877      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
47878      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
47879      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/0,
47880      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2MOVi,
47881      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
47882      GIR_AddImm, /*InsnID*/1, /*Imm*/16,
47883      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
47884      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47885      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47886      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47887      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR16,
47888      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
47889      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
47890      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
47891      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
47892      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47893      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47894      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
47895      GIR_EraseFromParent, /*InsnID*/0,
47896      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47897      // GIR_Coverage, 4857,
47898      GIR_Done,
47899    // Label 2552: @128496
47900    GIM_Reject,
47901    // Label 2546: @128497
47902    GIM_Try, /*On fail goto*//*Label 2553*/ 128584, // Rule ID 4855 //
47903      GIM_CheckFeatures, GIFBS_HasMVEInt,
47904      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
47905      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
47906      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
47907      // (bitreverse:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1)  =>  (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1, (t2MOVi:{ *:[i32] } 8:{ *:[i32] }))
47908      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47909      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
47910      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
47911      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/0,
47912      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2MOVi,
47913      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
47914      GIR_AddImm, /*InsnID*/1, /*Imm*/8,
47915      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
47916      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47917      GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47918      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47919      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR8,
47920      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
47921      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
47922      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
47923      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
47924      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47925      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47926      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
47927      GIR_EraseFromParent, /*InsnID*/0,
47928      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47929      // GIR_Coverage, 4855,
47930      GIR_Done,
47931    // Label 2553: @128584
47932    GIM_Reject,
47933    // Label 2547: @128585
47934    GIM_Reject,
47935    // Label 60: @128586
47936    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2559*/ 128793,
47937    /*GILLT_s16*//*Label 2554*/ 128605,
47938    /*GILLT_s32*//*Label 2555*/ 128629,
47939    /*GILLT_s64*//*Label 2556*/ 128653, 0, 0, 0, 0, 0,
47940    /*GILLT_v4s32*//*Label 2557*/ 128677, 0, 0, 0,
47941    /*GILLT_v8s16*//*Label 2558*/ 128735,
47942    // Label 2554: @128605
47943    GIM_Try, /*On fail goto*//*Label 2560*/ 128628, // Rule ID 696 //
47944      GIM_CheckFeatures, GIFBS_HasFullFP16,
47945      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
47946      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
47947      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
47948      // (fceil:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VRINTPH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
47949      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTPH,
47950      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47951      // GIR_Coverage, 696,
47952      GIR_Done,
47953    // Label 2560: @128628
47954    GIM_Reject,
47955    // Label 2555: @128629
47956    GIM_Try, /*On fail goto*//*Label 2561*/ 128652, // Rule ID 697 //
47957      GIM_CheckFeatures, GIFBS_HasFPARMv8,
47958      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
47959      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
47960      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
47961      // (fceil:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VRINTPS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
47962      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTPS,
47963      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47964      // GIR_Coverage, 697,
47965      GIR_Done,
47966    // Label 2561: @128652
47967    GIM_Reject,
47968    // Label 2556: @128653
47969    GIM_Try, /*On fail goto*//*Label 2562*/ 128676, // Rule ID 698 //
47970      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
47971      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
47972      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
47973      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
47974      // (fceil:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VRINTPD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
47975      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTPD,
47976      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
47977      // GIR_Coverage, 698,
47978      GIR_Done,
47979    // Label 2562: @128676
47980    GIM_Reject,
47981    // Label 2557: @128677
47982    GIM_Try, /*On fail goto*//*Label 2563*/ 128734, // Rule ID 4086 //
47983      GIM_CheckFeatures, GIFBS_HasMVEFloat,
47984      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
47985      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
47986      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
47987      // (fceil:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)  =>  (MVE_VRINTf32P:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
47988      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47989      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
47990      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
47991      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32P,
47992      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
47993      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
47994      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
47995      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47996      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
47997      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
47998      GIR_EraseFromParent, /*InsnID*/0,
47999      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48000      // GIR_Coverage, 4086,
48001      GIR_Done,
48002    // Label 2563: @128734
48003    GIM_Reject,
48004    // Label 2558: @128735
48005    GIM_Try, /*On fail goto*//*Label 2564*/ 128792, // Rule ID 4074 //
48006      GIM_CheckFeatures, GIFBS_HasMVEFloat,
48007      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
48008      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
48009      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
48010      // (fceil:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)  =>  (MVE_VRINTf16P:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
48011      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48012      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
48013      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
48014      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16P,
48015      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
48016      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
48017      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
48018      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
48019      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
48020      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
48021      GIR_EraseFromParent, /*InsnID*/0,
48022      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48023      // GIR_Coverage, 4074,
48024      GIR_Done,
48025    // Label 2564: @128792
48026    GIM_Reject,
48027    // Label 2559: @128793
48028    GIM_Reject,
48029    // Label 61: @128794
48030    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 2568*/ 128923,
48031    /*GILLT_s16*//*Label 2565*/ 128803,
48032    /*GILLT_s32*//*Label 2566*/ 128843,
48033    /*GILLT_s64*//*Label 2567*/ 128883,
48034    // Label 2565: @128803
48035    GIM_Try, /*On fail goto*//*Label 2569*/ 128842, // Rule ID 704 //
48036      GIM_CheckFeatures, GIFBS_HasFullFP16,
48037      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
48038      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
48039      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
48040      // (fsqrt:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VSQRTH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
48041      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSQRTH,
48042      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
48043      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
48044      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
48045      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
48046      GIR_EraseFromParent, /*InsnID*/0,
48047      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48048      // GIR_Coverage, 704,
48049      GIR_Done,
48050    // Label 2569: @128842
48051    GIM_Reject,
48052    // Label 2566: @128843
48053    GIM_Try, /*On fail goto*//*Label 2570*/ 128882, // Rule ID 703 //
48054      GIM_CheckFeatures, GIFBS_HasVFP2,
48055      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
48056      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
48057      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
48058      // (fsqrt:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VSQRTS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
48059      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSQRTS,
48060      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
48061      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
48062      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
48063      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
48064      GIR_EraseFromParent, /*InsnID*/0,
48065      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48066      // GIR_Coverage, 703,
48067      GIR_Done,
48068    // Label 2570: @128882
48069    GIM_Reject,
48070    // Label 2567: @128883
48071    GIM_Try, /*On fail goto*//*Label 2571*/ 128922, // Rule ID 702 //
48072      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
48073      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
48074      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
48075      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
48076      // (fsqrt:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VSQRTD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
48077      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSQRTD,
48078      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
48079      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
48080      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
48081      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
48082      GIR_EraseFromParent, /*InsnID*/0,
48083      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48084      // GIR_Coverage, 702,
48085      GIR_Done,
48086    // Label 2571: @128922
48087    GIM_Reject,
48088    // Label 2568: @128923
48089    GIM_Reject,
48090    // Label 62: @128924
48091    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2577*/ 129131,
48092    /*GILLT_s16*//*Label 2572*/ 128943,
48093    /*GILLT_s32*//*Label 2573*/ 128967,
48094    /*GILLT_s64*//*Label 2574*/ 128991, 0, 0, 0, 0, 0,
48095    /*GILLT_v4s32*//*Label 2575*/ 129015, 0, 0, 0,
48096    /*GILLT_v8s16*//*Label 2576*/ 129073,
48097    // Label 2572: @128943
48098    GIM_Try, /*On fail goto*//*Label 2578*/ 128966, // Rule ID 699 //
48099      GIM_CheckFeatures, GIFBS_HasFullFP16,
48100      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
48101      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
48102      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
48103      // (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VRINTMH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
48104      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTMH,
48105      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48106      // GIR_Coverage, 699,
48107      GIR_Done,
48108    // Label 2578: @128966
48109    GIM_Reject,
48110    // Label 2573: @128967
48111    GIM_Try, /*On fail goto*//*Label 2579*/ 128990, // Rule ID 700 //
48112      GIM_CheckFeatures, GIFBS_HasFPARMv8,
48113      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
48114      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
48115      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
48116      // (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VRINTMS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
48117      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTMS,
48118      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48119      // GIR_Coverage, 700,
48120      GIR_Done,
48121    // Label 2579: @128990
48122    GIM_Reject,
48123    // Label 2574: @128991
48124    GIM_Try, /*On fail goto*//*Label 2580*/ 129014, // Rule ID 701 //
48125      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
48126      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
48127      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
48128      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
48129      // (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VRINTMD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
48130      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTMD,
48131      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48132      // GIR_Coverage, 701,
48133      GIR_Done,
48134    // Label 2580: @129014
48135    GIM_Reject,
48136    // Label 2575: @129015
48137    GIM_Try, /*On fail goto*//*Label 2581*/ 129072, // Rule ID 4084 //
48138      GIM_CheckFeatures, GIFBS_HasMVEFloat,
48139      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
48140      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
48141      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
48142      // (ffloor:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)  =>  (MVE_VRINTf32M:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
48143      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48144      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
48145      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
48146      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32M,
48147      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
48148      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
48149      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
48150      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
48151      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
48152      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
48153      GIR_EraseFromParent, /*InsnID*/0,
48154      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48155      // GIR_Coverage, 4084,
48156      GIR_Done,
48157    // Label 2581: @129072
48158    GIM_Reject,
48159    // Label 2576: @129073
48160    GIM_Try, /*On fail goto*//*Label 2582*/ 129130, // Rule ID 4072 //
48161      GIM_CheckFeatures, GIFBS_HasMVEFloat,
48162      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
48163      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
48164      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
48165      // (ffloor:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)  =>  (MVE_VRINTf16M:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
48166      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48167      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
48168      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
48169      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16M,
48170      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
48171      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
48172      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
48173      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
48174      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
48175      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
48176      GIR_EraseFromParent, /*InsnID*/0,
48177      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48178      // GIR_Coverage, 4072,
48179      GIR_Done,
48180    // Label 2582: @129130
48181    GIM_Reject,
48182    // Label 2577: @129131
48183    GIM_Reject,
48184    // Label 63: @129132
48185    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2588*/ 129387,
48186    /*GILLT_s16*//*Label 2583*/ 129151,
48187    /*GILLT_s32*//*Label 2584*/ 129191,
48188    /*GILLT_s64*//*Label 2585*/ 129231, 0, 0, 0, 0, 0,
48189    /*GILLT_v4s32*//*Label 2586*/ 129271, 0, 0, 0,
48190    /*GILLT_v8s16*//*Label 2587*/ 129329,
48191    // Label 2583: @129151
48192    GIM_Try, /*On fail goto*//*Label 2589*/ 129190, // Rule ID 687 //
48193      GIM_CheckFeatures, GIFBS_HasFullFP16,
48194      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
48195      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
48196      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
48197      // (frint:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VRINTXH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
48198      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXH,
48199      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
48200      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
48201      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
48202      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
48203      GIR_EraseFromParent, /*InsnID*/0,
48204      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48205      // GIR_Coverage, 687,
48206      GIR_Done,
48207    // Label 2589: @129190
48208    GIM_Reject,
48209    // Label 2584: @129191
48210    GIM_Try, /*On fail goto*//*Label 2590*/ 129230, // Rule ID 688 //
48211      GIM_CheckFeatures, GIFBS_HasFPARMv8,
48212      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
48213      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
48214      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
48215      // (frint:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VRINTXS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
48216      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXS,
48217      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
48218      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
48219      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
48220      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
48221      GIR_EraseFromParent, /*InsnID*/0,
48222      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48223      // GIR_Coverage, 688,
48224      GIR_Done,
48225    // Label 2590: @129230
48226    GIM_Reject,
48227    // Label 2585: @129231
48228    GIM_Try, /*On fail goto*//*Label 2591*/ 129270, // Rule ID 689 //
48229      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
48230      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
48231      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
48232      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
48233      // (frint:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VRINTXD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
48234      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXD,
48235      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
48236      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
48237      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
48238      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
48239      GIR_EraseFromParent, /*InsnID*/0,
48240      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48241      // GIR_Coverage, 689,
48242      GIR_Done,
48243    // Label 2591: @129270
48244    GIM_Reject,
48245    // Label 2586: @129271
48246    GIM_Try, /*On fail goto*//*Label 2592*/ 129328, // Rule ID 4078 //
48247      GIM_CheckFeatures, GIFBS_HasMVEFloat,
48248      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
48249      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
48250      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
48251      // (frint:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)  =>  (MVE_VRINTf32X:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
48252      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48253      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
48254      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
48255      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32X,
48256      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
48257      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
48258      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
48259      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
48260      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
48261      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
48262      GIR_EraseFromParent, /*InsnID*/0,
48263      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48264      // GIR_Coverage, 4078,
48265      GIR_Done,
48266    // Label 2592: @129328
48267    GIM_Reject,
48268    // Label 2587: @129329
48269    GIM_Try, /*On fail goto*//*Label 2593*/ 129386, // Rule ID 4066 //
48270      GIM_CheckFeatures, GIFBS_HasMVEFloat,
48271      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
48272      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
48273      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
48274      // (frint:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)  =>  (MVE_VRINTf16X:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
48275      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48276      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
48277      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
48278      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16X,
48279      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
48280      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
48281      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
48282      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
48283      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
48284      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
48285      GIR_EraseFromParent, /*InsnID*/0,
48286      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48287      // GIR_Coverage, 4066,
48288      GIR_Done,
48289    // Label 2593: @129386
48290    GIM_Reject,
48291    // Label 2588: @129387
48292    GIM_Reject,
48293    // Label 64: @129388
48294    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 2597*/ 129517,
48295    /*GILLT_s16*//*Label 2594*/ 129397,
48296    /*GILLT_s32*//*Label 2595*/ 129437,
48297    /*GILLT_s64*//*Label 2596*/ 129477,
48298    // Label 2594: @129397
48299    GIM_Try, /*On fail goto*//*Label 2598*/ 129436, // Rule ID 684 //
48300      GIM_CheckFeatures, GIFBS_HasFullFP16,
48301      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
48302      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
48303      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
48304      // (fnearbyint:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VRINTRH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
48305      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTRH,
48306      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
48307      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
48308      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
48309      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
48310      GIR_EraseFromParent, /*InsnID*/0,
48311      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48312      // GIR_Coverage, 684,
48313      GIR_Done,
48314    // Label 2598: @129436
48315    GIM_Reject,
48316    // Label 2595: @129437
48317    GIM_Try, /*On fail goto*//*Label 2599*/ 129476, // Rule ID 685 //
48318      GIM_CheckFeatures, GIFBS_HasFPARMv8,
48319      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
48320      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
48321      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
48322      // (fnearbyint:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VRINTRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
48323      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTRS,
48324      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
48325      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
48326      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
48327      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
48328      GIR_EraseFromParent, /*InsnID*/0,
48329      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48330      // GIR_Coverage, 685,
48331      GIR_Done,
48332    // Label 2599: @129476
48333    GIM_Reject,
48334    // Label 2596: @129477
48335    GIM_Try, /*On fail goto*//*Label 2600*/ 129516, // Rule ID 686 //
48336      GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
48337      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
48338      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
48339      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
48340      // (fnearbyint:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VRINTRD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
48341      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTRD,
48342      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
48343      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
48344      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
48345      GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
48346      GIR_EraseFromParent, /*InsnID*/0,
48347      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48348      // GIR_Coverage, 686,
48349      GIR_Done,
48350    // Label 2600: @129516
48351    GIM_Reject,
48352    // Label 2597: @129517
48353    GIM_Reject,
48354    // Label 65: @129518
48355    GIM_Reject,
48356    };
48357  return MatchTable0;
48358}
48359#endif // ifdef GET_GLOBALISEL_IMPL
48360#ifdef GET_GLOBALISEL_PREDICATES_DECL
48361PredicateBitset AvailableModuleFeatures;
48362mutable PredicateBitset AvailableFunctionFeatures;
48363PredicateBitset getAvailableFeatures() const {
48364  return AvailableModuleFeatures | AvailableFunctionFeatures;
48365}
48366PredicateBitset
48367computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const;
48368PredicateBitset
48369computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget,
48370                                 const MachineFunction *MF) const;
48371void setupGeneratedPerFunctionState(MachineFunction &MF) override;
48372#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
48373#ifdef GET_GLOBALISEL_PREDICATES_INIT
48374AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
48375AvailableFunctionFeatures()
48376#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT
48377