1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Machine Code Emitter *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9uint64_t ARMMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, 10 SmallVectorImpl<MCFixup> &Fixups, 11 const MCSubtargetInfo &STI) const { 12 static const uint64_t InstBits[] = { 13 UINT64_C(0), 14 UINT64_C(0), 15 UINT64_C(0), 16 UINT64_C(0), 17 UINT64_C(0), 18 UINT64_C(0), 19 UINT64_C(0), 20 UINT64_C(0), 21 UINT64_C(0), 22 UINT64_C(0), 23 UINT64_C(0), 24 UINT64_C(0), 25 UINT64_C(0), 26 UINT64_C(0), 27 UINT64_C(0), 28 UINT64_C(0), 29 UINT64_C(0), 30 UINT64_C(0), 31 UINT64_C(0), 32 UINT64_C(0), 33 UINT64_C(0), 34 UINT64_C(0), 35 UINT64_C(0), 36 UINT64_C(0), 37 UINT64_C(0), 38 UINT64_C(0), 39 UINT64_C(0), 40 UINT64_C(0), 41 UINT64_C(0), 42 UINT64_C(0), 43 UINT64_C(0), 44 UINT64_C(0), 45 UINT64_C(0), 46 UINT64_C(0), 47 UINT64_C(0), 48 UINT64_C(0), 49 UINT64_C(0), 50 UINT64_C(0), 51 UINT64_C(0), 52 UINT64_C(0), 53 UINT64_C(0), 54 UINT64_C(0), 55 UINT64_C(0), 56 UINT64_C(0), 57 UINT64_C(0), 58 UINT64_C(0), 59 UINT64_C(0), 60 UINT64_C(0), 61 UINT64_C(0), 62 UINT64_C(0), 63 UINT64_C(0), 64 UINT64_C(0), 65 UINT64_C(0), 66 UINT64_C(0), 67 UINT64_C(0), 68 UINT64_C(0), 69 UINT64_C(0), 70 UINT64_C(0), 71 UINT64_C(0), 72 UINT64_C(0), 73 UINT64_C(0), 74 UINT64_C(0), 75 UINT64_C(0), 76 UINT64_C(0), 77 UINT64_C(0), 78 UINT64_C(0), 79 UINT64_C(0), 80 UINT64_C(0), 81 UINT64_C(0), 82 UINT64_C(0), 83 UINT64_C(0), 84 UINT64_C(0), 85 UINT64_C(0), 86 UINT64_C(0), 87 UINT64_C(0), 88 UINT64_C(0), 89 UINT64_C(0), 90 UINT64_C(0), 91 UINT64_C(0), 92 UINT64_C(0), 93 UINT64_C(0), 94 UINT64_C(0), 95 UINT64_C(0), 96 UINT64_C(0), 97 UINT64_C(0), 98 UINT64_C(0), 99 UINT64_C(0), 100 UINT64_C(0), 101 UINT64_C(0), 102 UINT64_C(0), 103 UINT64_C(0), 104 UINT64_C(0), 105 UINT64_C(0), 106 UINT64_C(0), 107 UINT64_C(0), 108 UINT64_C(0), 109 UINT64_C(0), 110 UINT64_C(0), 111 UINT64_C(0), 112 UINT64_C(0), 113 UINT64_C(0), 114 UINT64_C(0), 115 UINT64_C(0), 116 UINT64_C(0), 117 UINT64_C(0), 118 UINT64_C(0), 119 UINT64_C(0), 120 UINT64_C(0), 121 UINT64_C(0), 122 UINT64_C(0), 123 UINT64_C(0), 124 UINT64_C(0), 125 UINT64_C(0), 126 UINT64_C(0), 127 UINT64_C(0), 128 UINT64_C(0), 129 UINT64_C(0), 130 UINT64_C(0), 131 UINT64_C(0), 132 UINT64_C(0), 133 UINT64_C(0), 134 UINT64_C(0), 135 UINT64_C(0), 136 UINT64_C(0), 137 UINT64_C(0), 138 UINT64_C(0), 139 UINT64_C(0), 140 UINT64_C(0), 141 UINT64_C(0), 142 UINT64_C(0), 143 UINT64_C(0), 144 UINT64_C(0), 145 UINT64_C(0), 146 UINT64_C(0), 147 UINT64_C(0), 148 UINT64_C(0), 149 UINT64_C(0), 150 UINT64_C(0), 151 UINT64_C(0), 152 UINT64_C(0), 153 UINT64_C(0), 154 UINT64_C(0), 155 UINT64_C(0), 156 UINT64_C(0), 157 UINT64_C(0), 158 UINT64_C(0), 159 UINT64_C(0), 160 UINT64_C(0), 161 UINT64_C(0), 162 UINT64_C(0), 163 UINT64_C(0), 164 UINT64_C(0), 165 UINT64_C(0), 166 UINT64_C(0), 167 UINT64_C(0), 168 UINT64_C(0), 169 UINT64_C(0), 170 UINT64_C(0), 171 UINT64_C(0), 172 UINT64_C(0), 173 UINT64_C(0), 174 UINT64_C(0), 175 UINT64_C(0), 176 UINT64_C(0), 177 UINT64_C(0), 178 UINT64_C(0), 179 UINT64_C(0), 180 UINT64_C(0), 181 UINT64_C(0), 182 UINT64_C(0), 183 UINT64_C(0), 184 UINT64_C(0), 185 UINT64_C(0), 186 UINT64_C(0), 187 UINT64_C(0), 188 UINT64_C(0), 189 UINT64_C(0), 190 UINT64_C(0), 191 UINT64_C(0), 192 UINT64_C(0), 193 UINT64_C(0), 194 UINT64_C(0), 195 UINT64_C(0), 196 UINT64_C(0), 197 UINT64_C(0), 198 UINT64_C(0), 199 UINT64_C(0), 200 UINT64_C(0), 201 UINT64_C(0), 202 UINT64_C(0), 203 UINT64_C(0), 204 UINT64_C(0), 205 UINT64_C(0), 206 UINT64_C(0), 207 UINT64_C(0), 208 UINT64_C(0), 209 UINT64_C(0), 210 UINT64_C(0), 211 UINT64_C(0), 212 UINT64_C(0), 213 UINT64_C(0), 214 UINT64_C(0), 215 UINT64_C(0), 216 UINT64_C(0), 217 UINT64_C(0), 218 UINT64_C(0), 219 UINT64_C(0), 220 UINT64_C(0), 221 UINT64_C(0), 222 UINT64_C(0), 223 UINT64_C(0), 224 UINT64_C(0), 225 UINT64_C(0), 226 UINT64_C(0), 227 UINT64_C(0), 228 UINT64_C(0), 229 UINT64_C(0), 230 UINT64_C(0), 231 UINT64_C(0), 232 UINT64_C(0), 233 UINT64_C(0), 234 UINT64_C(0), 235 UINT64_C(0), 236 UINT64_C(0), 237 UINT64_C(0), 238 UINT64_C(0), 239 UINT64_C(0), 240 UINT64_C(0), 241 UINT64_C(0), 242 UINT64_C(0), 243 UINT64_C(0), 244 UINT64_C(0), 245 UINT64_C(0), 246 UINT64_C(0), 247 UINT64_C(0), 248 UINT64_C(0), 249 UINT64_C(0), 250 UINT64_C(0), 251 UINT64_C(0), 252 UINT64_C(0), 253 UINT64_C(0), 254 UINT64_C(0), 255 UINT64_C(0), 256 UINT64_C(0), 257 UINT64_C(0), 258 UINT64_C(0), 259 UINT64_C(0), 260 UINT64_C(0), 261 UINT64_C(0), 262 UINT64_C(0), 263 UINT64_C(0), 264 UINT64_C(0), 265 UINT64_C(0), 266 UINT64_C(0), 267 UINT64_C(0), 268 UINT64_C(0), 269 UINT64_C(0), 270 UINT64_C(0), 271 UINT64_C(0), 272 UINT64_C(0), 273 UINT64_C(0), 274 UINT64_C(0), 275 UINT64_C(0), 276 UINT64_C(0), 277 UINT64_C(0), 278 UINT64_C(0), 279 UINT64_C(0), 280 UINT64_C(0), 281 UINT64_C(0), 282 UINT64_C(0), 283 UINT64_C(0), 284 UINT64_C(0), 285 UINT64_C(0), 286 UINT64_C(0), 287 UINT64_C(0), 288 UINT64_C(0), 289 UINT64_C(0), 290 UINT64_C(0), 291 UINT64_C(0), 292 UINT64_C(0), 293 UINT64_C(0), 294 UINT64_C(0), 295 UINT64_C(0), 296 UINT64_C(0), 297 UINT64_C(0), 298 UINT64_C(0), 299 UINT64_C(0), 300 UINT64_C(0), 301 UINT64_C(0), 302 UINT64_C(0), 303 UINT64_C(0), 304 UINT64_C(0), 305 UINT64_C(0), 306 UINT64_C(0), 307 UINT64_C(0), 308 UINT64_C(0), 309 UINT64_C(0), 310 UINT64_C(0), 311 UINT64_C(0), 312 UINT64_C(0), 313 UINT64_C(0), 314 UINT64_C(0), 315 UINT64_C(0), 316 UINT64_C(0), 317 UINT64_C(0), 318 UINT64_C(0), 319 UINT64_C(0), 320 UINT64_C(0), 321 UINT64_C(0), 322 UINT64_C(0), 323 UINT64_C(0), 324 UINT64_C(0), 325 UINT64_C(0), 326 UINT64_C(0), 327 UINT64_C(0), 328 UINT64_C(0), 329 UINT64_C(0), 330 UINT64_C(0), 331 UINT64_C(0), 332 UINT64_C(0), 333 UINT64_C(0), 334 UINT64_C(0), 335 UINT64_C(0), 336 UINT64_C(0), 337 UINT64_C(0), 338 UINT64_C(0), 339 UINT64_C(0), 340 UINT64_C(0), 341 UINT64_C(0), 342 UINT64_C(0), 343 UINT64_C(0), 344 UINT64_C(0), 345 UINT64_C(0), 346 UINT64_C(0), 347 UINT64_C(0), 348 UINT64_C(0), 349 UINT64_C(0), 350 UINT64_C(0), 351 UINT64_C(0), 352 UINT64_C(0), 353 UINT64_C(0), 354 UINT64_C(0), 355 UINT64_C(0), 356 UINT64_C(0), 357 UINT64_C(0), 358 UINT64_C(0), 359 UINT64_C(0), 360 UINT64_C(0), 361 UINT64_C(0), 362 UINT64_C(0), 363 UINT64_C(0), 364 UINT64_C(0), 365 UINT64_C(0), 366 UINT64_C(0), 367 UINT64_C(0), 368 UINT64_C(0), 369 UINT64_C(0), 370 UINT64_C(0), 371 UINT64_C(0), 372 UINT64_C(0), 373 UINT64_C(0), 374 UINT64_C(0), 375 UINT64_C(0), 376 UINT64_C(0), 377 UINT64_C(0), 378 UINT64_C(0), 379 UINT64_C(0), 380 UINT64_C(0), 381 UINT64_C(0), 382 UINT64_C(0), 383 UINT64_C(0), 384 UINT64_C(0), 385 UINT64_C(0), 386 UINT64_C(0), 387 UINT64_C(0), 388 UINT64_C(0), 389 UINT64_C(0), 390 UINT64_C(0), 391 UINT64_C(0), 392 UINT64_C(0), 393 UINT64_C(0), 394 UINT64_C(0), 395 UINT64_C(0), 396 UINT64_C(0), 397 UINT64_C(0), 398 UINT64_C(0), 399 UINT64_C(0), 400 UINT64_C(0), 401 UINT64_C(0), 402 UINT64_C(0), 403 UINT64_C(0), 404 UINT64_C(0), 405 UINT64_C(0), 406 UINT64_C(0), 407 UINT64_C(0), 408 UINT64_C(0), 409 UINT64_C(0), 410 UINT64_C(0), 411 UINT64_C(0), 412 UINT64_C(0), 413 UINT64_C(0), 414 UINT64_C(0), 415 UINT64_C(0), 416 UINT64_C(0), 417 UINT64_C(0), 418 UINT64_C(0), 419 UINT64_C(0), 420 UINT64_C(0), 421 UINT64_C(0), 422 UINT64_C(0), 423 UINT64_C(0), 424 UINT64_C(0), 425 UINT64_C(0), 426 UINT64_C(0), 427 UINT64_C(0), 428 UINT64_C(0), 429 UINT64_C(0), 430 UINT64_C(0), 431 UINT64_C(0), 432 UINT64_C(0), 433 UINT64_C(0), 434 UINT64_C(0), 435 UINT64_C(0), 436 UINT64_C(0), 437 UINT64_C(0), 438 UINT64_C(0), 439 UINT64_C(0), 440 UINT64_C(0), 441 UINT64_C(0), 442 UINT64_C(0), 443 UINT64_C(0), 444 UINT64_C(0), 445 UINT64_C(0), 446 UINT64_C(0), 447 UINT64_C(0), 448 UINT64_C(0), 449 UINT64_C(0), 450 UINT64_C(0), 451 UINT64_C(0), 452 UINT64_C(0), 453 UINT64_C(0), 454 UINT64_C(0), 455 UINT64_C(0), 456 UINT64_C(0), 457 UINT64_C(0), 458 UINT64_C(0), 459 UINT64_C(0), 460 UINT64_C(0), 461 UINT64_C(0), 462 UINT64_C(0), 463 UINT64_C(0), 464 UINT64_C(0), 465 UINT64_C(0), 466 UINT64_C(0), 467 UINT64_C(0), 468 UINT64_C(0), 469 UINT64_C(0), 470 UINT64_C(0), 471 UINT64_C(0), 472 UINT64_C(0), 473 UINT64_C(0), 474 UINT64_C(0), 475 UINT64_C(0), 476 UINT64_C(0), 477 UINT64_C(0), 478 UINT64_C(0), 479 UINT64_C(0), 480 UINT64_C(0), 481 UINT64_C(0), 482 UINT64_C(0), 483 UINT64_C(0), 484 UINT64_C(0), 485 UINT64_C(0), 486 UINT64_C(0), 487 UINT64_C(0), 488 UINT64_C(0), 489 UINT64_C(0), 490 UINT64_C(0), 491 UINT64_C(0), 492 UINT64_C(0), 493 UINT64_C(0), 494 UINT64_C(0), 495 UINT64_C(0), 496 UINT64_C(0), 497 UINT64_C(0), 498 UINT64_C(0), 499 UINT64_C(0), 500 UINT64_C(0), 501 UINT64_C(0), 502 UINT64_C(0), 503 UINT64_C(0), 504 UINT64_C(0), 505 UINT64_C(0), 506 UINT64_C(0), 507 UINT64_C(0), 508 UINT64_C(0), 509 UINT64_C(0), 510 UINT64_C(0), 511 UINT64_C(0), 512 UINT64_C(0), 513 UINT64_C(0), 514 UINT64_C(0), 515 UINT64_C(0), 516 UINT64_C(0), 517 UINT64_C(0), 518 UINT64_C(0), 519 UINT64_C(0), 520 UINT64_C(0), 521 UINT64_C(0), 522 UINT64_C(0), 523 UINT64_C(0), 524 UINT64_C(0), 525 UINT64_C(0), 526 UINT64_C(0), 527 UINT64_C(0), 528 UINT64_C(0), 529 UINT64_C(0), 530 UINT64_C(0), 531 UINT64_C(0), 532 UINT64_C(0), 533 UINT64_C(0), 534 UINT64_C(0), 535 UINT64_C(0), 536 UINT64_C(0), 537 UINT64_C(0), 538 UINT64_C(0), 539 UINT64_C(0), 540 UINT64_C(0), 541 UINT64_C(0), 542 UINT64_C(0), 543 UINT64_C(0), 544 UINT64_C(0), 545 UINT64_C(0), 546 UINT64_C(0), 547 UINT64_C(0), 548 UINT64_C(0), 549 UINT64_C(0), 550 UINT64_C(0), 551 UINT64_C(0), 552 UINT64_C(0), 553 UINT64_C(0), 554 UINT64_C(0), 555 UINT64_C(0), 556 UINT64_C(0), 557 UINT64_C(0), 558 UINT64_C(0), 559 UINT64_C(0), 560 UINT64_C(0), 561 UINT64_C(0), 562 UINT64_C(0), 563 UINT64_C(0), 564 UINT64_C(0), 565 UINT64_C(0), 566 UINT64_C(0), 567 UINT64_C(0), 568 UINT64_C(0), 569 UINT64_C(0), 570 UINT64_C(0), 571 UINT64_C(0), 572 UINT64_C(0), 573 UINT64_C(0), 574 UINT64_C(0), 575 UINT64_C(0), 576 UINT64_C(0), 577 UINT64_C(0), 578 UINT64_C(0), 579 UINT64_C(0), 580 UINT64_C(0), 581 UINT64_C(0), 582 UINT64_C(0), 583 UINT64_C(0), 584 UINT64_C(0), 585 UINT64_C(0), 586 UINT64_C(0), 587 UINT64_C(0), 588 UINT64_C(0), 589 UINT64_C(0), 590 UINT64_C(0), 591 UINT64_C(0), 592 UINT64_C(0), 593 UINT64_C(0), 594 UINT64_C(0), 595 UINT64_C(0), 596 UINT64_C(0), 597 UINT64_C(0), 598 UINT64_C(0), 599 UINT64_C(0), 600 UINT64_C(0), 601 UINT64_C(0), 602 UINT64_C(0), 603 UINT64_C(0), 604 UINT64_C(0), 605 UINT64_C(0), 606 UINT64_C(0), 607 UINT64_C(0), 608 UINT64_C(0), 609 UINT64_C(0), 610 UINT64_C(0), 611 UINT64_C(0), 612 UINT64_C(0), 613 UINT64_C(0), 614 UINT64_C(0), 615 UINT64_C(0), 616 UINT64_C(0), 617 UINT64_C(0), 618 UINT64_C(0), 619 UINT64_C(0), 620 UINT64_C(0), 621 UINT64_C(0), 622 UINT64_C(0), 623 UINT64_C(0), 624 UINT64_C(0), 625 UINT64_C(0), 626 UINT64_C(0), 627 UINT64_C(0), 628 UINT64_C(0), 629 UINT64_C(0), 630 UINT64_C(0), 631 UINT64_C(0), 632 UINT64_C(0), 633 UINT64_C(0), 634 UINT64_C(0), 635 UINT64_C(0), 636 UINT64_C(0), 637 UINT64_C(0), 638 UINT64_C(0), 639 UINT64_C(0), 640 UINT64_C(0), 641 UINT64_C(0), 642 UINT64_C(0), 643 UINT64_C(0), 644 UINT64_C(0), 645 UINT64_C(0), 646 UINT64_C(0), 647 UINT64_C(0), 648 UINT64_C(0), 649 UINT64_C(0), 650 UINT64_C(0), 651 UINT64_C(0), 652 UINT64_C(0), 653 UINT64_C(0), 654 UINT64_C(0), 655 UINT64_C(0), 656 UINT64_C(0), 657 UINT64_C(0), 658 UINT64_C(0), 659 UINT64_C(0), 660 UINT64_C(0), 661 UINT64_C(0), 662 UINT64_C(0), 663 UINT64_C(0), 664 UINT64_C(0), 665 UINT64_C(0), 666 UINT64_C(0), 667 UINT64_C(0), 668 UINT64_C(0), 669 UINT64_C(0), 670 UINT64_C(0), 671 UINT64_C(0), 672 UINT64_C(0), 673 UINT64_C(0), 674 UINT64_C(0), 675 UINT64_C(0), 676 UINT64_C(0), 677 UINT64_C(0), 678 UINT64_C(0), 679 UINT64_C(0), 680 UINT64_C(0), 681 UINT64_C(0), 682 UINT64_C(0), 683 UINT64_C(0), 684 UINT64_C(0), 685 UINT64_C(0), 686 UINT64_C(0), 687 UINT64_C(0), 688 UINT64_C(0), 689 UINT64_C(0), 690 UINT64_C(0), 691 UINT64_C(0), 692 UINT64_C(0), 693 UINT64_C(0), 694 UINT64_C(0), 695 UINT64_C(0), 696 UINT64_C(0), 697 UINT64_C(0), 698 UINT64_C(0), 699 UINT64_C(0), 700 UINT64_C(0), 701 UINT64_C(0), 702 UINT64_C(0), 703 UINT64_C(0), 704 UINT64_C(0), 705 UINT64_C(0), 706 UINT64_C(0), 707 UINT64_C(0), 708 UINT64_C(0), 709 UINT64_C(0), 710 UINT64_C(0), 711 UINT64_C(0), 712 UINT64_C(0), 713 UINT64_C(0), 714 UINT64_C(0), 715 UINT64_C(0), 716 UINT64_C(0), 717 UINT64_C(0), 718 UINT64_C(0), 719 UINT64_C(0), 720 UINT64_C(0), 721 UINT64_C(0), 722 UINT64_C(44040192), // ADCri 723 UINT64_C(10485760), // ADCrr 724 UINT64_C(10485760), // ADCrsi 725 UINT64_C(10485776), // ADCrsr 726 UINT64_C(41943040), // ADDri 727 UINT64_C(8388608), // ADDrr 728 UINT64_C(8388608), // ADDrsi 729 UINT64_C(8388624), // ADDrsr 730 UINT64_C(34537472), // ADR 731 UINT64_C(4088398656), // AESD 732 UINT64_C(4088398592), // AESE 733 UINT64_C(4088398784), // AESIMC 734 UINT64_C(4088398720), // AESMC 735 UINT64_C(33554432), // ANDri 736 UINT64_C(0), // ANDrr 737 UINT64_C(0), // ANDrsi 738 UINT64_C(16), // ANDrsr 739 UINT64_C(4261416192), // BF16VDOTI_VDOTD 740 UINT64_C(4261416256), // BF16VDOTI_VDOTQ 741 UINT64_C(4227861760), // BF16VDOTS_VDOTD 742 UINT64_C(4227861824), // BF16VDOTS_VDOTQ 743 UINT64_C(4088792640), // BF16_VCVT 744 UINT64_C(246614336), // BF16_VCVTB 745 UINT64_C(246614464), // BF16_VCVTT 746 UINT64_C(130023455), // BFC 747 UINT64_C(130023440), // BFI 748 UINT64_C(62914560), // BICri 749 UINT64_C(29360128), // BICrr 750 UINT64_C(29360128), // BICrsi 751 UINT64_C(29360144), // BICrsr 752 UINT64_C(3776970864), // BKPT 753 UINT64_C(3942645760), // BL 754 UINT64_C(3778019120), // BLX 755 UINT64_C(19922736), // BLX_pred 756 UINT64_C(4194304000), // BLXi 757 UINT64_C(184549376), // BL_pred 758 UINT64_C(3778019088), // BX 759 UINT64_C(19922720), // BXJ 760 UINT64_C(19922718), // BX_RET 761 UINT64_C(19922704), // BX_pred 762 UINT64_C(167772160), // Bcc 763 UINT64_C(3992977408), // CDE_CX1 764 UINT64_C(4261412864), // CDE_CX1A 765 UINT64_C(3992977472), // CDE_CX1D 766 UINT64_C(4261412928), // CDE_CX1DA 767 UINT64_C(3997171712), // CDE_CX2 768 UINT64_C(4265607168), // CDE_CX2A 769 UINT64_C(3997171776), // CDE_CX2D 770 UINT64_C(4265607232), // CDE_CX2DA 771 UINT64_C(4001366016), // CDE_CX3 772 UINT64_C(4269801472), // CDE_CX3A 773 UINT64_C(4001366080), // CDE_CX3D 774 UINT64_C(4269801536), // CDE_CX3DA 775 UINT64_C(4246732800), // CDE_VCX1A_fpdp 776 UINT64_C(4229955584), // CDE_VCX1A_fpsp 777 UINT64_C(4229955648), // CDE_VCX1A_vec 778 UINT64_C(3978297344), // CDE_VCX1_fpdp 779 UINT64_C(3961520128), // CDE_VCX1_fpsp 780 UINT64_C(3961520192), // CDE_VCX1_vec 781 UINT64_C(4247781376), // CDE_VCX2A_fpdp 782 UINT64_C(4231004160), // CDE_VCX2A_fpsp 783 UINT64_C(4231004224), // CDE_VCX2A_vec 784 UINT64_C(3979345920), // CDE_VCX2_fpdp 785 UINT64_C(3962568704), // CDE_VCX2_fpsp 786 UINT64_C(3962568768), // CDE_VCX2_vec 787 UINT64_C(4253024256), // CDE_VCX3A_fpdp 788 UINT64_C(4236247040), // CDE_VCX3A_fpsp 789 UINT64_C(4236247104), // CDE_VCX3A_vec 790 UINT64_C(3984588800), // CDE_VCX3_fpdp 791 UINT64_C(3967811584), // CDE_VCX3_fpsp 792 UINT64_C(3967811648), // CDE_VCX3_vec 793 UINT64_C(234881024), // CDP 794 UINT64_C(4261412864), // CDP2 795 UINT64_C(4118802463), // CLREX 796 UINT64_C(24055568), // CLZ 797 UINT64_C(57671680), // CMNri 798 UINT64_C(24117248), // CMNzrr 799 UINT64_C(24117248), // CMNzrsi 800 UINT64_C(24117264), // CMNzrsr 801 UINT64_C(55574528), // CMPri 802 UINT64_C(22020096), // CMPrr 803 UINT64_C(22020096), // CMPrsi 804 UINT64_C(22020112), // CMPrsr 805 UINT64_C(4043440128), // CPS1p 806 UINT64_C(4043309056), // CPS2p 807 UINT64_C(4043440128), // CPS3p 808 UINT64_C(3774873664), // CRC32B 809 UINT64_C(3774874176), // CRC32CB 810 UINT64_C(3776971328), // CRC32CH 811 UINT64_C(3779068480), // CRC32CW 812 UINT64_C(3776970816), // CRC32H 813 UINT64_C(3779067968), // CRC32W 814 UINT64_C(52490480), // DBG 815 UINT64_C(4118802512), // DMB 816 UINT64_C(4118802496), // DSB 817 UINT64_C(35651584), // EORri 818 UINT64_C(2097152), // EORrr 819 UINT64_C(2097152), // EORrsi 820 UINT64_C(2097168), // EORrsr 821 UINT64_C(23068782), // ERET 822 UINT64_C(246418176), // FCONSTD 823 UINT64_C(246417664), // FCONSTH 824 UINT64_C(246417920), // FCONSTS 825 UINT64_C(221252353), // FLDMXDB_UPD 826 UINT64_C(210766593), // FLDMXIA 827 UINT64_C(212863745), // FLDMXIA_UPD 828 UINT64_C(250739216), // FMSTAT 829 UINT64_C(220203777), // FSTMXDB_UPD 830 UINT64_C(209718017), // FSTMXIA 831 UINT64_C(211815169), // FSTMXIA_UPD 832 UINT64_C(52490240), // HINT 833 UINT64_C(3774873712), // HLT 834 UINT64_C(3779068016), // HVC 835 UINT64_C(4118802528), // ISB 836 UINT64_C(26217631), // LDA 837 UINT64_C(30411935), // LDAB 838 UINT64_C(26218143), // LDAEX 839 UINT64_C(30412447), // LDAEXB 840 UINT64_C(28315295), // LDAEXD 841 UINT64_C(32509599), // LDAEXH 842 UINT64_C(32509087), // LDAH 843 UINT64_C(4249878528), // LDC2L_OFFSET 844 UINT64_C(4241489920), // LDC2L_OPTION 845 UINT64_C(4235198464), // LDC2L_POST 846 UINT64_C(4251975680), // LDC2L_PRE 847 UINT64_C(4245684224), // LDC2_OFFSET 848 UINT64_C(4237295616), // LDC2_OPTION 849 UINT64_C(4231004160), // LDC2_POST 850 UINT64_C(4247781376), // LDC2_PRE 851 UINT64_C(223346688), // LDCL_OFFSET 852 UINT64_C(214958080), // LDCL_OPTION 853 UINT64_C(208666624), // LDCL_POST 854 UINT64_C(225443840), // LDCL_PRE 855 UINT64_C(219152384), // LDC_OFFSET 856 UINT64_C(210763776), // LDC_OPTION 857 UINT64_C(204472320), // LDC_POST 858 UINT64_C(221249536), // LDC_PRE 859 UINT64_C(135266304), // LDMDA 860 UINT64_C(137363456), // LDMDA_UPD 861 UINT64_C(152043520), // LDMDB 862 UINT64_C(154140672), // LDMDB_UPD 863 UINT64_C(143654912), // LDMIA 864 UINT64_C(145752064), // LDMIA_UPD 865 UINT64_C(160432128), // LDMIB 866 UINT64_C(162529280), // LDMIB_UPD 867 UINT64_C(74448896), // LDRBT_POST_IMM 868 UINT64_C(108003328), // LDRBT_POST_REG 869 UINT64_C(72351744), // LDRB_POST_IMM 870 UINT64_C(105906176), // LDRB_POST_REG 871 UINT64_C(91226112), // LDRB_PRE_IMM 872 UINT64_C(124780544), // LDRB_PRE_REG 873 UINT64_C(89128960), // LDRBi12 874 UINT64_C(122683392), // LDRBrs 875 UINT64_C(16777424), // LDRD 876 UINT64_C(208), // LDRD_POST 877 UINT64_C(18874576), // LDRD_PRE 878 UINT64_C(26218399), // LDREX 879 UINT64_C(30412703), // LDREXB 880 UINT64_C(28315551), // LDREXD 881 UINT64_C(32509855), // LDREXH 882 UINT64_C(17825968), // LDRH 883 UINT64_C(7340208), // LDRHTi 884 UINT64_C(3145904), // LDRHTr 885 UINT64_C(1048752), // LDRH_POST 886 UINT64_C(19923120), // LDRH_PRE 887 UINT64_C(17826000), // LDRSB 888 UINT64_C(7340240), // LDRSBTi 889 UINT64_C(3145936), // LDRSBTr 890 UINT64_C(1048784), // LDRSB_POST 891 UINT64_C(19923152), // LDRSB_PRE 892 UINT64_C(17826032), // LDRSH 893 UINT64_C(7340272), // LDRSHTi 894 UINT64_C(3145968), // LDRSHTr 895 UINT64_C(1048816), // LDRSH_POST 896 UINT64_C(19923184), // LDRSH_PRE 897 UINT64_C(70254592), // LDRT_POST_IMM 898 UINT64_C(103809024), // LDRT_POST_REG 899 UINT64_C(68157440), // LDR_POST_IMM 900 UINT64_C(101711872), // LDR_POST_REG 901 UINT64_C(87031808), // LDR_PRE_IMM 902 UINT64_C(120586240), // LDR_PRE_REG 903 UINT64_C(85917696), // LDRcp 904 UINT64_C(84934656), // LDRi12 905 UINT64_C(118489088), // LDRrs 906 UINT64_C(234881040), // MCR 907 UINT64_C(4261412880), // MCR2 908 UINT64_C(205520896), // MCRR 909 UINT64_C(4232052736), // MCRR2 910 UINT64_C(2097296), // MLA 911 UINT64_C(6291600), // MLS 912 UINT64_C(27324430), // MOVPCLR 913 UINT64_C(54525952), // MOVTi16 914 UINT64_C(60817408), // MOVi 915 UINT64_C(50331648), // MOVi16 916 UINT64_C(27262976), // MOVr 917 UINT64_C(27262976), // MOVr_TC 918 UINT64_C(27262976), // MOVsi 919 UINT64_C(27262992), // MOVsr 920 UINT64_C(235929616), // MRC 921 UINT64_C(4262461456), // MRC2 922 UINT64_C(206569472), // MRRC 923 UINT64_C(4233101312), // MRRC2 924 UINT64_C(17760256), // MRS 925 UINT64_C(16777728), // MRSbanked 926 UINT64_C(21954560), // MRSsys 927 UINT64_C(18935808), // MSR 928 UINT64_C(18936320), // MSRbanked 929 UINT64_C(52490240), // MSRi 930 UINT64_C(144), // MUL 931 UINT64_C(3931111727), // MVE_ASRLi 932 UINT64_C(3931111725), // MVE_ASRLr 933 UINT64_C(4027637761), // MVE_DLSTP_16 934 UINT64_C(4028686337), // MVE_DLSTP_32 935 UINT64_C(4029734913), // MVE_DLSTP_64 936 UINT64_C(4026589185), // MVE_DLSTP_8 937 UINT64_C(4027572225), // MVE_LCTP 938 UINT64_C(4028612609), // MVE_LETP 939 UINT64_C(3931111695), // MVE_LSLLi 940 UINT64_C(3931111693), // MVE_LSLLr 941 UINT64_C(3931111711), // MVE_LSRL 942 UINT64_C(3931115309), // MVE_SQRSHR 943 UINT64_C(3931177261), // MVE_SQRSHRL 944 UINT64_C(3931115327), // MVE_SQSHL 945 UINT64_C(3931177279), // MVE_SQSHLL 946 UINT64_C(3931115311), // MVE_SRSHR 947 UINT64_C(3931177263), // MVE_SRSHRL 948 UINT64_C(3931115277), // MVE_UQRSHL 949 UINT64_C(3931177229), // MVE_UQRSHLL 950 UINT64_C(3931115279), // MVE_UQSHL 951 UINT64_C(3931177231), // MVE_UQSHLL 952 UINT64_C(3931115295), // MVE_URSHR 953 UINT64_C(3931177247), // MVE_URSHRL 954 UINT64_C(4002418433), // MVE_VABAVs16 955 UINT64_C(4003467009), // MVE_VABAVs32 956 UINT64_C(4001369857), // MVE_VABAVs8 957 UINT64_C(4270853889), // MVE_VABAVu16 958 UINT64_C(4271902465), // MVE_VABAVu32 959 UINT64_C(4269805313), // MVE_VABAVu8 960 UINT64_C(4281339200), // MVE_VABDf16 961 UINT64_C(4280290624), // MVE_VABDf32 962 UINT64_C(4010805056), // MVE_VABDs16 963 UINT64_C(4011853632), // MVE_VABDs32 964 UINT64_C(4009756480), // MVE_VABDs8 965 UINT64_C(4279240512), // MVE_VABDu16 966 UINT64_C(4280289088), // MVE_VABDu32 967 UINT64_C(4278191936), // MVE_VABDu8 968 UINT64_C(4290053952), // MVE_VABSf16 969 UINT64_C(4290316096), // MVE_VABSf32 970 UINT64_C(4290052928), // MVE_VABSs16 971 UINT64_C(4290315072), // MVE_VABSs32 972 UINT64_C(4289790784), // MVE_VABSs8 973 UINT64_C(3996126976), // MVE_VADC 974 UINT64_C(3996131072), // MVE_VADCI 975 UINT64_C(4001959712), // MVE_VADDLVs32acc 976 UINT64_C(4001959680), // MVE_VADDLVs32no_acc 977 UINT64_C(4270395168), // MVE_VADDLVu32acc 978 UINT64_C(4270395136), // MVE_VADDLVu32no_acc 979 UINT64_C(4009037600), // MVE_VADDVs16acc 980 UINT64_C(4009037568), // MVE_VADDVs16no_acc 981 UINT64_C(4009299744), // MVE_VADDVs32acc 982 UINT64_C(4009299712), // MVE_VADDVs32no_acc 983 UINT64_C(4008775456), // MVE_VADDVs8acc 984 UINT64_C(4008775424), // MVE_VADDVs8no_acc 985 UINT64_C(4277473056), // MVE_VADDVu16acc 986 UINT64_C(4277473024), // MVE_VADDVu16no_acc 987 UINT64_C(4277735200), // MVE_VADDVu32acc 988 UINT64_C(4277735168), // MVE_VADDVu32no_acc 989 UINT64_C(4277210912), // MVE_VADDVu8acc 990 UINT64_C(4277210880), // MVE_VADDVu8no_acc 991 UINT64_C(4264562496), // MVE_VADD_qr_f16 992 UINT64_C(3996127040), // MVE_VADD_qr_f32 993 UINT64_C(3994095424), // MVE_VADD_qr_i16 994 UINT64_C(3995144000), // MVE_VADD_qr_i32 995 UINT64_C(3993046848), // MVE_VADD_qr_i8 996 UINT64_C(4010806592), // MVE_VADDf16 997 UINT64_C(4009758016), // MVE_VADDf32 998 UINT64_C(4010805312), // MVE_VADDi16 999 UINT64_C(4011853888), // MVE_VADDi32 1000 UINT64_C(4009756736), // MVE_VADDi8 1001 UINT64_C(4009754960), // MVE_VAND 1002 UINT64_C(4010803536), // MVE_VBIC 1003 UINT64_C(4018145648), // MVE_VBICimmi16 1004 UINT64_C(4018143600), // MVE_VBICimmi32 1005 UINT64_C(4262534752), // MVE_VBRSR16 1006 UINT64_C(4263583328), // MVE_VBRSR32 1007 UINT64_C(4261486176), // MVE_VBRSR8 1008 UINT64_C(4236249152), // MVE_VCADDf16 1009 UINT64_C(4237297728), // MVE_VCADDf32 1010 UINT64_C(4262465280), // MVE_VCADDi16 1011 UINT64_C(4263513856), // MVE_VCADDi32 1012 UINT64_C(4261416704), // MVE_VCADDi8 1013 UINT64_C(4289987648), // MVE_VCLSs16 1014 UINT64_C(4290249792), // MVE_VCLSs32 1015 UINT64_C(4289725504), // MVE_VCLSs8 1016 UINT64_C(4289987776), // MVE_VCLZs16 1017 UINT64_C(4290249920), // MVE_VCLZs32 1018 UINT64_C(4289725632), // MVE_VCLZs8 1019 UINT64_C(4229957696), // MVE_VCMLAf16 1020 UINT64_C(4231006272), // MVE_VCMLAf32 1021 UINT64_C(4264627968), // MVE_VCMPf16 1022 UINT64_C(4264628032), // MVE_VCMPf16r 1023 UINT64_C(3996192512), // MVE_VCMPf32 1024 UINT64_C(3996192576), // MVE_VCMPf32r 1025 UINT64_C(4262530816), // MVE_VCMPi16 1026 UINT64_C(4262530880), // MVE_VCMPi16r 1027 UINT64_C(4263579392), // MVE_VCMPi32 1028 UINT64_C(4263579456), // MVE_VCMPi32r 1029 UINT64_C(4261482240), // MVE_VCMPi8 1030 UINT64_C(4261482304), // MVE_VCMPi8r 1031 UINT64_C(4262534912), // MVE_VCMPs16 1032 UINT64_C(4262534976), // MVE_VCMPs16r 1033 UINT64_C(4263583488), // MVE_VCMPs32 1034 UINT64_C(4263583552), // MVE_VCMPs32r 1035 UINT64_C(4261486336), // MVE_VCMPs8 1036 UINT64_C(4261486400), // MVE_VCMPs8r 1037 UINT64_C(4262530817), // MVE_VCMPu16 1038 UINT64_C(4262530912), // MVE_VCMPu16r 1039 UINT64_C(4263579393), // MVE_VCMPu32 1040 UINT64_C(4263579488), // MVE_VCMPu32r 1041 UINT64_C(4261482241), // MVE_VCMPu8 1042 UINT64_C(4261482336), // MVE_VCMPu8r 1043 UINT64_C(3996126720), // MVE_VCMULf16 1044 UINT64_C(4264562176), // MVE_VCMULf32 1045 UINT64_C(4027639809), // MVE_VCTP16 1046 UINT64_C(4028688385), // MVE_VCTP32 1047 UINT64_C(4029736961), // MVE_VCTP64 1048 UINT64_C(4026591233), // MVE_VCTP8 1049 UINT64_C(3997109761), // MVE_VCVTf16f32bh 1050 UINT64_C(3997113857), // MVE_VCVTf16f32th 1051 UINT64_C(4021292112), // MVE_VCVTf16s16_fix 1052 UINT64_C(4290184768), // MVE_VCVTf16s16n 1053 UINT64_C(4289727568), // MVE_VCVTf16u16_fix 1054 UINT64_C(4290184896), // MVE_VCVTf16u16n 1055 UINT64_C(4265545217), // MVE_VCVTf32f16bh 1056 UINT64_C(4265549313), // MVE_VCVTf32f16th 1057 UINT64_C(4020244048), // MVE_VCVTf32s32_fix 1058 UINT64_C(4290446912), // MVE_VCVTf32s32n 1059 UINT64_C(4288679504), // MVE_VCVTf32u32_fix 1060 UINT64_C(4290447040), // MVE_VCVTf32u32n 1061 UINT64_C(4021292368), // MVE_VCVTs16f16_fix 1062 UINT64_C(4290183232), // MVE_VCVTs16f16a 1063 UINT64_C(4290184000), // MVE_VCVTs16f16m 1064 UINT64_C(4290183488), // MVE_VCVTs16f16n 1065 UINT64_C(4290183744), // MVE_VCVTs16f16p 1066 UINT64_C(4290185024), // MVE_VCVTs16f16z 1067 UINT64_C(4020244304), // MVE_VCVTs32f32_fix 1068 UINT64_C(4290445376), // MVE_VCVTs32f32a 1069 UINT64_C(4290446144), // MVE_VCVTs32f32m 1070 UINT64_C(4290445632), // MVE_VCVTs32f32n 1071 UINT64_C(4290445888), // MVE_VCVTs32f32p 1072 UINT64_C(4290447168), // MVE_VCVTs32f32z 1073 UINT64_C(4289727824), // MVE_VCVTu16f16_fix 1074 UINT64_C(4290183360), // MVE_VCVTu16f16a 1075 UINT64_C(4290184128), // MVE_VCVTu16f16m 1076 UINT64_C(4290183616), // MVE_VCVTu16f16n 1077 UINT64_C(4290183872), // MVE_VCVTu16f16p 1078 UINT64_C(4290185152), // MVE_VCVTu16f16z 1079 UINT64_C(4288679760), // MVE_VCVTu32f32_fix 1080 UINT64_C(4290445504), // MVE_VCVTu32f32a 1081 UINT64_C(4290446272), // MVE_VCVTu32f32m 1082 UINT64_C(4290445760), // MVE_VCVTu32f32n 1083 UINT64_C(4290446016), // MVE_VCVTu32f32p 1084 UINT64_C(4290447296), // MVE_VCVTu32f32z 1085 UINT64_C(3994099566), // MVE_VDDUPu16 1086 UINT64_C(3995148142), // MVE_VDDUPu32 1087 UINT64_C(3993050990), // MVE_VDDUPu8 1088 UINT64_C(4003466032), // MVE_VDUP16 1089 UINT64_C(4003466000), // MVE_VDUP32 1090 UINT64_C(4007660304), // MVE_VDUP8 1091 UINT64_C(3994099552), // MVE_VDWDUPu16 1092 UINT64_C(3995148128), // MVE_VDWDUPu32 1093 UINT64_C(3993050976), // MVE_VDWDUPu8 1094 UINT64_C(4278190416), // MVE_VEOR 1095 UINT64_C(4264631872), // MVE_VFMA_qr_Sf16 1096 UINT64_C(3996196416), // MVE_VFMA_qr_Sf32 1097 UINT64_C(4264627776), // MVE_VFMA_qr_f16 1098 UINT64_C(3996192320), // MVE_VFMA_qr_f32 1099 UINT64_C(4010806352), // MVE_VFMAf16 1100 UINT64_C(4009757776), // MVE_VFMAf32 1101 UINT64_C(4012903504), // MVE_VFMSf16 1102 UINT64_C(4011854928), // MVE_VFMSf32 1103 UINT64_C(3994029888), // MVE_VHADD_qr_s16 1104 UINT64_C(3995078464), // MVE_VHADD_qr_s32 1105 UINT64_C(3992981312), // MVE_VHADD_qr_s8 1106 UINT64_C(4262465344), // MVE_VHADD_qr_u16 1107 UINT64_C(4263513920), // MVE_VHADD_qr_u32 1108 UINT64_C(4261416768), // MVE_VHADD_qr_u8 1109 UINT64_C(4010803264), // MVE_VHADDs16 1110 UINT64_C(4011851840), // MVE_VHADDs32 1111 UINT64_C(4009754688), // MVE_VHADDs8 1112 UINT64_C(4279238720), // MVE_VHADDu16 1113 UINT64_C(4280287296), // MVE_VHADDu32 1114 UINT64_C(4278190144), // MVE_VHADDu8 1115 UINT64_C(3994029824), // MVE_VHCADDs16 1116 UINT64_C(3995078400), // MVE_VHCADDs32 1117 UINT64_C(3992981248), // MVE_VHCADDs8 1118 UINT64_C(3994033984), // MVE_VHSUB_qr_s16 1119 UINT64_C(3995082560), // MVE_VHSUB_qr_s32 1120 UINT64_C(3992985408), // MVE_VHSUB_qr_s8 1121 UINT64_C(4262469440), // MVE_VHSUB_qr_u16 1122 UINT64_C(4263518016), // MVE_VHSUB_qr_u32 1123 UINT64_C(4261420864), // MVE_VHSUB_qr_u8 1124 UINT64_C(4010803776), // MVE_VHSUBs16 1125 UINT64_C(4011852352), // MVE_VHSUBs32 1126 UINT64_C(4009755200), // MVE_VHSUBs8 1127 UINT64_C(4279239232), // MVE_VHSUBu16 1128 UINT64_C(4280287808), // MVE_VHSUBu32 1129 UINT64_C(4278190656), // MVE_VHSUBu8 1130 UINT64_C(3994095470), // MVE_VIDUPu16 1131 UINT64_C(3995144046), // MVE_VIDUPu32 1132 UINT64_C(3993046894), // MVE_VIDUPu8 1133 UINT64_C(3994095456), // MVE_VIWDUPu16 1134 UINT64_C(3995144032), // MVE_VIWDUPu32 1135 UINT64_C(3993046880), // MVE_VIWDUPu8 1136 UINT64_C(4237303424), // MVE_VLD20_16 1137 UINT64_C(4239400576), // MVE_VLD20_16_wb 1138 UINT64_C(4237303552), // MVE_VLD20_32 1139 UINT64_C(4239400704), // MVE_VLD20_32_wb 1140 UINT64_C(4237303296), // MVE_VLD20_8 1141 UINT64_C(4239400448), // MVE_VLD20_8_wb 1142 UINT64_C(4237303456), // MVE_VLD21_16 1143 UINT64_C(4239400608), // MVE_VLD21_16_wb 1144 UINT64_C(4237303584), // MVE_VLD21_32 1145 UINT64_C(4239400736), // MVE_VLD21_32_wb 1146 UINT64_C(4237303328), // MVE_VLD21_8 1147 UINT64_C(4239400480), // MVE_VLD21_8_wb 1148 UINT64_C(4237303425), // MVE_VLD40_16 1149 UINT64_C(4239400577), // MVE_VLD40_16_wb 1150 UINT64_C(4237303553), // MVE_VLD40_32 1151 UINT64_C(4239400705), // MVE_VLD40_32_wb 1152 UINT64_C(4237303297), // MVE_VLD40_8 1153 UINT64_C(4239400449), // MVE_VLD40_8_wb 1154 UINT64_C(4237303457), // MVE_VLD41_16 1155 UINT64_C(4239400609), // MVE_VLD41_16_wb 1156 UINT64_C(4237303585), // MVE_VLD41_32 1157 UINT64_C(4239400737), // MVE_VLD41_32_wb 1158 UINT64_C(4237303329), // MVE_VLD41_8 1159 UINT64_C(4239400481), // MVE_VLD41_8_wb 1160 UINT64_C(4237303489), // MVE_VLD42_16 1161 UINT64_C(4239400641), // MVE_VLD42_16_wb 1162 UINT64_C(4237303617), // MVE_VLD42_32 1163 UINT64_C(4239400769), // MVE_VLD42_32_wb 1164 UINT64_C(4237303361), // MVE_VLD42_8 1165 UINT64_C(4239400513), // MVE_VLD42_8_wb 1166 UINT64_C(4237303521), // MVE_VLD43_16 1167 UINT64_C(4239400673), // MVE_VLD43_16_wb 1168 UINT64_C(4237303649), // MVE_VLD43_32 1169 UINT64_C(4239400801), // MVE_VLD43_32_wb 1170 UINT64_C(4237303393), // MVE_VLD43_8 1171 UINT64_C(4239400545), // MVE_VLD43_8_wb 1172 UINT64_C(3977252480), // MVE_VLDRBS16 1173 UINT64_C(3962572416), // MVE_VLDRBS16_post 1174 UINT64_C(3979349632), // MVE_VLDRBS16_pre 1175 UINT64_C(3968863872), // MVE_VLDRBS16_rq 1176 UINT64_C(3977252608), // MVE_VLDRBS32 1177 UINT64_C(3962572544), // MVE_VLDRBS32_post 1178 UINT64_C(3979349760), // MVE_VLDRBS32_pre 1179 UINT64_C(3968864000), // MVE_VLDRBS32_rq 1180 UINT64_C(4245687936), // MVE_VLDRBU16 1181 UINT64_C(4231007872), // MVE_VLDRBU16_post 1182 UINT64_C(4247785088), // MVE_VLDRBU16_pre 1183 UINT64_C(4237299328), // MVE_VLDRBU16_rq 1184 UINT64_C(4245688064), // MVE_VLDRBU32 1185 UINT64_C(4231008000), // MVE_VLDRBU32_post 1186 UINT64_C(4247785216), // MVE_VLDRBU32_pre 1187 UINT64_C(4237299456), // MVE_VLDRBU32_rq 1188 UINT64_C(3977256448), // MVE_VLDRBU8 1189 UINT64_C(3962576384), // MVE_VLDRBU8_post 1190 UINT64_C(3979353600), // MVE_VLDRBU8_pre 1191 UINT64_C(4237299200), // MVE_VLDRBU8_rq 1192 UINT64_C(4245692160), // MVE_VLDRDU64_qi 1193 UINT64_C(4247789312), // MVE_VLDRDU64_qi_pre 1194 UINT64_C(4237299665), // MVE_VLDRDU64_rq 1195 UINT64_C(4237299664), // MVE_VLDRDU64_rq_u 1196 UINT64_C(3977776896), // MVE_VLDRHS32 1197 UINT64_C(3963096832), // MVE_VLDRHS32_post 1198 UINT64_C(3979874048), // MVE_VLDRHS32_pre 1199 UINT64_C(3968864017), // MVE_VLDRHS32_rq 1200 UINT64_C(3968864016), // MVE_VLDRHS32_rq_u 1201 UINT64_C(3977256576), // MVE_VLDRHU16 1202 UINT64_C(3962576512), // MVE_VLDRHU16_post 1203 UINT64_C(3979353728), // MVE_VLDRHU16_pre 1204 UINT64_C(4237299345), // MVE_VLDRHU16_rq 1205 UINT64_C(4237299344), // MVE_VLDRHU16_rq_u 1206 UINT64_C(4246212352), // MVE_VLDRHU32 1207 UINT64_C(4231532288), // MVE_VLDRHU32_post 1208 UINT64_C(4248309504), // MVE_VLDRHU32_pre 1209 UINT64_C(4237299473), // MVE_VLDRHU32_rq 1210 UINT64_C(4237299472), // MVE_VLDRHU32_rq_u 1211 UINT64_C(3977256704), // MVE_VLDRWU32 1212 UINT64_C(3962576640), // MVE_VLDRWU32_post 1213 UINT64_C(3979353856), // MVE_VLDRWU32_pre 1214 UINT64_C(4245691904), // MVE_VLDRWU32_qi 1215 UINT64_C(4247789056), // MVE_VLDRWU32_qi_pre 1216 UINT64_C(4237299521), // MVE_VLDRWU32_rq 1217 UINT64_C(4237299520), // MVE_VLDRWU32_rq_u 1218 UINT64_C(4007923456), // MVE_VMAXAVs16 1219 UINT64_C(4008185600), // MVE_VMAXAVs32 1220 UINT64_C(4007661312), // MVE_VMAXAVs8 1221 UINT64_C(3996585601), // MVE_VMAXAs16 1222 UINT64_C(3996847745), // MVE_VMAXAs32 1223 UINT64_C(3996323457), // MVE_VMAXAs8 1224 UINT64_C(4276883200), // MVE_VMAXNMAVf16 1225 UINT64_C(4008447744), // MVE_VMAXNMAVf32 1226 UINT64_C(4265545345), // MVE_VMAXNMAf16 1227 UINT64_C(3997109889), // MVE_VMAXNMAf32 1228 UINT64_C(4277014272), // MVE_VMAXNMVf16 1229 UINT64_C(4008578816), // MVE_VMAXNMVf32 1230 UINT64_C(4279242576), // MVE_VMAXNMf16 1231 UINT64_C(4278194000), // MVE_VMAXNMf32 1232 UINT64_C(4008054528), // MVE_VMAXVs16 1233 UINT64_C(4008316672), // MVE_VMAXVs32 1234 UINT64_C(4007792384), // MVE_VMAXVs8 1235 UINT64_C(4276489984), // MVE_VMAXVu16 1236 UINT64_C(4276752128), // MVE_VMAXVu32 1237 UINT64_C(4276227840), // MVE_VMAXVu8 1238 UINT64_C(4010804800), // MVE_VMAXs16 1239 UINT64_C(4011853376), // MVE_VMAXs32 1240 UINT64_C(4009756224), // MVE_VMAXs8 1241 UINT64_C(4279240256), // MVE_VMAXu16 1242 UINT64_C(4280288832), // MVE_VMAXu32 1243 UINT64_C(4278191680), // MVE_VMAXu8 1244 UINT64_C(4007923584), // MVE_VMINAVs16 1245 UINT64_C(4008185728), // MVE_VMINAVs32 1246 UINT64_C(4007661440), // MVE_VMINAVs8 1247 UINT64_C(3996589697), // MVE_VMINAs16 1248 UINT64_C(3996851841), // MVE_VMINAs32 1249 UINT64_C(3996327553), // MVE_VMINAs8 1250 UINT64_C(4276883328), // MVE_VMINNMAVf16 1251 UINT64_C(4008447872), // MVE_VMINNMAVf32 1252 UINT64_C(4265549441), // MVE_VMINNMAf16 1253 UINT64_C(3997113985), // MVE_VMINNMAf32 1254 UINT64_C(4277014400), // MVE_VMINNMVf16 1255 UINT64_C(4008578944), // MVE_VMINNMVf32 1256 UINT64_C(4281339728), // MVE_VMINNMf16 1257 UINT64_C(4280291152), // MVE_VMINNMf32 1258 UINT64_C(4008054656), // MVE_VMINVs16 1259 UINT64_C(4008316800), // MVE_VMINVs32 1260 UINT64_C(4007792512), // MVE_VMINVs8 1261 UINT64_C(4276490112), // MVE_VMINVu16 1262 UINT64_C(4276752256), // MVE_VMINVu32 1263 UINT64_C(4276227968), // MVE_VMINVu8 1264 UINT64_C(4010804816), // MVE_VMINs16 1265 UINT64_C(4011853392), // MVE_VMINs32 1266 UINT64_C(4009756240), // MVE_VMINs8 1267 UINT64_C(4279240272), // MVE_VMINu16 1268 UINT64_C(4280288848), // MVE_VMINu32 1269 UINT64_C(4278191696), // MVE_VMINu8 1270 UINT64_C(4008709664), // MVE_VMLADAVas16 1271 UINT64_C(4008775200), // MVE_VMLADAVas32 1272 UINT64_C(4008709920), // MVE_VMLADAVas8 1273 UINT64_C(4277145120), // MVE_VMLADAVau16 1274 UINT64_C(4277210656), // MVE_VMLADAVau32 1275 UINT64_C(4277145376), // MVE_VMLADAVau8 1276 UINT64_C(4008713760), // MVE_VMLADAVaxs16 1277 UINT64_C(4008779296), // MVE_VMLADAVaxs32 1278 UINT64_C(4008714016), // MVE_VMLADAVaxs8 1279 UINT64_C(4008709632), // MVE_VMLADAVs16 1280 UINT64_C(4008775168), // MVE_VMLADAVs32 1281 UINT64_C(4008709888), // MVE_VMLADAVs8 1282 UINT64_C(4277145088), // MVE_VMLADAVu16 1283 UINT64_C(4277210624), // MVE_VMLADAVu32 1284 UINT64_C(4277145344), // MVE_VMLADAVu8 1285 UINT64_C(4008713728), // MVE_VMLADAVxs16 1286 UINT64_C(4008779264), // MVE_VMLADAVxs32 1287 UINT64_C(4008713984), // MVE_VMLADAVxs8 1288 UINT64_C(4001369632), // MVE_VMLALDAVas16 1289 UINT64_C(4001435168), // MVE_VMLALDAVas32 1290 UINT64_C(4269805088), // MVE_VMLALDAVau16 1291 UINT64_C(4269870624), // MVE_VMLALDAVau32 1292 UINT64_C(4001373728), // MVE_VMLALDAVaxs16 1293 UINT64_C(4001439264), // MVE_VMLALDAVaxs32 1294 UINT64_C(4001369600), // MVE_VMLALDAVs16 1295 UINT64_C(4001435136), // MVE_VMLALDAVs32 1296 UINT64_C(4269805056), // MVE_VMLALDAVu16 1297 UINT64_C(4269870592), // MVE_VMLALDAVu32 1298 UINT64_C(4001373696), // MVE_VMLALDAVxs16 1299 UINT64_C(4001439232), // MVE_VMLALDAVxs32 1300 UINT64_C(3994099264), // MVE_VMLAS_qr_i16 1301 UINT64_C(3995147840), // MVE_VMLAS_qr_i32 1302 UINT64_C(3993050688), // MVE_VMLAS_qr_i8 1303 UINT64_C(3994095168), // MVE_VMLA_qr_i16 1304 UINT64_C(3995143744), // MVE_VMLA_qr_i32 1305 UINT64_C(3993046592), // MVE_VMLA_qr_i8 1306 UINT64_C(4008709665), // MVE_VMLSDAVas16 1307 UINT64_C(4008775201), // MVE_VMLSDAVas32 1308 UINT64_C(4277145121), // MVE_VMLSDAVas8 1309 UINT64_C(4008713761), // MVE_VMLSDAVaxs16 1310 UINT64_C(4008779297), // MVE_VMLSDAVaxs32 1311 UINT64_C(4277149217), // MVE_VMLSDAVaxs8 1312 UINT64_C(4008709633), // MVE_VMLSDAVs16 1313 UINT64_C(4008775169), // MVE_VMLSDAVs32 1314 UINT64_C(4277145089), // MVE_VMLSDAVs8 1315 UINT64_C(4008713729), // MVE_VMLSDAVxs16 1316 UINT64_C(4008779265), // MVE_VMLSDAVxs32 1317 UINT64_C(4277149185), // MVE_VMLSDAVxs8 1318 UINT64_C(4001369633), // MVE_VMLSLDAVas16 1319 UINT64_C(4001435169), // MVE_VMLSLDAVas32 1320 UINT64_C(4001373729), // MVE_VMLSLDAVaxs16 1321 UINT64_C(4001439265), // MVE_VMLSLDAVaxs32 1322 UINT64_C(4001369601), // MVE_VMLSLDAVs16 1323 UINT64_C(4001435137), // MVE_VMLSLDAVs32 1324 UINT64_C(4001373697), // MVE_VMLSLDAVxs16 1325 UINT64_C(4001439233), // MVE_VMLSLDAVxs32 1326 UINT64_C(4004515648), // MVE_VMOVLs16bh 1327 UINT64_C(4004519744), // MVE_VMOVLs16th 1328 UINT64_C(4003991360), // MVE_VMOVLs8bh 1329 UINT64_C(4003995456), // MVE_VMOVLs8th 1330 UINT64_C(4272951104), // MVE_VMOVLu16bh 1331 UINT64_C(4272955200), // MVE_VMOVLu16th 1332 UINT64_C(4272426816), // MVE_VMOVLu8bh 1333 UINT64_C(4272430912), // MVE_VMOVLu8th 1334 UINT64_C(4264627841), // MVE_VMOVNi16bh 1335 UINT64_C(4264631937), // MVE_VMOVNi16th 1336 UINT64_C(4264889985), // MVE_VMOVNi32bh 1337 UINT64_C(4264894081), // MVE_VMOVNi32th 1338 UINT64_C(3994028816), // MVE_VMOV_from_lane_32 1339 UINT64_C(3994028848), // MVE_VMOV_from_lane_s16 1340 UINT64_C(3998223120), // MVE_VMOV_from_lane_s8 1341 UINT64_C(4002417456), // MVE_VMOV_from_lane_u16 1342 UINT64_C(4006611728), // MVE_VMOV_from_lane_u8 1343 UINT64_C(3960475392), // MVE_VMOV_q_rr 1344 UINT64_C(3959426816), // MVE_VMOV_rr_q 1345 UINT64_C(3992980272), // MVE_VMOV_to_lane_16 1346 UINT64_C(3992980240), // MVE_VMOV_to_lane_32 1347 UINT64_C(3997174544), // MVE_VMOV_to_lane_8 1348 UINT64_C(4018147152), // MVE_VMOVimmf32 1349 UINT64_C(4018145360), // MVE_VMOVimmi16 1350 UINT64_C(4018143312), // MVE_VMOVimmi32 1351 UINT64_C(4018146928), // MVE_VMOVimmi64 1352 UINT64_C(4018146896), // MVE_VMOVimmi8 1353 UINT64_C(3994095105), // MVE_VMULHs16 1354 UINT64_C(3995143681), // MVE_VMULHs32 1355 UINT64_C(3993046529), // MVE_VMULHs8 1356 UINT64_C(4262530561), // MVE_VMULHu16 1357 UINT64_C(4263579137), // MVE_VMULHu32 1358 UINT64_C(4261481985), // MVE_VMULHu8 1359 UINT64_C(4264627712), // MVE_VMULLBp16 1360 UINT64_C(3996192256), // MVE_VMULLBp8 1361 UINT64_C(3994095104), // MVE_VMULLBs16 1362 UINT64_C(3995143680), // MVE_VMULLBs32 1363 UINT64_C(3993046528), // MVE_VMULLBs8 1364 UINT64_C(4262530560), // MVE_VMULLBu16 1365 UINT64_C(4263579136), // MVE_VMULLBu32 1366 UINT64_C(4261481984), // MVE_VMULLBu8 1367 UINT64_C(4264631808), // MVE_VMULLTp16 1368 UINT64_C(3996196352), // MVE_VMULLTp8 1369 UINT64_C(3994099200), // MVE_VMULLTs16 1370 UINT64_C(3995147776), // MVE_VMULLTs32 1371 UINT64_C(3993050624), // MVE_VMULLTs8 1372 UINT64_C(4262534656), // MVE_VMULLTu16 1373 UINT64_C(4263583232), // MVE_VMULLTu32 1374 UINT64_C(4261486080), // MVE_VMULLTu8 1375 UINT64_C(4264627808), // MVE_VMUL_qr_f16 1376 UINT64_C(3996192352), // MVE_VMUL_qr_f32 1377 UINT64_C(3994099296), // MVE_VMUL_qr_i16 1378 UINT64_C(3995147872), // MVE_VMUL_qr_i32 1379 UINT64_C(3993050720), // MVE_VMUL_qr_i8 1380 UINT64_C(4279242064), // MVE_VMULf16 1381 UINT64_C(4278193488), // MVE_VMULf32 1382 UINT64_C(4010805584), // MVE_VMULi16 1383 UINT64_C(4011854160), // MVE_VMULi32 1384 UINT64_C(4009757008), // MVE_VMULi8 1385 UINT64_C(4289725888), // MVE_VMVN 1386 UINT64_C(4018145392), // MVE_VMVNimmi16 1387 UINT64_C(4018143344), // MVE_VMVNimmi32 1388 UINT64_C(4290054080), // MVE_VNEGf16 1389 UINT64_C(4290316224), // MVE_VNEGf32 1390 UINT64_C(4290053056), // MVE_VNEGs16 1391 UINT64_C(4290315200), // MVE_VNEGs32 1392 UINT64_C(4289790912), // MVE_VNEGs8 1393 UINT64_C(4012900688), // MVE_VORN 1394 UINT64_C(4011852112), // MVE_VORR 1395 UINT64_C(4018145616), // MVE_VORRimmi16 1396 UINT64_C(4018143568), // MVE_VORRimmi32 1397 UINT64_C(4264628045), // MVE_VPNOT 1398 UINT64_C(4264627969), // MVE_VPSEL 1399 UINT64_C(4264628045), // MVE_VPST 1400 UINT64_C(4261482240), // MVE_VPTv16i8 1401 UINT64_C(4261482304), // MVE_VPTv16i8r 1402 UINT64_C(4261486336), // MVE_VPTv16s8 1403 UINT64_C(4261486400), // MVE_VPTv16s8r 1404 UINT64_C(4261482241), // MVE_VPTv16u8 1405 UINT64_C(4261482336), // MVE_VPTv16u8r 1406 UINT64_C(3996192512), // MVE_VPTv4f32 1407 UINT64_C(3996192576), // MVE_VPTv4f32r 1408 UINT64_C(4263579392), // MVE_VPTv4i32 1409 UINT64_C(4263579456), // MVE_VPTv4i32r 1410 UINT64_C(4263583488), // MVE_VPTv4s32 1411 UINT64_C(4263583552), // MVE_VPTv4s32r 1412 UINT64_C(4263579393), // MVE_VPTv4u32 1413 UINT64_C(4263579488), // MVE_VPTv4u32r 1414 UINT64_C(4264627968), // MVE_VPTv8f16 1415 UINT64_C(4264628032), // MVE_VPTv8f16r 1416 UINT64_C(4262530816), // MVE_VPTv8i16 1417 UINT64_C(4262530880), // MVE_VPTv8i16r 1418 UINT64_C(4262534912), // MVE_VPTv8s16 1419 UINT64_C(4262534976), // MVE_VPTv8s16r 1420 UINT64_C(4262530817), // MVE_VPTv8u16 1421 UINT64_C(4262530912), // MVE_VPTv8u16r 1422 UINT64_C(4289988416), // MVE_VQABSs16 1423 UINT64_C(4290250560), // MVE_VQABSs32 1424 UINT64_C(4289726272), // MVE_VQABSs8 1425 UINT64_C(3994029920), // MVE_VQADD_qr_s16 1426 UINT64_C(3995078496), // MVE_VQADD_qr_s32 1427 UINT64_C(3992981344), // MVE_VQADD_qr_s8 1428 UINT64_C(4262465376), // MVE_VQADD_qr_u16 1429 UINT64_C(4263513952), // MVE_VQADD_qr_u32 1430 UINT64_C(4261416800), // MVE_VQADD_qr_u8 1431 UINT64_C(4010803280), // MVE_VQADDs16 1432 UINT64_C(4011851856), // MVE_VQADDs32 1433 UINT64_C(4009754704), // MVE_VQADDs8 1434 UINT64_C(4279238736), // MVE_VQADDu16 1435 UINT64_C(4280287312), // MVE_VQADDu32 1436 UINT64_C(4278190160), // MVE_VQADDu8 1437 UINT64_C(3994033664), // MVE_VQDMLADHXs16 1438 UINT64_C(3995082240), // MVE_VQDMLADHXs32 1439 UINT64_C(3992985088), // MVE_VQDMLADHXs8 1440 UINT64_C(3994029568), // MVE_VQDMLADHs16 1441 UINT64_C(3995078144), // MVE_VQDMLADHs32 1442 UINT64_C(3992980992), // MVE_VQDMLADHs8 1443 UINT64_C(3994029664), // MVE_VQDMLAH_qrs16 1444 UINT64_C(3995078240), // MVE_VQDMLAH_qrs32 1445 UINT64_C(3992981088), // MVE_VQDMLAH_qrs8 1446 UINT64_C(3994033760), // MVE_VQDMLASH_qrs16 1447 UINT64_C(3995082336), // MVE_VQDMLASH_qrs32 1448 UINT64_C(3992985184), // MVE_VQDMLASH_qrs8 1449 UINT64_C(4262469120), // MVE_VQDMLSDHXs16 1450 UINT64_C(4263517696), // MVE_VQDMLSDHXs32 1451 UINT64_C(4261420544), // MVE_VQDMLSDHXs8 1452 UINT64_C(4262465024), // MVE_VQDMLSDHs16 1453 UINT64_C(4263513600), // MVE_VQDMLSDHs32 1454 UINT64_C(4261416448), // MVE_VQDMLSDHs8 1455 UINT64_C(3994095200), // MVE_VQDMULH_qr_s16 1456 UINT64_C(3995143776), // MVE_VQDMULH_qr_s32 1457 UINT64_C(3993046624), // MVE_VQDMULH_qr_s8 1458 UINT64_C(4010806080), // MVE_VQDMULHi16 1459 UINT64_C(4011854656), // MVE_VQDMULHi32 1460 UINT64_C(4009757504), // MVE_VQDMULHi8 1461 UINT64_C(3996127072), // MVE_VQDMULL_qr_s16bh 1462 UINT64_C(3996131168), // MVE_VQDMULL_qr_s16th 1463 UINT64_C(4264562528), // MVE_VQDMULL_qr_s32bh 1464 UINT64_C(4264566624), // MVE_VQDMULL_qr_s32th 1465 UINT64_C(3996126977), // MVE_VQDMULLs16bh 1466 UINT64_C(3996131073), // MVE_VQDMULLs16th 1467 UINT64_C(4264562433), // MVE_VQDMULLs32bh 1468 UINT64_C(4264566529), // MVE_VQDMULLs32th 1469 UINT64_C(3996323329), // MVE_VQMOVNs16bh 1470 UINT64_C(3996327425), // MVE_VQMOVNs16th 1471 UINT64_C(3996585473), // MVE_VQMOVNs32bh 1472 UINT64_C(3996589569), // MVE_VQMOVNs32th 1473 UINT64_C(4264758785), // MVE_VQMOVNu16bh 1474 UINT64_C(4264762881), // MVE_VQMOVNu16th 1475 UINT64_C(4265020929), // MVE_VQMOVNu32bh 1476 UINT64_C(4265025025), // MVE_VQMOVNu32th 1477 UINT64_C(3996192385), // MVE_VQMOVUNs16bh 1478 UINT64_C(3996196481), // MVE_VQMOVUNs16th 1479 UINT64_C(3996454529), // MVE_VQMOVUNs32bh 1480 UINT64_C(3996458625), // MVE_VQMOVUNs32th 1481 UINT64_C(4289988544), // MVE_VQNEGs16 1482 UINT64_C(4290250688), // MVE_VQNEGs32 1483 UINT64_C(4289726400), // MVE_VQNEGs8 1484 UINT64_C(3994033665), // MVE_VQRDMLADHXs16 1485 UINT64_C(3995082241), // MVE_VQRDMLADHXs32 1486 UINT64_C(3992985089), // MVE_VQRDMLADHXs8 1487 UINT64_C(3994029569), // MVE_VQRDMLADHs16 1488 UINT64_C(3995078145), // MVE_VQRDMLADHs32 1489 UINT64_C(3992980993), // MVE_VQRDMLADHs8 1490 UINT64_C(3994029632), // MVE_VQRDMLAH_qrs16 1491 UINT64_C(3995078208), // MVE_VQRDMLAH_qrs32 1492 UINT64_C(3992981056), // MVE_VQRDMLAH_qrs8 1493 UINT64_C(3994033728), // MVE_VQRDMLASH_qrs16 1494 UINT64_C(3995082304), // MVE_VQRDMLASH_qrs32 1495 UINT64_C(3992985152), // MVE_VQRDMLASH_qrs8 1496 UINT64_C(4262469121), // MVE_VQRDMLSDHXs16 1497 UINT64_C(4263517697), // MVE_VQRDMLSDHXs32 1498 UINT64_C(4261420545), // MVE_VQRDMLSDHXs8 1499 UINT64_C(4262465025), // MVE_VQRDMLSDHs16 1500 UINT64_C(4263513601), // MVE_VQRDMLSDHs32 1501 UINT64_C(4261416449), // MVE_VQRDMLSDHs8 1502 UINT64_C(4262530656), // MVE_VQRDMULH_qr_s16 1503 UINT64_C(4263579232), // MVE_VQRDMULH_qr_s32 1504 UINT64_C(4261482080), // MVE_VQRDMULH_qr_s8 1505 UINT64_C(4279241536), // MVE_VQRDMULHi16 1506 UINT64_C(4280290112), // MVE_VQRDMULHi32 1507 UINT64_C(4278192960), // MVE_VQRDMULHi8 1508 UINT64_C(4010804560), // MVE_VQRSHL_by_vecs16 1509 UINT64_C(4011853136), // MVE_VQRSHL_by_vecs32 1510 UINT64_C(4009755984), // MVE_VQRSHL_by_vecs8 1511 UINT64_C(4279240016), // MVE_VQRSHL_by_vecu16 1512 UINT64_C(4280288592), // MVE_VQRSHL_by_vecu32 1513 UINT64_C(4278191440), // MVE_VQRSHL_by_vecu8 1514 UINT64_C(3996589792), // MVE_VQRSHL_qrs16 1515 UINT64_C(3996851936), // MVE_VQRSHL_qrs32 1516 UINT64_C(3996327648), // MVE_VQRSHL_qrs8 1517 UINT64_C(4265025248), // MVE_VQRSHL_qru16 1518 UINT64_C(4265287392), // MVE_VQRSHL_qru32 1519 UINT64_C(4264763104), // MVE_VQRSHL_qru8 1520 UINT64_C(4001894209), // MVE_VQRSHRNbhs16 1521 UINT64_C(4002418497), // MVE_VQRSHRNbhs32 1522 UINT64_C(4270329665), // MVE_VQRSHRNbhu16 1523 UINT64_C(4270853953), // MVE_VQRSHRNbhu32 1524 UINT64_C(4001898305), // MVE_VQRSHRNths16 1525 UINT64_C(4002422593), // MVE_VQRSHRNths32 1526 UINT64_C(4270333761), // MVE_VQRSHRNthu16 1527 UINT64_C(4270858049), // MVE_VQRSHRNthu32 1528 UINT64_C(4270329792), // MVE_VQRSHRUNs16bh 1529 UINT64_C(4270333888), // MVE_VQRSHRUNs16th 1530 UINT64_C(4270854080), // MVE_VQRSHRUNs32bh 1531 UINT64_C(4270858176), // MVE_VQRSHRUNs32th 1532 UINT64_C(4287628880), // MVE_VQSHLU_imms16 1533 UINT64_C(4288677456), // MVE_VQSHLU_imms32 1534 UINT64_C(4287104592), // MVE_VQSHLU_imms8 1535 UINT64_C(4010804304), // MVE_VQSHL_by_vecs16 1536 UINT64_C(4011852880), // MVE_VQSHL_by_vecs32 1537 UINT64_C(4009755728), // MVE_VQSHL_by_vecs8 1538 UINT64_C(4279239760), // MVE_VQSHL_by_vecu16 1539 UINT64_C(4280288336), // MVE_VQSHL_by_vecu32 1540 UINT64_C(4278191184), // MVE_VQSHL_by_vecu8 1541 UINT64_C(3996458720), // MVE_VQSHL_qrs16 1542 UINT64_C(3996720864), // MVE_VQSHL_qrs32 1543 UINT64_C(3996196576), // MVE_VQSHL_qrs8 1544 UINT64_C(4264894176), // MVE_VQSHL_qru16 1545 UINT64_C(4265156320), // MVE_VQSHL_qru32 1546 UINT64_C(4264632032), // MVE_VQSHL_qru8 1547 UINT64_C(4019193680), // MVE_VQSHLimms16 1548 UINT64_C(4020242256), // MVE_VQSHLimms32 1549 UINT64_C(4018669392), // MVE_VQSHLimms8 1550 UINT64_C(4287629136), // MVE_VQSHLimmu16 1551 UINT64_C(4288677712), // MVE_VQSHLimmu32 1552 UINT64_C(4287104848), // MVE_VQSHLimmu8 1553 UINT64_C(4001894208), // MVE_VQSHRNbhs16 1554 UINT64_C(4002418496), // MVE_VQSHRNbhs32 1555 UINT64_C(4270329664), // MVE_VQSHRNbhu16 1556 UINT64_C(4270853952), // MVE_VQSHRNbhu32 1557 UINT64_C(4001898304), // MVE_VQSHRNths16 1558 UINT64_C(4002422592), // MVE_VQSHRNths32 1559 UINT64_C(4270333760), // MVE_VQSHRNthu16 1560 UINT64_C(4270858048), // MVE_VQSHRNthu32 1561 UINT64_C(4001894336), // MVE_VQSHRUNs16bh 1562 UINT64_C(4001898432), // MVE_VQSHRUNs16th 1563 UINT64_C(4002418624), // MVE_VQSHRUNs32bh 1564 UINT64_C(4002422720), // MVE_VQSHRUNs32th 1565 UINT64_C(3994034016), // MVE_VQSUB_qr_s16 1566 UINT64_C(3995082592), // MVE_VQSUB_qr_s32 1567 UINT64_C(3992985440), // MVE_VQSUB_qr_s8 1568 UINT64_C(4262469472), // MVE_VQSUB_qr_u16 1569 UINT64_C(4263518048), // MVE_VQSUB_qr_u32 1570 UINT64_C(4261420896), // MVE_VQSUB_qr_u8 1571 UINT64_C(4010803792), // MVE_VQSUBs16 1572 UINT64_C(4011852368), // MVE_VQSUBs32 1573 UINT64_C(4009755216), // MVE_VQSUBs8 1574 UINT64_C(4279239248), // MVE_VQSUBu16 1575 UINT64_C(4280287824), // MVE_VQSUBu32 1576 UINT64_C(4278190672), // MVE_VQSUBu8 1577 UINT64_C(4289724736), // MVE_VREV16_8 1578 UINT64_C(4289986752), // MVE_VREV32_16 1579 UINT64_C(4289724608), // MVE_VREV32_8 1580 UINT64_C(4289986624), // MVE_VREV64_16 1581 UINT64_C(4290248768), // MVE_VREV64_32 1582 UINT64_C(4289724480), // MVE_VREV64_8 1583 UINT64_C(4010803520), // MVE_VRHADDs16 1584 UINT64_C(4011852096), // MVE_VRHADDs32 1585 UINT64_C(4009754944), // MVE_VRHADDs8 1586 UINT64_C(4279238976), // MVE_VRHADDu16 1587 UINT64_C(4280287552), // MVE_VRHADDu32 1588 UINT64_C(4278190400), // MVE_VRHADDu8 1589 UINT64_C(4290118976), // MVE_VRINTf16A 1590 UINT64_C(4290119360), // MVE_VRINTf16M 1591 UINT64_C(4290118720), // MVE_VRINTf16N 1592 UINT64_C(4290119616), // MVE_VRINTf16P 1593 UINT64_C(4290118848), // MVE_VRINTf16X 1594 UINT64_C(4290119104), // MVE_VRINTf16Z 1595 UINT64_C(4290381120), // MVE_VRINTf32A 1596 UINT64_C(4290381504), // MVE_VRINTf32M 1597 UINT64_C(4290380864), // MVE_VRINTf32N 1598 UINT64_C(4290381760), // MVE_VRINTf32P 1599 UINT64_C(4290380992), // MVE_VRINTf32X 1600 UINT64_C(4290381248), // MVE_VRINTf32Z 1601 UINT64_C(4001369888), // MVE_VRMLALDAVHas32 1602 UINT64_C(4269805344), // MVE_VRMLALDAVHau32 1603 UINT64_C(4001373984), // MVE_VRMLALDAVHaxs32 1604 UINT64_C(4001369856), // MVE_VRMLALDAVHs32 1605 UINT64_C(4269805312), // MVE_VRMLALDAVHu32 1606 UINT64_C(4001373952), // MVE_VRMLALDAVHxs32 1607 UINT64_C(4269805089), // MVE_VRMLSLDAVHas32 1608 UINT64_C(4269809185), // MVE_VRMLSLDAVHaxs32 1609 UINT64_C(4269805057), // MVE_VRMLSLDAVHs32 1610 UINT64_C(4269809153), // MVE_VRMLSLDAVHxs32 1611 UINT64_C(3994099201), // MVE_VRMULHs16 1612 UINT64_C(3995147777), // MVE_VRMULHs32 1613 UINT64_C(3993050625), // MVE_VRMULHs8 1614 UINT64_C(4262534657), // MVE_VRMULHu16 1615 UINT64_C(4263583233), // MVE_VRMULHu32 1616 UINT64_C(4261486081), // MVE_VRMULHu8 1617 UINT64_C(4010804544), // MVE_VRSHL_by_vecs16 1618 UINT64_C(4011853120), // MVE_VRSHL_by_vecs32 1619 UINT64_C(4009755968), // MVE_VRSHL_by_vecs8 1620 UINT64_C(4279240000), // MVE_VRSHL_by_vecu16 1621 UINT64_C(4280288576), // MVE_VRSHL_by_vecu32 1622 UINT64_C(4278191424), // MVE_VRSHL_by_vecu8 1623 UINT64_C(3996589664), // MVE_VRSHL_qrs16 1624 UINT64_C(3996851808), // MVE_VRSHL_qrs32 1625 UINT64_C(3996327520), // MVE_VRSHL_qrs8 1626 UINT64_C(4265025120), // MVE_VRSHL_qru16 1627 UINT64_C(4265287264), // MVE_VRSHL_qru32 1628 UINT64_C(4264762976), // MVE_VRSHL_qru8 1629 UINT64_C(4270329793), // MVE_VRSHRNi16bh 1630 UINT64_C(4270333889), // MVE_VRSHRNi16th 1631 UINT64_C(4270854081), // MVE_VRSHRNi32bh 1632 UINT64_C(4270858177), // MVE_VRSHRNi32th 1633 UINT64_C(4019192400), // MVE_VRSHR_imms16 1634 UINT64_C(4020240976), // MVE_VRSHR_imms32 1635 UINT64_C(4018668112), // MVE_VRSHR_imms8 1636 UINT64_C(4287627856), // MVE_VRSHR_immu16 1637 UINT64_C(4288676432), // MVE_VRSHR_immu32 1638 UINT64_C(4287103568), // MVE_VRSHR_immu8 1639 UINT64_C(4264562432), // MVE_VSBC 1640 UINT64_C(4264566528), // MVE_VSBCI 1641 UINT64_C(4003467200), // MVE_VSHLC 1642 UINT64_C(4004515648), // MVE_VSHLL_imms16bh 1643 UINT64_C(4004519744), // MVE_VSHLL_imms16th 1644 UINT64_C(4003991360), // MVE_VSHLL_imms8bh 1645 UINT64_C(4003995456), // MVE_VSHLL_imms8th 1646 UINT64_C(4272951104), // MVE_VSHLL_immu16bh 1647 UINT64_C(4272955200), // MVE_VSHLL_immu16th 1648 UINT64_C(4272426816), // MVE_VSHLL_immu8bh 1649 UINT64_C(4272430912), // MVE_VSHLL_immu8th 1650 UINT64_C(3996454401), // MVE_VSHLL_lws16bh 1651 UINT64_C(3996458497), // MVE_VSHLL_lws16th 1652 UINT64_C(3996192257), // MVE_VSHLL_lws8bh 1653 UINT64_C(3996196353), // MVE_VSHLL_lws8th 1654 UINT64_C(4264889857), // MVE_VSHLL_lwu16bh 1655 UINT64_C(4264893953), // MVE_VSHLL_lwu16th 1656 UINT64_C(4264627713), // MVE_VSHLL_lwu8bh 1657 UINT64_C(4264631809), // MVE_VSHLL_lwu8th 1658 UINT64_C(4010804288), // MVE_VSHL_by_vecs16 1659 UINT64_C(4011852864), // MVE_VSHL_by_vecs32 1660 UINT64_C(4009755712), // MVE_VSHL_by_vecs8 1661 UINT64_C(4279239744), // MVE_VSHL_by_vecu16 1662 UINT64_C(4280288320), // MVE_VSHL_by_vecu32 1663 UINT64_C(4278191168), // MVE_VSHL_by_vecu8 1664 UINT64_C(4019193168), // MVE_VSHL_immi16 1665 UINT64_C(4020241744), // MVE_VSHL_immi32 1666 UINT64_C(4018668880), // MVE_VSHL_immi8 1667 UINT64_C(3996458592), // MVE_VSHL_qrs16 1668 UINT64_C(3996720736), // MVE_VSHL_qrs32 1669 UINT64_C(3996196448), // MVE_VSHL_qrs8 1670 UINT64_C(4264894048), // MVE_VSHL_qru16 1671 UINT64_C(4265156192), // MVE_VSHL_qru32 1672 UINT64_C(4264631904), // MVE_VSHL_qru8 1673 UINT64_C(4001894337), // MVE_VSHRNi16bh 1674 UINT64_C(4001898433), // MVE_VSHRNi16th 1675 UINT64_C(4002418625), // MVE_VSHRNi32bh 1676 UINT64_C(4002422721), // MVE_VSHRNi32th 1677 UINT64_C(4019191888), // MVE_VSHR_imms16 1678 UINT64_C(4020240464), // MVE_VSHR_imms32 1679 UINT64_C(4018667600), // MVE_VSHR_imms8 1680 UINT64_C(4287627344), // MVE_VSHR_immu16 1681 UINT64_C(4288675920), // MVE_VSHR_immu32 1682 UINT64_C(4287103056), // MVE_VSHR_immu8 1683 UINT64_C(4287628624), // MVE_VSLIimm16 1684 UINT64_C(4288677200), // MVE_VSLIimm32 1685 UINT64_C(4287104336), // MVE_VSLIimm8 1686 UINT64_C(4287628368), // MVE_VSRIimm16 1687 UINT64_C(4288676944), // MVE_VSRIimm32 1688 UINT64_C(4287104080), // MVE_VSRIimm8 1689 UINT64_C(4236254848), // MVE_VST20_16 1690 UINT64_C(4238352000), // MVE_VST20_16_wb 1691 UINT64_C(4236254976), // MVE_VST20_32 1692 UINT64_C(4238352128), // MVE_VST20_32_wb 1693 UINT64_C(4236254720), // MVE_VST20_8 1694 UINT64_C(4238351872), // MVE_VST20_8_wb 1695 UINT64_C(4236254880), // MVE_VST21_16 1696 UINT64_C(4238352032), // MVE_VST21_16_wb 1697 UINT64_C(4236255008), // MVE_VST21_32 1698 UINT64_C(4238352160), // MVE_VST21_32_wb 1699 UINT64_C(4236254752), // MVE_VST21_8 1700 UINT64_C(4238351904), // MVE_VST21_8_wb 1701 UINT64_C(4236254849), // MVE_VST40_16 1702 UINT64_C(4238352001), // MVE_VST40_16_wb 1703 UINT64_C(4236254977), // MVE_VST40_32 1704 UINT64_C(4238352129), // MVE_VST40_32_wb 1705 UINT64_C(4236254721), // MVE_VST40_8 1706 UINT64_C(4238351873), // MVE_VST40_8_wb 1707 UINT64_C(4236254881), // MVE_VST41_16 1708 UINT64_C(4238352033), // MVE_VST41_16_wb 1709 UINT64_C(4236255009), // MVE_VST41_32 1710 UINT64_C(4238352161), // MVE_VST41_32_wb 1711 UINT64_C(4236254753), // MVE_VST41_8 1712 UINT64_C(4238351905), // MVE_VST41_8_wb 1713 UINT64_C(4236254913), // MVE_VST42_16 1714 UINT64_C(4238352065), // MVE_VST42_16_wb 1715 UINT64_C(4236255041), // MVE_VST42_32 1716 UINT64_C(4238352193), // MVE_VST42_32_wb 1717 UINT64_C(4236254785), // MVE_VST42_8 1718 UINT64_C(4238351937), // MVE_VST42_8_wb 1719 UINT64_C(4236254945), // MVE_VST43_16 1720 UINT64_C(4238352097), // MVE_VST43_16_wb 1721 UINT64_C(4236255073), // MVE_VST43_32 1722 UINT64_C(4238352225), // MVE_VST43_32_wb 1723 UINT64_C(4236254817), // MVE_VST43_8 1724 UINT64_C(4238351969), // MVE_VST43_8_wb 1725 UINT64_C(3976203904), // MVE_VSTRB16 1726 UINT64_C(3961523840), // MVE_VSTRB16_post 1727 UINT64_C(3978301056), // MVE_VSTRB16_pre 1728 UINT64_C(3967815296), // MVE_VSTRB16_rq 1729 UINT64_C(3976204032), // MVE_VSTRB32 1730 UINT64_C(3961523968), // MVE_VSTRB32_post 1731 UINT64_C(3978301184), // MVE_VSTRB32_pre 1732 UINT64_C(3967815424), // MVE_VSTRB32_rq 1733 UINT64_C(3967815168), // MVE_VSTRB8_rq 1734 UINT64_C(3976207872), // MVE_VSTRBU8 1735 UINT64_C(3961527808), // MVE_VSTRBU8_post 1736 UINT64_C(3978305024), // MVE_VSTRBU8_pre 1737 UINT64_C(4244643584), // MVE_VSTRD64_qi 1738 UINT64_C(4246740736), // MVE_VSTRD64_qi_pre 1739 UINT64_C(3967815633), // MVE_VSTRD64_rq 1740 UINT64_C(3967815632), // MVE_VSTRD64_rq_u 1741 UINT64_C(3967815313), // MVE_VSTRH16_rq 1742 UINT64_C(3967815312), // MVE_VSTRH16_rq_u 1743 UINT64_C(3976728320), // MVE_VSTRH32 1744 UINT64_C(3962048256), // MVE_VSTRH32_post 1745 UINT64_C(3978825472), // MVE_VSTRH32_pre 1746 UINT64_C(3967815441), // MVE_VSTRH32_rq 1747 UINT64_C(3967815440), // MVE_VSTRH32_rq_u 1748 UINT64_C(3976208000), // MVE_VSTRHU16 1749 UINT64_C(3961527936), // MVE_VSTRHU16_post 1750 UINT64_C(3978305152), // MVE_VSTRHU16_pre 1751 UINT64_C(4244643328), // MVE_VSTRW32_qi 1752 UINT64_C(4246740480), // MVE_VSTRW32_qi_pre 1753 UINT64_C(3967815489), // MVE_VSTRW32_rq 1754 UINT64_C(3967815488), // MVE_VSTRW32_rq_u 1755 UINT64_C(3976208128), // MVE_VSTRWU32 1756 UINT64_C(3961528064), // MVE_VSTRWU32_post 1757 UINT64_C(3978305280), // MVE_VSTRWU32_pre 1758 UINT64_C(4264566592), // MVE_VSUB_qr_f16 1759 UINT64_C(3996131136), // MVE_VSUB_qr_f32 1760 UINT64_C(3994099520), // MVE_VSUB_qr_i16 1761 UINT64_C(3995148096), // MVE_VSUB_qr_i32 1762 UINT64_C(3993050944), // MVE_VSUB_qr_i8 1763 UINT64_C(4012903744), // MVE_VSUBf16 1764 UINT64_C(4011855168), // MVE_VSUBf32 1765 UINT64_C(4279240768), // MVE_VSUBi16 1766 UINT64_C(4280289344), // MVE_VSUBi32 1767 UINT64_C(4278192192), // MVE_VSUBi8 1768 UINT64_C(4027629569), // MVE_WLSTP_16 1769 UINT64_C(4028678145), // MVE_WLSTP_32 1770 UINT64_C(4029726721), // MVE_WLSTP_64 1771 UINT64_C(4026580993), // MVE_WLSTP_8 1772 UINT64_C(65011712), // MVNi 1773 UINT64_C(31457280), // MVNr 1774 UINT64_C(31457280), // MVNsi 1775 UINT64_C(31457296), // MVNsr 1776 UINT64_C(4076867344), // NEON_VMAXNMNDf 1777 UINT64_C(4077915920), // NEON_VMAXNMNDh 1778 UINT64_C(4076867408), // NEON_VMAXNMNQf 1779 UINT64_C(4077915984), // NEON_VMAXNMNQh 1780 UINT64_C(4078964496), // NEON_VMINNMNDf 1781 UINT64_C(4080013072), // NEON_VMINNMNDh 1782 UINT64_C(4078964560), // NEON_VMINNMNQf 1783 UINT64_C(4080013136), // NEON_VMINNMNQh 1784 UINT64_C(58720256), // ORRri 1785 UINT64_C(25165824), // ORRrr 1786 UINT64_C(25165824), // ORRrsi 1787 UINT64_C(25165840), // ORRrsr 1788 UINT64_C(109051920), // PKHBT 1789 UINT64_C(109051984), // PKHTB 1790 UINT64_C(4111527936), // PLDWi12 1791 UINT64_C(4145082368), // PLDWrs 1792 UINT64_C(4115722240), // PLDi12 1793 UINT64_C(4149276672), // PLDrs 1794 UINT64_C(4098945024), // PLIi12 1795 UINT64_C(4132499456), // PLIrs 1796 UINT64_C(16777296), // QADD 1797 UINT64_C(102764304), // QADD16 1798 UINT64_C(102764432), // QADD8 1799 UINT64_C(102764336), // QASX 1800 UINT64_C(20971600), // QDADD 1801 UINT64_C(23068752), // QDSUB 1802 UINT64_C(102764368), // QSAX 1803 UINT64_C(18874448), // QSUB 1804 UINT64_C(102764400), // QSUB16 1805 UINT64_C(102764528), // QSUB8 1806 UINT64_C(117378864), // RBIT 1807 UINT64_C(113184560), // REV 1808 UINT64_C(113184688), // REV16 1809 UINT64_C(117378992), // REVSH 1810 UINT64_C(4161800704), // RFEDA 1811 UINT64_C(4163897856), // RFEDA_UPD 1812 UINT64_C(4178577920), // RFEDB 1813 UINT64_C(4180675072), // RFEDB_UPD 1814 UINT64_C(4170189312), // RFEIA 1815 UINT64_C(4172286464), // RFEIA_UPD 1816 UINT64_C(4186966528), // RFEIB 1817 UINT64_C(4189063680), // RFEIB_UPD 1818 UINT64_C(39845888), // RSBri 1819 UINT64_C(6291456), // RSBrr 1820 UINT64_C(6291456), // RSBrsi 1821 UINT64_C(6291472), // RSBrsr 1822 UINT64_C(48234496), // RSCri 1823 UINT64_C(14680064), // RSCrr 1824 UINT64_C(14680064), // RSCrsi 1825 UINT64_C(14680080), // RSCrsr 1826 UINT64_C(101715728), // SADD16 1827 UINT64_C(101715856), // SADD8 1828 UINT64_C(101715760), // SASX 1829 UINT64_C(4118802544), // SB 1830 UINT64_C(46137344), // SBCri 1831 UINT64_C(12582912), // SBCrr 1832 UINT64_C(12582912), // SBCrsi 1833 UINT64_C(12582928), // SBCrsr 1834 UINT64_C(127926352), // SBFX 1835 UINT64_C(118550544), // SDIV 1836 UINT64_C(109055920), // SEL 1837 UINT64_C(4043374592), // SETEND 1838 UINT64_C(4044357632), // SETPAN 1839 UINT64_C(4060089408), // SHA1C 1840 UINT64_C(4088988352), // SHA1H 1841 UINT64_C(4062186560), // SHA1M 1842 UINT64_C(4061137984), // SHA1P 1843 UINT64_C(4063235136), // SHA1SU0 1844 UINT64_C(4089054080), // SHA1SU1 1845 UINT64_C(4076866624), // SHA256H 1846 UINT64_C(4077915200), // SHA256H2 1847 UINT64_C(4089054144), // SHA256SU0 1848 UINT64_C(4078963776), // SHA256SU1 1849 UINT64_C(103812880), // SHADD16 1850 UINT64_C(103813008), // SHADD8 1851 UINT64_C(103812912), // SHASX 1852 UINT64_C(103812944), // SHSAX 1853 UINT64_C(103812976), // SHSUB16 1854 UINT64_C(103813104), // SHSUB8 1855 UINT64_C(23068784), // SMC 1856 UINT64_C(16777344), // SMLABB 1857 UINT64_C(16777408), // SMLABT 1858 UINT64_C(117440528), // SMLAD 1859 UINT64_C(117440560), // SMLADX 1860 UINT64_C(14680208), // SMLAL 1861 UINT64_C(20971648), // SMLALBB 1862 UINT64_C(20971712), // SMLALBT 1863 UINT64_C(121634832), // SMLALD 1864 UINT64_C(121634864), // SMLALDX 1865 UINT64_C(20971680), // SMLALTB 1866 UINT64_C(20971744), // SMLALTT 1867 UINT64_C(16777376), // SMLATB 1868 UINT64_C(16777440), // SMLATT 1869 UINT64_C(18874496), // SMLAWB 1870 UINT64_C(18874560), // SMLAWT 1871 UINT64_C(117440592), // SMLSD 1872 UINT64_C(117440624), // SMLSDX 1873 UINT64_C(121634896), // SMLSLD 1874 UINT64_C(121634928), // SMLSLDX 1875 UINT64_C(122683408), // SMMLA 1876 UINT64_C(122683440), // SMMLAR 1877 UINT64_C(122683600), // SMMLS 1878 UINT64_C(122683632), // SMMLSR 1879 UINT64_C(122744848), // SMMUL 1880 UINT64_C(122744880), // SMMULR 1881 UINT64_C(117501968), // SMUAD 1882 UINT64_C(117502000), // SMUADX 1883 UINT64_C(23068800), // SMULBB 1884 UINT64_C(23068864), // SMULBT 1885 UINT64_C(12583056), // SMULL 1886 UINT64_C(23068832), // SMULTB 1887 UINT64_C(23068896), // SMULTT 1888 UINT64_C(18874528), // SMULWB 1889 UINT64_C(18874592), // SMULWT 1890 UINT64_C(117502032), // SMUSD 1891 UINT64_C(117502064), // SMUSDX 1892 UINT64_C(4165797120), // SRSDA 1893 UINT64_C(4167894272), // SRSDA_UPD 1894 UINT64_C(4182574336), // SRSDB 1895 UINT64_C(4184671488), // SRSDB_UPD 1896 UINT64_C(4174185728), // SRSIA 1897 UINT64_C(4176282880), // SRSIA_UPD 1898 UINT64_C(4190962944), // SRSIB 1899 UINT64_C(4193060096), // SRSIB_UPD 1900 UINT64_C(111149072), // SSAT 1901 UINT64_C(111152944), // SSAT16 1902 UINT64_C(101715792), // SSAX 1903 UINT64_C(101715824), // SSUB16 1904 UINT64_C(101715952), // SSUB8 1905 UINT64_C(4248829952), // STC2L_OFFSET 1906 UINT64_C(4240441344), // STC2L_OPTION 1907 UINT64_C(4234149888), // STC2L_POST 1908 UINT64_C(4250927104), // STC2L_PRE 1909 UINT64_C(4244635648), // STC2_OFFSET 1910 UINT64_C(4236247040), // STC2_OPTION 1911 UINT64_C(4229955584), // STC2_POST 1912 UINT64_C(4246732800), // STC2_PRE 1913 UINT64_C(222298112), // STCL_OFFSET 1914 UINT64_C(213909504), // STCL_OPTION 1915 UINT64_C(207618048), // STCL_POST 1916 UINT64_C(224395264), // STCL_PRE 1917 UINT64_C(218103808), // STC_OFFSET 1918 UINT64_C(209715200), // STC_OPTION 1919 UINT64_C(203423744), // STC_POST 1920 UINT64_C(220200960), // STC_PRE 1921 UINT64_C(25230480), // STL 1922 UINT64_C(29424784), // STLB 1923 UINT64_C(25169552), // STLEX 1924 UINT64_C(29363856), // STLEXB 1925 UINT64_C(27266704), // STLEXD 1926 UINT64_C(31461008), // STLEXH 1927 UINT64_C(31521936), // STLH 1928 UINT64_C(134217728), // STMDA 1929 UINT64_C(136314880), // STMDA_UPD 1930 UINT64_C(150994944), // STMDB 1931 UINT64_C(153092096), // STMDB_UPD 1932 UINT64_C(142606336), // STMIA 1933 UINT64_C(144703488), // STMIA_UPD 1934 UINT64_C(159383552), // STMIB 1935 UINT64_C(161480704), // STMIB_UPD 1936 UINT64_C(73400320), // STRBT_POST_IMM 1937 UINT64_C(106954752), // STRBT_POST_REG 1938 UINT64_C(71303168), // STRB_POST_IMM 1939 UINT64_C(104857600), // STRB_POST_REG 1940 UINT64_C(90177536), // STRB_PRE_IMM 1941 UINT64_C(123731968), // STRB_PRE_REG 1942 UINT64_C(88080384), // STRBi12 1943 UINT64_C(121634816), // STRBrs 1944 UINT64_C(16777456), // STRD 1945 UINT64_C(240), // STRD_POST 1946 UINT64_C(18874608), // STRD_PRE 1947 UINT64_C(25169808), // STREX 1948 UINT64_C(29364112), // STREXB 1949 UINT64_C(27266960), // STREXD 1950 UINT64_C(31461264), // STREXH 1951 UINT64_C(16777392), // STRH 1952 UINT64_C(6291632), // STRHTi 1953 UINT64_C(2097328), // STRHTr 1954 UINT64_C(176), // STRH_POST 1955 UINT64_C(18874544), // STRH_PRE 1956 UINT64_C(69206016), // STRT_POST_IMM 1957 UINT64_C(102760448), // STRT_POST_REG 1958 UINT64_C(67108864), // STR_POST_IMM 1959 UINT64_C(100663296), // STR_POST_REG 1960 UINT64_C(85983232), // STR_PRE_IMM 1961 UINT64_C(119537664), // STR_PRE_REG 1962 UINT64_C(83886080), // STRi12 1963 UINT64_C(117440512), // STRrs 1964 UINT64_C(37748736), // SUBri 1965 UINT64_C(4194304), // SUBrr 1966 UINT64_C(4194304), // SUBrsi 1967 UINT64_C(4194320), // SUBrsr 1968 UINT64_C(251658240), // SVC 1969 UINT64_C(16777360), // SWP 1970 UINT64_C(20971664), // SWPB 1971 UINT64_C(111149168), // SXTAB 1972 UINT64_C(109052016), // SXTAB16 1973 UINT64_C(112197744), // SXTAH 1974 UINT64_C(112132208), // SXTB 1975 UINT64_C(110035056), // SXTB16 1976 UINT64_C(113180784), // SXTH 1977 UINT64_C(53477376), // TEQri 1978 UINT64_C(19922944), // TEQrr 1979 UINT64_C(19922944), // TEQrsi 1980 UINT64_C(19922960), // TEQrsr 1981 UINT64_C(3892305662), // TRAP 1982 UINT64_C(3892240112), // TRAPNaCl 1983 UINT64_C(3810586642), // TSB 1984 UINT64_C(51380224), // TSTri 1985 UINT64_C(17825792), // TSTrr 1986 UINT64_C(17825792), // TSTrsi 1987 UINT64_C(17825808), // TSTrsr 1988 UINT64_C(105910032), // UADD16 1989 UINT64_C(105910160), // UADD8 1990 UINT64_C(105910064), // UASX 1991 UINT64_C(132120656), // UBFX 1992 UINT64_C(3891265776), // UDF 1993 UINT64_C(120647696), // UDIV 1994 UINT64_C(108007184), // UHADD16 1995 UINT64_C(108007312), // UHADD8 1996 UINT64_C(108007216), // UHASX 1997 UINT64_C(108007248), // UHSAX 1998 UINT64_C(108007280), // UHSUB16 1999 UINT64_C(108007408), // UHSUB8 2000 UINT64_C(4194448), // UMAAL 2001 UINT64_C(10485904), // UMLAL 2002 UINT64_C(8388752), // UMULL 2003 UINT64_C(106958608), // UQADD16 2004 UINT64_C(106958736), // UQADD8 2005 UINT64_C(106958640), // UQASX 2006 UINT64_C(106958672), // UQSAX 2007 UINT64_C(106958704), // UQSUB16 2008 UINT64_C(106958832), // UQSUB8 2009 UINT64_C(125890576), // USAD8 2010 UINT64_C(125829136), // USADA8 2011 UINT64_C(115343376), // USAT 2012 UINT64_C(115347248), // USAT16 2013 UINT64_C(105910096), // USAX 2014 UINT64_C(105910128), // USUB16 2015 UINT64_C(105910256), // USUB8 2016 UINT64_C(115343472), // UXTAB 2017 UINT64_C(113246320), // UXTAB16 2018 UINT64_C(116392048), // UXTAH 2019 UINT64_C(116326512), // UXTB 2020 UINT64_C(114229360), // UXTB16 2021 UINT64_C(117375088), // UXTH 2022 UINT64_C(4070573312), // VABALsv2i64 2023 UINT64_C(4069524736), // VABALsv4i32 2024 UINT64_C(4068476160), // VABALsv8i16 2025 UINT64_C(4087350528), // VABALuv2i64 2026 UINT64_C(4086301952), // VABALuv4i32 2027 UINT64_C(4085253376), // VABALuv8i16 2028 UINT64_C(4060088144), // VABAsv16i8 2029 UINT64_C(4062185232), // VABAsv2i32 2030 UINT64_C(4061136656), // VABAsv4i16 2031 UINT64_C(4062185296), // VABAsv4i32 2032 UINT64_C(4061136720), // VABAsv8i16 2033 UINT64_C(4060088080), // VABAsv8i8 2034 UINT64_C(4076865360), // VABAuv16i8 2035 UINT64_C(4078962448), // VABAuv2i32 2036 UINT64_C(4077913872), // VABAuv4i16 2037 UINT64_C(4078962512), // VABAuv4i32 2038 UINT64_C(4077913936), // VABAuv8i16 2039 UINT64_C(4076865296), // VABAuv8i8 2040 UINT64_C(4070573824), // VABDLsv2i64 2041 UINT64_C(4069525248), // VABDLsv4i32 2042 UINT64_C(4068476672), // VABDLsv8i16 2043 UINT64_C(4087351040), // VABDLuv2i64 2044 UINT64_C(4086302464), // VABDLuv4i32 2045 UINT64_C(4085253888), // VABDLuv8i16 2046 UINT64_C(4078963968), // VABDfd 2047 UINT64_C(4078964032), // VABDfq 2048 UINT64_C(4080012544), // VABDhd 2049 UINT64_C(4080012608), // VABDhq 2050 UINT64_C(4060088128), // VABDsv16i8 2051 UINT64_C(4062185216), // VABDsv2i32 2052 UINT64_C(4061136640), // VABDsv4i16 2053 UINT64_C(4062185280), // VABDsv4i32 2054 UINT64_C(4061136704), // VABDsv8i16 2055 UINT64_C(4060088064), // VABDsv8i8 2056 UINT64_C(4076865344), // VABDuv16i8 2057 UINT64_C(4078962432), // VABDuv2i32 2058 UINT64_C(4077913856), // VABDuv4i16 2059 UINT64_C(4078962496), // VABDuv4i32 2060 UINT64_C(4077913920), // VABDuv8i16 2061 UINT64_C(4076865280), // VABDuv8i8 2062 UINT64_C(246418368), // VABSD 2063 UINT64_C(246417856), // VABSH 2064 UINT64_C(246418112), // VABSS 2065 UINT64_C(4088989440), // VABSfd 2066 UINT64_C(4088989504), // VABSfq 2067 UINT64_C(4088727296), // VABShd 2068 UINT64_C(4088727360), // VABShq 2069 UINT64_C(4088464192), // VABSv16i8 2070 UINT64_C(4088988416), // VABSv2i32 2071 UINT64_C(4088726272), // VABSv4i16 2072 UINT64_C(4088988480), // VABSv4i32 2073 UINT64_C(4088726336), // VABSv8i16 2074 UINT64_C(4088464128), // VABSv8i8 2075 UINT64_C(4076867088), // VACGEfd 2076 UINT64_C(4076867152), // VACGEfq 2077 UINT64_C(4077915664), // VACGEhd 2078 UINT64_C(4077915728), // VACGEhq 2079 UINT64_C(4078964240), // VACGTfd 2080 UINT64_C(4078964304), // VACGTfq 2081 UINT64_C(4080012816), // VACGThd 2082 UINT64_C(4080012880), // VACGThq 2083 UINT64_C(238029568), // VADDD 2084 UINT64_C(238029056), // VADDH 2085 UINT64_C(4070573056), // VADDHNv2i32 2086 UINT64_C(4069524480), // VADDHNv4i16 2087 UINT64_C(4068475904), // VADDHNv8i8 2088 UINT64_C(4070572032), // VADDLsv2i64 2089 UINT64_C(4069523456), // VADDLsv4i32 2090 UINT64_C(4068474880), // VADDLsv8i16 2091 UINT64_C(4087349248), // VADDLuv2i64 2092 UINT64_C(4086300672), // VADDLuv4i32 2093 UINT64_C(4085252096), // VADDLuv8i16 2094 UINT64_C(238029312), // VADDS 2095 UINT64_C(4070572288), // VADDWsv2i64 2096 UINT64_C(4069523712), // VADDWsv4i32 2097 UINT64_C(4068475136), // VADDWsv8i16 2098 UINT64_C(4087349504), // VADDWuv2i64 2099 UINT64_C(4086300928), // VADDWuv4i32 2100 UINT64_C(4085252352), // VADDWuv8i16 2101 UINT64_C(4060089600), // VADDfd 2102 UINT64_C(4060089664), // VADDfq 2103 UINT64_C(4061138176), // VADDhd 2104 UINT64_C(4061138240), // VADDhq 2105 UINT64_C(4060088384), // VADDv16i8 2106 UINT64_C(4063234048), // VADDv1i64 2107 UINT64_C(4062185472), // VADDv2i32 2108 UINT64_C(4063234112), // VADDv2i64 2109 UINT64_C(4061136896), // VADDv4i16 2110 UINT64_C(4062185536), // VADDv4i32 2111 UINT64_C(4061136960), // VADDv8i16 2112 UINT64_C(4060088320), // VADDv8i8 2113 UINT64_C(4060086544), // VANDd 2114 UINT64_C(4060086608), // VANDq 2115 UINT64_C(4231006224), // VBF16MALBQ 2116 UINT64_C(4264560656), // VBF16MALBQI 2117 UINT64_C(4231006288), // VBF16MALTQ 2118 UINT64_C(4264560720), // VBF16MALTQI 2119 UINT64_C(4061135120), // VBICd 2120 UINT64_C(4068475184), // VBICiv2i32 2121 UINT64_C(4068477232), // VBICiv4i16 2122 UINT64_C(4068475248), // VBICiv4i32 2123 UINT64_C(4068477296), // VBICiv8i16 2124 UINT64_C(4061135184), // VBICq 2125 UINT64_C(4080009488), // VBIFd 2126 UINT64_C(4080009552), // VBIFq 2127 UINT64_C(4078960912), // VBITd 2128 UINT64_C(4078960976), // VBITq 2129 UINT64_C(4077912336), // VBSLd 2130 UINT64_C(4077912400), // VBSLq 2131 UINT64_C(0), // VBSPd 2132 UINT64_C(0), // VBSPq 2133 UINT64_C(4237297664), // VCADDv2f32 2134 UINT64_C(4236249088), // VCADDv4f16 2135 UINT64_C(4237297728), // VCADDv4f32 2136 UINT64_C(4236249152), // VCADDv8f16 2137 UINT64_C(4060089856), // VCEQfd 2138 UINT64_C(4060089920), // VCEQfq 2139 UINT64_C(4061138432), // VCEQhd 2140 UINT64_C(4061138496), // VCEQhq 2141 UINT64_C(4076865616), // VCEQv16i8 2142 UINT64_C(4078962704), // VCEQv2i32 2143 UINT64_C(4077914128), // VCEQv4i16 2144 UINT64_C(4078962768), // VCEQv4i32 2145 UINT64_C(4077914192), // VCEQv8i16 2146 UINT64_C(4076865552), // VCEQv8i8 2147 UINT64_C(4088463680), // VCEQzv16i8 2148 UINT64_C(4088988928), // VCEQzv2f32 2149 UINT64_C(4088987904), // VCEQzv2i32 2150 UINT64_C(4088726784), // VCEQzv4f16 2151 UINT64_C(4088988992), // VCEQzv4f32 2152 UINT64_C(4088725760), // VCEQzv4i16 2153 UINT64_C(4088987968), // VCEQzv4i32 2154 UINT64_C(4088726848), // VCEQzv8f16 2155 UINT64_C(4088725824), // VCEQzv8i16 2156 UINT64_C(4088463616), // VCEQzv8i8 2157 UINT64_C(4076867072), // VCGEfd 2158 UINT64_C(4076867136), // VCGEfq 2159 UINT64_C(4077915648), // VCGEhd 2160 UINT64_C(4077915712), // VCGEhq 2161 UINT64_C(4060087120), // VCGEsv16i8 2162 UINT64_C(4062184208), // VCGEsv2i32 2163 UINT64_C(4061135632), // VCGEsv4i16 2164 UINT64_C(4062184272), // VCGEsv4i32 2165 UINT64_C(4061135696), // VCGEsv8i16 2166 UINT64_C(4060087056), // VCGEsv8i8 2167 UINT64_C(4076864336), // VCGEuv16i8 2168 UINT64_C(4078961424), // VCGEuv2i32 2169 UINT64_C(4077912848), // VCGEuv4i16 2170 UINT64_C(4078961488), // VCGEuv4i32 2171 UINT64_C(4077912912), // VCGEuv8i16 2172 UINT64_C(4076864272), // VCGEuv8i8 2173 UINT64_C(4088463552), // VCGEzv16i8 2174 UINT64_C(4088988800), // VCGEzv2f32 2175 UINT64_C(4088987776), // VCGEzv2i32 2176 UINT64_C(4088726656), // VCGEzv4f16 2177 UINT64_C(4088988864), // VCGEzv4f32 2178 UINT64_C(4088725632), // VCGEzv4i16 2179 UINT64_C(4088987840), // VCGEzv4i32 2180 UINT64_C(4088726720), // VCGEzv8f16 2181 UINT64_C(4088725696), // VCGEzv8i16 2182 UINT64_C(4088463488), // VCGEzv8i8 2183 UINT64_C(4078964224), // VCGTfd 2184 UINT64_C(4078964288), // VCGTfq 2185 UINT64_C(4080012800), // VCGThd 2186 UINT64_C(4080012864), // VCGThq 2187 UINT64_C(4060087104), // VCGTsv16i8 2188 UINT64_C(4062184192), // VCGTsv2i32 2189 UINT64_C(4061135616), // VCGTsv4i16 2190 UINT64_C(4062184256), // VCGTsv4i32 2191 UINT64_C(4061135680), // VCGTsv8i16 2192 UINT64_C(4060087040), // VCGTsv8i8 2193 UINT64_C(4076864320), // VCGTuv16i8 2194 UINT64_C(4078961408), // VCGTuv2i32 2195 UINT64_C(4077912832), // VCGTuv4i16 2196 UINT64_C(4078961472), // VCGTuv4i32 2197 UINT64_C(4077912896), // VCGTuv8i16 2198 UINT64_C(4076864256), // VCGTuv8i8 2199 UINT64_C(4088463424), // VCGTzv16i8 2200 UINT64_C(4088988672), // VCGTzv2f32 2201 UINT64_C(4088987648), // VCGTzv2i32 2202 UINT64_C(4088726528), // VCGTzv4f16 2203 UINT64_C(4088988736), // VCGTzv4f32 2204 UINT64_C(4088725504), // VCGTzv4i16 2205 UINT64_C(4088987712), // VCGTzv4i32 2206 UINT64_C(4088726592), // VCGTzv8f16 2207 UINT64_C(4088725568), // VCGTzv8i16 2208 UINT64_C(4088463360), // VCGTzv8i8 2209 UINT64_C(4088463808), // VCLEzv16i8 2210 UINT64_C(4088989056), // VCLEzv2f32 2211 UINT64_C(4088988032), // VCLEzv2i32 2212 UINT64_C(4088726912), // VCLEzv4f16 2213 UINT64_C(4088989120), // VCLEzv4f32 2214 UINT64_C(4088725888), // VCLEzv4i16 2215 UINT64_C(4088988096), // VCLEzv4i32 2216 UINT64_C(4088726976), // VCLEzv8f16 2217 UINT64_C(4088725952), // VCLEzv8i16 2218 UINT64_C(4088463744), // VCLEzv8i8 2219 UINT64_C(4088398912), // VCLSv16i8 2220 UINT64_C(4088923136), // VCLSv2i32 2221 UINT64_C(4088660992), // VCLSv4i16 2222 UINT64_C(4088923200), // VCLSv4i32 2223 UINT64_C(4088661056), // VCLSv8i16 2224 UINT64_C(4088398848), // VCLSv8i8 2225 UINT64_C(4088463936), // VCLTzv16i8 2226 UINT64_C(4088989184), // VCLTzv2f32 2227 UINT64_C(4088988160), // VCLTzv2i32 2228 UINT64_C(4088727040), // VCLTzv4f16 2229 UINT64_C(4088989248), // VCLTzv4f32 2230 UINT64_C(4088726016), // VCLTzv4i16 2231 UINT64_C(4088988224), // VCLTzv4i32 2232 UINT64_C(4088727104), // VCLTzv8f16 2233 UINT64_C(4088726080), // VCLTzv8i16 2234 UINT64_C(4088463872), // VCLTzv8i8 2235 UINT64_C(4088399040), // VCLZv16i8 2236 UINT64_C(4088923264), // VCLZv2i32 2237 UINT64_C(4088661120), // VCLZv4i16 2238 UINT64_C(4088923328), // VCLZv4i32 2239 UINT64_C(4088661184), // VCLZv8i16 2240 UINT64_C(4088398976), // VCLZv8i8 2241 UINT64_C(4231006208), // VCMLAv2f32 2242 UINT64_C(4269803520), // VCMLAv2f32_indexed 2243 UINT64_C(4229957632), // VCMLAv4f16 2244 UINT64_C(4261414912), // VCMLAv4f16_indexed 2245 UINT64_C(4231006272), // VCMLAv4f32 2246 UINT64_C(4269803584), // VCMLAv4f32_indexed 2247 UINT64_C(4229957696), // VCMLAv8f16 2248 UINT64_C(4261414976), // VCMLAv8f16_indexed 2249 UINT64_C(246680384), // VCMPD 2250 UINT64_C(246680512), // VCMPED 2251 UINT64_C(246680000), // VCMPEH 2252 UINT64_C(246680256), // VCMPES 2253 UINT64_C(246746048), // VCMPEZD 2254 UINT64_C(246745536), // VCMPEZH 2255 UINT64_C(246745792), // VCMPEZS 2256 UINT64_C(246679872), // VCMPH 2257 UINT64_C(246680128), // VCMPS 2258 UINT64_C(246745920), // VCMPZD 2259 UINT64_C(246745408), // VCMPZH 2260 UINT64_C(246745664), // VCMPZS 2261 UINT64_C(4088399104), // VCNTd 2262 UINT64_C(4088399168), // VCNTq 2263 UINT64_C(4089118720), // VCVTANSDf 2264 UINT64_C(4088856576), // VCVTANSDh 2265 UINT64_C(4089118784), // VCVTANSQf 2266 UINT64_C(4088856640), // VCVTANSQh 2267 UINT64_C(4089118848), // VCVTANUDf 2268 UINT64_C(4088856704), // VCVTANUDh 2269 UINT64_C(4089118912), // VCVTANUQf 2270 UINT64_C(4088856768), // VCVTANUQh 2271 UINT64_C(4273736640), // VCVTASD 2272 UINT64_C(4273736128), // VCVTASH 2273 UINT64_C(4273736384), // VCVTASS 2274 UINT64_C(4273736512), // VCVTAUD 2275 UINT64_C(4273736000), // VCVTAUH 2276 UINT64_C(4273736256), // VCVTAUS 2277 UINT64_C(246614848), // VCVTBDH 2278 UINT64_C(246549312), // VCVTBHD 2279 UINT64_C(246549056), // VCVTBHS 2280 UINT64_C(246614592), // VCVTBSH 2281 UINT64_C(246876864), // VCVTDS 2282 UINT64_C(4089119488), // VCVTMNSDf 2283 UINT64_C(4088857344), // VCVTMNSDh 2284 UINT64_C(4089119552), // VCVTMNSQf 2285 UINT64_C(4088857408), // VCVTMNSQh 2286 UINT64_C(4089119616), // VCVTMNUDf 2287 UINT64_C(4088857472), // VCVTMNUDh 2288 UINT64_C(4089119680), // VCVTMNUQf 2289 UINT64_C(4088857536), // VCVTMNUQh 2290 UINT64_C(4273933248), // VCVTMSD 2291 UINT64_C(4273932736), // VCVTMSH 2292 UINT64_C(4273932992), // VCVTMSS 2293 UINT64_C(4273933120), // VCVTMUD 2294 UINT64_C(4273932608), // VCVTMUH 2295 UINT64_C(4273932864), // VCVTMUS 2296 UINT64_C(4089118976), // VCVTNNSDf 2297 UINT64_C(4088856832), // VCVTNNSDh 2298 UINT64_C(4089119040), // VCVTNNSQf 2299 UINT64_C(4088856896), // VCVTNNSQh 2300 UINT64_C(4089119104), // VCVTNNUDf 2301 UINT64_C(4088856960), // VCVTNNUDh 2302 UINT64_C(4089119168), // VCVTNNUQf 2303 UINT64_C(4088857024), // VCVTNNUQh 2304 UINT64_C(4273802176), // VCVTNSD 2305 UINT64_C(4273801664), // VCVTNSH 2306 UINT64_C(4273801920), // VCVTNSS 2307 UINT64_C(4273802048), // VCVTNUD 2308 UINT64_C(4273801536), // VCVTNUH 2309 UINT64_C(4273801792), // VCVTNUS 2310 UINT64_C(4089119232), // VCVTPNSDf 2311 UINT64_C(4088857088), // VCVTPNSDh 2312 UINT64_C(4089119296), // VCVTPNSQf 2313 UINT64_C(4088857152), // VCVTPNSQh 2314 UINT64_C(4089119360), // VCVTPNUDf 2315 UINT64_C(4088857216), // VCVTPNUDh 2316 UINT64_C(4089119424), // VCVTPNUQf 2317 UINT64_C(4088857280), // VCVTPNUQh 2318 UINT64_C(4273867712), // VCVTPSD 2319 UINT64_C(4273867200), // VCVTPSH 2320 UINT64_C(4273867456), // VCVTPSS 2321 UINT64_C(4273867584), // VCVTPUD 2322 UINT64_C(4273867072), // VCVTPUH 2323 UINT64_C(4273867328), // VCVTPUS 2324 UINT64_C(246877120), // VCVTSD 2325 UINT64_C(246614976), // VCVTTDH 2326 UINT64_C(246549440), // VCVTTHD 2327 UINT64_C(246549184), // VCVTTHS 2328 UINT64_C(246614720), // VCVTTSH 2329 UINT64_C(4088792576), // VCVTf2h 2330 UINT64_C(4089120512), // VCVTf2sd 2331 UINT64_C(4089120576), // VCVTf2sq 2332 UINT64_C(4089120640), // VCVTf2ud 2333 UINT64_C(4089120704), // VCVTf2uq 2334 UINT64_C(4068478736), // VCVTf2xsd 2335 UINT64_C(4068478800), // VCVTf2xsq 2336 UINT64_C(4085255952), // VCVTf2xud 2337 UINT64_C(4085256016), // VCVTf2xuq 2338 UINT64_C(4088792832), // VCVTh2f 2339 UINT64_C(4088858368), // VCVTh2sd 2340 UINT64_C(4088858432), // VCVTh2sq 2341 UINT64_C(4088858496), // VCVTh2ud 2342 UINT64_C(4088858560), // VCVTh2uq 2343 UINT64_C(4068478224), // VCVTh2xsd 2344 UINT64_C(4068478288), // VCVTh2xsq 2345 UINT64_C(4085255440), // VCVTh2xud 2346 UINT64_C(4085255504), // VCVTh2xuq 2347 UINT64_C(4089120256), // VCVTs2fd 2348 UINT64_C(4089120320), // VCVTs2fq 2349 UINT64_C(4088858112), // VCVTs2hd 2350 UINT64_C(4088858176), // VCVTs2hq 2351 UINT64_C(4089120384), // VCVTu2fd 2352 UINT64_C(4089120448), // VCVTu2fq 2353 UINT64_C(4088858240), // VCVTu2hd 2354 UINT64_C(4088858304), // VCVTu2hq 2355 UINT64_C(4068478480), // VCVTxs2fd 2356 UINT64_C(4068478544), // VCVTxs2fq 2357 UINT64_C(4068477968), // VCVTxs2hd 2358 UINT64_C(4068478032), // VCVTxs2hq 2359 UINT64_C(4085255696), // VCVTxu2fd 2360 UINT64_C(4085255760), // VCVTxu2fq 2361 UINT64_C(4085255184), // VCVTxu2hd 2362 UINT64_C(4085255248), // VCVTxu2hq 2363 UINT64_C(243272448), // VDIVD 2364 UINT64_C(243271936), // VDIVH 2365 UINT64_C(243272192), // VDIVS 2366 UINT64_C(243272496), // VDUP16d 2367 UINT64_C(245369648), // VDUP16q 2368 UINT64_C(243272464), // VDUP32d 2369 UINT64_C(245369616), // VDUP32q 2370 UINT64_C(247466768), // VDUP8d 2371 UINT64_C(249563920), // VDUP8q 2372 UINT64_C(4088531968), // VDUPLN16d 2373 UINT64_C(4088532032), // VDUPLN16q 2374 UINT64_C(4088663040), // VDUPLN32d 2375 UINT64_C(4088663104), // VDUPLN32q 2376 UINT64_C(4088466432), // VDUPLN8d 2377 UINT64_C(4088466496), // VDUPLN8q 2378 UINT64_C(4076863760), // VEORd 2379 UINT64_C(4076863824), // VEORq 2380 UINT64_C(4071620608), // VEXTd16 2381 UINT64_C(4071620608), // VEXTd32 2382 UINT64_C(4071620608), // VEXTd8 2383 UINT64_C(4071620672), // VEXTq16 2384 UINT64_C(4071620672), // VEXTq32 2385 UINT64_C(4071620672), // VEXTq64 2386 UINT64_C(4071620672), // VEXTq8 2387 UINT64_C(245369600), // VFMAD 2388 UINT64_C(245369088), // VFMAH 2389 UINT64_C(4229957648), // VFMALD 2390 UINT64_C(4261414928), // VFMALDI 2391 UINT64_C(4229957712), // VFMALQ 2392 UINT64_C(4261414992), // VFMALQI 2393 UINT64_C(245369344), // VFMAS 2394 UINT64_C(4060089360), // VFMAfd 2395 UINT64_C(4060089424), // VFMAfq 2396 UINT64_C(4061137936), // VFMAhd 2397 UINT64_C(4061138000), // VFMAhq 2398 UINT64_C(245369664), // VFMSD 2399 UINT64_C(245369152), // VFMSH 2400 UINT64_C(4238346256), // VFMSLD 2401 UINT64_C(4262463504), // VFMSLDI 2402 UINT64_C(4238346320), // VFMSLQ 2403 UINT64_C(4262463568), // VFMSLQI 2404 UINT64_C(245369408), // VFMSS 2405 UINT64_C(4062186512), // VFMSfd 2406 UINT64_C(4062186576), // VFMSfq 2407 UINT64_C(4063235088), // VFMShd 2408 UINT64_C(4063235152), // VFMShq 2409 UINT64_C(244321088), // VFNMAD 2410 UINT64_C(244320576), // VFNMAH 2411 UINT64_C(244320832), // VFNMAS 2412 UINT64_C(244321024), // VFNMSD 2413 UINT64_C(244320512), // VFNMSH 2414 UINT64_C(244320768), // VFNMSS 2415 UINT64_C(4269804288), // VFP_VMAXNMD 2416 UINT64_C(4269803776), // VFP_VMAXNMH 2417 UINT64_C(4269804032), // VFP_VMAXNMS 2418 UINT64_C(4269804352), // VFP_VMINNMD 2419 UINT64_C(4269803840), // VFP_VMINNMH 2420 UINT64_C(4269804096), // VFP_VMINNMS 2421 UINT64_C(235932432), // VGETLNi32 2422 UINT64_C(235932464), // VGETLNs16 2423 UINT64_C(240126736), // VGETLNs8 2424 UINT64_C(244321072), // VGETLNu16 2425 UINT64_C(248515344), // VGETLNu8 2426 UINT64_C(4060086336), // VHADDsv16i8 2427 UINT64_C(4062183424), // VHADDsv2i32 2428 UINT64_C(4061134848), // VHADDsv4i16 2429 UINT64_C(4062183488), // VHADDsv4i32 2430 UINT64_C(4061134912), // VHADDsv8i16 2431 UINT64_C(4060086272), // VHADDsv8i8 2432 UINT64_C(4076863552), // VHADDuv16i8 2433 UINT64_C(4078960640), // VHADDuv2i32 2434 UINT64_C(4077912064), // VHADDuv4i16 2435 UINT64_C(4078960704), // VHADDuv4i32 2436 UINT64_C(4077912128), // VHADDuv8i16 2437 UINT64_C(4076863488), // VHADDuv8i8 2438 UINT64_C(4060086848), // VHSUBsv16i8 2439 UINT64_C(4062183936), // VHSUBsv2i32 2440 UINT64_C(4061135360), // VHSUBsv4i16 2441 UINT64_C(4062184000), // VHSUBsv4i32 2442 UINT64_C(4061135424), // VHSUBsv8i16 2443 UINT64_C(4060086784), // VHSUBsv8i8 2444 UINT64_C(4076864064), // VHSUBuv16i8 2445 UINT64_C(4078961152), // VHSUBuv2i32 2446 UINT64_C(4077912576), // VHSUBuv4i16 2447 UINT64_C(4078961216), // VHSUBuv4i32 2448 UINT64_C(4077912640), // VHSUBuv8i16 2449 UINT64_C(4076864000), // VHSUBuv8i8 2450 UINT64_C(4272949952), // VINSH 2451 UINT64_C(247008192), // VJCVT 2452 UINT64_C(4104129615), // VLD1DUPd16 2453 UINT64_C(4104129613), // VLD1DUPd16wb_fixed 2454 UINT64_C(4104129600), // VLD1DUPd16wb_register 2455 UINT64_C(4104129679), // VLD1DUPd32 2456 UINT64_C(4104129677), // VLD1DUPd32wb_fixed 2457 UINT64_C(4104129664), // VLD1DUPd32wb_register 2458 UINT64_C(4104129551), // VLD1DUPd8 2459 UINT64_C(4104129549), // VLD1DUPd8wb_fixed 2460 UINT64_C(4104129536), // VLD1DUPd8wb_register 2461 UINT64_C(4104129647), // VLD1DUPq16 2462 UINT64_C(4104129645), // VLD1DUPq16wb_fixed 2463 UINT64_C(4104129632), // VLD1DUPq16wb_register 2464 UINT64_C(4104129711), // VLD1DUPq32 2465 UINT64_C(4104129709), // VLD1DUPq32wb_fixed 2466 UINT64_C(4104129696), // VLD1DUPq32wb_register 2467 UINT64_C(4104129583), // VLD1DUPq8 2468 UINT64_C(4104129581), // VLD1DUPq8wb_fixed 2469 UINT64_C(4104129568), // VLD1DUPq8wb_register 2470 UINT64_C(4104127503), // VLD1LNd16 2471 UINT64_C(4104127488), // VLD1LNd16_UPD 2472 UINT64_C(4104128527), // VLD1LNd32 2473 UINT64_C(4104128512), // VLD1LNd32_UPD 2474 UINT64_C(4104126479), // VLD1LNd8 2475 UINT64_C(4104126464), // VLD1LNd8_UPD 2476 UINT64_C(0), // VLD1LNq16Pseudo 2477 UINT64_C(0), // VLD1LNq16Pseudo_UPD 2478 UINT64_C(0), // VLD1LNq32Pseudo 2479 UINT64_C(0), // VLD1LNq32Pseudo_UPD 2480 UINT64_C(0), // VLD1LNq8Pseudo 2481 UINT64_C(0), // VLD1LNq8Pseudo_UPD 2482 UINT64_C(4095739727), // VLD1d16 2483 UINT64_C(4095738447), // VLD1d16Q 2484 UINT64_C(0), // VLD1d16QPseudo 2485 UINT64_C(0), // VLD1d16QPseudoWB_fixed 2486 UINT64_C(0), // VLD1d16QPseudoWB_register 2487 UINT64_C(4095738445), // VLD1d16Qwb_fixed 2488 UINT64_C(4095738432), // VLD1d16Qwb_register 2489 UINT64_C(4095739471), // VLD1d16T 2490 UINT64_C(0), // VLD1d16TPseudo 2491 UINT64_C(0), // VLD1d16TPseudoWB_fixed 2492 UINT64_C(0), // VLD1d16TPseudoWB_register 2493 UINT64_C(4095739469), // VLD1d16Twb_fixed 2494 UINT64_C(4095739456), // VLD1d16Twb_register 2495 UINT64_C(4095739725), // VLD1d16wb_fixed 2496 UINT64_C(4095739712), // VLD1d16wb_register 2497 UINT64_C(4095739791), // VLD1d32 2498 UINT64_C(4095738511), // VLD1d32Q 2499 UINT64_C(0), // VLD1d32QPseudo 2500 UINT64_C(0), // VLD1d32QPseudoWB_fixed 2501 UINT64_C(0), // VLD1d32QPseudoWB_register 2502 UINT64_C(4095738509), // VLD1d32Qwb_fixed 2503 UINT64_C(4095738496), // VLD1d32Qwb_register 2504 UINT64_C(4095739535), // VLD1d32T 2505 UINT64_C(0), // VLD1d32TPseudo 2506 UINT64_C(0), // VLD1d32TPseudoWB_fixed 2507 UINT64_C(0), // VLD1d32TPseudoWB_register 2508 UINT64_C(4095739533), // VLD1d32Twb_fixed 2509 UINT64_C(4095739520), // VLD1d32Twb_register 2510 UINT64_C(4095739789), // VLD1d32wb_fixed 2511 UINT64_C(4095739776), // VLD1d32wb_register 2512 UINT64_C(4095739855), // VLD1d64 2513 UINT64_C(4095738575), // VLD1d64Q 2514 UINT64_C(0), // VLD1d64QPseudo 2515 UINT64_C(0), // VLD1d64QPseudoWB_fixed 2516 UINT64_C(0), // VLD1d64QPseudoWB_register 2517 UINT64_C(4095738573), // VLD1d64Qwb_fixed 2518 UINT64_C(4095738560), // VLD1d64Qwb_register 2519 UINT64_C(4095739599), // VLD1d64T 2520 UINT64_C(0), // VLD1d64TPseudo 2521 UINT64_C(0), // VLD1d64TPseudoWB_fixed 2522 UINT64_C(0), // VLD1d64TPseudoWB_register 2523 UINT64_C(4095739597), // VLD1d64Twb_fixed 2524 UINT64_C(4095739584), // VLD1d64Twb_register 2525 UINT64_C(4095739853), // VLD1d64wb_fixed 2526 UINT64_C(4095739840), // VLD1d64wb_register 2527 UINT64_C(4095739663), // VLD1d8 2528 UINT64_C(4095738383), // VLD1d8Q 2529 UINT64_C(0), // VLD1d8QPseudo 2530 UINT64_C(0), // VLD1d8QPseudoWB_fixed 2531 UINT64_C(0), // VLD1d8QPseudoWB_register 2532 UINT64_C(4095738381), // VLD1d8Qwb_fixed 2533 UINT64_C(4095738368), // VLD1d8Qwb_register 2534 UINT64_C(4095739407), // VLD1d8T 2535 UINT64_C(0), // VLD1d8TPseudo 2536 UINT64_C(0), // VLD1d8TPseudoWB_fixed 2537 UINT64_C(0), // VLD1d8TPseudoWB_register 2538 UINT64_C(4095739405), // VLD1d8Twb_fixed 2539 UINT64_C(4095739392), // VLD1d8Twb_register 2540 UINT64_C(4095739661), // VLD1d8wb_fixed 2541 UINT64_C(4095739648), // VLD1d8wb_register 2542 UINT64_C(4095740495), // VLD1q16 2543 UINT64_C(0), // VLD1q16HighQPseudo 2544 UINT64_C(0), // VLD1q16HighQPseudo_UPD 2545 UINT64_C(0), // VLD1q16HighTPseudo 2546 UINT64_C(0), // VLD1q16HighTPseudo_UPD 2547 UINT64_C(0), // VLD1q16LowQPseudo_UPD 2548 UINT64_C(0), // VLD1q16LowTPseudo_UPD 2549 UINT64_C(4095740493), // VLD1q16wb_fixed 2550 UINT64_C(4095740480), // VLD1q16wb_register 2551 UINT64_C(4095740559), // VLD1q32 2552 UINT64_C(0), // VLD1q32HighQPseudo 2553 UINT64_C(0), // VLD1q32HighQPseudo_UPD 2554 UINT64_C(0), // VLD1q32HighTPseudo 2555 UINT64_C(0), // VLD1q32HighTPseudo_UPD 2556 UINT64_C(0), // VLD1q32LowQPseudo_UPD 2557 UINT64_C(0), // VLD1q32LowTPseudo_UPD 2558 UINT64_C(4095740557), // VLD1q32wb_fixed 2559 UINT64_C(4095740544), // VLD1q32wb_register 2560 UINT64_C(4095740623), // VLD1q64 2561 UINT64_C(0), // VLD1q64HighQPseudo 2562 UINT64_C(0), // VLD1q64HighQPseudo_UPD 2563 UINT64_C(0), // VLD1q64HighTPseudo 2564 UINT64_C(0), // VLD1q64HighTPseudo_UPD 2565 UINT64_C(0), // VLD1q64LowQPseudo_UPD 2566 UINT64_C(0), // VLD1q64LowTPseudo_UPD 2567 UINT64_C(4095740621), // VLD1q64wb_fixed 2568 UINT64_C(4095740608), // VLD1q64wb_register 2569 UINT64_C(4095740431), // VLD1q8 2570 UINT64_C(0), // VLD1q8HighQPseudo 2571 UINT64_C(0), // VLD1q8HighQPseudo_UPD 2572 UINT64_C(0), // VLD1q8HighTPseudo 2573 UINT64_C(0), // VLD1q8HighTPseudo_UPD 2574 UINT64_C(0), // VLD1q8LowQPseudo_UPD 2575 UINT64_C(0), // VLD1q8LowTPseudo_UPD 2576 UINT64_C(4095740429), // VLD1q8wb_fixed 2577 UINT64_C(4095740416), // VLD1q8wb_register 2578 UINT64_C(4104129871), // VLD2DUPd16 2579 UINT64_C(4104129869), // VLD2DUPd16wb_fixed 2580 UINT64_C(4104129856), // VLD2DUPd16wb_register 2581 UINT64_C(4104129903), // VLD2DUPd16x2 2582 UINT64_C(4104129901), // VLD2DUPd16x2wb_fixed 2583 UINT64_C(4104129888), // VLD2DUPd16x2wb_register 2584 UINT64_C(4104129935), // VLD2DUPd32 2585 UINT64_C(4104129933), // VLD2DUPd32wb_fixed 2586 UINT64_C(4104129920), // VLD2DUPd32wb_register 2587 UINT64_C(4104129967), // VLD2DUPd32x2 2588 UINT64_C(4104129965), // VLD2DUPd32x2wb_fixed 2589 UINT64_C(4104129952), // VLD2DUPd32x2wb_register 2590 UINT64_C(4104129807), // VLD2DUPd8 2591 UINT64_C(4104129805), // VLD2DUPd8wb_fixed 2592 UINT64_C(4104129792), // VLD2DUPd8wb_register 2593 UINT64_C(4104129839), // VLD2DUPd8x2 2594 UINT64_C(4104129837), // VLD2DUPd8x2wb_fixed 2595 UINT64_C(4104129824), // VLD2DUPd8x2wb_register 2596 UINT64_C(0), // VLD2DUPq16EvenPseudo 2597 UINT64_C(0), // VLD2DUPq16OddPseudo 2598 UINT64_C(0), // VLD2DUPq16OddPseudoWB_fixed 2599 UINT64_C(0), // VLD2DUPq16OddPseudoWB_register 2600 UINT64_C(0), // VLD2DUPq32EvenPseudo 2601 UINT64_C(0), // VLD2DUPq32OddPseudo 2602 UINT64_C(0), // VLD2DUPq32OddPseudoWB_fixed 2603 UINT64_C(0), // VLD2DUPq32OddPseudoWB_register 2604 UINT64_C(0), // VLD2DUPq8EvenPseudo 2605 UINT64_C(0), // VLD2DUPq8OddPseudo 2606 UINT64_C(0), // VLD2DUPq8OddPseudoWB_fixed 2607 UINT64_C(0), // VLD2DUPq8OddPseudoWB_register 2608 UINT64_C(4104127759), // VLD2LNd16 2609 UINT64_C(0), // VLD2LNd16Pseudo 2610 UINT64_C(0), // VLD2LNd16Pseudo_UPD 2611 UINT64_C(4104127744), // VLD2LNd16_UPD 2612 UINT64_C(4104128783), // VLD2LNd32 2613 UINT64_C(0), // VLD2LNd32Pseudo 2614 UINT64_C(0), // VLD2LNd32Pseudo_UPD 2615 UINT64_C(4104128768), // VLD2LNd32_UPD 2616 UINT64_C(4104126735), // VLD2LNd8 2617 UINT64_C(0), // VLD2LNd8Pseudo 2618 UINT64_C(0), // VLD2LNd8Pseudo_UPD 2619 UINT64_C(4104126720), // VLD2LNd8_UPD 2620 UINT64_C(4104127791), // VLD2LNq16 2621 UINT64_C(0), // VLD2LNq16Pseudo 2622 UINT64_C(0), // VLD2LNq16Pseudo_UPD 2623 UINT64_C(4104127776), // VLD2LNq16_UPD 2624 UINT64_C(4104128847), // VLD2LNq32 2625 UINT64_C(0), // VLD2LNq32Pseudo 2626 UINT64_C(0), // VLD2LNq32Pseudo_UPD 2627 UINT64_C(4104128832), // VLD2LNq32_UPD 2628 UINT64_C(4095740239), // VLD2b16 2629 UINT64_C(4095740237), // VLD2b16wb_fixed 2630 UINT64_C(4095740224), // VLD2b16wb_register 2631 UINT64_C(4095740303), // VLD2b32 2632 UINT64_C(4095740301), // VLD2b32wb_fixed 2633 UINT64_C(4095740288), // VLD2b32wb_register 2634 UINT64_C(4095740175), // VLD2b8 2635 UINT64_C(4095740173), // VLD2b8wb_fixed 2636 UINT64_C(4095740160), // VLD2b8wb_register 2637 UINT64_C(4095739983), // VLD2d16 2638 UINT64_C(4095739981), // VLD2d16wb_fixed 2639 UINT64_C(4095739968), // VLD2d16wb_register 2640 UINT64_C(4095740047), // VLD2d32 2641 UINT64_C(4095740045), // VLD2d32wb_fixed 2642 UINT64_C(4095740032), // VLD2d32wb_register 2643 UINT64_C(4095739919), // VLD2d8 2644 UINT64_C(4095739917), // VLD2d8wb_fixed 2645 UINT64_C(4095739904), // VLD2d8wb_register 2646 UINT64_C(4095738703), // VLD2q16 2647 UINT64_C(0), // VLD2q16Pseudo 2648 UINT64_C(0), // VLD2q16PseudoWB_fixed 2649 UINT64_C(0), // VLD2q16PseudoWB_register 2650 UINT64_C(4095738701), // VLD2q16wb_fixed 2651 UINT64_C(4095738688), // VLD2q16wb_register 2652 UINT64_C(4095738767), // VLD2q32 2653 UINT64_C(0), // VLD2q32Pseudo 2654 UINT64_C(0), // VLD2q32PseudoWB_fixed 2655 UINT64_C(0), // VLD2q32PseudoWB_register 2656 UINT64_C(4095738765), // VLD2q32wb_fixed 2657 UINT64_C(4095738752), // VLD2q32wb_register 2658 UINT64_C(4095738639), // VLD2q8 2659 UINT64_C(0), // VLD2q8Pseudo 2660 UINT64_C(0), // VLD2q8PseudoWB_fixed 2661 UINT64_C(0), // VLD2q8PseudoWB_register 2662 UINT64_C(4095738637), // VLD2q8wb_fixed 2663 UINT64_C(4095738624), // VLD2q8wb_register 2664 UINT64_C(4104130127), // VLD3DUPd16 2665 UINT64_C(0), // VLD3DUPd16Pseudo 2666 UINT64_C(0), // VLD3DUPd16Pseudo_UPD 2667 UINT64_C(4104130112), // VLD3DUPd16_UPD 2668 UINT64_C(4104130191), // VLD3DUPd32 2669 UINT64_C(0), // VLD3DUPd32Pseudo 2670 UINT64_C(0), // VLD3DUPd32Pseudo_UPD 2671 UINT64_C(4104130176), // VLD3DUPd32_UPD 2672 UINT64_C(4104130063), // VLD3DUPd8 2673 UINT64_C(0), // VLD3DUPd8Pseudo 2674 UINT64_C(0), // VLD3DUPd8Pseudo_UPD 2675 UINT64_C(4104130048), // VLD3DUPd8_UPD 2676 UINT64_C(4104130159), // VLD3DUPq16 2677 UINT64_C(0), // VLD3DUPq16EvenPseudo 2678 UINT64_C(0), // VLD3DUPq16OddPseudo 2679 UINT64_C(0), // VLD3DUPq16OddPseudo_UPD 2680 UINT64_C(4104130144), // VLD3DUPq16_UPD 2681 UINT64_C(4104130223), // VLD3DUPq32 2682 UINT64_C(0), // VLD3DUPq32EvenPseudo 2683 UINT64_C(0), // VLD3DUPq32OddPseudo 2684 UINT64_C(0), // VLD3DUPq32OddPseudo_UPD 2685 UINT64_C(4104130208), // VLD3DUPq32_UPD 2686 UINT64_C(4104130095), // VLD3DUPq8 2687 UINT64_C(0), // VLD3DUPq8EvenPseudo 2688 UINT64_C(0), // VLD3DUPq8OddPseudo 2689 UINT64_C(0), // VLD3DUPq8OddPseudo_UPD 2690 UINT64_C(4104130080), // VLD3DUPq8_UPD 2691 UINT64_C(4104128015), // VLD3LNd16 2692 UINT64_C(0), // VLD3LNd16Pseudo 2693 UINT64_C(0), // VLD3LNd16Pseudo_UPD 2694 UINT64_C(4104128000), // VLD3LNd16_UPD 2695 UINT64_C(4104129039), // VLD3LNd32 2696 UINT64_C(0), // VLD3LNd32Pseudo 2697 UINT64_C(0), // VLD3LNd32Pseudo_UPD 2698 UINT64_C(4104129024), // VLD3LNd32_UPD 2699 UINT64_C(4104126991), // VLD3LNd8 2700 UINT64_C(0), // VLD3LNd8Pseudo 2701 UINT64_C(0), // VLD3LNd8Pseudo_UPD 2702 UINT64_C(4104126976), // VLD3LNd8_UPD 2703 UINT64_C(4104128047), // VLD3LNq16 2704 UINT64_C(0), // VLD3LNq16Pseudo 2705 UINT64_C(0), // VLD3LNq16Pseudo_UPD 2706 UINT64_C(4104128032), // VLD3LNq16_UPD 2707 UINT64_C(4104129103), // VLD3LNq32 2708 UINT64_C(0), // VLD3LNq32Pseudo 2709 UINT64_C(0), // VLD3LNq32Pseudo_UPD 2710 UINT64_C(4104129088), // VLD3LNq32_UPD 2711 UINT64_C(4095738959), // VLD3d16 2712 UINT64_C(0), // VLD3d16Pseudo 2713 UINT64_C(0), // VLD3d16Pseudo_UPD 2714 UINT64_C(4095738944), // VLD3d16_UPD 2715 UINT64_C(4095739023), // VLD3d32 2716 UINT64_C(0), // VLD3d32Pseudo 2717 UINT64_C(0), // VLD3d32Pseudo_UPD 2718 UINT64_C(4095739008), // VLD3d32_UPD 2719 UINT64_C(4095738895), // VLD3d8 2720 UINT64_C(0), // VLD3d8Pseudo 2721 UINT64_C(0), // VLD3d8Pseudo_UPD 2722 UINT64_C(4095738880), // VLD3d8_UPD 2723 UINT64_C(4095739215), // VLD3q16 2724 UINT64_C(0), // VLD3q16Pseudo_UPD 2725 UINT64_C(4095739200), // VLD3q16_UPD 2726 UINT64_C(0), // VLD3q16oddPseudo 2727 UINT64_C(0), // VLD3q16oddPseudo_UPD 2728 UINT64_C(4095739279), // VLD3q32 2729 UINT64_C(0), // VLD3q32Pseudo_UPD 2730 UINT64_C(4095739264), // VLD3q32_UPD 2731 UINT64_C(0), // VLD3q32oddPseudo 2732 UINT64_C(0), // VLD3q32oddPseudo_UPD 2733 UINT64_C(4095739151), // VLD3q8 2734 UINT64_C(0), // VLD3q8Pseudo_UPD 2735 UINT64_C(4095739136), // VLD3q8_UPD 2736 UINT64_C(0), // VLD3q8oddPseudo 2737 UINT64_C(0), // VLD3q8oddPseudo_UPD 2738 UINT64_C(4104130383), // VLD4DUPd16 2739 UINT64_C(0), // VLD4DUPd16Pseudo 2740 UINT64_C(0), // VLD4DUPd16Pseudo_UPD 2741 UINT64_C(4104130368), // VLD4DUPd16_UPD 2742 UINT64_C(4104130447), // VLD4DUPd32 2743 UINT64_C(0), // VLD4DUPd32Pseudo 2744 UINT64_C(0), // VLD4DUPd32Pseudo_UPD 2745 UINT64_C(4104130432), // VLD4DUPd32_UPD 2746 UINT64_C(4104130319), // VLD4DUPd8 2747 UINT64_C(0), // VLD4DUPd8Pseudo 2748 UINT64_C(0), // VLD4DUPd8Pseudo_UPD 2749 UINT64_C(4104130304), // VLD4DUPd8_UPD 2750 UINT64_C(4104130415), // VLD4DUPq16 2751 UINT64_C(0), // VLD4DUPq16EvenPseudo 2752 UINT64_C(0), // VLD4DUPq16OddPseudo 2753 UINT64_C(0), // VLD4DUPq16OddPseudo_UPD 2754 UINT64_C(4104130400), // VLD4DUPq16_UPD 2755 UINT64_C(4104130479), // VLD4DUPq32 2756 UINT64_C(0), // VLD4DUPq32EvenPseudo 2757 UINT64_C(0), // VLD4DUPq32OddPseudo 2758 UINT64_C(0), // VLD4DUPq32OddPseudo_UPD 2759 UINT64_C(4104130464), // VLD4DUPq32_UPD 2760 UINT64_C(4104130351), // VLD4DUPq8 2761 UINT64_C(0), // VLD4DUPq8EvenPseudo 2762 UINT64_C(0), // VLD4DUPq8OddPseudo 2763 UINT64_C(0), // VLD4DUPq8OddPseudo_UPD 2764 UINT64_C(4104130336), // VLD4DUPq8_UPD 2765 UINT64_C(4104128271), // VLD4LNd16 2766 UINT64_C(0), // VLD4LNd16Pseudo 2767 UINT64_C(0), // VLD4LNd16Pseudo_UPD 2768 UINT64_C(4104128256), // VLD4LNd16_UPD 2769 UINT64_C(4104129295), // VLD4LNd32 2770 UINT64_C(0), // VLD4LNd32Pseudo 2771 UINT64_C(0), // VLD4LNd32Pseudo_UPD 2772 UINT64_C(4104129280), // VLD4LNd32_UPD 2773 UINT64_C(4104127247), // VLD4LNd8 2774 UINT64_C(0), // VLD4LNd8Pseudo 2775 UINT64_C(0), // VLD4LNd8Pseudo_UPD 2776 UINT64_C(4104127232), // VLD4LNd8_UPD 2777 UINT64_C(4104128303), // VLD4LNq16 2778 UINT64_C(0), // VLD4LNq16Pseudo 2779 UINT64_C(0), // VLD4LNq16Pseudo_UPD 2780 UINT64_C(4104128288), // VLD4LNq16_UPD 2781 UINT64_C(4104129359), // VLD4LNq32 2782 UINT64_C(0), // VLD4LNq32Pseudo 2783 UINT64_C(0), // VLD4LNq32Pseudo_UPD 2784 UINT64_C(4104129344), // VLD4LNq32_UPD 2785 UINT64_C(4095737935), // VLD4d16 2786 UINT64_C(0), // VLD4d16Pseudo 2787 UINT64_C(0), // VLD4d16Pseudo_UPD 2788 UINT64_C(4095737920), // VLD4d16_UPD 2789 UINT64_C(4095737999), // VLD4d32 2790 UINT64_C(0), // VLD4d32Pseudo 2791 UINT64_C(0), // VLD4d32Pseudo_UPD 2792 UINT64_C(4095737984), // VLD4d32_UPD 2793 UINT64_C(4095737871), // VLD4d8 2794 UINT64_C(0), // VLD4d8Pseudo 2795 UINT64_C(0), // VLD4d8Pseudo_UPD 2796 UINT64_C(4095737856), // VLD4d8_UPD 2797 UINT64_C(4095738191), // VLD4q16 2798 UINT64_C(0), // VLD4q16Pseudo_UPD 2799 UINT64_C(4095738176), // VLD4q16_UPD 2800 UINT64_C(0), // VLD4q16oddPseudo 2801 UINT64_C(0), // VLD4q16oddPseudo_UPD 2802 UINT64_C(4095738255), // VLD4q32 2803 UINT64_C(0), // VLD4q32Pseudo_UPD 2804 UINT64_C(4095738240), // VLD4q32_UPD 2805 UINT64_C(0), // VLD4q32oddPseudo 2806 UINT64_C(0), // VLD4q32oddPseudo_UPD 2807 UINT64_C(4095738127), // VLD4q8 2808 UINT64_C(0), // VLD4q8Pseudo_UPD 2809 UINT64_C(4095738112), // VLD4q8_UPD 2810 UINT64_C(0), // VLD4q8oddPseudo 2811 UINT64_C(0), // VLD4q8oddPseudo_UPD 2812 UINT64_C(221252352), // VLDMDDB_UPD 2813 UINT64_C(210766592), // VLDMDIA 2814 UINT64_C(212863744), // VLDMDIA_UPD 2815 UINT64_C(0), // VLDMQIA 2816 UINT64_C(221252096), // VLDMSDB_UPD 2817 UINT64_C(210766336), // VLDMSIA 2818 UINT64_C(212863488), // VLDMSIA_UPD 2819 UINT64_C(219155200), // VLDRD 2820 UINT64_C(219154688), // VLDRH 2821 UINT64_C(219154944), // VLDRS 2822 UINT64_C(223399808), // VLDR_FPCXTNS_off 2823 UINT64_C(208719744), // VLDR_FPCXTNS_post 2824 UINT64_C(225496960), // VLDR_FPCXTNS_pre 2825 UINT64_C(223408000), // VLDR_FPCXTS_off 2826 UINT64_C(208727936), // VLDR_FPCXTS_post 2827 UINT64_C(225505152), // VLDR_FPCXTS_pre 2828 UINT64_C(219172736), // VLDR_FPSCR_NZCVQC_off 2829 UINT64_C(204492672), // VLDR_FPSCR_NZCVQC_post 2830 UINT64_C(221269888), // VLDR_FPSCR_NZCVQC_pre 2831 UINT64_C(219164544), // VLDR_FPSCR_off 2832 UINT64_C(204484480), // VLDR_FPSCR_post 2833 UINT64_C(221261696), // VLDR_FPSCR_pre 2834 UINT64_C(223391616), // VLDR_P0_off 2835 UINT64_C(208711552), // VLDR_P0_post 2836 UINT64_C(225488768), // VLDR_P0_pre 2837 UINT64_C(223383424), // VLDR_VPR_off 2838 UINT64_C(208703360), // VLDR_VPR_post 2839 UINT64_C(225480576), // VLDR_VPR_pre 2840 UINT64_C(204474880), // VLLDM 2841 UINT64_C(203426304), // VLSTM 2842 UINT64_C(4060090112), // VMAXfd 2843 UINT64_C(4060090176), // VMAXfq 2844 UINT64_C(4061138688), // VMAXhd 2845 UINT64_C(4061138752), // VMAXhq 2846 UINT64_C(4060087872), // VMAXsv16i8 2847 UINT64_C(4062184960), // VMAXsv2i32 2848 UINT64_C(4061136384), // VMAXsv4i16 2849 UINT64_C(4062185024), // VMAXsv4i32 2850 UINT64_C(4061136448), // VMAXsv8i16 2851 UINT64_C(4060087808), // VMAXsv8i8 2852 UINT64_C(4076865088), // VMAXuv16i8 2853 UINT64_C(4078962176), // VMAXuv2i32 2854 UINT64_C(4077913600), // VMAXuv4i16 2855 UINT64_C(4078962240), // VMAXuv4i32 2856 UINT64_C(4077913664), // VMAXuv8i16 2857 UINT64_C(4076865024), // VMAXuv8i8 2858 UINT64_C(4062187264), // VMINfd 2859 UINT64_C(4062187328), // VMINfq 2860 UINT64_C(4063235840), // VMINhd 2861 UINT64_C(4063235904), // VMINhq 2862 UINT64_C(4060087888), // VMINsv16i8 2863 UINT64_C(4062184976), // VMINsv2i32 2864 UINT64_C(4061136400), // VMINsv4i16 2865 UINT64_C(4062185040), // VMINsv4i32 2866 UINT64_C(4061136464), // VMINsv8i16 2867 UINT64_C(4060087824), // VMINsv8i8 2868 UINT64_C(4076865104), // VMINuv16i8 2869 UINT64_C(4078962192), // VMINuv2i32 2870 UINT64_C(4077913616), // VMINuv4i16 2871 UINT64_C(4078962256), // VMINuv4i32 2872 UINT64_C(4077913680), // VMINuv8i16 2873 UINT64_C(4076865040), // VMINuv8i8 2874 UINT64_C(234883840), // VMLAD 2875 UINT64_C(234883328), // VMLAH 2876 UINT64_C(4070572608), // VMLALslsv2i32 2877 UINT64_C(4069524032), // VMLALslsv4i16 2878 UINT64_C(4087349824), // VMLALsluv2i32 2879 UINT64_C(4086301248), // VMLALsluv4i16 2880 UINT64_C(4070574080), // VMLALsv2i64 2881 UINT64_C(4069525504), // VMLALsv4i32 2882 UINT64_C(4068476928), // VMLALsv8i16 2883 UINT64_C(4087351296), // VMLALuv2i64 2884 UINT64_C(4086302720), // VMLALuv4i32 2885 UINT64_C(4085254144), // VMLALuv8i16 2886 UINT64_C(234883584), // VMLAS 2887 UINT64_C(4060089616), // VMLAfd 2888 UINT64_C(4060089680), // VMLAfq 2889 UINT64_C(4061138192), // VMLAhd 2890 UINT64_C(4061138256), // VMLAhq 2891 UINT64_C(4070572352), // VMLAslfd 2892 UINT64_C(4087349568), // VMLAslfq 2893 UINT64_C(4069523776), // VMLAslhd 2894 UINT64_C(4086300992), // VMLAslhq 2895 UINT64_C(4070572096), // VMLAslv2i32 2896 UINT64_C(4069523520), // VMLAslv4i16 2897 UINT64_C(4087349312), // VMLAslv4i32 2898 UINT64_C(4086300736), // VMLAslv8i16 2899 UINT64_C(4060088640), // VMLAv16i8 2900 UINT64_C(4062185728), // VMLAv2i32 2901 UINT64_C(4061137152), // VMLAv4i16 2902 UINT64_C(4062185792), // VMLAv4i32 2903 UINT64_C(4061137216), // VMLAv8i16 2904 UINT64_C(4060088576), // VMLAv8i8 2905 UINT64_C(234883904), // VMLSD 2906 UINT64_C(234883392), // VMLSH 2907 UINT64_C(4070573632), // VMLSLslsv2i32 2908 UINT64_C(4069525056), // VMLSLslsv4i16 2909 UINT64_C(4087350848), // VMLSLsluv2i32 2910 UINT64_C(4086302272), // VMLSLsluv4i16 2911 UINT64_C(4070574592), // VMLSLsv2i64 2912 UINT64_C(4069526016), // VMLSLsv4i32 2913 UINT64_C(4068477440), // VMLSLsv8i16 2914 UINT64_C(4087351808), // VMLSLuv2i64 2915 UINT64_C(4086303232), // VMLSLuv4i32 2916 UINT64_C(4085254656), // VMLSLuv8i16 2917 UINT64_C(234883648), // VMLSS 2918 UINT64_C(4062186768), // VMLSfd 2919 UINT64_C(4062186832), // VMLSfq 2920 UINT64_C(4063235344), // VMLShd 2921 UINT64_C(4063235408), // VMLShq 2922 UINT64_C(4070573376), // VMLSslfd 2923 UINT64_C(4087350592), // VMLSslfq 2924 UINT64_C(4069524800), // VMLSslhd 2925 UINT64_C(4086302016), // VMLSslhq 2926 UINT64_C(4070573120), // VMLSslv2i32 2927 UINT64_C(4069524544), // VMLSslv4i16 2928 UINT64_C(4087350336), // VMLSslv4i32 2929 UINT64_C(4086301760), // VMLSslv8i16 2930 UINT64_C(4076865856), // VMLSv16i8 2931 UINT64_C(4078962944), // VMLSv2i32 2932 UINT64_C(4077914368), // VMLSv4i16 2933 UINT64_C(4078963008), // VMLSv4i32 2934 UINT64_C(4077914432), // VMLSv8i16 2935 UINT64_C(4076865792), // VMLSv8i8 2936 UINT64_C(4227861568), // VMMLA 2937 UINT64_C(246418240), // VMOVD 2938 UINT64_C(205523728), // VMOVDRR 2939 UINT64_C(4272949824), // VMOVH 2940 UINT64_C(234883344), // VMOVHR 2941 UINT64_C(4070574608), // VMOVLsv2i64 2942 UINT64_C(4069526032), // VMOVLsv4i32 2943 UINT64_C(4069001744), // VMOVLsv8i16 2944 UINT64_C(4087351824), // VMOVLuv2i64 2945 UINT64_C(4086303248), // VMOVLuv4i32 2946 UINT64_C(4085778960), // VMOVLuv8i16 2947 UINT64_C(4089053696), // VMOVNv2i32 2948 UINT64_C(4088791552), // VMOVNv4i16 2949 UINT64_C(4088529408), // VMOVNv8i8 2950 UINT64_C(235931920), // VMOVRH 2951 UINT64_C(206572304), // VMOVRRD 2952 UINT64_C(206572048), // VMOVRRS 2953 UINT64_C(235932176), // VMOVRS 2954 UINT64_C(246417984), // VMOVS 2955 UINT64_C(234883600), // VMOVSR 2956 UINT64_C(205523472), // VMOVSRR 2957 UINT64_C(4068478544), // VMOVv16i8 2958 UINT64_C(4068478512), // VMOVv1i64 2959 UINT64_C(4068478736), // VMOVv2f32 2960 UINT64_C(4068474896), // VMOVv2i32 2961 UINT64_C(4068478576), // VMOVv2i64 2962 UINT64_C(4068478800), // VMOVv4f32 2963 UINT64_C(4068476944), // VMOVv4i16 2964 UINT64_C(4068474960), // VMOVv4i32 2965 UINT64_C(4068477008), // VMOVv8i16 2966 UINT64_C(4068478480), // VMOVv8i8 2967 UINT64_C(250677776), // VMRS 2968 UINT64_C(251529744), // VMRS_FPCXTNS 2969 UINT64_C(251595280), // VMRS_FPCXTS 2970 UINT64_C(251136528), // VMRS_FPEXC 2971 UINT64_C(251202064), // VMRS_FPINST 2972 UINT64_C(251267600), // VMRS_FPINST2 2973 UINT64_C(250743312), // VMRS_FPSCR_NZCVQC 2974 UINT64_C(250612240), // VMRS_FPSID 2975 UINT64_C(251070992), // VMRS_MVFR0 2976 UINT64_C(251005456), // VMRS_MVFR1 2977 UINT64_C(250939920), // VMRS_MVFR2 2978 UINT64_C(251464208), // VMRS_P0 2979 UINT64_C(251398672), // VMRS_VPR 2980 UINT64_C(249629200), // VMSR 2981 UINT64_C(250481168), // VMSR_FPCXTNS 2982 UINT64_C(250546704), // VMSR_FPCXTS 2983 UINT64_C(250087952), // VMSR_FPEXC 2984 UINT64_C(250153488), // VMSR_FPINST 2985 UINT64_C(250219024), // VMSR_FPINST2 2986 UINT64_C(249694736), // VMSR_FPSCR_NZCVQC 2987 UINT64_C(249563664), // VMSR_FPSID 2988 UINT64_C(250415632), // VMSR_P0 2989 UINT64_C(250350096), // VMSR_VPR 2990 UINT64_C(236980992), // VMULD 2991 UINT64_C(236980480), // VMULH 2992 UINT64_C(4070575616), // VMULLp64 2993 UINT64_C(4068478464), // VMULLp8 2994 UINT64_C(4070574656), // VMULLslsv2i32 2995 UINT64_C(4069526080), // VMULLslsv4i16 2996 UINT64_C(4087351872), // VMULLsluv2i32 2997 UINT64_C(4086303296), // VMULLsluv4i16 2998 UINT64_C(4070575104), // VMULLsv2i64 2999 UINT64_C(4069526528), // VMULLsv4i32 3000 UINT64_C(4068477952), // VMULLsv8i16 3001 UINT64_C(4087352320), // VMULLuv2i64 3002 UINT64_C(4086303744), // VMULLuv4i32 3003 UINT64_C(4085255168), // VMULLuv8i16 3004 UINT64_C(236980736), // VMULS 3005 UINT64_C(4076866832), // VMULfd 3006 UINT64_C(4076866896), // VMULfq 3007 UINT64_C(4077915408), // VMULhd 3008 UINT64_C(4077915472), // VMULhq 3009 UINT64_C(4076865808), // VMULpd 3010 UINT64_C(4076865872), // VMULpq 3011 UINT64_C(4070574400), // VMULslfd 3012 UINT64_C(4087351616), // VMULslfq 3013 UINT64_C(4069525824), // VMULslhd 3014 UINT64_C(4086303040), // VMULslhq 3015 UINT64_C(4070574144), // VMULslv2i32 3016 UINT64_C(4069525568), // VMULslv4i16 3017 UINT64_C(4087351360), // VMULslv4i32 3018 UINT64_C(4086302784), // VMULslv8i16 3019 UINT64_C(4060088656), // VMULv16i8 3020 UINT64_C(4062185744), // VMULv2i32 3021 UINT64_C(4061137168), // VMULv4i16 3022 UINT64_C(4062185808), // VMULv4i32 3023 UINT64_C(4061137232), // VMULv8i16 3024 UINT64_C(4060088592), // VMULv8i8 3025 UINT64_C(4088399232), // VMVNd 3026 UINT64_C(4088399296), // VMVNq 3027 UINT64_C(4068474928), // VMVNv2i32 3028 UINT64_C(4068476976), // VMVNv4i16 3029 UINT64_C(4068474992), // VMVNv4i32 3030 UINT64_C(4068477040), // VMVNv8i16 3031 UINT64_C(246483776), // VNEGD 3032 UINT64_C(246483264), // VNEGH 3033 UINT64_C(246483520), // VNEGS 3034 UINT64_C(4088989632), // VNEGf32q 3035 UINT64_C(4088989568), // VNEGfd 3036 UINT64_C(4088727424), // VNEGhd 3037 UINT64_C(4088727488), // VNEGhq 3038 UINT64_C(4088726400), // VNEGs16d 3039 UINT64_C(4088726464), // VNEGs16q 3040 UINT64_C(4088988544), // VNEGs32d 3041 UINT64_C(4088988608), // VNEGs32q 3042 UINT64_C(4088464256), // VNEGs8d 3043 UINT64_C(4088464320), // VNEGs8q 3044 UINT64_C(235932480), // VNMLAD 3045 UINT64_C(235931968), // VNMLAH 3046 UINT64_C(235932224), // VNMLAS 3047 UINT64_C(235932416), // VNMLSD 3048 UINT64_C(235931904), // VNMLSH 3049 UINT64_C(235932160), // VNMLSS 3050 UINT64_C(236981056), // VNMULD 3051 UINT64_C(236980544), // VNMULH 3052 UINT64_C(236980800), // VNMULS 3053 UINT64_C(4063232272), // VORNd 3054 UINT64_C(4063232336), // VORNq 3055 UINT64_C(4062183696), // VORRd 3056 UINT64_C(4068475152), // VORRiv2i32 3057 UINT64_C(4068477200), // VORRiv4i16 3058 UINT64_C(4068475216), // VORRiv4i32 3059 UINT64_C(4068477264), // VORRiv8i16 3060 UINT64_C(4062183760), // VORRq 3061 UINT64_C(4088399424), // VPADALsv16i8 3062 UINT64_C(4088923648), // VPADALsv2i32 3063 UINT64_C(4088661504), // VPADALsv4i16 3064 UINT64_C(4088923712), // VPADALsv4i32 3065 UINT64_C(4088661568), // VPADALsv8i16 3066 UINT64_C(4088399360), // VPADALsv8i8 3067 UINT64_C(4088399552), // VPADALuv16i8 3068 UINT64_C(4088923776), // VPADALuv2i32 3069 UINT64_C(4088661632), // VPADALuv4i16 3070 UINT64_C(4088923840), // VPADALuv4i32 3071 UINT64_C(4088661696), // VPADALuv8i16 3072 UINT64_C(4088399488), // VPADALuv8i8 3073 UINT64_C(4088398400), // VPADDLsv16i8 3074 UINT64_C(4088922624), // VPADDLsv2i32 3075 UINT64_C(4088660480), // VPADDLsv4i16 3076 UINT64_C(4088922688), // VPADDLsv4i32 3077 UINT64_C(4088660544), // VPADDLsv8i16 3078 UINT64_C(4088398336), // VPADDLsv8i8 3079 UINT64_C(4088398528), // VPADDLuv16i8 3080 UINT64_C(4088922752), // VPADDLuv2i32 3081 UINT64_C(4088660608), // VPADDLuv4i16 3082 UINT64_C(4088922816), // VPADDLuv4i32 3083 UINT64_C(4088660672), // VPADDLuv8i16 3084 UINT64_C(4088398464), // VPADDLuv8i8 3085 UINT64_C(4076866816), // VPADDf 3086 UINT64_C(4077915392), // VPADDh 3087 UINT64_C(4061137680), // VPADDi16 3088 UINT64_C(4062186256), // VPADDi32 3089 UINT64_C(4060089104), // VPADDi8 3090 UINT64_C(4076867328), // VPMAXf 3091 UINT64_C(4077915904), // VPMAXh 3092 UINT64_C(4061137408), // VPMAXs16 3093 UINT64_C(4062185984), // VPMAXs32 3094 UINT64_C(4060088832), // VPMAXs8 3095 UINT64_C(4077914624), // VPMAXu16 3096 UINT64_C(4078963200), // VPMAXu32 3097 UINT64_C(4076866048), // VPMAXu8 3098 UINT64_C(4078964480), // VPMINf 3099 UINT64_C(4080013056), // VPMINh 3100 UINT64_C(4061137424), // VPMINs16 3101 UINT64_C(4062186000), // VPMINs32 3102 UINT64_C(4060088848), // VPMINs8 3103 UINT64_C(4077914640), // VPMINu16 3104 UINT64_C(4078963216), // VPMINu32 3105 UINT64_C(4076866064), // VPMINu8 3106 UINT64_C(4088399680), // VQABSv16i8 3107 UINT64_C(4088923904), // VQABSv2i32 3108 UINT64_C(4088661760), // VQABSv4i16 3109 UINT64_C(4088923968), // VQABSv4i32 3110 UINT64_C(4088661824), // VQABSv8i16 3111 UINT64_C(4088399616), // VQABSv8i8 3112 UINT64_C(4060086352), // VQADDsv16i8 3113 UINT64_C(4063232016), // VQADDsv1i64 3114 UINT64_C(4062183440), // VQADDsv2i32 3115 UINT64_C(4063232080), // VQADDsv2i64 3116 UINT64_C(4061134864), // VQADDsv4i16 3117 UINT64_C(4062183504), // VQADDsv4i32 3118 UINT64_C(4061134928), // VQADDsv8i16 3119 UINT64_C(4060086288), // VQADDsv8i8 3120 UINT64_C(4076863568), // VQADDuv16i8 3121 UINT64_C(4080009232), // VQADDuv1i64 3122 UINT64_C(4078960656), // VQADDuv2i32 3123 UINT64_C(4080009296), // VQADDuv2i64 3124 UINT64_C(4077912080), // VQADDuv4i16 3125 UINT64_C(4078960720), // VQADDuv4i32 3126 UINT64_C(4077912144), // VQADDuv8i16 3127 UINT64_C(4076863504), // VQADDuv8i8 3128 UINT64_C(4070572864), // VQDMLALslv2i32 3129 UINT64_C(4069524288), // VQDMLALslv4i16 3130 UINT64_C(4070574336), // VQDMLALv2i64 3131 UINT64_C(4069525760), // VQDMLALv4i32 3132 UINT64_C(4070573888), // VQDMLSLslv2i32 3133 UINT64_C(4069525312), // VQDMLSLslv4i16 3134 UINT64_C(4070574848), // VQDMLSLv2i64 3135 UINT64_C(4069526272), // VQDMLSLv4i32 3136 UINT64_C(4070575168), // VQDMULHslv2i32 3137 UINT64_C(4069526592), // VQDMULHslv4i16 3138 UINT64_C(4087352384), // VQDMULHslv4i32 3139 UINT64_C(4086303808), // VQDMULHslv8i16 3140 UINT64_C(4062186240), // VQDMULHv2i32 3141 UINT64_C(4061137664), // VQDMULHv4i16 3142 UINT64_C(4062186304), // VQDMULHv4i32 3143 UINT64_C(4061137728), // VQDMULHv8i16 3144 UINT64_C(4070574912), // VQDMULLslv2i32 3145 UINT64_C(4069526336), // VQDMULLslv4i16 3146 UINT64_C(4070575360), // VQDMULLv2i64 3147 UINT64_C(4069526784), // VQDMULLv4i32 3148 UINT64_C(4089053760), // VQMOVNsuv2i32 3149 UINT64_C(4088791616), // VQMOVNsuv4i16 3150 UINT64_C(4088529472), // VQMOVNsuv8i8 3151 UINT64_C(4089053824), // VQMOVNsv2i32 3152 UINT64_C(4088791680), // VQMOVNsv4i16 3153 UINT64_C(4088529536), // VQMOVNsv8i8 3154 UINT64_C(4089053888), // VQMOVNuv2i32 3155 UINT64_C(4088791744), // VQMOVNuv4i16 3156 UINT64_C(4088529600), // VQMOVNuv8i8 3157 UINT64_C(4088399808), // VQNEGv16i8 3158 UINT64_C(4088924032), // VQNEGv2i32 3159 UINT64_C(4088661888), // VQNEGv4i16 3160 UINT64_C(4088924096), // VQNEGv4i32 3161 UINT64_C(4088661952), // VQNEGv8i16 3162 UINT64_C(4088399744), // VQNEGv8i8 3163 UINT64_C(4070575680), // VQRDMLAHslv2i32 3164 UINT64_C(4069527104), // VQRDMLAHslv4i16 3165 UINT64_C(4087352896), // VQRDMLAHslv4i32 3166 UINT64_C(4086304320), // VQRDMLAHslv8i16 3167 UINT64_C(4078963472), // VQRDMLAHv2i32 3168 UINT64_C(4077914896), // VQRDMLAHv4i16 3169 UINT64_C(4078963536), // VQRDMLAHv4i32 3170 UINT64_C(4077914960), // VQRDMLAHv8i16 3171 UINT64_C(4070575936), // VQRDMLSHslv2i32 3172 UINT64_C(4069527360), // VQRDMLSHslv4i16 3173 UINT64_C(4087353152), // VQRDMLSHslv4i32 3174 UINT64_C(4086304576), // VQRDMLSHslv8i16 3175 UINT64_C(4078963728), // VQRDMLSHv2i32 3176 UINT64_C(4077915152), // VQRDMLSHv4i16 3177 UINT64_C(4078963792), // VQRDMLSHv4i32 3178 UINT64_C(4077915216), // VQRDMLSHv8i16 3179 UINT64_C(4070575424), // VQRDMULHslv2i32 3180 UINT64_C(4069526848), // VQRDMULHslv4i16 3181 UINT64_C(4087352640), // VQRDMULHslv4i32 3182 UINT64_C(4086304064), // VQRDMULHslv8i16 3183 UINT64_C(4078963456), // VQRDMULHv2i32 3184 UINT64_C(4077914880), // VQRDMULHv4i16 3185 UINT64_C(4078963520), // VQRDMULHv4i32 3186 UINT64_C(4077914944), // VQRDMULHv8i16 3187 UINT64_C(4060087632), // VQRSHLsv16i8 3188 UINT64_C(4063233296), // VQRSHLsv1i64 3189 UINT64_C(4062184720), // VQRSHLsv2i32 3190 UINT64_C(4063233360), // VQRSHLsv2i64 3191 UINT64_C(4061136144), // VQRSHLsv4i16 3192 UINT64_C(4062184784), // VQRSHLsv4i32 3193 UINT64_C(4061136208), // VQRSHLsv8i16 3194 UINT64_C(4060087568), // VQRSHLsv8i8 3195 UINT64_C(4076864848), // VQRSHLuv16i8 3196 UINT64_C(4080010512), // VQRSHLuv1i64 3197 UINT64_C(4078961936), // VQRSHLuv2i32 3198 UINT64_C(4080010576), // VQRSHLuv2i64 3199 UINT64_C(4077913360), // VQRSHLuv4i16 3200 UINT64_C(4078962000), // VQRSHLuv4i32 3201 UINT64_C(4077913424), // VQRSHLuv8i16 3202 UINT64_C(4076864784), // VQRSHLuv8i8 3203 UINT64_C(4070574416), // VQRSHRNsv2i32 3204 UINT64_C(4069525840), // VQRSHRNsv4i16 3205 UINT64_C(4069001552), // VQRSHRNsv8i8 3206 UINT64_C(4087351632), // VQRSHRNuv2i32 3207 UINT64_C(4086303056), // VQRSHRNuv4i16 3208 UINT64_C(4085778768), // VQRSHRNuv8i8 3209 UINT64_C(4087351376), // VQRSHRUNv2i32 3210 UINT64_C(4086302800), // VQRSHRUNv4i16 3211 UINT64_C(4085778512), // VQRSHRUNv8i8 3212 UINT64_C(4069001040), // VQSHLsiv16i8 3213 UINT64_C(4068476816), // VQSHLsiv1i64 3214 UINT64_C(4070573840), // VQSHLsiv2i32 3215 UINT64_C(4068476880), // VQSHLsiv2i64 3216 UINT64_C(4069525264), // VQSHLsiv4i16 3217 UINT64_C(4070573904), // VQSHLsiv4i32 3218 UINT64_C(4069525328), // VQSHLsiv8i16 3219 UINT64_C(4069000976), // VQSHLsiv8i8 3220 UINT64_C(4085778000), // VQSHLsuv16i8 3221 UINT64_C(4085253776), // VQSHLsuv1i64 3222 UINT64_C(4087350800), // VQSHLsuv2i32 3223 UINT64_C(4085253840), // VQSHLsuv2i64 3224 UINT64_C(4086302224), // VQSHLsuv4i16 3225 UINT64_C(4087350864), // VQSHLsuv4i32 3226 UINT64_C(4086302288), // VQSHLsuv8i16 3227 UINT64_C(4085777936), // VQSHLsuv8i8 3228 UINT64_C(4060087376), // VQSHLsv16i8 3229 UINT64_C(4063233040), // VQSHLsv1i64 3230 UINT64_C(4062184464), // VQSHLsv2i32 3231 UINT64_C(4063233104), // VQSHLsv2i64 3232 UINT64_C(4061135888), // VQSHLsv4i16 3233 UINT64_C(4062184528), // VQSHLsv4i32 3234 UINT64_C(4061135952), // VQSHLsv8i16 3235 UINT64_C(4060087312), // VQSHLsv8i8 3236 UINT64_C(4085778256), // VQSHLuiv16i8 3237 UINT64_C(4085254032), // VQSHLuiv1i64 3238 UINT64_C(4087351056), // VQSHLuiv2i32 3239 UINT64_C(4085254096), // VQSHLuiv2i64 3240 UINT64_C(4086302480), // VQSHLuiv4i16 3241 UINT64_C(4087351120), // VQSHLuiv4i32 3242 UINT64_C(4086302544), // VQSHLuiv8i16 3243 UINT64_C(4085778192), // VQSHLuiv8i8 3244 UINT64_C(4076864592), // VQSHLuv16i8 3245 UINT64_C(4080010256), // VQSHLuv1i64 3246 UINT64_C(4078961680), // VQSHLuv2i32 3247 UINT64_C(4080010320), // VQSHLuv2i64 3248 UINT64_C(4077913104), // VQSHLuv4i16 3249 UINT64_C(4078961744), // VQSHLuv4i32 3250 UINT64_C(4077913168), // VQSHLuv8i16 3251 UINT64_C(4076864528), // VQSHLuv8i8 3252 UINT64_C(4070574352), // VQSHRNsv2i32 3253 UINT64_C(4069525776), // VQSHRNsv4i16 3254 UINT64_C(4069001488), // VQSHRNsv8i8 3255 UINT64_C(4087351568), // VQSHRNuv2i32 3256 UINT64_C(4086302992), // VQSHRNuv4i16 3257 UINT64_C(4085778704), // VQSHRNuv8i8 3258 UINT64_C(4087351312), // VQSHRUNv2i32 3259 UINT64_C(4086302736), // VQSHRUNv4i16 3260 UINT64_C(4085778448), // VQSHRUNv8i8 3261 UINT64_C(4060086864), // VQSUBsv16i8 3262 UINT64_C(4063232528), // VQSUBsv1i64 3263 UINT64_C(4062183952), // VQSUBsv2i32 3264 UINT64_C(4063232592), // VQSUBsv2i64 3265 UINT64_C(4061135376), // VQSUBsv4i16 3266 UINT64_C(4062184016), // VQSUBsv4i32 3267 UINT64_C(4061135440), // VQSUBsv8i16 3268 UINT64_C(4060086800), // VQSUBsv8i8 3269 UINT64_C(4076864080), // VQSUBuv16i8 3270 UINT64_C(4080009744), // VQSUBuv1i64 3271 UINT64_C(4078961168), // VQSUBuv2i32 3272 UINT64_C(4080009808), // VQSUBuv2i64 3273 UINT64_C(4077912592), // VQSUBuv4i16 3274 UINT64_C(4078961232), // VQSUBuv4i32 3275 UINT64_C(4077912656), // VQSUBuv8i16 3276 UINT64_C(4076864016), // VQSUBuv8i8 3277 UINT64_C(4087350272), // VRADDHNv2i32 3278 UINT64_C(4086301696), // VRADDHNv4i16 3279 UINT64_C(4085253120), // VRADDHNv8i8 3280 UINT64_C(4089119744), // VRECPEd 3281 UINT64_C(4089120000), // VRECPEfd 3282 UINT64_C(4089120064), // VRECPEfq 3283 UINT64_C(4088857856), // VRECPEhd 3284 UINT64_C(4088857920), // VRECPEhq 3285 UINT64_C(4089119808), // VRECPEq 3286 UINT64_C(4060090128), // VRECPSfd 3287 UINT64_C(4060090192), // VRECPSfq 3288 UINT64_C(4061138704), // VRECPShd 3289 UINT64_C(4061138768), // VRECPShq 3290 UINT64_C(4088398080), // VREV16d8 3291 UINT64_C(4088398144), // VREV16q8 3292 UINT64_C(4088660096), // VREV32d16 3293 UINT64_C(4088397952), // VREV32d8 3294 UINT64_C(4088660160), // VREV32q16 3295 UINT64_C(4088398016), // VREV32q8 3296 UINT64_C(4088659968), // VREV64d16 3297 UINT64_C(4088922112), // VREV64d32 3298 UINT64_C(4088397824), // VREV64d8 3299 UINT64_C(4088660032), // VREV64q16 3300 UINT64_C(4088922176), // VREV64q32 3301 UINT64_C(4088397888), // VREV64q8 3302 UINT64_C(4060086592), // VRHADDsv16i8 3303 UINT64_C(4062183680), // VRHADDsv2i32 3304 UINT64_C(4061135104), // VRHADDsv4i16 3305 UINT64_C(4062183744), // VRHADDsv4i32 3306 UINT64_C(4061135168), // VRHADDsv8i16 3307 UINT64_C(4060086528), // VRHADDsv8i8 3308 UINT64_C(4076863808), // VRHADDuv16i8 3309 UINT64_C(4078960896), // VRHADDuv2i32 3310 UINT64_C(4077912320), // VRHADDuv4i16 3311 UINT64_C(4078960960), // VRHADDuv4i32 3312 UINT64_C(4077912384), // VRHADDuv8i16 3313 UINT64_C(4076863744), // VRHADDuv8i8 3314 UINT64_C(4273474368), // VRINTAD 3315 UINT64_C(4273473856), // VRINTAH 3316 UINT64_C(4089054464), // VRINTANDf 3317 UINT64_C(4088792320), // VRINTANDh 3318 UINT64_C(4089054528), // VRINTANQf 3319 UINT64_C(4088792384), // VRINTANQh 3320 UINT64_C(4273474112), // VRINTAS 3321 UINT64_C(4273670976), // VRINTMD 3322 UINT64_C(4273670464), // VRINTMH 3323 UINT64_C(4089054848), // VRINTMNDf 3324 UINT64_C(4088792704), // VRINTMNDh 3325 UINT64_C(4089054912), // VRINTMNQf 3326 UINT64_C(4088792768), // VRINTMNQh 3327 UINT64_C(4273670720), // VRINTMS 3328 UINT64_C(4273539904), // VRINTND 3329 UINT64_C(4273539392), // VRINTNH 3330 UINT64_C(4089054208), // VRINTNNDf 3331 UINT64_C(4088792064), // VRINTNNDh 3332 UINT64_C(4089054272), // VRINTNNQf 3333 UINT64_C(4088792128), // VRINTNNQh 3334 UINT64_C(4273539648), // VRINTNS 3335 UINT64_C(4273605440), // VRINTPD 3336 UINT64_C(4273604928), // VRINTPH 3337 UINT64_C(4089055104), // VRINTPNDf 3338 UINT64_C(4088792960), // VRINTPNDh 3339 UINT64_C(4089055168), // VRINTPNQf 3340 UINT64_C(4088793024), // VRINTPNQh 3341 UINT64_C(4273605184), // VRINTPS 3342 UINT64_C(246811456), // VRINTRD 3343 UINT64_C(246810944), // VRINTRH 3344 UINT64_C(246811200), // VRINTRS 3345 UINT64_C(246876992), // VRINTXD 3346 UINT64_C(246876480), // VRINTXH 3347 UINT64_C(4089054336), // VRINTXNDf 3348 UINT64_C(4088792192), // VRINTXNDh 3349 UINT64_C(4089054400), // VRINTXNQf 3350 UINT64_C(4088792256), // VRINTXNQh 3351 UINT64_C(246876736), // VRINTXS 3352 UINT64_C(246811584), // VRINTZD 3353 UINT64_C(246811072), // VRINTZH 3354 UINT64_C(4089054592), // VRINTZNDf 3355 UINT64_C(4088792448), // VRINTZNDh 3356 UINT64_C(4089054656), // VRINTZNQf 3357 UINT64_C(4088792512), // VRINTZNQh 3358 UINT64_C(246811328), // VRINTZS 3359 UINT64_C(4060087616), // VRSHLsv16i8 3360 UINT64_C(4063233280), // VRSHLsv1i64 3361 UINT64_C(4062184704), // VRSHLsv2i32 3362 UINT64_C(4063233344), // VRSHLsv2i64 3363 UINT64_C(4061136128), // VRSHLsv4i16 3364 UINT64_C(4062184768), // VRSHLsv4i32 3365 UINT64_C(4061136192), // VRSHLsv8i16 3366 UINT64_C(4060087552), // VRSHLsv8i8 3367 UINT64_C(4076864832), // VRSHLuv16i8 3368 UINT64_C(4080010496), // VRSHLuv1i64 3369 UINT64_C(4078961920), // VRSHLuv2i32 3370 UINT64_C(4080010560), // VRSHLuv2i64 3371 UINT64_C(4077913344), // VRSHLuv4i16 3372 UINT64_C(4078961984), // VRSHLuv4i32 3373 UINT64_C(4077913408), // VRSHLuv8i16 3374 UINT64_C(4076864768), // VRSHLuv8i8 3375 UINT64_C(4070574160), // VRSHRNv2i32 3376 UINT64_C(4069525584), // VRSHRNv4i16 3377 UINT64_C(4069001296), // VRSHRNv8i8 3378 UINT64_C(4068999760), // VRSHRsv16i8 3379 UINT64_C(4068475536), // VRSHRsv1i64 3380 UINT64_C(4070572560), // VRSHRsv2i32 3381 UINT64_C(4068475600), // VRSHRsv2i64 3382 UINT64_C(4069523984), // VRSHRsv4i16 3383 UINT64_C(4070572624), // VRSHRsv4i32 3384 UINT64_C(4069524048), // VRSHRsv8i16 3385 UINT64_C(4068999696), // VRSHRsv8i8 3386 UINT64_C(4085776976), // VRSHRuv16i8 3387 UINT64_C(4085252752), // VRSHRuv1i64 3388 UINT64_C(4087349776), // VRSHRuv2i32 3389 UINT64_C(4085252816), // VRSHRuv2i64 3390 UINT64_C(4086301200), // VRSHRuv4i16 3391 UINT64_C(4087349840), // VRSHRuv4i32 3392 UINT64_C(4086301264), // VRSHRuv8i16 3393 UINT64_C(4085776912), // VRSHRuv8i8 3394 UINT64_C(4089119872), // VRSQRTEd 3395 UINT64_C(4089120128), // VRSQRTEfd 3396 UINT64_C(4089120192), // VRSQRTEfq 3397 UINT64_C(4088857984), // VRSQRTEhd 3398 UINT64_C(4088858048), // VRSQRTEhq 3399 UINT64_C(4089119936), // VRSQRTEq 3400 UINT64_C(4062187280), // VRSQRTSfd 3401 UINT64_C(4062187344), // VRSQRTSfq 3402 UINT64_C(4063235856), // VRSQRTShd 3403 UINT64_C(4063235920), // VRSQRTShq 3404 UINT64_C(4069000016), // VRSRAsv16i8 3405 UINT64_C(4068475792), // VRSRAsv1i64 3406 UINT64_C(4070572816), // VRSRAsv2i32 3407 UINT64_C(4068475856), // VRSRAsv2i64 3408 UINT64_C(4069524240), // VRSRAsv4i16 3409 UINT64_C(4070572880), // VRSRAsv4i32 3410 UINT64_C(4069524304), // VRSRAsv8i16 3411 UINT64_C(4068999952), // VRSRAsv8i8 3412 UINT64_C(4085777232), // VRSRAuv16i8 3413 UINT64_C(4085253008), // VRSRAuv1i64 3414 UINT64_C(4087350032), // VRSRAuv2i32 3415 UINT64_C(4085253072), // VRSRAuv2i64 3416 UINT64_C(4086301456), // VRSRAuv4i16 3417 UINT64_C(4087350096), // VRSRAuv4i32 3418 UINT64_C(4086301520), // VRSRAuv8i16 3419 UINT64_C(4085777168), // VRSRAuv8i8 3420 UINT64_C(4087350784), // VRSUBHNv2i32 3421 UINT64_C(4086302208), // VRSUBHNv4i16 3422 UINT64_C(4085253632), // VRSUBHNv8i8 3423 UINT64_C(3969846016), // VSCCLRMD 3424 UINT64_C(3969845760), // VSCCLRMS 3425 UINT64_C(4229958912), // VSDOTD 3426 UINT64_C(4263513344), // VSDOTDI 3427 UINT64_C(4229958976), // VSDOTQ 3428 UINT64_C(4263513408), // VSDOTQI 3429 UINT64_C(4261415680), // VSELEQD 3430 UINT64_C(4261415168), // VSELEQH 3431 UINT64_C(4261415424), // VSELEQS 3432 UINT64_C(4263512832), // VSELGED 3433 UINT64_C(4263512320), // VSELGEH 3434 UINT64_C(4263512576), // VSELGES 3435 UINT64_C(4264561408), // VSELGTD 3436 UINT64_C(4264560896), // VSELGTH 3437 UINT64_C(4264561152), // VSELGTS 3438 UINT64_C(4262464256), // VSELVSD 3439 UINT64_C(4262463744), // VSELVSH 3440 UINT64_C(4262464000), // VSELVSS 3441 UINT64_C(234883888), // VSETLNi16 3442 UINT64_C(234883856), // VSETLNi32 3443 UINT64_C(239078160), // VSETLNi8 3444 UINT64_C(4088791808), // VSHLLi16 3445 UINT64_C(4089053952), // VSHLLi32 3446 UINT64_C(4088529664), // VSHLLi8 3447 UINT64_C(4070574608), // VSHLLsv2i64 3448 UINT64_C(4069526032), // VSHLLsv4i32 3449 UINT64_C(4069001744), // VSHLLsv8i16 3450 UINT64_C(4087351824), // VSHLLuv2i64 3451 UINT64_C(4086303248), // VSHLLuv4i32 3452 UINT64_C(4085778960), // VSHLLuv8i16 3453 UINT64_C(4069000528), // VSHLiv16i8 3454 UINT64_C(4068476304), // VSHLiv1i64 3455 UINT64_C(4070573328), // VSHLiv2i32 3456 UINT64_C(4068476368), // VSHLiv2i64 3457 UINT64_C(4069524752), // VSHLiv4i16 3458 UINT64_C(4070573392), // VSHLiv4i32 3459 UINT64_C(4069524816), // VSHLiv8i16 3460 UINT64_C(4069000464), // VSHLiv8i8 3461 UINT64_C(4060087360), // VSHLsv16i8 3462 UINT64_C(4063233024), // VSHLsv1i64 3463 UINT64_C(4062184448), // VSHLsv2i32 3464 UINT64_C(4063233088), // VSHLsv2i64 3465 UINT64_C(4061135872), // VSHLsv4i16 3466 UINT64_C(4062184512), // VSHLsv4i32 3467 UINT64_C(4061135936), // VSHLsv8i16 3468 UINT64_C(4060087296), // VSHLsv8i8 3469 UINT64_C(4076864576), // VSHLuv16i8 3470 UINT64_C(4080010240), // VSHLuv1i64 3471 UINT64_C(4078961664), // VSHLuv2i32 3472 UINT64_C(4080010304), // VSHLuv2i64 3473 UINT64_C(4077913088), // VSHLuv4i16 3474 UINT64_C(4078961728), // VSHLuv4i32 3475 UINT64_C(4077913152), // VSHLuv8i16 3476 UINT64_C(4076864512), // VSHLuv8i8 3477 UINT64_C(4070574096), // VSHRNv2i32 3478 UINT64_C(4069525520), // VSHRNv4i16 3479 UINT64_C(4069001232), // VSHRNv8i8 3480 UINT64_C(4068999248), // VSHRsv16i8 3481 UINT64_C(4068475024), // VSHRsv1i64 3482 UINT64_C(4070572048), // VSHRsv2i32 3483 UINT64_C(4068475088), // VSHRsv2i64 3484 UINT64_C(4069523472), // VSHRsv4i16 3485 UINT64_C(4070572112), // VSHRsv4i32 3486 UINT64_C(4069523536), // VSHRsv8i16 3487 UINT64_C(4068999184), // VSHRsv8i8 3488 UINT64_C(4085776464), // VSHRuv16i8 3489 UINT64_C(4085252240), // VSHRuv1i64 3490 UINT64_C(4087349264), // VSHRuv2i32 3491 UINT64_C(4085252304), // VSHRuv2i64 3492 UINT64_C(4086300688), // VSHRuv4i16 3493 UINT64_C(4087349328), // VSHRuv4i32 3494 UINT64_C(4086300752), // VSHRuv8i16 3495 UINT64_C(4085776400), // VSHRuv8i8 3496 UINT64_C(247073600), // VSHTOD 3497 UINT64_C(247073088), // VSHTOH 3498 UINT64_C(247073344), // VSHTOS 3499 UINT64_C(246942656), // VSITOD 3500 UINT64_C(246942144), // VSITOH 3501 UINT64_C(246942400), // VSITOS 3502 UINT64_C(4085777744), // VSLIv16i8 3503 UINT64_C(4085253520), // VSLIv1i64 3504 UINT64_C(4087350544), // VSLIv2i32 3505 UINT64_C(4085253584), // VSLIv2i64 3506 UINT64_C(4086301968), // VSLIv4i16 3507 UINT64_C(4087350608), // VSLIv4i32 3508 UINT64_C(4086302032), // VSLIv8i16 3509 UINT64_C(4085777680), // VSLIv8i8 3510 UINT64_C(247073728), // VSLTOD 3511 UINT64_C(247073216), // VSLTOH 3512 UINT64_C(247073472), // VSLTOS 3513 UINT64_C(4229958720), // VSMMLA 3514 UINT64_C(246483904), // VSQRTD 3515 UINT64_C(246483392), // VSQRTH 3516 UINT64_C(246483648), // VSQRTS 3517 UINT64_C(4068999504), // VSRAsv16i8 3518 UINT64_C(4068475280), // VSRAsv1i64 3519 UINT64_C(4070572304), // VSRAsv2i32 3520 UINT64_C(4068475344), // VSRAsv2i64 3521 UINT64_C(4069523728), // VSRAsv4i16 3522 UINT64_C(4070572368), // VSRAsv4i32 3523 UINT64_C(4069523792), // VSRAsv8i16 3524 UINT64_C(4068999440), // VSRAsv8i8 3525 UINT64_C(4085776720), // VSRAuv16i8 3526 UINT64_C(4085252496), // VSRAuv1i64 3527 UINT64_C(4087349520), // VSRAuv2i32 3528 UINT64_C(4085252560), // VSRAuv2i64 3529 UINT64_C(4086300944), // VSRAuv4i16 3530 UINT64_C(4087349584), // VSRAuv4i32 3531 UINT64_C(4086301008), // VSRAuv8i16 3532 UINT64_C(4085776656), // VSRAuv8i8 3533 UINT64_C(4085777488), // VSRIv16i8 3534 UINT64_C(4085253264), // VSRIv1i64 3535 UINT64_C(4087350288), // VSRIv2i32 3536 UINT64_C(4085253328), // VSRIv2i64 3537 UINT64_C(4086301712), // VSRIv4i16 3538 UINT64_C(4087350352), // VSRIv4i32 3539 UINT64_C(4086301776), // VSRIv8i16 3540 UINT64_C(4085777424), // VSRIv8i8 3541 UINT64_C(4102030351), // VST1LNd16 3542 UINT64_C(4102030336), // VST1LNd16_UPD 3543 UINT64_C(4102031375), // VST1LNd32 3544 UINT64_C(4102031360), // VST1LNd32_UPD 3545 UINT64_C(4102029327), // VST1LNd8 3546 UINT64_C(4102029312), // VST1LNd8_UPD 3547 UINT64_C(0), // VST1LNq16Pseudo 3548 UINT64_C(0), // VST1LNq16Pseudo_UPD 3549 UINT64_C(0), // VST1LNq32Pseudo 3550 UINT64_C(0), // VST1LNq32Pseudo_UPD 3551 UINT64_C(0), // VST1LNq8Pseudo 3552 UINT64_C(0), // VST1LNq8Pseudo_UPD 3553 UINT64_C(4093642575), // VST1d16 3554 UINT64_C(4093641295), // VST1d16Q 3555 UINT64_C(0), // VST1d16QPseudo 3556 UINT64_C(0), // VST1d16QPseudoWB_fixed 3557 UINT64_C(0), // VST1d16QPseudoWB_register 3558 UINT64_C(4093641293), // VST1d16Qwb_fixed 3559 UINT64_C(4093641280), // VST1d16Qwb_register 3560 UINT64_C(4093642319), // VST1d16T 3561 UINT64_C(0), // VST1d16TPseudo 3562 UINT64_C(0), // VST1d16TPseudoWB_fixed 3563 UINT64_C(0), // VST1d16TPseudoWB_register 3564 UINT64_C(4093642317), // VST1d16Twb_fixed 3565 UINT64_C(4093642304), // VST1d16Twb_register 3566 UINT64_C(4093642573), // VST1d16wb_fixed 3567 UINT64_C(4093642560), // VST1d16wb_register 3568 UINT64_C(4093642639), // VST1d32 3569 UINT64_C(4093641359), // VST1d32Q 3570 UINT64_C(0), // VST1d32QPseudo 3571 UINT64_C(0), // VST1d32QPseudoWB_fixed 3572 UINT64_C(0), // VST1d32QPseudoWB_register 3573 UINT64_C(4093641357), // VST1d32Qwb_fixed 3574 UINT64_C(4093641344), // VST1d32Qwb_register 3575 UINT64_C(4093642383), // VST1d32T 3576 UINT64_C(0), // VST1d32TPseudo 3577 UINT64_C(0), // VST1d32TPseudoWB_fixed 3578 UINT64_C(0), // VST1d32TPseudoWB_register 3579 UINT64_C(4093642381), // VST1d32Twb_fixed 3580 UINT64_C(4093642368), // VST1d32Twb_register 3581 UINT64_C(4093642637), // VST1d32wb_fixed 3582 UINT64_C(4093642624), // VST1d32wb_register 3583 UINT64_C(4093642703), // VST1d64 3584 UINT64_C(4093641423), // VST1d64Q 3585 UINT64_C(0), // VST1d64QPseudo 3586 UINT64_C(0), // VST1d64QPseudoWB_fixed 3587 UINT64_C(0), // VST1d64QPseudoWB_register 3588 UINT64_C(4093641421), // VST1d64Qwb_fixed 3589 UINT64_C(4093641408), // VST1d64Qwb_register 3590 UINT64_C(4093642447), // VST1d64T 3591 UINT64_C(0), // VST1d64TPseudo 3592 UINT64_C(0), // VST1d64TPseudoWB_fixed 3593 UINT64_C(0), // VST1d64TPseudoWB_register 3594 UINT64_C(4093642445), // VST1d64Twb_fixed 3595 UINT64_C(4093642432), // VST1d64Twb_register 3596 UINT64_C(4093642701), // VST1d64wb_fixed 3597 UINT64_C(4093642688), // VST1d64wb_register 3598 UINT64_C(4093642511), // VST1d8 3599 UINT64_C(4093641231), // VST1d8Q 3600 UINT64_C(0), // VST1d8QPseudo 3601 UINT64_C(0), // VST1d8QPseudoWB_fixed 3602 UINT64_C(0), // VST1d8QPseudoWB_register 3603 UINT64_C(4093641229), // VST1d8Qwb_fixed 3604 UINT64_C(4093641216), // VST1d8Qwb_register 3605 UINT64_C(4093642255), // VST1d8T 3606 UINT64_C(0), // VST1d8TPseudo 3607 UINT64_C(0), // VST1d8TPseudoWB_fixed 3608 UINT64_C(0), // VST1d8TPseudoWB_register 3609 UINT64_C(4093642253), // VST1d8Twb_fixed 3610 UINT64_C(4093642240), // VST1d8Twb_register 3611 UINT64_C(4093642509), // VST1d8wb_fixed 3612 UINT64_C(4093642496), // VST1d8wb_register 3613 UINT64_C(4093643343), // VST1q16 3614 UINT64_C(0), // VST1q16HighQPseudo 3615 UINT64_C(0), // VST1q16HighQPseudo_UPD 3616 UINT64_C(0), // VST1q16HighTPseudo 3617 UINT64_C(0), // VST1q16HighTPseudo_UPD 3618 UINT64_C(0), // VST1q16LowQPseudo_UPD 3619 UINT64_C(0), // VST1q16LowTPseudo_UPD 3620 UINT64_C(4093643341), // VST1q16wb_fixed 3621 UINT64_C(4093643328), // VST1q16wb_register 3622 UINT64_C(4093643407), // VST1q32 3623 UINT64_C(0), // VST1q32HighQPseudo 3624 UINT64_C(0), // VST1q32HighQPseudo_UPD 3625 UINT64_C(0), // VST1q32HighTPseudo 3626 UINT64_C(0), // VST1q32HighTPseudo_UPD 3627 UINT64_C(0), // VST1q32LowQPseudo_UPD 3628 UINT64_C(0), // VST1q32LowTPseudo_UPD 3629 UINT64_C(4093643405), // VST1q32wb_fixed 3630 UINT64_C(4093643392), // VST1q32wb_register 3631 UINT64_C(4093643471), // VST1q64 3632 UINT64_C(0), // VST1q64HighQPseudo 3633 UINT64_C(0), // VST1q64HighQPseudo_UPD 3634 UINT64_C(0), // VST1q64HighTPseudo 3635 UINT64_C(0), // VST1q64HighTPseudo_UPD 3636 UINT64_C(0), // VST1q64LowQPseudo_UPD 3637 UINT64_C(0), // VST1q64LowTPseudo_UPD 3638 UINT64_C(4093643469), // VST1q64wb_fixed 3639 UINT64_C(4093643456), // VST1q64wb_register 3640 UINT64_C(4093643279), // VST1q8 3641 UINT64_C(0), // VST1q8HighQPseudo 3642 UINT64_C(0), // VST1q8HighQPseudo_UPD 3643 UINT64_C(0), // VST1q8HighTPseudo 3644 UINT64_C(0), // VST1q8HighTPseudo_UPD 3645 UINT64_C(0), // VST1q8LowQPseudo_UPD 3646 UINT64_C(0), // VST1q8LowTPseudo_UPD 3647 UINT64_C(4093643277), // VST1q8wb_fixed 3648 UINT64_C(4093643264), // VST1q8wb_register 3649 UINT64_C(4102030607), // VST2LNd16 3650 UINT64_C(0), // VST2LNd16Pseudo 3651 UINT64_C(0), // VST2LNd16Pseudo_UPD 3652 UINT64_C(4102030592), // VST2LNd16_UPD 3653 UINT64_C(4102031631), // VST2LNd32 3654 UINT64_C(0), // VST2LNd32Pseudo 3655 UINT64_C(0), // VST2LNd32Pseudo_UPD 3656 UINT64_C(4102031616), // VST2LNd32_UPD 3657 UINT64_C(4102029583), // VST2LNd8 3658 UINT64_C(0), // VST2LNd8Pseudo 3659 UINT64_C(0), // VST2LNd8Pseudo_UPD 3660 UINT64_C(4102029568), // VST2LNd8_UPD 3661 UINT64_C(4102030639), // VST2LNq16 3662 UINT64_C(0), // VST2LNq16Pseudo 3663 UINT64_C(0), // VST2LNq16Pseudo_UPD 3664 UINT64_C(4102030624), // VST2LNq16_UPD 3665 UINT64_C(4102031695), // VST2LNq32 3666 UINT64_C(0), // VST2LNq32Pseudo 3667 UINT64_C(0), // VST2LNq32Pseudo_UPD 3668 UINT64_C(4102031680), // VST2LNq32_UPD 3669 UINT64_C(4093643087), // VST2b16 3670 UINT64_C(4093643085), // VST2b16wb_fixed 3671 UINT64_C(4093643072), // VST2b16wb_register 3672 UINT64_C(4093643151), // VST2b32 3673 UINT64_C(4093643149), // VST2b32wb_fixed 3674 UINT64_C(4093643136), // VST2b32wb_register 3675 UINT64_C(4093643023), // VST2b8 3676 UINT64_C(4093643021), // VST2b8wb_fixed 3677 UINT64_C(4093643008), // VST2b8wb_register 3678 UINT64_C(4093642831), // VST2d16 3679 UINT64_C(4093642829), // VST2d16wb_fixed 3680 UINT64_C(4093642816), // VST2d16wb_register 3681 UINT64_C(4093642895), // VST2d32 3682 UINT64_C(4093642893), // VST2d32wb_fixed 3683 UINT64_C(4093642880), // VST2d32wb_register 3684 UINT64_C(4093642767), // VST2d8 3685 UINT64_C(4093642765), // VST2d8wb_fixed 3686 UINT64_C(4093642752), // VST2d8wb_register 3687 UINT64_C(4093641551), // VST2q16 3688 UINT64_C(0), // VST2q16Pseudo 3689 UINT64_C(0), // VST2q16PseudoWB_fixed 3690 UINT64_C(0), // VST2q16PseudoWB_register 3691 UINT64_C(4093641549), // VST2q16wb_fixed 3692 UINT64_C(4093641536), // VST2q16wb_register 3693 UINT64_C(4093641615), // VST2q32 3694 UINT64_C(0), // VST2q32Pseudo 3695 UINT64_C(0), // VST2q32PseudoWB_fixed 3696 UINT64_C(0), // VST2q32PseudoWB_register 3697 UINT64_C(4093641613), // VST2q32wb_fixed 3698 UINT64_C(4093641600), // VST2q32wb_register 3699 UINT64_C(4093641487), // VST2q8 3700 UINT64_C(0), // VST2q8Pseudo 3701 UINT64_C(0), // VST2q8PseudoWB_fixed 3702 UINT64_C(0), // VST2q8PseudoWB_register 3703 UINT64_C(4093641485), // VST2q8wb_fixed 3704 UINT64_C(4093641472), // VST2q8wb_register 3705 UINT64_C(4102030863), // VST3LNd16 3706 UINT64_C(0), // VST3LNd16Pseudo 3707 UINT64_C(0), // VST3LNd16Pseudo_UPD 3708 UINT64_C(4102030848), // VST3LNd16_UPD 3709 UINT64_C(4102031887), // VST3LNd32 3710 UINT64_C(0), // VST3LNd32Pseudo 3711 UINT64_C(0), // VST3LNd32Pseudo_UPD 3712 UINT64_C(4102031872), // VST3LNd32_UPD 3713 UINT64_C(4102029839), // VST3LNd8 3714 UINT64_C(0), // VST3LNd8Pseudo 3715 UINT64_C(0), // VST3LNd8Pseudo_UPD 3716 UINT64_C(4102029824), // VST3LNd8_UPD 3717 UINT64_C(4102030895), // VST3LNq16 3718 UINT64_C(0), // VST3LNq16Pseudo 3719 UINT64_C(0), // VST3LNq16Pseudo_UPD 3720 UINT64_C(4102030880), // VST3LNq16_UPD 3721 UINT64_C(4102031951), // VST3LNq32 3722 UINT64_C(0), // VST3LNq32Pseudo 3723 UINT64_C(0), // VST3LNq32Pseudo_UPD 3724 UINT64_C(4102031936), // VST3LNq32_UPD 3725 UINT64_C(4093641807), // VST3d16 3726 UINT64_C(0), // VST3d16Pseudo 3727 UINT64_C(0), // VST3d16Pseudo_UPD 3728 UINT64_C(4093641792), // VST3d16_UPD 3729 UINT64_C(4093641871), // VST3d32 3730 UINT64_C(0), // VST3d32Pseudo 3731 UINT64_C(0), // VST3d32Pseudo_UPD 3732 UINT64_C(4093641856), // VST3d32_UPD 3733 UINT64_C(4093641743), // VST3d8 3734 UINT64_C(0), // VST3d8Pseudo 3735 UINT64_C(0), // VST3d8Pseudo_UPD 3736 UINT64_C(4093641728), // VST3d8_UPD 3737 UINT64_C(4093642063), // VST3q16 3738 UINT64_C(0), // VST3q16Pseudo_UPD 3739 UINT64_C(4093642048), // VST3q16_UPD 3740 UINT64_C(0), // VST3q16oddPseudo 3741 UINT64_C(0), // VST3q16oddPseudo_UPD 3742 UINT64_C(4093642127), // VST3q32 3743 UINT64_C(0), // VST3q32Pseudo_UPD 3744 UINT64_C(4093642112), // VST3q32_UPD 3745 UINT64_C(0), // VST3q32oddPseudo 3746 UINT64_C(0), // VST3q32oddPseudo_UPD 3747 UINT64_C(4093641999), // VST3q8 3748 UINT64_C(0), // VST3q8Pseudo_UPD 3749 UINT64_C(4093641984), // VST3q8_UPD 3750 UINT64_C(0), // VST3q8oddPseudo 3751 UINT64_C(0), // VST3q8oddPseudo_UPD 3752 UINT64_C(4102031119), // VST4LNd16 3753 UINT64_C(0), // VST4LNd16Pseudo 3754 UINT64_C(0), // VST4LNd16Pseudo_UPD 3755 UINT64_C(4102031104), // VST4LNd16_UPD 3756 UINT64_C(4102032143), // VST4LNd32 3757 UINT64_C(0), // VST4LNd32Pseudo 3758 UINT64_C(0), // VST4LNd32Pseudo_UPD 3759 UINT64_C(4102032128), // VST4LNd32_UPD 3760 UINT64_C(4102030095), // VST4LNd8 3761 UINT64_C(0), // VST4LNd8Pseudo 3762 UINT64_C(0), // VST4LNd8Pseudo_UPD 3763 UINT64_C(4102030080), // VST4LNd8_UPD 3764 UINT64_C(4102031151), // VST4LNq16 3765 UINT64_C(0), // VST4LNq16Pseudo 3766 UINT64_C(0), // VST4LNq16Pseudo_UPD 3767 UINT64_C(4102031136), // VST4LNq16_UPD 3768 UINT64_C(4102032207), // VST4LNq32 3769 UINT64_C(0), // VST4LNq32Pseudo 3770 UINT64_C(0), // VST4LNq32Pseudo_UPD 3771 UINT64_C(4102032192), // VST4LNq32_UPD 3772 UINT64_C(4093640783), // VST4d16 3773 UINT64_C(0), // VST4d16Pseudo 3774 UINT64_C(0), // VST4d16Pseudo_UPD 3775 UINT64_C(4093640768), // VST4d16_UPD 3776 UINT64_C(4093640847), // VST4d32 3777 UINT64_C(0), // VST4d32Pseudo 3778 UINT64_C(0), // VST4d32Pseudo_UPD 3779 UINT64_C(4093640832), // VST4d32_UPD 3780 UINT64_C(4093640719), // VST4d8 3781 UINT64_C(0), // VST4d8Pseudo 3782 UINT64_C(0), // VST4d8Pseudo_UPD 3783 UINT64_C(4093640704), // VST4d8_UPD 3784 UINT64_C(4093641039), // VST4q16 3785 UINT64_C(0), // VST4q16Pseudo_UPD 3786 UINT64_C(4093641024), // VST4q16_UPD 3787 UINT64_C(0), // VST4q16oddPseudo 3788 UINT64_C(0), // VST4q16oddPseudo_UPD 3789 UINT64_C(4093641103), // VST4q32 3790 UINT64_C(0), // VST4q32Pseudo_UPD 3791 UINT64_C(4093641088), // VST4q32_UPD 3792 UINT64_C(0), // VST4q32oddPseudo 3793 UINT64_C(0), // VST4q32oddPseudo_UPD 3794 UINT64_C(4093640975), // VST4q8 3795 UINT64_C(0), // VST4q8Pseudo_UPD 3796 UINT64_C(4093640960), // VST4q8_UPD 3797 UINT64_C(0), // VST4q8oddPseudo 3798 UINT64_C(0), // VST4q8oddPseudo_UPD 3799 UINT64_C(220203776), // VSTMDDB_UPD 3800 UINT64_C(209718016), // VSTMDIA 3801 UINT64_C(211815168), // VSTMDIA_UPD 3802 UINT64_C(0), // VSTMQIA 3803 UINT64_C(220203520), // VSTMSDB_UPD 3804 UINT64_C(209717760), // VSTMSIA 3805 UINT64_C(211814912), // VSTMSIA_UPD 3806 UINT64_C(218106624), // VSTRD 3807 UINT64_C(218106112), // VSTRH 3808 UINT64_C(218106368), // VSTRS 3809 UINT64_C(222351232), // VSTR_FPCXTNS_off 3810 UINT64_C(207671168), // VSTR_FPCXTNS_post 3811 UINT64_C(224448384), // VSTR_FPCXTNS_pre 3812 UINT64_C(222359424), // VSTR_FPCXTS_off 3813 UINT64_C(207679360), // VSTR_FPCXTS_post 3814 UINT64_C(224456576), // VSTR_FPCXTS_pre 3815 UINT64_C(218124160), // VSTR_FPSCR_NZCVQC_off 3816 UINT64_C(203444096), // VSTR_FPSCR_NZCVQC_post 3817 UINT64_C(220221312), // VSTR_FPSCR_NZCVQC_pre 3818 UINT64_C(218115968), // VSTR_FPSCR_off 3819 UINT64_C(203435904), // VSTR_FPSCR_post 3820 UINT64_C(220213120), // VSTR_FPSCR_pre 3821 UINT64_C(222343040), // VSTR_P0_off 3822 UINT64_C(207662976), // VSTR_P0_post 3823 UINT64_C(224440192), // VSTR_P0_pre 3824 UINT64_C(222334848), // VSTR_VPR_off 3825 UINT64_C(207654784), // VSTR_VPR_post 3826 UINT64_C(224432000), // VSTR_VPR_pre 3827 UINT64_C(238029632), // VSUBD 3828 UINT64_C(238029120), // VSUBH 3829 UINT64_C(4070573568), // VSUBHNv2i32 3830 UINT64_C(4069524992), // VSUBHNv4i16 3831 UINT64_C(4068476416), // VSUBHNv8i8 3832 UINT64_C(4070572544), // VSUBLsv2i64 3833 UINT64_C(4069523968), // VSUBLsv4i32 3834 UINT64_C(4068475392), // VSUBLsv8i16 3835 UINT64_C(4087349760), // VSUBLuv2i64 3836 UINT64_C(4086301184), // VSUBLuv4i32 3837 UINT64_C(4085252608), // VSUBLuv8i16 3838 UINT64_C(238029376), // VSUBS 3839 UINT64_C(4070572800), // VSUBWsv2i64 3840 UINT64_C(4069524224), // VSUBWsv4i32 3841 UINT64_C(4068475648), // VSUBWsv8i16 3842 UINT64_C(4087350016), // VSUBWuv2i64 3843 UINT64_C(4086301440), // VSUBWuv4i32 3844 UINT64_C(4085252864), // VSUBWuv8i16 3845 UINT64_C(4062186752), // VSUBfd 3846 UINT64_C(4062186816), // VSUBfq 3847 UINT64_C(4063235328), // VSUBhd 3848 UINT64_C(4063235392), // VSUBhq 3849 UINT64_C(4076865600), // VSUBv16i8 3850 UINT64_C(4080011264), // VSUBv1i64 3851 UINT64_C(4078962688), // VSUBv2i32 3852 UINT64_C(4080011328), // VSUBv2i64 3853 UINT64_C(4077914112), // VSUBv4i16 3854 UINT64_C(4078962752), // VSUBv4i32 3855 UINT64_C(4077914176), // VSUBv8i16 3856 UINT64_C(4076865536), // VSUBv8i8 3857 UINT64_C(4269804816), // VSUDOTDI 3858 UINT64_C(4269804880), // VSUDOTQI 3859 UINT64_C(4088528896), // VSWPd 3860 UINT64_C(4088528960), // VSWPq 3861 UINT64_C(4088399872), // VTBL1 3862 UINT64_C(4088400128), // VTBL2 3863 UINT64_C(4088400384), // VTBL3 3864 UINT64_C(0), // VTBL3Pseudo 3865 UINT64_C(4088400640), // VTBL4 3866 UINT64_C(0), // VTBL4Pseudo 3867 UINT64_C(4088399936), // VTBX1 3868 UINT64_C(4088400192), // VTBX2 3869 UINT64_C(4088400448), // VTBX3 3870 UINT64_C(0), // VTBX3Pseudo 3871 UINT64_C(4088400704), // VTBX4 3872 UINT64_C(0), // VTBX4Pseudo 3873 UINT64_C(247335744), // VTOSHD 3874 UINT64_C(247335232), // VTOSHH 3875 UINT64_C(247335488), // VTOSHS 3876 UINT64_C(247270208), // VTOSIRD 3877 UINT64_C(247269696), // VTOSIRH 3878 UINT64_C(247269952), // VTOSIRS 3879 UINT64_C(247270336), // VTOSIZD 3880 UINT64_C(247269824), // VTOSIZH 3881 UINT64_C(247270080), // VTOSIZS 3882 UINT64_C(247335872), // VTOSLD 3883 UINT64_C(247335360), // VTOSLH 3884 UINT64_C(247335616), // VTOSLS 3885 UINT64_C(247401280), // VTOUHD 3886 UINT64_C(247400768), // VTOUHH 3887 UINT64_C(247401024), // VTOUHS 3888 UINT64_C(247204672), // VTOUIRD 3889 UINT64_C(247204160), // VTOUIRH 3890 UINT64_C(247204416), // VTOUIRS 3891 UINT64_C(247204800), // VTOUIZD 3892 UINT64_C(247204288), // VTOUIZH 3893 UINT64_C(247204544), // VTOUIZS 3894 UINT64_C(247401408), // VTOULD 3895 UINT64_C(247400896), // VTOULH 3896 UINT64_C(247401152), // VTOULS 3897 UINT64_C(4088791168), // VTRNd16 3898 UINT64_C(4089053312), // VTRNd32 3899 UINT64_C(4088529024), // VTRNd8 3900 UINT64_C(4088791232), // VTRNq16 3901 UINT64_C(4089053376), // VTRNq32 3902 UINT64_C(4088529088), // VTRNq8 3903 UINT64_C(4060088400), // VTSTv16i8 3904 UINT64_C(4062185488), // VTSTv2i32 3905 UINT64_C(4061136912), // VTSTv4i16 3906 UINT64_C(4062185552), // VTSTv4i32 3907 UINT64_C(4061136976), // VTSTv8i16 3908 UINT64_C(4060088336), // VTSTv8i8 3909 UINT64_C(4229958928), // VUDOTD 3910 UINT64_C(4263513360), // VUDOTDI 3911 UINT64_C(4229958992), // VUDOTQ 3912 UINT64_C(4263513424), // VUDOTQI 3913 UINT64_C(247139136), // VUHTOD 3914 UINT64_C(247138624), // VUHTOH 3915 UINT64_C(247138880), // VUHTOS 3916 UINT64_C(246942528), // VUITOD 3917 UINT64_C(246942016), // VUITOH 3918 UINT64_C(246942272), // VUITOS 3919 UINT64_C(247139264), // VULTOD 3920 UINT64_C(247138752), // VULTOH 3921 UINT64_C(247139008), // VULTOS 3922 UINT64_C(4229958736), // VUMMLA 3923 UINT64_C(4238347520), // VUSDOTD 3924 UINT64_C(4269804800), // VUSDOTDI 3925 UINT64_C(4238347584), // VUSDOTQ 3926 UINT64_C(4269804864), // VUSDOTQI 3927 UINT64_C(4238347328), // VUSMMLA 3928 UINT64_C(4088791296), // VUZPd16 3929 UINT64_C(4088529152), // VUZPd8 3930 UINT64_C(4088791360), // VUZPq16 3931 UINT64_C(4089053504), // VUZPq32 3932 UINT64_C(4088529216), // VUZPq8 3933 UINT64_C(4088791424), // VZIPd16 3934 UINT64_C(4088529280), // VZIPd8 3935 UINT64_C(4088791488), // VZIPq16 3936 UINT64_C(4089053632), // VZIPq32 3937 UINT64_C(4088529344), // VZIPq8 3938 UINT64_C(139460608), // sysLDMDA 3939 UINT64_C(141557760), // sysLDMDA_UPD 3940 UINT64_C(156237824), // sysLDMDB 3941 UINT64_C(158334976), // sysLDMDB_UPD 3942 UINT64_C(147849216), // sysLDMIA 3943 UINT64_C(149946368), // sysLDMIA_UPD 3944 UINT64_C(164626432), // sysLDMIB 3945 UINT64_C(166723584), // sysLDMIB_UPD 3946 UINT64_C(138412032), // sysSTMDA 3947 UINT64_C(140509184), // sysSTMDA_UPD 3948 UINT64_C(155189248), // sysSTMDB 3949 UINT64_C(157286400), // sysSTMDB_UPD 3950 UINT64_C(146800640), // sysSTMIA 3951 UINT64_C(148897792), // sysSTMIA_UPD 3952 UINT64_C(163577856), // sysSTMIB 3953 UINT64_C(165675008), // sysSTMIB_UPD 3954 UINT64_C(4047503360), // t2ADCri 3955 UINT64_C(3946840064), // t2ADCrr 3956 UINT64_C(3946840064), // t2ADCrs 3957 UINT64_C(4043309056), // t2ADDri 3958 UINT64_C(4060086272), // t2ADDri12 3959 UINT64_C(3942645760), // t2ADDrr 3960 UINT64_C(3942645760), // t2ADDrs 3961 UINT64_C(4044164352), // t2ADDspImm 3962 UINT64_C(4060941568), // t2ADDspImm12 3963 UINT64_C(4061069312), // t2ADR 3964 UINT64_C(4026531840), // t2ANDri 3965 UINT64_C(3925868544), // t2ANDrr 3966 UINT64_C(3925868544), // t2ANDrs 3967 UINT64_C(3931045920), // t2ASRri 3968 UINT64_C(4198559744), // t2ASRrr 3969 UINT64_C(4088365101), // t2AUT 3970 UINT64_C(4216327936), // t2AUTG 3971 UINT64_C(4026568704), // t2B 3972 UINT64_C(4084137984), // t2BFC 3973 UINT64_C(4083154944), // t2BFI 3974 UINT64_C(4026580993), // t2BFLi 3975 UINT64_C(4033929217), // t2BFLr 3976 UINT64_C(4030783489), // t2BFi 3977 UINT64_C(4026589185), // t2BFic 3978 UINT64_C(4032880641), // t2BFr 3979 UINT64_C(4028628992), // t2BICri 3980 UINT64_C(3927965696), // t2BICrr 3981 UINT64_C(3927965696), // t2BICrs 3982 UINT64_C(4088365071), // t2BTI 3983 UINT64_C(4216327952), // t2BXAUT 3984 UINT64_C(4089483008), // t2BXJ 3985 UINT64_C(4026564608), // t2Bcc 3986 UINT64_C(3992977408), // t2CDP 3987 UINT64_C(4261412864), // t2CDP2 3988 UINT64_C(4089417519), // t2CLREX 3989 UINT64_C(3902734336), // t2CLRM 3990 UINT64_C(4205899904), // t2CLZ 3991 UINT64_C(4044361472), // t2CMNri 3992 UINT64_C(3943698176), // t2CMNzrr 3993 UINT64_C(3943698176), // t2CMNzrs 3994 UINT64_C(4054847232), // t2CMPri 3995 UINT64_C(3954183936), // t2CMPrr 3996 UINT64_C(3954183936), // t2CMPrs 3997 UINT64_C(4088365312), // t2CPS1p 3998 UINT64_C(4088365056), // t2CPS2p 3999 UINT64_C(4088365312), // t2CPS3p 4000 UINT64_C(4206948480), // t2CRC32B 4001 UINT64_C(4207997056), // t2CRC32CB 4002 UINT64_C(4207997072), // t2CRC32CH 4003 UINT64_C(4207997088), // t2CRC32CW 4004 UINT64_C(4206948496), // t2CRC32H 4005 UINT64_C(4206948512), // t2CRC32W 4006 UINT64_C(3931144192), // t2CSEL 4007 UINT64_C(3931148288), // t2CSINC 4008 UINT64_C(3931152384), // t2CSINV 4009 UINT64_C(3931156480), // t2CSNEG 4010 UINT64_C(4088365296), // t2DBG 4011 UINT64_C(4153376769), // t2DCPS1 4012 UINT64_C(4153376770), // t2DCPS2 4013 UINT64_C(4153376771), // t2DCPS3 4014 UINT64_C(4030783489), // t2DLS 4015 UINT64_C(4089417552), // t2DMB 4016 UINT64_C(4089417536), // t2DSB 4017 UINT64_C(4034920448), // t2EORri 4018 UINT64_C(3934257152), // t2EORrr 4019 UINT64_C(3934257152), // t2EORrs 4020 UINT64_C(4088365056), // t2HINT 4021 UINT64_C(4158685184), // t2HVC 4022 UINT64_C(4089417568), // t2ISB 4023 UINT64_C(48896), // t2IT 4024 UINT64_C(0), // t2Int_eh_sjlj_setjmp 4025 UINT64_C(0), // t2Int_eh_sjlj_setjmp_nofp 4026 UINT64_C(3905949615), // t2LDA 4027 UINT64_C(3905949583), // t2LDAB 4028 UINT64_C(3905949679), // t2LDAEX 4029 UINT64_C(3905949647), // t2LDAEXB 4030 UINT64_C(3905945855), // t2LDAEXD 4031 UINT64_C(3905949663), // t2LDAEXH 4032 UINT64_C(3905949599), // t2LDAH 4033 UINT64_C(4249878528), // t2LDC2L_OFFSET 4034 UINT64_C(4241489920), // t2LDC2L_OPTION 4035 UINT64_C(4235198464), // t2LDC2L_POST 4036 UINT64_C(4251975680), // t2LDC2L_PRE 4037 UINT64_C(4245684224), // t2LDC2_OFFSET 4038 UINT64_C(4237295616), // t2LDC2_OPTION 4039 UINT64_C(4231004160), // t2LDC2_POST 4040 UINT64_C(4247781376), // t2LDC2_PRE 4041 UINT64_C(3981443072), // t2LDCL_OFFSET 4042 UINT64_C(3973054464), // t2LDCL_OPTION 4043 UINT64_C(3966763008), // t2LDCL_POST 4044 UINT64_C(3983540224), // t2LDCL_PRE 4045 UINT64_C(3977248768), // t2LDC_OFFSET 4046 UINT64_C(3968860160), // t2LDC_OPTION 4047 UINT64_C(3962568704), // t2LDC_POST 4048 UINT64_C(3979345920), // t2LDC_PRE 4049 UINT64_C(3910139904), // t2LDMDB 4050 UINT64_C(3912237056), // t2LDMDB_UPD 4051 UINT64_C(3901751296), // t2LDMIA 4052 UINT64_C(3903848448), // t2LDMIA_UPD 4053 UINT64_C(4161801728), // t2LDRBT 4054 UINT64_C(4161800448), // t2LDRB_POST 4055 UINT64_C(4161801472), // t2LDRB_PRE 4056 UINT64_C(4170186752), // t2LDRBi12 4057 UINT64_C(4161801216), // t2LDRBi8 4058 UINT64_C(4162781184), // t2LDRBpci 4059 UINT64_C(4161798144), // t2LDRBs 4060 UINT64_C(3899654144), // t2LDRD_POST 4061 UINT64_C(3916431360), // t2LDRD_PRE 4062 UINT64_C(3914334208), // t2LDRDi8 4063 UINT64_C(3897560832), // t2LDREX 4064 UINT64_C(3905949519), // t2LDREXB 4065 UINT64_C(3905945727), // t2LDREXD 4066 UINT64_C(3905949535), // t2LDREXH 4067 UINT64_C(4163898880), // t2LDRHT 4068 UINT64_C(4163897600), // t2LDRH_POST 4069 UINT64_C(4163898624), // t2LDRH_PRE 4070 UINT64_C(4172283904), // t2LDRHi12 4071 UINT64_C(4163898368), // t2LDRHi8 4072 UINT64_C(4164878336), // t2LDRHpci 4073 UINT64_C(4163895296), // t2LDRHs 4074 UINT64_C(4178578944), // t2LDRSBT 4075 UINT64_C(4178577664), // t2LDRSB_POST 4076 UINT64_C(4178578688), // t2LDRSB_PRE 4077 UINT64_C(4186963968), // t2LDRSBi12 4078 UINT64_C(4178578432), // t2LDRSBi8 4079 UINT64_C(4179558400), // t2LDRSBpci 4080 UINT64_C(4178575360), // t2LDRSBs 4081 UINT64_C(4180676096), // t2LDRSHT 4082 UINT64_C(4180674816), // t2LDRSH_POST 4083 UINT64_C(4180675840), // t2LDRSH_PRE 4084 UINT64_C(4189061120), // t2LDRSHi12 4085 UINT64_C(4180675584), // t2LDRSHi8 4086 UINT64_C(4181655552), // t2LDRSHpci 4087 UINT64_C(4180672512), // t2LDRSHs 4088 UINT64_C(4165996032), // t2LDRT 4089 UINT64_C(4165994752), // t2LDR_POST 4090 UINT64_C(4165995776), // t2LDR_PRE 4091 UINT64_C(4174381056), // t2LDRi12 4092 UINT64_C(4165995520), // t2LDRi8 4093 UINT64_C(4166975488), // t2LDRpci 4094 UINT64_C(4165992448), // t2LDRs 4095 UINT64_C(4029661185), // t2LE 4096 UINT64_C(4027564033), // t2LEUpdate 4097 UINT64_C(3931045888), // t2LSLri 4098 UINT64_C(4194365440), // t2LSLrr 4099 UINT64_C(3931045904), // t2LSRri 4100 UINT64_C(4196462592), // t2LSRrr 4101 UINT64_C(3992977424), // t2MCR 4102 UINT64_C(4261412880), // t2MCR2 4103 UINT64_C(3963617280), // t2MCRR 4104 UINT64_C(4232052736), // t2MCRR2 4105 UINT64_C(4211081216), // t2MLA 4106 UINT64_C(4211081232), // t2MLS 4107 UINT64_C(4072669184), // t2MOVTi16 4108 UINT64_C(4031709184), // t2MOVi 4109 UINT64_C(4064280576), // t2MOVi16 4110 UINT64_C(3931045888), // t2MOVr 4111 UINT64_C(3932094560), // t2MOVsra_flag 4112 UINT64_C(3932094544), // t2MOVsrl_flag 4113 UINT64_C(3994026000), // t2MRC 4114 UINT64_C(4262461456), // t2MRC2 4115 UINT64_C(3964665856), // t2MRRC 4116 UINT64_C(4233101312), // t2MRRC2 4117 UINT64_C(4092559360), // t2MRS_AR 4118 UINT64_C(4092559360), // t2MRS_M 4119 UINT64_C(4091576352), // t2MRSbanked 4120 UINT64_C(4093607936), // t2MRSsys_AR 4121 UINT64_C(4085284864), // t2MSR_AR 4122 UINT64_C(4085284864), // t2MSR_M 4123 UINT64_C(4085284896), // t2MSRbanked 4124 UINT64_C(4211142656), // t2MUL 4125 UINT64_C(4033806336), // t2MVNi 4126 UINT64_C(3933143040), // t2MVNr 4127 UINT64_C(3933143040), // t2MVNs 4128 UINT64_C(4032823296), // t2ORNri 4129 UINT64_C(3932160000), // t2ORNrr 4130 UINT64_C(3932160000), // t2ORNrs 4131 UINT64_C(4030726144), // t2ORRri 4132 UINT64_C(3930062848), // t2ORRrr 4133 UINT64_C(3930062848), // t2ORRrs 4134 UINT64_C(4088365085), // t2PAC 4135 UINT64_C(4088365069), // t2PACBTI 4136 UINT64_C(4217434112), // t2PACG 4137 UINT64_C(3938451456), // t2PKHBT 4138 UINT64_C(3938451488), // t2PKHTB 4139 UINT64_C(4172345344), // t2PLDWi12 4140 UINT64_C(4163959808), // t2PLDWi8 4141 UINT64_C(4163956736), // t2PLDWs 4142 UINT64_C(4170248192), // t2PLDi12 4143 UINT64_C(4161862656), // t2PLDi8 4144 UINT64_C(4162842624), // t2PLDpci 4145 UINT64_C(4161859584), // t2PLDs 4146 UINT64_C(4187025408), // t2PLIi12 4147 UINT64_C(4178639872), // t2PLIi8 4148 UINT64_C(4179619840), // t2PLIpci 4149 UINT64_C(4178636800), // t2PLIs 4150 UINT64_C(4202754176), // t2QADD 4151 UINT64_C(4203802640), // t2QADD16 4152 UINT64_C(4202754064), // t2QADD8 4153 UINT64_C(4204851216), // t2QASX 4154 UINT64_C(4202754192), // t2QDADD 4155 UINT64_C(4202754224), // t2QDSUB 4156 UINT64_C(4209045520), // t2QSAX 4157 UINT64_C(4202754208), // t2QSUB 4158 UINT64_C(4207996944), // t2QSUB16 4159 UINT64_C(4206948368), // t2QSUB8 4160 UINT64_C(4203802784), // t2RBIT 4161 UINT64_C(4203802752), // t2REV 4162 UINT64_C(4203802768), // t2REV16 4163 UINT64_C(4203802800), // t2REVSH 4164 UINT64_C(3893411840), // t2RFEDB 4165 UINT64_C(3895508992), // t2RFEDBW 4166 UINT64_C(3918577664), // t2RFEIA 4167 UINT64_C(3920674816), // t2RFEIAW 4168 UINT64_C(3931045936), // t2RORri 4169 UINT64_C(4200656896), // t2RORrr 4170 UINT64_C(3931045936), // t2RRX 4171 UINT64_C(4055891968), // t2RSBri 4172 UINT64_C(3955228672), // t2RSBrr 4173 UINT64_C(3955228672), // t2RSBrs 4174 UINT64_C(4203802624), // t2SADD16 4175 UINT64_C(4202754048), // t2SADD8 4176 UINT64_C(4204851200), // t2SASX 4177 UINT64_C(4089417584), // t2SB 4178 UINT64_C(4049600512), // t2SBCri 4179 UINT64_C(3948937216), // t2SBCrr 4180 UINT64_C(3948937216), // t2SBCrs 4181 UINT64_C(4081057792), // t2SBFX 4182 UINT64_C(4220580080), // t2SDIV 4183 UINT64_C(4204851328), // t2SEL 4184 UINT64_C(46608), // t2SETPAN 4185 UINT64_C(3917474175), // t2SG 4186 UINT64_C(4203802656), // t2SHADD16 4187 UINT64_C(4202754080), // t2SHADD8 4188 UINT64_C(4204851232), // t2SHASX 4189 UINT64_C(4209045536), // t2SHSAX 4190 UINT64_C(4207996960), // t2SHSUB16 4191 UINT64_C(4206948384), // t2SHSUB8 4192 UINT64_C(4159733760), // t2SMC 4193 UINT64_C(4212129792), // t2SMLABB 4194 UINT64_C(4212129808), // t2SMLABT 4195 UINT64_C(4213178368), // t2SMLAD 4196 UINT64_C(4213178384), // t2SMLADX 4197 UINT64_C(4223664128), // t2SMLAL 4198 UINT64_C(4223664256), // t2SMLALBB 4199 UINT64_C(4223664272), // t2SMLALBT 4200 UINT64_C(4223664320), // t2SMLALD 4201 UINT64_C(4223664336), // t2SMLALDX 4202 UINT64_C(4223664288), // t2SMLALTB 4203 UINT64_C(4223664304), // t2SMLALTT 4204 UINT64_C(4212129824), // t2SMLATB 4205 UINT64_C(4212129840), // t2SMLATT 4206 UINT64_C(4214226944), // t2SMLAWB 4207 UINT64_C(4214226960), // t2SMLAWT 4208 UINT64_C(4215275520), // t2SMLSD 4209 UINT64_C(4215275536), // t2SMLSDX 4210 UINT64_C(4224712896), // t2SMLSLD 4211 UINT64_C(4224712912), // t2SMLSLDX 4212 UINT64_C(4216324096), // t2SMMLA 4213 UINT64_C(4216324112), // t2SMMLAR 4214 UINT64_C(4217372672), // t2SMMLS 4215 UINT64_C(4217372688), // t2SMMLSR 4216 UINT64_C(4216385536), // t2SMMUL 4217 UINT64_C(4216385552), // t2SMMULR 4218 UINT64_C(4213239808), // t2SMUAD 4219 UINT64_C(4213239824), // t2SMUADX 4220 UINT64_C(4212191232), // t2SMULBB 4221 UINT64_C(4212191248), // t2SMULBT 4222 UINT64_C(4219469824), // t2SMULL 4223 UINT64_C(4212191264), // t2SMULTB 4224 UINT64_C(4212191280), // t2SMULTT 4225 UINT64_C(4214288384), // t2SMULWB 4226 UINT64_C(4214288400), // t2SMULWT 4227 UINT64_C(4215336960), // t2SMUSD 4228 UINT64_C(4215336976), // t2SMUSDX 4229 UINT64_C(3893215232), // t2SRSDB 4230 UINT64_C(3895312384), // t2SRSDB_UPD 4231 UINT64_C(3918381056), // t2SRSIA 4232 UINT64_C(3920478208), // t2SRSIA_UPD 4233 UINT64_C(4076863488), // t2SSAT 4234 UINT64_C(4078960640), // t2SSAT16 4235 UINT64_C(4209045504), // t2SSAX 4236 UINT64_C(4207996928), // t2SSUB16 4237 UINT64_C(4206948352), // t2SSUB8 4238 UINT64_C(4248829952), // t2STC2L_OFFSET 4239 UINT64_C(4240441344), // t2STC2L_OPTION 4240 UINT64_C(4234149888), // t2STC2L_POST 4241 UINT64_C(4250927104), // t2STC2L_PRE 4242 UINT64_C(4244635648), // t2STC2_OFFSET 4243 UINT64_C(4236247040), // t2STC2_OPTION 4244 UINT64_C(4229955584), // t2STC2_POST 4245 UINT64_C(4246732800), // t2STC2_PRE 4246 UINT64_C(3980394496), // t2STCL_OFFSET 4247 UINT64_C(3972005888), // t2STCL_OPTION 4248 UINT64_C(3965714432), // t2STCL_POST 4249 UINT64_C(3982491648), // t2STCL_PRE 4250 UINT64_C(3976200192), // t2STC_OFFSET 4251 UINT64_C(3967811584), // t2STC_OPTION 4252 UINT64_C(3961520128), // t2STC_POST 4253 UINT64_C(3978297344), // t2STC_PRE 4254 UINT64_C(3904901039), // t2STL 4255 UINT64_C(3904901007), // t2STLB 4256 UINT64_C(3904901088), // t2STLEX 4257 UINT64_C(3904901056), // t2STLEXB 4258 UINT64_C(3904897264), // t2STLEXD 4259 UINT64_C(3904901072), // t2STLEXH 4260 UINT64_C(3904901023), // t2STLH 4261 UINT64_C(3909091328), // t2STMDB 4262 UINT64_C(3911188480), // t2STMDB_UPD 4263 UINT64_C(3900702720), // t2STMIA 4264 UINT64_C(3902799872), // t2STMIA_UPD 4265 UINT64_C(4160753152), // t2STRBT 4266 UINT64_C(4160751872), // t2STRB_POST 4267 UINT64_C(4160752896), // t2STRB_PRE 4268 UINT64_C(4169138176), // t2STRBi12 4269 UINT64_C(4160752640), // t2STRBi8 4270 UINT64_C(4160749568), // t2STRBs 4271 UINT64_C(3898605568), // t2STRD_POST 4272 UINT64_C(3915382784), // t2STRD_PRE 4273 UINT64_C(3913285632), // t2STRDi8 4274 UINT64_C(3896508416), // t2STREX 4275 UINT64_C(3904900928), // t2STREXB 4276 UINT64_C(3904897136), // t2STREXD 4277 UINT64_C(3904900944), // t2STREXH 4278 UINT64_C(4162850304), // t2STRHT 4279 UINT64_C(4162849024), // t2STRH_POST 4280 UINT64_C(4162850048), // t2STRH_PRE 4281 UINT64_C(4171235328), // t2STRHi12 4282 UINT64_C(4162849792), // t2STRHi8 4283 UINT64_C(4162846720), // t2STRHs 4284 UINT64_C(4164947456), // t2STRT 4285 UINT64_C(4164946176), // t2STR_POST 4286 UINT64_C(4164947200), // t2STR_PRE 4287 UINT64_C(4173332480), // t2STRi12 4288 UINT64_C(4164946944), // t2STRi8 4289 UINT64_C(4164943872), // t2STRs 4290 UINT64_C(4091449088), // t2SUBS_PC_LR 4291 UINT64_C(4053794816), // t2SUBri 4292 UINT64_C(4070572032), // t2SUBri12 4293 UINT64_C(3953131520), // t2SUBrr 4294 UINT64_C(3953131520), // t2SUBrs 4295 UINT64_C(4054650112), // t2SUBspImm 4296 UINT64_C(4071427328), // t2SUBspImm12 4297 UINT64_C(4198559872), // t2SXTAB 4298 UINT64_C(4196462720), // t2SXTAB16 4299 UINT64_C(4194365568), // t2SXTAH 4300 UINT64_C(4199542912), // t2SXTB 4301 UINT64_C(4197445760), // t2SXTB16 4302 UINT64_C(4195348608), // t2SXTH 4303 UINT64_C(3906007040), // t2TBB 4304 UINT64_C(3906007056), // t2TBH 4305 UINT64_C(4035972864), // t2TEQri 4306 UINT64_C(3935309568), // t2TEQrr 4307 UINT64_C(3935309568), // t2TEQrs 4308 UINT64_C(4088365074), // t2TSB 4309 UINT64_C(4027584256), // t2TSTri 4310 UINT64_C(3926920960), // t2TSTrr 4311 UINT64_C(3926920960), // t2TSTrs 4312 UINT64_C(3896569856), // t2TT 4313 UINT64_C(3896569984), // t2TTA 4314 UINT64_C(3896570048), // t2TTAT 4315 UINT64_C(3896569920), // t2TTT 4316 UINT64_C(4203802688), // t2UADD16 4317 UINT64_C(4202754112), // t2UADD8 4318 UINT64_C(4204851264), // t2UASX 4319 UINT64_C(4089446400), // t2UBFX 4320 UINT64_C(4159741952), // t2UDF 4321 UINT64_C(4222677232), // t2UDIV 4322 UINT64_C(4203802720), // t2UHADD16 4323 UINT64_C(4202754144), // t2UHADD8 4324 UINT64_C(4204851296), // t2UHASX 4325 UINT64_C(4209045600), // t2UHSAX 4326 UINT64_C(4207997024), // t2UHSUB16 4327 UINT64_C(4206948448), // t2UHSUB8 4328 UINT64_C(4225761376), // t2UMAAL 4329 UINT64_C(4225761280), // t2UMLAL 4330 UINT64_C(4221566976), // t2UMULL 4331 UINT64_C(4203802704), // t2UQADD16 4332 UINT64_C(4202754128), // t2UQADD8 4333 UINT64_C(4204851280), // t2UQASX 4334 UINT64_C(4209045584), // t2UQSAX 4335 UINT64_C(4207997008), // t2UQSUB16 4336 UINT64_C(4206948432), // t2UQSUB8 4337 UINT64_C(4218482688), // t2USAD8 4338 UINT64_C(4218421248), // t2USADA8 4339 UINT64_C(4085252096), // t2USAT 4340 UINT64_C(4087349248), // t2USAT16 4341 UINT64_C(4209045568), // t2USAX 4342 UINT64_C(4207996992), // t2USUB16 4343 UINT64_C(4206948416), // t2USUB8 4344 UINT64_C(4199608448), // t2UXTAB 4345 UINT64_C(4197511296), // t2UXTAB16 4346 UINT64_C(4195414144), // t2UXTAH 4347 UINT64_C(4200591488), // t2UXTB 4348 UINT64_C(4198494336), // t2UXTB16 4349 UINT64_C(4196397184), // t2UXTH 4350 UINT64_C(4030775297), // t2WLS 4351 UINT64_C(16704), // tADC 4352 UINT64_C(17408), // tADDhirr 4353 UINT64_C(7168), // tADDi3 4354 UINT64_C(12288), // tADDi8 4355 UINT64_C(17512), // tADDrSP 4356 UINT64_C(43008), // tADDrSPi 4357 UINT64_C(6144), // tADDrr 4358 UINT64_C(45056), // tADDspi 4359 UINT64_C(17541), // tADDspr 4360 UINT64_C(40960), // tADR 4361 UINT64_C(16384), // tAND 4362 UINT64_C(4096), // tASRri 4363 UINT64_C(16640), // tASRrr 4364 UINT64_C(57344), // tB 4365 UINT64_C(17280), // tBIC 4366 UINT64_C(48640), // tBKPT 4367 UINT64_C(4026585088), // tBL 4368 UINT64_C(18308), // tBLXNSr 4369 UINT64_C(4026580992), // tBLXi 4370 UINT64_C(18304), // tBLXr 4371 UINT64_C(18176), // tBX 4372 UINT64_C(18180), // tBXNS 4373 UINT64_C(53248), // tBcc 4374 UINT64_C(47360), // tCBNZ 4375 UINT64_C(45312), // tCBZ 4376 UINT64_C(17088), // tCMNz 4377 UINT64_C(17664), // tCMPhir 4378 UINT64_C(10240), // tCMPi8 4379 UINT64_C(17024), // tCMPr 4380 UINT64_C(46688), // tCPS 4381 UINT64_C(16448), // tEOR 4382 UINT64_C(48896), // tHINT 4383 UINT64_C(47744), // tHLT 4384 UINT64_C(0), // tInt_WIN_eh_sjlj_longjmp 4385 UINT64_C(0), // tInt_eh_sjlj_longjmp 4386 UINT64_C(0), // tInt_eh_sjlj_setjmp 4387 UINT64_C(51200), // tLDMIA 4388 UINT64_C(30720), // tLDRBi 4389 UINT64_C(23552), // tLDRBr 4390 UINT64_C(34816), // tLDRHi 4391 UINT64_C(23040), // tLDRHr 4392 UINT64_C(22016), // tLDRSB 4393 UINT64_C(24064), // tLDRSH 4394 UINT64_C(26624), // tLDRi 4395 UINT64_C(18432), // tLDRpci 4396 UINT64_C(22528), // tLDRr 4397 UINT64_C(38912), // tLDRspi 4398 UINT64_C(0), // tLSLri 4399 UINT64_C(16512), // tLSLrr 4400 UINT64_C(2048), // tLSRri 4401 UINT64_C(16576), // tLSRrr 4402 UINT64_C(0), // tMOVSr 4403 UINT64_C(8192), // tMOVi8 4404 UINT64_C(17920), // tMOVr 4405 UINT64_C(17216), // tMUL 4406 UINT64_C(17344), // tMVN 4407 UINT64_C(17152), // tORR 4408 UINT64_C(17528), // tPICADD 4409 UINT64_C(48128), // tPOP 4410 UINT64_C(46080), // tPUSH 4411 UINT64_C(47616), // tREV 4412 UINT64_C(47680), // tREV16 4413 UINT64_C(47808), // tREVSH 4414 UINT64_C(16832), // tROR 4415 UINT64_C(16960), // tRSB 4416 UINT64_C(16768), // tSBC 4417 UINT64_C(46672), // tSETEND 4418 UINT64_C(49152), // tSTMIA_UPD 4419 UINT64_C(28672), // tSTRBi 4420 UINT64_C(21504), // tSTRBr 4421 UINT64_C(32768), // tSTRHi 4422 UINT64_C(20992), // tSTRHr 4423 UINT64_C(24576), // tSTRi 4424 UINT64_C(20480), // tSTRr 4425 UINT64_C(36864), // tSTRspi 4426 UINT64_C(7680), // tSUBi3 4427 UINT64_C(14336), // tSUBi8 4428 UINT64_C(6656), // tSUBrr 4429 UINT64_C(45184), // tSUBspi 4430 UINT64_C(57088), // tSVC 4431 UINT64_C(45632), // tSXTB 4432 UINT64_C(45568), // tSXTH 4433 UINT64_C(57086), // tTRAP 4434 UINT64_C(16896), // tTST 4435 UINT64_C(56832), // tUDF 4436 UINT64_C(45760), // tUXTB 4437 UINT64_C(45696), // tUXTH 4438 UINT64_C(57081), // t__brkdiv0 4439 UINT64_C(0) 4440 }; 4441 const unsigned opcode = MI.getOpcode(); 4442 uint64_t Value = InstBits[opcode]; 4443 uint64_t op = 0; 4444 (void)op; // suppress warning 4445 switch (opcode) { 4446 case ARM::CLREX: 4447 case ARM::MVE_LCTP: 4448 case ARM::MVE_VPNOT: 4449 case ARM::SB: 4450 case ARM::TRAP: 4451 case ARM::TRAPNaCl: 4452 case ARM::TSB: 4453 case ARM::VBSPd: 4454 case ARM::VBSPq: 4455 case ARM::VLD1LNq16Pseudo: 4456 case ARM::VLD1LNq16Pseudo_UPD: 4457 case ARM::VLD1LNq32Pseudo: 4458 case ARM::VLD1LNq32Pseudo_UPD: 4459 case ARM::VLD1LNq8Pseudo: 4460 case ARM::VLD1LNq8Pseudo_UPD: 4461 case ARM::VLD1d16QPseudo: 4462 case ARM::VLD1d16QPseudoWB_fixed: 4463 case ARM::VLD1d16QPseudoWB_register: 4464 case ARM::VLD1d16TPseudo: 4465 case ARM::VLD1d16TPseudoWB_fixed: 4466 case ARM::VLD1d16TPseudoWB_register: 4467 case ARM::VLD1d32QPseudo: 4468 case ARM::VLD1d32QPseudoWB_fixed: 4469 case ARM::VLD1d32QPseudoWB_register: 4470 case ARM::VLD1d32TPseudo: 4471 case ARM::VLD1d32TPseudoWB_fixed: 4472 case ARM::VLD1d32TPseudoWB_register: 4473 case ARM::VLD1d64QPseudo: 4474 case ARM::VLD1d64QPseudoWB_fixed: 4475 case ARM::VLD1d64QPseudoWB_register: 4476 case ARM::VLD1d64TPseudo: 4477 case ARM::VLD1d64TPseudoWB_fixed: 4478 case ARM::VLD1d64TPseudoWB_register: 4479 case ARM::VLD1d8QPseudo: 4480 case ARM::VLD1d8QPseudoWB_fixed: 4481 case ARM::VLD1d8QPseudoWB_register: 4482 case ARM::VLD1d8TPseudo: 4483 case ARM::VLD1d8TPseudoWB_fixed: 4484 case ARM::VLD1d8TPseudoWB_register: 4485 case ARM::VLD1q16HighQPseudo: 4486 case ARM::VLD1q16HighQPseudo_UPD: 4487 case ARM::VLD1q16HighTPseudo: 4488 case ARM::VLD1q16HighTPseudo_UPD: 4489 case ARM::VLD1q16LowQPseudo_UPD: 4490 case ARM::VLD1q16LowTPseudo_UPD: 4491 case ARM::VLD1q32HighQPseudo: 4492 case ARM::VLD1q32HighQPseudo_UPD: 4493 case ARM::VLD1q32HighTPseudo: 4494 case ARM::VLD1q32HighTPseudo_UPD: 4495 case ARM::VLD1q32LowQPseudo_UPD: 4496 case ARM::VLD1q32LowTPseudo_UPD: 4497 case ARM::VLD1q64HighQPseudo: 4498 case ARM::VLD1q64HighQPseudo_UPD: 4499 case ARM::VLD1q64HighTPseudo: 4500 case ARM::VLD1q64HighTPseudo_UPD: 4501 case ARM::VLD1q64LowQPseudo_UPD: 4502 case ARM::VLD1q64LowTPseudo_UPD: 4503 case ARM::VLD1q8HighQPseudo: 4504 case ARM::VLD1q8HighQPseudo_UPD: 4505 case ARM::VLD1q8HighTPseudo: 4506 case ARM::VLD1q8HighTPseudo_UPD: 4507 case ARM::VLD1q8LowQPseudo_UPD: 4508 case ARM::VLD1q8LowTPseudo_UPD: 4509 case ARM::VLD2DUPq16EvenPseudo: 4510 case ARM::VLD2DUPq16OddPseudo: 4511 case ARM::VLD2DUPq16OddPseudoWB_fixed: 4512 case ARM::VLD2DUPq16OddPseudoWB_register: 4513 case ARM::VLD2DUPq32EvenPseudo: 4514 case ARM::VLD2DUPq32OddPseudo: 4515 case ARM::VLD2DUPq32OddPseudoWB_fixed: 4516 case ARM::VLD2DUPq32OddPseudoWB_register: 4517 case ARM::VLD2DUPq8EvenPseudo: 4518 case ARM::VLD2DUPq8OddPseudo: 4519 case ARM::VLD2DUPq8OddPseudoWB_fixed: 4520 case ARM::VLD2DUPq8OddPseudoWB_register: 4521 case ARM::VLD2LNd16Pseudo: 4522 case ARM::VLD2LNd16Pseudo_UPD: 4523 case ARM::VLD2LNd32Pseudo: 4524 case ARM::VLD2LNd32Pseudo_UPD: 4525 case ARM::VLD2LNd8Pseudo: 4526 case ARM::VLD2LNd8Pseudo_UPD: 4527 case ARM::VLD2LNq16Pseudo: 4528 case ARM::VLD2LNq16Pseudo_UPD: 4529 case ARM::VLD2LNq32Pseudo: 4530 case ARM::VLD2LNq32Pseudo_UPD: 4531 case ARM::VLD2q16Pseudo: 4532 case ARM::VLD2q16PseudoWB_fixed: 4533 case ARM::VLD2q16PseudoWB_register: 4534 case ARM::VLD2q32Pseudo: 4535 case ARM::VLD2q32PseudoWB_fixed: 4536 case ARM::VLD2q32PseudoWB_register: 4537 case ARM::VLD2q8Pseudo: 4538 case ARM::VLD2q8PseudoWB_fixed: 4539 case ARM::VLD2q8PseudoWB_register: 4540 case ARM::VLD3DUPd16Pseudo: 4541 case ARM::VLD3DUPd16Pseudo_UPD: 4542 case ARM::VLD3DUPd32Pseudo: 4543 case ARM::VLD3DUPd32Pseudo_UPD: 4544 case ARM::VLD3DUPd8Pseudo: 4545 case ARM::VLD3DUPd8Pseudo_UPD: 4546 case ARM::VLD3DUPq16EvenPseudo: 4547 case ARM::VLD3DUPq16OddPseudo: 4548 case ARM::VLD3DUPq16OddPseudo_UPD: 4549 case ARM::VLD3DUPq32EvenPseudo: 4550 case ARM::VLD3DUPq32OddPseudo: 4551 case ARM::VLD3DUPq32OddPseudo_UPD: 4552 case ARM::VLD3DUPq8EvenPseudo: 4553 case ARM::VLD3DUPq8OddPseudo: 4554 case ARM::VLD3DUPq8OddPseudo_UPD: 4555 case ARM::VLD3LNd16Pseudo: 4556 case ARM::VLD3LNd16Pseudo_UPD: 4557 case ARM::VLD3LNd32Pseudo: 4558 case ARM::VLD3LNd32Pseudo_UPD: 4559 case ARM::VLD3LNd8Pseudo: 4560 case ARM::VLD3LNd8Pseudo_UPD: 4561 case ARM::VLD3LNq16Pseudo: 4562 case ARM::VLD3LNq16Pseudo_UPD: 4563 case ARM::VLD3LNq32Pseudo: 4564 case ARM::VLD3LNq32Pseudo_UPD: 4565 case ARM::VLD3d16Pseudo: 4566 case ARM::VLD3d16Pseudo_UPD: 4567 case ARM::VLD3d32Pseudo: 4568 case ARM::VLD3d32Pseudo_UPD: 4569 case ARM::VLD3d8Pseudo: 4570 case ARM::VLD3d8Pseudo_UPD: 4571 case ARM::VLD3q16Pseudo_UPD: 4572 case ARM::VLD3q16oddPseudo: 4573 case ARM::VLD3q16oddPseudo_UPD: 4574 case ARM::VLD3q32Pseudo_UPD: 4575 case ARM::VLD3q32oddPseudo: 4576 case ARM::VLD3q32oddPseudo_UPD: 4577 case ARM::VLD3q8Pseudo_UPD: 4578 case ARM::VLD3q8oddPseudo: 4579 case ARM::VLD3q8oddPseudo_UPD: 4580 case ARM::VLD4DUPd16Pseudo: 4581 case ARM::VLD4DUPd16Pseudo_UPD: 4582 case ARM::VLD4DUPd32Pseudo: 4583 case ARM::VLD4DUPd32Pseudo_UPD: 4584 case ARM::VLD4DUPd8Pseudo: 4585 case ARM::VLD4DUPd8Pseudo_UPD: 4586 case ARM::VLD4DUPq16EvenPseudo: 4587 case ARM::VLD4DUPq16OddPseudo: 4588 case ARM::VLD4DUPq16OddPseudo_UPD: 4589 case ARM::VLD4DUPq32EvenPseudo: 4590 case ARM::VLD4DUPq32OddPseudo: 4591 case ARM::VLD4DUPq32OddPseudo_UPD: 4592 case ARM::VLD4DUPq8EvenPseudo: 4593 case ARM::VLD4DUPq8OddPseudo: 4594 case ARM::VLD4DUPq8OddPseudo_UPD: 4595 case ARM::VLD4LNd16Pseudo: 4596 case ARM::VLD4LNd16Pseudo_UPD: 4597 case ARM::VLD4LNd32Pseudo: 4598 case ARM::VLD4LNd32Pseudo_UPD: 4599 case ARM::VLD4LNd8Pseudo: 4600 case ARM::VLD4LNd8Pseudo_UPD: 4601 case ARM::VLD4LNq16Pseudo: 4602 case ARM::VLD4LNq16Pseudo_UPD: 4603 case ARM::VLD4LNq32Pseudo: 4604 case ARM::VLD4LNq32Pseudo_UPD: 4605 case ARM::VLD4d16Pseudo: 4606 case ARM::VLD4d16Pseudo_UPD: 4607 case ARM::VLD4d32Pseudo: 4608 case ARM::VLD4d32Pseudo_UPD: 4609 case ARM::VLD4d8Pseudo: 4610 case ARM::VLD4d8Pseudo_UPD: 4611 case ARM::VLD4q16Pseudo_UPD: 4612 case ARM::VLD4q16oddPseudo: 4613 case ARM::VLD4q16oddPseudo_UPD: 4614 case ARM::VLD4q32Pseudo_UPD: 4615 case ARM::VLD4q32oddPseudo: 4616 case ARM::VLD4q32oddPseudo_UPD: 4617 case ARM::VLD4q8Pseudo_UPD: 4618 case ARM::VLD4q8oddPseudo: 4619 case ARM::VLD4q8oddPseudo_UPD: 4620 case ARM::VLDMQIA: 4621 case ARM::VST1LNq16Pseudo: 4622 case ARM::VST1LNq16Pseudo_UPD: 4623 case ARM::VST1LNq32Pseudo: 4624 case ARM::VST1LNq32Pseudo_UPD: 4625 case ARM::VST1LNq8Pseudo: 4626 case ARM::VST1LNq8Pseudo_UPD: 4627 case ARM::VST1d16QPseudo: 4628 case ARM::VST1d16QPseudoWB_fixed: 4629 case ARM::VST1d16QPseudoWB_register: 4630 case ARM::VST1d16TPseudo: 4631 case ARM::VST1d16TPseudoWB_fixed: 4632 case ARM::VST1d16TPseudoWB_register: 4633 case ARM::VST1d32QPseudo: 4634 case ARM::VST1d32QPseudoWB_fixed: 4635 case ARM::VST1d32QPseudoWB_register: 4636 case ARM::VST1d32TPseudo: 4637 case ARM::VST1d32TPseudoWB_fixed: 4638 case ARM::VST1d32TPseudoWB_register: 4639 case ARM::VST1d64QPseudo: 4640 case ARM::VST1d64QPseudoWB_fixed: 4641 case ARM::VST1d64QPseudoWB_register: 4642 case ARM::VST1d64TPseudo: 4643 case ARM::VST1d64TPseudoWB_fixed: 4644 case ARM::VST1d64TPseudoWB_register: 4645 case ARM::VST1d8QPseudo: 4646 case ARM::VST1d8QPseudoWB_fixed: 4647 case ARM::VST1d8QPseudoWB_register: 4648 case ARM::VST1d8TPseudo: 4649 case ARM::VST1d8TPseudoWB_fixed: 4650 case ARM::VST1d8TPseudoWB_register: 4651 case ARM::VST1q16HighQPseudo: 4652 case ARM::VST1q16HighQPseudo_UPD: 4653 case ARM::VST1q16HighTPseudo: 4654 case ARM::VST1q16HighTPseudo_UPD: 4655 case ARM::VST1q16LowQPseudo_UPD: 4656 case ARM::VST1q16LowTPseudo_UPD: 4657 case ARM::VST1q32HighQPseudo: 4658 case ARM::VST1q32HighQPseudo_UPD: 4659 case ARM::VST1q32HighTPseudo: 4660 case ARM::VST1q32HighTPseudo_UPD: 4661 case ARM::VST1q32LowQPseudo_UPD: 4662 case ARM::VST1q32LowTPseudo_UPD: 4663 case ARM::VST1q64HighQPseudo: 4664 case ARM::VST1q64HighQPseudo_UPD: 4665 case ARM::VST1q64HighTPseudo: 4666 case ARM::VST1q64HighTPseudo_UPD: 4667 case ARM::VST1q64LowQPseudo_UPD: 4668 case ARM::VST1q64LowTPseudo_UPD: 4669 case ARM::VST1q8HighQPseudo: 4670 case ARM::VST1q8HighQPseudo_UPD: 4671 case ARM::VST1q8HighTPseudo: 4672 case ARM::VST1q8HighTPseudo_UPD: 4673 case ARM::VST1q8LowQPseudo_UPD: 4674 case ARM::VST1q8LowTPseudo_UPD: 4675 case ARM::VST2LNd16Pseudo: 4676 case ARM::VST2LNd16Pseudo_UPD: 4677 case ARM::VST2LNd32Pseudo: 4678 case ARM::VST2LNd32Pseudo_UPD: 4679 case ARM::VST2LNd8Pseudo: 4680 case ARM::VST2LNd8Pseudo_UPD: 4681 case ARM::VST2LNq16Pseudo: 4682 case ARM::VST2LNq16Pseudo_UPD: 4683 case ARM::VST2LNq32Pseudo: 4684 case ARM::VST2LNq32Pseudo_UPD: 4685 case ARM::VST2q16Pseudo: 4686 case ARM::VST2q16PseudoWB_fixed: 4687 case ARM::VST2q16PseudoWB_register: 4688 case ARM::VST2q32Pseudo: 4689 case ARM::VST2q32PseudoWB_fixed: 4690 case ARM::VST2q32PseudoWB_register: 4691 case ARM::VST2q8Pseudo: 4692 case ARM::VST2q8PseudoWB_fixed: 4693 case ARM::VST2q8PseudoWB_register: 4694 case ARM::VST3LNd16Pseudo: 4695 case ARM::VST3LNd16Pseudo_UPD: 4696 case ARM::VST3LNd32Pseudo: 4697 case ARM::VST3LNd32Pseudo_UPD: 4698 case ARM::VST3LNd8Pseudo: 4699 case ARM::VST3LNd8Pseudo_UPD: 4700 case ARM::VST3LNq16Pseudo: 4701 case ARM::VST3LNq16Pseudo_UPD: 4702 case ARM::VST3LNq32Pseudo: 4703 case ARM::VST3LNq32Pseudo_UPD: 4704 case ARM::VST3d16Pseudo: 4705 case ARM::VST3d16Pseudo_UPD: 4706 case ARM::VST3d32Pseudo: 4707 case ARM::VST3d32Pseudo_UPD: 4708 case ARM::VST3d8Pseudo: 4709 case ARM::VST3d8Pseudo_UPD: 4710 case ARM::VST3q16Pseudo_UPD: 4711 case ARM::VST3q16oddPseudo: 4712 case ARM::VST3q16oddPseudo_UPD: 4713 case ARM::VST3q32Pseudo_UPD: 4714 case ARM::VST3q32oddPseudo: 4715 case ARM::VST3q32oddPseudo_UPD: 4716 case ARM::VST3q8Pseudo_UPD: 4717 case ARM::VST3q8oddPseudo: 4718 case ARM::VST3q8oddPseudo_UPD: 4719 case ARM::VST4LNd16Pseudo: 4720 case ARM::VST4LNd16Pseudo_UPD: 4721 case ARM::VST4LNd32Pseudo: 4722 case ARM::VST4LNd32Pseudo_UPD: 4723 case ARM::VST4LNd8Pseudo: 4724 case ARM::VST4LNd8Pseudo_UPD: 4725 case ARM::VST4LNq16Pseudo: 4726 case ARM::VST4LNq16Pseudo_UPD: 4727 case ARM::VST4LNq32Pseudo: 4728 case ARM::VST4LNq32Pseudo_UPD: 4729 case ARM::VST4d16Pseudo: 4730 case ARM::VST4d16Pseudo_UPD: 4731 case ARM::VST4d32Pseudo: 4732 case ARM::VST4d32Pseudo_UPD: 4733 case ARM::VST4d8Pseudo: 4734 case ARM::VST4d8Pseudo_UPD: 4735 case ARM::VST4q16Pseudo_UPD: 4736 case ARM::VST4q16oddPseudo: 4737 case ARM::VST4q16oddPseudo_UPD: 4738 case ARM::VST4q32Pseudo_UPD: 4739 case ARM::VST4q32oddPseudo: 4740 case ARM::VST4q32oddPseudo_UPD: 4741 case ARM::VST4q8Pseudo_UPD: 4742 case ARM::VST4q8oddPseudo: 4743 case ARM::VST4q8oddPseudo_UPD: 4744 case ARM::VSTMQIA: 4745 case ARM::VTBL3Pseudo: 4746 case ARM::VTBL4Pseudo: 4747 case ARM::VTBX3Pseudo: 4748 case ARM::VTBX4Pseudo: 4749 case ARM::t2AUT: 4750 case ARM::t2BTI: 4751 case ARM::t2CLREX: 4752 case ARM::t2DCPS1: 4753 case ARM::t2DCPS2: 4754 case ARM::t2DCPS3: 4755 case ARM::t2Int_eh_sjlj_setjmp: 4756 case ARM::t2Int_eh_sjlj_setjmp_nofp: 4757 case ARM::t2PAC: 4758 case ARM::t2PACBTI: 4759 case ARM::t2SB: 4760 case ARM::t2SG: 4761 case ARM::t2TSB: 4762 case ARM::tInt_WIN_eh_sjlj_longjmp: 4763 case ARM::tInt_eh_sjlj_longjmp: 4764 case ARM::tInt_eh_sjlj_setjmp: 4765 case ARM::tTRAP: 4766 case ARM::t__brkdiv0: { 4767 break; 4768 } 4769 case ARM::VRINTAD: 4770 case ARM::VRINTMD: 4771 case ARM::VRINTND: 4772 case ARM::VRINTPD: { 4773 // op: Dd 4774 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4775 Value |= (op & UINT64_C(16)) << 18; 4776 Value |= (op & UINT64_C(15)) << 12; 4777 // op: Dm 4778 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4779 Value |= (op & UINT64_C(16)) << 1; 4780 Value |= (op & UINT64_C(15)); 4781 break; 4782 } 4783 case ARM::VFP_VMAXNMD: 4784 case ARM::VFP_VMINNMD: 4785 case ARM::VSELEQD: 4786 case ARM::VSELGED: 4787 case ARM::VSELGTD: 4788 case ARM::VSELVSD: { 4789 // op: Dd 4790 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4791 Value |= (op & UINT64_C(16)) << 18; 4792 Value |= (op & UINT64_C(15)) << 12; 4793 // op: Dn 4794 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4795 Value |= (op & UINT64_C(15)) << 16; 4796 Value |= (op & UINT64_C(16)) << 3; 4797 // op: Dm 4798 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4799 Value |= (op & UINT64_C(16)) << 1; 4800 Value |= (op & UINT64_C(15)); 4801 break; 4802 } 4803 case ARM::MVE_VPST: { 4804 // op: Mk 4805 op = getVPTMaskOpValue(MI, 0, Fixups, STI); 4806 Value |= (op & UINT64_C(8)) << 19; 4807 Value |= (op & UINT64_C(7)) << 13; 4808 break; 4809 } 4810 case ARM::MVE_VDUP16: 4811 case ARM::MVE_VDUP32: 4812 case ARM::MVE_VDUP8: { 4813 // op: Qd 4814 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4815 Value |= (op & UINT64_C(7)) << 17; 4816 Value |= (op & UINT64_C(8)) << 4; 4817 // op: Rt 4818 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4819 op &= UINT64_C(15); 4820 op <<= 12; 4821 Value |= op; 4822 break; 4823 } 4824 case ARM::MVE_VMOV_to_lane_32: { 4825 // op: Qd 4826 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4827 Value |= (op & UINT64_C(7)) << 17; 4828 Value |= (op & UINT64_C(8)) << 4; 4829 // op: Rt 4830 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4831 op &= UINT64_C(15); 4832 op <<= 12; 4833 Value |= op; 4834 // op: Idx 4835 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4836 Value |= (op & UINT64_C(1)) << 21; 4837 Value |= (op & UINT64_C(2)) << 15; 4838 break; 4839 } 4840 case ARM::MVE_VMOV_to_lane_16: { 4841 // op: Qd 4842 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4843 Value |= (op & UINT64_C(7)) << 17; 4844 Value |= (op & UINT64_C(8)) << 4; 4845 // op: Rt 4846 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4847 op &= UINT64_C(15); 4848 op <<= 12; 4849 Value |= op; 4850 // op: Idx 4851 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4852 Value |= (op & UINT64_C(2)) << 20; 4853 Value |= (op & UINT64_C(4)) << 14; 4854 Value |= (op & UINT64_C(1)) << 6; 4855 break; 4856 } 4857 case ARM::MVE_VMOV_to_lane_8: { 4858 // op: Qd 4859 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4860 Value |= (op & UINT64_C(7)) << 17; 4861 Value |= (op & UINT64_C(8)) << 4; 4862 // op: Rt 4863 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4864 op &= UINT64_C(15); 4865 op <<= 12; 4866 Value |= op; 4867 // op: Idx 4868 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4869 Value |= (op & UINT64_C(4)) << 19; 4870 Value |= (op & UINT64_C(8)) << 13; 4871 Value |= (op & UINT64_C(3)) << 5; 4872 break; 4873 } 4874 case ARM::MVE_VABSs16: 4875 case ARM::MVE_VABSs32: 4876 case ARM::MVE_VABSs8: 4877 case ARM::MVE_VCLSs16: 4878 case ARM::MVE_VCLSs32: 4879 case ARM::MVE_VCLSs8: 4880 case ARM::MVE_VCLZs16: 4881 case ARM::MVE_VCLZs32: 4882 case ARM::MVE_VCLZs8: 4883 case ARM::MVE_VCVTf32f16bh: 4884 case ARM::MVE_VCVTf32f16th: 4885 case ARM::MVE_VMOVLs16bh: 4886 case ARM::MVE_VMOVLs16th: 4887 case ARM::MVE_VMOVLs8bh: 4888 case ARM::MVE_VMOVLs8th: 4889 case ARM::MVE_VMOVLu16bh: 4890 case ARM::MVE_VMOVLu16th: 4891 case ARM::MVE_VMOVLu8bh: 4892 case ARM::MVE_VMOVLu8th: 4893 case ARM::MVE_VMVN: 4894 case ARM::MVE_VNEGs16: 4895 case ARM::MVE_VNEGs32: 4896 case ARM::MVE_VNEGs8: 4897 case ARM::MVE_VQABSs16: 4898 case ARM::MVE_VQABSs32: 4899 case ARM::MVE_VQABSs8: 4900 case ARM::MVE_VQNEGs16: 4901 case ARM::MVE_VQNEGs32: 4902 case ARM::MVE_VQNEGs8: 4903 case ARM::MVE_VREV16_8: 4904 case ARM::MVE_VREV32_16: 4905 case ARM::MVE_VREV32_8: 4906 case ARM::MVE_VREV64_16: 4907 case ARM::MVE_VREV64_32: 4908 case ARM::MVE_VREV64_8: 4909 case ARM::MVE_VSHLL_lws16bh: 4910 case ARM::MVE_VSHLL_lws16th: 4911 case ARM::MVE_VSHLL_lws8bh: 4912 case ARM::MVE_VSHLL_lws8th: 4913 case ARM::MVE_VSHLL_lwu16bh: 4914 case ARM::MVE_VSHLL_lwu16th: 4915 case ARM::MVE_VSHLL_lwu8bh: 4916 case ARM::MVE_VSHLL_lwu8th: { 4917 // op: Qd 4918 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4919 Value |= (op & UINT64_C(8)) << 19; 4920 Value |= (op & UINT64_C(7)) << 13; 4921 // op: Qm 4922 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4923 Value |= (op & UINT64_C(8)) << 2; 4924 Value |= (op & UINT64_C(7)) << 1; 4925 break; 4926 } 4927 case ARM::MVE_VQRSHL_by_vecs16: 4928 case ARM::MVE_VQRSHL_by_vecs32: 4929 case ARM::MVE_VQRSHL_by_vecs8: 4930 case ARM::MVE_VQRSHL_by_vecu16: 4931 case ARM::MVE_VQRSHL_by_vecu32: 4932 case ARM::MVE_VQRSHL_by_vecu8: 4933 case ARM::MVE_VQSHL_by_vecs16: 4934 case ARM::MVE_VQSHL_by_vecs32: 4935 case ARM::MVE_VQSHL_by_vecs8: 4936 case ARM::MVE_VQSHL_by_vecu16: 4937 case ARM::MVE_VQSHL_by_vecu32: 4938 case ARM::MVE_VQSHL_by_vecu8: 4939 case ARM::MVE_VRSHL_by_vecs16: 4940 case ARM::MVE_VRSHL_by_vecs32: 4941 case ARM::MVE_VRSHL_by_vecs8: 4942 case ARM::MVE_VRSHL_by_vecu16: 4943 case ARM::MVE_VRSHL_by_vecu32: 4944 case ARM::MVE_VRSHL_by_vecu8: 4945 case ARM::MVE_VSHL_by_vecs16: 4946 case ARM::MVE_VSHL_by_vecs32: 4947 case ARM::MVE_VSHL_by_vecs8: 4948 case ARM::MVE_VSHL_by_vecu16: 4949 case ARM::MVE_VSHL_by_vecu32: 4950 case ARM::MVE_VSHL_by_vecu8: { 4951 // op: Qd 4952 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4953 Value |= (op & UINT64_C(8)) << 19; 4954 Value |= (op & UINT64_C(7)) << 13; 4955 // op: Qm 4956 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4957 Value |= (op & UINT64_C(8)) << 2; 4958 Value |= (op & UINT64_C(7)) << 1; 4959 // op: Qn 4960 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4961 Value |= (op & UINT64_C(7)) << 17; 4962 Value |= (op & UINT64_C(8)) << 4; 4963 break; 4964 } 4965 case ARM::MVE_VSHLL_imms16bh: 4966 case ARM::MVE_VSHLL_imms16th: 4967 case ARM::MVE_VSHLL_immu16bh: 4968 case ARM::MVE_VSHLL_immu16th: { 4969 // op: Qd 4970 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4971 Value |= (op & UINT64_C(8)) << 19; 4972 Value |= (op & UINT64_C(7)) << 13; 4973 // op: Qm 4974 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4975 Value |= (op & UINT64_C(8)) << 2; 4976 Value |= (op & UINT64_C(7)) << 1; 4977 // op: imm 4978 op = getMVEShiftImmOpValue(MI, 2, Fixups, STI); 4979 op &= UINT64_C(15); 4980 op <<= 16; 4981 Value |= op; 4982 break; 4983 } 4984 case ARM::MVE_VSHLL_imms8bh: 4985 case ARM::MVE_VSHLL_imms8th: 4986 case ARM::MVE_VSHLL_immu8bh: 4987 case ARM::MVE_VSHLL_immu8th: { 4988 // op: Qd 4989 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4990 Value |= (op & UINT64_C(8)) << 19; 4991 Value |= (op & UINT64_C(7)) << 13; 4992 // op: Qm 4993 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4994 Value |= (op & UINT64_C(8)) << 2; 4995 Value |= (op & UINT64_C(7)) << 1; 4996 // op: imm 4997 op = getMVEShiftImmOpValue(MI, 2, Fixups, STI); 4998 op &= UINT64_C(7); 4999 op <<= 16; 5000 Value |= op; 5001 break; 5002 } 5003 case ARM::MVE_VQSHLU_imms16: 5004 case ARM::MVE_VQSHLimms16: 5005 case ARM::MVE_VQSHLimmu16: 5006 case ARM::MVE_VSHL_immi16: { 5007 // op: Qd 5008 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5009 Value |= (op & UINT64_C(8)) << 19; 5010 Value |= (op & UINT64_C(7)) << 13; 5011 // op: Qm 5012 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5013 Value |= (op & UINT64_C(8)) << 2; 5014 Value |= (op & UINT64_C(7)) << 1; 5015 // op: imm 5016 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5017 op &= UINT64_C(15); 5018 op <<= 16; 5019 Value |= op; 5020 break; 5021 } 5022 case ARM::MVE_VQSHLU_imms32: 5023 case ARM::MVE_VQSHLimms32: 5024 case ARM::MVE_VQSHLimmu32: 5025 case ARM::MVE_VSHL_immi32: { 5026 // op: Qd 5027 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5028 Value |= (op & UINT64_C(8)) << 19; 5029 Value |= (op & UINT64_C(7)) << 13; 5030 // op: Qm 5031 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5032 Value |= (op & UINT64_C(8)) << 2; 5033 Value |= (op & UINT64_C(7)) << 1; 5034 // op: imm 5035 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5036 op &= UINT64_C(31); 5037 op <<= 16; 5038 Value |= op; 5039 break; 5040 } 5041 case ARM::MVE_VQSHLU_imms8: 5042 case ARM::MVE_VQSHLimms8: 5043 case ARM::MVE_VQSHLimmu8: 5044 case ARM::MVE_VSHL_immi8: { 5045 // op: Qd 5046 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5047 Value |= (op & UINT64_C(8)) << 19; 5048 Value |= (op & UINT64_C(7)) << 13; 5049 // op: Qm 5050 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5051 Value |= (op & UINT64_C(8)) << 2; 5052 Value |= (op & UINT64_C(7)) << 1; 5053 // op: imm 5054 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5055 op &= UINT64_C(7); 5056 op <<= 16; 5057 Value |= op; 5058 break; 5059 } 5060 case ARM::MVE_VRSHR_imms16: 5061 case ARM::MVE_VRSHR_immu16: 5062 case ARM::MVE_VSHR_imms16: 5063 case ARM::MVE_VSHR_immu16: { 5064 // op: Qd 5065 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5066 Value |= (op & UINT64_C(8)) << 19; 5067 Value |= (op & UINT64_C(7)) << 13; 5068 // op: Qm 5069 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5070 Value |= (op & UINT64_C(8)) << 2; 5071 Value |= (op & UINT64_C(7)) << 1; 5072 // op: imm 5073 op = getShiftRight16Imm(MI, 2, Fixups, STI); 5074 op &= UINT64_C(15); 5075 op <<= 16; 5076 Value |= op; 5077 break; 5078 } 5079 case ARM::MVE_VRSHR_imms32: 5080 case ARM::MVE_VRSHR_immu32: 5081 case ARM::MVE_VSHR_imms32: 5082 case ARM::MVE_VSHR_immu32: { 5083 // op: Qd 5084 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5085 Value |= (op & UINT64_C(8)) << 19; 5086 Value |= (op & UINT64_C(7)) << 13; 5087 // op: Qm 5088 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5089 Value |= (op & UINT64_C(8)) << 2; 5090 Value |= (op & UINT64_C(7)) << 1; 5091 // op: imm 5092 op = getShiftRight32Imm(MI, 2, Fixups, STI); 5093 op &= UINT64_C(31); 5094 op <<= 16; 5095 Value |= op; 5096 break; 5097 } 5098 case ARM::MVE_VRSHR_imms8: 5099 case ARM::MVE_VRSHR_immu8: 5100 case ARM::MVE_VSHR_imms8: 5101 case ARM::MVE_VSHR_immu8: { 5102 // op: Qd 5103 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5104 Value |= (op & UINT64_C(8)) << 19; 5105 Value |= (op & UINT64_C(7)) << 13; 5106 // op: Qm 5107 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5108 Value |= (op & UINT64_C(8)) << 2; 5109 Value |= (op & UINT64_C(7)) << 1; 5110 // op: imm 5111 op = getShiftRight8Imm(MI, 2, Fixups, STI); 5112 op &= UINT64_C(7); 5113 op <<= 16; 5114 Value |= op; 5115 break; 5116 } 5117 case ARM::MVE_VCVTf16f32bh: 5118 case ARM::MVE_VCVTf16f32th: 5119 case ARM::MVE_VMAXAs16: 5120 case ARM::MVE_VMAXAs32: 5121 case ARM::MVE_VMAXAs8: 5122 case ARM::MVE_VMAXNMAf16: 5123 case ARM::MVE_VMAXNMAf32: 5124 case ARM::MVE_VMINAs16: 5125 case ARM::MVE_VMINAs32: 5126 case ARM::MVE_VMINAs8: 5127 case ARM::MVE_VMINNMAf16: 5128 case ARM::MVE_VMINNMAf32: 5129 case ARM::MVE_VMOVNi16bh: 5130 case ARM::MVE_VMOVNi16th: 5131 case ARM::MVE_VMOVNi32bh: 5132 case ARM::MVE_VMOVNi32th: 5133 case ARM::MVE_VQMOVNs16bh: 5134 case ARM::MVE_VQMOVNs16th: 5135 case ARM::MVE_VQMOVNs32bh: 5136 case ARM::MVE_VQMOVNs32th: 5137 case ARM::MVE_VQMOVNu16bh: 5138 case ARM::MVE_VQMOVNu16th: 5139 case ARM::MVE_VQMOVNu32bh: 5140 case ARM::MVE_VQMOVNu32th: 5141 case ARM::MVE_VQMOVUNs16bh: 5142 case ARM::MVE_VQMOVUNs16th: 5143 case ARM::MVE_VQMOVUNs32bh: 5144 case ARM::MVE_VQMOVUNs32th: { 5145 // op: Qd 5146 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5147 Value |= (op & UINT64_C(8)) << 19; 5148 Value |= (op & UINT64_C(7)) << 13; 5149 // op: Qm 5150 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5151 Value |= (op & UINT64_C(8)) << 2; 5152 Value |= (op & UINT64_C(7)) << 1; 5153 break; 5154 } 5155 case ARM::MVE_VAND: 5156 case ARM::MVE_VBIC: 5157 case ARM::MVE_VEOR: 5158 case ARM::MVE_VMULHs16: 5159 case ARM::MVE_VMULHs32: 5160 case ARM::MVE_VMULHs8: 5161 case ARM::MVE_VMULHu16: 5162 case ARM::MVE_VMULHu32: 5163 case ARM::MVE_VMULHu8: 5164 case ARM::MVE_VMULLBp16: 5165 case ARM::MVE_VMULLBp8: 5166 case ARM::MVE_VMULLBs16: 5167 case ARM::MVE_VMULLBs32: 5168 case ARM::MVE_VMULLBs8: 5169 case ARM::MVE_VMULLBu16: 5170 case ARM::MVE_VMULLBu32: 5171 case ARM::MVE_VMULLBu8: 5172 case ARM::MVE_VMULLTp16: 5173 case ARM::MVE_VMULLTp8: 5174 case ARM::MVE_VMULLTs16: 5175 case ARM::MVE_VMULLTs32: 5176 case ARM::MVE_VMULLTs8: 5177 case ARM::MVE_VMULLTu16: 5178 case ARM::MVE_VMULLTu32: 5179 case ARM::MVE_VMULLTu8: 5180 case ARM::MVE_VORN: 5181 case ARM::MVE_VORR: 5182 case ARM::MVE_VQDMULLs16bh: 5183 case ARM::MVE_VQDMULLs16th: 5184 case ARM::MVE_VQDMULLs32bh: 5185 case ARM::MVE_VQDMULLs32th: 5186 case ARM::MVE_VRMULHs16: 5187 case ARM::MVE_VRMULHs32: 5188 case ARM::MVE_VRMULHs8: 5189 case ARM::MVE_VRMULHu16: 5190 case ARM::MVE_VRMULHu32: 5191 case ARM::MVE_VRMULHu8: { 5192 // op: Qd 5193 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5194 Value |= (op & UINT64_C(8)) << 19; 5195 Value |= (op & UINT64_C(7)) << 13; 5196 // op: Qm 5197 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5198 Value |= (op & UINT64_C(8)) << 2; 5199 Value |= (op & UINT64_C(7)) << 1; 5200 // op: Qn 5201 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5202 Value |= (op & UINT64_C(7)) << 17; 5203 Value |= (op & UINT64_C(8)) << 4; 5204 break; 5205 } 5206 case ARM::MVE_VCMULf16: 5207 case ARM::MVE_VCMULf32: { 5208 // op: Qd 5209 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5210 Value |= (op & UINT64_C(8)) << 19; 5211 Value |= (op & UINT64_C(7)) << 13; 5212 // op: Qm 5213 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5214 Value |= (op & UINT64_C(8)) << 2; 5215 Value |= (op & UINT64_C(7)) << 1; 5216 // op: Qn 5217 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5218 Value |= (op & UINT64_C(7)) << 17; 5219 Value |= (op & UINT64_C(8)) << 4; 5220 // op: rot 5221 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 5222 Value |= (op & UINT64_C(2)) << 11; 5223 Value |= (op & UINT64_C(1)); 5224 break; 5225 } 5226 case ARM::MVE_VCADDi16: 5227 case ARM::MVE_VCADDi32: 5228 case ARM::MVE_VCADDi8: 5229 case ARM::MVE_VHCADDs16: 5230 case ARM::MVE_VHCADDs32: 5231 case ARM::MVE_VHCADDs8: { 5232 // op: Qd 5233 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5234 Value |= (op & UINT64_C(8)) << 19; 5235 Value |= (op & UINT64_C(7)) << 13; 5236 // op: Qm 5237 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5238 Value |= (op & UINT64_C(8)) << 2; 5239 Value |= (op & UINT64_C(7)) << 1; 5240 // op: Qn 5241 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5242 Value |= (op & UINT64_C(7)) << 17; 5243 Value |= (op & UINT64_C(8)) << 4; 5244 // op: rot 5245 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 5246 op &= UINT64_C(1); 5247 op <<= 12; 5248 Value |= op; 5249 break; 5250 } 5251 case ARM::MVE_VSLIimm16: { 5252 // op: Qd 5253 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5254 Value |= (op & UINT64_C(8)) << 19; 5255 Value |= (op & UINT64_C(7)) << 13; 5256 // op: Qm 5257 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5258 Value |= (op & UINT64_C(8)) << 2; 5259 Value |= (op & UINT64_C(7)) << 1; 5260 // op: imm 5261 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 5262 op &= UINT64_C(15); 5263 op <<= 16; 5264 Value |= op; 5265 break; 5266 } 5267 case ARM::MVE_VSLIimm32: { 5268 // op: Qd 5269 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5270 Value |= (op & UINT64_C(8)) << 19; 5271 Value |= (op & UINT64_C(7)) << 13; 5272 // op: Qm 5273 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5274 Value |= (op & UINT64_C(8)) << 2; 5275 Value |= (op & UINT64_C(7)) << 1; 5276 // op: imm 5277 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 5278 op &= UINT64_C(31); 5279 op <<= 16; 5280 Value |= op; 5281 break; 5282 } 5283 case ARM::MVE_VSLIimm8: { 5284 // op: Qd 5285 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5286 Value |= (op & UINT64_C(8)) << 19; 5287 Value |= (op & UINT64_C(7)) << 13; 5288 // op: Qm 5289 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5290 Value |= (op & UINT64_C(8)) << 2; 5291 Value |= (op & UINT64_C(7)) << 1; 5292 // op: imm 5293 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 5294 op &= UINT64_C(7); 5295 op <<= 16; 5296 Value |= op; 5297 break; 5298 } 5299 case ARM::MVE_VQRSHRNbhs32: 5300 case ARM::MVE_VQRSHRNbhu32: 5301 case ARM::MVE_VQRSHRNths32: 5302 case ARM::MVE_VQRSHRNthu32: 5303 case ARM::MVE_VQRSHRUNs32bh: 5304 case ARM::MVE_VQRSHRUNs32th: 5305 case ARM::MVE_VQSHRNbhs32: 5306 case ARM::MVE_VQSHRNbhu32: 5307 case ARM::MVE_VQSHRNths32: 5308 case ARM::MVE_VQSHRNthu32: 5309 case ARM::MVE_VQSHRUNs32bh: 5310 case ARM::MVE_VQSHRUNs32th: 5311 case ARM::MVE_VRSHRNi32bh: 5312 case ARM::MVE_VRSHRNi32th: 5313 case ARM::MVE_VSHRNi32bh: 5314 case ARM::MVE_VSHRNi32th: 5315 case ARM::MVE_VSRIimm16: { 5316 // op: Qd 5317 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5318 Value |= (op & UINT64_C(8)) << 19; 5319 Value |= (op & UINT64_C(7)) << 13; 5320 // op: Qm 5321 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5322 Value |= (op & UINT64_C(8)) << 2; 5323 Value |= (op & UINT64_C(7)) << 1; 5324 // op: imm 5325 op = getShiftRight16Imm(MI, 3, Fixups, STI); 5326 op &= UINT64_C(15); 5327 op <<= 16; 5328 Value |= op; 5329 break; 5330 } 5331 case ARM::MVE_VSRIimm32: { 5332 // op: Qd 5333 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5334 Value |= (op & UINT64_C(8)) << 19; 5335 Value |= (op & UINT64_C(7)) << 13; 5336 // op: Qm 5337 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5338 Value |= (op & UINT64_C(8)) << 2; 5339 Value |= (op & UINT64_C(7)) << 1; 5340 // op: imm 5341 op = getShiftRight32Imm(MI, 3, Fixups, STI); 5342 op &= UINT64_C(31); 5343 op <<= 16; 5344 Value |= op; 5345 break; 5346 } 5347 case ARM::MVE_VQRSHRNbhs16: 5348 case ARM::MVE_VQRSHRNbhu16: 5349 case ARM::MVE_VQRSHRNths16: 5350 case ARM::MVE_VQRSHRNthu16: 5351 case ARM::MVE_VQRSHRUNs16bh: 5352 case ARM::MVE_VQRSHRUNs16th: 5353 case ARM::MVE_VQSHRNbhs16: 5354 case ARM::MVE_VQSHRNbhu16: 5355 case ARM::MVE_VQSHRNths16: 5356 case ARM::MVE_VQSHRNthu16: 5357 case ARM::MVE_VQSHRUNs16bh: 5358 case ARM::MVE_VQSHRUNs16th: 5359 case ARM::MVE_VRSHRNi16bh: 5360 case ARM::MVE_VRSHRNi16th: 5361 case ARM::MVE_VSHRNi16bh: 5362 case ARM::MVE_VSHRNi16th: 5363 case ARM::MVE_VSRIimm8: { 5364 // op: Qd 5365 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5366 Value |= (op & UINT64_C(8)) << 19; 5367 Value |= (op & UINT64_C(7)) << 13; 5368 // op: Qm 5369 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5370 Value |= (op & UINT64_C(8)) << 2; 5371 Value |= (op & UINT64_C(7)) << 1; 5372 // op: imm 5373 op = getShiftRight8Imm(MI, 3, Fixups, STI); 5374 op &= UINT64_C(7); 5375 op <<= 16; 5376 Value |= op; 5377 break; 5378 } 5379 case ARM::MVE_VADC: 5380 case ARM::MVE_VADCI: 5381 case ARM::MVE_VQDMLADHXs16: 5382 case ARM::MVE_VQDMLADHXs32: 5383 case ARM::MVE_VQDMLADHXs8: 5384 case ARM::MVE_VQDMLADHs16: 5385 case ARM::MVE_VQDMLADHs32: 5386 case ARM::MVE_VQDMLADHs8: 5387 case ARM::MVE_VQDMLSDHXs16: 5388 case ARM::MVE_VQDMLSDHXs32: 5389 case ARM::MVE_VQDMLSDHXs8: 5390 case ARM::MVE_VQDMLSDHs16: 5391 case ARM::MVE_VQDMLSDHs32: 5392 case ARM::MVE_VQDMLSDHs8: 5393 case ARM::MVE_VQRDMLADHXs16: 5394 case ARM::MVE_VQRDMLADHXs32: 5395 case ARM::MVE_VQRDMLADHXs8: 5396 case ARM::MVE_VQRDMLADHs16: 5397 case ARM::MVE_VQRDMLADHs32: 5398 case ARM::MVE_VQRDMLADHs8: 5399 case ARM::MVE_VQRDMLSDHXs16: 5400 case ARM::MVE_VQRDMLSDHXs32: 5401 case ARM::MVE_VQRDMLSDHXs8: 5402 case ARM::MVE_VQRDMLSDHs16: 5403 case ARM::MVE_VQRDMLSDHs32: 5404 case ARM::MVE_VQRDMLSDHs8: 5405 case ARM::MVE_VSBC: 5406 case ARM::MVE_VSBCI: { 5407 // op: Qd 5408 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5409 Value |= (op & UINT64_C(8)) << 19; 5410 Value |= (op & UINT64_C(7)) << 13; 5411 // op: Qm 5412 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 5413 Value |= (op & UINT64_C(8)) << 2; 5414 Value |= (op & UINT64_C(7)) << 1; 5415 // op: Qn 5416 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5417 Value |= (op & UINT64_C(7)) << 17; 5418 Value |= (op & UINT64_C(8)) << 4; 5419 break; 5420 } 5421 case ARM::MVE_VABDs16: 5422 case ARM::MVE_VABDs32: 5423 case ARM::MVE_VABDs8: 5424 case ARM::MVE_VABDu16: 5425 case ARM::MVE_VABDu32: 5426 case ARM::MVE_VABDu8: 5427 case ARM::MVE_VADDi16: 5428 case ARM::MVE_VADDi32: 5429 case ARM::MVE_VADDi8: 5430 case ARM::MVE_VHADDs16: 5431 case ARM::MVE_VHADDs32: 5432 case ARM::MVE_VHADDs8: 5433 case ARM::MVE_VHADDu16: 5434 case ARM::MVE_VHADDu32: 5435 case ARM::MVE_VHADDu8: 5436 case ARM::MVE_VHSUBs16: 5437 case ARM::MVE_VHSUBs32: 5438 case ARM::MVE_VHSUBs8: 5439 case ARM::MVE_VHSUBu16: 5440 case ARM::MVE_VHSUBu32: 5441 case ARM::MVE_VHSUBu8: 5442 case ARM::MVE_VMAXNMf16: 5443 case ARM::MVE_VMAXNMf32: 5444 case ARM::MVE_VMAXs16: 5445 case ARM::MVE_VMAXs32: 5446 case ARM::MVE_VMAXs8: 5447 case ARM::MVE_VMAXu16: 5448 case ARM::MVE_VMAXu32: 5449 case ARM::MVE_VMAXu8: 5450 case ARM::MVE_VMINNMf16: 5451 case ARM::MVE_VMINNMf32: 5452 case ARM::MVE_VMINs16: 5453 case ARM::MVE_VMINs32: 5454 case ARM::MVE_VMINs8: 5455 case ARM::MVE_VMINu16: 5456 case ARM::MVE_VMINu32: 5457 case ARM::MVE_VMINu8: 5458 case ARM::MVE_VMULi16: 5459 case ARM::MVE_VMULi32: 5460 case ARM::MVE_VMULi8: 5461 case ARM::MVE_VQADDs16: 5462 case ARM::MVE_VQADDs32: 5463 case ARM::MVE_VQADDs8: 5464 case ARM::MVE_VQADDu16: 5465 case ARM::MVE_VQADDu32: 5466 case ARM::MVE_VQADDu8: 5467 case ARM::MVE_VQDMULHi16: 5468 case ARM::MVE_VQDMULHi32: 5469 case ARM::MVE_VQDMULHi8: 5470 case ARM::MVE_VQRDMULHi16: 5471 case ARM::MVE_VQRDMULHi32: 5472 case ARM::MVE_VQRDMULHi8: 5473 case ARM::MVE_VQSUBs16: 5474 case ARM::MVE_VQSUBs32: 5475 case ARM::MVE_VQSUBs8: 5476 case ARM::MVE_VQSUBu16: 5477 case ARM::MVE_VQSUBu32: 5478 case ARM::MVE_VQSUBu8: 5479 case ARM::MVE_VRHADDs16: 5480 case ARM::MVE_VRHADDs32: 5481 case ARM::MVE_VRHADDs8: 5482 case ARM::MVE_VRHADDu16: 5483 case ARM::MVE_VRHADDu32: 5484 case ARM::MVE_VRHADDu8: 5485 case ARM::MVE_VSUBi16: 5486 case ARM::MVE_VSUBi32: 5487 case ARM::MVE_VSUBi8: { 5488 // op: Qd 5489 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5490 Value |= (op & UINT64_C(8)) << 19; 5491 Value |= (op & UINT64_C(7)) << 13; 5492 // op: Qn 5493 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5494 Value |= (op & UINT64_C(7)) << 17; 5495 Value |= (op & UINT64_C(8)) << 4; 5496 // op: Qm 5497 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5498 Value |= (op & UINT64_C(8)) << 2; 5499 Value |= (op & UINT64_C(7)) << 1; 5500 break; 5501 } 5502 case ARM::MVE_VADD_qr_f16: 5503 case ARM::MVE_VADD_qr_f32: 5504 case ARM::MVE_VADD_qr_i16: 5505 case ARM::MVE_VADD_qr_i32: 5506 case ARM::MVE_VADD_qr_i8: 5507 case ARM::MVE_VBRSR16: 5508 case ARM::MVE_VBRSR32: 5509 case ARM::MVE_VBRSR8: 5510 case ARM::MVE_VHADD_qr_s16: 5511 case ARM::MVE_VHADD_qr_s32: 5512 case ARM::MVE_VHADD_qr_s8: 5513 case ARM::MVE_VHADD_qr_u16: 5514 case ARM::MVE_VHADD_qr_u32: 5515 case ARM::MVE_VHADD_qr_u8: 5516 case ARM::MVE_VHSUB_qr_s16: 5517 case ARM::MVE_VHSUB_qr_s32: 5518 case ARM::MVE_VHSUB_qr_s8: 5519 case ARM::MVE_VHSUB_qr_u16: 5520 case ARM::MVE_VHSUB_qr_u32: 5521 case ARM::MVE_VHSUB_qr_u8: 5522 case ARM::MVE_VMUL_qr_f16: 5523 case ARM::MVE_VMUL_qr_f32: 5524 case ARM::MVE_VMUL_qr_i16: 5525 case ARM::MVE_VMUL_qr_i32: 5526 case ARM::MVE_VMUL_qr_i8: 5527 case ARM::MVE_VQADD_qr_s16: 5528 case ARM::MVE_VQADD_qr_s32: 5529 case ARM::MVE_VQADD_qr_s8: 5530 case ARM::MVE_VQADD_qr_u16: 5531 case ARM::MVE_VQADD_qr_u32: 5532 case ARM::MVE_VQADD_qr_u8: 5533 case ARM::MVE_VQDMULH_qr_s16: 5534 case ARM::MVE_VQDMULH_qr_s32: 5535 case ARM::MVE_VQDMULH_qr_s8: 5536 case ARM::MVE_VQDMULL_qr_s16bh: 5537 case ARM::MVE_VQDMULL_qr_s16th: 5538 case ARM::MVE_VQDMULL_qr_s32bh: 5539 case ARM::MVE_VQDMULL_qr_s32th: 5540 case ARM::MVE_VQRDMULH_qr_s16: 5541 case ARM::MVE_VQRDMULH_qr_s32: 5542 case ARM::MVE_VQRDMULH_qr_s8: 5543 case ARM::MVE_VQSUB_qr_s16: 5544 case ARM::MVE_VQSUB_qr_s32: 5545 case ARM::MVE_VQSUB_qr_s8: 5546 case ARM::MVE_VQSUB_qr_u16: 5547 case ARM::MVE_VQSUB_qr_u32: 5548 case ARM::MVE_VQSUB_qr_u8: 5549 case ARM::MVE_VSUB_qr_f16: 5550 case ARM::MVE_VSUB_qr_f32: 5551 case ARM::MVE_VSUB_qr_i16: 5552 case ARM::MVE_VSUB_qr_i32: 5553 case ARM::MVE_VSUB_qr_i8: { 5554 // op: Qd 5555 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5556 Value |= (op & UINT64_C(8)) << 19; 5557 Value |= (op & UINT64_C(7)) << 13; 5558 // op: Qn 5559 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5560 Value |= (op & UINT64_C(7)) << 17; 5561 Value |= (op & UINT64_C(8)) << 4; 5562 // op: Rm 5563 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5564 op &= UINT64_C(15); 5565 Value |= op; 5566 break; 5567 } 5568 case ARM::MVE_VFMA_qr_Sf16: 5569 case ARM::MVE_VFMA_qr_Sf32: 5570 case ARM::MVE_VFMA_qr_f16: 5571 case ARM::MVE_VFMA_qr_f32: 5572 case ARM::MVE_VMLAS_qr_i16: 5573 case ARM::MVE_VMLAS_qr_i32: 5574 case ARM::MVE_VMLAS_qr_i8: 5575 case ARM::MVE_VMLA_qr_i16: 5576 case ARM::MVE_VMLA_qr_i32: 5577 case ARM::MVE_VMLA_qr_i8: 5578 case ARM::MVE_VQDMLAH_qrs16: 5579 case ARM::MVE_VQDMLAH_qrs32: 5580 case ARM::MVE_VQDMLAH_qrs8: 5581 case ARM::MVE_VQDMLASH_qrs16: 5582 case ARM::MVE_VQDMLASH_qrs32: 5583 case ARM::MVE_VQDMLASH_qrs8: 5584 case ARM::MVE_VQRDMLAH_qrs16: 5585 case ARM::MVE_VQRDMLAH_qrs32: 5586 case ARM::MVE_VQRDMLAH_qrs8: 5587 case ARM::MVE_VQRDMLASH_qrs16: 5588 case ARM::MVE_VQRDMLASH_qrs32: 5589 case ARM::MVE_VQRDMLASH_qrs8: { 5590 // op: Qd 5591 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5592 Value |= (op & UINT64_C(8)) << 19; 5593 Value |= (op & UINT64_C(7)) << 13; 5594 // op: Qn 5595 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5596 Value |= (op & UINT64_C(7)) << 17; 5597 Value |= (op & UINT64_C(8)) << 4; 5598 // op: Rm 5599 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 5600 op &= UINT64_C(15); 5601 Value |= op; 5602 break; 5603 } 5604 case ARM::MVE_VQRSHL_qrs16: 5605 case ARM::MVE_VQRSHL_qrs32: 5606 case ARM::MVE_VQRSHL_qrs8: 5607 case ARM::MVE_VQRSHL_qru16: 5608 case ARM::MVE_VQRSHL_qru32: 5609 case ARM::MVE_VQRSHL_qru8: 5610 case ARM::MVE_VQSHL_qrs16: 5611 case ARM::MVE_VQSHL_qrs32: 5612 case ARM::MVE_VQSHL_qrs8: 5613 case ARM::MVE_VQSHL_qru16: 5614 case ARM::MVE_VQSHL_qru32: 5615 case ARM::MVE_VQSHL_qru8: 5616 case ARM::MVE_VRSHL_qrs16: 5617 case ARM::MVE_VRSHL_qrs32: 5618 case ARM::MVE_VRSHL_qrs8: 5619 case ARM::MVE_VRSHL_qru16: 5620 case ARM::MVE_VRSHL_qru32: 5621 case ARM::MVE_VRSHL_qru8: 5622 case ARM::MVE_VSHL_qrs16: 5623 case ARM::MVE_VSHL_qrs32: 5624 case ARM::MVE_VSHL_qrs8: 5625 case ARM::MVE_VSHL_qru16: 5626 case ARM::MVE_VSHL_qru32: 5627 case ARM::MVE_VSHL_qru8: { 5628 // op: Qd 5629 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5630 Value |= (op & UINT64_C(8)) << 19; 5631 Value |= (op & UINT64_C(7)) << 13; 5632 // op: Rm 5633 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5634 op &= UINT64_C(15); 5635 Value |= op; 5636 break; 5637 } 5638 case ARM::MVE_VDWDUPu16: 5639 case ARM::MVE_VDWDUPu32: 5640 case ARM::MVE_VDWDUPu8: 5641 case ARM::MVE_VIWDUPu16: 5642 case ARM::MVE_VIWDUPu32: 5643 case ARM::MVE_VIWDUPu8: { 5644 // op: Qd 5645 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5646 Value |= (op & UINT64_C(8)) << 19; 5647 Value |= (op & UINT64_C(7)) << 13; 5648 // op: Rm 5649 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 5650 op &= UINT64_C(14); 5651 Value |= op; 5652 // op: Rn 5653 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5654 op &= UINT64_C(14); 5655 op <<= 16; 5656 Value |= op; 5657 // op: imm 5658 op = getPowerTwoOpValue(MI, 4, Fixups, STI); 5659 Value |= (op & UINT64_C(2)) << 6; 5660 Value |= (op & UINT64_C(1)); 5661 break; 5662 } 5663 case ARM::MVE_VDDUPu16: 5664 case ARM::MVE_VDDUPu32: 5665 case ARM::MVE_VDDUPu8: 5666 case ARM::MVE_VIDUPu16: 5667 case ARM::MVE_VIDUPu32: 5668 case ARM::MVE_VIDUPu8: { 5669 // op: Qd 5670 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5671 Value |= (op & UINT64_C(8)) << 19; 5672 Value |= (op & UINT64_C(7)) << 13; 5673 // op: Rn 5674 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5675 op &= UINT64_C(14); 5676 op <<= 16; 5677 Value |= op; 5678 // op: imm 5679 op = getPowerTwoOpValue(MI, 3, Fixups, STI); 5680 Value |= (op & UINT64_C(2)) << 6; 5681 Value |= (op & UINT64_C(1)); 5682 break; 5683 } 5684 case ARM::MVE_VLDRWU32_qi: 5685 case ARM::MVE_VSTRW32_qi: { 5686 // op: Qd 5687 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5688 op &= UINT64_C(7); 5689 op <<= 13; 5690 Value |= op; 5691 // op: addr 5692 op = getMveAddrModeQOpValue<2>(MI, 1, Fixups, STI); 5693 Value |= (op & UINT64_C(128)) << 16; 5694 Value |= (op & UINT64_C(1792)) << 9; 5695 Value |= (op & UINT64_C(127)); 5696 break; 5697 } 5698 case ARM::MVE_VLDRDU64_qi: 5699 case ARM::MVE_VSTRD64_qi: { 5700 // op: Qd 5701 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5702 op &= UINT64_C(7); 5703 op <<= 13; 5704 Value |= op; 5705 // op: addr 5706 op = getMveAddrModeQOpValue<3>(MI, 1, Fixups, STI); 5707 Value |= (op & UINT64_C(128)) << 16; 5708 Value |= (op & UINT64_C(1792)) << 9; 5709 Value |= (op & UINT64_C(127)); 5710 break; 5711 } 5712 case ARM::MVE_VLDRBS16_rq: 5713 case ARM::MVE_VLDRBS32_rq: 5714 case ARM::MVE_VLDRBU16_rq: 5715 case ARM::MVE_VLDRBU32_rq: 5716 case ARM::MVE_VLDRBU8_rq: 5717 case ARM::MVE_VLDRDU64_rq: 5718 case ARM::MVE_VLDRDU64_rq_u: 5719 case ARM::MVE_VLDRHS32_rq: 5720 case ARM::MVE_VLDRHS32_rq_u: 5721 case ARM::MVE_VLDRHU16_rq: 5722 case ARM::MVE_VLDRHU16_rq_u: 5723 case ARM::MVE_VLDRHU32_rq: 5724 case ARM::MVE_VLDRHU32_rq_u: 5725 case ARM::MVE_VLDRWU32_rq: 5726 case ARM::MVE_VLDRWU32_rq_u: 5727 case ARM::MVE_VSTRB16_rq: 5728 case ARM::MVE_VSTRB32_rq: 5729 case ARM::MVE_VSTRB8_rq: 5730 case ARM::MVE_VSTRD64_rq: 5731 case ARM::MVE_VSTRD64_rq_u: 5732 case ARM::MVE_VSTRH16_rq: 5733 case ARM::MVE_VSTRH16_rq_u: 5734 case ARM::MVE_VSTRH32_rq: 5735 case ARM::MVE_VSTRH32_rq_u: 5736 case ARM::MVE_VSTRW32_rq: 5737 case ARM::MVE_VSTRW32_rq_u: { 5738 // op: Qd 5739 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5740 op &= UINT64_C(7); 5741 op <<= 13; 5742 Value |= op; 5743 // op: addr 5744 op = getMveAddrModeRQOpValue(MI, 1, Fixups, STI); 5745 Value |= (op & UINT64_C(120)) << 13; 5746 Value |= (op & UINT64_C(7)) << 1; 5747 break; 5748 } 5749 case ARM::MVE_VLDRBS16: 5750 case ARM::MVE_VLDRBS32: 5751 case ARM::MVE_VLDRBU16: 5752 case ARM::MVE_VLDRBU32: 5753 case ARM::MVE_VSTRB16: 5754 case ARM::MVE_VSTRB32: { 5755 // op: Qd 5756 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5757 op &= UINT64_C(7); 5758 op <<= 13; 5759 Value |= op; 5760 // op: addr 5761 op = getT2AddrModeImmOpValue<7,0>(MI, 1, Fixups, STI); 5762 Value |= (op & UINT64_C(128)) << 16; 5763 Value |= (op & UINT64_C(1792)) << 8; 5764 Value |= (op & UINT64_C(127)); 5765 break; 5766 } 5767 case ARM::MVE_VLDRBU8: 5768 case ARM::MVE_VSTRBU8: { 5769 // op: Qd 5770 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5771 op &= UINT64_C(7); 5772 op <<= 13; 5773 Value |= op; 5774 // op: addr 5775 op = getT2AddrModeImmOpValue<7,0>(MI, 1, Fixups, STI); 5776 Value |= (op & UINT64_C(128)) << 16; 5777 Value |= (op & UINT64_C(3840)) << 8; 5778 Value |= (op & UINT64_C(127)); 5779 break; 5780 } 5781 case ARM::MVE_VLDRHS32: 5782 case ARM::MVE_VLDRHU32: 5783 case ARM::MVE_VSTRH32: { 5784 // op: Qd 5785 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5786 op &= UINT64_C(7); 5787 op <<= 13; 5788 Value |= op; 5789 // op: addr 5790 op = getT2AddrModeImmOpValue<7,1>(MI, 1, Fixups, STI); 5791 Value |= (op & UINT64_C(128)) << 16; 5792 Value |= (op & UINT64_C(1792)) << 8; 5793 Value |= (op & UINT64_C(127)); 5794 break; 5795 } 5796 case ARM::MVE_VLDRHU16: 5797 case ARM::MVE_VSTRHU16: { 5798 // op: Qd 5799 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5800 op &= UINT64_C(7); 5801 op <<= 13; 5802 Value |= op; 5803 // op: addr 5804 op = getT2AddrModeImmOpValue<7,1>(MI, 1, Fixups, STI); 5805 Value |= (op & UINT64_C(128)) << 16; 5806 Value |= (op & UINT64_C(3840)) << 8; 5807 Value |= (op & UINT64_C(127)); 5808 break; 5809 } 5810 case ARM::MVE_VLDRWU32: 5811 case ARM::MVE_VSTRWU32: { 5812 // op: Qd 5813 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5814 op &= UINT64_C(7); 5815 op <<= 13; 5816 Value |= op; 5817 // op: addr 5818 op = getT2AddrModeImmOpValue<7,2>(MI, 1, Fixups, STI); 5819 Value |= (op & UINT64_C(128)) << 16; 5820 Value |= (op & UINT64_C(3840)) << 8; 5821 Value |= (op & UINT64_C(127)); 5822 break; 5823 } 5824 case ARM::MVE_VMOV_from_lane_32: { 5825 // op: Qd 5826 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5827 Value |= (op & UINT64_C(7)) << 17; 5828 Value |= (op & UINT64_C(8)) << 4; 5829 // op: Rt 5830 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5831 op &= UINT64_C(15); 5832 op <<= 12; 5833 Value |= op; 5834 // op: Idx 5835 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5836 Value |= (op & UINT64_C(1)) << 21; 5837 Value |= (op & UINT64_C(2)) << 15; 5838 break; 5839 } 5840 case ARM::MVE_VMOV_from_lane_s16: 5841 case ARM::MVE_VMOV_from_lane_u16: { 5842 // op: Qd 5843 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5844 Value |= (op & UINT64_C(7)) << 17; 5845 Value |= (op & UINT64_C(8)) << 4; 5846 // op: Rt 5847 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5848 op &= UINT64_C(15); 5849 op <<= 12; 5850 Value |= op; 5851 // op: Idx 5852 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5853 Value |= (op & UINT64_C(2)) << 20; 5854 Value |= (op & UINT64_C(4)) << 14; 5855 Value |= (op & UINT64_C(1)) << 6; 5856 break; 5857 } 5858 case ARM::MVE_VMOV_from_lane_s8: 5859 case ARM::MVE_VMOV_from_lane_u8: { 5860 // op: Qd 5861 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5862 Value |= (op & UINT64_C(7)) << 17; 5863 Value |= (op & UINT64_C(8)) << 4; 5864 // op: Rt 5865 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5866 op &= UINT64_C(15); 5867 op <<= 12; 5868 Value |= op; 5869 // op: Idx 5870 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5871 Value |= (op & UINT64_C(4)) << 19; 5872 Value |= (op & UINT64_C(8)) << 13; 5873 Value |= (op & UINT64_C(3)) << 5; 5874 break; 5875 } 5876 case ARM::MVE_VLDRWU32_qi_pre: 5877 case ARM::MVE_VSTRW32_qi_pre: { 5878 // op: Qd 5879 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5880 op &= UINT64_C(7); 5881 op <<= 13; 5882 Value |= op; 5883 // op: addr 5884 op = getMveAddrModeQOpValue<2>(MI, 2, Fixups, STI); 5885 Value |= (op & UINT64_C(128)) << 16; 5886 Value |= (op & UINT64_C(1792)) << 9; 5887 Value |= (op & UINT64_C(127)); 5888 break; 5889 } 5890 case ARM::MVE_VLDRDU64_qi_pre: 5891 case ARM::MVE_VSTRD64_qi_pre: { 5892 // op: Qd 5893 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5894 op &= UINT64_C(7); 5895 op <<= 13; 5896 Value |= op; 5897 // op: addr 5898 op = getMveAddrModeQOpValue<3>(MI, 2, Fixups, STI); 5899 Value |= (op & UINT64_C(128)) << 16; 5900 Value |= (op & UINT64_C(1792)) << 9; 5901 Value |= (op & UINT64_C(127)); 5902 break; 5903 } 5904 case ARM::MVE_VLDRBS16_pre: 5905 case ARM::MVE_VLDRBS32_pre: 5906 case ARM::MVE_VLDRBU16_pre: 5907 case ARM::MVE_VLDRBU32_pre: 5908 case ARM::MVE_VSTRB16_pre: 5909 case ARM::MVE_VSTRB32_pre: { 5910 // op: Qd 5911 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5912 op &= UINT64_C(7); 5913 op <<= 13; 5914 Value |= op; 5915 // op: addr 5916 op = getT2AddrModeImmOpValue<7,0>(MI, 2, Fixups, STI); 5917 Value |= (op & UINT64_C(128)) << 16; 5918 Value |= (op & UINT64_C(1792)) << 8; 5919 Value |= (op & UINT64_C(127)); 5920 break; 5921 } 5922 case ARM::MVE_VLDRBU8_pre: 5923 case ARM::MVE_VSTRBU8_pre: { 5924 // op: Qd 5925 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5926 op &= UINT64_C(7); 5927 op <<= 13; 5928 Value |= op; 5929 // op: addr 5930 op = getT2AddrModeImmOpValue<7,0>(MI, 2, Fixups, STI); 5931 Value |= (op & UINT64_C(128)) << 16; 5932 Value |= (op & UINT64_C(3840)) << 8; 5933 Value |= (op & UINT64_C(127)); 5934 break; 5935 } 5936 case ARM::MVE_VLDRHS32_pre: 5937 case ARM::MVE_VLDRHU32_pre: 5938 case ARM::MVE_VSTRH32_pre: { 5939 // op: Qd 5940 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5941 op &= UINT64_C(7); 5942 op <<= 13; 5943 Value |= op; 5944 // op: addr 5945 op = getT2AddrModeImmOpValue<7,1>(MI, 2, Fixups, STI); 5946 Value |= (op & UINT64_C(128)) << 16; 5947 Value |= (op & UINT64_C(1792)) << 8; 5948 Value |= (op & UINT64_C(127)); 5949 break; 5950 } 5951 case ARM::MVE_VLDRHU16_pre: 5952 case ARM::MVE_VSTRHU16_pre: { 5953 // op: Qd 5954 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5955 op &= UINT64_C(7); 5956 op <<= 13; 5957 Value |= op; 5958 // op: addr 5959 op = getT2AddrModeImmOpValue<7,1>(MI, 2, Fixups, STI); 5960 Value |= (op & UINT64_C(128)) << 16; 5961 Value |= (op & UINT64_C(3840)) << 8; 5962 Value |= (op & UINT64_C(127)); 5963 break; 5964 } 5965 case ARM::MVE_VLDRWU32_pre: 5966 case ARM::MVE_VSTRWU32_pre: { 5967 // op: Qd 5968 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5969 op &= UINT64_C(7); 5970 op <<= 13; 5971 Value |= op; 5972 // op: addr 5973 op = getT2AddrModeImmOpValue<7,2>(MI, 2, Fixups, STI); 5974 Value |= (op & UINT64_C(128)) << 16; 5975 Value |= (op & UINT64_C(3840)) << 8; 5976 Value |= (op & UINT64_C(127)); 5977 break; 5978 } 5979 case ARM::MVE_VLDRBU8_post: 5980 case ARM::MVE_VSTRBU8_post: { 5981 // op: Qd 5982 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5983 op &= UINT64_C(7); 5984 op <<= 13; 5985 Value |= op; 5986 // op: addr 5987 op = getT2ScaledImmOpValue<7,0>(MI, 3, Fixups, STI); 5988 Value |= (op & UINT64_C(128)) << 16; 5989 Value |= (op & UINT64_C(127)); 5990 // op: Rn 5991 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5992 op &= UINT64_C(15); 5993 op <<= 16; 5994 Value |= op; 5995 break; 5996 } 5997 case ARM::MVE_VLDRBS16_post: 5998 case ARM::MVE_VLDRBS32_post: 5999 case ARM::MVE_VLDRBU16_post: 6000 case ARM::MVE_VLDRBU32_post: 6001 case ARM::MVE_VSTRB16_post: 6002 case ARM::MVE_VSTRB32_post: { 6003 // op: Qd 6004 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6005 op &= UINT64_C(7); 6006 op <<= 13; 6007 Value |= op; 6008 // op: addr 6009 op = getT2ScaledImmOpValue<7,0>(MI, 3, Fixups, STI); 6010 Value |= (op & UINT64_C(128)) << 16; 6011 Value |= (op & UINT64_C(127)); 6012 // op: Rn 6013 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6014 op &= UINT64_C(7); 6015 op <<= 16; 6016 Value |= op; 6017 break; 6018 } 6019 case ARM::MVE_VLDRHU16_post: 6020 case ARM::MVE_VSTRHU16_post: { 6021 // op: Qd 6022 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6023 op &= UINT64_C(7); 6024 op <<= 13; 6025 Value |= op; 6026 // op: addr 6027 op = getT2ScaledImmOpValue<7,1>(MI, 3, Fixups, STI); 6028 Value |= (op & UINT64_C(128)) << 16; 6029 Value |= (op & UINT64_C(127)); 6030 // op: Rn 6031 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6032 op &= UINT64_C(15); 6033 op <<= 16; 6034 Value |= op; 6035 break; 6036 } 6037 case ARM::MVE_VLDRHS32_post: 6038 case ARM::MVE_VLDRHU32_post: 6039 case ARM::MVE_VSTRH32_post: { 6040 // op: Qd 6041 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6042 op &= UINT64_C(7); 6043 op <<= 13; 6044 Value |= op; 6045 // op: addr 6046 op = getT2ScaledImmOpValue<7,1>(MI, 3, Fixups, STI); 6047 Value |= (op & UINT64_C(128)) << 16; 6048 Value |= (op & UINT64_C(127)); 6049 // op: Rn 6050 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6051 op &= UINT64_C(7); 6052 op <<= 16; 6053 Value |= op; 6054 break; 6055 } 6056 case ARM::MVE_VLDRWU32_post: 6057 case ARM::MVE_VSTRWU32_post: { 6058 // op: Qd 6059 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6060 op &= UINT64_C(7); 6061 op <<= 13; 6062 Value |= op; 6063 // op: addr 6064 op = getT2ScaledImmOpValue<7,2>(MI, 3, Fixups, STI); 6065 Value |= (op & UINT64_C(128)) << 16; 6066 Value |= (op & UINT64_C(127)); 6067 // op: Rn 6068 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6069 op &= UINT64_C(15); 6070 op <<= 16; 6071 Value |= op; 6072 break; 6073 } 6074 case ARM::MVE_VABSf16: 6075 case ARM::MVE_VABSf32: 6076 case ARM::MVE_VCVTf16s16n: 6077 case ARM::MVE_VCVTf16u16n: 6078 case ARM::MVE_VCVTf32s32n: 6079 case ARM::MVE_VCVTf32u32n: 6080 case ARM::MVE_VCVTs16f16a: 6081 case ARM::MVE_VCVTs16f16m: 6082 case ARM::MVE_VCVTs16f16n: 6083 case ARM::MVE_VCVTs16f16p: 6084 case ARM::MVE_VCVTs16f16z: 6085 case ARM::MVE_VCVTs32f32a: 6086 case ARM::MVE_VCVTs32f32m: 6087 case ARM::MVE_VCVTs32f32n: 6088 case ARM::MVE_VCVTs32f32p: 6089 case ARM::MVE_VCVTs32f32z: 6090 case ARM::MVE_VCVTu16f16a: 6091 case ARM::MVE_VCVTu16f16m: 6092 case ARM::MVE_VCVTu16f16n: 6093 case ARM::MVE_VCVTu16f16p: 6094 case ARM::MVE_VCVTu16f16z: 6095 case ARM::MVE_VCVTu32f32a: 6096 case ARM::MVE_VCVTu32f32m: 6097 case ARM::MVE_VCVTu32f32n: 6098 case ARM::MVE_VCVTu32f32p: 6099 case ARM::MVE_VCVTu32f32z: 6100 case ARM::MVE_VNEGf16: 6101 case ARM::MVE_VNEGf32: 6102 case ARM::MVE_VRINTf16A: 6103 case ARM::MVE_VRINTf16M: 6104 case ARM::MVE_VRINTf16N: 6105 case ARM::MVE_VRINTf16P: 6106 case ARM::MVE_VRINTf16X: 6107 case ARM::MVE_VRINTf16Z: 6108 case ARM::MVE_VRINTf32A: 6109 case ARM::MVE_VRINTf32M: 6110 case ARM::MVE_VRINTf32N: 6111 case ARM::MVE_VRINTf32P: 6112 case ARM::MVE_VRINTf32X: 6113 case ARM::MVE_VRINTf32Z: { 6114 // op: Qm 6115 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6116 Value |= (op & UINT64_C(8)) << 2; 6117 Value |= (op & UINT64_C(7)) << 1; 6118 // op: Qd 6119 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6120 Value |= (op & UINT64_C(8)) << 19; 6121 Value |= (op & UINT64_C(7)) << 13; 6122 break; 6123 } 6124 case ARM::MVE_VCVTf16s16_fix: 6125 case ARM::MVE_VCVTf16u16_fix: 6126 case ARM::MVE_VCVTs16f16_fix: 6127 case ARM::MVE_VCVTu16f16_fix: { 6128 // op: Qm 6129 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6130 Value |= (op & UINT64_C(8)) << 2; 6131 Value |= (op & UINT64_C(7)) << 1; 6132 // op: Qd 6133 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6134 Value |= (op & UINT64_C(8)) << 19; 6135 Value |= (op & UINT64_C(7)) << 13; 6136 // op: imm6 6137 op = getNEONVcvtImm32OpValue(MI, 2, Fixups, STI); 6138 op &= UINT64_C(15); 6139 op <<= 16; 6140 Value |= op; 6141 break; 6142 } 6143 case ARM::MVE_VCVTf32s32_fix: 6144 case ARM::MVE_VCVTf32u32_fix: 6145 case ARM::MVE_VCVTs32f32_fix: 6146 case ARM::MVE_VCVTu32f32_fix: { 6147 // op: Qm 6148 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6149 Value |= (op & UINT64_C(8)) << 2; 6150 Value |= (op & UINT64_C(7)) << 1; 6151 // op: Qd 6152 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6153 Value |= (op & UINT64_C(8)) << 19; 6154 Value |= (op & UINT64_C(7)) << 13; 6155 // op: imm6 6156 op = getNEONVcvtImm32OpValue(MI, 2, Fixups, STI); 6157 op &= UINT64_C(31); 6158 op <<= 16; 6159 Value |= op; 6160 break; 6161 } 6162 case ARM::MVE_VADDVs16no_acc: 6163 case ARM::MVE_VADDVs32no_acc: 6164 case ARM::MVE_VADDVs8no_acc: 6165 case ARM::MVE_VADDVu16no_acc: 6166 case ARM::MVE_VADDVu32no_acc: 6167 case ARM::MVE_VADDVu8no_acc: { 6168 // op: Qm 6169 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6170 op &= UINT64_C(7); 6171 op <<= 1; 6172 Value |= op; 6173 // op: Rda 6174 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6175 op &= UINT64_C(14); 6176 op <<= 12; 6177 Value |= op; 6178 break; 6179 } 6180 case ARM::MVE_VABDf16: 6181 case ARM::MVE_VABDf32: 6182 case ARM::MVE_VADDf16: 6183 case ARM::MVE_VADDf32: 6184 case ARM::MVE_VMULf16: 6185 case ARM::MVE_VMULf32: 6186 case ARM::MVE_VSUBf16: 6187 case ARM::MVE_VSUBf32: { 6188 // op: Qm 6189 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6190 Value |= (op & UINT64_C(8)) << 2; 6191 Value |= (op & UINT64_C(7)) << 1; 6192 // op: Qd 6193 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6194 Value |= (op & UINT64_C(8)) << 19; 6195 Value |= (op & UINT64_C(7)) << 13; 6196 // op: Qn 6197 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6198 Value |= (op & UINT64_C(7)) << 17; 6199 Value |= (op & UINT64_C(8)) << 4; 6200 break; 6201 } 6202 case ARM::MVE_VCADDf16: 6203 case ARM::MVE_VCADDf32: { 6204 // op: Qm 6205 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6206 Value |= (op & UINT64_C(8)) << 2; 6207 Value |= (op & UINT64_C(7)) << 1; 6208 // op: Qd 6209 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6210 Value |= (op & UINT64_C(8)) << 19; 6211 Value |= (op & UINT64_C(7)) << 13; 6212 // op: Qn 6213 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6214 Value |= (op & UINT64_C(7)) << 17; 6215 Value |= (op & UINT64_C(8)) << 4; 6216 // op: rot 6217 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6218 op &= UINT64_C(1); 6219 op <<= 24; 6220 Value |= op; 6221 break; 6222 } 6223 case ARM::MVE_VADDVs16acc: 6224 case ARM::MVE_VADDVs32acc: 6225 case ARM::MVE_VADDVs8acc: 6226 case ARM::MVE_VADDVu16acc: 6227 case ARM::MVE_VADDVu32acc: 6228 case ARM::MVE_VADDVu8acc: { 6229 // op: Qm 6230 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6231 op &= UINT64_C(7); 6232 op <<= 1; 6233 Value |= op; 6234 // op: Rda 6235 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6236 op &= UINT64_C(14); 6237 op <<= 12; 6238 Value |= op; 6239 break; 6240 } 6241 case ARM::MVE_VMAXAVs16: 6242 case ARM::MVE_VMAXAVs32: 6243 case ARM::MVE_VMAXAVs8: 6244 case ARM::MVE_VMAXNMAVf16: 6245 case ARM::MVE_VMAXNMAVf32: 6246 case ARM::MVE_VMAXNMVf16: 6247 case ARM::MVE_VMAXNMVf32: 6248 case ARM::MVE_VMAXVs16: 6249 case ARM::MVE_VMAXVs32: 6250 case ARM::MVE_VMAXVs8: 6251 case ARM::MVE_VMAXVu16: 6252 case ARM::MVE_VMAXVu32: 6253 case ARM::MVE_VMAXVu8: 6254 case ARM::MVE_VMINAVs16: 6255 case ARM::MVE_VMINAVs32: 6256 case ARM::MVE_VMINAVs8: 6257 case ARM::MVE_VMINNMAVf16: 6258 case ARM::MVE_VMINNMAVf32: 6259 case ARM::MVE_VMINNMVf16: 6260 case ARM::MVE_VMINNMVf32: 6261 case ARM::MVE_VMINVs16: 6262 case ARM::MVE_VMINVs32: 6263 case ARM::MVE_VMINVs8: 6264 case ARM::MVE_VMINVu16: 6265 case ARM::MVE_VMINVu32: 6266 case ARM::MVE_VMINVu8: { 6267 // op: Qm 6268 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6269 op &= UINT64_C(7); 6270 op <<= 1; 6271 Value |= op; 6272 // op: RdaDest 6273 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6274 op &= UINT64_C(15); 6275 op <<= 12; 6276 Value |= op; 6277 break; 6278 } 6279 case ARM::MVE_VADDLVs32no_acc: 6280 case ARM::MVE_VADDLVu32no_acc: { 6281 // op: Qm 6282 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6283 op &= UINT64_C(7); 6284 op <<= 1; 6285 Value |= op; 6286 // op: RdaLo 6287 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6288 op &= UINT64_C(14); 6289 op <<= 12; 6290 Value |= op; 6291 // op: RdaHi 6292 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6293 op &= UINT64_C(14); 6294 op <<= 19; 6295 Value |= op; 6296 break; 6297 } 6298 case ARM::MVE_VFMAf16: 6299 case ARM::MVE_VFMAf32: 6300 case ARM::MVE_VFMSf16: 6301 case ARM::MVE_VFMSf32: { 6302 // op: Qm 6303 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6304 Value |= (op & UINT64_C(8)) << 2; 6305 Value |= (op & UINT64_C(7)) << 1; 6306 // op: Qd 6307 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6308 Value |= (op & UINT64_C(8)) << 19; 6309 Value |= (op & UINT64_C(7)) << 13; 6310 // op: Qn 6311 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6312 Value |= (op & UINT64_C(7)) << 17; 6313 Value |= (op & UINT64_C(8)) << 4; 6314 break; 6315 } 6316 case ARM::MVE_VCMLAf16: 6317 case ARM::MVE_VCMLAf32: { 6318 // op: Qm 6319 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6320 Value |= (op & UINT64_C(8)) << 2; 6321 Value |= (op & UINT64_C(7)) << 1; 6322 // op: Qd 6323 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6324 Value |= (op & UINT64_C(8)) << 19; 6325 Value |= (op & UINT64_C(7)) << 13; 6326 // op: Qn 6327 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6328 Value |= (op & UINT64_C(7)) << 17; 6329 Value |= (op & UINT64_C(8)) << 4; 6330 // op: rot 6331 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 6332 op &= UINT64_C(3); 6333 op <<= 23; 6334 Value |= op; 6335 break; 6336 } 6337 case ARM::MVE_VABAVs16: 6338 case ARM::MVE_VABAVs32: 6339 case ARM::MVE_VABAVs8: 6340 case ARM::MVE_VABAVu16: 6341 case ARM::MVE_VABAVu32: 6342 case ARM::MVE_VABAVu8: { 6343 // op: Qm 6344 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6345 Value |= (op & UINT64_C(8)) << 2; 6346 Value |= (op & UINT64_C(7)) << 1; 6347 // op: Qn 6348 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6349 Value |= (op & UINT64_C(7)) << 17; 6350 Value |= (op & UINT64_C(8)) << 4; 6351 // op: Rda 6352 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6353 op &= UINT64_C(15); 6354 op <<= 12; 6355 Value |= op; 6356 break; 6357 } 6358 case ARM::MVE_VADDLVs32acc: 6359 case ARM::MVE_VADDLVu32acc: { 6360 // op: Qm 6361 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 6362 op &= UINT64_C(7); 6363 op <<= 1; 6364 Value |= op; 6365 // op: RdaLo 6366 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6367 op &= UINT64_C(14); 6368 op <<= 12; 6369 Value |= op; 6370 // op: RdaHi 6371 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6372 op &= UINT64_C(14); 6373 op <<= 19; 6374 Value |= op; 6375 break; 6376 } 6377 case ARM::MVE_VPSEL: { 6378 // op: Qn 6379 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6380 Value |= (op & UINT64_C(7)) << 17; 6381 Value |= (op & UINT64_C(8)) << 4; 6382 // op: Qd 6383 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6384 Value |= (op & UINT64_C(8)) << 19; 6385 Value |= (op & UINT64_C(7)) << 13; 6386 // op: Qm 6387 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6388 Value |= (op & UINT64_C(8)) << 2; 6389 Value |= (op & UINT64_C(7)) << 1; 6390 break; 6391 } 6392 case ARM::t2AUTG: 6393 case ARM::t2BXAUT: { 6394 // op: Ra 6395 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6396 op &= UINT64_C(15); 6397 op <<= 12; 6398 Value |= op; 6399 // op: Rn 6400 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6401 op &= UINT64_C(15); 6402 op <<= 16; 6403 Value |= op; 6404 // op: Rm 6405 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 6406 op &= UINT64_C(15); 6407 Value |= op; 6408 break; 6409 } 6410 case ARM::tMOVr: { 6411 // op: Rd 6412 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6413 Value |= (op & UINT64_C(8)) << 4; 6414 Value |= (op & UINT64_C(7)); 6415 // op: Rm 6416 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6417 op &= UINT64_C(15); 6418 op <<= 3; 6419 Value |= op; 6420 break; 6421 } 6422 case ARM::t2STLEX: { 6423 // op: Rd 6424 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6425 op &= UINT64_C(15); 6426 Value |= op; 6427 // op: Rt 6428 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6429 op &= UINT64_C(15); 6430 op <<= 12; 6431 Value |= op; 6432 // op: addr 6433 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6434 op &= UINT64_C(15); 6435 op <<= 16; 6436 Value |= op; 6437 break; 6438 } 6439 case ARM::t2STLEXB: 6440 case ARM::t2STLEXH: 6441 case ARM::t2STREXB: 6442 case ARM::t2STREXH: { 6443 // op: Rd 6444 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6445 op &= UINT64_C(15); 6446 Value |= op; 6447 // op: addr 6448 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6449 op &= UINT64_C(15); 6450 op <<= 16; 6451 Value |= op; 6452 // op: Rt 6453 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6454 op &= UINT64_C(15); 6455 op <<= 12; 6456 Value |= op; 6457 break; 6458 } 6459 case ARM::t2STLEXD: 6460 case ARM::t2STREXD: { 6461 // op: Rd 6462 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6463 op &= UINT64_C(15); 6464 Value |= op; 6465 // op: addr 6466 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6467 op &= UINT64_C(15); 6468 op <<= 16; 6469 Value |= op; 6470 // op: Rt 6471 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6472 op &= UINT64_C(15); 6473 op <<= 12; 6474 Value |= op; 6475 // op: Rt2 6476 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6477 op &= UINT64_C(15); 6478 op <<= 8; 6479 Value |= op; 6480 break; 6481 } 6482 case ARM::CRC32B: 6483 case ARM::CRC32CB: 6484 case ARM::CRC32CH: 6485 case ARM::CRC32CW: 6486 case ARM::CRC32H: 6487 case ARM::CRC32W: { 6488 // op: Rd 6489 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6490 op &= UINT64_C(15); 6491 op <<= 12; 6492 Value |= op; 6493 // op: Rn 6494 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6495 op &= UINT64_C(15); 6496 op <<= 16; 6497 Value |= op; 6498 // op: Rm 6499 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6500 op &= UINT64_C(15); 6501 Value |= op; 6502 break; 6503 } 6504 case ARM::t2MRS_AR: 6505 case ARM::t2MRSsys_AR: { 6506 // op: Rd 6507 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6508 op &= UINT64_C(15); 6509 op <<= 8; 6510 Value |= op; 6511 break; 6512 } 6513 case ARM::t2CLZ: 6514 case ARM::t2RBIT: 6515 case ARM::t2REV: 6516 case ARM::t2REV16: 6517 case ARM::t2REVSH: { 6518 // op: Rd 6519 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6520 op &= UINT64_C(15); 6521 op <<= 8; 6522 Value |= op; 6523 // op: Rm 6524 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6525 Value |= (op & UINT64_C(15)) << 16; 6526 Value |= (op & UINT64_C(15)); 6527 break; 6528 } 6529 case ARM::t2MOVsra_flag: 6530 case ARM::t2MOVsrl_flag: { 6531 // op: Rd 6532 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6533 op &= UINT64_C(15); 6534 op <<= 8; 6535 Value |= op; 6536 // op: Rm 6537 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6538 op &= UINT64_C(15); 6539 Value |= op; 6540 break; 6541 } 6542 case ARM::t2SXTB: 6543 case ARM::t2SXTB16: 6544 case ARM::t2SXTH: 6545 case ARM::t2UXTB: 6546 case ARM::t2UXTB16: 6547 case ARM::t2UXTH: { 6548 // op: Rd 6549 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6550 op &= UINT64_C(15); 6551 op <<= 8; 6552 Value |= op; 6553 // op: Rm 6554 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6555 op &= UINT64_C(15); 6556 Value |= op; 6557 // op: rot 6558 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6559 op &= UINT64_C(3); 6560 op <<= 4; 6561 Value |= op; 6562 break; 6563 } 6564 case ARM::t2CSEL: 6565 case ARM::t2CSINC: 6566 case ARM::t2CSINV: 6567 case ARM::t2CSNEG: { 6568 // op: Rd 6569 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6570 op &= UINT64_C(15); 6571 op <<= 8; 6572 Value |= op; 6573 // op: Rm 6574 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6575 op &= UINT64_C(15); 6576 Value |= op; 6577 // op: Rn 6578 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6579 op &= UINT64_C(15); 6580 op <<= 16; 6581 Value |= op; 6582 // op: fcond 6583 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6584 op &= UINT64_C(15); 6585 op <<= 4; 6586 Value |= op; 6587 break; 6588 } 6589 case ARM::t2CRC32B: 6590 case ARM::t2CRC32CB: 6591 case ARM::t2CRC32CH: 6592 case ARM::t2CRC32CW: 6593 case ARM::t2CRC32H: 6594 case ARM::t2CRC32W: 6595 case ARM::t2MUL: 6596 case ARM::t2QADD16: 6597 case ARM::t2QADD8: 6598 case ARM::t2QASX: 6599 case ARM::t2QSAX: 6600 case ARM::t2QSUB16: 6601 case ARM::t2QSUB8: 6602 case ARM::t2SADD16: 6603 case ARM::t2SADD8: 6604 case ARM::t2SASX: 6605 case ARM::t2SDIV: 6606 case ARM::t2SEL: 6607 case ARM::t2SHADD16: 6608 case ARM::t2SHADD8: 6609 case ARM::t2SHASX: 6610 case ARM::t2SHSAX: 6611 case ARM::t2SHSUB16: 6612 case ARM::t2SHSUB8: 6613 case ARM::t2SMMUL: 6614 case ARM::t2SMMULR: 6615 case ARM::t2SMUAD: 6616 case ARM::t2SMUADX: 6617 case ARM::t2SMULBB: 6618 case ARM::t2SMULBT: 6619 case ARM::t2SMULTB: 6620 case ARM::t2SMULTT: 6621 case ARM::t2SMULWB: 6622 case ARM::t2SMULWT: 6623 case ARM::t2SMUSD: 6624 case ARM::t2SMUSDX: 6625 case ARM::t2SSAX: 6626 case ARM::t2SSUB16: 6627 case ARM::t2SSUB8: 6628 case ARM::t2UADD16: 6629 case ARM::t2UADD8: 6630 case ARM::t2UASX: 6631 case ARM::t2UDIV: 6632 case ARM::t2UHADD16: 6633 case ARM::t2UHADD8: 6634 case ARM::t2UHASX: 6635 case ARM::t2UHSAX: 6636 case ARM::t2UHSUB16: 6637 case ARM::t2UHSUB8: 6638 case ARM::t2UQADD16: 6639 case ARM::t2UQADD8: 6640 case ARM::t2UQASX: 6641 case ARM::t2UQSAX: 6642 case ARM::t2UQSUB16: 6643 case ARM::t2UQSUB8: 6644 case ARM::t2USAD8: 6645 case ARM::t2USAX: 6646 case ARM::t2USUB16: 6647 case ARM::t2USUB8: { 6648 // op: Rd 6649 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6650 op &= UINT64_C(15); 6651 op <<= 8; 6652 Value |= op; 6653 // op: Rn 6654 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6655 op &= UINT64_C(15); 6656 op <<= 16; 6657 Value |= op; 6658 // op: Rm 6659 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6660 op &= UINT64_C(15); 6661 Value |= op; 6662 break; 6663 } 6664 case ARM::t2MLA: 6665 case ARM::t2MLS: 6666 case ARM::t2SMLABB: 6667 case ARM::t2SMLABT: 6668 case ARM::t2SMLAD: 6669 case ARM::t2SMLADX: 6670 case ARM::t2SMLATB: 6671 case ARM::t2SMLATT: 6672 case ARM::t2SMLAWB: 6673 case ARM::t2SMLAWT: 6674 case ARM::t2SMLSD: 6675 case ARM::t2SMLSDX: 6676 case ARM::t2SMMLA: 6677 case ARM::t2SMMLAR: 6678 case ARM::t2SMMLS: 6679 case ARM::t2SMMLSR: 6680 case ARM::t2USADA8: { 6681 // op: Rd 6682 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6683 op &= UINT64_C(15); 6684 op <<= 8; 6685 Value |= op; 6686 // op: Rn 6687 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6688 op &= UINT64_C(15); 6689 op <<= 16; 6690 Value |= op; 6691 // op: Rm 6692 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6693 op &= UINT64_C(15); 6694 Value |= op; 6695 // op: Ra 6696 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6697 op &= UINT64_C(15); 6698 op <<= 12; 6699 Value |= op; 6700 break; 6701 } 6702 case ARM::t2SXTAB: 6703 case ARM::t2SXTAB16: 6704 case ARM::t2SXTAH: 6705 case ARM::t2UXTAB: 6706 case ARM::t2UXTAB16: 6707 case ARM::t2UXTAH: { 6708 // op: Rd 6709 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6710 op &= UINT64_C(15); 6711 op <<= 8; 6712 Value |= op; 6713 // op: Rn 6714 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6715 op &= UINT64_C(15); 6716 op <<= 16; 6717 Value |= op; 6718 // op: Rm 6719 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6720 op &= UINT64_C(15); 6721 Value |= op; 6722 // op: rot 6723 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6724 op &= UINT64_C(3); 6725 op <<= 4; 6726 Value |= op; 6727 break; 6728 } 6729 case ARM::t2PKHBT: 6730 case ARM::t2PKHTB: { 6731 // op: Rd 6732 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6733 op &= UINT64_C(15); 6734 op <<= 8; 6735 Value |= op; 6736 // op: Rn 6737 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6738 op &= UINT64_C(15); 6739 op <<= 16; 6740 Value |= op; 6741 // op: Rm 6742 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6743 op &= UINT64_C(15); 6744 Value |= op; 6745 // op: sh 6746 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6747 Value |= (op & UINT64_C(28)) << 10; 6748 Value |= (op & UINT64_C(3)) << 6; 6749 break; 6750 } 6751 case ARM::t2ADDri12: 6752 case ARM::t2SUBri12: { 6753 // op: Rd 6754 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6755 op &= UINT64_C(15); 6756 op <<= 8; 6757 Value |= op; 6758 // op: Rn 6759 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6760 op &= UINT64_C(15); 6761 op <<= 16; 6762 Value |= op; 6763 // op: imm 6764 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6765 Value |= (op & UINT64_C(2048)) << 15; 6766 Value |= (op & UINT64_C(1792)) << 4; 6767 Value |= (op & UINT64_C(255)); 6768 break; 6769 } 6770 case ARM::t2QADD: 6771 case ARM::t2QDADD: 6772 case ARM::t2QDSUB: 6773 case ARM::t2QSUB: { 6774 // op: Rd 6775 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6776 op &= UINT64_C(15); 6777 op <<= 8; 6778 Value |= op; 6779 // op: Rn 6780 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6781 op &= UINT64_C(15); 6782 op <<= 16; 6783 Value |= op; 6784 // op: Rm 6785 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6786 op &= UINT64_C(15); 6787 Value |= op; 6788 break; 6789 } 6790 case ARM::t2BFI: { 6791 // op: Rd 6792 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6793 op &= UINT64_C(15); 6794 op <<= 8; 6795 Value |= op; 6796 // op: Rn 6797 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6798 op &= UINT64_C(15); 6799 op <<= 16; 6800 Value |= op; 6801 // op: imm 6802 op = getBitfieldInvertedMaskOpValue(MI, 3, Fixups, STI); 6803 Value |= (op & UINT64_C(28)) << 10; 6804 Value |= (op & UINT64_C(3)) << 6; 6805 Value |= (op & UINT64_C(992)) >> 5; 6806 break; 6807 } 6808 case ARM::t2SSAT16: 6809 case ARM::t2USAT16: { 6810 // op: Rd 6811 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6812 op &= UINT64_C(15); 6813 op <<= 8; 6814 Value |= op; 6815 // op: Rn 6816 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6817 op &= UINT64_C(15); 6818 op <<= 16; 6819 Value |= op; 6820 // op: sat_imm 6821 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6822 op &= UINT64_C(15); 6823 Value |= op; 6824 break; 6825 } 6826 case ARM::t2SSAT: 6827 case ARM::t2USAT: { 6828 // op: Rd 6829 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6830 op &= UINT64_C(15); 6831 op <<= 8; 6832 Value |= op; 6833 // op: Rn 6834 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6835 op &= UINT64_C(15); 6836 op <<= 16; 6837 Value |= op; 6838 // op: sat_imm 6839 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6840 op &= UINT64_C(31); 6841 Value |= op; 6842 // op: sh 6843 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6844 Value |= (op & UINT64_C(32)) << 16; 6845 Value |= (op & UINT64_C(28)) << 10; 6846 Value |= (op & UINT64_C(3)) << 6; 6847 break; 6848 } 6849 case ARM::t2PACG: { 6850 // op: Rd 6851 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6852 op &= UINT64_C(15); 6853 op <<= 8; 6854 Value |= op; 6855 // op: Rn 6856 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6857 op &= UINT64_C(15); 6858 op <<= 16; 6859 Value |= op; 6860 // op: Rm 6861 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 6862 op &= UINT64_C(15); 6863 Value |= op; 6864 break; 6865 } 6866 case ARM::t2STREX: { 6867 // op: Rd 6868 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6869 op &= UINT64_C(15); 6870 op <<= 8; 6871 Value |= op; 6872 // op: Rt 6873 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6874 op &= UINT64_C(15); 6875 op <<= 12; 6876 Value |= op; 6877 // op: addr 6878 op = getT2AddrModeImm0_1020s4OpValue(MI, 2, Fixups, STI); 6879 Value |= (op & UINT64_C(3840)) << 8; 6880 Value |= (op & UINT64_C(255)); 6881 break; 6882 } 6883 case ARM::t2MRS_M: { 6884 // op: Rd 6885 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6886 op &= UINT64_C(15); 6887 op <<= 8; 6888 Value |= op; 6889 // op: SYSm 6890 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6891 op &= UINT64_C(255); 6892 Value |= op; 6893 break; 6894 } 6895 case ARM::t2ADR: { 6896 // op: Rd 6897 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6898 op &= UINT64_C(15); 6899 op <<= 8; 6900 Value |= op; 6901 // op: addr 6902 op = getT2AdrLabelOpValue(MI, 1, Fixups, STI); 6903 Value |= (op & UINT64_C(2048)) << 15; 6904 Value |= (op & UINT64_C(4096)) << 11; 6905 Value |= (op & UINT64_C(4096)) << 9; 6906 Value |= (op & UINT64_C(1792)) << 4; 6907 Value |= (op & UINT64_C(255)); 6908 break; 6909 } 6910 case ARM::t2BFC: { 6911 // op: Rd 6912 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6913 op &= UINT64_C(15); 6914 op <<= 8; 6915 Value |= op; 6916 // op: imm 6917 op = getBitfieldInvertedMaskOpValue(MI, 2, Fixups, STI); 6918 Value |= (op & UINT64_C(28)) << 10; 6919 Value |= (op & UINT64_C(3)) << 6; 6920 Value |= (op & UINT64_C(992)) >> 5; 6921 break; 6922 } 6923 case ARM::t2MOVi16: { 6924 // op: Rd 6925 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6926 op &= UINT64_C(15); 6927 op <<= 8; 6928 Value |= op; 6929 // op: imm 6930 op = getHiLo16ImmOpValue(MI, 1, Fixups, STI); 6931 Value |= (op & UINT64_C(2048)) << 15; 6932 Value |= (op & UINT64_C(61440)) << 4; 6933 Value |= (op & UINT64_C(1792)) << 4; 6934 Value |= (op & UINT64_C(255)); 6935 break; 6936 } 6937 case ARM::t2MOVTi16: { 6938 // op: Rd 6939 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6940 op &= UINT64_C(15); 6941 op <<= 8; 6942 Value |= op; 6943 // op: imm 6944 op = getHiLo16ImmOpValue(MI, 2, Fixups, STI); 6945 Value |= (op & UINT64_C(2048)) << 15; 6946 Value |= (op & UINT64_C(61440)) << 4; 6947 Value |= (op & UINT64_C(1792)) << 4; 6948 Value |= (op & UINT64_C(255)); 6949 break; 6950 } 6951 case ARM::t2SBFX: 6952 case ARM::t2UBFX: { 6953 // op: Rd 6954 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6955 op &= UINT64_C(15); 6956 op <<= 8; 6957 Value |= op; 6958 // op: msb 6959 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6960 op &= UINT64_C(31); 6961 Value |= op; 6962 // op: lsb 6963 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6964 Value |= (op & UINT64_C(28)) << 10; 6965 Value |= (op & UINT64_C(3)) << 6; 6966 // op: Rn 6967 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6968 op &= UINT64_C(15); 6969 op <<= 16; 6970 Value |= op; 6971 break; 6972 } 6973 case ARM::tMOVSr: { 6974 // op: Rd 6975 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6976 op &= UINT64_C(7); 6977 Value |= op; 6978 // op: Rm 6979 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6980 op &= UINT64_C(7); 6981 op <<= 3; 6982 Value |= op; 6983 break; 6984 } 6985 case ARM::tADDi3: 6986 case ARM::tSUBi3: { 6987 // op: Rd 6988 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6989 op &= UINT64_C(7); 6990 Value |= op; 6991 // op: Rm 6992 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6993 op &= UINT64_C(7); 6994 op <<= 3; 6995 Value |= op; 6996 // op: imm3 6997 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6998 op &= UINT64_C(7); 6999 op <<= 6; 7000 Value |= op; 7001 break; 7002 } 7003 case ARM::tASRri: 7004 case ARM::tLSLri: 7005 case ARM::tLSRri: { 7006 // op: Rd 7007 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7008 op &= UINT64_C(7); 7009 Value |= op; 7010 // op: Rm 7011 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7012 op &= UINT64_C(7); 7013 op <<= 3; 7014 Value |= op; 7015 // op: imm5 7016 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7017 op &= UINT64_C(31); 7018 op <<= 6; 7019 Value |= op; 7020 break; 7021 } 7022 case ARM::tMUL: 7023 case ARM::tMVN: 7024 case ARM::tRSB: { 7025 // op: Rd 7026 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7027 op &= UINT64_C(7); 7028 Value |= op; 7029 // op: Rn 7030 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7031 op &= UINT64_C(7); 7032 op <<= 3; 7033 Value |= op; 7034 break; 7035 } 7036 case ARM::tADR: { 7037 // op: Rd 7038 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7039 op &= UINT64_C(7); 7040 op <<= 8; 7041 Value |= op; 7042 // op: addr 7043 op = getThumbAdrLabelOpValue(MI, 1, Fixups, STI); 7044 op &= UINT64_C(255); 7045 Value |= op; 7046 break; 7047 } 7048 case ARM::tMOVi8: { 7049 // op: Rd 7050 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7051 op &= UINT64_C(7); 7052 op <<= 8; 7053 Value |= op; 7054 // op: imm8 7055 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7056 op &= UINT64_C(255); 7057 Value |= op; 7058 break; 7059 } 7060 case ARM::t2SMLALD: 7061 case ARM::t2SMLALDX: 7062 case ARM::t2SMLSLD: 7063 case ARM::t2SMLSLDX: { 7064 // op: Rd 7065 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7066 op &= UINT64_C(15); 7067 op <<= 8; 7068 Value |= op; 7069 // op: Rn 7070 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7071 op &= UINT64_C(15); 7072 op <<= 16; 7073 Value |= op; 7074 // op: Rm 7075 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7076 op &= UINT64_C(15); 7077 Value |= op; 7078 // op: Ra 7079 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7080 op &= UINT64_C(15); 7081 op <<= 12; 7082 Value |= op; 7083 break; 7084 } 7085 case ARM::t2SMLAL: 7086 case ARM::t2SMLALBB: 7087 case ARM::t2SMLALBT: 7088 case ARM::t2SMLALTB: 7089 case ARM::t2SMLALTT: 7090 case ARM::t2SMULL: 7091 case ARM::t2UMAAL: 7092 case ARM::t2UMLAL: 7093 case ARM::t2UMULL: { 7094 // op: RdLo 7095 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7096 op &= UINT64_C(15); 7097 op <<= 12; 7098 Value |= op; 7099 // op: RdHi 7100 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7101 op &= UINT64_C(15); 7102 op <<= 8; 7103 Value |= op; 7104 // op: Rn 7105 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7106 op &= UINT64_C(15); 7107 op <<= 16; 7108 Value |= op; 7109 // op: Rm 7110 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7111 op &= UINT64_C(15); 7112 Value |= op; 7113 break; 7114 } 7115 case ARM::MVE_VMLADAVs16: 7116 case ARM::MVE_VMLADAVs32: 7117 case ARM::MVE_VMLADAVs8: 7118 case ARM::MVE_VMLADAVu16: 7119 case ARM::MVE_VMLADAVu32: 7120 case ARM::MVE_VMLADAVu8: 7121 case ARM::MVE_VMLADAVxs16: 7122 case ARM::MVE_VMLADAVxs32: 7123 case ARM::MVE_VMLADAVxs8: 7124 case ARM::MVE_VMLSDAVs16: 7125 case ARM::MVE_VMLSDAVs32: 7126 case ARM::MVE_VMLSDAVs8: 7127 case ARM::MVE_VMLSDAVxs16: 7128 case ARM::MVE_VMLSDAVxs32: 7129 case ARM::MVE_VMLSDAVxs8: { 7130 // op: RdaDest 7131 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7132 op &= UINT64_C(14); 7133 op <<= 12; 7134 Value |= op; 7135 // op: Qm 7136 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7137 op &= UINT64_C(7); 7138 op <<= 1; 7139 Value |= op; 7140 // op: Qn 7141 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7142 op &= UINT64_C(7); 7143 op <<= 17; 7144 Value |= op; 7145 break; 7146 } 7147 case ARM::MVE_VMLADAVas16: 7148 case ARM::MVE_VMLADAVas32: 7149 case ARM::MVE_VMLADAVas8: 7150 case ARM::MVE_VMLADAVau16: 7151 case ARM::MVE_VMLADAVau32: 7152 case ARM::MVE_VMLADAVau8: 7153 case ARM::MVE_VMLADAVaxs16: 7154 case ARM::MVE_VMLADAVaxs32: 7155 case ARM::MVE_VMLADAVaxs8: 7156 case ARM::MVE_VMLSDAVas16: 7157 case ARM::MVE_VMLSDAVas32: 7158 case ARM::MVE_VMLSDAVas8: 7159 case ARM::MVE_VMLSDAVaxs16: 7160 case ARM::MVE_VMLSDAVaxs32: 7161 case ARM::MVE_VMLSDAVaxs8: { 7162 // op: RdaDest 7163 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7164 op &= UINT64_C(14); 7165 op <<= 12; 7166 Value |= op; 7167 // op: Qm 7168 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7169 op &= UINT64_C(7); 7170 op <<= 1; 7171 Value |= op; 7172 // op: Qn 7173 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7174 op &= UINT64_C(7); 7175 op <<= 17; 7176 Value |= op; 7177 break; 7178 } 7179 case ARM::MVE_SQRSHR: 7180 case ARM::MVE_UQRSHL: { 7181 // op: RdaDest 7182 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7183 op &= UINT64_C(15); 7184 op <<= 16; 7185 Value |= op; 7186 // op: Rm 7187 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7188 op &= UINT64_C(15); 7189 op <<= 12; 7190 Value |= op; 7191 break; 7192 } 7193 case ARM::MVE_SQSHL: 7194 case ARM::MVE_SRSHR: 7195 case ARM::MVE_UQSHL: 7196 case ARM::MVE_URSHR: { 7197 // op: RdaDest 7198 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7199 op &= UINT64_C(15); 7200 op <<= 16; 7201 Value |= op; 7202 // op: imm 7203 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7204 Value |= (op & UINT64_C(28)) << 10; 7205 Value |= (op & UINT64_C(3)) << 6; 7206 break; 7207 } 7208 case ARM::MVE_ASRLr: 7209 case ARM::MVE_LSLLr: { 7210 // op: RdaLo 7211 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7212 op &= UINT64_C(14); 7213 op <<= 16; 7214 Value |= op; 7215 // op: RdaHi 7216 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7217 op &= UINT64_C(14); 7218 op <<= 8; 7219 Value |= op; 7220 // op: Rm 7221 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7222 op &= UINT64_C(15); 7223 op <<= 12; 7224 Value |= op; 7225 break; 7226 } 7227 case ARM::MVE_SQRSHRL: 7228 case ARM::MVE_UQRSHLL: { 7229 // op: RdaLo 7230 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7231 op &= UINT64_C(14); 7232 op <<= 16; 7233 Value |= op; 7234 // op: RdaHi 7235 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7236 op &= UINT64_C(14); 7237 op <<= 8; 7238 Value |= op; 7239 // op: Rm 7240 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7241 op &= UINT64_C(15); 7242 op <<= 12; 7243 Value |= op; 7244 // op: sat 7245 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7246 op &= UINT64_C(1); 7247 op <<= 7; 7248 Value |= op; 7249 break; 7250 } 7251 case ARM::MVE_ASRLi: 7252 case ARM::MVE_LSLLi: 7253 case ARM::MVE_LSRL: 7254 case ARM::MVE_SQSHLL: 7255 case ARM::MVE_SRSHRL: 7256 case ARM::MVE_UQSHLL: 7257 case ARM::MVE_URSHRL: { 7258 // op: RdaLo 7259 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7260 op &= UINT64_C(14); 7261 op <<= 16; 7262 Value |= op; 7263 // op: RdaHi 7264 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7265 op &= UINT64_C(14); 7266 op <<= 8; 7267 Value |= op; 7268 // op: imm 7269 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7270 Value |= (op & UINT64_C(28)) << 10; 7271 Value |= (op & UINT64_C(3)) << 6; 7272 break; 7273 } 7274 case ARM::MVE_VMLALDAVs16: 7275 case ARM::MVE_VMLALDAVs32: 7276 case ARM::MVE_VMLALDAVu16: 7277 case ARM::MVE_VMLALDAVu32: 7278 case ARM::MVE_VMLALDAVxs16: 7279 case ARM::MVE_VMLALDAVxs32: 7280 case ARM::MVE_VMLSLDAVs16: 7281 case ARM::MVE_VMLSLDAVs32: 7282 case ARM::MVE_VMLSLDAVxs16: 7283 case ARM::MVE_VMLSLDAVxs32: 7284 case ARM::MVE_VRMLALDAVHs32: 7285 case ARM::MVE_VRMLALDAVHu32: 7286 case ARM::MVE_VRMLALDAVHxs32: 7287 case ARM::MVE_VRMLSLDAVHs32: 7288 case ARM::MVE_VRMLSLDAVHxs32: { 7289 // op: RdaLoDest 7290 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7291 op &= UINT64_C(14); 7292 op <<= 12; 7293 Value |= op; 7294 // op: RdaHiDest 7295 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7296 op &= UINT64_C(14); 7297 op <<= 19; 7298 Value |= op; 7299 // op: Qm 7300 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7301 op &= UINT64_C(7); 7302 op <<= 1; 7303 Value |= op; 7304 // op: Qn 7305 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7306 op &= UINT64_C(7); 7307 op <<= 17; 7308 Value |= op; 7309 break; 7310 } 7311 case ARM::MVE_VMLALDAVas16: 7312 case ARM::MVE_VMLALDAVas32: 7313 case ARM::MVE_VMLALDAVau16: 7314 case ARM::MVE_VMLALDAVau32: 7315 case ARM::MVE_VMLALDAVaxs16: 7316 case ARM::MVE_VMLALDAVaxs32: 7317 case ARM::MVE_VMLSLDAVas16: 7318 case ARM::MVE_VMLSLDAVas32: 7319 case ARM::MVE_VMLSLDAVaxs16: 7320 case ARM::MVE_VMLSLDAVaxs32: 7321 case ARM::MVE_VRMLALDAVHas32: 7322 case ARM::MVE_VRMLALDAVHau32: 7323 case ARM::MVE_VRMLALDAVHaxs32: 7324 case ARM::MVE_VRMLSLDAVHas32: 7325 case ARM::MVE_VRMLSLDAVHaxs32: { 7326 // op: RdaLoDest 7327 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7328 op &= UINT64_C(14); 7329 op <<= 12; 7330 Value |= op; 7331 // op: RdaHiDest 7332 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7333 op &= UINT64_C(14); 7334 op <<= 19; 7335 Value |= op; 7336 // op: Qm 7337 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7338 op &= UINT64_C(7); 7339 op <<= 1; 7340 Value |= op; 7341 // op: Qn 7342 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7343 op &= UINT64_C(7); 7344 op <<= 17; 7345 Value |= op; 7346 break; 7347 } 7348 case ARM::tADDrSP: { 7349 // op: Rdn 7350 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7351 Value |= (op & UINT64_C(8)) << 4; 7352 Value |= (op & UINT64_C(7)); 7353 break; 7354 } 7355 case ARM::tADDhirr: { 7356 // op: Rdn 7357 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7358 Value |= (op & UINT64_C(8)) << 4; 7359 Value |= (op & UINT64_C(7)); 7360 // op: Rm 7361 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7362 op &= UINT64_C(15); 7363 op <<= 3; 7364 Value |= op; 7365 break; 7366 } 7367 case ARM::tADC: 7368 case ARM::tAND: 7369 case ARM::tASRrr: 7370 case ARM::tBIC: 7371 case ARM::tEOR: 7372 case ARM::tLSLrr: 7373 case ARM::tLSRrr: 7374 case ARM::tORR: 7375 case ARM::tROR: 7376 case ARM::tSBC: { 7377 // op: Rdn 7378 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7379 op &= UINT64_C(7); 7380 Value |= op; 7381 // op: Rm 7382 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7383 op &= UINT64_C(7); 7384 op <<= 3; 7385 Value |= op; 7386 break; 7387 } 7388 case ARM::tADDi8: 7389 case ARM::tSUBi8: { 7390 // op: Rdn 7391 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7392 op &= UINT64_C(7); 7393 op <<= 8; 7394 Value |= op; 7395 // op: imm8 7396 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7397 op &= UINT64_C(255); 7398 Value |= op; 7399 break; 7400 } 7401 case ARM::tBX: 7402 case ARM::tBXNS: { 7403 // op: Rm 7404 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7405 op &= UINT64_C(15); 7406 op <<= 3; 7407 Value |= op; 7408 break; 7409 } 7410 case ARM::tCMPhir: { 7411 // op: Rm 7412 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7413 op &= UINT64_C(15); 7414 op <<= 3; 7415 Value |= op; 7416 // op: Rn 7417 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7418 Value |= (op & UINT64_C(8)) << 4; 7419 Value |= (op & UINT64_C(7)); 7420 break; 7421 } 7422 case ARM::tREV: 7423 case ARM::tREV16: 7424 case ARM::tREVSH: 7425 case ARM::tSXTB: 7426 case ARM::tSXTH: 7427 case ARM::tUXTB: 7428 case ARM::tUXTH: { 7429 // op: Rm 7430 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7431 op &= UINT64_C(7); 7432 op <<= 3; 7433 Value |= op; 7434 // op: Rd 7435 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7436 op &= UINT64_C(7); 7437 Value |= op; 7438 break; 7439 } 7440 case ARM::tCMNz: 7441 case ARM::tCMPr: 7442 case ARM::tTST: { 7443 // op: Rm 7444 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7445 op &= UINT64_C(7); 7446 op <<= 3; 7447 Value |= op; 7448 // op: Rn 7449 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7450 op &= UINT64_C(7); 7451 Value |= op; 7452 break; 7453 } 7454 case ARM::tADDspr: { 7455 // op: Rm 7456 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7457 op &= UINT64_C(15); 7458 op <<= 3; 7459 Value |= op; 7460 break; 7461 } 7462 case ARM::tADDrr: 7463 case ARM::tSUBrr: { 7464 // op: Rm 7465 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7466 op &= UINT64_C(7); 7467 op <<= 6; 7468 Value |= op; 7469 // op: Rn 7470 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7471 op &= UINT64_C(7); 7472 op <<= 3; 7473 Value |= op; 7474 // op: Rd 7475 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7476 op &= UINT64_C(7); 7477 Value |= op; 7478 break; 7479 } 7480 case ARM::RFEDA: 7481 case ARM::RFEDA_UPD: 7482 case ARM::RFEDB: 7483 case ARM::RFEDB_UPD: 7484 case ARM::RFEIA: 7485 case ARM::RFEIA_UPD: 7486 case ARM::RFEIB: 7487 case ARM::RFEIB_UPD: 7488 case ARM::t2RFEDB: 7489 case ARM::t2RFEDBW: 7490 case ARM::t2RFEIA: 7491 case ARM::t2RFEIAW: { 7492 // op: Rn 7493 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7494 op &= UINT64_C(15); 7495 op <<= 16; 7496 Value |= op; 7497 break; 7498 } 7499 case ARM::t2CMNzrr: 7500 case ARM::t2CMPrr: 7501 case ARM::t2TBB: 7502 case ARM::t2TBH: 7503 case ARM::t2TEQrr: 7504 case ARM::t2TSTrr: { 7505 // op: Rn 7506 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7507 op &= UINT64_C(15); 7508 op <<= 16; 7509 Value |= op; 7510 // op: Rm 7511 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7512 op &= UINT64_C(15); 7513 Value |= op; 7514 break; 7515 } 7516 case ARM::t2CMNzrs: 7517 case ARM::t2CMPrs: 7518 case ARM::t2TEQrs: 7519 case ARM::t2TSTrs: { 7520 // op: Rn 7521 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7522 op &= UINT64_C(15); 7523 op <<= 16; 7524 Value |= op; 7525 // op: ShiftedRm 7526 op = getT2SORegOpValue(MI, 1, Fixups, STI); 7527 Value |= (op & UINT64_C(3584)) << 3; 7528 Value |= (op & UINT64_C(480)) >> 1; 7529 Value |= (op & UINT64_C(15)); 7530 break; 7531 } 7532 case ARM::t2CMNri: 7533 case ARM::t2CMPri: 7534 case ARM::t2TEQri: 7535 case ARM::t2TSTri: { 7536 // op: Rn 7537 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7538 op &= UINT64_C(15); 7539 op <<= 16; 7540 Value |= op; 7541 // op: imm 7542 op = getT2SOImmOpValue(MI, 1, Fixups, STI); 7543 Value |= (op & UINT64_C(2048)) << 15; 7544 Value |= (op & UINT64_C(1792)) << 4; 7545 Value |= (op & UINT64_C(255)); 7546 break; 7547 } 7548 case ARM::t2STMDB: 7549 case ARM::t2STMIA: { 7550 // op: Rn 7551 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7552 op &= UINT64_C(15); 7553 op <<= 16; 7554 Value |= op; 7555 // op: regs 7556 op = getRegisterListOpValue(MI, 3, Fixups, STI); 7557 Value |= (op & UINT64_C(16384)); 7558 Value |= (op & UINT64_C(8191)); 7559 break; 7560 } 7561 case ARM::t2LDMDB: 7562 case ARM::t2LDMIA: { 7563 // op: Rn 7564 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7565 op &= UINT64_C(15); 7566 op <<= 16; 7567 Value |= op; 7568 // op: regs 7569 op = getRegisterListOpValue(MI, 3, Fixups, STI); 7570 op &= UINT64_C(65535); 7571 Value |= op; 7572 break; 7573 } 7574 case ARM::tCMPi8: { 7575 // op: Rn 7576 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7577 op &= UINT64_C(7); 7578 op <<= 8; 7579 Value |= op; 7580 // op: imm8 7581 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7582 op &= UINT64_C(255); 7583 Value |= op; 7584 break; 7585 } 7586 case ARM::tLDMIA: { 7587 // op: Rn 7588 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7589 op &= UINT64_C(7); 7590 op <<= 8; 7591 Value |= op; 7592 // op: regs 7593 op = getRegisterListOpValue(MI, 3, Fixups, STI); 7594 op &= UINT64_C(255); 7595 Value |= op; 7596 break; 7597 } 7598 case ARM::MVE_DLSTP_16: 7599 case ARM::MVE_DLSTP_32: 7600 case ARM::MVE_DLSTP_64: 7601 case ARM::MVE_DLSTP_8: 7602 case ARM::MVE_VCTP16: 7603 case ARM::MVE_VCTP32: 7604 case ARM::MVE_VCTP64: 7605 case ARM::MVE_VCTP8: 7606 case ARM::t2DLS: { 7607 // op: Rn 7608 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7609 op &= UINT64_C(15); 7610 op <<= 16; 7611 Value |= op; 7612 break; 7613 } 7614 case ARM::t2TT: 7615 case ARM::t2TTA: 7616 case ARM::t2TTAT: 7617 case ARM::t2TTT: { 7618 // op: Rn 7619 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7620 op &= UINT64_C(15); 7621 op <<= 16; 7622 Value |= op; 7623 // op: Rt 7624 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7625 op &= UINT64_C(15); 7626 op <<= 8; 7627 Value |= op; 7628 break; 7629 } 7630 case ARM::MVE_WLSTP_16: 7631 case ARM::MVE_WLSTP_32: 7632 case ARM::MVE_WLSTP_64: 7633 case ARM::MVE_WLSTP_8: 7634 case ARM::t2WLS: { 7635 // op: Rn 7636 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7637 op &= UINT64_C(15); 7638 op <<= 16; 7639 Value |= op; 7640 // op: label 7641 op = getBFTargetOpValue<false, ARM::fixup_wls>(MI, 2, Fixups, STI); 7642 Value |= (op & UINT64_C(1)) << 11; 7643 Value |= (op & UINT64_C(2046)); 7644 break; 7645 } 7646 case ARM::t2STMDB_UPD: 7647 case ARM::t2STMIA_UPD: { 7648 // op: Rn 7649 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7650 op &= UINT64_C(15); 7651 op <<= 16; 7652 Value |= op; 7653 // op: regs 7654 op = getRegisterListOpValue(MI, 4, Fixups, STI); 7655 Value |= (op & UINT64_C(16384)); 7656 Value |= (op & UINT64_C(8191)); 7657 break; 7658 } 7659 case ARM::t2LDMDB_UPD: 7660 case ARM::t2LDMIA_UPD: { 7661 // op: Rn 7662 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7663 op &= UINT64_C(15); 7664 op <<= 16; 7665 Value |= op; 7666 // op: regs 7667 op = getRegisterListOpValue(MI, 4, Fixups, STI); 7668 op &= UINT64_C(65535); 7669 Value |= op; 7670 break; 7671 } 7672 case ARM::tSTMIA_UPD: { 7673 // op: Rn 7674 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7675 op &= UINT64_C(7); 7676 op <<= 8; 7677 Value |= op; 7678 // op: regs 7679 op = getRegisterListOpValue(MI, 4, Fixups, STI); 7680 op &= UINT64_C(255); 7681 Value |= op; 7682 break; 7683 } 7684 case ARM::MVE_VMOV_rr_q: { 7685 // op: Rt 7686 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7687 op &= UINT64_C(15); 7688 Value |= op; 7689 // op: Rt2 7690 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7691 op &= UINT64_C(15); 7692 op <<= 16; 7693 Value |= op; 7694 // op: Qd 7695 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7696 Value |= (op & UINT64_C(8)) << 19; 7697 Value |= (op & UINT64_C(7)) << 13; 7698 // op: idx2 7699 op = getMVEPairVectorIndexOpValue<0>(MI, 4, Fixups, STI); 7700 op &= UINT64_C(1); 7701 op <<= 4; 7702 Value |= op; 7703 break; 7704 } 7705 case ARM::t2LDRB_POST: 7706 case ARM::t2LDRH_POST: 7707 case ARM::t2LDRSB_POST: 7708 case ARM::t2LDRSH_POST: 7709 case ARM::t2LDR_POST: { 7710 // op: Rt 7711 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7712 op &= UINT64_C(15); 7713 op <<= 12; 7714 Value |= op; 7715 // op: Rn 7716 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7717 op &= UINT64_C(15); 7718 op <<= 16; 7719 Value |= op; 7720 // op: offset 7721 op = getT2AddrModeImm8OffsetOpValue(MI, 3, Fixups, STI); 7722 Value |= (op & UINT64_C(256)) << 1; 7723 Value |= (op & UINT64_C(255)); 7724 break; 7725 } 7726 case ARM::MRRC2: 7727 case ARM::t2MRRC: 7728 case ARM::t2MRRC2: { 7729 // op: Rt 7730 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7731 op &= UINT64_C(15); 7732 op <<= 12; 7733 Value |= op; 7734 // op: Rt2 7735 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7736 op &= UINT64_C(15); 7737 op <<= 16; 7738 Value |= op; 7739 // op: cop 7740 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7741 op &= UINT64_C(15); 7742 op <<= 8; 7743 Value |= op; 7744 // op: opc1 7745 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7746 op &= UINT64_C(15); 7747 op <<= 4; 7748 Value |= op; 7749 // op: CRm 7750 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7751 op &= UINT64_C(15); 7752 Value |= op; 7753 break; 7754 } 7755 case ARM::t2LDRD_POST: { 7756 // op: Rt 7757 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7758 op &= UINT64_C(15); 7759 op <<= 12; 7760 Value |= op; 7761 // op: Rt2 7762 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7763 op &= UINT64_C(15); 7764 op <<= 8; 7765 Value |= op; 7766 // op: addr 7767 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7768 op &= UINT64_C(15); 7769 op <<= 16; 7770 Value |= op; 7771 // op: imm 7772 op = getT2ScaledImmOpValue<8,2>(MI, 4, Fixups, STI); 7773 Value |= (op & UINT64_C(256)) << 15; 7774 Value |= (op & UINT64_C(255)); 7775 break; 7776 } 7777 case ARM::t2LDRDi8: 7778 case ARM::t2STRDi8: { 7779 // op: Rt 7780 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7781 op &= UINT64_C(15); 7782 op <<= 12; 7783 Value |= op; 7784 // op: Rt2 7785 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7786 op &= UINT64_C(15); 7787 op <<= 8; 7788 Value |= op; 7789 // op: addr 7790 op = getT2AddrModeImm8s4OpValue(MI, 2, Fixups, STI); 7791 Value |= (op & UINT64_C(256)) << 15; 7792 Value |= (op & UINT64_C(7680)) << 7; 7793 Value |= (op & UINT64_C(255)); 7794 break; 7795 } 7796 case ARM::t2LDRD_PRE: { 7797 // op: Rt 7798 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7799 op &= UINT64_C(15); 7800 op <<= 12; 7801 Value |= op; 7802 // op: Rt2 7803 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7804 op &= UINT64_C(15); 7805 op <<= 8; 7806 Value |= op; 7807 // op: addr 7808 op = getT2AddrModeImm8s4OpValue(MI, 3, Fixups, STI); 7809 Value |= (op & UINT64_C(256)) << 15; 7810 Value |= (op & UINT64_C(7680)) << 7; 7811 Value |= (op & UINT64_C(255)); 7812 break; 7813 } 7814 case ARM::t2LDRBi12: 7815 case ARM::t2LDRHi12: 7816 case ARM::t2LDRSBi12: 7817 case ARM::t2LDRSHi12: 7818 case ARM::t2LDRi12: 7819 case ARM::t2STRBi12: 7820 case ARM::t2STRHi12: 7821 case ARM::t2STRi12: { 7822 // op: Rt 7823 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7824 op &= UINT64_C(15); 7825 op <<= 12; 7826 Value |= op; 7827 // op: addr 7828 op = getAddrModeImm12OpValue(MI, 1, Fixups, STI); 7829 Value |= (op & UINT64_C(122880)) << 3; 7830 Value |= (op & UINT64_C(4095)); 7831 break; 7832 } 7833 case ARM::t2LDRBpci: 7834 case ARM::t2LDRHpci: 7835 case ARM::t2LDRSBpci: 7836 case ARM::t2LDRSHpci: 7837 case ARM::t2LDRpci: { 7838 // op: Rt 7839 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7840 op &= UINT64_C(15); 7841 op <<= 12; 7842 Value |= op; 7843 // op: addr 7844 op = getAddrModeImm12OpValue(MI, 1, Fixups, STI); 7845 Value |= (op & UINT64_C(4096)) << 11; 7846 Value |= (op & UINT64_C(4095)); 7847 break; 7848 } 7849 case ARM::t2LDA: 7850 case ARM::t2LDAB: 7851 case ARM::t2LDAEX: 7852 case ARM::t2LDAH: 7853 case ARM::t2STL: 7854 case ARM::t2STLB: 7855 case ARM::t2STLH: { 7856 // op: Rt 7857 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7858 op &= UINT64_C(15); 7859 op <<= 12; 7860 Value |= op; 7861 // op: addr 7862 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7863 op &= UINT64_C(15); 7864 op <<= 16; 7865 Value |= op; 7866 break; 7867 } 7868 case ARM::t2LDREX: { 7869 // op: Rt 7870 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7871 op &= UINT64_C(15); 7872 op <<= 12; 7873 Value |= op; 7874 // op: addr 7875 op = getT2AddrModeImm0_1020s4OpValue(MI, 1, Fixups, STI); 7876 Value |= (op & UINT64_C(3840)) << 8; 7877 Value |= (op & UINT64_C(255)); 7878 break; 7879 } 7880 case ARM::t2LDRBT: 7881 case ARM::t2LDRHT: 7882 case ARM::t2LDRSBT: 7883 case ARM::t2LDRSHT: 7884 case ARM::t2LDRT: 7885 case ARM::t2STRBT: 7886 case ARM::t2STRHT: 7887 case ARM::t2STRT: { 7888 // op: Rt 7889 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7890 op &= UINT64_C(15); 7891 op <<= 12; 7892 Value |= op; 7893 // op: addr 7894 op = getT2AddrModeImmOpValue<8,0>(MI, 1, Fixups, STI); 7895 Value |= (op & UINT64_C(7680)) << 7; 7896 Value |= (op & UINT64_C(255)); 7897 break; 7898 } 7899 case ARM::t2LDRBi8: 7900 case ARM::t2LDRHi8: 7901 case ARM::t2LDRSBi8: 7902 case ARM::t2LDRSHi8: 7903 case ARM::t2LDRi8: 7904 case ARM::t2STRBi8: 7905 case ARM::t2STRHi8: 7906 case ARM::t2STRi8: { 7907 // op: Rt 7908 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7909 op &= UINT64_C(15); 7910 op <<= 12; 7911 Value |= op; 7912 // op: addr 7913 op = getT2AddrModeImmOpValue<8,0>(MI, 1, Fixups, STI); 7914 Value |= (op & UINT64_C(7680)) << 7; 7915 Value |= (op & UINT64_C(256)) << 1; 7916 Value |= (op & UINT64_C(255)); 7917 break; 7918 } 7919 case ARM::t2LDRB_PRE: 7920 case ARM::t2LDRH_PRE: 7921 case ARM::t2LDRSB_PRE: 7922 case ARM::t2LDRSH_PRE: 7923 case ARM::t2LDR_PRE: { 7924 // op: Rt 7925 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7926 op &= UINT64_C(15); 7927 op <<= 12; 7928 Value |= op; 7929 // op: addr 7930 op = getT2AddrModeImmOpValue<8,0>(MI, 2, Fixups, STI); 7931 Value |= (op & UINT64_C(7680)) << 7; 7932 Value |= (op & UINT64_C(256)) << 1; 7933 Value |= (op & UINT64_C(255)); 7934 break; 7935 } 7936 case ARM::t2LDRBs: 7937 case ARM::t2LDRHs: 7938 case ARM::t2LDRSBs: 7939 case ARM::t2LDRSHs: 7940 case ARM::t2LDRs: 7941 case ARM::t2STRBs: 7942 case ARM::t2STRHs: 7943 case ARM::t2STRs: { 7944 // op: Rt 7945 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7946 op &= UINT64_C(15); 7947 op <<= 12; 7948 Value |= op; 7949 // op: addr 7950 op = getT2AddrModeSORegOpValue(MI, 1, Fixups, STI); 7951 Value |= (op & UINT64_C(960)) << 10; 7952 Value |= (op & UINT64_C(3)) << 4; 7953 Value |= (op & UINT64_C(60)) >> 2; 7954 break; 7955 } 7956 case ARM::MRC2: 7957 case ARM::t2MRC: 7958 case ARM::t2MRC2: { 7959 // op: Rt 7960 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7961 op &= UINT64_C(15); 7962 op <<= 12; 7963 Value |= op; 7964 // op: cop 7965 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7966 op &= UINT64_C(15); 7967 op <<= 8; 7968 Value |= op; 7969 // op: opc1 7970 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7971 op &= UINT64_C(7); 7972 op <<= 21; 7973 Value |= op; 7974 // op: opc2 7975 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7976 op &= UINT64_C(7); 7977 op <<= 5; 7978 Value |= op; 7979 // op: CRm 7980 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7981 op &= UINT64_C(15); 7982 Value |= op; 7983 // op: CRn 7984 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7985 op &= UINT64_C(15); 7986 op <<= 16; 7987 Value |= op; 7988 break; 7989 } 7990 case ARM::tLDRBi: 7991 case ARM::tLDRHi: 7992 case ARM::tLDRi: 7993 case ARM::tSTRBi: 7994 case ARM::tSTRHi: 7995 case ARM::tSTRi: { 7996 // op: Rt 7997 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7998 op &= UINT64_C(7); 7999 Value |= op; 8000 // op: addr 8001 op = getAddrModeISOpValue(MI, 1, Fixups, STI); 8002 op &= UINT64_C(255); 8003 op <<= 3; 8004 Value |= op; 8005 break; 8006 } 8007 case ARM::tLDRBr: 8008 case ARM::tLDRHr: 8009 case ARM::tLDRSB: 8010 case ARM::tLDRSH: 8011 case ARM::tLDRr: 8012 case ARM::tSTRBr: 8013 case ARM::tSTRHr: 8014 case ARM::tSTRr: { 8015 // op: Rt 8016 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8017 op &= UINT64_C(7); 8018 Value |= op; 8019 // op: addr 8020 op = getThumbAddrModeRegRegOpValue(MI, 1, Fixups, STI); 8021 op &= UINT64_C(63); 8022 op <<= 3; 8023 Value |= op; 8024 break; 8025 } 8026 case ARM::tLDRpci: { 8027 // op: Rt 8028 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8029 op &= UINT64_C(7); 8030 op <<= 8; 8031 Value |= op; 8032 // op: addr 8033 op = getAddrModePCOpValue(MI, 1, Fixups, STI); 8034 op &= UINT64_C(255); 8035 Value |= op; 8036 break; 8037 } 8038 case ARM::tLDRspi: 8039 case ARM::tSTRspi: { 8040 // op: Rt 8041 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8042 op &= UINT64_C(7); 8043 op <<= 8; 8044 Value |= op; 8045 // op: addr 8046 op = getAddrModeThumbSPOpValue(MI, 1, Fixups, STI); 8047 op &= UINT64_C(255); 8048 Value |= op; 8049 break; 8050 } 8051 case ARM::t2STRB_POST: 8052 case ARM::t2STRH_POST: 8053 case ARM::t2STR_POST: { 8054 // op: Rt 8055 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8056 op &= UINT64_C(15); 8057 op <<= 12; 8058 Value |= op; 8059 // op: Rn 8060 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8061 op &= UINT64_C(15); 8062 op <<= 16; 8063 Value |= op; 8064 // op: offset 8065 op = getT2AddrModeImm8OffsetOpValue(MI, 3, Fixups, STI); 8066 Value |= (op & UINT64_C(256)) << 1; 8067 Value |= (op & UINT64_C(255)); 8068 break; 8069 } 8070 case ARM::t2STRD_POST: { 8071 // op: Rt 8072 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8073 op &= UINT64_C(15); 8074 op <<= 12; 8075 Value |= op; 8076 // op: Rt2 8077 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8078 op &= UINT64_C(15); 8079 op <<= 8; 8080 Value |= op; 8081 // op: addr 8082 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8083 op &= UINT64_C(15); 8084 op <<= 16; 8085 Value |= op; 8086 // op: imm 8087 op = getT2ScaledImmOpValue<8,2>(MI, 4, Fixups, STI); 8088 Value |= (op & UINT64_C(256)) << 15; 8089 Value |= (op & UINT64_C(255)); 8090 break; 8091 } 8092 case ARM::t2STRD_PRE: { 8093 // op: Rt 8094 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8095 op &= UINT64_C(15); 8096 op <<= 12; 8097 Value |= op; 8098 // op: Rt2 8099 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8100 op &= UINT64_C(15); 8101 op <<= 8; 8102 Value |= op; 8103 // op: addr 8104 op = getT2AddrModeImm8s4OpValue(MI, 3, Fixups, STI); 8105 Value |= (op & UINT64_C(256)) << 15; 8106 Value |= (op & UINT64_C(7680)) << 7; 8107 Value |= (op & UINT64_C(255)); 8108 break; 8109 } 8110 case ARM::t2STRB_PRE: 8111 case ARM::t2STRH_PRE: 8112 case ARM::t2STR_PRE: { 8113 // op: Rt 8114 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8115 op &= UINT64_C(15); 8116 op <<= 12; 8117 Value |= op; 8118 // op: addr 8119 op = getT2AddrModeImmOpValue<8,0>(MI, 2, Fixups, STI); 8120 Value |= (op & UINT64_C(7680)) << 7; 8121 Value |= (op & UINT64_C(256)) << 1; 8122 Value |= (op & UINT64_C(255)); 8123 break; 8124 } 8125 case ARM::MVE_VMOV_q_rr: { 8126 // op: Rt 8127 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8128 op &= UINT64_C(15); 8129 Value |= op; 8130 // op: Rt2 8131 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8132 op &= UINT64_C(15); 8133 op <<= 16; 8134 Value |= op; 8135 // op: Qd 8136 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8137 Value |= (op & UINT64_C(8)) << 19; 8138 Value |= (op & UINT64_C(7)) << 13; 8139 // op: idx2 8140 op = getMVEPairVectorIndexOpValue<0>(MI, 5, Fixups, STI); 8141 op &= UINT64_C(1); 8142 op <<= 4; 8143 Value |= op; 8144 break; 8145 } 8146 case ARM::MCRR2: 8147 case ARM::t2MCRR: 8148 case ARM::t2MCRR2: { 8149 // op: Rt 8150 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8151 op &= UINT64_C(15); 8152 op <<= 12; 8153 Value |= op; 8154 // op: Rt2 8155 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8156 op &= UINT64_C(15); 8157 op <<= 16; 8158 Value |= op; 8159 // op: cop 8160 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8161 op &= UINT64_C(15); 8162 op <<= 8; 8163 Value |= op; 8164 // op: opc1 8165 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8166 op &= UINT64_C(15); 8167 op <<= 4; 8168 Value |= op; 8169 // op: CRm 8170 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 8171 op &= UINT64_C(15); 8172 Value |= op; 8173 break; 8174 } 8175 case ARM::MCR2: 8176 case ARM::t2MCR: 8177 case ARM::t2MCR2: { 8178 // op: Rt 8179 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8180 op &= UINT64_C(15); 8181 op <<= 12; 8182 Value |= op; 8183 // op: cop 8184 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8185 op &= UINT64_C(15); 8186 op <<= 8; 8187 Value |= op; 8188 // op: opc1 8189 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8190 op &= UINT64_C(7); 8191 op <<= 21; 8192 Value |= op; 8193 // op: opc2 8194 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 8195 op &= UINT64_C(7); 8196 op <<= 5; 8197 Value |= op; 8198 // op: CRm 8199 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 8200 op &= UINT64_C(15); 8201 Value |= op; 8202 // op: CRn 8203 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8204 op &= UINT64_C(15); 8205 op <<= 16; 8206 Value |= op; 8207 break; 8208 } 8209 case ARM::t2MSR_M: { 8210 // op: SYSm 8211 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8212 Value |= (op & UINT64_C(3072)); 8213 Value |= (op & UINT64_C(255)); 8214 // op: Rn 8215 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8216 op &= UINT64_C(15); 8217 op <<= 16; 8218 Value |= op; 8219 break; 8220 } 8221 case ARM::VCVTASD: 8222 case ARM::VCVTAUD: 8223 case ARM::VCVTMSD: 8224 case ARM::VCVTMUD: 8225 case ARM::VCVTNSD: 8226 case ARM::VCVTNUD: 8227 case ARM::VCVTPSD: 8228 case ARM::VCVTPUD: { 8229 // op: Sd 8230 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8231 Value |= (op & UINT64_C(1)) << 22; 8232 Value |= (op & UINT64_C(30)) << 11; 8233 // op: Dm 8234 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8235 Value |= (op & UINT64_C(16)) << 1; 8236 Value |= (op & UINT64_C(15)); 8237 break; 8238 } 8239 case ARM::VCVTASH: 8240 case ARM::VCVTASS: 8241 case ARM::VCVTAUH: 8242 case ARM::VCVTAUS: 8243 case ARM::VCVTMSH: 8244 case ARM::VCVTMSS: 8245 case ARM::VCVTMUH: 8246 case ARM::VCVTMUS: 8247 case ARM::VCVTNSH: 8248 case ARM::VCVTNSS: 8249 case ARM::VCVTNUH: 8250 case ARM::VCVTNUS: 8251 case ARM::VCVTPSH: 8252 case ARM::VCVTPSS: 8253 case ARM::VCVTPUH: 8254 case ARM::VCVTPUS: 8255 case ARM::VMOVH: 8256 case ARM::VRINTAH: 8257 case ARM::VRINTAS: 8258 case ARM::VRINTMH: 8259 case ARM::VRINTMS: 8260 case ARM::VRINTNH: 8261 case ARM::VRINTNS: 8262 case ARM::VRINTPH: 8263 case ARM::VRINTPS: { 8264 // op: Sd 8265 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8266 Value |= (op & UINT64_C(1)) << 22; 8267 Value |= (op & UINT64_C(30)) << 11; 8268 // op: Sm 8269 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8270 Value |= (op & UINT64_C(1)) << 5; 8271 Value |= (op & UINT64_C(30)) >> 1; 8272 break; 8273 } 8274 case ARM::VINSH: { 8275 // op: Sd 8276 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8277 Value |= (op & UINT64_C(1)) << 22; 8278 Value |= (op & UINT64_C(30)) << 11; 8279 // op: Sm 8280 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8281 Value |= (op & UINT64_C(1)) << 5; 8282 Value |= (op & UINT64_C(30)) >> 1; 8283 break; 8284 } 8285 case ARM::VFP_VMAXNMH: 8286 case ARM::VFP_VMAXNMS: 8287 case ARM::VFP_VMINNMH: 8288 case ARM::VFP_VMINNMS: 8289 case ARM::VSELEQH: 8290 case ARM::VSELEQS: 8291 case ARM::VSELGEH: 8292 case ARM::VSELGES: 8293 case ARM::VSELGTH: 8294 case ARM::VSELGTS: 8295 case ARM::VSELVSH: 8296 case ARM::VSELVSS: { 8297 // op: Sd 8298 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8299 Value |= (op & UINT64_C(1)) << 22; 8300 Value |= (op & UINT64_C(30)) << 11; 8301 // op: Sn 8302 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8303 Value |= (op & UINT64_C(30)) << 15; 8304 Value |= (op & UINT64_C(1)) << 7; 8305 // op: Sm 8306 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8307 Value |= (op & UINT64_C(1)) << 5; 8308 Value |= (op & UINT64_C(30)) >> 1; 8309 break; 8310 } 8311 case ARM::VDUP16d: 8312 case ARM::VDUP16q: 8313 case ARM::VDUP32d: 8314 case ARM::VDUP32q: 8315 case ARM::VDUP8d: 8316 case ARM::VDUP8q: { 8317 // op: V 8318 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8319 Value |= (op & UINT64_C(15)) << 16; 8320 Value |= (op & UINT64_C(16)) << 3; 8321 // op: R 8322 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8323 op &= UINT64_C(15); 8324 op <<= 12; 8325 Value |= op; 8326 // op: p 8327 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8328 op &= UINT64_C(15); 8329 op <<= 28; 8330 Value |= op; 8331 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 8332 break; 8333 } 8334 case ARM::VSETLNi16: { 8335 // op: V 8336 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8337 Value |= (op & UINT64_C(15)) << 16; 8338 Value |= (op & UINT64_C(16)) << 3; 8339 // op: R 8340 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8341 op &= UINT64_C(15); 8342 op <<= 12; 8343 Value |= op; 8344 // op: p 8345 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 8346 op &= UINT64_C(15); 8347 op <<= 28; 8348 Value |= op; 8349 // op: lane 8350 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8351 Value |= (op & UINT64_C(2)) << 20; 8352 Value |= (op & UINT64_C(1)) << 6; 8353 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 8354 break; 8355 } 8356 case ARM::VSETLNi8: { 8357 // op: V 8358 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8359 Value |= (op & UINT64_C(15)) << 16; 8360 Value |= (op & UINT64_C(16)) << 3; 8361 // op: R 8362 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8363 op &= UINT64_C(15); 8364 op <<= 12; 8365 Value |= op; 8366 // op: p 8367 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 8368 op &= UINT64_C(15); 8369 op <<= 28; 8370 Value |= op; 8371 // op: lane 8372 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8373 Value |= (op & UINT64_C(4)) << 19; 8374 Value |= (op & UINT64_C(3)) << 5; 8375 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 8376 break; 8377 } 8378 case ARM::VSETLNi32: { 8379 // op: V 8380 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8381 Value |= (op & UINT64_C(15)) << 16; 8382 Value |= (op & UINT64_C(16)) << 3; 8383 // op: R 8384 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8385 op &= UINT64_C(15); 8386 op <<= 12; 8387 Value |= op; 8388 // op: p 8389 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 8390 op &= UINT64_C(15); 8391 op <<= 28; 8392 Value |= op; 8393 // op: lane 8394 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8395 op &= UINT64_C(1); 8396 op <<= 21; 8397 Value |= op; 8398 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 8399 break; 8400 } 8401 case ARM::VGETLNs16: 8402 case ARM::VGETLNu16: { 8403 // op: V 8404 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8405 Value |= (op & UINT64_C(15)) << 16; 8406 Value |= (op & UINT64_C(16)) << 3; 8407 // op: R 8408 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8409 op &= UINT64_C(15); 8410 op <<= 12; 8411 Value |= op; 8412 // op: p 8413 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8414 op &= UINT64_C(15); 8415 op <<= 28; 8416 Value |= op; 8417 // op: lane 8418 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8419 Value |= (op & UINT64_C(2)) << 20; 8420 Value |= (op & UINT64_C(1)) << 6; 8421 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 8422 break; 8423 } 8424 case ARM::VGETLNs8: 8425 case ARM::VGETLNu8: { 8426 // op: V 8427 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8428 Value |= (op & UINT64_C(15)) << 16; 8429 Value |= (op & UINT64_C(16)) << 3; 8430 // op: R 8431 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8432 op &= UINT64_C(15); 8433 op <<= 12; 8434 Value |= op; 8435 // op: p 8436 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8437 op &= UINT64_C(15); 8438 op <<= 28; 8439 Value |= op; 8440 // op: lane 8441 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8442 Value |= (op & UINT64_C(4)) << 19; 8443 Value |= (op & UINT64_C(3)) << 5; 8444 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 8445 break; 8446 } 8447 case ARM::VGETLNi32: { 8448 // op: V 8449 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8450 Value |= (op & UINT64_C(15)) << 16; 8451 Value |= (op & UINT64_C(16)) << 3; 8452 // op: R 8453 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8454 op &= UINT64_C(15); 8455 op <<= 12; 8456 Value |= op; 8457 // op: p 8458 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8459 op &= UINT64_C(15); 8460 op <<= 28; 8461 Value |= op; 8462 // op: lane 8463 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8464 op &= UINT64_C(1); 8465 op <<= 21; 8466 Value |= op; 8467 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 8468 break; 8469 } 8470 case ARM::MVE_VST20_16: 8471 case ARM::MVE_VST20_32: 8472 case ARM::MVE_VST20_8: 8473 case ARM::MVE_VST21_16: 8474 case ARM::MVE_VST21_32: 8475 case ARM::MVE_VST21_8: 8476 case ARM::MVE_VST40_16: 8477 case ARM::MVE_VST40_32: 8478 case ARM::MVE_VST40_8: 8479 case ARM::MVE_VST41_16: 8480 case ARM::MVE_VST41_32: 8481 case ARM::MVE_VST41_8: 8482 case ARM::MVE_VST42_16: 8483 case ARM::MVE_VST42_32: 8484 case ARM::MVE_VST42_8: 8485 case ARM::MVE_VST43_16: 8486 case ARM::MVE_VST43_32: 8487 case ARM::MVE_VST43_8: { 8488 // op: VQd 8489 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8490 op &= UINT64_C(7); 8491 op <<= 13; 8492 Value |= op; 8493 // op: Rn 8494 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8495 op &= UINT64_C(15); 8496 op <<= 16; 8497 Value |= op; 8498 break; 8499 } 8500 case ARM::MVE_VLD20_16: 8501 case ARM::MVE_VLD20_32: 8502 case ARM::MVE_VLD20_8: 8503 case ARM::MVE_VLD21_16: 8504 case ARM::MVE_VLD21_32: 8505 case ARM::MVE_VLD21_8: 8506 case ARM::MVE_VLD40_16: 8507 case ARM::MVE_VLD40_32: 8508 case ARM::MVE_VLD40_8: 8509 case ARM::MVE_VLD41_16: 8510 case ARM::MVE_VLD41_32: 8511 case ARM::MVE_VLD41_8: 8512 case ARM::MVE_VLD42_16: 8513 case ARM::MVE_VLD42_32: 8514 case ARM::MVE_VLD42_8: 8515 case ARM::MVE_VLD43_16: 8516 case ARM::MVE_VLD43_32: 8517 case ARM::MVE_VLD43_8: { 8518 // op: VQd 8519 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8520 op &= UINT64_C(7); 8521 op <<= 13; 8522 Value |= op; 8523 // op: Rn 8524 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8525 op &= UINT64_C(15); 8526 op <<= 16; 8527 Value |= op; 8528 break; 8529 } 8530 case ARM::MVE_VLD20_16_wb: 8531 case ARM::MVE_VLD20_32_wb: 8532 case ARM::MVE_VLD20_8_wb: 8533 case ARM::MVE_VLD21_16_wb: 8534 case ARM::MVE_VLD21_32_wb: 8535 case ARM::MVE_VLD21_8_wb: 8536 case ARM::MVE_VLD40_16_wb: 8537 case ARM::MVE_VLD40_32_wb: 8538 case ARM::MVE_VLD40_8_wb: 8539 case ARM::MVE_VLD41_16_wb: 8540 case ARM::MVE_VLD41_32_wb: 8541 case ARM::MVE_VLD41_8_wb: 8542 case ARM::MVE_VLD42_16_wb: 8543 case ARM::MVE_VLD42_32_wb: 8544 case ARM::MVE_VLD42_8_wb: 8545 case ARM::MVE_VLD43_16_wb: 8546 case ARM::MVE_VLD43_32_wb: 8547 case ARM::MVE_VLD43_8_wb: { 8548 // op: VQd 8549 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8550 op &= UINT64_C(7); 8551 op <<= 13; 8552 Value |= op; 8553 // op: Rn 8554 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8555 op &= UINT64_C(15); 8556 op <<= 16; 8557 Value |= op; 8558 break; 8559 } 8560 case ARM::MVE_VST20_16_wb: 8561 case ARM::MVE_VST20_32_wb: 8562 case ARM::MVE_VST20_8_wb: 8563 case ARM::MVE_VST21_16_wb: 8564 case ARM::MVE_VST21_32_wb: 8565 case ARM::MVE_VST21_8_wb: 8566 case ARM::MVE_VST40_16_wb: 8567 case ARM::MVE_VST40_32_wb: 8568 case ARM::MVE_VST40_8_wb: 8569 case ARM::MVE_VST41_16_wb: 8570 case ARM::MVE_VST41_32_wb: 8571 case ARM::MVE_VST41_8_wb: 8572 case ARM::MVE_VST42_16_wb: 8573 case ARM::MVE_VST42_32_wb: 8574 case ARM::MVE_VST42_8_wb: 8575 case ARM::MVE_VST43_16_wb: 8576 case ARM::MVE_VST43_32_wb: 8577 case ARM::MVE_VST43_8_wb: { 8578 // op: VQd 8579 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8580 op &= UINT64_C(7); 8581 op <<= 13; 8582 Value |= op; 8583 // op: Rn 8584 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8585 op &= UINT64_C(15); 8586 op <<= 16; 8587 Value |= op; 8588 break; 8589 } 8590 case ARM::VLD1d16: 8591 case ARM::VLD1d16T: 8592 case ARM::VLD1d32: 8593 case ARM::VLD1d32T: 8594 case ARM::VLD1d64: 8595 case ARM::VLD1d64T: 8596 case ARM::VLD1d8: 8597 case ARM::VLD1d8T: { 8598 // op: Vd 8599 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8600 Value |= (op & UINT64_C(16)) << 18; 8601 Value |= (op & UINT64_C(15)) << 12; 8602 // op: Rn 8603 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 8604 Value |= (op & UINT64_C(15)) << 16; 8605 Value |= (op & UINT64_C(16)); 8606 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8607 break; 8608 } 8609 case ARM::VLD1LNd16: { 8610 // op: Vd 8611 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8612 Value |= (op & UINT64_C(16)) << 18; 8613 Value |= (op & UINT64_C(15)) << 12; 8614 // op: Rn 8615 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 8616 Value |= (op & UINT64_C(15)) << 16; 8617 Value |= (op & UINT64_C(48)); 8618 // op: lane 8619 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 8620 op &= UINT64_C(3); 8621 op <<= 6; 8622 Value |= op; 8623 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8624 break; 8625 } 8626 case ARM::VLD1d16Q: 8627 case ARM::VLD1d32Q: 8628 case ARM::VLD1d64Q: 8629 case ARM::VLD1d8Q: 8630 case ARM::VLD1q16: 8631 case ARM::VLD1q32: 8632 case ARM::VLD1q64: 8633 case ARM::VLD1q8: 8634 case ARM::VLD2b16: 8635 case ARM::VLD2b32: 8636 case ARM::VLD2b8: 8637 case ARM::VLD2d16: 8638 case ARM::VLD2d32: 8639 case ARM::VLD2d8: 8640 case ARM::VLD2q16: 8641 case ARM::VLD2q32: 8642 case ARM::VLD2q8: { 8643 // op: Vd 8644 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8645 Value |= (op & UINT64_C(16)) << 18; 8646 Value |= (op & UINT64_C(15)) << 12; 8647 // op: Rn 8648 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 8649 Value |= (op & UINT64_C(15)) << 16; 8650 Value |= (op & UINT64_C(48)); 8651 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8652 break; 8653 } 8654 case ARM::VLD1LNd8: { 8655 // op: Vd 8656 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8657 Value |= (op & UINT64_C(16)) << 18; 8658 Value |= (op & UINT64_C(15)) << 12; 8659 // op: Rn 8660 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 8661 op &= UINT64_C(15); 8662 op <<= 16; 8663 Value |= op; 8664 // op: lane 8665 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 8666 op &= UINT64_C(7); 8667 op <<= 5; 8668 Value |= op; 8669 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8670 break; 8671 } 8672 case ARM::VLD1LNd32_UPD: { 8673 // op: Vd 8674 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8675 Value |= (op & UINT64_C(16)) << 18; 8676 Value |= (op & UINT64_C(15)) << 12; 8677 // op: Rn 8678 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 8679 Value |= (op & UINT64_C(15)) << 16; 8680 Value |= (op & UINT64_C(16)) << 1; 8681 Value |= (op & UINT64_C(16)); 8682 // op: Rm 8683 op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI); 8684 op &= UINT64_C(15); 8685 Value |= op; 8686 // op: lane 8687 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 8688 op &= UINT64_C(1); 8689 op <<= 7; 8690 Value |= op; 8691 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8692 break; 8693 } 8694 case ARM::VLD1LNd16_UPD: { 8695 // op: Vd 8696 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8697 Value |= (op & UINT64_C(16)) << 18; 8698 Value |= (op & UINT64_C(15)) << 12; 8699 // op: Rn 8700 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 8701 Value |= (op & UINT64_C(15)) << 16; 8702 Value |= (op & UINT64_C(16)); 8703 // op: Rm 8704 op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI); 8705 op &= UINT64_C(15); 8706 Value |= op; 8707 // op: lane 8708 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 8709 op &= UINT64_C(3); 8710 op <<= 6; 8711 Value |= op; 8712 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8713 break; 8714 } 8715 case ARM::VLD1d16Twb_register: 8716 case ARM::VLD1d16wb_register: 8717 case ARM::VLD1d32Twb_register: 8718 case ARM::VLD1d32wb_register: 8719 case ARM::VLD1d64Twb_register: 8720 case ARM::VLD1d64wb_register: 8721 case ARM::VLD1d8Twb_register: 8722 case ARM::VLD1d8wb_register: { 8723 // op: Vd 8724 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8725 Value |= (op & UINT64_C(16)) << 18; 8726 Value |= (op & UINT64_C(15)) << 12; 8727 // op: Rn 8728 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 8729 Value |= (op & UINT64_C(15)) << 16; 8730 Value |= (op & UINT64_C(16)); 8731 // op: Rm 8732 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 8733 op &= UINT64_C(15); 8734 Value |= op; 8735 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8736 break; 8737 } 8738 case ARM::VLD2LNd32: 8739 case ARM::VLD2LNq32: { 8740 // op: Vd 8741 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8742 Value |= (op & UINT64_C(16)) << 18; 8743 Value |= (op & UINT64_C(15)) << 12; 8744 // op: Rn 8745 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 8746 Value |= (op & UINT64_C(15)) << 16; 8747 Value |= (op & UINT64_C(16)); 8748 // op: lane 8749 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 8750 op &= UINT64_C(1); 8751 op <<= 7; 8752 Value |= op; 8753 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8754 break; 8755 } 8756 case ARM::VLD2LNd16: 8757 case ARM::VLD2LNq16: { 8758 // op: Vd 8759 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8760 Value |= (op & UINT64_C(16)) << 18; 8761 Value |= (op & UINT64_C(15)) << 12; 8762 // op: Rn 8763 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 8764 Value |= (op & UINT64_C(15)) << 16; 8765 Value |= (op & UINT64_C(16)); 8766 // op: lane 8767 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 8768 op &= UINT64_C(3); 8769 op <<= 6; 8770 Value |= op; 8771 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8772 break; 8773 } 8774 case ARM::VLD2LNd8: { 8775 // op: Vd 8776 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8777 Value |= (op & UINT64_C(16)) << 18; 8778 Value |= (op & UINT64_C(15)) << 12; 8779 // op: Rn 8780 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 8781 Value |= (op & UINT64_C(15)) << 16; 8782 Value |= (op & UINT64_C(16)); 8783 // op: lane 8784 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 8785 op &= UINT64_C(7); 8786 op <<= 5; 8787 Value |= op; 8788 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8789 break; 8790 } 8791 case ARM::VLD1d16Twb_fixed: 8792 case ARM::VLD1d16wb_fixed: 8793 case ARM::VLD1d32Twb_fixed: 8794 case ARM::VLD1d32wb_fixed: 8795 case ARM::VLD1d64Twb_fixed: 8796 case ARM::VLD1d64wb_fixed: 8797 case ARM::VLD1d8Twb_fixed: 8798 case ARM::VLD1d8wb_fixed: { 8799 // op: Vd 8800 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8801 Value |= (op & UINT64_C(16)) << 18; 8802 Value |= (op & UINT64_C(15)) << 12; 8803 // op: Rn 8804 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 8805 Value |= (op & UINT64_C(15)) << 16; 8806 Value |= (op & UINT64_C(16)); 8807 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8808 break; 8809 } 8810 case ARM::VLD1d16Qwb_register: 8811 case ARM::VLD1d32Qwb_register: 8812 case ARM::VLD1d64Qwb_register: 8813 case ARM::VLD1d8Qwb_register: 8814 case ARM::VLD1q16wb_register: 8815 case ARM::VLD1q32wb_register: 8816 case ARM::VLD1q64wb_register: 8817 case ARM::VLD1q8wb_register: 8818 case ARM::VLD2b16wb_register: 8819 case ARM::VLD2b32wb_register: 8820 case ARM::VLD2b8wb_register: 8821 case ARM::VLD2d16wb_register: 8822 case ARM::VLD2d32wb_register: 8823 case ARM::VLD2d8wb_register: 8824 case ARM::VLD2q16wb_register: 8825 case ARM::VLD2q32wb_register: 8826 case ARM::VLD2q8wb_register: { 8827 // op: Vd 8828 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8829 Value |= (op & UINT64_C(16)) << 18; 8830 Value |= (op & UINT64_C(15)) << 12; 8831 // op: Rn 8832 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 8833 Value |= (op & UINT64_C(15)) << 16; 8834 Value |= (op & UINT64_C(48)); 8835 // op: Rm 8836 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 8837 op &= UINT64_C(15); 8838 Value |= op; 8839 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8840 break; 8841 } 8842 case ARM::VLD1d16Qwb_fixed: 8843 case ARM::VLD1d32Qwb_fixed: 8844 case ARM::VLD1d64Qwb_fixed: 8845 case ARM::VLD1d8Qwb_fixed: 8846 case ARM::VLD1q16wb_fixed: 8847 case ARM::VLD1q32wb_fixed: 8848 case ARM::VLD1q64wb_fixed: 8849 case ARM::VLD1q8wb_fixed: 8850 case ARM::VLD2b16wb_fixed: 8851 case ARM::VLD2b32wb_fixed: 8852 case ARM::VLD2b8wb_fixed: 8853 case ARM::VLD2d16wb_fixed: 8854 case ARM::VLD2d32wb_fixed: 8855 case ARM::VLD2d8wb_fixed: 8856 case ARM::VLD2q16wb_fixed: 8857 case ARM::VLD2q32wb_fixed: 8858 case ARM::VLD2q8wb_fixed: { 8859 // op: Vd 8860 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8861 Value |= (op & UINT64_C(16)) << 18; 8862 Value |= (op & UINT64_C(15)) << 12; 8863 // op: Rn 8864 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 8865 Value |= (op & UINT64_C(15)) << 16; 8866 Value |= (op & UINT64_C(48)); 8867 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8868 break; 8869 } 8870 case ARM::VLD1LNd8_UPD: { 8871 // op: Vd 8872 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8873 Value |= (op & UINT64_C(16)) << 18; 8874 Value |= (op & UINT64_C(15)) << 12; 8875 // op: Rn 8876 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 8877 op &= UINT64_C(15); 8878 op <<= 16; 8879 Value |= op; 8880 // op: Rm 8881 op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI); 8882 op &= UINT64_C(15); 8883 Value |= op; 8884 // op: lane 8885 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 8886 op &= UINT64_C(7); 8887 op <<= 5; 8888 Value |= op; 8889 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8890 break; 8891 } 8892 case ARM::VLD2LNd32_UPD: 8893 case ARM::VLD2LNq32_UPD: { 8894 // op: Vd 8895 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8896 Value |= (op & UINT64_C(16)) << 18; 8897 Value |= (op & UINT64_C(15)) << 12; 8898 // op: Rn 8899 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 8900 Value |= (op & UINT64_C(15)) << 16; 8901 Value |= (op & UINT64_C(16)); 8902 // op: Rm 8903 op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI); 8904 op &= UINT64_C(15); 8905 Value |= op; 8906 // op: lane 8907 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 8908 op &= UINT64_C(1); 8909 op <<= 7; 8910 Value |= op; 8911 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8912 break; 8913 } 8914 case ARM::VLD2LNd16_UPD: 8915 case ARM::VLD2LNq16_UPD: { 8916 // op: Vd 8917 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8918 Value |= (op & UINT64_C(16)) << 18; 8919 Value |= (op & UINT64_C(15)) << 12; 8920 // op: Rn 8921 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 8922 Value |= (op & UINT64_C(15)) << 16; 8923 Value |= (op & UINT64_C(16)); 8924 // op: Rm 8925 op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI); 8926 op &= UINT64_C(15); 8927 Value |= op; 8928 // op: lane 8929 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 8930 op &= UINT64_C(3); 8931 op <<= 6; 8932 Value |= op; 8933 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8934 break; 8935 } 8936 case ARM::VLD2LNd8_UPD: { 8937 // op: Vd 8938 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8939 Value |= (op & UINT64_C(16)) << 18; 8940 Value |= (op & UINT64_C(15)) << 12; 8941 // op: Rn 8942 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 8943 Value |= (op & UINT64_C(15)) << 16; 8944 Value |= (op & UINT64_C(16)); 8945 // op: Rm 8946 op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI); 8947 op &= UINT64_C(15); 8948 Value |= op; 8949 // op: lane 8950 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 8951 op &= UINT64_C(7); 8952 op <<= 5; 8953 Value |= op; 8954 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8955 break; 8956 } 8957 case ARM::VLD3d16: 8958 case ARM::VLD3d32: 8959 case ARM::VLD3d8: 8960 case ARM::VLD3q16: 8961 case ARM::VLD3q32: 8962 case ARM::VLD3q8: { 8963 // op: Vd 8964 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8965 Value |= (op & UINT64_C(16)) << 18; 8966 Value |= (op & UINT64_C(15)) << 12; 8967 // op: Rn 8968 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 8969 Value |= (op & UINT64_C(15)) << 16; 8970 Value |= (op & UINT64_C(16)); 8971 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8972 break; 8973 } 8974 case ARM::VLD3LNd32: 8975 case ARM::VLD3LNq32: { 8976 // op: Vd 8977 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8978 Value |= (op & UINT64_C(16)) << 18; 8979 Value |= (op & UINT64_C(15)) << 12; 8980 // op: Rn 8981 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 8982 op &= UINT64_C(15); 8983 op <<= 16; 8984 Value |= op; 8985 // op: lane 8986 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 8987 op &= UINT64_C(1); 8988 op <<= 7; 8989 Value |= op; 8990 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8991 break; 8992 } 8993 case ARM::VLD3LNd16: 8994 case ARM::VLD3LNq16: { 8995 // op: Vd 8996 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8997 Value |= (op & UINT64_C(16)) << 18; 8998 Value |= (op & UINT64_C(15)) << 12; 8999 // op: Rn 9000 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 9001 op &= UINT64_C(15); 9002 op <<= 16; 9003 Value |= op; 9004 // op: lane 9005 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 9006 op &= UINT64_C(3); 9007 op <<= 6; 9008 Value |= op; 9009 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9010 break; 9011 } 9012 case ARM::VLD3LNd8: { 9013 // op: Vd 9014 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9015 Value |= (op & UINT64_C(16)) << 18; 9016 Value |= (op & UINT64_C(15)) << 12; 9017 // op: Rn 9018 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 9019 op &= UINT64_C(15); 9020 op <<= 16; 9021 Value |= op; 9022 // op: lane 9023 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 9024 op &= UINT64_C(7); 9025 op <<= 5; 9026 Value |= op; 9027 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9028 break; 9029 } 9030 case ARM::VLD3d16_UPD: 9031 case ARM::VLD3d32_UPD: 9032 case ARM::VLD3d8_UPD: 9033 case ARM::VLD3q16_UPD: 9034 case ARM::VLD3q32_UPD: 9035 case ARM::VLD3q8_UPD: { 9036 // op: Vd 9037 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9038 Value |= (op & UINT64_C(16)) << 18; 9039 Value |= (op & UINT64_C(15)) << 12; 9040 // op: Rn 9041 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 9042 Value |= (op & UINT64_C(15)) << 16; 9043 Value |= (op & UINT64_C(16)); 9044 // op: Rm 9045 op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 9046 op &= UINT64_C(15); 9047 Value |= op; 9048 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9049 break; 9050 } 9051 case ARM::VLD4LNd16: 9052 case ARM::VLD4LNq16: { 9053 // op: Vd 9054 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9055 Value |= (op & UINT64_C(16)) << 18; 9056 Value |= (op & UINT64_C(15)) << 12; 9057 // op: Rn 9058 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 9059 Value |= (op & UINT64_C(15)) << 16; 9060 Value |= (op & UINT64_C(16)); 9061 // op: lane 9062 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 9063 op &= UINT64_C(3); 9064 op <<= 6; 9065 Value |= op; 9066 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9067 break; 9068 } 9069 case ARM::VLD4LNd8: { 9070 // op: Vd 9071 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9072 Value |= (op & UINT64_C(16)) << 18; 9073 Value |= (op & UINT64_C(15)) << 12; 9074 // op: Rn 9075 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 9076 Value |= (op & UINT64_C(15)) << 16; 9077 Value |= (op & UINT64_C(16)); 9078 // op: lane 9079 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 9080 op &= UINT64_C(7); 9081 op <<= 5; 9082 Value |= op; 9083 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9084 break; 9085 } 9086 case ARM::VLD4LNd32: 9087 case ARM::VLD4LNq32: { 9088 // op: Vd 9089 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9090 Value |= (op & UINT64_C(16)) << 18; 9091 Value |= (op & UINT64_C(15)) << 12; 9092 // op: Rn 9093 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 9094 Value |= (op & UINT64_C(15)) << 16; 9095 Value |= (op & UINT64_C(48)); 9096 // op: lane 9097 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 9098 op &= UINT64_C(1); 9099 op <<= 7; 9100 Value |= op; 9101 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9102 break; 9103 } 9104 case ARM::VLD4d16: 9105 case ARM::VLD4d32: 9106 case ARM::VLD4d8: 9107 case ARM::VLD4q16: 9108 case ARM::VLD4q32: 9109 case ARM::VLD4q8: { 9110 // op: Vd 9111 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9112 Value |= (op & UINT64_C(16)) << 18; 9113 Value |= (op & UINT64_C(15)) << 12; 9114 // op: Rn 9115 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 9116 Value |= (op & UINT64_C(15)) << 16; 9117 Value |= (op & UINT64_C(48)); 9118 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9119 break; 9120 } 9121 case ARM::VLD3LNd32_UPD: 9122 case ARM::VLD3LNq32_UPD: { 9123 // op: Vd 9124 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9125 Value |= (op & UINT64_C(16)) << 18; 9126 Value |= (op & UINT64_C(15)) << 12; 9127 // op: Rn 9128 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 9129 op &= UINT64_C(15); 9130 op <<= 16; 9131 Value |= op; 9132 // op: Rm 9133 op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 9134 op &= UINT64_C(15); 9135 Value |= op; 9136 // op: lane 9137 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 9138 op &= UINT64_C(1); 9139 op <<= 7; 9140 Value |= op; 9141 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9142 break; 9143 } 9144 case ARM::VLD3LNd16_UPD: 9145 case ARM::VLD3LNq16_UPD: { 9146 // op: Vd 9147 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9148 Value |= (op & UINT64_C(16)) << 18; 9149 Value |= (op & UINT64_C(15)) << 12; 9150 // op: Rn 9151 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 9152 op &= UINT64_C(15); 9153 op <<= 16; 9154 Value |= op; 9155 // op: Rm 9156 op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 9157 op &= UINT64_C(15); 9158 Value |= op; 9159 // op: lane 9160 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 9161 op &= UINT64_C(3); 9162 op <<= 6; 9163 Value |= op; 9164 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9165 break; 9166 } 9167 case ARM::VLD3LNd8_UPD: { 9168 // op: Vd 9169 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9170 Value |= (op & UINT64_C(16)) << 18; 9171 Value |= (op & UINT64_C(15)) << 12; 9172 // op: Rn 9173 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 9174 op &= UINT64_C(15); 9175 op <<= 16; 9176 Value |= op; 9177 // op: Rm 9178 op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 9179 op &= UINT64_C(15); 9180 Value |= op; 9181 // op: lane 9182 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 9183 op &= UINT64_C(7); 9184 op <<= 5; 9185 Value |= op; 9186 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9187 break; 9188 } 9189 case ARM::VLD4LNd16_UPD: 9190 case ARM::VLD4LNq16_UPD: { 9191 // op: Vd 9192 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9193 Value |= (op & UINT64_C(16)) << 18; 9194 Value |= (op & UINT64_C(15)) << 12; 9195 // op: Rn 9196 op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI); 9197 Value |= (op & UINT64_C(15)) << 16; 9198 Value |= (op & UINT64_C(16)); 9199 // op: Rm 9200 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 9201 op &= UINT64_C(15); 9202 Value |= op; 9203 // op: lane 9204 op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI); 9205 op &= UINT64_C(3); 9206 op <<= 6; 9207 Value |= op; 9208 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9209 break; 9210 } 9211 case ARM::VLD4LNd8_UPD: { 9212 // op: Vd 9213 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9214 Value |= (op & UINT64_C(16)) << 18; 9215 Value |= (op & UINT64_C(15)) << 12; 9216 // op: Rn 9217 op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI); 9218 Value |= (op & UINT64_C(15)) << 16; 9219 Value |= (op & UINT64_C(16)); 9220 // op: Rm 9221 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 9222 op &= UINT64_C(15); 9223 Value |= op; 9224 // op: lane 9225 op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI); 9226 op &= UINT64_C(7); 9227 op <<= 5; 9228 Value |= op; 9229 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9230 break; 9231 } 9232 case ARM::VLD4LNd32_UPD: 9233 case ARM::VLD4LNq32_UPD: { 9234 // op: Vd 9235 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9236 Value |= (op & UINT64_C(16)) << 18; 9237 Value |= (op & UINT64_C(15)) << 12; 9238 // op: Rn 9239 op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI); 9240 Value |= (op & UINT64_C(15)) << 16; 9241 Value |= (op & UINT64_C(48)); 9242 // op: Rm 9243 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 9244 op &= UINT64_C(15); 9245 Value |= op; 9246 // op: lane 9247 op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI); 9248 op &= UINT64_C(1); 9249 op <<= 7; 9250 Value |= op; 9251 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9252 break; 9253 } 9254 case ARM::VLD4d16_UPD: 9255 case ARM::VLD4d32_UPD: 9256 case ARM::VLD4d8_UPD: 9257 case ARM::VLD4q16_UPD: 9258 case ARM::VLD4q32_UPD: 9259 case ARM::VLD4q8_UPD: { 9260 // op: Vd 9261 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9262 Value |= (op & UINT64_C(16)) << 18; 9263 Value |= (op & UINT64_C(15)) << 12; 9264 // op: Rn 9265 op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI); 9266 Value |= (op & UINT64_C(15)) << 16; 9267 Value |= (op & UINT64_C(48)); 9268 // op: Rm 9269 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 9270 op &= UINT64_C(15); 9271 Value |= op; 9272 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9273 break; 9274 } 9275 case ARM::VLD1DUPd16: 9276 case ARM::VLD1DUPd32: 9277 case ARM::VLD1DUPd8: 9278 case ARM::VLD1DUPq16: 9279 case ARM::VLD1DUPq32: 9280 case ARM::VLD1DUPq8: 9281 case ARM::VLD2DUPd16: 9282 case ARM::VLD2DUPd16x2: 9283 case ARM::VLD2DUPd32: 9284 case ARM::VLD2DUPd32x2: 9285 case ARM::VLD2DUPd8: 9286 case ARM::VLD2DUPd8x2: { 9287 // op: Vd 9288 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9289 Value |= (op & UINT64_C(16)) << 18; 9290 Value |= (op & UINT64_C(15)) << 12; 9291 // op: Rn 9292 op = getAddrMode6DupAddressOpValue(MI, 1, Fixups, STI); 9293 Value |= (op & UINT64_C(15)) << 16; 9294 Value |= (op & UINT64_C(16)); 9295 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9296 break; 9297 } 9298 case ARM::VLD1DUPd16wb_register: 9299 case ARM::VLD1DUPd32wb_register: 9300 case ARM::VLD1DUPd8wb_register: 9301 case ARM::VLD1DUPq16wb_register: 9302 case ARM::VLD1DUPq32wb_register: 9303 case ARM::VLD1DUPq8wb_register: 9304 case ARM::VLD2DUPd16wb_register: 9305 case ARM::VLD2DUPd16x2wb_register: 9306 case ARM::VLD2DUPd32wb_register: 9307 case ARM::VLD2DUPd32x2wb_register: 9308 case ARM::VLD2DUPd8wb_register: 9309 case ARM::VLD2DUPd8x2wb_register: { 9310 // op: Vd 9311 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9312 Value |= (op & UINT64_C(16)) << 18; 9313 Value |= (op & UINT64_C(15)) << 12; 9314 // op: Rn 9315 op = getAddrMode6DupAddressOpValue(MI, 2, Fixups, STI); 9316 Value |= (op & UINT64_C(15)) << 16; 9317 Value |= (op & UINT64_C(16)); 9318 // op: Rm 9319 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9320 op &= UINT64_C(15); 9321 Value |= op; 9322 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9323 break; 9324 } 9325 case ARM::VLD1DUPd16wb_fixed: 9326 case ARM::VLD1DUPd32wb_fixed: 9327 case ARM::VLD1DUPd8wb_fixed: 9328 case ARM::VLD1DUPq16wb_fixed: 9329 case ARM::VLD1DUPq32wb_fixed: 9330 case ARM::VLD1DUPq8wb_fixed: 9331 case ARM::VLD2DUPd16wb_fixed: 9332 case ARM::VLD2DUPd16x2wb_fixed: 9333 case ARM::VLD2DUPd32wb_fixed: 9334 case ARM::VLD2DUPd32x2wb_fixed: 9335 case ARM::VLD2DUPd8wb_fixed: 9336 case ARM::VLD2DUPd8x2wb_fixed: { 9337 // op: Vd 9338 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9339 Value |= (op & UINT64_C(16)) << 18; 9340 Value |= (op & UINT64_C(15)) << 12; 9341 // op: Rn 9342 op = getAddrMode6DupAddressOpValue(MI, 2, Fixups, STI); 9343 Value |= (op & UINT64_C(15)) << 16; 9344 Value |= (op & UINT64_C(16)); 9345 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9346 break; 9347 } 9348 case ARM::VLD3DUPd16: 9349 case ARM::VLD3DUPd32: 9350 case ARM::VLD3DUPd8: 9351 case ARM::VLD3DUPq16: 9352 case ARM::VLD3DUPq32: 9353 case ARM::VLD3DUPq8: { 9354 // op: Vd 9355 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9356 Value |= (op & UINT64_C(16)) << 18; 9357 Value |= (op & UINT64_C(15)) << 12; 9358 // op: Rn 9359 op = getAddrMode6DupAddressOpValue(MI, 3, Fixups, STI); 9360 op &= UINT64_C(15); 9361 op <<= 16; 9362 Value |= op; 9363 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9364 break; 9365 } 9366 case ARM::VLD4DUPd16: 9367 case ARM::VLD4DUPd8: 9368 case ARM::VLD4DUPq16: 9369 case ARM::VLD4DUPq8: { 9370 // op: Vd 9371 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9372 Value |= (op & UINT64_C(16)) << 18; 9373 Value |= (op & UINT64_C(15)) << 12; 9374 // op: Rn 9375 op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI); 9376 Value |= (op & UINT64_C(15)) << 16; 9377 Value |= (op & UINT64_C(16)); 9378 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9379 break; 9380 } 9381 case ARM::VLD4DUPd32: 9382 case ARM::VLD4DUPq32: { 9383 // op: Vd 9384 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9385 Value |= (op & UINT64_C(16)) << 18; 9386 Value |= (op & UINT64_C(15)) << 12; 9387 // op: Rn 9388 op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI); 9389 Value |= (op & UINT64_C(15)) << 16; 9390 Value |= (op & UINT64_C(32)) << 1; 9391 Value |= (op & UINT64_C(16)); 9392 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9393 break; 9394 } 9395 case ARM::VLD3DUPd16_UPD: 9396 case ARM::VLD3DUPd32_UPD: 9397 case ARM::VLD3DUPd8_UPD: 9398 case ARM::VLD3DUPq16_UPD: 9399 case ARM::VLD3DUPq32_UPD: 9400 case ARM::VLD3DUPq8_UPD: { 9401 // op: Vd 9402 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9403 Value |= (op & UINT64_C(16)) << 18; 9404 Value |= (op & UINT64_C(15)) << 12; 9405 // op: Rn 9406 op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI); 9407 op &= UINT64_C(15); 9408 op <<= 16; 9409 Value |= op; 9410 // op: Rm 9411 op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 9412 op &= UINT64_C(15); 9413 Value |= op; 9414 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9415 break; 9416 } 9417 case ARM::VLD4DUPd16_UPD: 9418 case ARM::VLD4DUPd8_UPD: 9419 case ARM::VLD4DUPq16_UPD: 9420 case ARM::VLD4DUPq8_UPD: { 9421 // op: Vd 9422 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9423 Value |= (op & UINT64_C(16)) << 18; 9424 Value |= (op & UINT64_C(15)) << 12; 9425 // op: Rn 9426 op = getAddrMode6DupAddressOpValue(MI, 5, Fixups, STI); 9427 Value |= (op & UINT64_C(15)) << 16; 9428 Value |= (op & UINT64_C(16)); 9429 // op: Rm 9430 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 9431 op &= UINT64_C(15); 9432 Value |= op; 9433 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9434 break; 9435 } 9436 case ARM::VLD4DUPd32_UPD: 9437 case ARM::VLD4DUPq32_UPD: { 9438 // op: Vd 9439 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9440 Value |= (op & UINT64_C(16)) << 18; 9441 Value |= (op & UINT64_C(15)) << 12; 9442 // op: Rn 9443 op = getAddrMode6DupAddressOpValue(MI, 5, Fixups, STI); 9444 Value |= (op & UINT64_C(15)) << 16; 9445 Value |= (op & UINT64_C(32)) << 1; 9446 Value |= (op & UINT64_C(16)); 9447 // op: Rm 9448 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 9449 op &= UINT64_C(15); 9450 Value |= op; 9451 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9452 break; 9453 } 9454 case ARM::VLD1LNd32: { 9455 // op: Vd 9456 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9457 Value |= (op & UINT64_C(16)) << 18; 9458 Value |= (op & UINT64_C(15)) << 12; 9459 // op: Rn 9460 op = getAddrMode6OneLane32AddressOpValue(MI, 1, Fixups, STI); 9461 Value |= (op & UINT64_C(15)) << 16; 9462 Value |= (op & UINT64_C(48)); 9463 // op: lane 9464 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9465 op &= UINT64_C(1); 9466 op <<= 7; 9467 Value |= op; 9468 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9469 break; 9470 } 9471 case ARM::VMOVv16i8: 9472 case ARM::VMOVv1i64: 9473 case ARM::VMOVv2f32: 9474 case ARM::VMOVv2i64: 9475 case ARM::VMOVv4f32: 9476 case ARM::VMOVv8i8: { 9477 // op: Vd 9478 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9479 Value |= (op & UINT64_C(16)) << 18; 9480 Value |= (op & UINT64_C(15)) << 12; 9481 // op: SIMM 9482 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9483 Value |= (op & UINT64_C(128)) << 17; 9484 Value |= (op & UINT64_C(112)) << 12; 9485 Value |= (op & UINT64_C(15)); 9486 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9487 break; 9488 } 9489 case ARM::VBICiv2i32: 9490 case ARM::VBICiv4i32: 9491 case ARM::VORRiv2i32: 9492 case ARM::VORRiv4i32: { 9493 // op: Vd 9494 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9495 Value |= (op & UINT64_C(16)) << 18; 9496 Value |= (op & UINT64_C(15)) << 12; 9497 // op: SIMM 9498 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9499 Value |= (op & UINT64_C(128)) << 17; 9500 Value |= (op & UINT64_C(112)) << 12; 9501 Value |= (op & UINT64_C(1536)); 9502 Value |= (op & UINT64_C(15)); 9503 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9504 break; 9505 } 9506 case ARM::VMOVv2i32: 9507 case ARM::VMOVv4i32: 9508 case ARM::VMVNv2i32: 9509 case ARM::VMVNv4i32: { 9510 // op: Vd 9511 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9512 Value |= (op & UINT64_C(16)) << 18; 9513 Value |= (op & UINT64_C(15)) << 12; 9514 // op: SIMM 9515 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9516 Value |= (op & UINT64_C(128)) << 17; 9517 Value |= (op & UINT64_C(112)) << 12; 9518 Value |= (op & UINT64_C(3840)); 9519 Value |= (op & UINT64_C(15)); 9520 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9521 break; 9522 } 9523 case ARM::VBICiv4i16: 9524 case ARM::VBICiv8i16: 9525 case ARM::VMOVv4i16: 9526 case ARM::VMOVv8i16: 9527 case ARM::VMVNv4i16: 9528 case ARM::VMVNv8i16: 9529 case ARM::VORRiv4i16: 9530 case ARM::VORRiv8i16: { 9531 // op: Vd 9532 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9533 Value |= (op & UINT64_C(16)) << 18; 9534 Value |= (op & UINT64_C(15)) << 12; 9535 // op: SIMM 9536 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9537 Value |= (op & UINT64_C(128)) << 17; 9538 Value |= (op & UINT64_C(112)) << 12; 9539 Value |= (op & UINT64_C(512)); 9540 Value |= (op & UINT64_C(15)); 9541 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9542 break; 9543 } 9544 case ARM::VQSHLsiv4i16: 9545 case ARM::VQSHLsiv8i16: 9546 case ARM::VQSHLsuv4i16: 9547 case ARM::VQSHLsuv8i16: 9548 case ARM::VQSHLuiv4i16: 9549 case ARM::VQSHLuiv8i16: 9550 case ARM::VSHLLsv4i32: 9551 case ARM::VSHLLuv4i32: 9552 case ARM::VSHLiv4i16: 9553 case ARM::VSHLiv8i16: { 9554 // op: Vd 9555 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9556 Value |= (op & UINT64_C(16)) << 18; 9557 Value |= (op & UINT64_C(15)) << 12; 9558 // op: Vm 9559 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9560 Value |= (op & UINT64_C(16)) << 1; 9561 Value |= (op & UINT64_C(15)); 9562 // op: SIMM 9563 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9564 op &= UINT64_C(15); 9565 op <<= 16; 9566 Value |= op; 9567 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9568 break; 9569 } 9570 case ARM::VQSHLsiv2i32: 9571 case ARM::VQSHLsiv4i32: 9572 case ARM::VQSHLsuv2i32: 9573 case ARM::VQSHLsuv4i32: 9574 case ARM::VQSHLuiv2i32: 9575 case ARM::VQSHLuiv4i32: 9576 case ARM::VSHLLsv2i64: 9577 case ARM::VSHLLuv2i64: 9578 case ARM::VSHLiv2i32: 9579 case ARM::VSHLiv4i32: { 9580 // op: Vd 9581 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9582 Value |= (op & UINT64_C(16)) << 18; 9583 Value |= (op & UINT64_C(15)) << 12; 9584 // op: Vm 9585 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9586 Value |= (op & UINT64_C(16)) << 1; 9587 Value |= (op & UINT64_C(15)); 9588 // op: SIMM 9589 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9590 op &= UINT64_C(31); 9591 op <<= 16; 9592 Value |= op; 9593 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9594 break; 9595 } 9596 case ARM::VQSHLsiv1i64: 9597 case ARM::VQSHLsiv2i64: 9598 case ARM::VQSHLsuv1i64: 9599 case ARM::VQSHLsuv2i64: 9600 case ARM::VQSHLuiv1i64: 9601 case ARM::VQSHLuiv2i64: 9602 case ARM::VSHLiv1i64: 9603 case ARM::VSHLiv2i64: { 9604 // op: Vd 9605 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9606 Value |= (op & UINT64_C(16)) << 18; 9607 Value |= (op & UINT64_C(15)) << 12; 9608 // op: Vm 9609 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9610 Value |= (op & UINT64_C(16)) << 1; 9611 Value |= (op & UINT64_C(15)); 9612 // op: SIMM 9613 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9614 op &= UINT64_C(63); 9615 op <<= 16; 9616 Value |= op; 9617 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9618 break; 9619 } 9620 case ARM::VQSHLsiv16i8: 9621 case ARM::VQSHLsiv8i8: 9622 case ARM::VQSHLsuv16i8: 9623 case ARM::VQSHLsuv8i8: 9624 case ARM::VQSHLuiv16i8: 9625 case ARM::VQSHLuiv8i8: 9626 case ARM::VSHLLsv8i16: 9627 case ARM::VSHLLuv8i16: 9628 case ARM::VSHLiv16i8: 9629 case ARM::VSHLiv8i8: { 9630 // op: Vd 9631 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9632 Value |= (op & UINT64_C(16)) << 18; 9633 Value |= (op & UINT64_C(15)) << 12; 9634 // op: Vm 9635 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9636 Value |= (op & UINT64_C(16)) << 1; 9637 Value |= (op & UINT64_C(15)); 9638 // op: SIMM 9639 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9640 op &= UINT64_C(7); 9641 op <<= 16; 9642 Value |= op; 9643 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9644 break; 9645 } 9646 case ARM::VCVTf2xsd: 9647 case ARM::VCVTf2xsq: 9648 case ARM::VCVTf2xud: 9649 case ARM::VCVTf2xuq: 9650 case ARM::VCVTh2xsd: 9651 case ARM::VCVTh2xsq: 9652 case ARM::VCVTh2xud: 9653 case ARM::VCVTh2xuq: 9654 case ARM::VCVTxs2fd: 9655 case ARM::VCVTxs2fq: 9656 case ARM::VCVTxs2hd: 9657 case ARM::VCVTxs2hq: 9658 case ARM::VCVTxu2fd: 9659 case ARM::VCVTxu2fq: 9660 case ARM::VCVTxu2hd: 9661 case ARM::VCVTxu2hq: { 9662 // op: Vd 9663 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9664 Value |= (op & UINT64_C(16)) << 18; 9665 Value |= (op & UINT64_C(15)) << 12; 9666 // op: Vm 9667 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9668 Value |= (op & UINT64_C(16)) << 1; 9669 Value |= (op & UINT64_C(15)); 9670 // op: SIMM 9671 op = getNEONVcvtImm32OpValue(MI, 2, Fixups, STI); 9672 op &= UINT64_C(63); 9673 op <<= 16; 9674 Value |= op; 9675 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9676 break; 9677 } 9678 case ARM::VQRSHRNsv4i16: 9679 case ARM::VQRSHRNuv4i16: 9680 case ARM::VQRSHRUNv4i16: 9681 case ARM::VQSHRNsv4i16: 9682 case ARM::VQSHRNuv4i16: 9683 case ARM::VQSHRUNv4i16: 9684 case ARM::VRSHRNv4i16: 9685 case ARM::VRSHRsv4i16: 9686 case ARM::VRSHRsv8i16: 9687 case ARM::VRSHRuv4i16: 9688 case ARM::VRSHRuv8i16: 9689 case ARM::VSHRNv4i16: 9690 case ARM::VSHRsv4i16: 9691 case ARM::VSHRsv8i16: 9692 case ARM::VSHRuv4i16: 9693 case ARM::VSHRuv8i16: { 9694 // op: Vd 9695 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9696 Value |= (op & UINT64_C(16)) << 18; 9697 Value |= (op & UINT64_C(15)) << 12; 9698 // op: Vm 9699 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9700 Value |= (op & UINT64_C(16)) << 1; 9701 Value |= (op & UINT64_C(15)); 9702 // op: SIMM 9703 op = getShiftRight16Imm(MI, 2, Fixups, STI); 9704 op &= UINT64_C(15); 9705 op <<= 16; 9706 Value |= op; 9707 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9708 break; 9709 } 9710 case ARM::VQRSHRNsv2i32: 9711 case ARM::VQRSHRNuv2i32: 9712 case ARM::VQRSHRUNv2i32: 9713 case ARM::VQSHRNsv2i32: 9714 case ARM::VQSHRNuv2i32: 9715 case ARM::VQSHRUNv2i32: 9716 case ARM::VRSHRNv2i32: 9717 case ARM::VRSHRsv2i32: 9718 case ARM::VRSHRsv4i32: 9719 case ARM::VRSHRuv2i32: 9720 case ARM::VRSHRuv4i32: 9721 case ARM::VSHRNv2i32: 9722 case ARM::VSHRsv2i32: 9723 case ARM::VSHRsv4i32: 9724 case ARM::VSHRuv2i32: 9725 case ARM::VSHRuv4i32: { 9726 // op: Vd 9727 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9728 Value |= (op & UINT64_C(16)) << 18; 9729 Value |= (op & UINT64_C(15)) << 12; 9730 // op: Vm 9731 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9732 Value |= (op & UINT64_C(16)) << 1; 9733 Value |= (op & UINT64_C(15)); 9734 // op: SIMM 9735 op = getShiftRight32Imm(MI, 2, Fixups, STI); 9736 op &= UINT64_C(31); 9737 op <<= 16; 9738 Value |= op; 9739 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9740 break; 9741 } 9742 case ARM::VRSHRsv1i64: 9743 case ARM::VRSHRsv2i64: 9744 case ARM::VRSHRuv1i64: 9745 case ARM::VRSHRuv2i64: 9746 case ARM::VSHRsv1i64: 9747 case ARM::VSHRsv2i64: 9748 case ARM::VSHRuv1i64: 9749 case ARM::VSHRuv2i64: { 9750 // op: Vd 9751 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9752 Value |= (op & UINT64_C(16)) << 18; 9753 Value |= (op & UINT64_C(15)) << 12; 9754 // op: Vm 9755 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9756 Value |= (op & UINT64_C(16)) << 1; 9757 Value |= (op & UINT64_C(15)); 9758 // op: SIMM 9759 op = getShiftRight64Imm(MI, 2, Fixups, STI); 9760 op &= UINT64_C(63); 9761 op <<= 16; 9762 Value |= op; 9763 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9764 break; 9765 } 9766 case ARM::VQRSHRNsv8i8: 9767 case ARM::VQRSHRNuv8i8: 9768 case ARM::VQRSHRUNv8i8: 9769 case ARM::VQSHRNsv8i8: 9770 case ARM::VQSHRNuv8i8: 9771 case ARM::VQSHRUNv8i8: 9772 case ARM::VRSHRNv8i8: 9773 case ARM::VRSHRsv16i8: 9774 case ARM::VRSHRsv8i8: 9775 case ARM::VRSHRuv16i8: 9776 case ARM::VRSHRuv8i8: 9777 case ARM::VSHRNv8i8: 9778 case ARM::VSHRsv16i8: 9779 case ARM::VSHRsv8i8: 9780 case ARM::VSHRuv16i8: 9781 case ARM::VSHRuv8i8: { 9782 // op: Vd 9783 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9784 Value |= (op & UINT64_C(16)) << 18; 9785 Value |= (op & UINT64_C(15)) << 12; 9786 // op: Vm 9787 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9788 Value |= (op & UINT64_C(16)) << 1; 9789 Value |= (op & UINT64_C(15)); 9790 // op: SIMM 9791 op = getShiftRight8Imm(MI, 2, Fixups, STI); 9792 op &= UINT64_C(7); 9793 op <<= 16; 9794 Value |= op; 9795 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9796 break; 9797 } 9798 case ARM::VDUPLN32d: 9799 case ARM::VDUPLN32q: { 9800 // op: Vd 9801 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9802 Value |= (op & UINT64_C(16)) << 18; 9803 Value |= (op & UINT64_C(15)) << 12; 9804 // op: Vm 9805 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9806 Value |= (op & UINT64_C(16)) << 1; 9807 Value |= (op & UINT64_C(15)); 9808 // op: lane 9809 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9810 op &= UINT64_C(1); 9811 op <<= 19; 9812 Value |= op; 9813 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9814 break; 9815 } 9816 case ARM::VDUPLN16d: 9817 case ARM::VDUPLN16q: { 9818 // op: Vd 9819 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9820 Value |= (op & UINT64_C(16)) << 18; 9821 Value |= (op & UINT64_C(15)) << 12; 9822 // op: Vm 9823 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9824 Value |= (op & UINT64_C(16)) << 1; 9825 Value |= (op & UINT64_C(15)); 9826 // op: lane 9827 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9828 op &= UINT64_C(3); 9829 op <<= 18; 9830 Value |= op; 9831 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9832 break; 9833 } 9834 case ARM::VDUPLN8d: 9835 case ARM::VDUPLN8q: { 9836 // op: Vd 9837 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9838 Value |= (op & UINT64_C(16)) << 18; 9839 Value |= (op & UINT64_C(15)) << 12; 9840 // op: Vm 9841 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9842 Value |= (op & UINT64_C(16)) << 1; 9843 Value |= (op & UINT64_C(15)); 9844 // op: lane 9845 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9846 op &= UINT64_C(7); 9847 op <<= 17; 9848 Value |= op; 9849 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9850 break; 9851 } 9852 case ARM::AESIMC: 9853 case ARM::AESMC: 9854 case ARM::BF16_VCVT: 9855 case ARM::SHA1H: 9856 case ARM::VABSfd: 9857 case ARM::VABSfq: 9858 case ARM::VABShd: 9859 case ARM::VABShq: 9860 case ARM::VABSv16i8: 9861 case ARM::VABSv2i32: 9862 case ARM::VABSv4i16: 9863 case ARM::VABSv4i32: 9864 case ARM::VABSv8i16: 9865 case ARM::VABSv8i8: 9866 case ARM::VCEQzv16i8: 9867 case ARM::VCEQzv2f32: 9868 case ARM::VCEQzv2i32: 9869 case ARM::VCEQzv4f16: 9870 case ARM::VCEQzv4f32: 9871 case ARM::VCEQzv4i16: 9872 case ARM::VCEQzv4i32: 9873 case ARM::VCEQzv8f16: 9874 case ARM::VCEQzv8i16: 9875 case ARM::VCEQzv8i8: 9876 case ARM::VCGEzv16i8: 9877 case ARM::VCGEzv2f32: 9878 case ARM::VCGEzv2i32: 9879 case ARM::VCGEzv4f16: 9880 case ARM::VCGEzv4f32: 9881 case ARM::VCGEzv4i16: 9882 case ARM::VCGEzv4i32: 9883 case ARM::VCGEzv8f16: 9884 case ARM::VCGEzv8i16: 9885 case ARM::VCGEzv8i8: 9886 case ARM::VCGTzv16i8: 9887 case ARM::VCGTzv2f32: 9888 case ARM::VCGTzv2i32: 9889 case ARM::VCGTzv4f16: 9890 case ARM::VCGTzv4f32: 9891 case ARM::VCGTzv4i16: 9892 case ARM::VCGTzv4i32: 9893 case ARM::VCGTzv8f16: 9894 case ARM::VCGTzv8i16: 9895 case ARM::VCGTzv8i8: 9896 case ARM::VCLEzv16i8: 9897 case ARM::VCLEzv2f32: 9898 case ARM::VCLEzv2i32: 9899 case ARM::VCLEzv4f16: 9900 case ARM::VCLEzv4f32: 9901 case ARM::VCLEzv4i16: 9902 case ARM::VCLEzv4i32: 9903 case ARM::VCLEzv8f16: 9904 case ARM::VCLEzv8i16: 9905 case ARM::VCLEzv8i8: 9906 case ARM::VCLSv16i8: 9907 case ARM::VCLSv2i32: 9908 case ARM::VCLSv4i16: 9909 case ARM::VCLSv4i32: 9910 case ARM::VCLSv8i16: 9911 case ARM::VCLSv8i8: 9912 case ARM::VCLTzv16i8: 9913 case ARM::VCLTzv2f32: 9914 case ARM::VCLTzv2i32: 9915 case ARM::VCLTzv4f16: 9916 case ARM::VCLTzv4f32: 9917 case ARM::VCLTzv4i16: 9918 case ARM::VCLTzv4i32: 9919 case ARM::VCLTzv8f16: 9920 case ARM::VCLTzv8i16: 9921 case ARM::VCLTzv8i8: 9922 case ARM::VCLZv16i8: 9923 case ARM::VCLZv2i32: 9924 case ARM::VCLZv4i16: 9925 case ARM::VCLZv4i32: 9926 case ARM::VCLZv8i16: 9927 case ARM::VCLZv8i8: 9928 case ARM::VCNTd: 9929 case ARM::VCNTq: 9930 case ARM::VCVTf2h: 9931 case ARM::VCVTf2sd: 9932 case ARM::VCVTf2sq: 9933 case ARM::VCVTf2ud: 9934 case ARM::VCVTf2uq: 9935 case ARM::VCVTh2f: 9936 case ARM::VCVTh2sd: 9937 case ARM::VCVTh2sq: 9938 case ARM::VCVTh2ud: 9939 case ARM::VCVTh2uq: 9940 case ARM::VCVTs2fd: 9941 case ARM::VCVTs2fq: 9942 case ARM::VCVTs2hd: 9943 case ARM::VCVTs2hq: 9944 case ARM::VCVTu2fd: 9945 case ARM::VCVTu2fq: 9946 case ARM::VCVTu2hd: 9947 case ARM::VCVTu2hq: 9948 case ARM::VMOVLsv2i64: 9949 case ARM::VMOVLsv4i32: 9950 case ARM::VMOVLsv8i16: 9951 case ARM::VMOVLuv2i64: 9952 case ARM::VMOVLuv4i32: 9953 case ARM::VMOVLuv8i16: 9954 case ARM::VMOVNv2i32: 9955 case ARM::VMOVNv4i16: 9956 case ARM::VMOVNv8i8: 9957 case ARM::VMVNd: 9958 case ARM::VMVNq: 9959 case ARM::VNEGf32q: 9960 case ARM::VNEGfd: 9961 case ARM::VNEGhd: 9962 case ARM::VNEGhq: 9963 case ARM::VNEGs16d: 9964 case ARM::VNEGs16q: 9965 case ARM::VNEGs32d: 9966 case ARM::VNEGs32q: 9967 case ARM::VNEGs8d: 9968 case ARM::VNEGs8q: 9969 case ARM::VPADDLsv16i8: 9970 case ARM::VPADDLsv2i32: 9971 case ARM::VPADDLsv4i16: 9972 case ARM::VPADDLsv4i32: 9973 case ARM::VPADDLsv8i16: 9974 case ARM::VPADDLsv8i8: 9975 case ARM::VPADDLuv16i8: 9976 case ARM::VPADDLuv2i32: 9977 case ARM::VPADDLuv4i16: 9978 case ARM::VPADDLuv4i32: 9979 case ARM::VPADDLuv8i16: 9980 case ARM::VPADDLuv8i8: 9981 case ARM::VQABSv16i8: 9982 case ARM::VQABSv2i32: 9983 case ARM::VQABSv4i16: 9984 case ARM::VQABSv4i32: 9985 case ARM::VQABSv8i16: 9986 case ARM::VQABSv8i8: 9987 case ARM::VQMOVNsuv2i32: 9988 case ARM::VQMOVNsuv4i16: 9989 case ARM::VQMOVNsuv8i8: 9990 case ARM::VQMOVNsv2i32: 9991 case ARM::VQMOVNsv4i16: 9992 case ARM::VQMOVNsv8i8: 9993 case ARM::VQMOVNuv2i32: 9994 case ARM::VQMOVNuv4i16: 9995 case ARM::VQMOVNuv8i8: 9996 case ARM::VQNEGv16i8: 9997 case ARM::VQNEGv2i32: 9998 case ARM::VQNEGv4i16: 9999 case ARM::VQNEGv4i32: 10000 case ARM::VQNEGv8i16: 10001 case ARM::VQNEGv8i8: 10002 case ARM::VRECPEd: 10003 case ARM::VRECPEfd: 10004 case ARM::VRECPEfq: 10005 case ARM::VRECPEhd: 10006 case ARM::VRECPEhq: 10007 case ARM::VRECPEq: 10008 case ARM::VREV16d8: 10009 case ARM::VREV16q8: 10010 case ARM::VREV32d16: 10011 case ARM::VREV32d8: 10012 case ARM::VREV32q16: 10013 case ARM::VREV32q8: 10014 case ARM::VREV64d16: 10015 case ARM::VREV64d32: 10016 case ARM::VREV64d8: 10017 case ARM::VREV64q16: 10018 case ARM::VREV64q32: 10019 case ARM::VREV64q8: 10020 case ARM::VRSQRTEd: 10021 case ARM::VRSQRTEfd: 10022 case ARM::VRSQRTEfq: 10023 case ARM::VRSQRTEhd: 10024 case ARM::VRSQRTEhq: 10025 case ARM::VRSQRTEq: 10026 case ARM::VSHLLi16: 10027 case ARM::VSHLLi32: 10028 case ARM::VSHLLi8: 10029 case ARM::VSWPd: 10030 case ARM::VSWPq: 10031 case ARM::VTRNd16: 10032 case ARM::VTRNd32: 10033 case ARM::VTRNd8: 10034 case ARM::VTRNq16: 10035 case ARM::VTRNq32: 10036 case ARM::VTRNq8: 10037 case ARM::VUZPd16: 10038 case ARM::VUZPd8: 10039 case ARM::VUZPq16: 10040 case ARM::VUZPq32: 10041 case ARM::VUZPq8: 10042 case ARM::VZIPd16: 10043 case ARM::VZIPd8: 10044 case ARM::VZIPq16: 10045 case ARM::VZIPq32: 10046 case ARM::VZIPq8: { 10047 // op: Vd 10048 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10049 Value |= (op & UINT64_C(16)) << 18; 10050 Value |= (op & UINT64_C(15)) << 12; 10051 // op: Vm 10052 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10053 Value |= (op & UINT64_C(16)) << 1; 10054 Value |= (op & UINT64_C(15)); 10055 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10056 break; 10057 } 10058 case ARM::VCVTANSDf: 10059 case ARM::VCVTANSDh: 10060 case ARM::VCVTANSQf: 10061 case ARM::VCVTANSQh: 10062 case ARM::VCVTANUDf: 10063 case ARM::VCVTANUDh: 10064 case ARM::VCVTANUQf: 10065 case ARM::VCVTANUQh: 10066 case ARM::VCVTMNSDf: 10067 case ARM::VCVTMNSDh: 10068 case ARM::VCVTMNSQf: 10069 case ARM::VCVTMNSQh: 10070 case ARM::VCVTMNUDf: 10071 case ARM::VCVTMNUDh: 10072 case ARM::VCVTMNUQf: 10073 case ARM::VCVTMNUQh: 10074 case ARM::VCVTNNSDf: 10075 case ARM::VCVTNNSDh: 10076 case ARM::VCVTNNSQf: 10077 case ARM::VCVTNNSQh: 10078 case ARM::VCVTNNUDf: 10079 case ARM::VCVTNNUDh: 10080 case ARM::VCVTNNUQf: 10081 case ARM::VCVTNNUQh: 10082 case ARM::VCVTPNSDf: 10083 case ARM::VCVTPNSDh: 10084 case ARM::VCVTPNSQf: 10085 case ARM::VCVTPNSQh: 10086 case ARM::VCVTPNUDf: 10087 case ARM::VCVTPNUDh: 10088 case ARM::VCVTPNUQf: 10089 case ARM::VCVTPNUQh: 10090 case ARM::VRINTANDf: 10091 case ARM::VRINTANDh: 10092 case ARM::VRINTANQf: 10093 case ARM::VRINTANQh: 10094 case ARM::VRINTMNDf: 10095 case ARM::VRINTMNDh: 10096 case ARM::VRINTMNQf: 10097 case ARM::VRINTMNQh: 10098 case ARM::VRINTNNDf: 10099 case ARM::VRINTNNDh: 10100 case ARM::VRINTNNQf: 10101 case ARM::VRINTNNQh: 10102 case ARM::VRINTPNDf: 10103 case ARM::VRINTPNDh: 10104 case ARM::VRINTPNQf: 10105 case ARM::VRINTPNQh: 10106 case ARM::VRINTXNDf: 10107 case ARM::VRINTXNDh: 10108 case ARM::VRINTXNQf: 10109 case ARM::VRINTXNQh: 10110 case ARM::VRINTZNDf: 10111 case ARM::VRINTZNDh: 10112 case ARM::VRINTZNQf: 10113 case ARM::VRINTZNQh: { 10114 // op: Vd 10115 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10116 Value |= (op & UINT64_C(16)) << 18; 10117 Value |= (op & UINT64_C(15)) << 12; 10118 // op: Vm 10119 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10120 Value |= (op & UINT64_C(16)) << 1; 10121 Value |= (op & UINT64_C(15)); 10122 Value = NEONThumb2V8PostEncoder(MI, Value, STI); 10123 break; 10124 } 10125 case ARM::VSLIv4i16: 10126 case ARM::VSLIv8i16: { 10127 // op: Vd 10128 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10129 Value |= (op & UINT64_C(16)) << 18; 10130 Value |= (op & UINT64_C(15)) << 12; 10131 // op: Vm 10132 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10133 Value |= (op & UINT64_C(16)) << 1; 10134 Value |= (op & UINT64_C(15)); 10135 // op: SIMM 10136 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10137 op &= UINT64_C(15); 10138 op <<= 16; 10139 Value |= op; 10140 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10141 break; 10142 } 10143 case ARM::VSLIv2i32: 10144 case ARM::VSLIv4i32: { 10145 // op: Vd 10146 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10147 Value |= (op & UINT64_C(16)) << 18; 10148 Value |= (op & UINT64_C(15)) << 12; 10149 // op: Vm 10150 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10151 Value |= (op & UINT64_C(16)) << 1; 10152 Value |= (op & UINT64_C(15)); 10153 // op: SIMM 10154 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10155 op &= UINT64_C(31); 10156 op <<= 16; 10157 Value |= op; 10158 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10159 break; 10160 } 10161 case ARM::VSLIv1i64: 10162 case ARM::VSLIv2i64: { 10163 // op: Vd 10164 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10165 Value |= (op & UINT64_C(16)) << 18; 10166 Value |= (op & UINT64_C(15)) << 12; 10167 // op: Vm 10168 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10169 Value |= (op & UINT64_C(16)) << 1; 10170 Value |= (op & UINT64_C(15)); 10171 // op: SIMM 10172 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10173 op &= UINT64_C(63); 10174 op <<= 16; 10175 Value |= op; 10176 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10177 break; 10178 } 10179 case ARM::VSLIv16i8: 10180 case ARM::VSLIv8i8: { 10181 // op: Vd 10182 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10183 Value |= (op & UINT64_C(16)) << 18; 10184 Value |= (op & UINT64_C(15)) << 12; 10185 // op: Vm 10186 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10187 Value |= (op & UINT64_C(16)) << 1; 10188 Value |= (op & UINT64_C(15)); 10189 // op: SIMM 10190 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10191 op &= UINT64_C(7); 10192 op <<= 16; 10193 Value |= op; 10194 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10195 break; 10196 } 10197 case ARM::VRSRAsv4i16: 10198 case ARM::VRSRAsv8i16: 10199 case ARM::VRSRAuv4i16: 10200 case ARM::VRSRAuv8i16: 10201 case ARM::VSRAsv4i16: 10202 case ARM::VSRAsv8i16: 10203 case ARM::VSRAuv4i16: 10204 case ARM::VSRAuv8i16: 10205 case ARM::VSRIv4i16: 10206 case ARM::VSRIv8i16: { 10207 // op: Vd 10208 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10209 Value |= (op & UINT64_C(16)) << 18; 10210 Value |= (op & UINT64_C(15)) << 12; 10211 // op: Vm 10212 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10213 Value |= (op & UINT64_C(16)) << 1; 10214 Value |= (op & UINT64_C(15)); 10215 // op: SIMM 10216 op = getShiftRight16Imm(MI, 3, Fixups, STI); 10217 op &= UINT64_C(15); 10218 op <<= 16; 10219 Value |= op; 10220 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10221 break; 10222 } 10223 case ARM::VRSRAsv2i32: 10224 case ARM::VRSRAsv4i32: 10225 case ARM::VRSRAuv2i32: 10226 case ARM::VRSRAuv4i32: 10227 case ARM::VSRAsv2i32: 10228 case ARM::VSRAsv4i32: 10229 case ARM::VSRAuv2i32: 10230 case ARM::VSRAuv4i32: 10231 case ARM::VSRIv2i32: 10232 case ARM::VSRIv4i32: { 10233 // op: Vd 10234 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10235 Value |= (op & UINT64_C(16)) << 18; 10236 Value |= (op & UINT64_C(15)) << 12; 10237 // op: Vm 10238 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10239 Value |= (op & UINT64_C(16)) << 1; 10240 Value |= (op & UINT64_C(15)); 10241 // op: SIMM 10242 op = getShiftRight32Imm(MI, 3, Fixups, STI); 10243 op &= UINT64_C(31); 10244 op <<= 16; 10245 Value |= op; 10246 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10247 break; 10248 } 10249 case ARM::VRSRAsv1i64: 10250 case ARM::VRSRAsv2i64: 10251 case ARM::VRSRAuv1i64: 10252 case ARM::VRSRAuv2i64: 10253 case ARM::VSRAsv1i64: 10254 case ARM::VSRAsv2i64: 10255 case ARM::VSRAuv1i64: 10256 case ARM::VSRAuv2i64: 10257 case ARM::VSRIv1i64: 10258 case ARM::VSRIv2i64: { 10259 // op: Vd 10260 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10261 Value |= (op & UINT64_C(16)) << 18; 10262 Value |= (op & UINT64_C(15)) << 12; 10263 // op: Vm 10264 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10265 Value |= (op & UINT64_C(16)) << 1; 10266 Value |= (op & UINT64_C(15)); 10267 // op: SIMM 10268 op = getShiftRight64Imm(MI, 3, Fixups, STI); 10269 op &= UINT64_C(63); 10270 op <<= 16; 10271 Value |= op; 10272 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10273 break; 10274 } 10275 case ARM::VRSRAsv16i8: 10276 case ARM::VRSRAsv8i8: 10277 case ARM::VRSRAuv16i8: 10278 case ARM::VRSRAuv8i8: 10279 case ARM::VSRAsv16i8: 10280 case ARM::VSRAsv8i8: 10281 case ARM::VSRAuv16i8: 10282 case ARM::VSRAuv8i8: 10283 case ARM::VSRIv16i8: 10284 case ARM::VSRIv8i8: { 10285 // op: Vd 10286 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10287 Value |= (op & UINT64_C(16)) << 18; 10288 Value |= (op & UINT64_C(15)) << 12; 10289 // op: Vm 10290 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10291 Value |= (op & UINT64_C(16)) << 1; 10292 Value |= (op & UINT64_C(15)); 10293 // op: SIMM 10294 op = getShiftRight8Imm(MI, 3, Fixups, STI); 10295 op &= UINT64_C(7); 10296 op <<= 16; 10297 Value |= op; 10298 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10299 break; 10300 } 10301 case ARM::AESD: 10302 case ARM::AESE: 10303 case ARM::SHA1SU1: 10304 case ARM::SHA256SU0: 10305 case ARM::VPADALsv16i8: 10306 case ARM::VPADALsv2i32: 10307 case ARM::VPADALsv4i16: 10308 case ARM::VPADALsv4i32: 10309 case ARM::VPADALsv8i16: 10310 case ARM::VPADALsv8i8: 10311 case ARM::VPADALuv16i8: 10312 case ARM::VPADALuv2i32: 10313 case ARM::VPADALuv4i16: 10314 case ARM::VPADALuv4i32: 10315 case ARM::VPADALuv8i16: 10316 case ARM::VPADALuv8i8: { 10317 // op: Vd 10318 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10319 Value |= (op & UINT64_C(16)) << 18; 10320 Value |= (op & UINT64_C(15)) << 12; 10321 // op: Vm 10322 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10323 Value |= (op & UINT64_C(16)) << 1; 10324 Value |= (op & UINT64_C(15)); 10325 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10326 break; 10327 } 10328 case ARM::VFMALQ: 10329 case ARM::VFMSLQ: { 10330 // op: Vd 10331 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10332 Value |= (op & UINT64_C(16)) << 18; 10333 Value |= (op & UINT64_C(15)) << 12; 10334 // op: Vn 10335 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10336 Value |= (op & UINT64_C(15)) << 16; 10337 Value |= (op & UINT64_C(16)) << 3; 10338 // op: Vm 10339 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10340 Value |= (op & UINT64_C(16)) << 1; 10341 Value |= (op & UINT64_C(15)); 10342 break; 10343 } 10344 case ARM::VEXTd32: { 10345 // op: Vd 10346 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10347 Value |= (op & UINT64_C(16)) << 18; 10348 Value |= (op & UINT64_C(15)) << 12; 10349 // op: Vn 10350 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10351 Value |= (op & UINT64_C(15)) << 16; 10352 Value |= (op & UINT64_C(16)) << 3; 10353 // op: Vm 10354 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10355 Value |= (op & UINT64_C(16)) << 1; 10356 Value |= (op & UINT64_C(15)); 10357 // op: index 10358 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10359 op &= UINT64_C(1); 10360 op <<= 10; 10361 Value |= op; 10362 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10363 break; 10364 } 10365 case ARM::VEXTq64: { 10366 // op: Vd 10367 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10368 Value |= (op & UINT64_C(16)) << 18; 10369 Value |= (op & UINT64_C(15)) << 12; 10370 // op: Vn 10371 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10372 Value |= (op & UINT64_C(15)) << 16; 10373 Value |= (op & UINT64_C(16)) << 3; 10374 // op: Vm 10375 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10376 Value |= (op & UINT64_C(16)) << 1; 10377 Value |= (op & UINT64_C(15)); 10378 // op: index 10379 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10380 op &= UINT64_C(1); 10381 op <<= 11; 10382 Value |= op; 10383 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10384 break; 10385 } 10386 case ARM::VEXTq8: { 10387 // op: Vd 10388 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10389 Value |= (op & UINT64_C(16)) << 18; 10390 Value |= (op & UINT64_C(15)) << 12; 10391 // op: Vn 10392 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10393 Value |= (op & UINT64_C(15)) << 16; 10394 Value |= (op & UINT64_C(16)) << 3; 10395 // op: Vm 10396 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10397 Value |= (op & UINT64_C(16)) << 1; 10398 Value |= (op & UINT64_C(15)); 10399 // op: index 10400 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10401 op &= UINT64_C(15); 10402 op <<= 8; 10403 Value |= op; 10404 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10405 break; 10406 } 10407 case ARM::VEXTq32: { 10408 // op: Vd 10409 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10410 Value |= (op & UINT64_C(16)) << 18; 10411 Value |= (op & UINT64_C(15)) << 12; 10412 // op: Vn 10413 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10414 Value |= (op & UINT64_C(15)) << 16; 10415 Value |= (op & UINT64_C(16)) << 3; 10416 // op: Vm 10417 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10418 Value |= (op & UINT64_C(16)) << 1; 10419 Value |= (op & UINT64_C(15)); 10420 // op: index 10421 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10422 op &= UINT64_C(3); 10423 op <<= 10; 10424 Value |= op; 10425 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10426 break; 10427 } 10428 case ARM::VEXTd16: { 10429 // op: Vd 10430 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10431 Value |= (op & UINT64_C(16)) << 18; 10432 Value |= (op & UINT64_C(15)) << 12; 10433 // op: Vn 10434 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10435 Value |= (op & UINT64_C(15)) << 16; 10436 Value |= (op & UINT64_C(16)) << 3; 10437 // op: Vm 10438 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10439 Value |= (op & UINT64_C(16)) << 1; 10440 Value |= (op & UINT64_C(15)); 10441 // op: index 10442 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10443 op &= UINT64_C(3); 10444 op <<= 9; 10445 Value |= op; 10446 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10447 break; 10448 } 10449 case ARM::VEXTd8: { 10450 // op: Vd 10451 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10452 Value |= (op & UINT64_C(16)) << 18; 10453 Value |= (op & UINT64_C(15)) << 12; 10454 // op: Vn 10455 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10456 Value |= (op & UINT64_C(15)) << 16; 10457 Value |= (op & UINT64_C(16)) << 3; 10458 // op: Vm 10459 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10460 Value |= (op & UINT64_C(16)) << 1; 10461 Value |= (op & UINT64_C(15)); 10462 // op: index 10463 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10464 op &= UINT64_C(7); 10465 op <<= 8; 10466 Value |= op; 10467 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10468 break; 10469 } 10470 case ARM::VEXTq16: { 10471 // op: Vd 10472 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10473 Value |= (op & UINT64_C(16)) << 18; 10474 Value |= (op & UINT64_C(15)) << 12; 10475 // op: Vn 10476 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10477 Value |= (op & UINT64_C(15)) << 16; 10478 Value |= (op & UINT64_C(16)) << 3; 10479 // op: Vm 10480 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10481 Value |= (op & UINT64_C(16)) << 1; 10482 Value |= (op & UINT64_C(15)); 10483 // op: index 10484 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10485 op &= UINT64_C(7); 10486 op <<= 9; 10487 Value |= op; 10488 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10489 break; 10490 } 10491 case ARM::VCADDv2f32: 10492 case ARM::VCADDv4f16: 10493 case ARM::VCADDv4f32: 10494 case ARM::VCADDv8f16: { 10495 // op: Vd 10496 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10497 Value |= (op & UINT64_C(16)) << 18; 10498 Value |= (op & UINT64_C(15)) << 12; 10499 // op: Vn 10500 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10501 Value |= (op & UINT64_C(15)) << 16; 10502 Value |= (op & UINT64_C(16)) << 3; 10503 // op: Vm 10504 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10505 Value |= (op & UINT64_C(16)) << 1; 10506 Value |= (op & UINT64_C(15)); 10507 // op: rot 10508 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10509 op &= UINT64_C(1); 10510 op <<= 24; 10511 Value |= op; 10512 break; 10513 } 10514 case ARM::VABDLsv2i64: 10515 case ARM::VABDLsv4i32: 10516 case ARM::VABDLsv8i16: 10517 case ARM::VABDLuv2i64: 10518 case ARM::VABDLuv4i32: 10519 case ARM::VABDLuv8i16: 10520 case ARM::VABDfd: 10521 case ARM::VABDfq: 10522 case ARM::VABDhd: 10523 case ARM::VABDhq: 10524 case ARM::VABDsv16i8: 10525 case ARM::VABDsv2i32: 10526 case ARM::VABDsv4i16: 10527 case ARM::VABDsv4i32: 10528 case ARM::VABDsv8i16: 10529 case ARM::VABDsv8i8: 10530 case ARM::VABDuv16i8: 10531 case ARM::VABDuv2i32: 10532 case ARM::VABDuv4i16: 10533 case ARM::VABDuv4i32: 10534 case ARM::VABDuv8i16: 10535 case ARM::VABDuv8i8: 10536 case ARM::VACGEfd: 10537 case ARM::VACGEfq: 10538 case ARM::VACGEhd: 10539 case ARM::VACGEhq: 10540 case ARM::VACGTfd: 10541 case ARM::VACGTfq: 10542 case ARM::VACGThd: 10543 case ARM::VACGThq: 10544 case ARM::VADDHNv2i32: 10545 case ARM::VADDHNv4i16: 10546 case ARM::VADDHNv8i8: 10547 case ARM::VADDLsv2i64: 10548 case ARM::VADDLsv4i32: 10549 case ARM::VADDLsv8i16: 10550 case ARM::VADDLuv2i64: 10551 case ARM::VADDLuv4i32: 10552 case ARM::VADDLuv8i16: 10553 case ARM::VADDWsv2i64: 10554 case ARM::VADDWsv4i32: 10555 case ARM::VADDWsv8i16: 10556 case ARM::VADDWuv2i64: 10557 case ARM::VADDWuv4i32: 10558 case ARM::VADDWuv8i16: 10559 case ARM::VADDfd: 10560 case ARM::VADDfq: 10561 case ARM::VADDhd: 10562 case ARM::VADDhq: 10563 case ARM::VADDv16i8: 10564 case ARM::VADDv1i64: 10565 case ARM::VADDv2i32: 10566 case ARM::VADDv2i64: 10567 case ARM::VADDv4i16: 10568 case ARM::VADDv4i32: 10569 case ARM::VADDv8i16: 10570 case ARM::VADDv8i8: 10571 case ARM::VANDd: 10572 case ARM::VANDq: 10573 case ARM::VBICd: 10574 case ARM::VBICq: 10575 case ARM::VCEQfd: 10576 case ARM::VCEQfq: 10577 case ARM::VCEQhd: 10578 case ARM::VCEQhq: 10579 case ARM::VCEQv16i8: 10580 case ARM::VCEQv2i32: 10581 case ARM::VCEQv4i16: 10582 case ARM::VCEQv4i32: 10583 case ARM::VCEQv8i16: 10584 case ARM::VCEQv8i8: 10585 case ARM::VCGEfd: 10586 case ARM::VCGEfq: 10587 case ARM::VCGEhd: 10588 case ARM::VCGEhq: 10589 case ARM::VCGEsv16i8: 10590 case ARM::VCGEsv2i32: 10591 case ARM::VCGEsv4i16: 10592 case ARM::VCGEsv4i32: 10593 case ARM::VCGEsv8i16: 10594 case ARM::VCGEsv8i8: 10595 case ARM::VCGEuv16i8: 10596 case ARM::VCGEuv2i32: 10597 case ARM::VCGEuv4i16: 10598 case ARM::VCGEuv4i32: 10599 case ARM::VCGEuv8i16: 10600 case ARM::VCGEuv8i8: 10601 case ARM::VCGTfd: 10602 case ARM::VCGTfq: 10603 case ARM::VCGThd: 10604 case ARM::VCGThq: 10605 case ARM::VCGTsv16i8: 10606 case ARM::VCGTsv2i32: 10607 case ARM::VCGTsv4i16: 10608 case ARM::VCGTsv4i32: 10609 case ARM::VCGTsv8i16: 10610 case ARM::VCGTsv8i8: 10611 case ARM::VCGTuv16i8: 10612 case ARM::VCGTuv2i32: 10613 case ARM::VCGTuv4i16: 10614 case ARM::VCGTuv4i32: 10615 case ARM::VCGTuv8i16: 10616 case ARM::VCGTuv8i8: 10617 case ARM::VEORd: 10618 case ARM::VEORq: 10619 case ARM::VHADDsv16i8: 10620 case ARM::VHADDsv2i32: 10621 case ARM::VHADDsv4i16: 10622 case ARM::VHADDsv4i32: 10623 case ARM::VHADDsv8i16: 10624 case ARM::VHADDsv8i8: 10625 case ARM::VHADDuv16i8: 10626 case ARM::VHADDuv2i32: 10627 case ARM::VHADDuv4i16: 10628 case ARM::VHADDuv4i32: 10629 case ARM::VHADDuv8i16: 10630 case ARM::VHADDuv8i8: 10631 case ARM::VHSUBsv16i8: 10632 case ARM::VHSUBsv2i32: 10633 case ARM::VHSUBsv4i16: 10634 case ARM::VHSUBsv4i32: 10635 case ARM::VHSUBsv8i16: 10636 case ARM::VHSUBsv8i8: 10637 case ARM::VHSUBuv16i8: 10638 case ARM::VHSUBuv2i32: 10639 case ARM::VHSUBuv4i16: 10640 case ARM::VHSUBuv4i32: 10641 case ARM::VHSUBuv8i16: 10642 case ARM::VHSUBuv8i8: 10643 case ARM::VMAXfd: 10644 case ARM::VMAXfq: 10645 case ARM::VMAXhd: 10646 case ARM::VMAXhq: 10647 case ARM::VMAXsv16i8: 10648 case ARM::VMAXsv2i32: 10649 case ARM::VMAXsv4i16: 10650 case ARM::VMAXsv4i32: 10651 case ARM::VMAXsv8i16: 10652 case ARM::VMAXsv8i8: 10653 case ARM::VMAXuv16i8: 10654 case ARM::VMAXuv2i32: 10655 case ARM::VMAXuv4i16: 10656 case ARM::VMAXuv4i32: 10657 case ARM::VMAXuv8i16: 10658 case ARM::VMAXuv8i8: 10659 case ARM::VMINfd: 10660 case ARM::VMINfq: 10661 case ARM::VMINhd: 10662 case ARM::VMINhq: 10663 case ARM::VMINsv16i8: 10664 case ARM::VMINsv2i32: 10665 case ARM::VMINsv4i16: 10666 case ARM::VMINsv4i32: 10667 case ARM::VMINsv8i16: 10668 case ARM::VMINsv8i8: 10669 case ARM::VMINuv16i8: 10670 case ARM::VMINuv2i32: 10671 case ARM::VMINuv4i16: 10672 case ARM::VMINuv4i32: 10673 case ARM::VMINuv8i16: 10674 case ARM::VMINuv8i8: 10675 case ARM::VMULLp64: 10676 case ARM::VMULLp8: 10677 case ARM::VMULLsv2i64: 10678 case ARM::VMULLsv4i32: 10679 case ARM::VMULLsv8i16: 10680 case ARM::VMULLuv2i64: 10681 case ARM::VMULLuv4i32: 10682 case ARM::VMULLuv8i16: 10683 case ARM::VMULfd: 10684 case ARM::VMULfq: 10685 case ARM::VMULhd: 10686 case ARM::VMULhq: 10687 case ARM::VMULpd: 10688 case ARM::VMULpq: 10689 case ARM::VMULv16i8: 10690 case ARM::VMULv2i32: 10691 case ARM::VMULv4i16: 10692 case ARM::VMULv4i32: 10693 case ARM::VMULv8i16: 10694 case ARM::VMULv8i8: 10695 case ARM::VORNd: 10696 case ARM::VORNq: 10697 case ARM::VORRd: 10698 case ARM::VORRq: 10699 case ARM::VPADDf: 10700 case ARM::VPADDh: 10701 case ARM::VPADDi16: 10702 case ARM::VPADDi32: 10703 case ARM::VPADDi8: 10704 case ARM::VPMAXf: 10705 case ARM::VPMAXh: 10706 case ARM::VPMAXs16: 10707 case ARM::VPMAXs32: 10708 case ARM::VPMAXs8: 10709 case ARM::VPMAXu16: 10710 case ARM::VPMAXu32: 10711 case ARM::VPMAXu8: 10712 case ARM::VPMINf: 10713 case ARM::VPMINh: 10714 case ARM::VPMINs16: 10715 case ARM::VPMINs32: 10716 case ARM::VPMINs8: 10717 case ARM::VPMINu16: 10718 case ARM::VPMINu32: 10719 case ARM::VPMINu8: 10720 case ARM::VQADDsv16i8: 10721 case ARM::VQADDsv1i64: 10722 case ARM::VQADDsv2i32: 10723 case ARM::VQADDsv2i64: 10724 case ARM::VQADDsv4i16: 10725 case ARM::VQADDsv4i32: 10726 case ARM::VQADDsv8i16: 10727 case ARM::VQADDsv8i8: 10728 case ARM::VQADDuv16i8: 10729 case ARM::VQADDuv1i64: 10730 case ARM::VQADDuv2i32: 10731 case ARM::VQADDuv2i64: 10732 case ARM::VQADDuv4i16: 10733 case ARM::VQADDuv4i32: 10734 case ARM::VQADDuv8i16: 10735 case ARM::VQADDuv8i8: 10736 case ARM::VQDMULHv2i32: 10737 case ARM::VQDMULHv4i16: 10738 case ARM::VQDMULHv4i32: 10739 case ARM::VQDMULHv8i16: 10740 case ARM::VQDMULLv2i64: 10741 case ARM::VQDMULLv4i32: 10742 case ARM::VQRDMULHv2i32: 10743 case ARM::VQRDMULHv4i16: 10744 case ARM::VQRDMULHv4i32: 10745 case ARM::VQRDMULHv8i16: 10746 case ARM::VQSUBsv16i8: 10747 case ARM::VQSUBsv1i64: 10748 case ARM::VQSUBsv2i32: 10749 case ARM::VQSUBsv2i64: 10750 case ARM::VQSUBsv4i16: 10751 case ARM::VQSUBsv4i32: 10752 case ARM::VQSUBsv8i16: 10753 case ARM::VQSUBsv8i8: 10754 case ARM::VQSUBuv16i8: 10755 case ARM::VQSUBuv1i64: 10756 case ARM::VQSUBuv2i32: 10757 case ARM::VQSUBuv2i64: 10758 case ARM::VQSUBuv4i16: 10759 case ARM::VQSUBuv4i32: 10760 case ARM::VQSUBuv8i16: 10761 case ARM::VQSUBuv8i8: 10762 case ARM::VRADDHNv2i32: 10763 case ARM::VRADDHNv4i16: 10764 case ARM::VRADDHNv8i8: 10765 case ARM::VRECPSfd: 10766 case ARM::VRECPSfq: 10767 case ARM::VRECPShd: 10768 case ARM::VRECPShq: 10769 case ARM::VRHADDsv16i8: 10770 case ARM::VRHADDsv2i32: 10771 case ARM::VRHADDsv4i16: 10772 case ARM::VRHADDsv4i32: 10773 case ARM::VRHADDsv8i16: 10774 case ARM::VRHADDsv8i8: 10775 case ARM::VRHADDuv16i8: 10776 case ARM::VRHADDuv2i32: 10777 case ARM::VRHADDuv4i16: 10778 case ARM::VRHADDuv4i32: 10779 case ARM::VRHADDuv8i16: 10780 case ARM::VRHADDuv8i8: 10781 case ARM::VRSQRTSfd: 10782 case ARM::VRSQRTSfq: 10783 case ARM::VRSQRTShd: 10784 case ARM::VRSQRTShq: 10785 case ARM::VRSUBHNv2i32: 10786 case ARM::VRSUBHNv4i16: 10787 case ARM::VRSUBHNv8i8: 10788 case ARM::VSUBHNv2i32: 10789 case ARM::VSUBHNv4i16: 10790 case ARM::VSUBHNv8i8: 10791 case ARM::VSUBLsv2i64: 10792 case ARM::VSUBLsv4i32: 10793 case ARM::VSUBLsv8i16: 10794 case ARM::VSUBLuv2i64: 10795 case ARM::VSUBLuv4i32: 10796 case ARM::VSUBLuv8i16: 10797 case ARM::VSUBWsv2i64: 10798 case ARM::VSUBWsv4i32: 10799 case ARM::VSUBWsv8i16: 10800 case ARM::VSUBWuv2i64: 10801 case ARM::VSUBWuv4i32: 10802 case ARM::VSUBWuv8i16: 10803 case ARM::VSUBfd: 10804 case ARM::VSUBfq: 10805 case ARM::VSUBhd: 10806 case ARM::VSUBhq: 10807 case ARM::VSUBv16i8: 10808 case ARM::VSUBv1i64: 10809 case ARM::VSUBv2i32: 10810 case ARM::VSUBv2i64: 10811 case ARM::VSUBv4i16: 10812 case ARM::VSUBv4i32: 10813 case ARM::VSUBv8i16: 10814 case ARM::VSUBv8i8: 10815 case ARM::VTBL1: 10816 case ARM::VTBL2: 10817 case ARM::VTBL3: 10818 case ARM::VTBL4: 10819 case ARM::VTSTv16i8: 10820 case ARM::VTSTv2i32: 10821 case ARM::VTSTv4i16: 10822 case ARM::VTSTv4i32: 10823 case ARM::VTSTv8i16: 10824 case ARM::VTSTv8i8: { 10825 // op: Vd 10826 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10827 Value |= (op & UINT64_C(16)) << 18; 10828 Value |= (op & UINT64_C(15)) << 12; 10829 // op: Vn 10830 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10831 Value |= (op & UINT64_C(15)) << 16; 10832 Value |= (op & UINT64_C(16)) << 3; 10833 // op: Vm 10834 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10835 Value |= (op & UINT64_C(16)) << 1; 10836 Value |= (op & UINT64_C(15)); 10837 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10838 break; 10839 } 10840 case ARM::NEON_VMAXNMNDf: 10841 case ARM::NEON_VMAXNMNDh: 10842 case ARM::NEON_VMAXNMNQf: 10843 case ARM::NEON_VMAXNMNQh: 10844 case ARM::NEON_VMINNMNDf: 10845 case ARM::NEON_VMINNMNDh: 10846 case ARM::NEON_VMINNMNQf: 10847 case ARM::NEON_VMINNMNQh: { 10848 // op: Vd 10849 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10850 Value |= (op & UINT64_C(16)) << 18; 10851 Value |= (op & UINT64_C(15)) << 12; 10852 // op: Vn 10853 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10854 Value |= (op & UINT64_C(15)) << 16; 10855 Value |= (op & UINT64_C(16)) << 3; 10856 // op: Vm 10857 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10858 Value |= (op & UINT64_C(16)) << 1; 10859 Value |= (op & UINT64_C(15)); 10860 Value = NEONThumb2V8PostEncoder(MI, Value, STI); 10861 break; 10862 } 10863 case ARM::VMULLslsv2i32: 10864 case ARM::VMULLsluv2i32: 10865 case ARM::VMULslfd: 10866 case ARM::VMULslfq: 10867 case ARM::VMULslv2i32: 10868 case ARM::VMULslv4i32: 10869 case ARM::VQDMULHslv2i32: 10870 case ARM::VQDMULHslv4i32: 10871 case ARM::VQDMULLslv2i32: 10872 case ARM::VQRDMULHslv2i32: 10873 case ARM::VQRDMULHslv4i32: { 10874 // op: Vd 10875 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10876 Value |= (op & UINT64_C(16)) << 18; 10877 Value |= (op & UINT64_C(15)) << 12; 10878 // op: Vn 10879 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10880 Value |= (op & UINT64_C(15)) << 16; 10881 Value |= (op & UINT64_C(16)) << 3; 10882 // op: Vm 10883 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10884 op &= UINT64_C(15); 10885 Value |= op; 10886 // op: lane 10887 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10888 op &= UINT64_C(1); 10889 op <<= 5; 10890 Value |= op; 10891 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10892 break; 10893 } 10894 case ARM::VFMALQI: 10895 case ARM::VFMSLQI: { 10896 // op: Vd 10897 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10898 Value |= (op & UINT64_C(16)) << 18; 10899 Value |= (op & UINT64_C(15)) << 12; 10900 // op: Vn 10901 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10902 Value |= (op & UINT64_C(15)) << 16; 10903 Value |= (op & UINT64_C(16)) << 3; 10904 // op: Vm 10905 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10906 op &= UINT64_C(7); 10907 Value |= op; 10908 // op: idx 10909 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10910 Value |= (op & UINT64_C(2)) << 4; 10911 Value |= (op & UINT64_C(1)) << 3; 10912 break; 10913 } 10914 case ARM::VMULLslsv4i16: 10915 case ARM::VMULLsluv4i16: 10916 case ARM::VMULslhd: 10917 case ARM::VMULslhq: 10918 case ARM::VMULslv4i16: 10919 case ARM::VMULslv8i16: 10920 case ARM::VQDMULHslv4i16: 10921 case ARM::VQDMULHslv8i16: 10922 case ARM::VQDMULLslv4i16: 10923 case ARM::VQRDMULHslv4i16: 10924 case ARM::VQRDMULHslv8i16: { 10925 // op: Vd 10926 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10927 Value |= (op & UINT64_C(16)) << 18; 10928 Value |= (op & UINT64_C(15)) << 12; 10929 // op: Vn 10930 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10931 Value |= (op & UINT64_C(15)) << 16; 10932 Value |= (op & UINT64_C(16)) << 3; 10933 // op: Vm 10934 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10935 op &= UINT64_C(7); 10936 Value |= op; 10937 // op: lane 10938 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10939 Value |= (op & UINT64_C(2)) << 4; 10940 Value |= (op & UINT64_C(1)) << 3; 10941 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10942 break; 10943 } 10944 case ARM::VFMALDI: 10945 case ARM::VFMSLDI: { 10946 // op: Vd 10947 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10948 Value |= (op & UINT64_C(16)) << 18; 10949 Value |= (op & UINT64_C(15)) << 12; 10950 // op: Vn 10951 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10952 Value |= (op & UINT64_C(30)) << 15; 10953 Value |= (op & UINT64_C(1)) << 7; 10954 // op: Vm 10955 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10956 Value |= (op & UINT64_C(1)) << 5; 10957 Value |= (op & UINT64_C(14)) >> 1; 10958 // op: idx 10959 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10960 op &= UINT64_C(1); 10961 op <<= 3; 10962 Value |= op; 10963 break; 10964 } 10965 case ARM::VFMALD: 10966 case ARM::VFMSLD: { 10967 // op: Vd 10968 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10969 Value |= (op & UINT64_C(16)) << 18; 10970 Value |= (op & UINT64_C(15)) << 12; 10971 // op: Vn 10972 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10973 Value |= (op & UINT64_C(30)) << 15; 10974 Value |= (op & UINT64_C(1)) << 7; 10975 // op: Vm 10976 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10977 Value |= (op & UINT64_C(1)) << 5; 10978 Value |= (op & UINT64_C(30)) >> 1; 10979 break; 10980 } 10981 case ARM::VQRSHLsv16i8: 10982 case ARM::VQRSHLsv1i64: 10983 case ARM::VQRSHLsv2i32: 10984 case ARM::VQRSHLsv2i64: 10985 case ARM::VQRSHLsv4i16: 10986 case ARM::VQRSHLsv4i32: 10987 case ARM::VQRSHLsv8i16: 10988 case ARM::VQRSHLsv8i8: 10989 case ARM::VQRSHLuv16i8: 10990 case ARM::VQRSHLuv1i64: 10991 case ARM::VQRSHLuv2i32: 10992 case ARM::VQRSHLuv2i64: 10993 case ARM::VQRSHLuv4i16: 10994 case ARM::VQRSHLuv4i32: 10995 case ARM::VQRSHLuv8i16: 10996 case ARM::VQRSHLuv8i8: 10997 case ARM::VQSHLsv16i8: 10998 case ARM::VQSHLsv1i64: 10999 case ARM::VQSHLsv2i32: 11000 case ARM::VQSHLsv2i64: 11001 case ARM::VQSHLsv4i16: 11002 case ARM::VQSHLsv4i32: 11003 case ARM::VQSHLsv8i16: 11004 case ARM::VQSHLsv8i8: 11005 case ARM::VQSHLuv16i8: 11006 case ARM::VQSHLuv1i64: 11007 case ARM::VQSHLuv2i32: 11008 case ARM::VQSHLuv2i64: 11009 case ARM::VQSHLuv4i16: 11010 case ARM::VQSHLuv4i32: 11011 case ARM::VQSHLuv8i16: 11012 case ARM::VQSHLuv8i8: 11013 case ARM::VRSHLsv16i8: 11014 case ARM::VRSHLsv1i64: 11015 case ARM::VRSHLsv2i32: 11016 case ARM::VRSHLsv2i64: 11017 case ARM::VRSHLsv4i16: 11018 case ARM::VRSHLsv4i32: 11019 case ARM::VRSHLsv8i16: 11020 case ARM::VRSHLsv8i8: 11021 case ARM::VRSHLuv16i8: 11022 case ARM::VRSHLuv1i64: 11023 case ARM::VRSHLuv2i32: 11024 case ARM::VRSHLuv2i64: 11025 case ARM::VRSHLuv4i16: 11026 case ARM::VRSHLuv4i32: 11027 case ARM::VRSHLuv8i16: 11028 case ARM::VRSHLuv8i8: 11029 case ARM::VSHLsv16i8: 11030 case ARM::VSHLsv1i64: 11031 case ARM::VSHLsv2i32: 11032 case ARM::VSHLsv2i64: 11033 case ARM::VSHLsv4i16: 11034 case ARM::VSHLsv4i32: 11035 case ARM::VSHLsv8i16: 11036 case ARM::VSHLsv8i8: 11037 case ARM::VSHLuv16i8: 11038 case ARM::VSHLuv1i64: 11039 case ARM::VSHLuv2i32: 11040 case ARM::VSHLuv2i64: 11041 case ARM::VSHLuv4i16: 11042 case ARM::VSHLuv4i32: 11043 case ARM::VSHLuv8i16: 11044 case ARM::VSHLuv8i8: { 11045 // op: Vd 11046 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 11047 Value |= (op & UINT64_C(16)) << 18; 11048 Value |= (op & UINT64_C(15)) << 12; 11049 // op: Vn 11050 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11051 Value |= (op & UINT64_C(15)) << 16; 11052 Value |= (op & UINT64_C(16)) << 3; 11053 // op: Vm 11054 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 11055 Value |= (op & UINT64_C(16)) << 1; 11056 Value |= (op & UINT64_C(15)); 11057 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 11058 break; 11059 } 11060 case ARM::VCMLAv2f32: 11061 case ARM::VCMLAv4f16: 11062 case ARM::VCMLAv4f32: 11063 case ARM::VCMLAv8f16: { 11064 // op: Vd 11065 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 11066 Value |= (op & UINT64_C(16)) << 18; 11067 Value |= (op & UINT64_C(15)) << 12; 11068 // op: Vn 11069 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11070 Value |= (op & UINT64_C(15)) << 16; 11071 Value |= (op & UINT64_C(16)) << 3; 11072 // op: Vm 11073 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11074 Value |= (op & UINT64_C(16)) << 1; 11075 Value |= (op & UINT64_C(15)); 11076 // op: rot 11077 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11078 op &= UINT64_C(3); 11079 op <<= 23; 11080 Value |= op; 11081 break; 11082 } 11083 case ARM::VCMLAv2f32_indexed: 11084 case ARM::VCMLAv4f32_indexed: { 11085 // op: Vd 11086 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 11087 Value |= (op & UINT64_C(16)) << 18; 11088 Value |= (op & UINT64_C(15)) << 12; 11089 // op: Vn 11090 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11091 Value |= (op & UINT64_C(15)) << 16; 11092 Value |= (op & UINT64_C(16)) << 3; 11093 // op: Vm 11094 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11095 Value |= (op & UINT64_C(16)) << 1; 11096 Value |= (op & UINT64_C(15)); 11097 // op: rot 11098 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 11099 op &= UINT64_C(3); 11100 op <<= 20; 11101 Value |= op; 11102 break; 11103 } 11104 case ARM::SHA1C: 11105 case ARM::SHA1M: 11106 case ARM::SHA1P: 11107 case ARM::SHA1SU0: 11108 case ARM::SHA256H: 11109 case ARM::SHA256H2: 11110 case ARM::SHA256SU1: 11111 case ARM::VABALsv2i64: 11112 case ARM::VABALsv4i32: 11113 case ARM::VABALsv8i16: 11114 case ARM::VABALuv2i64: 11115 case ARM::VABALuv4i32: 11116 case ARM::VABALuv8i16: 11117 case ARM::VABAsv16i8: 11118 case ARM::VABAsv2i32: 11119 case ARM::VABAsv4i16: 11120 case ARM::VABAsv4i32: 11121 case ARM::VABAsv8i16: 11122 case ARM::VABAsv8i8: 11123 case ARM::VABAuv16i8: 11124 case ARM::VABAuv2i32: 11125 case ARM::VABAuv4i16: 11126 case ARM::VABAuv4i32: 11127 case ARM::VABAuv8i16: 11128 case ARM::VABAuv8i8: 11129 case ARM::VBIFd: 11130 case ARM::VBIFq: 11131 case ARM::VBITd: 11132 case ARM::VBITq: 11133 case ARM::VBSLd: 11134 case ARM::VBSLq: 11135 case ARM::VFMAfd: 11136 case ARM::VFMAfq: 11137 case ARM::VFMAhd: 11138 case ARM::VFMAhq: 11139 case ARM::VFMSfd: 11140 case ARM::VFMSfq: 11141 case ARM::VFMShd: 11142 case ARM::VFMShq: 11143 case ARM::VMLALsv2i64: 11144 case ARM::VMLALsv4i32: 11145 case ARM::VMLALsv8i16: 11146 case ARM::VMLALuv2i64: 11147 case ARM::VMLALuv4i32: 11148 case ARM::VMLALuv8i16: 11149 case ARM::VMLAfd: 11150 case ARM::VMLAfq: 11151 case ARM::VMLAhd: 11152 case ARM::VMLAhq: 11153 case ARM::VMLAv16i8: 11154 case ARM::VMLAv2i32: 11155 case ARM::VMLAv4i16: 11156 case ARM::VMLAv4i32: 11157 case ARM::VMLAv8i16: 11158 case ARM::VMLAv8i8: 11159 case ARM::VMLSLsv2i64: 11160 case ARM::VMLSLsv4i32: 11161 case ARM::VMLSLsv8i16: 11162 case ARM::VMLSLuv2i64: 11163 case ARM::VMLSLuv4i32: 11164 case ARM::VMLSLuv8i16: 11165 case ARM::VMLSfd: 11166 case ARM::VMLSfq: 11167 case ARM::VMLShd: 11168 case ARM::VMLShq: 11169 case ARM::VMLSv16i8: 11170 case ARM::VMLSv2i32: 11171 case ARM::VMLSv4i16: 11172 case ARM::VMLSv4i32: 11173 case ARM::VMLSv8i16: 11174 case ARM::VMLSv8i8: 11175 case ARM::VQDMLALv2i64: 11176 case ARM::VQDMLALv4i32: 11177 case ARM::VQDMLSLv2i64: 11178 case ARM::VQDMLSLv4i32: 11179 case ARM::VQRDMLAHv2i32: 11180 case ARM::VQRDMLAHv4i16: 11181 case ARM::VQRDMLAHv4i32: 11182 case ARM::VQRDMLAHv8i16: 11183 case ARM::VQRDMLSHv2i32: 11184 case ARM::VQRDMLSHv4i16: 11185 case ARM::VQRDMLSHv4i32: 11186 case ARM::VQRDMLSHv8i16: 11187 case ARM::VTBX1: 11188 case ARM::VTBX2: 11189 case ARM::VTBX3: 11190 case ARM::VTBX4: { 11191 // op: Vd 11192 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 11193 Value |= (op & UINT64_C(16)) << 18; 11194 Value |= (op & UINT64_C(15)) << 12; 11195 // op: Vn 11196 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11197 Value |= (op & UINT64_C(15)) << 16; 11198 Value |= (op & UINT64_C(16)) << 3; 11199 // op: Vm 11200 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11201 Value |= (op & UINT64_C(16)) << 1; 11202 Value |= (op & UINT64_C(15)); 11203 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 11204 break; 11205 } 11206 case ARM::VMLALslsv2i32: 11207 case ARM::VMLALsluv2i32: 11208 case ARM::VMLAslfd: 11209 case ARM::VMLAslfq: 11210 case ARM::VMLAslv2i32: 11211 case ARM::VMLAslv4i32: 11212 case ARM::VMLSLslsv2i32: 11213 case ARM::VMLSLsluv2i32: 11214 case ARM::VMLSslfd: 11215 case ARM::VMLSslfq: 11216 case ARM::VMLSslv2i32: 11217 case ARM::VMLSslv4i32: 11218 case ARM::VQDMLALslv2i32: 11219 case ARM::VQDMLSLslv2i32: 11220 case ARM::VQRDMLAHslv2i32: 11221 case ARM::VQRDMLAHslv4i32: 11222 case ARM::VQRDMLSHslv2i32: 11223 case ARM::VQRDMLSHslv4i32: { 11224 // op: Vd 11225 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 11226 Value |= (op & UINT64_C(16)) << 18; 11227 Value |= (op & UINT64_C(15)) << 12; 11228 // op: Vn 11229 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11230 Value |= (op & UINT64_C(15)) << 16; 11231 Value |= (op & UINT64_C(16)) << 3; 11232 // op: Vm 11233 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11234 op &= UINT64_C(15); 11235 Value |= op; 11236 // op: lane 11237 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11238 op &= UINT64_C(1); 11239 op <<= 5; 11240 Value |= op; 11241 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 11242 break; 11243 } 11244 case ARM::VCMLAv4f16_indexed: 11245 case ARM::VCMLAv8f16_indexed: { 11246 // op: Vd 11247 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 11248 Value |= (op & UINT64_C(16)) << 18; 11249 Value |= (op & UINT64_C(15)) << 12; 11250 // op: Vn 11251 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11252 Value |= (op & UINT64_C(15)) << 16; 11253 Value |= (op & UINT64_C(16)) << 3; 11254 // op: Vm 11255 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11256 op &= UINT64_C(15); 11257 Value |= op; 11258 // op: rot 11259 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 11260 op &= UINT64_C(3); 11261 op <<= 20; 11262 Value |= op; 11263 // op: lane 11264 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11265 op &= UINT64_C(1); 11266 op <<= 5; 11267 Value |= op; 11268 break; 11269 } 11270 case ARM::VMLALslsv4i16: 11271 case ARM::VMLALsluv4i16: 11272 case ARM::VMLAslhd: 11273 case ARM::VMLAslhq: 11274 case ARM::VMLAslv4i16: 11275 case ARM::VMLAslv8i16: 11276 case ARM::VMLSLslsv4i16: 11277 case ARM::VMLSLsluv4i16: 11278 case ARM::VMLSslhd: 11279 case ARM::VMLSslhq: 11280 case ARM::VMLSslv4i16: 11281 case ARM::VMLSslv8i16: 11282 case ARM::VQDMLALslv4i16: 11283 case ARM::VQDMLSLslv4i16: 11284 case ARM::VQRDMLAHslv4i16: 11285 case ARM::VQRDMLAHslv8i16: 11286 case ARM::VQRDMLSHslv4i16: 11287 case ARM::VQRDMLSHslv8i16: { 11288 // op: Vd 11289 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 11290 Value |= (op & UINT64_C(16)) << 18; 11291 Value |= (op & UINT64_C(15)) << 12; 11292 // op: Vn 11293 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11294 Value |= (op & UINT64_C(15)) << 16; 11295 Value |= (op & UINT64_C(16)) << 3; 11296 // op: Vm 11297 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11298 op &= UINT64_C(7); 11299 Value |= op; 11300 // op: lane 11301 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11302 Value |= (op & UINT64_C(2)) << 4; 11303 Value |= (op & UINT64_C(1)) << 3; 11304 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 11305 break; 11306 } 11307 case ARM::BF16VDOTS_VDOTD: 11308 case ARM::BF16VDOTS_VDOTQ: 11309 case ARM::VBF16MALBQ: 11310 case ARM::VBF16MALTQ: 11311 case ARM::VMMLA: 11312 case ARM::VSDOTD: 11313 case ARM::VSDOTQ: 11314 case ARM::VSMMLA: 11315 case ARM::VUDOTD: 11316 case ARM::VUDOTQ: 11317 case ARM::VUMMLA: 11318 case ARM::VUSDOTD: 11319 case ARM::VUSDOTQ: 11320 case ARM::VUSMMLA: { 11321 // op: Vd 11322 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 11323 Value |= (op & UINT64_C(16)) << 18; 11324 Value |= (op & UINT64_C(15)) << 12; 11325 // op: Vn 11326 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11327 Value |= (op & UINT64_C(15)) << 16; 11328 Value |= (op & UINT64_C(16)) << 3; 11329 // op: Vm 11330 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11331 Value |= (op & UINT64_C(16)) << 1; 11332 Value |= (op & UINT64_C(15)); 11333 break; 11334 } 11335 case ARM::BF16VDOTI_VDOTD: 11336 case ARM::BF16VDOTI_VDOTQ: 11337 case ARM::VSDOTDI: 11338 case ARM::VSDOTQI: 11339 case ARM::VSUDOTDI: 11340 case ARM::VSUDOTQI: 11341 case ARM::VUDOTDI: 11342 case ARM::VUDOTQI: 11343 case ARM::VUSDOTDI: 11344 case ARM::VUSDOTQI: { 11345 // op: Vd 11346 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 11347 Value |= (op & UINT64_C(16)) << 18; 11348 Value |= (op & UINT64_C(15)) << 12; 11349 // op: Vn 11350 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11351 Value |= (op & UINT64_C(15)) << 16; 11352 Value |= (op & UINT64_C(16)) << 3; 11353 // op: Vm 11354 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11355 op &= UINT64_C(15); 11356 Value |= op; 11357 // op: lane 11358 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11359 op &= UINT64_C(1); 11360 op <<= 5; 11361 Value |= op; 11362 break; 11363 } 11364 case ARM::VBF16MALBQI: 11365 case ARM::VBF16MALTQI: { 11366 // op: Vd 11367 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 11368 Value |= (op & UINT64_C(16)) << 18; 11369 Value |= (op & UINT64_C(15)) << 12; 11370 // op: Vn 11371 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11372 Value |= (op & UINT64_C(15)) << 16; 11373 Value |= (op & UINT64_C(16)) << 3; 11374 // op: Vm 11375 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11376 op &= UINT64_C(7); 11377 Value |= op; 11378 // op: idx 11379 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11380 Value |= (op & UINT64_C(2)) << 4; 11381 Value |= (op & UINT64_C(1)) << 3; 11382 break; 11383 } 11384 case ARM::VST1LNd16: { 11385 // op: Vd 11386 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11387 Value |= (op & UINT64_C(16)) << 18; 11388 Value |= (op & UINT64_C(15)) << 12; 11389 // op: Rn 11390 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11391 Value |= (op & UINT64_C(15)) << 16; 11392 Value |= (op & UINT64_C(16)); 11393 // op: lane 11394 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11395 op &= UINT64_C(3); 11396 op <<= 6; 11397 Value |= op; 11398 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11399 break; 11400 } 11401 case ARM::VST2LNd32: 11402 case ARM::VST2LNq32: { 11403 // op: Vd 11404 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11405 Value |= (op & UINT64_C(16)) << 18; 11406 Value |= (op & UINT64_C(15)) << 12; 11407 // op: Rn 11408 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11409 Value |= (op & UINT64_C(15)) << 16; 11410 Value |= (op & UINT64_C(16)); 11411 // op: lane 11412 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11413 op &= UINT64_C(1); 11414 op <<= 7; 11415 Value |= op; 11416 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11417 break; 11418 } 11419 case ARM::VST2LNd16: 11420 case ARM::VST2LNq16: { 11421 // op: Vd 11422 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11423 Value |= (op & UINT64_C(16)) << 18; 11424 Value |= (op & UINT64_C(15)) << 12; 11425 // op: Rn 11426 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11427 Value |= (op & UINT64_C(15)) << 16; 11428 Value |= (op & UINT64_C(16)); 11429 // op: lane 11430 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11431 op &= UINT64_C(3); 11432 op <<= 6; 11433 Value |= op; 11434 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11435 break; 11436 } 11437 case ARM::VST2LNd8: { 11438 // op: Vd 11439 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11440 Value |= (op & UINT64_C(16)) << 18; 11441 Value |= (op & UINT64_C(15)) << 12; 11442 // op: Rn 11443 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11444 Value |= (op & UINT64_C(15)) << 16; 11445 Value |= (op & UINT64_C(16)); 11446 // op: lane 11447 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11448 op &= UINT64_C(7); 11449 op <<= 5; 11450 Value |= op; 11451 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11452 break; 11453 } 11454 case ARM::VST4LNd16: 11455 case ARM::VST4LNq16: { 11456 // op: Vd 11457 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11458 Value |= (op & UINT64_C(16)) << 18; 11459 Value |= (op & UINT64_C(15)) << 12; 11460 // op: Rn 11461 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11462 Value |= (op & UINT64_C(15)) << 16; 11463 Value |= (op & UINT64_C(16)); 11464 // op: lane 11465 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 11466 op &= UINT64_C(3); 11467 op <<= 6; 11468 Value |= op; 11469 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11470 break; 11471 } 11472 case ARM::VST4LNd8: { 11473 // op: Vd 11474 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11475 Value |= (op & UINT64_C(16)) << 18; 11476 Value |= (op & UINT64_C(15)) << 12; 11477 // op: Rn 11478 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11479 Value |= (op & UINT64_C(15)) << 16; 11480 Value |= (op & UINT64_C(16)); 11481 // op: lane 11482 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 11483 op &= UINT64_C(7); 11484 op <<= 5; 11485 Value |= op; 11486 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11487 break; 11488 } 11489 case ARM::VST1d16: 11490 case ARM::VST1d16T: 11491 case ARM::VST1d32: 11492 case ARM::VST1d32T: 11493 case ARM::VST1d64: 11494 case ARM::VST1d64T: 11495 case ARM::VST1d8: 11496 case ARM::VST1d8T: 11497 case ARM::VST3d16: 11498 case ARM::VST3d32: 11499 case ARM::VST3d8: 11500 case ARM::VST3q16: 11501 case ARM::VST3q32: 11502 case ARM::VST3q8: { 11503 // op: Vd 11504 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11505 Value |= (op & UINT64_C(16)) << 18; 11506 Value |= (op & UINT64_C(15)) << 12; 11507 // op: Rn 11508 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11509 Value |= (op & UINT64_C(15)) << 16; 11510 Value |= (op & UINT64_C(16)); 11511 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11512 break; 11513 } 11514 case ARM::VST4LNd32: 11515 case ARM::VST4LNq32: { 11516 // op: Vd 11517 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11518 Value |= (op & UINT64_C(16)) << 18; 11519 Value |= (op & UINT64_C(15)) << 12; 11520 // op: Rn 11521 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11522 Value |= (op & UINT64_C(15)) << 16; 11523 Value |= (op & UINT64_C(48)); 11524 // op: lane 11525 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 11526 op &= UINT64_C(1); 11527 op <<= 7; 11528 Value |= op; 11529 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11530 break; 11531 } 11532 case ARM::VST1d16Q: 11533 case ARM::VST1d32Q: 11534 case ARM::VST1d64Q: 11535 case ARM::VST1d8Q: 11536 case ARM::VST1q16: 11537 case ARM::VST1q32: 11538 case ARM::VST1q64: 11539 case ARM::VST1q8: 11540 case ARM::VST2b16: 11541 case ARM::VST2b32: 11542 case ARM::VST2b8: 11543 case ARM::VST2d16: 11544 case ARM::VST2d32: 11545 case ARM::VST2d8: 11546 case ARM::VST2q16: 11547 case ARM::VST2q32: 11548 case ARM::VST2q8: 11549 case ARM::VST4d16: 11550 case ARM::VST4d32: 11551 case ARM::VST4d8: 11552 case ARM::VST4q16: 11553 case ARM::VST4q32: 11554 case ARM::VST4q8: { 11555 // op: Vd 11556 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11557 Value |= (op & UINT64_C(16)) << 18; 11558 Value |= (op & UINT64_C(15)) << 12; 11559 // op: Rn 11560 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11561 Value |= (op & UINT64_C(15)) << 16; 11562 Value |= (op & UINT64_C(48)); 11563 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11564 break; 11565 } 11566 case ARM::VST1LNd8: { 11567 // op: Vd 11568 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11569 Value |= (op & UINT64_C(16)) << 18; 11570 Value |= (op & UINT64_C(15)) << 12; 11571 // op: Rn 11572 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11573 op &= UINT64_C(15); 11574 op <<= 16; 11575 Value |= op; 11576 // op: lane 11577 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11578 op &= UINT64_C(7); 11579 op <<= 5; 11580 Value |= op; 11581 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11582 break; 11583 } 11584 case ARM::VST3LNd32: 11585 case ARM::VST3LNq32: { 11586 // op: Vd 11587 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11588 Value |= (op & UINT64_C(16)) << 18; 11589 Value |= (op & UINT64_C(15)) << 12; 11590 // op: Rn 11591 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11592 op &= UINT64_C(15); 11593 op <<= 16; 11594 Value |= op; 11595 // op: lane 11596 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 11597 op &= UINT64_C(1); 11598 op <<= 7; 11599 Value |= op; 11600 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11601 break; 11602 } 11603 case ARM::VST3LNd16: 11604 case ARM::VST3LNq16: { 11605 // op: Vd 11606 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11607 Value |= (op & UINT64_C(16)) << 18; 11608 Value |= (op & UINT64_C(15)) << 12; 11609 // op: Rn 11610 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11611 op &= UINT64_C(15); 11612 op <<= 16; 11613 Value |= op; 11614 // op: lane 11615 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 11616 op &= UINT64_C(3); 11617 op <<= 6; 11618 Value |= op; 11619 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11620 break; 11621 } 11622 case ARM::VST3LNd8: { 11623 // op: Vd 11624 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11625 Value |= (op & UINT64_C(16)) << 18; 11626 Value |= (op & UINT64_C(15)) << 12; 11627 // op: Rn 11628 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11629 op &= UINT64_C(15); 11630 op <<= 16; 11631 Value |= op; 11632 // op: lane 11633 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 11634 op &= UINT64_C(7); 11635 op <<= 5; 11636 Value |= op; 11637 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11638 break; 11639 } 11640 case ARM::VST1LNd32: { 11641 // op: Vd 11642 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11643 Value |= (op & UINT64_C(16)) << 18; 11644 Value |= (op & UINT64_C(15)) << 12; 11645 // op: Rn 11646 op = getAddrMode6OneLane32AddressOpValue(MI, 0, Fixups, STI); 11647 Value |= (op & UINT64_C(15)) << 16; 11648 Value |= (op & UINT64_C(48)); 11649 // op: lane 11650 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11651 op &= UINT64_C(1); 11652 op <<= 7; 11653 Value |= op; 11654 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11655 break; 11656 } 11657 case ARM::VST1d16wb_fixed: 11658 case ARM::VST1d32wb_fixed: 11659 case ARM::VST1d64wb_fixed: 11660 case ARM::VST1d8wb_fixed: { 11661 // op: Vd 11662 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11663 Value |= (op & UINT64_C(16)) << 18; 11664 Value |= (op & UINT64_C(15)) << 12; 11665 // op: Rn 11666 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11667 Value |= (op & UINT64_C(15)) << 16; 11668 Value |= (op & UINT64_C(16)); 11669 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11670 break; 11671 } 11672 case ARM::VST1d16Qwb_fixed: 11673 case ARM::VST1d16Twb_fixed: 11674 case ARM::VST1d32Qwb_fixed: 11675 case ARM::VST1d32Twb_fixed: 11676 case ARM::VST1d64Qwb_fixed: 11677 case ARM::VST1d64Twb_fixed: 11678 case ARM::VST1d8Qwb_fixed: 11679 case ARM::VST1d8Twb_fixed: 11680 case ARM::VST1q16wb_fixed: 11681 case ARM::VST1q32wb_fixed: 11682 case ARM::VST1q64wb_fixed: 11683 case ARM::VST1q8wb_fixed: 11684 case ARM::VST2b16wb_fixed: 11685 case ARM::VST2b32wb_fixed: 11686 case ARM::VST2b8wb_fixed: 11687 case ARM::VST2d16wb_fixed: 11688 case ARM::VST2d32wb_fixed: 11689 case ARM::VST2d8wb_fixed: 11690 case ARM::VST2q16wb_fixed: 11691 case ARM::VST2q32wb_fixed: 11692 case ARM::VST2q8wb_fixed: { 11693 // op: Vd 11694 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11695 Value |= (op & UINT64_C(16)) << 18; 11696 Value |= (op & UINT64_C(15)) << 12; 11697 // op: Rn 11698 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11699 Value |= (op & UINT64_C(15)) << 16; 11700 Value |= (op & UINT64_C(48)); 11701 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11702 break; 11703 } 11704 case ARM::VST1LNd16_UPD: { 11705 // op: Vd 11706 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11707 Value |= (op & UINT64_C(16)) << 18; 11708 Value |= (op & UINT64_C(15)) << 12; 11709 // op: Rn 11710 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11711 Value |= (op & UINT64_C(15)) << 16; 11712 Value |= (op & UINT64_C(16)); 11713 // op: Rm 11714 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11715 op &= UINT64_C(15); 11716 Value |= op; 11717 // op: lane 11718 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 11719 op &= UINT64_C(3); 11720 op <<= 6; 11721 Value |= op; 11722 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11723 break; 11724 } 11725 case ARM::VST2LNd32_UPD: 11726 case ARM::VST2LNq32_UPD: { 11727 // op: Vd 11728 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11729 Value |= (op & UINT64_C(16)) << 18; 11730 Value |= (op & UINT64_C(15)) << 12; 11731 // op: Rn 11732 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11733 Value |= (op & UINT64_C(15)) << 16; 11734 Value |= (op & UINT64_C(16)); 11735 // op: Rm 11736 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11737 op &= UINT64_C(15); 11738 Value |= op; 11739 // op: lane 11740 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 11741 op &= UINT64_C(1); 11742 op <<= 7; 11743 Value |= op; 11744 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11745 break; 11746 } 11747 case ARM::VST2LNd16_UPD: 11748 case ARM::VST2LNq16_UPD: { 11749 // op: Vd 11750 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11751 Value |= (op & UINT64_C(16)) << 18; 11752 Value |= (op & UINT64_C(15)) << 12; 11753 // op: Rn 11754 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11755 Value |= (op & UINT64_C(15)) << 16; 11756 Value |= (op & UINT64_C(16)); 11757 // op: Rm 11758 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11759 op &= UINT64_C(15); 11760 Value |= op; 11761 // op: lane 11762 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 11763 op &= UINT64_C(3); 11764 op <<= 6; 11765 Value |= op; 11766 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11767 break; 11768 } 11769 case ARM::VST2LNd8_UPD: { 11770 // op: Vd 11771 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11772 Value |= (op & UINT64_C(16)) << 18; 11773 Value |= (op & UINT64_C(15)) << 12; 11774 // op: Rn 11775 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11776 Value |= (op & UINT64_C(15)) << 16; 11777 Value |= (op & UINT64_C(16)); 11778 // op: Rm 11779 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11780 op &= UINT64_C(15); 11781 Value |= op; 11782 // op: lane 11783 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 11784 op &= UINT64_C(7); 11785 op <<= 5; 11786 Value |= op; 11787 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11788 break; 11789 } 11790 case ARM::VST4LNd16_UPD: 11791 case ARM::VST4LNq16_UPD: { 11792 // op: Vd 11793 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11794 Value |= (op & UINT64_C(16)) << 18; 11795 Value |= (op & UINT64_C(15)) << 12; 11796 // op: Rn 11797 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11798 Value |= (op & UINT64_C(15)) << 16; 11799 Value |= (op & UINT64_C(16)); 11800 // op: Rm 11801 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11802 op &= UINT64_C(15); 11803 Value |= op; 11804 // op: lane 11805 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 11806 op &= UINT64_C(3); 11807 op <<= 6; 11808 Value |= op; 11809 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11810 break; 11811 } 11812 case ARM::VST4LNd8_UPD: { 11813 // op: Vd 11814 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11815 Value |= (op & UINT64_C(16)) << 18; 11816 Value |= (op & UINT64_C(15)) << 12; 11817 // op: Rn 11818 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11819 Value |= (op & UINT64_C(15)) << 16; 11820 Value |= (op & UINT64_C(16)); 11821 // op: Rm 11822 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11823 op &= UINT64_C(15); 11824 Value |= op; 11825 // op: lane 11826 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 11827 op &= UINT64_C(7); 11828 op <<= 5; 11829 Value |= op; 11830 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11831 break; 11832 } 11833 case ARM::VST3d16_UPD: 11834 case ARM::VST3d32_UPD: 11835 case ARM::VST3d8_UPD: 11836 case ARM::VST3q16_UPD: 11837 case ARM::VST3q32_UPD: 11838 case ARM::VST3q8_UPD: { 11839 // op: Vd 11840 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11841 Value |= (op & UINT64_C(16)) << 18; 11842 Value |= (op & UINT64_C(15)) << 12; 11843 // op: Rn 11844 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11845 Value |= (op & UINT64_C(15)) << 16; 11846 Value |= (op & UINT64_C(16)); 11847 // op: Rm 11848 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11849 op &= UINT64_C(15); 11850 Value |= op; 11851 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11852 break; 11853 } 11854 case ARM::VST1d16wb_register: 11855 case ARM::VST1d32wb_register: 11856 case ARM::VST1d64wb_register: 11857 case ARM::VST1d8wb_register: { 11858 // op: Vd 11859 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11860 Value |= (op & UINT64_C(16)) << 18; 11861 Value |= (op & UINT64_C(15)) << 12; 11862 // op: Rn 11863 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11864 Value |= (op & UINT64_C(15)) << 16; 11865 Value |= (op & UINT64_C(16)); 11866 // op: Rm 11867 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11868 op &= UINT64_C(15); 11869 Value |= op; 11870 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11871 break; 11872 } 11873 case ARM::VST4LNd32_UPD: 11874 case ARM::VST4LNq32_UPD: { 11875 // op: Vd 11876 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11877 Value |= (op & UINT64_C(16)) << 18; 11878 Value |= (op & UINT64_C(15)) << 12; 11879 // op: Rn 11880 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11881 Value |= (op & UINT64_C(15)) << 16; 11882 Value |= (op & UINT64_C(48)); 11883 // op: Rm 11884 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11885 op &= UINT64_C(15); 11886 Value |= op; 11887 // op: lane 11888 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 11889 op &= UINT64_C(1); 11890 op <<= 7; 11891 Value |= op; 11892 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11893 break; 11894 } 11895 case ARM::VST4d16_UPD: 11896 case ARM::VST4d32_UPD: 11897 case ARM::VST4d8_UPD: 11898 case ARM::VST4q16_UPD: 11899 case ARM::VST4q32_UPD: 11900 case ARM::VST4q8_UPD: { 11901 // op: Vd 11902 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11903 Value |= (op & UINT64_C(16)) << 18; 11904 Value |= (op & UINT64_C(15)) << 12; 11905 // op: Rn 11906 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11907 Value |= (op & UINT64_C(15)) << 16; 11908 Value |= (op & UINT64_C(48)); 11909 // op: Rm 11910 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11911 op &= UINT64_C(15); 11912 Value |= op; 11913 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11914 break; 11915 } 11916 case ARM::VST1d16Qwb_register: 11917 case ARM::VST1d16Twb_register: 11918 case ARM::VST1d32Qwb_register: 11919 case ARM::VST1d32Twb_register: 11920 case ARM::VST1d64Qwb_register: 11921 case ARM::VST1d64Twb_register: 11922 case ARM::VST1d8Qwb_register: 11923 case ARM::VST1d8Twb_register: 11924 case ARM::VST1q16wb_register: 11925 case ARM::VST1q32wb_register: 11926 case ARM::VST1q64wb_register: 11927 case ARM::VST1q8wb_register: 11928 case ARM::VST2b16wb_register: 11929 case ARM::VST2b32wb_register: 11930 case ARM::VST2b8wb_register: 11931 case ARM::VST2d16wb_register: 11932 case ARM::VST2d32wb_register: 11933 case ARM::VST2d8wb_register: 11934 case ARM::VST2q16wb_register: 11935 case ARM::VST2q32wb_register: 11936 case ARM::VST2q8wb_register: { 11937 // op: Vd 11938 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11939 Value |= (op & UINT64_C(16)) << 18; 11940 Value |= (op & UINT64_C(15)) << 12; 11941 // op: Rn 11942 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11943 Value |= (op & UINT64_C(15)) << 16; 11944 Value |= (op & UINT64_C(48)); 11945 // op: Rm 11946 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11947 op &= UINT64_C(15); 11948 Value |= op; 11949 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11950 break; 11951 } 11952 case ARM::VST1LNd8_UPD: { 11953 // op: Vd 11954 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11955 Value |= (op & UINT64_C(16)) << 18; 11956 Value |= (op & UINT64_C(15)) << 12; 11957 // op: Rn 11958 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11959 op &= UINT64_C(15); 11960 op <<= 16; 11961 Value |= op; 11962 // op: Rm 11963 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11964 op &= UINT64_C(15); 11965 Value |= op; 11966 // op: lane 11967 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 11968 op &= UINT64_C(7); 11969 op <<= 5; 11970 Value |= op; 11971 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11972 break; 11973 } 11974 case ARM::VST3LNd32_UPD: 11975 case ARM::VST3LNq32_UPD: { 11976 // op: Vd 11977 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11978 Value |= (op & UINT64_C(16)) << 18; 11979 Value |= (op & UINT64_C(15)) << 12; 11980 // op: Rn 11981 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11982 op &= UINT64_C(15); 11983 op <<= 16; 11984 Value |= op; 11985 // op: Rm 11986 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11987 op &= UINT64_C(15); 11988 Value |= op; 11989 // op: lane 11990 op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); 11991 op &= UINT64_C(1); 11992 op <<= 7; 11993 Value |= op; 11994 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11995 break; 11996 } 11997 case ARM::VST3LNd16_UPD: 11998 case ARM::VST3LNq16_UPD: { 11999 // op: Vd 12000 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 12001 Value |= (op & UINT64_C(16)) << 18; 12002 Value |= (op & UINT64_C(15)) << 12; 12003 // op: Rn 12004 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 12005 op &= UINT64_C(15); 12006 op <<= 16; 12007 Value |= op; 12008 // op: Rm 12009 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 12010 op &= UINT64_C(15); 12011 Value |= op; 12012 // op: lane 12013 op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); 12014 op &= UINT64_C(3); 12015 op <<= 6; 12016 Value |= op; 12017 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 12018 break; 12019 } 12020 case ARM::VST3LNd8_UPD: { 12021 // op: Vd 12022 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 12023 Value |= (op & UINT64_C(16)) << 18; 12024 Value |= (op & UINT64_C(15)) << 12; 12025 // op: Rn 12026 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 12027 op &= UINT64_C(15); 12028 op <<= 16; 12029 Value |= op; 12030 // op: Rm 12031 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 12032 op &= UINT64_C(15); 12033 Value |= op; 12034 // op: lane 12035 op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); 12036 op &= UINT64_C(7); 12037 op <<= 5; 12038 Value |= op; 12039 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 12040 break; 12041 } 12042 case ARM::VST1LNd32_UPD: { 12043 // op: Vd 12044 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 12045 Value |= (op & UINT64_C(16)) << 18; 12046 Value |= (op & UINT64_C(15)) << 12; 12047 // op: Rn 12048 op = getAddrMode6OneLane32AddressOpValue(MI, 1, Fixups, STI); 12049 Value |= (op & UINT64_C(15)) << 16; 12050 Value |= (op & UINT64_C(48)); 12051 // op: Rm 12052 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 12053 op &= UINT64_C(15); 12054 Value |= op; 12055 // op: lane 12056 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 12057 op &= UINT64_C(1); 12058 op <<= 7; 12059 Value |= op; 12060 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 12061 break; 12062 } 12063 case ARM::LDC2L_OFFSET: 12064 case ARM::LDC2L_PRE: 12065 case ARM::LDC2_OFFSET: 12066 case ARM::LDC2_PRE: 12067 case ARM::STC2L_OFFSET: 12068 case ARM::STC2L_PRE: 12069 case ARM::STC2_OFFSET: 12070 case ARM::STC2_PRE: 12071 case ARM::t2LDC2L_OFFSET: 12072 case ARM::t2LDC2L_PRE: 12073 case ARM::t2LDC2_OFFSET: 12074 case ARM::t2LDC2_PRE: 12075 case ARM::t2LDCL_OFFSET: 12076 case ARM::t2LDCL_PRE: 12077 case ARM::t2LDC_OFFSET: 12078 case ARM::t2LDC_PRE: 12079 case ARM::t2STC2L_OFFSET: 12080 case ARM::t2STC2L_PRE: 12081 case ARM::t2STC2_OFFSET: 12082 case ARM::t2STC2_PRE: 12083 case ARM::t2STCL_OFFSET: 12084 case ARM::t2STCL_PRE: 12085 case ARM::t2STC_OFFSET: 12086 case ARM::t2STC_PRE: { 12087 // op: addr 12088 op = getAddrMode5OpValue(MI, 2, Fixups, STI); 12089 Value |= (op & UINT64_C(256)) << 15; 12090 Value |= (op & UINT64_C(7680)) << 7; 12091 Value |= (op & UINT64_C(255)); 12092 // op: cop 12093 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12094 op &= UINT64_C(15); 12095 op <<= 8; 12096 Value |= op; 12097 // op: CRd 12098 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12099 op &= UINT64_C(15); 12100 op <<= 12; 12101 Value |= op; 12102 break; 12103 } 12104 case ARM::t2PLDWi12: 12105 case ARM::t2PLDi12: 12106 case ARM::t2PLIi12: { 12107 // op: addr 12108 op = getAddrModeImm12OpValue(MI, 0, Fixups, STI); 12109 Value |= (op & UINT64_C(122880)) << 3; 12110 Value |= (op & UINT64_C(4095)); 12111 break; 12112 } 12113 case ARM::PLDWi12: 12114 case ARM::PLDi12: 12115 case ARM::PLIi12: { 12116 // op: addr 12117 op = getAddrModeImm12OpValue(MI, 0, Fixups, STI); 12118 Value |= (op & UINT64_C(4096)) << 11; 12119 Value |= (op & UINT64_C(122880)) << 3; 12120 Value |= (op & UINT64_C(4095)); 12121 break; 12122 } 12123 case ARM::t2PLDpci: 12124 case ARM::t2PLIpci: { 12125 // op: addr 12126 op = getAddrModeImm12OpValue(MI, 0, Fixups, STI); 12127 Value |= (op & UINT64_C(4096)) << 11; 12128 Value |= (op & UINT64_C(4095)); 12129 break; 12130 } 12131 case ARM::t2LDAEXB: 12132 case ARM::t2LDAEXH: 12133 case ARM::t2LDREXB: 12134 case ARM::t2LDREXH: { 12135 // op: addr 12136 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12137 op &= UINT64_C(15); 12138 op <<= 16; 12139 Value |= op; 12140 // op: Rt 12141 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12142 op &= UINT64_C(15); 12143 op <<= 12; 12144 Value |= op; 12145 break; 12146 } 12147 case ARM::t2LDAEXD: 12148 case ARM::t2LDREXD: { 12149 // op: addr 12150 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12151 op &= UINT64_C(15); 12152 op <<= 16; 12153 Value |= op; 12154 // op: Rt 12155 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12156 op &= UINT64_C(15); 12157 op <<= 12; 12158 Value |= op; 12159 // op: Rt2 12160 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12161 op &= UINT64_C(15); 12162 op <<= 8; 12163 Value |= op; 12164 break; 12165 } 12166 case ARM::t2PLDWi8: 12167 case ARM::t2PLDi8: 12168 case ARM::t2PLIi8: { 12169 // op: addr 12170 op = getT2AddrModeImmOpValue<8,0>(MI, 0, Fixups, STI); 12171 Value |= (op & UINT64_C(7680)) << 7; 12172 Value |= (op & UINT64_C(255)); 12173 break; 12174 } 12175 case ARM::t2PLDWs: 12176 case ARM::t2PLDs: 12177 case ARM::t2PLIs: { 12178 // op: addr 12179 op = getT2AddrModeSORegOpValue(MI, 0, Fixups, STI); 12180 Value |= (op & UINT64_C(960)) << 10; 12181 Value |= (op & UINT64_C(3)) << 4; 12182 Value |= (op & UINT64_C(60)) >> 2; 12183 break; 12184 } 12185 case ARM::t2BFLr: 12186 case ARM::t2BFr: { 12187 // op: b_label 12188 op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, 0, Fixups, STI); 12189 op &= UINT64_C(15); 12190 op <<= 23; 12191 Value |= op; 12192 // op: Rn 12193 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12194 op &= UINT64_C(15); 12195 op <<= 16; 12196 Value |= op; 12197 break; 12198 } 12199 case ARM::t2BFi: { 12200 // op: b_label 12201 op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, 0, Fixups, STI); 12202 op &= UINT64_C(15); 12203 op <<= 23; 12204 Value |= op; 12205 // op: label 12206 op = getBFTargetOpValue<false, ARM::fixup_bf_target>(MI, 1, Fixups, STI); 12207 Value |= (op & UINT64_C(63488)) << 5; 12208 Value |= (op & UINT64_C(1)) << 11; 12209 Value |= (op & UINT64_C(2046)); 12210 break; 12211 } 12212 case ARM::t2BFLi: { 12213 // op: b_label 12214 op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, 0, Fixups, STI); 12215 op &= UINT64_C(15); 12216 op <<= 23; 12217 Value |= op; 12218 // op: label 12219 op = getBFTargetOpValue<false, ARM::fixup_bfl_target>(MI, 1, Fixups, STI); 12220 Value |= (op & UINT64_C(260096)) << 5; 12221 Value |= (op & UINT64_C(1)) << 11; 12222 Value |= (op & UINT64_C(2046)); 12223 break; 12224 } 12225 case ARM::t2MSRbanked: { 12226 // op: banked 12227 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12228 Value |= (op & UINT64_C(32)) << 15; 12229 Value |= (op & UINT64_C(15)) << 8; 12230 Value |= (op & UINT64_C(16)); 12231 // op: Rn 12232 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12233 op &= UINT64_C(15); 12234 op <<= 16; 12235 Value |= op; 12236 break; 12237 } 12238 case ARM::t2MRSbanked: { 12239 // op: banked 12240 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12241 Value |= (op & UINT64_C(32)) << 15; 12242 Value |= (op & UINT64_C(15)) << 16; 12243 Value |= (op & UINT64_C(16)); 12244 // op: Rd 12245 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12246 op &= UINT64_C(15); 12247 op <<= 8; 12248 Value |= op; 12249 break; 12250 } 12251 case ARM::t2BFic: { 12252 // op: bcond 12253 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12254 op &= UINT64_C(15); 12255 op <<= 18; 12256 Value |= op; 12257 // op: label 12258 op = getBFTargetOpValue<false, ARM::fixup_bfc_target>(MI, 1, Fixups, STI); 12259 Value |= (op & UINT64_C(2048)) << 5; 12260 Value |= (op & UINT64_C(1)) << 11; 12261 Value |= (op & UINT64_C(2046)); 12262 // op: ba_label 12263 op = getBFAfterTargetOpValue(MI, 2, Fixups, STI); 12264 op &= UINT64_C(1); 12265 op <<= 17; 12266 Value |= op; 12267 // op: b_label 12268 op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, 0, Fixups, STI); 12269 op &= UINT64_C(15); 12270 op <<= 23; 12271 Value |= op; 12272 break; 12273 } 12274 case ARM::t2IT: { 12275 // op: cc 12276 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12277 op &= UINT64_C(15); 12278 op <<= 4; 12279 Value |= op; 12280 // op: mask 12281 op = getITMaskOpValue(MI, 1, Fixups, STI); 12282 op &= UINT64_C(15); 12283 Value |= op; 12284 break; 12285 } 12286 case ARM::CDE_VCX1_fpsp: { 12287 // op: coproc 12288 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12289 op &= UINT64_C(7); 12290 op <<= 8; 12291 Value |= op; 12292 // op: imm 12293 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12294 Value |= (op & UINT64_C(1920)) << 9; 12295 Value |= (op & UINT64_C(64)) << 1; 12296 Value |= (op & UINT64_C(63)); 12297 // op: Vd 12298 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12299 Value |= (op & UINT64_C(1)) << 22; 12300 Value |= (op & UINT64_C(30)) << 11; 12301 break; 12302 } 12303 case ARM::CDE_VCX1_fpdp: { 12304 // op: coproc 12305 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12306 op &= UINT64_C(7); 12307 op <<= 8; 12308 Value |= op; 12309 // op: imm 12310 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12311 Value |= (op & UINT64_C(1920)) << 9; 12312 Value |= (op & UINT64_C(64)) << 1; 12313 Value |= (op & UINT64_C(63)); 12314 // op: Vd 12315 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12316 Value |= (op & UINT64_C(16)) << 18; 12317 Value |= (op & UINT64_C(15)) << 12; 12318 break; 12319 } 12320 case ARM::CDE_VCX1_vec: { 12321 // op: coproc 12322 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12323 op &= UINT64_C(7); 12324 op <<= 8; 12325 Value |= op; 12326 // op: imm 12327 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12328 Value |= (op & UINT64_C(2048)) << 13; 12329 Value |= (op & UINT64_C(1920)) << 9; 12330 Value |= (op & UINT64_C(64)) << 1; 12331 Value |= (op & UINT64_C(63)); 12332 // op: Qd 12333 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12334 op &= UINT64_C(7); 12335 op <<= 13; 12336 Value |= op; 12337 break; 12338 } 12339 case ARM::CDE_CX1: 12340 case ARM::CDE_CX1D: { 12341 // op: coproc 12342 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12343 op &= UINT64_C(7); 12344 op <<= 8; 12345 Value |= op; 12346 // op: imm 12347 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12348 Value |= (op & UINT64_C(8064)) << 9; 12349 Value |= (op & UINT64_C(64)) << 1; 12350 Value |= (op & UINT64_C(63)); 12351 // op: Rd 12352 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12353 op &= UINT64_C(15); 12354 op <<= 12; 12355 Value |= op; 12356 break; 12357 } 12358 case ARM::CDE_VCX1A_fpsp: { 12359 // op: coproc 12360 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12361 op &= UINT64_C(7); 12362 op <<= 8; 12363 Value |= op; 12364 // op: imm 12365 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12366 Value |= (op & UINT64_C(1920)) << 9; 12367 Value |= (op & UINT64_C(64)) << 1; 12368 Value |= (op & UINT64_C(63)); 12369 // op: Vd 12370 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12371 Value |= (op & UINT64_C(1)) << 22; 12372 Value |= (op & UINT64_C(30)) << 11; 12373 break; 12374 } 12375 case ARM::CDE_VCX1A_fpdp: { 12376 // op: coproc 12377 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12378 op &= UINT64_C(7); 12379 op <<= 8; 12380 Value |= op; 12381 // op: imm 12382 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12383 Value |= (op & UINT64_C(1920)) << 9; 12384 Value |= (op & UINT64_C(64)) << 1; 12385 Value |= (op & UINT64_C(63)); 12386 // op: Vd 12387 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12388 Value |= (op & UINT64_C(16)) << 18; 12389 Value |= (op & UINT64_C(15)) << 12; 12390 break; 12391 } 12392 case ARM::CDE_VCX1A_vec: { 12393 // op: coproc 12394 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12395 op &= UINT64_C(7); 12396 op <<= 8; 12397 Value |= op; 12398 // op: imm 12399 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12400 Value |= (op & UINT64_C(2048)) << 13; 12401 Value |= (op & UINT64_C(1920)) << 9; 12402 Value |= (op & UINT64_C(64)) << 1; 12403 Value |= (op & UINT64_C(63)); 12404 // op: Qd 12405 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12406 op &= UINT64_C(7); 12407 op <<= 13; 12408 Value |= op; 12409 break; 12410 } 12411 case ARM::CDE_CX2: 12412 case ARM::CDE_CX2D: { 12413 // op: coproc 12414 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12415 op &= UINT64_C(7); 12416 op <<= 8; 12417 Value |= op; 12418 // op: imm 12419 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12420 Value |= (op & UINT64_C(384)) << 13; 12421 Value |= (op & UINT64_C(64)) << 1; 12422 Value |= (op & UINT64_C(63)); 12423 // op: Rd 12424 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12425 op &= UINT64_C(15); 12426 op <<= 12; 12427 Value |= op; 12428 // op: Rn 12429 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12430 op &= UINT64_C(15); 12431 op <<= 16; 12432 Value |= op; 12433 break; 12434 } 12435 case ARM::CDE_VCX2_fpsp: { 12436 // op: coproc 12437 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12438 op &= UINT64_C(7); 12439 op <<= 8; 12440 Value |= op; 12441 // op: imm 12442 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12443 Value |= (op & UINT64_C(60)) << 14; 12444 Value |= (op & UINT64_C(2)) << 6; 12445 Value |= (op & UINT64_C(1)) << 4; 12446 // op: Vd 12447 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12448 Value |= (op & UINT64_C(1)) << 22; 12449 Value |= (op & UINT64_C(30)) << 11; 12450 // op: Vm 12451 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12452 Value |= (op & UINT64_C(1)) << 5; 12453 Value |= (op & UINT64_C(30)) >> 1; 12454 break; 12455 } 12456 case ARM::CDE_VCX2_fpdp: { 12457 // op: coproc 12458 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12459 op &= UINT64_C(7); 12460 op <<= 8; 12461 Value |= op; 12462 // op: imm 12463 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12464 Value |= (op & UINT64_C(60)) << 14; 12465 Value |= (op & UINT64_C(2)) << 6; 12466 Value |= (op & UINT64_C(1)) << 4; 12467 // op: Vd 12468 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12469 Value |= (op & UINT64_C(16)) << 18; 12470 Value |= (op & UINT64_C(15)) << 12; 12471 // op: Vm 12472 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12473 Value |= (op & UINT64_C(16)) << 1; 12474 Value |= (op & UINT64_C(15)); 12475 break; 12476 } 12477 case ARM::CDE_VCX2_vec: { 12478 // op: coproc 12479 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12480 op &= UINT64_C(7); 12481 op <<= 8; 12482 Value |= op; 12483 // op: imm 12484 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12485 Value |= (op & UINT64_C(64)) << 18; 12486 Value |= (op & UINT64_C(60)) << 14; 12487 Value |= (op & UINT64_C(2)) << 6; 12488 Value |= (op & UINT64_C(1)) << 4; 12489 // op: Qd 12490 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12491 op &= UINT64_C(7); 12492 op <<= 13; 12493 Value |= op; 12494 // op: Qm 12495 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12496 op &= UINT64_C(7); 12497 op <<= 1; 12498 Value |= op; 12499 break; 12500 } 12501 case ARM::CDE_CX1A: 12502 case ARM::CDE_CX1DA: { 12503 // op: coproc 12504 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12505 op &= UINT64_C(7); 12506 op <<= 8; 12507 Value |= op; 12508 // op: imm 12509 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12510 Value |= (op & UINT64_C(8064)) << 9; 12511 Value |= (op & UINT64_C(64)) << 1; 12512 Value |= (op & UINT64_C(63)); 12513 // op: Rd 12514 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12515 op &= UINT64_C(15); 12516 op <<= 12; 12517 Value |= op; 12518 break; 12519 } 12520 case ARM::CDE_CX2A: 12521 case ARM::CDE_CX2DA: { 12522 // op: coproc 12523 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12524 op &= UINT64_C(7); 12525 op <<= 8; 12526 Value |= op; 12527 // op: imm 12528 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 12529 Value |= (op & UINT64_C(384)) << 13; 12530 Value |= (op & UINT64_C(64)) << 1; 12531 Value |= (op & UINT64_C(63)); 12532 // op: Rd 12533 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12534 op &= UINT64_C(15); 12535 op <<= 12; 12536 Value |= op; 12537 // op: Rn 12538 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12539 op &= UINT64_C(15); 12540 op <<= 16; 12541 Value |= op; 12542 break; 12543 } 12544 case ARM::CDE_CX3: 12545 case ARM::CDE_CX3D: { 12546 // op: coproc 12547 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12548 op &= UINT64_C(7); 12549 op <<= 8; 12550 Value |= op; 12551 // op: imm 12552 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 12553 Value |= (op & UINT64_C(56)) << 17; 12554 Value |= (op & UINT64_C(4)) << 5; 12555 Value |= (op & UINT64_C(3)) << 4; 12556 // op: Rd 12557 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12558 op &= UINT64_C(15); 12559 Value |= op; 12560 // op: Rn 12561 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12562 op &= UINT64_C(15); 12563 op <<= 16; 12564 Value |= op; 12565 // op: Rm 12566 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12567 op &= UINT64_C(15); 12568 op <<= 12; 12569 Value |= op; 12570 break; 12571 } 12572 case ARM::CDE_VCX3_fpsp: { 12573 // op: coproc 12574 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12575 op &= UINT64_C(7); 12576 op <<= 8; 12577 Value |= op; 12578 // op: imm 12579 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 12580 Value |= (op & UINT64_C(6)) << 19; 12581 Value |= (op & UINT64_C(1)) << 4; 12582 // op: Vd 12583 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12584 Value |= (op & UINT64_C(1)) << 22; 12585 Value |= (op & UINT64_C(30)) << 11; 12586 // op: Vm 12587 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12588 Value |= (op & UINT64_C(1)) << 5; 12589 Value |= (op & UINT64_C(30)) >> 1; 12590 // op: Vn 12591 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12592 Value |= (op & UINT64_C(30)) << 15; 12593 Value |= (op & UINT64_C(1)) << 7; 12594 break; 12595 } 12596 case ARM::CDE_VCX3_fpdp: { 12597 // op: coproc 12598 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12599 op &= UINT64_C(7); 12600 op <<= 8; 12601 Value |= op; 12602 // op: imm 12603 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 12604 Value |= (op & UINT64_C(6)) << 19; 12605 Value |= (op & UINT64_C(1)) << 4; 12606 // op: Vd 12607 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12608 Value |= (op & UINT64_C(16)) << 18; 12609 Value |= (op & UINT64_C(15)) << 12; 12610 // op: Vm 12611 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12612 Value |= (op & UINT64_C(16)) << 1; 12613 Value |= (op & UINT64_C(15)); 12614 // op: Vn 12615 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12616 Value |= (op & UINT64_C(15)) << 16; 12617 Value |= (op & UINT64_C(16)) << 3; 12618 break; 12619 } 12620 case ARM::CDE_VCX2A_fpsp: { 12621 // op: coproc 12622 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12623 op &= UINT64_C(7); 12624 op <<= 8; 12625 Value |= op; 12626 // op: imm 12627 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 12628 Value |= (op & UINT64_C(60)) << 14; 12629 Value |= (op & UINT64_C(2)) << 6; 12630 Value |= (op & UINT64_C(1)) << 4; 12631 // op: Vd 12632 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12633 Value |= (op & UINT64_C(1)) << 22; 12634 Value |= (op & UINT64_C(30)) << 11; 12635 // op: Vm 12636 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12637 Value |= (op & UINT64_C(1)) << 5; 12638 Value |= (op & UINT64_C(30)) >> 1; 12639 break; 12640 } 12641 case ARM::CDE_VCX2A_fpdp: { 12642 // op: coproc 12643 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12644 op &= UINT64_C(7); 12645 op <<= 8; 12646 Value |= op; 12647 // op: imm 12648 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 12649 Value |= (op & UINT64_C(60)) << 14; 12650 Value |= (op & UINT64_C(2)) << 6; 12651 Value |= (op & UINT64_C(1)) << 4; 12652 // op: Vd 12653 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12654 Value |= (op & UINT64_C(16)) << 18; 12655 Value |= (op & UINT64_C(15)) << 12; 12656 // op: Vm 12657 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12658 Value |= (op & UINT64_C(16)) << 1; 12659 Value |= (op & UINT64_C(15)); 12660 break; 12661 } 12662 case ARM::CDE_VCX2A_vec: { 12663 // op: coproc 12664 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12665 op &= UINT64_C(7); 12666 op <<= 8; 12667 Value |= op; 12668 // op: imm 12669 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 12670 Value |= (op & UINT64_C(64)) << 18; 12671 Value |= (op & UINT64_C(60)) << 14; 12672 Value |= (op & UINT64_C(2)) << 6; 12673 Value |= (op & UINT64_C(1)) << 4; 12674 // op: Qd 12675 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12676 op &= UINT64_C(7); 12677 op <<= 13; 12678 Value |= op; 12679 // op: Qm 12680 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12681 op &= UINT64_C(7); 12682 op <<= 1; 12683 Value |= op; 12684 break; 12685 } 12686 case ARM::CDE_VCX3_vec: { 12687 // op: coproc 12688 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12689 op &= UINT64_C(7); 12690 op <<= 8; 12691 Value |= op; 12692 // op: imm 12693 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 12694 Value |= (op & UINT64_C(8)) << 21; 12695 Value |= (op & UINT64_C(6)) << 19; 12696 Value |= (op & UINT64_C(1)) << 4; 12697 // op: Qd 12698 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12699 op &= UINT64_C(7); 12700 op <<= 13; 12701 Value |= op; 12702 // op: Qm 12703 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12704 op &= UINT64_C(7); 12705 op <<= 1; 12706 Value |= op; 12707 // op: Qn 12708 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12709 op &= UINT64_C(7); 12710 op <<= 17; 12711 Value |= op; 12712 break; 12713 } 12714 case ARM::CDE_CX3A: 12715 case ARM::CDE_CX3DA: { 12716 // op: coproc 12717 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12718 op &= UINT64_C(7); 12719 op <<= 8; 12720 Value |= op; 12721 // op: imm 12722 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 12723 Value |= (op & UINT64_C(56)) << 17; 12724 Value |= (op & UINT64_C(4)) << 5; 12725 Value |= (op & UINT64_C(3)) << 4; 12726 // op: Rd 12727 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12728 op &= UINT64_C(15); 12729 Value |= op; 12730 // op: Rn 12731 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12732 op &= UINT64_C(15); 12733 op <<= 16; 12734 Value |= op; 12735 // op: Rm 12736 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 12737 op &= UINT64_C(15); 12738 op <<= 12; 12739 Value |= op; 12740 break; 12741 } 12742 case ARM::CDE_VCX3A_fpsp: { 12743 // op: coproc 12744 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12745 op &= UINT64_C(7); 12746 op <<= 8; 12747 Value |= op; 12748 // op: imm 12749 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 12750 Value |= (op & UINT64_C(6)) << 19; 12751 Value |= (op & UINT64_C(1)) << 4; 12752 // op: Vd 12753 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12754 Value |= (op & UINT64_C(1)) << 22; 12755 Value |= (op & UINT64_C(30)) << 11; 12756 // op: Vm 12757 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 12758 Value |= (op & UINT64_C(1)) << 5; 12759 Value |= (op & UINT64_C(30)) >> 1; 12760 // op: Vn 12761 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12762 Value |= (op & UINT64_C(30)) << 15; 12763 Value |= (op & UINT64_C(1)) << 7; 12764 break; 12765 } 12766 case ARM::CDE_VCX3A_fpdp: { 12767 // op: coproc 12768 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12769 op &= UINT64_C(7); 12770 op <<= 8; 12771 Value |= op; 12772 // op: imm 12773 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 12774 Value |= (op & UINT64_C(6)) << 19; 12775 Value |= (op & UINT64_C(1)) << 4; 12776 // op: Vd 12777 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12778 Value |= (op & UINT64_C(16)) << 18; 12779 Value |= (op & UINT64_C(15)) << 12; 12780 // op: Vm 12781 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 12782 Value |= (op & UINT64_C(16)) << 1; 12783 Value |= (op & UINT64_C(15)); 12784 // op: Vn 12785 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12786 Value |= (op & UINT64_C(15)) << 16; 12787 Value |= (op & UINT64_C(16)) << 3; 12788 break; 12789 } 12790 case ARM::CDE_VCX3A_vec: { 12791 // op: coproc 12792 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12793 op &= UINT64_C(7); 12794 op <<= 8; 12795 Value |= op; 12796 // op: imm 12797 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 12798 Value |= (op & UINT64_C(8)) << 21; 12799 Value |= (op & UINT64_C(6)) << 19; 12800 Value |= (op & UINT64_C(1)) << 4; 12801 // op: Qd 12802 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12803 op &= UINT64_C(7); 12804 op <<= 13; 12805 Value |= op; 12806 // op: Qm 12807 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 12808 op &= UINT64_C(7); 12809 op <<= 1; 12810 Value |= op; 12811 // op: Qn 12812 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12813 op &= UINT64_C(7); 12814 op <<= 17; 12815 Value |= op; 12816 break; 12817 } 12818 case ARM::BX: { 12819 // op: dst 12820 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12821 op &= UINT64_C(15); 12822 Value |= op; 12823 break; 12824 } 12825 case ARM::tPICADD: { 12826 // op: dst 12827 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12828 op &= UINT64_C(7); 12829 Value |= op; 12830 break; 12831 } 12832 case ARM::tADDrSPi: { 12833 // op: dst 12834 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12835 op &= UINT64_C(7); 12836 op <<= 8; 12837 Value |= op; 12838 // op: imm 12839 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12840 op &= UINT64_C(255); 12841 Value |= op; 12842 break; 12843 } 12844 case ARM::tSETEND: { 12845 // op: end 12846 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12847 op &= UINT64_C(1); 12848 op <<= 3; 12849 Value |= op; 12850 break; 12851 } 12852 case ARM::SETEND: { 12853 // op: end 12854 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12855 op &= UINT64_C(1); 12856 op <<= 9; 12857 Value |= op; 12858 break; 12859 } 12860 case ARM::MVE_VPTv16s8r: 12861 case ARM::MVE_VPTv4s32r: 12862 case ARM::MVE_VPTv8s16r: { 12863 // op: fc 12864 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 12865 Value |= (op & UINT64_C(1)) << 7; 12866 Value |= (op & UINT64_C(2)) << 4; 12867 // op: Mk 12868 op = getVPTMaskOpValue(MI, 0, Fixups, STI); 12869 Value |= (op & UINT64_C(8)) << 19; 12870 Value |= (op & UINT64_C(7)) << 13; 12871 // op: Qn 12872 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12873 op &= UINT64_C(7); 12874 op <<= 17; 12875 Value |= op; 12876 // op: Rm 12877 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12878 op &= UINT64_C(15); 12879 Value |= op; 12880 break; 12881 } 12882 case ARM::MVE_VCMPs16r: 12883 case ARM::MVE_VCMPs32r: 12884 case ARM::MVE_VCMPs8r: { 12885 // op: fc 12886 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 12887 Value |= (op & UINT64_C(1)) << 7; 12888 Value |= (op & UINT64_C(2)) << 4; 12889 // op: Qn 12890 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12891 op &= UINT64_C(7); 12892 op <<= 17; 12893 Value |= op; 12894 // op: Rm 12895 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12896 op &= UINT64_C(15); 12897 Value |= op; 12898 break; 12899 } 12900 case ARM::MVE_VPTv16s8: 12901 case ARM::MVE_VPTv4s32: 12902 case ARM::MVE_VPTv8s16: { 12903 // op: fc 12904 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 12905 Value |= (op & UINT64_C(1)) << 7; 12906 Value |= (op & UINT64_C(2)) >> 1; 12907 // op: Mk 12908 op = getVPTMaskOpValue(MI, 0, Fixups, STI); 12909 Value |= (op & UINT64_C(8)) << 19; 12910 Value |= (op & UINT64_C(7)) << 13; 12911 // op: Qn 12912 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12913 op &= UINT64_C(7); 12914 op <<= 17; 12915 Value |= op; 12916 // op: Qm 12917 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12918 Value |= (op & UINT64_C(8)) << 2; 12919 Value |= (op & UINT64_C(7)) << 1; 12920 break; 12921 } 12922 case ARM::MVE_VCMPs16: 12923 case ARM::MVE_VCMPs32: 12924 case ARM::MVE_VCMPs8: { 12925 // op: fc 12926 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 12927 Value |= (op & UINT64_C(1)) << 7; 12928 Value |= (op & UINT64_C(2)) >> 1; 12929 // op: Qn 12930 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12931 op &= UINT64_C(7); 12932 op <<= 17; 12933 Value |= op; 12934 // op: Qm 12935 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12936 Value |= (op & UINT64_C(8)) << 2; 12937 Value |= (op & UINT64_C(7)) << 1; 12938 break; 12939 } 12940 case ARM::MVE_VPTv4f32r: 12941 case ARM::MVE_VPTv8f16r: { 12942 // op: fc 12943 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 12944 Value |= (op & UINT64_C(4)) << 10; 12945 Value |= (op & UINT64_C(1)) << 7; 12946 Value |= (op & UINT64_C(2)) << 4; 12947 // op: Mk 12948 op = getVPTMaskOpValue(MI, 0, Fixups, STI); 12949 Value |= (op & UINT64_C(8)) << 19; 12950 Value |= (op & UINT64_C(7)) << 13; 12951 // op: Qn 12952 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12953 op &= UINT64_C(7); 12954 op <<= 17; 12955 Value |= op; 12956 // op: Rm 12957 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12958 op &= UINT64_C(15); 12959 Value |= op; 12960 break; 12961 } 12962 case ARM::MVE_VCMPf16r: 12963 case ARM::MVE_VCMPf32r: { 12964 // op: fc 12965 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 12966 Value |= (op & UINT64_C(4)) << 10; 12967 Value |= (op & UINT64_C(1)) << 7; 12968 Value |= (op & UINT64_C(2)) << 4; 12969 // op: Qn 12970 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12971 op &= UINT64_C(7); 12972 op <<= 17; 12973 Value |= op; 12974 // op: Rm 12975 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12976 op &= UINT64_C(15); 12977 Value |= op; 12978 break; 12979 } 12980 case ARM::MVE_VPTv4f32: 12981 case ARM::MVE_VPTv8f16: { 12982 // op: fc 12983 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 12984 Value |= (op & UINT64_C(4)) << 10; 12985 Value |= (op & UINT64_C(1)) << 7; 12986 Value |= (op & UINT64_C(2)) >> 1; 12987 // op: Mk 12988 op = getVPTMaskOpValue(MI, 0, Fixups, STI); 12989 Value |= (op & UINT64_C(8)) << 19; 12990 Value |= (op & UINT64_C(7)) << 13; 12991 // op: Qn 12992 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12993 op &= UINT64_C(7); 12994 op <<= 17; 12995 Value |= op; 12996 // op: Qm 12997 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12998 Value |= (op & UINT64_C(8)) << 2; 12999 Value |= (op & UINT64_C(7)) << 1; 13000 break; 13001 } 13002 case ARM::MVE_VCMPf16: 13003 case ARM::MVE_VCMPf32: { 13004 // op: fc 13005 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 13006 Value |= (op & UINT64_C(4)) << 10; 13007 Value |= (op & UINT64_C(1)) << 7; 13008 Value |= (op & UINT64_C(2)) >> 1; 13009 // op: Qn 13010 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13011 op &= UINT64_C(7); 13012 op <<= 17; 13013 Value |= op; 13014 // op: Qm 13015 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13016 Value |= (op & UINT64_C(8)) << 2; 13017 Value |= (op & UINT64_C(7)) << 1; 13018 break; 13019 } 13020 case ARM::MVE_VPTv16i8: 13021 case ARM::MVE_VPTv16u8: 13022 case ARM::MVE_VPTv4i32: 13023 case ARM::MVE_VPTv4u32: 13024 case ARM::MVE_VPTv8i16: 13025 case ARM::MVE_VPTv8u16: { 13026 // op: fc 13027 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 13028 op &= UINT64_C(1); 13029 op <<= 7; 13030 Value |= op; 13031 // op: Mk 13032 op = getVPTMaskOpValue(MI, 0, Fixups, STI); 13033 Value |= (op & UINT64_C(8)) << 19; 13034 Value |= (op & UINT64_C(7)) << 13; 13035 // op: Qn 13036 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13037 op &= UINT64_C(7); 13038 op <<= 17; 13039 Value |= op; 13040 // op: Qm 13041 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13042 Value |= (op & UINT64_C(8)) << 2; 13043 Value |= (op & UINT64_C(7)) << 1; 13044 break; 13045 } 13046 case ARM::MVE_VPTv16i8r: 13047 case ARM::MVE_VPTv16u8r: 13048 case ARM::MVE_VPTv4i32r: 13049 case ARM::MVE_VPTv4u32r: 13050 case ARM::MVE_VPTv8i16r: 13051 case ARM::MVE_VPTv8u16r: { 13052 // op: fc 13053 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 13054 op &= UINT64_C(1); 13055 op <<= 7; 13056 Value |= op; 13057 // op: Mk 13058 op = getVPTMaskOpValue(MI, 0, Fixups, STI); 13059 Value |= (op & UINT64_C(8)) << 19; 13060 Value |= (op & UINT64_C(7)) << 13; 13061 // op: Qn 13062 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13063 op &= UINT64_C(7); 13064 op <<= 17; 13065 Value |= op; 13066 // op: Rm 13067 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13068 op &= UINT64_C(15); 13069 Value |= op; 13070 break; 13071 } 13072 case ARM::MVE_VCMPi16: 13073 case ARM::MVE_VCMPi32: 13074 case ARM::MVE_VCMPi8: 13075 case ARM::MVE_VCMPu16: 13076 case ARM::MVE_VCMPu32: 13077 case ARM::MVE_VCMPu8: { 13078 // op: fc 13079 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 13080 op &= UINT64_C(1); 13081 op <<= 7; 13082 Value |= op; 13083 // op: Qn 13084 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13085 op &= UINT64_C(7); 13086 op <<= 17; 13087 Value |= op; 13088 // op: Qm 13089 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13090 Value |= (op & UINT64_C(8)) << 2; 13091 Value |= (op & UINT64_C(7)) << 1; 13092 break; 13093 } 13094 case ARM::MVE_VCMPi16r: 13095 case ARM::MVE_VCMPi32r: 13096 case ARM::MVE_VCMPi8r: 13097 case ARM::MVE_VCMPu16r: 13098 case ARM::MVE_VCMPu32r: 13099 case ARM::MVE_VCMPu8r: { 13100 // op: fc 13101 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 13102 op &= UINT64_C(1); 13103 op <<= 7; 13104 Value |= op; 13105 // op: Qn 13106 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13107 op &= UINT64_C(7); 13108 op <<= 17; 13109 Value |= op; 13110 // op: Rm 13111 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13112 op &= UINT64_C(15); 13113 Value |= op; 13114 break; 13115 } 13116 case ARM::BL: { 13117 // op: func 13118 op = getARMBLTargetOpValue(MI, 0, Fixups, STI); 13119 op &= UINT64_C(16777215); 13120 Value |= op; 13121 break; 13122 } 13123 case ARM::BLX: { 13124 // op: func 13125 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13126 op &= UINT64_C(15); 13127 Value |= op; 13128 break; 13129 } 13130 case ARM::t2BXJ: { 13131 // op: func 13132 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13133 op &= UINT64_C(15); 13134 op <<= 16; 13135 Value |= op; 13136 break; 13137 } 13138 case ARM::tBLXNSr: 13139 case ARM::tBLXr: { 13140 // op: func 13141 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13142 op &= UINT64_C(15); 13143 op <<= 3; 13144 Value |= op; 13145 break; 13146 } 13147 case ARM::tBL: { 13148 // op: func 13149 op = getThumbBLTargetOpValue(MI, 2, Fixups, STI); 13150 Value |= (op & UINT64_C(8388608)) << 3; 13151 Value |= (op & UINT64_C(2095104)) << 5; 13152 Value |= (op & UINT64_C(4194304)) >> 9; 13153 Value |= (op & UINT64_C(2097152)) >> 10; 13154 Value |= (op & UINT64_C(2047)); 13155 break; 13156 } 13157 case ARM::tBLXi: { 13158 // op: func 13159 op = getThumbBLXTargetOpValue(MI, 2, Fixups, STI); 13160 Value |= (op & UINT64_C(8388608)) << 3; 13161 Value |= (op & UINT64_C(2095104)) << 5; 13162 Value |= (op & UINT64_C(4194304)) >> 9; 13163 Value |= (op & UINT64_C(2097152)) >> 10; 13164 Value |= (op & UINT64_C(2046)); 13165 break; 13166 } 13167 case ARM::HVC: { 13168 // op: imm 13169 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13170 Value |= (op & UINT64_C(65520)) << 4; 13171 Value |= (op & UINT64_C(15)); 13172 break; 13173 } 13174 case ARM::t2SETPAN: { 13175 // op: imm 13176 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13177 op &= UINT64_C(1); 13178 op <<= 3; 13179 Value |= op; 13180 break; 13181 } 13182 case ARM::SETPAN: { 13183 // op: imm 13184 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13185 op &= UINT64_C(1); 13186 op <<= 9; 13187 Value |= op; 13188 break; 13189 } 13190 case ARM::tHINT: { 13191 // op: imm 13192 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13193 op &= UINT64_C(15); 13194 op <<= 4; 13195 Value |= op; 13196 break; 13197 } 13198 case ARM::t2HINT: 13199 case ARM::t2SUBS_PC_LR: 13200 case ARM::tSVC: { 13201 // op: imm 13202 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13203 op &= UINT64_C(255); 13204 Value |= op; 13205 break; 13206 } 13207 case ARM::MVE_VMOVimmf32: 13208 case ARM::MVE_VMOVimmi64: 13209 case ARM::MVE_VMOVimmi8: { 13210 // op: imm 13211 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13212 Value |= (op & UINT64_C(128)) << 21; 13213 Value |= (op & UINT64_C(112)) << 12; 13214 Value |= (op & UINT64_C(15)); 13215 // op: Qd 13216 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13217 Value |= (op & UINT64_C(8)) << 19; 13218 Value |= (op & UINT64_C(7)) << 13; 13219 break; 13220 } 13221 case ARM::MVE_VMOVimmi32: 13222 case ARM::MVE_VMVNimmi32: { 13223 // op: imm 13224 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13225 Value |= (op & UINT64_C(128)) << 21; 13226 Value |= (op & UINT64_C(112)) << 12; 13227 Value |= (op & UINT64_C(3840)); 13228 Value |= (op & UINT64_C(15)); 13229 // op: Qd 13230 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13231 Value |= (op & UINT64_C(8)) << 19; 13232 Value |= (op & UINT64_C(7)) << 13; 13233 break; 13234 } 13235 case ARM::MVE_VMOVimmi16: 13236 case ARM::MVE_VMVNimmi16: { 13237 // op: imm 13238 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13239 Value |= (op & UINT64_C(128)) << 21; 13240 Value |= (op & UINT64_C(112)) << 12; 13241 Value |= (op & UINT64_C(512)); 13242 Value |= (op & UINT64_C(15)); 13243 // op: Qd 13244 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13245 Value |= (op & UINT64_C(8)) << 19; 13246 Value |= (op & UINT64_C(7)) << 13; 13247 break; 13248 } 13249 case ARM::MVE_VBICimmi32: 13250 case ARM::MVE_VORRimmi32: { 13251 // op: imm 13252 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13253 Value |= (op & UINT64_C(128)) << 21; 13254 Value |= (op & UINT64_C(112)) << 12; 13255 Value |= (op & UINT64_C(1536)); 13256 Value |= (op & UINT64_C(15)); 13257 // op: Qd 13258 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13259 Value |= (op & UINT64_C(8)) << 19; 13260 Value |= (op & UINT64_C(7)) << 13; 13261 break; 13262 } 13263 case ARM::MVE_VBICimmi16: 13264 case ARM::MVE_VORRimmi16: { 13265 // op: imm 13266 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13267 Value |= (op & UINT64_C(128)) << 21; 13268 Value |= (op & UINT64_C(112)) << 12; 13269 Value |= (op & UINT64_C(512)); 13270 Value |= (op & UINT64_C(15)); 13271 // op: Qd 13272 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13273 Value |= (op & UINT64_C(8)) << 19; 13274 Value |= (op & UINT64_C(7)) << 13; 13275 break; 13276 } 13277 case ARM::t2ADDspImm12: 13278 case ARM::t2SUBspImm12: { 13279 // op: imm 13280 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13281 Value |= (op & UINT64_C(2048)) << 15; 13282 Value |= (op & UINT64_C(1792)) << 4; 13283 Value |= (op & UINT64_C(255)); 13284 break; 13285 } 13286 case ARM::tADDspi: 13287 case ARM::tSUBspi: { 13288 // op: imm 13289 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13290 op &= UINT64_C(127); 13291 Value |= op; 13292 break; 13293 } 13294 case ARM::MVE_VSHLC: { 13295 // op: imm 13296 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 13297 op &= UINT64_C(31); 13298 op <<= 16; 13299 Value |= op; 13300 // op: Qd 13301 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13302 Value |= (op & UINT64_C(8)) << 19; 13303 Value |= (op & UINT64_C(7)) << 13; 13304 // op: RdmDest 13305 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13306 op &= UINT64_C(15); 13307 Value |= op; 13308 break; 13309 } 13310 case ARM::t2HVC: 13311 case ARM::t2UDF: { 13312 // op: imm16 13313 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13314 Value |= (op & UINT64_C(61440)) << 4; 13315 Value |= (op & UINT64_C(4095)); 13316 break; 13317 } 13318 case ARM::UDF: { 13319 // op: imm16 13320 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13321 Value |= (op & UINT64_C(65520)) << 4; 13322 Value |= (op & UINT64_C(15)); 13323 break; 13324 } 13325 case ARM::tUDF: { 13326 // op: imm8 13327 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13328 op &= UINT64_C(255); 13329 Value |= op; 13330 break; 13331 } 13332 case ARM::tCPS: { 13333 // op: imod 13334 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13335 op &= UINT64_C(1); 13336 op <<= 4; 13337 Value |= op; 13338 // op: iflags 13339 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13340 op &= UINT64_C(7); 13341 Value |= op; 13342 break; 13343 } 13344 case ARM::CPS2p: { 13345 // op: imod 13346 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13347 op &= UINT64_C(3); 13348 op <<= 18; 13349 Value |= op; 13350 // op: iflags 13351 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13352 op &= UINT64_C(7); 13353 op <<= 6; 13354 Value |= op; 13355 break; 13356 } 13357 case ARM::CPS3p: { 13358 // op: imod 13359 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13360 op &= UINT64_C(3); 13361 op <<= 18; 13362 Value |= op; 13363 // op: iflags 13364 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13365 op &= UINT64_C(7); 13366 op <<= 6; 13367 Value |= op; 13368 // op: mode 13369 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13370 op &= UINT64_C(31); 13371 Value |= op; 13372 break; 13373 } 13374 case ARM::t2CPS2p: { 13375 // op: imod 13376 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13377 op &= UINT64_C(3); 13378 op <<= 9; 13379 Value |= op; 13380 // op: iflags 13381 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13382 op &= UINT64_C(7); 13383 op <<= 5; 13384 Value |= op; 13385 break; 13386 } 13387 case ARM::t2CPS3p: { 13388 // op: imod 13389 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13390 op &= UINT64_C(3); 13391 op <<= 9; 13392 Value |= op; 13393 // op: iflags 13394 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13395 op &= UINT64_C(7); 13396 op <<= 5; 13397 Value |= op; 13398 // op: mode 13399 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13400 op &= UINT64_C(31); 13401 Value |= op; 13402 break; 13403 } 13404 case ARM::t2LE: { 13405 // op: label 13406 op = getBFTargetOpValue<true, ARM::fixup_le>(MI, 0, Fixups, STI); 13407 Value |= (op & UINT64_C(1)) << 11; 13408 Value |= (op & UINT64_C(2046)); 13409 break; 13410 } 13411 case ARM::MVE_LETP: 13412 case ARM::t2LEUpdate: { 13413 // op: label 13414 op = getBFTargetOpValue<true, ARM::fixup_le>(MI, 2, Fixups, STI); 13415 Value |= (op & UINT64_C(1)) << 11; 13416 Value |= (op & UINT64_C(2046)); 13417 break; 13418 } 13419 case ARM::t2MSR_AR: { 13420 // op: mask 13421 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13422 Value |= (op & UINT64_C(16)) << 16; 13423 Value |= (op & UINT64_C(15)) << 8; 13424 // op: Rn 13425 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13426 op &= UINT64_C(15); 13427 op <<= 16; 13428 Value |= op; 13429 break; 13430 } 13431 case ARM::CPS1p: 13432 case ARM::SRSDA: 13433 case ARM::SRSDA_UPD: 13434 case ARM::SRSDB: 13435 case ARM::SRSDB_UPD: 13436 case ARM::SRSIA: 13437 case ARM::SRSIA_UPD: 13438 case ARM::SRSIB: 13439 case ARM::SRSIB_UPD: 13440 case ARM::t2CPS1p: 13441 case ARM::t2SRSDB: 13442 case ARM::t2SRSDB_UPD: 13443 case ARM::t2SRSIA: 13444 case ARM::t2SRSIA_UPD: { 13445 // op: mode 13446 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13447 op &= UINT64_C(31); 13448 Value |= op; 13449 break; 13450 } 13451 case ARM::LDC2L_POST: 13452 case ARM::LDC2_POST: 13453 case ARM::STC2L_POST: 13454 case ARM::STC2_POST: 13455 case ARM::t2LDC2L_POST: 13456 case ARM::t2LDC2_POST: 13457 case ARM::t2LDCL_POST: 13458 case ARM::t2LDC_POST: 13459 case ARM::t2STC2L_POST: 13460 case ARM::t2STC2_POST: 13461 case ARM::t2STCL_POST: 13462 case ARM::t2STC_POST: { 13463 // op: offset 13464 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 13465 Value |= (op & UINT64_C(256)) << 15; 13466 Value |= (op & UINT64_C(255)); 13467 // op: addr 13468 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13469 op &= UINT64_C(15); 13470 op <<= 16; 13471 Value |= op; 13472 // op: cop 13473 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13474 op &= UINT64_C(15); 13475 op <<= 8; 13476 Value |= op; 13477 // op: CRd 13478 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13479 op &= UINT64_C(15); 13480 op <<= 12; 13481 Value |= op; 13482 break; 13483 } 13484 case ARM::CDP2: 13485 case ARM::t2CDP: 13486 case ARM::t2CDP2: { 13487 // op: opc1 13488 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13489 op &= UINT64_C(15); 13490 op <<= 20; 13491 Value |= op; 13492 // op: CRn 13493 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 13494 op &= UINT64_C(15); 13495 op <<= 16; 13496 Value |= op; 13497 // op: CRd 13498 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13499 op &= UINT64_C(15); 13500 op <<= 12; 13501 Value |= op; 13502 // op: cop 13503 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13504 op &= UINT64_C(15); 13505 op <<= 8; 13506 Value |= op; 13507 // op: opc2 13508 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 13509 op &= UINT64_C(7); 13510 op <<= 5; 13511 Value |= op; 13512 // op: CRm 13513 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 13514 op &= UINT64_C(15); 13515 Value |= op; 13516 break; 13517 } 13518 case ARM::DMB: 13519 case ARM::DSB: 13520 case ARM::ISB: 13521 case ARM::t2DBG: 13522 case ARM::t2DMB: 13523 case ARM::t2DSB: 13524 case ARM::t2ISB: { 13525 // op: opt 13526 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13527 op &= UINT64_C(15); 13528 Value |= op; 13529 break; 13530 } 13531 case ARM::t2SMC: { 13532 // op: opt 13533 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13534 op &= UINT64_C(15); 13535 op <<= 16; 13536 Value |= op; 13537 break; 13538 } 13539 case ARM::LDC2L_OPTION: 13540 case ARM::LDC2_OPTION: 13541 case ARM::STC2L_OPTION: 13542 case ARM::STC2_OPTION: 13543 case ARM::t2LDC2L_OPTION: 13544 case ARM::t2LDC2_OPTION: 13545 case ARM::t2LDCL_OPTION: 13546 case ARM::t2LDC_OPTION: 13547 case ARM::t2STC2L_OPTION: 13548 case ARM::t2STC2_OPTION: 13549 case ARM::t2STCL_OPTION: 13550 case ARM::t2STC_OPTION: { 13551 // op: option 13552 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 13553 op &= UINT64_C(255); 13554 Value |= op; 13555 // op: addr 13556 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13557 op &= UINT64_C(15); 13558 op <<= 16; 13559 Value |= op; 13560 // op: cop 13561 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13562 op &= UINT64_C(15); 13563 op <<= 8; 13564 Value |= op; 13565 // op: CRd 13566 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13567 op &= UINT64_C(15); 13568 op <<= 12; 13569 Value |= op; 13570 break; 13571 } 13572 case ARM::BX_RET: 13573 case ARM::ERET: 13574 case ARM::MOVPCLR: { 13575 // op: p 13576 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13577 op &= UINT64_C(15); 13578 op <<= 28; 13579 Value |= op; 13580 break; 13581 } 13582 case ARM::FMSTAT: { 13583 // op: p 13584 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13585 op &= UINT64_C(15); 13586 op <<= 28; 13587 Value |= op; 13588 Value = VFPThumb2PostEncoder(MI, Value, STI); 13589 break; 13590 } 13591 case ARM::t2Bcc: { 13592 // op: p 13593 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13594 op &= UINT64_C(15); 13595 op <<= 22; 13596 Value |= op; 13597 // op: target 13598 op = getBranchTargetOpValue(MI, 0, Fixups, STI); 13599 Value |= (op & UINT64_C(1048576)) << 6; 13600 Value |= (op & UINT64_C(258048)) << 4; 13601 Value |= (op & UINT64_C(262144)) >> 5; 13602 Value |= (op & UINT64_C(524288)) >> 8; 13603 Value |= (op & UINT64_C(4094)) >> 1; 13604 break; 13605 } 13606 case ARM::VCMPEZD: 13607 case ARM::VCMPZD: { 13608 // op: p 13609 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13610 op &= UINT64_C(15); 13611 op <<= 28; 13612 Value |= op; 13613 // op: Dd 13614 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13615 Value |= (op & UINT64_C(16)) << 18; 13616 Value |= (op & UINT64_C(15)) << 12; 13617 Value = VFPThumb2PostEncoder(MI, Value, STI); 13618 break; 13619 } 13620 case ARM::MRS: 13621 case ARM::MRSsys: { 13622 // op: p 13623 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13624 op &= UINT64_C(15); 13625 op <<= 28; 13626 Value |= op; 13627 // op: Rd 13628 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13629 op &= UINT64_C(15); 13630 op <<= 12; 13631 Value |= op; 13632 break; 13633 } 13634 case ARM::VLDMSIA: 13635 case ARM::VSTMSIA: { 13636 // op: p 13637 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13638 op &= UINT64_C(15); 13639 op <<= 28; 13640 Value |= op; 13641 // op: Rn 13642 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13643 op &= UINT64_C(15); 13644 op <<= 16; 13645 Value |= op; 13646 // op: regs 13647 op = getRegisterListOpValue(MI, 3, Fixups, STI); 13648 Value |= (op & UINT64_C(256)) << 14; 13649 Value |= (op & UINT64_C(7680)) << 3; 13650 Value |= (op & UINT64_C(255)); 13651 Value = VFPThumb2PostEncoder(MI, Value, STI); 13652 break; 13653 } 13654 case ARM::FLDMXIA: 13655 case ARM::FSTMXIA: { 13656 // op: p 13657 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13658 op &= UINT64_C(15); 13659 op <<= 28; 13660 Value |= op; 13661 // op: Rn 13662 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13663 op &= UINT64_C(15); 13664 op <<= 16; 13665 Value |= op; 13666 // op: regs 13667 op = getRegisterListOpValue(MI, 3, Fixups, STI); 13668 Value |= (op & UINT64_C(3840)) << 4; 13669 Value |= (op & UINT64_C(254)); 13670 Value = VFPThumb2PostEncoder(MI, Value, STI); 13671 break; 13672 } 13673 case ARM::VLDMDIA: 13674 case ARM::VSTMDIA: { 13675 // op: p 13676 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13677 op &= UINT64_C(15); 13678 op <<= 28; 13679 Value |= op; 13680 // op: Rn 13681 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13682 op &= UINT64_C(15); 13683 op <<= 16; 13684 Value |= op; 13685 // op: regs 13686 op = getRegisterListOpValue(MI, 3, Fixups, STI); 13687 Value |= (op & UINT64_C(4096)) << 10; 13688 Value |= (op & UINT64_C(3840)) << 4; 13689 Value |= (op & UINT64_C(254)); 13690 Value = VFPThumb2PostEncoder(MI, Value, STI); 13691 break; 13692 } 13693 case ARM::VLLDM: 13694 case ARM::VLSTM: { 13695 // op: p 13696 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13697 op &= UINT64_C(15); 13698 op <<= 28; 13699 Value |= op; 13700 // op: Rn 13701 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13702 op &= UINT64_C(15); 13703 op <<= 16; 13704 Value |= op; 13705 Value = VFPThumb2PostEncoder(MI, Value, STI); 13706 break; 13707 } 13708 case ARM::VMRS: 13709 case ARM::VMRS_FPCXTNS: 13710 case ARM::VMRS_FPCXTS: 13711 case ARM::VMRS_FPEXC: 13712 case ARM::VMRS_FPINST: 13713 case ARM::VMRS_FPINST2: 13714 case ARM::VMRS_FPSID: 13715 case ARM::VMRS_MVFR0: 13716 case ARM::VMRS_MVFR1: 13717 case ARM::VMRS_MVFR2: 13718 case ARM::VMRS_VPR: 13719 case ARM::VMSR: 13720 case ARM::VMSR_FPCXTNS: 13721 case ARM::VMSR_FPCXTS: 13722 case ARM::VMSR_FPEXC: 13723 case ARM::VMSR_FPINST: 13724 case ARM::VMSR_FPINST2: 13725 case ARM::VMSR_FPSID: 13726 case ARM::VMSR_VPR: { 13727 // op: p 13728 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13729 op &= UINT64_C(15); 13730 op <<= 28; 13731 Value |= op; 13732 // op: Rt 13733 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13734 op &= UINT64_C(15); 13735 op <<= 12; 13736 Value |= op; 13737 Value = VFPThumb2PostEncoder(MI, Value, STI); 13738 break; 13739 } 13740 case ARM::VCMPEZH: 13741 case ARM::VCMPEZS: 13742 case ARM::VCMPZH: 13743 case ARM::VCMPZS: { 13744 // op: p 13745 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13746 op &= UINT64_C(15); 13747 op <<= 28; 13748 Value |= op; 13749 // op: Sd 13750 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13751 Value |= (op & UINT64_C(1)) << 22; 13752 Value |= (op & UINT64_C(30)) << 11; 13753 Value = VFPThumb2PostEncoder(MI, Value, STI); 13754 break; 13755 } 13756 case ARM::BX_pred: { 13757 // op: p 13758 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13759 op &= UINT64_C(15); 13760 op <<= 28; 13761 Value |= op; 13762 // op: dst 13763 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13764 op &= UINT64_C(15); 13765 Value |= op; 13766 break; 13767 } 13768 case ARM::BL_pred: { 13769 // op: p 13770 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13771 op &= UINT64_C(15); 13772 op <<= 28; 13773 Value |= op; 13774 // op: func 13775 op = getARMBLTargetOpValue(MI, 0, Fixups, STI); 13776 op &= UINT64_C(16777215); 13777 Value |= op; 13778 break; 13779 } 13780 case ARM::BLX_pred: 13781 case ARM::BXJ: { 13782 // op: p 13783 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13784 op &= UINT64_C(15); 13785 op <<= 28; 13786 Value |= op; 13787 // op: func 13788 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13789 op &= UINT64_C(15); 13790 Value |= op; 13791 break; 13792 } 13793 case ARM::HINT: { 13794 // op: p 13795 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13796 op &= UINT64_C(15); 13797 op <<= 28; 13798 Value |= op; 13799 // op: imm 13800 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13801 op &= UINT64_C(255); 13802 Value |= op; 13803 break; 13804 } 13805 case ARM::DBG: 13806 case ARM::SMC: { 13807 // op: p 13808 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13809 op &= UINT64_C(15); 13810 op <<= 28; 13811 Value |= op; 13812 // op: opt 13813 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13814 op &= UINT64_C(15); 13815 Value |= op; 13816 break; 13817 } 13818 case ARM::LDMDA: 13819 case ARM::LDMDB: 13820 case ARM::LDMIA: 13821 case ARM::LDMIB: 13822 case ARM::STMDA: 13823 case ARM::STMDB: 13824 case ARM::STMIA: 13825 case ARM::STMIB: 13826 case ARM::sysLDMDA: 13827 case ARM::sysLDMDB: 13828 case ARM::sysLDMIA: 13829 case ARM::sysLDMIB: 13830 case ARM::sysSTMDA: 13831 case ARM::sysSTMDB: 13832 case ARM::sysSTMIA: 13833 case ARM::sysSTMIB: { 13834 // op: p 13835 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13836 op &= UINT64_C(15); 13837 op <<= 28; 13838 Value |= op; 13839 // op: regs 13840 op = getRegisterListOpValue(MI, 3, Fixups, STI); 13841 op &= UINT64_C(65535); 13842 Value |= op; 13843 // op: Rn 13844 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13845 op &= UINT64_C(15); 13846 op <<= 16; 13847 Value |= op; 13848 break; 13849 } 13850 case ARM::SVC: { 13851 // op: p 13852 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13853 op &= UINT64_C(15); 13854 op <<= 28; 13855 Value |= op; 13856 // op: svc 13857 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13858 op &= UINT64_C(16777215); 13859 Value |= op; 13860 break; 13861 } 13862 case ARM::Bcc: { 13863 // op: p 13864 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13865 op &= UINT64_C(15); 13866 op <<= 28; 13867 Value |= op; 13868 // op: target 13869 op = getARMBranchTargetOpValue(MI, 0, Fixups, STI); 13870 op &= UINT64_C(16777215); 13871 Value |= op; 13872 break; 13873 } 13874 case ARM::tBcc: { 13875 // op: p 13876 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13877 op &= UINT64_C(15); 13878 op <<= 8; 13879 Value |= op; 13880 // op: target 13881 op = getThumbBCCTargetOpValue(MI, 0, Fixups, STI); 13882 op &= UINT64_C(255); 13883 Value |= op; 13884 break; 13885 } 13886 case ARM::VABSD: 13887 case ARM::VCMPD: 13888 case ARM::VCMPED: 13889 case ARM::VMOVD: 13890 case ARM::VNEGD: 13891 case ARM::VRINTRD: 13892 case ARM::VRINTXD: 13893 case ARM::VRINTZD: 13894 case ARM::VSQRTD: { 13895 // op: p 13896 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13897 op &= UINT64_C(15); 13898 op <<= 28; 13899 Value |= op; 13900 // op: Dd 13901 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13902 Value |= (op & UINT64_C(16)) << 18; 13903 Value |= (op & UINT64_C(15)) << 12; 13904 // op: Dm 13905 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13906 Value |= (op & UINT64_C(16)) << 1; 13907 Value |= (op & UINT64_C(15)); 13908 Value = VFPThumb2PostEncoder(MI, Value, STI); 13909 break; 13910 } 13911 case ARM::VCVTBHD: 13912 case ARM::VCVTTHD: 13913 case ARM::VSITOD: 13914 case ARM::VUITOD: { 13915 // op: p 13916 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13917 op &= UINT64_C(15); 13918 op <<= 28; 13919 Value |= op; 13920 // op: Dd 13921 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13922 Value |= (op & UINT64_C(16)) << 18; 13923 Value |= (op & UINT64_C(15)) << 12; 13924 // op: Sm 13925 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13926 Value |= (op & UINT64_C(1)) << 5; 13927 Value |= (op & UINT64_C(30)) >> 1; 13928 Value = VFPThumb2PostEncoder(MI, Value, STI); 13929 break; 13930 } 13931 case ARM::FCONSTD: { 13932 // op: p 13933 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13934 op &= UINT64_C(15); 13935 op <<= 28; 13936 Value |= op; 13937 // op: Dd 13938 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13939 Value |= (op & UINT64_C(16)) << 18; 13940 Value |= (op & UINT64_C(15)) << 12; 13941 // op: imm 13942 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13943 Value |= (op & UINT64_C(240)) << 12; 13944 Value |= (op & UINT64_C(15)); 13945 Value = VFPThumb2PostEncoder(MI, Value, STI); 13946 break; 13947 } 13948 case ARM::CLZ: 13949 case ARM::RBIT: 13950 case ARM::REV: 13951 case ARM::REV16: 13952 case ARM::REVSH: { 13953 // op: p 13954 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13955 op &= UINT64_C(15); 13956 op <<= 28; 13957 Value |= op; 13958 // op: Rd 13959 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13960 op &= UINT64_C(15); 13961 op <<= 12; 13962 Value |= op; 13963 // op: Rm 13964 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13965 op &= UINT64_C(15); 13966 Value |= op; 13967 break; 13968 } 13969 case ARM::MOVi16: { 13970 // op: p 13971 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13972 op &= UINT64_C(15); 13973 op <<= 28; 13974 Value |= op; 13975 // op: Rd 13976 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13977 op &= UINT64_C(15); 13978 op <<= 12; 13979 Value |= op; 13980 // op: imm 13981 op = getHiLo16ImmOpValue(MI, 1, Fixups, STI); 13982 Value |= (op & UINT64_C(61440)) << 4; 13983 Value |= (op & UINT64_C(4095)); 13984 break; 13985 } 13986 case ARM::ADR: { 13987 // op: p 13988 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13989 op &= UINT64_C(15); 13990 op <<= 28; 13991 Value |= op; 13992 // op: Rd 13993 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13994 op &= UINT64_C(15); 13995 op <<= 12; 13996 Value |= op; 13997 // op: label 13998 op = getAdrLabelOpValue(MI, 1, Fixups, STI); 13999 Value |= (op & UINT64_C(12288)) << 10; 14000 Value |= (op & UINT64_C(4095)); 14001 break; 14002 } 14003 case ARM::CMNzrr: 14004 case ARM::CMPrr: 14005 case ARM::TEQrr: 14006 case ARM::TSTrr: { 14007 // op: p 14008 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14009 op &= UINT64_C(15); 14010 op <<= 28; 14011 Value |= op; 14012 // op: Rn 14013 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14014 op &= UINT64_C(15); 14015 op <<= 16; 14016 Value |= op; 14017 // op: Rm 14018 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14019 op &= UINT64_C(15); 14020 Value |= op; 14021 break; 14022 } 14023 case ARM::CMNri: 14024 case ARM::CMPri: 14025 case ARM::TEQri: 14026 case ARM::TSTri: { 14027 // op: p 14028 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14029 op &= UINT64_C(15); 14030 op <<= 28; 14031 Value |= op; 14032 // op: Rn 14033 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14034 op &= UINT64_C(15); 14035 op <<= 16; 14036 Value |= op; 14037 // op: imm 14038 op = getModImmOpValue(MI, 1, Fixups, STI); 14039 op &= UINT64_C(4095); 14040 Value |= op; 14041 break; 14042 } 14043 case ARM::VLDMSDB_UPD: 14044 case ARM::VLDMSIA_UPD: 14045 case ARM::VSTMSDB_UPD: 14046 case ARM::VSTMSIA_UPD: { 14047 // op: p 14048 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14049 op &= UINT64_C(15); 14050 op <<= 28; 14051 Value |= op; 14052 // op: Rn 14053 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14054 op &= UINT64_C(15); 14055 op <<= 16; 14056 Value |= op; 14057 // op: regs 14058 op = getRegisterListOpValue(MI, 4, Fixups, STI); 14059 Value |= (op & UINT64_C(256)) << 14; 14060 Value |= (op & UINT64_C(7680)) << 3; 14061 Value |= (op & UINT64_C(255)); 14062 Value = VFPThumb2PostEncoder(MI, Value, STI); 14063 break; 14064 } 14065 case ARM::FLDMXDB_UPD: 14066 case ARM::FLDMXIA_UPD: 14067 case ARM::FSTMXDB_UPD: 14068 case ARM::FSTMXIA_UPD: { 14069 // op: p 14070 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14071 op &= UINT64_C(15); 14072 op <<= 28; 14073 Value |= op; 14074 // op: Rn 14075 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14076 op &= UINT64_C(15); 14077 op <<= 16; 14078 Value |= op; 14079 // op: regs 14080 op = getRegisterListOpValue(MI, 4, Fixups, STI); 14081 Value |= (op & UINT64_C(3840)) << 4; 14082 Value |= (op & UINT64_C(254)); 14083 Value = VFPThumb2PostEncoder(MI, Value, STI); 14084 break; 14085 } 14086 case ARM::VLDMDDB_UPD: 14087 case ARM::VLDMDIA_UPD: 14088 case ARM::VSTMDDB_UPD: 14089 case ARM::VSTMDIA_UPD: { 14090 // op: p 14091 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14092 op &= UINT64_C(15); 14093 op <<= 28; 14094 Value |= op; 14095 // op: Rn 14096 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14097 op &= UINT64_C(15); 14098 op <<= 16; 14099 Value |= op; 14100 // op: regs 14101 op = getRegisterListOpValue(MI, 4, Fixups, STI); 14102 Value |= (op & UINT64_C(4096)) << 10; 14103 Value |= (op & UINT64_C(3840)) << 4; 14104 Value |= (op & UINT64_C(254)); 14105 Value = VFPThumb2PostEncoder(MI, Value, STI); 14106 break; 14107 } 14108 case ARM::STL: 14109 case ARM::STLB: 14110 case ARM::STLH: { 14111 // op: p 14112 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14113 op &= UINT64_C(15); 14114 op <<= 28; 14115 Value |= op; 14116 // op: Rt 14117 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14118 op &= UINT64_C(15); 14119 Value |= op; 14120 // op: addr 14121 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14122 op &= UINT64_C(15); 14123 op <<= 16; 14124 Value |= op; 14125 break; 14126 } 14127 case ARM::VMOVRH: 14128 case ARM::VMOVRS: { 14129 // op: p 14130 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14131 op &= UINT64_C(15); 14132 op <<= 28; 14133 Value |= op; 14134 // op: Rt 14135 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14136 op &= UINT64_C(15); 14137 op <<= 12; 14138 Value |= op; 14139 // op: Sn 14140 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14141 Value |= (op & UINT64_C(30)) << 15; 14142 Value |= (op & UINT64_C(1)) << 7; 14143 Value = VFPThumb2PostEncoder(MI, Value, STI); 14144 break; 14145 } 14146 case ARM::LDA: 14147 case ARM::LDAB: 14148 case ARM::LDAEX: 14149 case ARM::LDAEXB: 14150 case ARM::LDAEXD: 14151 case ARM::LDAEXH: 14152 case ARM::LDAH: 14153 case ARM::LDREX: 14154 case ARM::LDREXB: 14155 case ARM::LDREXD: 14156 case ARM::LDREXH: { 14157 // op: p 14158 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14159 op &= UINT64_C(15); 14160 op <<= 28; 14161 Value |= op; 14162 // op: Rt 14163 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14164 op &= UINT64_C(15); 14165 op <<= 12; 14166 Value |= op; 14167 // op: addr 14168 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14169 op &= UINT64_C(15); 14170 op <<= 16; 14171 Value |= op; 14172 break; 14173 } 14174 case ARM::VMRS_FPSCR_NZCVQC: 14175 case ARM::VMRS_P0: { 14176 // op: p 14177 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14178 op &= UINT64_C(15); 14179 op <<= 28; 14180 Value |= op; 14181 // op: Rt 14182 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14183 op &= UINT64_C(15); 14184 op <<= 12; 14185 Value |= op; 14186 Value = VFPThumb2PostEncoder(MI, Value, STI); 14187 break; 14188 } 14189 case ARM::VMSR_FPSCR_NZCVQC: 14190 case ARM::VMSR_P0: { 14191 // op: p 14192 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14193 op &= UINT64_C(15); 14194 op <<= 28; 14195 Value |= op; 14196 // op: Rt 14197 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14198 op &= UINT64_C(15); 14199 op <<= 12; 14200 Value |= op; 14201 Value = VFPThumb2PostEncoder(MI, Value, STI); 14202 break; 14203 } 14204 case ARM::VCVTSD: 14205 case ARM::VJCVT: 14206 case ARM::VTOSIRD: 14207 case ARM::VTOSIZD: 14208 case ARM::VTOUIRD: 14209 case ARM::VTOUIZD: { 14210 // op: p 14211 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14212 op &= UINT64_C(15); 14213 op <<= 28; 14214 Value |= op; 14215 // op: Sd 14216 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14217 Value |= (op & UINT64_C(1)) << 22; 14218 Value |= (op & UINT64_C(30)) << 11; 14219 // op: Dm 14220 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14221 Value |= (op & UINT64_C(16)) << 1; 14222 Value |= (op & UINT64_C(15)); 14223 Value = VFPThumb2PostEncoder(MI, Value, STI); 14224 break; 14225 } 14226 case ARM::VABSH: 14227 case ARM::VABSS: 14228 case ARM::VCMPEH: 14229 case ARM::VCMPES: 14230 case ARM::VCMPH: 14231 case ARM::VCMPS: 14232 case ARM::VCVTBHS: 14233 case ARM::VCVTTHS: 14234 case ARM::VMOVS: 14235 case ARM::VNEGH: 14236 case ARM::VNEGS: 14237 case ARM::VRINTRH: 14238 case ARM::VRINTRS: 14239 case ARM::VRINTXH: 14240 case ARM::VRINTXS: 14241 case ARM::VRINTZH: 14242 case ARM::VRINTZS: 14243 case ARM::VSITOH: 14244 case ARM::VSITOS: 14245 case ARM::VSQRTH: 14246 case ARM::VSQRTS: 14247 case ARM::VTOSIRH: 14248 case ARM::VTOSIRS: 14249 case ARM::VTOSIZH: 14250 case ARM::VTOSIZS: 14251 case ARM::VTOUIRH: 14252 case ARM::VTOUIRS: 14253 case ARM::VTOUIZH: 14254 case ARM::VTOUIZS: 14255 case ARM::VUITOH: 14256 case ARM::VUITOS: { 14257 // op: p 14258 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14259 op &= UINT64_C(15); 14260 op <<= 28; 14261 Value |= op; 14262 // op: Sd 14263 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14264 Value |= (op & UINT64_C(1)) << 22; 14265 Value |= (op & UINT64_C(30)) << 11; 14266 // op: Sm 14267 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14268 Value |= (op & UINT64_C(1)) << 5; 14269 Value |= (op & UINT64_C(30)) >> 1; 14270 Value = VFPThumb2PostEncoder(MI, Value, STI); 14271 break; 14272 } 14273 case ARM::FCONSTH: 14274 case ARM::FCONSTS: { 14275 // op: p 14276 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14277 op &= UINT64_C(15); 14278 op <<= 28; 14279 Value |= op; 14280 // op: Sd 14281 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14282 Value |= (op & UINT64_C(1)) << 22; 14283 Value |= (op & UINT64_C(30)) << 11; 14284 // op: imm 14285 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14286 Value |= (op & UINT64_C(240)) << 12; 14287 Value |= (op & UINT64_C(15)); 14288 Value = VFPThumb2PostEncoder(MI, Value, STI); 14289 break; 14290 } 14291 case ARM::VCVTDS: { 14292 // op: p 14293 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14294 op &= UINT64_C(15); 14295 op <<= 28; 14296 Value |= op; 14297 // op: Sm 14298 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14299 Value |= (op & UINT64_C(1)) << 5; 14300 Value |= (op & UINT64_C(30)) >> 1; 14301 // op: Dd 14302 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14303 Value |= (op & UINT64_C(16)) << 18; 14304 Value |= (op & UINT64_C(15)) << 12; 14305 Value = VFPThumb2PostEncoder(MI, Value, STI); 14306 break; 14307 } 14308 case ARM::VMOVHR: 14309 case ARM::VMOVSR: { 14310 // op: p 14311 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14312 op &= UINT64_C(15); 14313 op <<= 28; 14314 Value |= op; 14315 // op: Sn 14316 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14317 Value |= (op & UINT64_C(30)) << 15; 14318 Value |= (op & UINT64_C(1)) << 7; 14319 // op: Rt 14320 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14321 op &= UINT64_C(15); 14322 op <<= 12; 14323 Value |= op; 14324 Value = VFPThumb2PostEncoder(MI, Value, STI); 14325 break; 14326 } 14327 case ARM::VLDR_FPCXTNS_off: 14328 case ARM::VLDR_FPCXTS_off: 14329 case ARM::VLDR_FPSCR_NZCVQC_off: 14330 case ARM::VLDR_FPSCR_off: 14331 case ARM::VLDR_VPR_off: 14332 case ARM::VSTR_FPCXTNS_off: 14333 case ARM::VSTR_FPCXTS_off: 14334 case ARM::VSTR_FPSCR_NZCVQC_off: 14335 case ARM::VSTR_FPSCR_off: 14336 case ARM::VSTR_VPR_off: { 14337 // op: p 14338 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14339 op &= UINT64_C(15); 14340 op <<= 28; 14341 Value |= op; 14342 // op: addr 14343 op = getT2AddrModeImm7s4OpValue(MI, 0, Fixups, STI); 14344 Value |= (op & UINT64_C(128)) << 16; 14345 Value |= (op & UINT64_C(3840)) << 8; 14346 Value |= (op & UINT64_C(127)); 14347 Value = VFPThumb2PostEncoder(MI, Value, STI); 14348 break; 14349 } 14350 case ARM::MSRbanked: { 14351 // op: p 14352 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14353 op &= UINT64_C(15); 14354 op <<= 28; 14355 Value |= op; 14356 // op: banked 14357 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14358 Value |= (op & UINT64_C(32)) << 17; 14359 Value |= (op & UINT64_C(15)) << 16; 14360 Value |= (op & UINT64_C(16)) << 4; 14361 // op: Rn 14362 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14363 op &= UINT64_C(15); 14364 Value |= op; 14365 break; 14366 } 14367 case ARM::MRSbanked: { 14368 // op: p 14369 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14370 op &= UINT64_C(15); 14371 op <<= 28; 14372 Value |= op; 14373 // op: banked 14374 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14375 Value |= (op & UINT64_C(32)) << 17; 14376 Value |= (op & UINT64_C(15)) << 16; 14377 Value |= (op & UINT64_C(16)) << 4; 14378 // op: Rd 14379 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14380 op &= UINT64_C(15); 14381 op <<= 12; 14382 Value |= op; 14383 break; 14384 } 14385 case ARM::MSR: { 14386 // op: p 14387 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14388 op &= UINT64_C(15); 14389 op <<= 28; 14390 Value |= op; 14391 // op: mask 14392 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14393 Value |= (op & UINT64_C(16)) << 18; 14394 Value |= (op & UINT64_C(15)) << 16; 14395 // op: Rn 14396 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14397 op &= UINT64_C(15); 14398 Value |= op; 14399 break; 14400 } 14401 case ARM::MSRi: { 14402 // op: p 14403 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14404 op &= UINT64_C(15); 14405 op <<= 28; 14406 Value |= op; 14407 // op: mask 14408 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14409 Value |= (op & UINT64_C(16)) << 18; 14410 Value |= (op & UINT64_C(15)) << 16; 14411 // op: imm 14412 op = getModImmOpValue(MI, 1, Fixups, STI); 14413 op &= UINT64_C(4095); 14414 Value |= op; 14415 break; 14416 } 14417 case ARM::LDMDA_UPD: 14418 case ARM::LDMDB_UPD: 14419 case ARM::LDMIA_UPD: 14420 case ARM::LDMIB_UPD: 14421 case ARM::STMDA_UPD: 14422 case ARM::STMDB_UPD: 14423 case ARM::STMIA_UPD: 14424 case ARM::STMIB_UPD: 14425 case ARM::sysLDMDA_UPD: 14426 case ARM::sysLDMDB_UPD: 14427 case ARM::sysLDMIA_UPD: 14428 case ARM::sysLDMIB_UPD: 14429 case ARM::sysSTMDA_UPD: 14430 case ARM::sysSTMDB_UPD: 14431 case ARM::sysSTMIA_UPD: 14432 case ARM::sysSTMIB_UPD: { 14433 // op: p 14434 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14435 op &= UINT64_C(15); 14436 op <<= 28; 14437 Value |= op; 14438 // op: regs 14439 op = getRegisterListOpValue(MI, 4, Fixups, STI); 14440 op &= UINT64_C(65535); 14441 Value |= op; 14442 // op: Rn 14443 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14444 op &= UINT64_C(15); 14445 op <<= 16; 14446 Value |= op; 14447 break; 14448 } 14449 case ARM::MOVr: 14450 case ARM::MOVr_TC: 14451 case ARM::MVNr: { 14452 // op: p 14453 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14454 op &= UINT64_C(15); 14455 op <<= 28; 14456 Value |= op; 14457 // op: s 14458 op = getCCOutOpValue(MI, 4, Fixups, STI); 14459 op &= UINT64_C(1); 14460 op <<= 20; 14461 Value |= op; 14462 // op: Rd 14463 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14464 op &= UINT64_C(15); 14465 op <<= 12; 14466 Value |= op; 14467 // op: Rm 14468 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14469 op &= UINT64_C(15); 14470 Value |= op; 14471 break; 14472 } 14473 case ARM::MOVi: 14474 case ARM::MVNi: { 14475 // op: p 14476 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14477 op &= UINT64_C(15); 14478 op <<= 28; 14479 Value |= op; 14480 // op: s 14481 op = getCCOutOpValue(MI, 4, Fixups, STI); 14482 op &= UINT64_C(1); 14483 op <<= 20; 14484 Value |= op; 14485 // op: Rd 14486 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14487 op &= UINT64_C(15); 14488 op <<= 12; 14489 Value |= op; 14490 // op: imm 14491 op = getModImmOpValue(MI, 1, Fixups, STI); 14492 op &= UINT64_C(4095); 14493 Value |= op; 14494 break; 14495 } 14496 case ARM::VADDD: 14497 case ARM::VDIVD: 14498 case ARM::VMULD: 14499 case ARM::VNMULD: 14500 case ARM::VSUBD: { 14501 // op: p 14502 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14503 op &= UINT64_C(15); 14504 op <<= 28; 14505 Value |= op; 14506 // op: Dd 14507 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14508 Value |= (op & UINT64_C(16)) << 18; 14509 Value |= (op & UINT64_C(15)) << 12; 14510 // op: Dn 14511 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14512 Value |= (op & UINT64_C(15)) << 16; 14513 Value |= (op & UINT64_C(16)) << 3; 14514 // op: Dm 14515 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14516 Value |= (op & UINT64_C(16)) << 1; 14517 Value |= (op & UINT64_C(15)); 14518 Value = VFPThumb2PostEncoder(MI, Value, STI); 14519 break; 14520 } 14521 case ARM::VLDRD: 14522 case ARM::VSTRD: { 14523 // op: p 14524 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14525 op &= UINT64_C(15); 14526 op <<= 28; 14527 Value |= op; 14528 // op: Dd 14529 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14530 Value |= (op & UINT64_C(16)) << 18; 14531 Value |= (op & UINT64_C(15)) << 12; 14532 // op: addr 14533 op = getAddrMode5OpValue(MI, 1, Fixups, STI); 14534 Value |= (op & UINT64_C(256)) << 15; 14535 Value |= (op & UINT64_C(7680)) << 7; 14536 Value |= (op & UINT64_C(255)); 14537 Value = VFPThumb2PostEncoder(MI, Value, STI); 14538 break; 14539 } 14540 case ARM::VMOVDRR: { 14541 // op: p 14542 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14543 op &= UINT64_C(15); 14544 op <<= 28; 14545 Value |= op; 14546 // op: Dm 14547 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14548 Value |= (op & UINT64_C(16)) << 1; 14549 Value |= (op & UINT64_C(15)); 14550 // op: Rt 14551 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14552 op &= UINT64_C(15); 14553 op <<= 12; 14554 Value |= op; 14555 // op: Rt2 14556 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14557 op &= UINT64_C(15); 14558 op <<= 16; 14559 Value |= op; 14560 Value = VFPThumb2PostEncoder(MI, Value, STI); 14561 break; 14562 } 14563 case ARM::VMOVRRD: { 14564 // op: p 14565 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14566 op &= UINT64_C(15); 14567 op <<= 28; 14568 Value |= op; 14569 // op: Dm 14570 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14571 Value |= (op & UINT64_C(16)) << 1; 14572 Value |= (op & UINT64_C(15)); 14573 // op: Rt 14574 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14575 op &= UINT64_C(15); 14576 op <<= 12; 14577 Value |= op; 14578 // op: Rt2 14579 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14580 op &= UINT64_C(15); 14581 op <<= 16; 14582 Value |= op; 14583 Value = VFPThumb2PostEncoder(MI, Value, STI); 14584 break; 14585 } 14586 case ARM::VCVTBDH: 14587 case ARM::VCVTTDH: { 14588 // op: p 14589 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14590 op &= UINT64_C(15); 14591 op <<= 28; 14592 Value |= op; 14593 // op: Dm 14594 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14595 Value |= (op & UINT64_C(16)) << 1; 14596 Value |= (op & UINT64_C(15)); 14597 // op: Sd 14598 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14599 Value |= (op & UINT64_C(1)) << 22; 14600 Value |= (op & UINT64_C(30)) << 11; 14601 Value = VFPThumb2PostEncoder(MI, Value, STI); 14602 break; 14603 } 14604 case ARM::SXTB: 14605 case ARM::SXTB16: 14606 case ARM::SXTH: 14607 case ARM::UXTB: 14608 case ARM::UXTB16: 14609 case ARM::UXTH: { 14610 // op: p 14611 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14612 op &= UINT64_C(15); 14613 op <<= 28; 14614 Value |= op; 14615 // op: Rd 14616 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14617 op &= UINT64_C(15); 14618 op <<= 12; 14619 Value |= op; 14620 // op: Rm 14621 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14622 op &= UINT64_C(15); 14623 Value |= op; 14624 // op: rot 14625 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14626 op &= UINT64_C(3); 14627 op <<= 10; 14628 Value |= op; 14629 break; 14630 } 14631 case ARM::SEL: { 14632 // op: p 14633 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14634 op &= UINT64_C(15); 14635 op <<= 28; 14636 Value |= op; 14637 // op: Rd 14638 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14639 op &= UINT64_C(15); 14640 op <<= 12; 14641 Value |= op; 14642 // op: Rn 14643 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14644 op &= UINT64_C(15); 14645 op <<= 16; 14646 Value |= op; 14647 // op: Rm 14648 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14649 op &= UINT64_C(15); 14650 Value |= op; 14651 break; 14652 } 14653 case ARM::BFC: { 14654 // op: p 14655 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14656 op &= UINT64_C(15); 14657 op <<= 28; 14658 Value |= op; 14659 // op: Rd 14660 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14661 op &= UINT64_C(15); 14662 op <<= 12; 14663 Value |= op; 14664 // op: imm 14665 op = getBitfieldInvertedMaskOpValue(MI, 2, Fixups, STI); 14666 Value |= (op & UINT64_C(992)) << 11; 14667 Value |= (op & UINT64_C(31)) << 7; 14668 break; 14669 } 14670 case ARM::MOVTi16: { 14671 // op: p 14672 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14673 op &= UINT64_C(15); 14674 op <<= 28; 14675 Value |= op; 14676 // op: Rd 14677 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14678 op &= UINT64_C(15); 14679 op <<= 12; 14680 Value |= op; 14681 // op: imm 14682 op = getHiLo16ImmOpValue(MI, 2, Fixups, STI); 14683 Value |= (op & UINT64_C(61440)) << 4; 14684 Value |= (op & UINT64_C(4095)); 14685 break; 14686 } 14687 case ARM::SSAT16: 14688 case ARM::USAT16: { 14689 // op: p 14690 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14691 op &= UINT64_C(15); 14692 op <<= 28; 14693 Value |= op; 14694 // op: Rd 14695 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14696 op &= UINT64_C(15); 14697 op <<= 12; 14698 Value |= op; 14699 // op: sat_imm 14700 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14701 op &= UINT64_C(15); 14702 op <<= 16; 14703 Value |= op; 14704 // op: Rn 14705 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14706 op &= UINT64_C(15); 14707 Value |= op; 14708 break; 14709 } 14710 case ARM::SDIV: 14711 case ARM::SMMUL: 14712 case ARM::SMMULR: 14713 case ARM::UDIV: 14714 case ARM::USAD8: { 14715 // op: p 14716 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14717 op &= UINT64_C(15); 14718 op <<= 28; 14719 Value |= op; 14720 // op: Rd 14721 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14722 op &= UINT64_C(15); 14723 op <<= 16; 14724 Value |= op; 14725 // op: Rn 14726 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14727 op &= UINT64_C(15); 14728 Value |= op; 14729 // op: Rm 14730 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14731 op &= UINT64_C(15); 14732 op <<= 8; 14733 Value |= op; 14734 break; 14735 } 14736 case ARM::CMNzrsi: 14737 case ARM::CMPrsi: 14738 case ARM::TEQrsi: 14739 case ARM::TSTrsi: { 14740 // op: p 14741 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14742 op &= UINT64_C(15); 14743 op <<= 28; 14744 Value |= op; 14745 // op: Rn 14746 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14747 op &= UINT64_C(15); 14748 op <<= 16; 14749 Value |= op; 14750 // op: shift 14751 op = getSORegImmOpValue(MI, 1, Fixups, STI); 14752 Value |= (op & UINT64_C(4064)); 14753 Value |= (op & UINT64_C(15)); 14754 break; 14755 } 14756 case ARM::SMUAD: 14757 case ARM::SMUADX: 14758 case ARM::SMULBB: 14759 case ARM::SMULBT: 14760 case ARM::SMULTB: 14761 case ARM::SMULTT: 14762 case ARM::SMULWB: 14763 case ARM::SMULWT: 14764 case ARM::SMUSD: 14765 case ARM::SMUSDX: { 14766 // op: p 14767 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14768 op &= UINT64_C(15); 14769 op <<= 28; 14770 Value |= op; 14771 // op: Rn 14772 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14773 op &= UINT64_C(15); 14774 Value |= op; 14775 // op: Rm 14776 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14777 op &= UINT64_C(15); 14778 op <<= 8; 14779 Value |= op; 14780 // op: Rd 14781 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14782 op &= UINT64_C(15); 14783 op <<= 16; 14784 Value |= op; 14785 break; 14786 } 14787 case ARM::QADD16: 14788 case ARM::QADD8: 14789 case ARM::QASX: 14790 case ARM::QSAX: 14791 case ARM::QSUB16: 14792 case ARM::QSUB8: 14793 case ARM::SADD16: 14794 case ARM::SADD8: 14795 case ARM::SASX: 14796 case ARM::SHADD16: 14797 case ARM::SHADD8: 14798 case ARM::SHASX: 14799 case ARM::SHSAX: 14800 case ARM::SHSUB16: 14801 case ARM::SHSUB8: 14802 case ARM::SSAX: 14803 case ARM::SSUB16: 14804 case ARM::SSUB8: 14805 case ARM::UADD16: 14806 case ARM::UADD8: 14807 case ARM::UASX: 14808 case ARM::UHADD16: 14809 case ARM::UHADD8: 14810 case ARM::UHASX: 14811 case ARM::UHSAX: 14812 case ARM::UHSUB16: 14813 case ARM::UHSUB8: 14814 case ARM::UQADD16: 14815 case ARM::UQADD8: 14816 case ARM::UQASX: 14817 case ARM::UQSAX: 14818 case ARM::UQSUB16: 14819 case ARM::UQSUB8: 14820 case ARM::USAX: 14821 case ARM::USUB16: 14822 case ARM::USUB8: { 14823 // op: p 14824 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14825 op &= UINT64_C(15); 14826 op <<= 28; 14827 Value |= op; 14828 // op: Rn 14829 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14830 op &= UINT64_C(15); 14831 op <<= 16; 14832 Value |= op; 14833 // op: Rd 14834 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14835 op &= UINT64_C(15); 14836 op <<= 12; 14837 Value |= op; 14838 // op: Rm 14839 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14840 op &= UINT64_C(15); 14841 Value |= op; 14842 break; 14843 } 14844 case ARM::QADD: 14845 case ARM::QDADD: 14846 case ARM::QDSUB: 14847 case ARM::QSUB: { 14848 // op: p 14849 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14850 op &= UINT64_C(15); 14851 op <<= 28; 14852 Value |= op; 14853 // op: Rn 14854 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14855 op &= UINT64_C(15); 14856 op <<= 16; 14857 Value |= op; 14858 // op: Rd 14859 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14860 op &= UINT64_C(15); 14861 op <<= 12; 14862 Value |= op; 14863 // op: Rm 14864 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14865 op &= UINT64_C(15); 14866 Value |= op; 14867 break; 14868 } 14869 case ARM::SWP: 14870 case ARM::SWPB: { 14871 // op: p 14872 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14873 op &= UINT64_C(15); 14874 op <<= 28; 14875 Value |= op; 14876 // op: Rt 14877 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14878 op &= UINT64_C(15); 14879 op <<= 12; 14880 Value |= op; 14881 // op: Rt2 14882 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14883 op &= UINT64_C(15); 14884 Value |= op; 14885 // op: addr 14886 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14887 op &= UINT64_C(15); 14888 op <<= 16; 14889 Value |= op; 14890 break; 14891 } 14892 case ARM::LDRBi12: 14893 case ARM::LDRi12: 14894 case ARM::STRBi12: 14895 case ARM::STRi12: { 14896 // op: p 14897 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14898 op &= UINT64_C(15); 14899 op <<= 28; 14900 Value |= op; 14901 // op: Rt 14902 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14903 op &= UINT64_C(15); 14904 op <<= 12; 14905 Value |= op; 14906 // op: addr 14907 op = getAddrModeImm12OpValue(MI, 1, Fixups, STI); 14908 Value |= (op & UINT64_C(4096)) << 11; 14909 Value |= (op & UINT64_C(122880)) << 3; 14910 Value |= (op & UINT64_C(4095)); 14911 break; 14912 } 14913 case ARM::LDRcp: { 14914 // op: p 14915 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14916 op &= UINT64_C(15); 14917 op <<= 28; 14918 Value |= op; 14919 // op: Rt 14920 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14921 op &= UINT64_C(15); 14922 op <<= 12; 14923 Value |= op; 14924 // op: addr 14925 op = getAddrModeImm12OpValue(MI, 1, Fixups, STI); 14926 Value |= (op & UINT64_C(4096)) << 11; 14927 Value |= (op & UINT64_C(4095)); 14928 break; 14929 } 14930 case ARM::STLEX: 14931 case ARM::STLEXB: 14932 case ARM::STLEXD: 14933 case ARM::STLEXH: 14934 case ARM::STREX: 14935 case ARM::STREXB: 14936 case ARM::STREXD: 14937 case ARM::STREXH: { 14938 // op: p 14939 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14940 op &= UINT64_C(15); 14941 op <<= 28; 14942 Value |= op; 14943 // op: Rt 14944 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14945 op &= UINT64_C(15); 14946 Value |= op; 14947 // op: addr 14948 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14949 op &= UINT64_C(15); 14950 op <<= 16; 14951 Value |= op; 14952 // op: Rd 14953 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14954 op &= UINT64_C(15); 14955 op <<= 12; 14956 Value |= op; 14957 break; 14958 } 14959 case ARM::BF16_VCVTB: 14960 case ARM::BF16_VCVTT: 14961 case ARM::VCVTBSH: 14962 case ARM::VCVTTSH: { 14963 // op: p 14964 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14965 op &= UINT64_C(15); 14966 op <<= 28; 14967 Value |= op; 14968 // op: Sd 14969 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14970 Value |= (op & UINT64_C(1)) << 22; 14971 Value |= (op & UINT64_C(30)) << 11; 14972 // op: Sm 14973 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14974 Value |= (op & UINT64_C(1)) << 5; 14975 Value |= (op & UINT64_C(30)) >> 1; 14976 Value = VFPThumb2PostEncoder(MI, Value, STI); 14977 break; 14978 } 14979 case ARM::VADDH: 14980 case ARM::VADDS: 14981 case ARM::VDIVH: 14982 case ARM::VDIVS: 14983 case ARM::VMULH: 14984 case ARM::VMULS: 14985 case ARM::VNMULH: 14986 case ARM::VNMULS: 14987 case ARM::VSUBH: 14988 case ARM::VSUBS: { 14989 // op: p 14990 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14991 op &= UINT64_C(15); 14992 op <<= 28; 14993 Value |= op; 14994 // op: Sd 14995 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14996 Value |= (op & UINT64_C(1)) << 22; 14997 Value |= (op & UINT64_C(30)) << 11; 14998 // op: Sn 14999 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15000 Value |= (op & UINT64_C(30)) << 15; 15001 Value |= (op & UINT64_C(1)) << 7; 15002 // op: Sm 15003 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15004 Value |= (op & UINT64_C(1)) << 5; 15005 Value |= (op & UINT64_C(30)) >> 1; 15006 Value = VFPThumb2PostEncoder(MI, Value, STI); 15007 break; 15008 } 15009 case ARM::VLDRH: 15010 case ARM::VSTRH: { 15011 // op: p 15012 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15013 op &= UINT64_C(15); 15014 op <<= 28; 15015 Value |= op; 15016 // op: Sd 15017 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15018 Value |= (op & UINT64_C(1)) << 22; 15019 Value |= (op & UINT64_C(30)) << 11; 15020 // op: addr 15021 op = getAddrMode5FP16OpValue(MI, 1, Fixups, STI); 15022 Value |= (op & UINT64_C(256)) << 15; 15023 Value |= (op & UINT64_C(7680)) << 7; 15024 Value |= (op & UINT64_C(255)); 15025 Value = VFPThumb2PostEncoder(MI, Value, STI); 15026 break; 15027 } 15028 case ARM::VLDRS: 15029 case ARM::VSTRS: { 15030 // op: p 15031 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15032 op &= UINT64_C(15); 15033 op <<= 28; 15034 Value |= op; 15035 // op: Sd 15036 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15037 Value |= (op & UINT64_C(1)) << 22; 15038 Value |= (op & UINT64_C(30)) << 11; 15039 // op: addr 15040 op = getAddrMode5OpValue(MI, 1, Fixups, STI); 15041 Value |= (op & UINT64_C(256)) << 15; 15042 Value |= (op & UINT64_C(7680)) << 7; 15043 Value |= (op & UINT64_C(255)); 15044 Value = VFPThumb2PostEncoder(MI, Value, STI); 15045 break; 15046 } 15047 case ARM::VLDR_FPCXTNS_pre: 15048 case ARM::VLDR_FPCXTS_pre: 15049 case ARM::VLDR_FPSCR_NZCVQC_pre: 15050 case ARM::VLDR_FPSCR_pre: 15051 case ARM::VLDR_P0_off: 15052 case ARM::VLDR_VPR_pre: 15053 case ARM::VSTR_FPCXTNS_pre: 15054 case ARM::VSTR_FPCXTS_pre: 15055 case ARM::VSTR_FPSCR_NZCVQC_pre: 15056 case ARM::VSTR_FPSCR_pre: 15057 case ARM::VSTR_P0_off: 15058 case ARM::VSTR_VPR_pre: { 15059 // op: p 15060 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15061 op &= UINT64_C(15); 15062 op <<= 28; 15063 Value |= op; 15064 // op: addr 15065 op = getT2AddrModeImm7s4OpValue(MI, 1, Fixups, STI); 15066 Value |= (op & UINT64_C(128)) << 16; 15067 Value |= (op & UINT64_C(3840)) << 8; 15068 Value |= (op & UINT64_C(127)); 15069 Value = VFPThumb2PostEncoder(MI, Value, STI); 15070 break; 15071 } 15072 case ARM::VLDR_FPCXTNS_post: 15073 case ARM::VLDR_FPCXTS_post: 15074 case ARM::VLDR_FPSCR_NZCVQC_post: 15075 case ARM::VLDR_FPSCR_post: 15076 case ARM::VLDR_VPR_post: 15077 case ARM::VSTR_FPCXTNS_post: 15078 case ARM::VSTR_FPCXTS_post: 15079 case ARM::VSTR_FPSCR_NZCVQC_post: 15080 case ARM::VSTR_FPSCR_post: 15081 case ARM::VSTR_VPR_post: { 15082 // op: p 15083 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15084 op &= UINT64_C(15); 15085 op <<= 28; 15086 Value |= op; 15087 // op: addr 15088 op = getT2ScaledImmOpValue<7,2>(MI, 2, Fixups, STI); 15089 Value |= (op & UINT64_C(128)) << 16; 15090 Value |= (op & UINT64_C(127)); 15091 // op: Rn 15092 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15093 op &= UINT64_C(15); 15094 op <<= 16; 15095 Value |= op; 15096 Value = VFPThumb2PostEncoder(MI, Value, STI); 15097 break; 15098 } 15099 case ARM::VSHTOH: 15100 case ARM::VSHTOS: 15101 case ARM::VSLTOH: 15102 case ARM::VSLTOS: 15103 case ARM::VTOSHH: 15104 case ARM::VTOSHS: 15105 case ARM::VTOSLH: 15106 case ARM::VTOSLS: 15107 case ARM::VTOUHH: 15108 case ARM::VTOUHS: 15109 case ARM::VTOULH: 15110 case ARM::VTOULS: 15111 case ARM::VUHTOH: 15112 case ARM::VUHTOS: 15113 case ARM::VULTOH: 15114 case ARM::VULTOS: { 15115 // op: p 15116 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15117 op &= UINT64_C(15); 15118 op <<= 28; 15119 Value |= op; 15120 // op: fbits 15121 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15122 Value |= (op & UINT64_C(1)) << 5; 15123 Value |= (op & UINT64_C(30)) >> 1; 15124 // op: dst 15125 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15126 Value |= (op & UINT64_C(1)) << 22; 15127 Value |= (op & UINT64_C(30)) << 11; 15128 Value = VFPThumb2PostEncoder(MI, Value, STI); 15129 break; 15130 } 15131 case ARM::VSHTOD: 15132 case ARM::VSLTOD: 15133 case ARM::VTOSHD: 15134 case ARM::VTOSLD: 15135 case ARM::VTOUHD: 15136 case ARM::VTOULD: 15137 case ARM::VUHTOD: 15138 case ARM::VULTOD: { 15139 // op: p 15140 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15141 op &= UINT64_C(15); 15142 op <<= 28; 15143 Value |= op; 15144 // op: fbits 15145 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15146 Value |= (op & UINT64_C(1)) << 5; 15147 Value |= (op & UINT64_C(30)) >> 1; 15148 // op: dst 15149 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15150 Value |= (op & UINT64_C(16)) << 18; 15151 Value |= (op & UINT64_C(15)) << 12; 15152 Value = VFPThumb2PostEncoder(MI, Value, STI); 15153 break; 15154 } 15155 case ARM::ADCrr: 15156 case ARM::ADDrr: 15157 case ARM::ANDrr: 15158 case ARM::BICrr: 15159 case ARM::EORrr: 15160 case ARM::ORRrr: 15161 case ARM::RSBrr: 15162 case ARM::RSCrr: 15163 case ARM::SBCrr: 15164 case ARM::SUBrr: { 15165 // op: p 15166 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15167 op &= UINT64_C(15); 15168 op <<= 28; 15169 Value |= op; 15170 // op: s 15171 op = getCCOutOpValue(MI, 5, Fixups, STI); 15172 op &= UINT64_C(1); 15173 op <<= 20; 15174 Value |= op; 15175 // op: Rd 15176 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15177 op &= UINT64_C(15); 15178 op <<= 12; 15179 Value |= op; 15180 // op: Rn 15181 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15182 op &= UINT64_C(15); 15183 op <<= 16; 15184 Value |= op; 15185 // op: Rm 15186 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15187 op &= UINT64_C(15); 15188 Value |= op; 15189 break; 15190 } 15191 case ARM::ADCri: 15192 case ARM::ADDri: 15193 case ARM::ANDri: 15194 case ARM::BICri: 15195 case ARM::EORri: 15196 case ARM::ORRri: 15197 case ARM::RSBri: 15198 case ARM::RSCri: 15199 case ARM::SBCri: 15200 case ARM::SUBri: { 15201 // op: p 15202 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15203 op &= UINT64_C(15); 15204 op <<= 28; 15205 Value |= op; 15206 // op: s 15207 op = getCCOutOpValue(MI, 5, Fixups, STI); 15208 op &= UINT64_C(1); 15209 op <<= 20; 15210 Value |= op; 15211 // op: Rd 15212 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15213 op &= UINT64_C(15); 15214 op <<= 12; 15215 Value |= op; 15216 // op: Rn 15217 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15218 op &= UINT64_C(15); 15219 op <<= 16; 15220 Value |= op; 15221 // op: imm 15222 op = getModImmOpValue(MI, 2, Fixups, STI); 15223 op &= UINT64_C(4095); 15224 Value |= op; 15225 break; 15226 } 15227 case ARM::MVNsi: { 15228 // op: p 15229 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15230 op &= UINT64_C(15); 15231 op <<= 28; 15232 Value |= op; 15233 // op: s 15234 op = getCCOutOpValue(MI, 5, Fixups, STI); 15235 op &= UINT64_C(1); 15236 op <<= 20; 15237 Value |= op; 15238 // op: Rd 15239 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15240 op &= UINT64_C(15); 15241 op <<= 12; 15242 Value |= op; 15243 // op: shift 15244 op = getSORegImmOpValue(MI, 1, Fixups, STI); 15245 Value |= (op & UINT64_C(4064)); 15246 Value |= (op & UINT64_C(15)); 15247 break; 15248 } 15249 case ARM::MOVsi: { 15250 // op: p 15251 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15252 op &= UINT64_C(15); 15253 op <<= 28; 15254 Value |= op; 15255 // op: s 15256 op = getCCOutOpValue(MI, 5, Fixups, STI); 15257 op &= UINT64_C(1); 15258 op <<= 20; 15259 Value |= op; 15260 // op: Rd 15261 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15262 op &= UINT64_C(15); 15263 op <<= 12; 15264 Value |= op; 15265 // op: src 15266 op = getSORegImmOpValue(MI, 1, Fixups, STI); 15267 Value |= (op & UINT64_C(4064)); 15268 Value |= (op & UINT64_C(15)); 15269 break; 15270 } 15271 case ARM::MUL: { 15272 // op: p 15273 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15274 op &= UINT64_C(15); 15275 op <<= 28; 15276 Value |= op; 15277 // op: s 15278 op = getCCOutOpValue(MI, 5, Fixups, STI); 15279 op &= UINT64_C(1); 15280 op <<= 20; 15281 Value |= op; 15282 // op: Rd 15283 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15284 op &= UINT64_C(15); 15285 op <<= 16; 15286 Value |= op; 15287 // op: Rm 15288 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15289 op &= UINT64_C(15); 15290 op <<= 8; 15291 Value |= op; 15292 // op: Rn 15293 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15294 op &= UINT64_C(15); 15295 Value |= op; 15296 break; 15297 } 15298 case ARM::VFMAD: 15299 case ARM::VFMSD: 15300 case ARM::VFNMAD: 15301 case ARM::VFNMSD: 15302 case ARM::VMLAD: 15303 case ARM::VMLSD: 15304 case ARM::VNMLAD: 15305 case ARM::VNMLSD: { 15306 // op: p 15307 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15308 op &= UINT64_C(15); 15309 op <<= 28; 15310 Value |= op; 15311 // op: Dd 15312 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15313 Value |= (op & UINT64_C(16)) << 18; 15314 Value |= (op & UINT64_C(15)) << 12; 15315 // op: Dn 15316 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15317 Value |= (op & UINT64_C(15)) << 16; 15318 Value |= (op & UINT64_C(16)) << 3; 15319 // op: Dm 15320 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15321 Value |= (op & UINT64_C(16)) << 1; 15322 Value |= (op & UINT64_C(15)); 15323 Value = VFPThumb2PostEncoder(MI, Value, STI); 15324 break; 15325 } 15326 case ARM::SXTAB: 15327 case ARM::SXTAB16: 15328 case ARM::SXTAH: 15329 case ARM::UXTAB: 15330 case ARM::UXTAB16: 15331 case ARM::UXTAH: { 15332 // op: p 15333 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15334 op &= UINT64_C(15); 15335 op <<= 28; 15336 Value |= op; 15337 // op: Rd 15338 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15339 op &= UINT64_C(15); 15340 op <<= 12; 15341 Value |= op; 15342 // op: Rm 15343 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15344 op &= UINT64_C(15); 15345 Value |= op; 15346 // op: Rn 15347 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15348 op &= UINT64_C(15); 15349 op <<= 16; 15350 Value |= op; 15351 // op: rot 15352 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15353 op &= UINT64_C(3); 15354 op <<= 10; 15355 Value |= op; 15356 break; 15357 } 15358 case ARM::SBFX: 15359 case ARM::UBFX: { 15360 // op: p 15361 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15362 op &= UINT64_C(15); 15363 op <<= 28; 15364 Value |= op; 15365 // op: Rd 15366 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15367 op &= UINT64_C(15); 15368 op <<= 12; 15369 Value |= op; 15370 // op: Rn 15371 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15372 op &= UINT64_C(15); 15373 Value |= op; 15374 // op: lsb 15375 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15376 op &= UINT64_C(31); 15377 op <<= 7; 15378 Value |= op; 15379 // op: width 15380 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15381 op &= UINT64_C(31); 15382 op <<= 16; 15383 Value |= op; 15384 break; 15385 } 15386 case ARM::PKHBT: 15387 case ARM::PKHTB: { 15388 // op: p 15389 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15390 op &= UINT64_C(15); 15391 op <<= 28; 15392 Value |= op; 15393 // op: Rd 15394 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15395 op &= UINT64_C(15); 15396 op <<= 12; 15397 Value |= op; 15398 // op: Rn 15399 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15400 op &= UINT64_C(15); 15401 op <<= 16; 15402 Value |= op; 15403 // op: Rm 15404 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15405 op &= UINT64_C(15); 15406 Value |= op; 15407 // op: sh 15408 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15409 op &= UINT64_C(31); 15410 op <<= 7; 15411 Value |= op; 15412 break; 15413 } 15414 case ARM::BFI: { 15415 // op: p 15416 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15417 op &= UINT64_C(15); 15418 op <<= 28; 15419 Value |= op; 15420 // op: Rd 15421 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15422 op &= UINT64_C(15); 15423 op <<= 12; 15424 Value |= op; 15425 // op: Rn 15426 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15427 op &= UINT64_C(15); 15428 Value |= op; 15429 // op: imm 15430 op = getBitfieldInvertedMaskOpValue(MI, 3, Fixups, STI); 15431 Value |= (op & UINT64_C(992)) << 11; 15432 Value |= (op & UINT64_C(31)) << 7; 15433 break; 15434 } 15435 case ARM::SSAT: 15436 case ARM::USAT: { 15437 // op: p 15438 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15439 op &= UINT64_C(15); 15440 op <<= 28; 15441 Value |= op; 15442 // op: Rd 15443 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15444 op &= UINT64_C(15); 15445 op <<= 12; 15446 Value |= op; 15447 // op: sat_imm 15448 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15449 op &= UINT64_C(31); 15450 op <<= 16; 15451 Value |= op; 15452 // op: Rn 15453 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15454 op &= UINT64_C(15); 15455 Value |= op; 15456 // op: sh 15457 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15458 Value |= (op & UINT64_C(31)) << 7; 15459 Value |= (op & UINT64_C(32)) << 1; 15460 break; 15461 } 15462 case ARM::MLS: { 15463 // op: p 15464 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15465 op &= UINT64_C(15); 15466 op <<= 28; 15467 Value |= op; 15468 // op: Rd 15469 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15470 op &= UINT64_C(15); 15471 op <<= 16; 15472 Value |= op; 15473 // op: Rm 15474 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15475 op &= UINT64_C(15); 15476 op <<= 8; 15477 Value |= op; 15478 // op: Rn 15479 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15480 op &= UINT64_C(15); 15481 Value |= op; 15482 // op: Ra 15483 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15484 op &= UINT64_C(15); 15485 op <<= 12; 15486 Value |= op; 15487 break; 15488 } 15489 case ARM::SMMLA: 15490 case ARM::SMMLAR: 15491 case ARM::SMMLS: 15492 case ARM::SMMLSR: 15493 case ARM::USADA8: { 15494 // op: p 15495 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15496 op &= UINT64_C(15); 15497 op <<= 28; 15498 Value |= op; 15499 // op: Rd 15500 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15501 op &= UINT64_C(15); 15502 op <<= 16; 15503 Value |= op; 15504 // op: Rn 15505 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15506 op &= UINT64_C(15); 15507 Value |= op; 15508 // op: Rm 15509 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15510 op &= UINT64_C(15); 15511 op <<= 8; 15512 Value |= op; 15513 // op: Ra 15514 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15515 op &= UINT64_C(15); 15516 op <<= 12; 15517 Value |= op; 15518 break; 15519 } 15520 case ARM::CMNzrsr: 15521 case ARM::CMPrsr: 15522 case ARM::TEQrsr: 15523 case ARM::TSTrsr: { 15524 // op: p 15525 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15526 op &= UINT64_C(15); 15527 op <<= 28; 15528 Value |= op; 15529 // op: Rn 15530 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15531 op &= UINT64_C(15); 15532 op <<= 16; 15533 Value |= op; 15534 // op: shift 15535 op = getSORegRegOpValue(MI, 1, Fixups, STI); 15536 Value |= (op & UINT64_C(3840)); 15537 Value |= (op & UINT64_C(96)); 15538 Value |= (op & UINT64_C(15)); 15539 break; 15540 } 15541 case ARM::SMLAD: 15542 case ARM::SMLADX: 15543 case ARM::SMLSD: 15544 case ARM::SMLSDX: { 15545 // op: p 15546 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15547 op &= UINT64_C(15); 15548 op <<= 28; 15549 Value |= op; 15550 // op: Rn 15551 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15552 op &= UINT64_C(15); 15553 Value |= op; 15554 // op: Rm 15555 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15556 op &= UINT64_C(15); 15557 op <<= 8; 15558 Value |= op; 15559 // op: Ra 15560 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15561 op &= UINT64_C(15); 15562 op <<= 12; 15563 Value |= op; 15564 // op: Rd 15565 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15566 op &= UINT64_C(15); 15567 op <<= 16; 15568 Value |= op; 15569 break; 15570 } 15571 case ARM::SMLABB: 15572 case ARM::SMLABT: 15573 case ARM::SMLATB: 15574 case ARM::SMLATT: 15575 case ARM::SMLAWB: 15576 case ARM::SMLAWT: { 15577 // op: p 15578 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15579 op &= UINT64_C(15); 15580 op <<= 28; 15581 Value |= op; 15582 // op: Rn 15583 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15584 op &= UINT64_C(15); 15585 Value |= op; 15586 // op: Rm 15587 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15588 op &= UINT64_C(15); 15589 op <<= 8; 15590 Value |= op; 15591 // op: Rd 15592 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15593 op &= UINT64_C(15); 15594 op <<= 16; 15595 Value |= op; 15596 // op: Ra 15597 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15598 op &= UINT64_C(15); 15599 op <<= 12; 15600 Value |= op; 15601 break; 15602 } 15603 case ARM::LDRB_PRE_IMM: 15604 case ARM::LDR_PRE_IMM: { 15605 // op: p 15606 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15607 op &= UINT64_C(15); 15608 op <<= 28; 15609 Value |= op; 15610 // op: Rt 15611 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15612 op &= UINT64_C(15); 15613 op <<= 12; 15614 Value |= op; 15615 // op: addr 15616 op = getAddrModeImm12OpValue(MI, 2, Fixups, STI); 15617 Value |= (op & UINT64_C(4096)) << 11; 15618 Value |= (op & UINT64_C(122880)) << 3; 15619 Value |= (op & UINT64_C(4095)); 15620 break; 15621 } 15622 case ARM::LDRBrs: 15623 case ARM::LDRrs: 15624 case ARM::STRBrs: 15625 case ARM::STRrs: { 15626 // op: p 15627 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15628 op &= UINT64_C(15); 15629 op <<= 28; 15630 Value |= op; 15631 // op: Rt 15632 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15633 op &= UINT64_C(15); 15634 op <<= 12; 15635 Value |= op; 15636 // op: shift 15637 op = getLdStSORegOpValue(MI, 1, Fixups, STI); 15638 Value |= (op & UINT64_C(4096)) << 11; 15639 Value |= (op & UINT64_C(122880)) << 3; 15640 Value |= (op & UINT64_C(4064)); 15641 Value |= (op & UINT64_C(15)); 15642 break; 15643 } 15644 case ARM::STRB_PRE_IMM: 15645 case ARM::STR_PRE_IMM: { 15646 // op: p 15647 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15648 op &= UINT64_C(15); 15649 op <<= 28; 15650 Value |= op; 15651 // op: Rt 15652 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15653 op &= UINT64_C(15); 15654 op <<= 12; 15655 Value |= op; 15656 // op: addr 15657 op = getAddrModeImm12OpValue(MI, 2, Fixups, STI); 15658 Value |= (op & UINT64_C(4096)) << 11; 15659 Value |= (op & UINT64_C(122880)) << 3; 15660 Value |= (op & UINT64_C(4095)); 15661 break; 15662 } 15663 case ARM::VFMAH: 15664 case ARM::VFMAS: 15665 case ARM::VFMSH: 15666 case ARM::VFMSS: 15667 case ARM::VFNMAH: 15668 case ARM::VFNMAS: 15669 case ARM::VFNMSH: 15670 case ARM::VFNMSS: 15671 case ARM::VMLAH: 15672 case ARM::VMLAS: 15673 case ARM::VMLSH: 15674 case ARM::VMLSS: 15675 case ARM::VNMLAH: 15676 case ARM::VNMLAS: 15677 case ARM::VNMLSH: 15678 case ARM::VNMLSS: { 15679 // op: p 15680 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15681 op &= UINT64_C(15); 15682 op <<= 28; 15683 Value |= op; 15684 // op: Sd 15685 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15686 Value |= (op & UINT64_C(1)) << 22; 15687 Value |= (op & UINT64_C(30)) << 11; 15688 // op: Sn 15689 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15690 Value |= (op & UINT64_C(30)) << 15; 15691 Value |= (op & UINT64_C(1)) << 7; 15692 // op: Sm 15693 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15694 Value |= (op & UINT64_C(1)) << 5; 15695 Value |= (op & UINT64_C(30)) >> 1; 15696 Value = VFPThumb2PostEncoder(MI, Value, STI); 15697 break; 15698 } 15699 case ARM::LDRH: 15700 case ARM::LDRSB: 15701 case ARM::LDRSH: 15702 case ARM::STRH: { 15703 // op: p 15704 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15705 op &= UINT64_C(15); 15706 op <<= 28; 15707 Value |= op; 15708 // op: addr 15709 op = getAddrMode3OpValue(MI, 1, Fixups, STI); 15710 Value |= (op & UINT64_C(256)) << 15; 15711 Value |= (op & UINT64_C(8192)) << 9; 15712 Value |= (op & UINT64_C(7680)) << 7; 15713 Value |= (op & UINT64_C(240)) << 4; 15714 Value |= (op & UINT64_C(15)); 15715 // op: Rt 15716 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15717 op &= UINT64_C(15); 15718 op <<= 12; 15719 Value |= op; 15720 break; 15721 } 15722 case ARM::LDCL_OFFSET: 15723 case ARM::LDCL_PRE: 15724 case ARM::LDC_OFFSET: 15725 case ARM::LDC_PRE: 15726 case ARM::STCL_OFFSET: 15727 case ARM::STCL_PRE: 15728 case ARM::STC_OFFSET: 15729 case ARM::STC_PRE: { 15730 // op: p 15731 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15732 op &= UINT64_C(15); 15733 op <<= 28; 15734 Value |= op; 15735 // op: addr 15736 op = getAddrMode5OpValue(MI, 2, Fixups, STI); 15737 Value |= (op & UINT64_C(256)) << 15; 15738 Value |= (op & UINT64_C(7680)) << 7; 15739 Value |= (op & UINT64_C(255)); 15740 // op: cop 15741 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15742 op &= UINT64_C(15); 15743 op <<= 8; 15744 Value |= op; 15745 // op: CRd 15746 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15747 op &= UINT64_C(15); 15748 op <<= 12; 15749 Value |= op; 15750 break; 15751 } 15752 case ARM::LDRHTi: 15753 case ARM::LDRSBTi: 15754 case ARM::LDRSHTi: { 15755 // op: p 15756 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15757 op &= UINT64_C(15); 15758 op <<= 28; 15759 Value |= op; 15760 // op: addr 15761 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15762 op &= UINT64_C(15); 15763 op <<= 16; 15764 Value |= op; 15765 // op: Rt 15766 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15767 op &= UINT64_C(15); 15768 op <<= 12; 15769 Value |= op; 15770 // op: offset 15771 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15772 Value |= (op & UINT64_C(256)) << 15; 15773 Value |= (op & UINT64_C(240)) << 4; 15774 Value |= (op & UINT64_C(15)); 15775 break; 15776 } 15777 case ARM::STRHTi: { 15778 // op: p 15779 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15780 op &= UINT64_C(15); 15781 op <<= 28; 15782 Value |= op; 15783 // op: addr 15784 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15785 op &= UINT64_C(15); 15786 op <<= 16; 15787 Value |= op; 15788 // op: Rt 15789 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15790 op &= UINT64_C(15); 15791 op <<= 12; 15792 Value |= op; 15793 // op: offset 15794 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15795 Value |= (op & UINT64_C(256)) << 15; 15796 Value |= (op & UINT64_C(240)) << 4; 15797 Value |= (op & UINT64_C(15)); 15798 break; 15799 } 15800 case ARM::VLDR_P0_pre: 15801 case ARM::VSTR_P0_pre: { 15802 // op: p 15803 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15804 op &= UINT64_C(15); 15805 op <<= 28; 15806 Value |= op; 15807 // op: addr 15808 op = getT2AddrModeImm7s4OpValue(MI, 2, Fixups, STI); 15809 Value |= (op & UINT64_C(128)) << 16; 15810 Value |= (op & UINT64_C(3840)) << 8; 15811 Value |= (op & UINT64_C(127)); 15812 Value = VFPThumb2PostEncoder(MI, Value, STI); 15813 break; 15814 } 15815 case ARM::VLDR_P0_post: 15816 case ARM::VSTR_P0_post: { 15817 // op: p 15818 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15819 op &= UINT64_C(15); 15820 op <<= 28; 15821 Value |= op; 15822 // op: addr 15823 op = getT2ScaledImmOpValue<7,2>(MI, 3, Fixups, STI); 15824 Value |= (op & UINT64_C(128)) << 16; 15825 Value |= (op & UINT64_C(127)); 15826 // op: Rn 15827 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15828 op &= UINT64_C(15); 15829 op <<= 16; 15830 Value |= op; 15831 Value = VFPThumb2PostEncoder(MI, Value, STI); 15832 break; 15833 } 15834 case ARM::VMOVSRR: { 15835 // op: p 15836 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15837 op &= UINT64_C(15); 15838 op <<= 28; 15839 Value |= op; 15840 // op: dst1 15841 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15842 Value |= (op & UINT64_C(1)) << 5; 15843 Value |= (op & UINT64_C(30)) >> 1; 15844 // op: src1 15845 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15846 op &= UINT64_C(15); 15847 op <<= 12; 15848 Value |= op; 15849 // op: src2 15850 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15851 op &= UINT64_C(15); 15852 op <<= 16; 15853 Value |= op; 15854 Value = VFPThumb2PostEncoder(MI, Value, STI); 15855 break; 15856 } 15857 case ARM::LDCL_POST: 15858 case ARM::LDC_POST: 15859 case ARM::STCL_POST: 15860 case ARM::STC_POST: { 15861 // op: p 15862 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15863 op &= UINT64_C(15); 15864 op <<= 28; 15865 Value |= op; 15866 // op: offset 15867 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15868 Value |= (op & UINT64_C(256)) << 15; 15869 Value |= (op & UINT64_C(255)); 15870 // op: addr 15871 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15872 op &= UINT64_C(15); 15873 op <<= 16; 15874 Value |= op; 15875 // op: cop 15876 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15877 op &= UINT64_C(15); 15878 op <<= 8; 15879 Value |= op; 15880 // op: CRd 15881 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15882 op &= UINT64_C(15); 15883 op <<= 12; 15884 Value |= op; 15885 break; 15886 } 15887 case ARM::LDCL_OPTION: 15888 case ARM::LDC_OPTION: 15889 case ARM::STCL_OPTION: 15890 case ARM::STC_OPTION: { 15891 // op: p 15892 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15893 op &= UINT64_C(15); 15894 op <<= 28; 15895 Value |= op; 15896 // op: option 15897 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15898 op &= UINT64_C(255); 15899 Value |= op; 15900 // op: addr 15901 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15902 op &= UINT64_C(15); 15903 op <<= 16; 15904 Value |= op; 15905 // op: cop 15906 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15907 op &= UINT64_C(15); 15908 op <<= 8; 15909 Value |= op; 15910 // op: CRd 15911 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15912 op &= UINT64_C(15); 15913 op <<= 12; 15914 Value |= op; 15915 break; 15916 } 15917 case ARM::ADCrsi: 15918 case ARM::ADDrsi: 15919 case ARM::ANDrsi: 15920 case ARM::BICrsi: 15921 case ARM::EORrsi: 15922 case ARM::ORRrsi: 15923 case ARM::RSBrsi: 15924 case ARM::RSCrsi: 15925 case ARM::SBCrsi: 15926 case ARM::SUBrsi: { 15927 // op: p 15928 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15929 op &= UINT64_C(15); 15930 op <<= 28; 15931 Value |= op; 15932 // op: s 15933 op = getCCOutOpValue(MI, 6, Fixups, STI); 15934 op &= UINT64_C(1); 15935 op <<= 20; 15936 Value |= op; 15937 // op: Rd 15938 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15939 op &= UINT64_C(15); 15940 op <<= 12; 15941 Value |= op; 15942 // op: Rn 15943 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15944 op &= UINT64_C(15); 15945 op <<= 16; 15946 Value |= op; 15947 // op: shift 15948 op = getSORegImmOpValue(MI, 2, Fixups, STI); 15949 Value |= (op & UINT64_C(4064)); 15950 Value |= (op & UINT64_C(15)); 15951 break; 15952 } 15953 case ARM::MVNsr: { 15954 // op: p 15955 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15956 op &= UINT64_C(15); 15957 op <<= 28; 15958 Value |= op; 15959 // op: s 15960 op = getCCOutOpValue(MI, 6, Fixups, STI); 15961 op &= UINT64_C(1); 15962 op <<= 20; 15963 Value |= op; 15964 // op: Rd 15965 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15966 op &= UINT64_C(15); 15967 op <<= 12; 15968 Value |= op; 15969 // op: shift 15970 op = getSORegRegOpValue(MI, 1, Fixups, STI); 15971 Value |= (op & UINT64_C(3840)); 15972 Value |= (op & UINT64_C(96)); 15973 Value |= (op & UINT64_C(15)); 15974 break; 15975 } 15976 case ARM::MOVsr: { 15977 // op: p 15978 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15979 op &= UINT64_C(15); 15980 op <<= 28; 15981 Value |= op; 15982 // op: s 15983 op = getCCOutOpValue(MI, 6, Fixups, STI); 15984 op &= UINT64_C(1); 15985 op <<= 20; 15986 Value |= op; 15987 // op: Rd 15988 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15989 op &= UINT64_C(15); 15990 op <<= 12; 15991 Value |= op; 15992 // op: src 15993 op = getSORegRegOpValue(MI, 1, Fixups, STI); 15994 Value |= (op & UINT64_C(3840)); 15995 Value |= (op & UINT64_C(96)); 15996 Value |= (op & UINT64_C(15)); 15997 break; 15998 } 15999 case ARM::MLA: { 16000 // op: p 16001 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 16002 op &= UINT64_C(15); 16003 op <<= 28; 16004 Value |= op; 16005 // op: s 16006 op = getCCOutOpValue(MI, 6, Fixups, STI); 16007 op &= UINT64_C(1); 16008 op <<= 20; 16009 Value |= op; 16010 // op: Rd 16011 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16012 op &= UINT64_C(15); 16013 op <<= 16; 16014 Value |= op; 16015 // op: Rm 16016 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16017 op &= UINT64_C(15); 16018 op <<= 8; 16019 Value |= op; 16020 // op: Rn 16021 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16022 op &= UINT64_C(15); 16023 Value |= op; 16024 // op: Ra 16025 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 16026 op &= UINT64_C(15); 16027 op <<= 12; 16028 Value |= op; 16029 break; 16030 } 16031 case ARM::SMULL: 16032 case ARM::UMULL: { 16033 // op: p 16034 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 16035 op &= UINT64_C(15); 16036 op <<= 28; 16037 Value |= op; 16038 // op: s 16039 op = getCCOutOpValue(MI, 6, Fixups, STI); 16040 op &= UINT64_C(1); 16041 op <<= 20; 16042 Value |= op; 16043 // op: RdLo 16044 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16045 op &= UINT64_C(15); 16046 op <<= 12; 16047 Value |= op; 16048 // op: RdHi 16049 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16050 op &= UINT64_C(15); 16051 op <<= 16; 16052 Value |= op; 16053 // op: Rm 16054 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 16055 op &= UINT64_C(15); 16056 op <<= 8; 16057 Value |= op; 16058 // op: Rn 16059 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16060 op &= UINT64_C(15); 16061 Value |= op; 16062 break; 16063 } 16064 case ARM::VMOVRRS: { 16065 // op: p 16066 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 16067 op &= UINT64_C(15); 16068 op <<= 28; 16069 Value |= op; 16070 // op: src1 16071 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16072 Value |= (op & UINT64_C(1)) << 5; 16073 Value |= (op & UINT64_C(30)) >> 1; 16074 // op: Rt 16075 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16076 op &= UINT64_C(15); 16077 op <<= 12; 16078 Value |= op; 16079 // op: Rt2 16080 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16081 op &= UINT64_C(15); 16082 op <<= 16; 16083 Value |= op; 16084 Value = VFPThumb2PostEncoder(MI, Value, STI); 16085 break; 16086 } 16087 case ARM::MRRC: { 16088 // op: p 16089 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 16090 op &= UINT64_C(15); 16091 op <<= 28; 16092 Value |= op; 16093 // op: Rt 16094 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16095 op &= UINT64_C(15); 16096 op <<= 12; 16097 Value |= op; 16098 // op: Rt2 16099 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16100 op &= UINT64_C(15); 16101 op <<= 16; 16102 Value |= op; 16103 // op: cop 16104 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16105 op &= UINT64_C(15); 16106 op <<= 8; 16107 Value |= op; 16108 // op: opc1 16109 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 16110 op &= UINT64_C(15); 16111 op <<= 4; 16112 Value |= op; 16113 // op: CRm 16114 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 16115 op &= UINT64_C(15); 16116 Value |= op; 16117 break; 16118 } 16119 case ARM::LDRH_PRE: 16120 case ARM::LDRSB_PRE: 16121 case ARM::LDRSH_PRE: { 16122 // op: p 16123 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 16124 op &= UINT64_C(15); 16125 op <<= 28; 16126 Value |= op; 16127 // op: Rt 16128 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16129 op &= UINT64_C(15); 16130 op <<= 12; 16131 Value |= op; 16132 // op: addr 16133 op = getAddrMode3OpValue(MI, 2, Fixups, STI); 16134 Value |= (op & UINT64_C(256)) << 15; 16135 Value |= (op & UINT64_C(8192)) << 9; 16136 Value |= (op & UINT64_C(7680)) << 7; 16137 Value |= (op & UINT64_C(240)) << 4; 16138 Value |= (op & UINT64_C(15)); 16139 break; 16140 } 16141 case ARM::LDRB_PRE_REG: 16142 case ARM::LDR_PRE_REG: { 16143 // op: p 16144 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 16145 op &= UINT64_C(15); 16146 op <<= 28; 16147 Value |= op; 16148 // op: Rt 16149 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16150 op &= UINT64_C(15); 16151 op <<= 12; 16152 Value |= op; 16153 // op: addr 16154 op = getLdStSORegOpValue(MI, 2, Fixups, STI); 16155 Value |= (op & UINT64_C(4096)) << 11; 16156 Value |= (op & UINT64_C(122880)) << 3; 16157 Value |= (op & UINT64_C(4064)); 16158 Value |= (op & UINT64_C(15)); 16159 break; 16160 } 16161 case ARM::LDRBT_POST_REG: 16162 case ARM::LDRB_POST_REG: 16163 case ARM::LDRT_POST_REG: 16164 case ARM::LDR_POST_REG: { 16165 // op: p 16166 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 16167 op &= UINT64_C(15); 16168 op <<= 28; 16169 Value |= op; 16170 // op: Rt 16171 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16172 op &= UINT64_C(15); 16173 op <<= 12; 16174 Value |= op; 16175 // op: offset 16176 op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI); 16177 Value |= (op & UINT64_C(4096)) << 11; 16178 Value |= (op & UINT64_C(4064)); 16179 Value |= (op & UINT64_C(15)); 16180 // op: addr 16181 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16182 op &= UINT64_C(15); 16183 op <<= 16; 16184 Value |= op; 16185 break; 16186 } 16187 case ARM::LDRBT_POST_IMM: 16188 case ARM::LDRB_POST_IMM: 16189 case ARM::LDRT_POST_IMM: 16190 case ARM::LDR_POST_IMM: { 16191 // op: p 16192 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 16193 op &= UINT64_C(15); 16194 op <<= 28; 16195 Value |= op; 16196 // op: Rt 16197 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16198 op &= UINT64_C(15); 16199 op <<= 12; 16200 Value |= op; 16201 // op: offset 16202 op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI); 16203 Value |= (op & UINT64_C(4096)) << 11; 16204 Value |= (op & UINT64_C(4095)); 16205 // op: addr 16206 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16207 op &= UINT64_C(15); 16208 op <<= 16; 16209 Value |= op; 16210 break; 16211 } 16212 case ARM::LDRH_POST: 16213 case ARM::LDRSB_POST: 16214 case ARM::LDRSH_POST: { 16215 // op: p 16216 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 16217 op &= UINT64_C(15); 16218 op <<= 28; 16219 Value |= op; 16220 // op: Rt 16221 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16222 op &= UINT64_C(15); 16223 op <<= 12; 16224 Value |= op; 16225 // op: offset 16226 op = getAddrMode3OffsetOpValue(MI, 3, Fixups, STI); 16227 Value |= (op & UINT64_C(256)) << 15; 16228 Value |= (op & UINT64_C(512)) << 13; 16229 Value |= (op & UINT64_C(240)) << 4; 16230 Value |= (op & UINT64_C(15)); 16231 // op: addr 16232 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16233 op &= UINT64_C(15); 16234 op <<= 16; 16235 Value |= op; 16236 break; 16237 } 16238 case ARM::STRH_PRE: { 16239 // op: p 16240 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 16241 op &= UINT64_C(15); 16242 op <<= 28; 16243 Value |= op; 16244 // op: Rt 16245 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16246 op &= UINT64_C(15); 16247 op <<= 12; 16248 Value |= op; 16249 // op: addr 16250 op = getAddrMode3OpValue(MI, 2, Fixups, STI); 16251 Value |= (op & UINT64_C(256)) << 15; 16252 Value |= (op & UINT64_C(8192)) << 9; 16253 Value |= (op & UINT64_C(7680)) << 7; 16254 Value |= (op & UINT64_C(240)) << 4; 16255 Value |= (op & UINT64_C(15)); 16256 break; 16257 } 16258 case ARM::STRB_PRE_REG: 16259 case ARM::STR_PRE_REG: { 16260 // op: p 16261 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 16262 op &= UINT64_C(15); 16263 op <<= 28; 16264 Value |= op; 16265 // op: Rt 16266 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16267 op &= UINT64_C(15); 16268 op <<= 12; 16269 Value |= op; 16270 // op: addr 16271 op = getLdStSORegOpValue(MI, 2, Fixups, STI); 16272 Value |= (op & UINT64_C(4096)) << 11; 16273 Value |= (op & UINT64_C(122880)) << 3; 16274 Value |= (op & UINT64_C(4064)); 16275 Value |= (op & UINT64_C(15)); 16276 break; 16277 } 16278 case ARM::STRBT_POST_REG: 16279 case ARM::STRB_POST_REG: 16280 case ARM::STRT_POST_REG: 16281 case ARM::STR_POST_REG: { 16282 // op: p 16283 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 16284 op &= UINT64_C(15); 16285 op <<= 28; 16286 Value |= op; 16287 // op: Rt 16288 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16289 op &= UINT64_C(15); 16290 op <<= 12; 16291 Value |= op; 16292 // op: offset 16293 op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI); 16294 Value |= (op & UINT64_C(4096)) << 11; 16295 Value |= (op & UINT64_C(4064)); 16296 Value |= (op & UINT64_C(15)); 16297 // op: addr 16298 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16299 op &= UINT64_C(15); 16300 op <<= 16; 16301 Value |= op; 16302 break; 16303 } 16304 case ARM::STRBT_POST_IMM: 16305 case ARM::STRB_POST_IMM: 16306 case ARM::STRT_POST_IMM: 16307 case ARM::STR_POST_IMM: { 16308 // op: p 16309 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 16310 op &= UINT64_C(15); 16311 op <<= 28; 16312 Value |= op; 16313 // op: Rt 16314 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16315 op &= UINT64_C(15); 16316 op <<= 12; 16317 Value |= op; 16318 // op: offset 16319 op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI); 16320 Value |= (op & UINT64_C(4096)) << 11; 16321 Value |= (op & UINT64_C(4095)); 16322 // op: addr 16323 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16324 op &= UINT64_C(15); 16325 op <<= 16; 16326 Value |= op; 16327 break; 16328 } 16329 case ARM::STRH_POST: { 16330 // op: p 16331 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 16332 op &= UINT64_C(15); 16333 op <<= 28; 16334 Value |= op; 16335 // op: Rt 16336 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16337 op &= UINT64_C(15); 16338 op <<= 12; 16339 Value |= op; 16340 // op: offset 16341 op = getAddrMode3OffsetOpValue(MI, 3, Fixups, STI); 16342 Value |= (op & UINT64_C(256)) << 15; 16343 Value |= (op & UINT64_C(512)) << 13; 16344 Value |= (op & UINT64_C(240)) << 4; 16345 Value |= (op & UINT64_C(15)); 16346 // op: addr 16347 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16348 op &= UINT64_C(15); 16349 op <<= 16; 16350 Value |= op; 16351 break; 16352 } 16353 case ARM::MCRR: { 16354 // op: p 16355 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 16356 op &= UINT64_C(15); 16357 op <<= 28; 16358 Value |= op; 16359 // op: Rt 16360 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16361 op &= UINT64_C(15); 16362 op <<= 12; 16363 Value |= op; 16364 // op: Rt2 16365 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 16366 op &= UINT64_C(15); 16367 op <<= 16; 16368 Value |= op; 16369 // op: cop 16370 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16371 op &= UINT64_C(15); 16372 op <<= 8; 16373 Value |= op; 16374 // op: opc1 16375 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16376 op &= UINT64_C(15); 16377 op <<= 4; 16378 Value |= op; 16379 // op: CRm 16380 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 16381 op &= UINT64_C(15); 16382 Value |= op; 16383 break; 16384 } 16385 case ARM::LDRD: 16386 case ARM::STRD: { 16387 // op: p 16388 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 16389 op &= UINT64_C(15); 16390 op <<= 28; 16391 Value |= op; 16392 // op: addr 16393 op = getAddrMode3OpValue(MI, 2, Fixups, STI); 16394 Value |= (op & UINT64_C(256)) << 15; 16395 Value |= (op & UINT64_C(8192)) << 9; 16396 Value |= (op & UINT64_C(7680)) << 7; 16397 Value |= (op & UINT64_C(240)) << 4; 16398 Value |= (op & UINT64_C(15)); 16399 // op: Rt 16400 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16401 op &= UINT64_C(15); 16402 op <<= 12; 16403 Value |= op; 16404 break; 16405 } 16406 case ARM::LDRHTr: 16407 case ARM::LDRSBTr: 16408 case ARM::LDRSHTr: { 16409 // op: p 16410 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 16411 op &= UINT64_C(15); 16412 op <<= 28; 16413 Value |= op; 16414 // op: addr 16415 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16416 op &= UINT64_C(15); 16417 op <<= 16; 16418 Value |= op; 16419 // op: Rt 16420 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16421 op &= UINT64_C(15); 16422 op <<= 12; 16423 Value |= op; 16424 // op: Rm 16425 op = getPostIdxRegOpValue(MI, 3, Fixups, STI); 16426 Value |= (op & UINT64_C(16)) << 19; 16427 Value |= (op & UINT64_C(15)); 16428 break; 16429 } 16430 case ARM::STRHTr: { 16431 // op: p 16432 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 16433 op &= UINT64_C(15); 16434 op <<= 28; 16435 Value |= op; 16436 // op: addr 16437 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16438 op &= UINT64_C(15); 16439 op <<= 16; 16440 Value |= op; 16441 // op: Rt 16442 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16443 op &= UINT64_C(15); 16444 op <<= 12; 16445 Value |= op; 16446 // op: Rm 16447 op = getPostIdxRegOpValue(MI, 3, Fixups, STI); 16448 Value |= (op & UINT64_C(16)) << 19; 16449 Value |= (op & UINT64_C(15)); 16450 break; 16451 } 16452 case ARM::ADCrsr: 16453 case ARM::ADDrsr: 16454 case ARM::ANDrsr: 16455 case ARM::BICrsr: 16456 case ARM::EORrsr: 16457 case ARM::ORRrsr: 16458 case ARM::RSBrsr: 16459 case ARM::RSCrsr: 16460 case ARM::SBCrsr: 16461 case ARM::SUBrsr: { 16462 // op: p 16463 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 16464 op &= UINT64_C(15); 16465 op <<= 28; 16466 Value |= op; 16467 // op: s 16468 op = getCCOutOpValue(MI, 7, Fixups, STI); 16469 op &= UINT64_C(1); 16470 op <<= 20; 16471 Value |= op; 16472 // op: Rd 16473 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16474 op &= UINT64_C(15); 16475 op <<= 12; 16476 Value |= op; 16477 // op: Rn 16478 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16479 op &= UINT64_C(15); 16480 op <<= 16; 16481 Value |= op; 16482 // op: shift 16483 op = getSORegRegOpValue(MI, 2, Fixups, STI); 16484 Value |= (op & UINT64_C(3840)); 16485 Value |= (op & UINT64_C(96)); 16486 Value |= (op & UINT64_C(15)); 16487 break; 16488 } 16489 case ARM::UMAAL: { 16490 // op: p 16491 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 16492 op &= UINT64_C(15); 16493 op <<= 28; 16494 Value |= op; 16495 // op: RdLo 16496 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16497 op &= UINT64_C(15); 16498 op <<= 12; 16499 Value |= op; 16500 // op: RdHi 16501 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16502 op &= UINT64_C(15); 16503 op <<= 16; 16504 Value |= op; 16505 // op: Rm 16506 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 16507 op &= UINT64_C(15); 16508 op <<= 8; 16509 Value |= op; 16510 // op: Rn 16511 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16512 op &= UINT64_C(15); 16513 Value |= op; 16514 break; 16515 } 16516 case ARM::SMLALBB: 16517 case ARM::SMLALBT: 16518 case ARM::SMLALD: 16519 case ARM::SMLALDX: 16520 case ARM::SMLALTB: 16521 case ARM::SMLALTT: 16522 case ARM::SMLSLD: 16523 case ARM::SMLSLDX: { 16524 // op: p 16525 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 16526 op &= UINT64_C(15); 16527 op <<= 28; 16528 Value |= op; 16529 // op: Rn 16530 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16531 op &= UINT64_C(15); 16532 Value |= op; 16533 // op: Rm 16534 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 16535 op &= UINT64_C(15); 16536 op <<= 8; 16537 Value |= op; 16538 // op: RdLo 16539 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16540 op &= UINT64_C(15); 16541 op <<= 12; 16542 Value |= op; 16543 // op: RdHi 16544 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16545 op &= UINT64_C(15); 16546 op <<= 16; 16547 Value |= op; 16548 break; 16549 } 16550 case ARM::LDRD_PRE: { 16551 // op: p 16552 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 16553 op &= UINT64_C(15); 16554 op <<= 28; 16555 Value |= op; 16556 // op: Rt 16557 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16558 op &= UINT64_C(15); 16559 op <<= 12; 16560 Value |= op; 16561 // op: addr 16562 op = getAddrMode3OpValue(MI, 3, Fixups, STI); 16563 Value |= (op & UINT64_C(256)) << 15; 16564 Value |= (op & UINT64_C(8192)) << 9; 16565 Value |= (op & UINT64_C(7680)) << 7; 16566 Value |= (op & UINT64_C(240)) << 4; 16567 Value |= (op & UINT64_C(15)); 16568 break; 16569 } 16570 case ARM::MRC: { 16571 // op: p 16572 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 16573 op &= UINT64_C(15); 16574 op <<= 28; 16575 Value |= op; 16576 // op: Rt 16577 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16578 op &= UINT64_C(15); 16579 op <<= 12; 16580 Value |= op; 16581 // op: cop 16582 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16583 op &= UINT64_C(15); 16584 op <<= 8; 16585 Value |= op; 16586 // op: opc1 16587 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16588 op &= UINT64_C(7); 16589 op <<= 21; 16590 Value |= op; 16591 // op: opc2 16592 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 16593 op &= UINT64_C(7); 16594 op <<= 5; 16595 Value |= op; 16596 // op: CRm 16597 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 16598 op &= UINT64_C(15); 16599 Value |= op; 16600 // op: CRn 16601 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 16602 op &= UINT64_C(15); 16603 op <<= 16; 16604 Value |= op; 16605 break; 16606 } 16607 case ARM::LDRD_POST: { 16608 // op: p 16609 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 16610 op &= UINT64_C(15); 16611 op <<= 28; 16612 Value |= op; 16613 // op: Rt 16614 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16615 op &= UINT64_C(15); 16616 op <<= 12; 16617 Value |= op; 16618 // op: offset 16619 op = getAddrMode3OffsetOpValue(MI, 4, Fixups, STI); 16620 Value |= (op & UINT64_C(256)) << 15; 16621 Value |= (op & UINT64_C(512)) << 13; 16622 Value |= (op & UINT64_C(240)) << 4; 16623 Value |= (op & UINT64_C(15)); 16624 // op: addr 16625 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 16626 op &= UINT64_C(15); 16627 op <<= 16; 16628 Value |= op; 16629 break; 16630 } 16631 case ARM::STRD_PRE: { 16632 // op: p 16633 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 16634 op &= UINT64_C(15); 16635 op <<= 28; 16636 Value |= op; 16637 // op: Rt 16638 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16639 op &= UINT64_C(15); 16640 op <<= 12; 16641 Value |= op; 16642 // op: addr 16643 op = getAddrMode3OpValue(MI, 3, Fixups, STI); 16644 Value |= (op & UINT64_C(256)) << 15; 16645 Value |= (op & UINT64_C(8192)) << 9; 16646 Value |= (op & UINT64_C(7680)) << 7; 16647 Value |= (op & UINT64_C(240)) << 4; 16648 Value |= (op & UINT64_C(15)); 16649 break; 16650 } 16651 case ARM::STRD_POST: { 16652 // op: p 16653 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 16654 op &= UINT64_C(15); 16655 op <<= 28; 16656 Value |= op; 16657 // op: Rt 16658 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16659 op &= UINT64_C(15); 16660 op <<= 12; 16661 Value |= op; 16662 // op: offset 16663 op = getAddrMode3OffsetOpValue(MI, 4, Fixups, STI); 16664 Value |= (op & UINT64_C(256)) << 15; 16665 Value |= (op & UINT64_C(512)) << 13; 16666 Value |= (op & UINT64_C(240)) << 4; 16667 Value |= (op & UINT64_C(15)); 16668 // op: addr 16669 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 16670 op &= UINT64_C(15); 16671 op <<= 16; 16672 Value |= op; 16673 break; 16674 } 16675 case ARM::MCR: { 16676 // op: p 16677 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 16678 op &= UINT64_C(15); 16679 op <<= 28; 16680 Value |= op; 16681 // op: Rt 16682 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16683 op &= UINT64_C(15); 16684 op <<= 12; 16685 Value |= op; 16686 // op: cop 16687 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16688 op &= UINT64_C(15); 16689 op <<= 8; 16690 Value |= op; 16691 // op: opc1 16692 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16693 op &= UINT64_C(7); 16694 op <<= 21; 16695 Value |= op; 16696 // op: opc2 16697 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 16698 op &= UINT64_C(7); 16699 op <<= 5; 16700 Value |= op; 16701 // op: CRm 16702 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 16703 op &= UINT64_C(15); 16704 Value |= op; 16705 // op: CRn 16706 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 16707 op &= UINT64_C(15); 16708 op <<= 16; 16709 Value |= op; 16710 break; 16711 } 16712 case ARM::CDP: { 16713 // op: p 16714 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 16715 op &= UINT64_C(15); 16716 op <<= 28; 16717 Value |= op; 16718 // op: opc1 16719 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16720 op &= UINT64_C(15); 16721 op <<= 20; 16722 Value |= op; 16723 // op: CRn 16724 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 16725 op &= UINT64_C(15); 16726 op <<= 16; 16727 Value |= op; 16728 // op: CRd 16729 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16730 op &= UINT64_C(15); 16731 op <<= 12; 16732 Value |= op; 16733 // op: cop 16734 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16735 op &= UINT64_C(15); 16736 op <<= 8; 16737 Value |= op; 16738 // op: opc2 16739 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 16740 op &= UINT64_C(7); 16741 op <<= 5; 16742 Value |= op; 16743 // op: CRm 16744 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 16745 op &= UINT64_C(15); 16746 Value |= op; 16747 break; 16748 } 16749 case ARM::SMLAL: 16750 case ARM::UMLAL: { 16751 // op: p 16752 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 16753 op &= UINT64_C(15); 16754 op <<= 28; 16755 Value |= op; 16756 // op: s 16757 op = getCCOutOpValue(MI, 8, Fixups, STI); 16758 op &= UINT64_C(1); 16759 op <<= 20; 16760 Value |= op; 16761 // op: RdLo 16762 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16763 op &= UINT64_C(15); 16764 op <<= 12; 16765 Value |= op; 16766 // op: RdHi 16767 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16768 op &= UINT64_C(15); 16769 op <<= 16; 16770 Value |= op; 16771 // op: Rm 16772 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 16773 op &= UINT64_C(15); 16774 op <<= 8; 16775 Value |= op; 16776 // op: Rn 16777 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16778 op &= UINT64_C(15); 16779 Value |= op; 16780 break; 16781 } 16782 case ARM::tPUSH: { 16783 // op: regs 16784 op = getRegisterListOpValue(MI, 2, Fixups, STI); 16785 Value |= (op & UINT64_C(16384)) >> 6; 16786 Value |= (op & UINT64_C(255)); 16787 break; 16788 } 16789 case ARM::VSCCLRMS: { 16790 // op: regs 16791 op = getRegisterListOpValue(MI, 2, Fixups, STI); 16792 Value |= (op & UINT64_C(256)) << 14; 16793 Value |= (op & UINT64_C(7680)) << 3; 16794 Value |= (op & UINT64_C(255)); 16795 Value = VFPThumb2PostEncoder(MI, Value, STI); 16796 break; 16797 } 16798 case ARM::tPOP: { 16799 // op: regs 16800 op = getRegisterListOpValue(MI, 2, Fixups, STI); 16801 Value |= (op & UINT64_C(32768)) >> 7; 16802 Value |= (op & UINT64_C(255)); 16803 break; 16804 } 16805 case ARM::VSCCLRMD: { 16806 // op: regs 16807 op = getRegisterListOpValue(MI, 2, Fixups, STI); 16808 Value |= (op & UINT64_C(4096)) << 10; 16809 Value |= (op & UINT64_C(3840)) << 4; 16810 Value |= (op & UINT64_C(254)); 16811 Value = VFPThumb2PostEncoder(MI, Value, STI); 16812 break; 16813 } 16814 case ARM::t2CLRM: { 16815 // op: regs 16816 op = getRegisterListOpValue(MI, 2, Fixups, STI); 16817 Value |= (op & UINT64_C(49152)); 16818 Value |= (op & UINT64_C(8191)); 16819 break; 16820 } 16821 case ARM::t2MOVr: 16822 case ARM::t2MVNr: 16823 case ARM::t2RRX: { 16824 // op: s 16825 op = getCCOutOpValue(MI, 4, Fixups, STI); 16826 op &= UINT64_C(1); 16827 op <<= 20; 16828 Value |= op; 16829 // op: Rd 16830 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16831 op &= UINT64_C(15); 16832 op <<= 8; 16833 Value |= op; 16834 // op: Rm 16835 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16836 op &= UINT64_C(15); 16837 Value |= op; 16838 break; 16839 } 16840 case ARM::t2MOVi: 16841 case ARM::t2MVNi: { 16842 // op: s 16843 op = getCCOutOpValue(MI, 4, Fixups, STI); 16844 op &= UINT64_C(1); 16845 op <<= 20; 16846 Value |= op; 16847 // op: Rd 16848 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16849 op &= UINT64_C(15); 16850 op <<= 8; 16851 Value |= op; 16852 // op: imm 16853 op = getT2SOImmOpValue(MI, 1, Fixups, STI); 16854 Value |= (op & UINT64_C(2048)) << 15; 16855 Value |= (op & UINT64_C(1792)) << 4; 16856 Value |= (op & UINT64_C(255)); 16857 break; 16858 } 16859 case ARM::t2ASRri: 16860 case ARM::t2LSLri: 16861 case ARM::t2LSRri: 16862 case ARM::t2RORri: { 16863 // op: s 16864 op = getCCOutOpValue(MI, 5, Fixups, STI); 16865 op &= UINT64_C(1); 16866 op <<= 20; 16867 Value |= op; 16868 // op: Rd 16869 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16870 op &= UINT64_C(15); 16871 op <<= 8; 16872 Value |= op; 16873 // op: Rm 16874 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16875 op &= UINT64_C(15); 16876 Value |= op; 16877 // op: imm 16878 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16879 Value |= (op & UINT64_C(28)) << 10; 16880 Value |= (op & UINT64_C(3)) << 6; 16881 break; 16882 } 16883 case ARM::t2ADCrr: 16884 case ARM::t2ADDrr: 16885 case ARM::t2ANDrr: 16886 case ARM::t2ASRrr: 16887 case ARM::t2BICrr: 16888 case ARM::t2EORrr: 16889 case ARM::t2LSLrr: 16890 case ARM::t2LSRrr: 16891 case ARM::t2ORNrr: 16892 case ARM::t2ORRrr: 16893 case ARM::t2RORrr: 16894 case ARM::t2RSBrr: 16895 case ARM::t2SBCrr: 16896 case ARM::t2SUBrr: { 16897 // op: s 16898 op = getCCOutOpValue(MI, 5, Fixups, STI); 16899 op &= UINT64_C(1); 16900 op <<= 20; 16901 Value |= op; 16902 // op: Rd 16903 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16904 op &= UINT64_C(15); 16905 op <<= 8; 16906 Value |= op; 16907 // op: Rn 16908 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16909 op &= UINT64_C(15); 16910 op <<= 16; 16911 Value |= op; 16912 // op: Rm 16913 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16914 op &= UINT64_C(15); 16915 Value |= op; 16916 break; 16917 } 16918 case ARM::t2ADCri: 16919 case ARM::t2ADDri: 16920 case ARM::t2ANDri: 16921 case ARM::t2BICri: 16922 case ARM::t2EORri: 16923 case ARM::t2ORNri: 16924 case ARM::t2ORRri: 16925 case ARM::t2RSBri: 16926 case ARM::t2SBCri: 16927 case ARM::t2SUBri: { 16928 // op: s 16929 op = getCCOutOpValue(MI, 5, Fixups, STI); 16930 op &= UINT64_C(1); 16931 op <<= 20; 16932 Value |= op; 16933 // op: Rd 16934 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16935 op &= UINT64_C(15); 16936 op <<= 8; 16937 Value |= op; 16938 // op: Rn 16939 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16940 op &= UINT64_C(15); 16941 op <<= 16; 16942 Value |= op; 16943 // op: imm 16944 op = getT2SOImmOpValue(MI, 2, Fixups, STI); 16945 Value |= (op & UINT64_C(2048)) << 15; 16946 Value |= (op & UINT64_C(1792)) << 4; 16947 Value |= (op & UINT64_C(255)); 16948 break; 16949 } 16950 case ARM::t2MVNs: { 16951 // op: s 16952 op = getCCOutOpValue(MI, 5, Fixups, STI); 16953 op &= UINT64_C(1); 16954 op <<= 20; 16955 Value |= op; 16956 // op: Rd 16957 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16958 op &= UINT64_C(15); 16959 op <<= 8; 16960 Value |= op; 16961 // op: ShiftedRm 16962 op = getT2SORegOpValue(MI, 1, Fixups, STI); 16963 Value |= (op & UINT64_C(3584)) << 3; 16964 Value |= (op & UINT64_C(480)) >> 1; 16965 Value |= (op & UINT64_C(15)); 16966 break; 16967 } 16968 case ARM::t2ADDspImm: 16969 case ARM::t2SUBspImm: { 16970 // op: s 16971 op = getCCOutOpValue(MI, 5, Fixups, STI); 16972 op &= UINT64_C(1); 16973 op <<= 20; 16974 Value |= op; 16975 // op: imm 16976 op = getT2SOImmOpValue(MI, 2, Fixups, STI); 16977 Value |= (op & UINT64_C(2048)) << 15; 16978 Value |= (op & UINT64_C(1792)) << 4; 16979 Value |= (op & UINT64_C(255)); 16980 break; 16981 } 16982 case ARM::t2ADCrs: 16983 case ARM::t2ADDrs: 16984 case ARM::t2ANDrs: 16985 case ARM::t2BICrs: 16986 case ARM::t2EORrs: 16987 case ARM::t2ORNrs: 16988 case ARM::t2ORRrs: 16989 case ARM::t2RSBrs: 16990 case ARM::t2SBCrs: 16991 case ARM::t2SUBrs: { 16992 // op: s 16993 op = getCCOutOpValue(MI, 6, Fixups, STI); 16994 op &= UINT64_C(1); 16995 op <<= 20; 16996 Value |= op; 16997 // op: Rd 16998 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16999 op &= UINT64_C(15); 17000 op <<= 8; 17001 Value |= op; 17002 // op: Rn 17003 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 17004 op &= UINT64_C(15); 17005 op <<= 16; 17006 Value |= op; 17007 // op: ShiftedRm 17008 op = getT2SORegOpValue(MI, 2, Fixups, STI); 17009 Value |= (op & UINT64_C(3584)) << 3; 17010 Value |= (op & UINT64_C(480)) >> 1; 17011 Value |= (op & UINT64_C(15)); 17012 break; 17013 } 17014 case ARM::PLDWrs: 17015 case ARM::PLDrs: 17016 case ARM::PLIrs: { 17017 // op: shift 17018 op = getLdStSORegOpValue(MI, 0, Fixups, STI); 17019 Value |= (op & UINT64_C(4096)) << 11; 17020 Value |= (op & UINT64_C(122880)) << 3; 17021 Value |= (op & UINT64_C(4064)); 17022 Value |= (op & UINT64_C(15)); 17023 break; 17024 } 17025 case ARM::BLXi: { 17026 // op: target 17027 op = getARMBLXTargetOpValue(MI, 0, Fixups, STI); 17028 Value |= (op & UINT64_C(1)) << 24; 17029 Value |= (op & UINT64_C(33554430)) >> 1; 17030 break; 17031 } 17032 case ARM::tB: { 17033 // op: target 17034 op = getThumbBRTargetOpValue(MI, 0, Fixups, STI); 17035 op &= UINT64_C(2047); 17036 Value |= op; 17037 break; 17038 } 17039 case ARM::t2B: { 17040 // op: target 17041 op = getThumbBranchTargetOpValue(MI, 0, Fixups, STI); 17042 Value |= (op & UINT64_C(8388608)) << 3; 17043 Value |= (op & UINT64_C(2095104)) << 5; 17044 Value |= (op & UINT64_C(4194304)) >> 9; 17045 Value |= (op & UINT64_C(2097152)) >> 10; 17046 Value |= (op & UINT64_C(2047)); 17047 break; 17048 } 17049 case ARM::tCBNZ: 17050 case ARM::tCBZ: { 17051 // op: target 17052 op = getThumbCBTargetOpValue(MI, 1, Fixups, STI); 17053 Value |= (op & UINT64_C(32)) << 4; 17054 Value |= (op & UINT64_C(31)) << 3; 17055 // op: Rn 17056 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 17057 op &= UINT64_C(7); 17058 Value |= op; 17059 break; 17060 } 17061 case ARM::BKPT: 17062 case ARM::HLT: { 17063 // op: val 17064 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 17065 Value |= (op & UINT64_C(65520)) << 4; 17066 Value |= (op & UINT64_C(15)); 17067 break; 17068 } 17069 case ARM::tBKPT: { 17070 // op: val 17071 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 17072 op &= UINT64_C(255); 17073 Value |= op; 17074 break; 17075 } 17076 case ARM::tHLT: { 17077 // op: val 17078 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 17079 op &= UINT64_C(63); 17080 Value |= op; 17081 break; 17082 } 17083 default: 17084 std::string msg; 17085 raw_string_ostream Msg(msg); 17086 Msg << "Not supported instr: " << MI; 17087 report_fatal_error(Msg.str().c_str()); 17088 } 17089 return Value; 17090} 17091 17092