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1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|* Register Bank Source Fragments                                             *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11namespace llvm {
12namespace ARM {
13enum : unsigned {
14  InvalidRegBankID = ~0u,
15  FPRRegBankID = 0,
16  GPRRegBankID = 1,
17  NumRegisterBanks,
18};
19} // end namespace ARM
20} // end namespace llvm
21#endif // GET_REGBANK_DECLARATIONS
22
23#ifdef GET_TARGET_REGBANK_CLASS
24#undef GET_TARGET_REGBANK_CLASS
25private:
26  static RegisterBank *RegBanks[];
27
28protected:
29  ARMGenRegisterBankInfo();
30
31#endif // GET_TARGET_REGBANK_CLASS
32
33#ifdef GET_TARGET_REGBANK_IMPL
34#undef GET_TARGET_REGBANK_IMPL
35namespace llvm {
36namespace ARM {
37const uint32_t FPRRegBankCoverageData[] = {
38    // 0-31
39    (1u << (ARM::HPRRegClassID - 0)) |
40    (1u << (ARM::SPRRegClassID - 0)) |
41    (1u << (ARM::SPR_8RegClassID - 0)) |
42    (1u << (ARM::FPWithVPRRegClassID - 0)) |
43    (1u << (ARM::FPWithVPR_with_ssub_0RegClassID - 0)) |
44    (1u << (ARM::FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID - 0)) |
45    0,
46    // 32-63
47    (1u << (ARM::DPRRegClassID - 32)) |
48    (1u << (ARM::DPR_VFP2RegClassID - 32)) |
49    (1u << (ARM::DPR_8RegClassID - 32)) |
50    0,
51    // 64-95
52    (1u << (ARM::QPRRegClassID - 64)) |
53    (1u << (ARM::MQPRRegClassID - 64)) |
54    (1u << (ARM::QPR_VFP2RegClassID - 64)) |
55    (1u << (ARM::QPR_8RegClassID - 64)) |
56    0,
57    // 96-127
58    0,
59    // 128-159
60    0,
61};
62const uint32_t GPRRegBankCoverageData[] = {
63    // 0-31
64    (1u << (ARM::GPRRegClassID - 0)) |
65    (1u << (ARM::GPRnopcRegClassID - 0)) |
66    (1u << (ARM::rGPRRegClassID - 0)) |
67    (1u << (ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID - 0)) |
68    (1u << (ARM::tGPRRegClassID - 0)) |
69    (1u << (ARM::GPRnoip_and_tGPREvenRegClassID - 0)) |
70    (1u << (ARM::tGPROddRegClassID - 0)) |
71    (1u << (ARM::tGPREvenRegClassID - 0)) |
72    (1u << (ARM::GPRnosp_and_GPRnopc_and_hGPRRegClassID - 0)) |
73    (1u << (ARM::tcGPRRegClassID - 0)) |
74    (1u << (ARM::GPRnoip_and_GPRnopcRegClassID - 0)) |
75    (1u << (ARM::GPRnopc_and_GPRnoip_and_hGPRRegClassID - 0)) |
76    (1u << (ARM::GPRnopc_and_hGPRRegClassID - 0)) |
77    (1u << (ARM::GPRnospRegClassID - 0)) |
78    (1u << (ARM::GPRnoip_and_GPRnospRegClassID - 0)) |
79    (1u << (ARM::tGPRwithpcRegClassID - 0)) |
80    (1u << (ARM::GPRnosp_and_GPRnoip_and_hGPRRegClassID - 0)) |
81    (1u << (ARM::GPRnosp_and_hGPRRegClassID - 0)) |
82    (1u << (ARM::GPRnoipRegClassID - 0)) |
83    (1u << (ARM::GPRnoip_and_hGPRRegClassID - 0)) |
84    (1u << (ARM::hGPRRegClassID - 0)) |
85    (1u << (ARM::GPRwithAPSRRegClassID - 0)) |
86    (1u << (ARM::GPRwithAPSR_NZCVnospRegClassID - 0)) |
87    0,
88    // 32-63
89    (1u << (ARM::GPRnoip_and_tcGPRRegClassID - 32)) |
90    (1u << (ARM::tGPREven_and_GPRnoip_and_tcGPRRegClassID - 32)) |
91    (1u << (ARM::tGPROdd_and_tcGPRRegClassID - 32)) |
92    (1u << (ARM::tGPR_and_tGPREvenRegClassID - 32)) |
93    (1u << (ARM::tGPR_and_tGPROddRegClassID - 32)) |
94    (1u << (ARM::hGPR_and_GPRnoip_and_tGPREvenRegClassID - 32)) |
95    (1u << (ARM::hGPR_and_tGPROddRegClassID - 32)) |
96    (1u << (ARM::GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRRegClassID - 32)) |
97    (1u << (ARM::hGPR_and_tGPREvenRegClassID - 32)) |
98    (1u << (ARM::GPRlrRegClassID - 32)) |
99    (1u << (ARM::hGPR_and_tcGPRRegClassID - 32)) |
100    (1u << (ARM::tGPREven_and_tcGPRRegClassID - 32)) |
101    (1u << (ARM::GPRspRegClassID - 32)) |
102    (1u << (ARM::hGPR_and_tGPRwithpcRegClassID - 32)) |
103    0,
104    // 64-95
105    0,
106    // 96-127
107    0,
108    // 128-159
109    0,
110};
111
112RegisterBank FPRRegBank(/* ID */ ARM::FPRRegBankID, /* Name */ "FPRB", /* Size */ 128, /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 136);
113RegisterBank GPRRegBank(/* ID */ ARM::GPRRegBankID, /* Name */ "GPRB", /* Size */ 32, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 136);
114} // end namespace ARM
115
116RegisterBank *ARMGenRegisterBankInfo::RegBanks[] = {
117    &ARM::FPRRegBank,
118    &ARM::GPRRegBank,
119};
120
121ARMGenRegisterBankInfo::ARMGenRegisterBankInfo()
122    : RegisterBankInfo(RegBanks, ARM::NumRegisterBanks) {
123  // Assert that RegBank indices match their ID's
124#ifndef NDEBUG
125  for (auto RB : enumerate(RegBanks))
126    assert(RB.index() == RB.value()->getID() && "Index != ID");
127#endif // NDEBUG
128}
129} // end namespace llvm
130#endif // GET_TARGET_REGBANK_IMPL
131