1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Global Instruction Selector for the PPC target *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9#ifdef GET_GLOBALISEL_PREDICATE_BITSET 10const unsigned MAX_SUBTARGET_PREDICATES = 39; 11using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>; 12#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET 13 14#ifdef GET_GLOBALISEL_TEMPORARIES_DECL 15 mutable MatcherState State; 16 typedef ComplexRendererFns(PPCInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; 17 typedef void(PPCInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const; 18 const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo; 19 static PPCInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; 20 static PPCInstructionSelector::CustomRendererFn CustomRenderers[]; 21 bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; 22 bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; 23 bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; 24 const int64_t *getMatchTable() const override; 25 bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const std::array<const MachineOperand *, 3> &Operands) const override; 26#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL 27 28#ifdef GET_GLOBALISEL_TEMPORARIES_INIT 29, State(0), 30ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) 31#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT 32 33#ifdef GET_GLOBALISEL_IMPL 34// Bits for subtarget features that participate in instruction matching. 35enum SubtargetFeatureBits : uint8_t { 36 Feature_In32BitModeBit = 1, 37 Feature_In64BitModeBit = 9, 38 Feature_HasOnlyMSYNCBit = 23, 39 Feature_HasSYNCBit = 22, 40 Feature_HasSPEBit = 8, 41 Feature_HasICBTBit = 21, 42 Feature_HasBPERMDBit = 10, 43 Feature_HasExtDivBit = 3, 44 Feature_IsISA2_06Bit = 11, 45 Feature_IsISA2_07Bit = 38, 46 Feature_IsISA3_0Bit = 2, 47 Feature_HasFPUBit = 0, 48 Feature_PCRelativeMemopsBit = 35, 49 Feature_IsNotISA3_1Bit = 37, 50 Feature_IsAIXBit = 24, 51 Feature_NotAIXBit = 25, 52 Feature_IsISAFutureBit = 20, 53 Feature_IsNotISAFutureBit = 18, 54 Feature_HasAltivecBit = 4, 55 Feature_HasP8AltivecBit = 5, 56 Feature_HasP8CryptoBit = 6, 57 Feature_HasP9AltivecBit = 7, 58 Feature_HasVSXBit = 12, 59 Feature_IsLittleEndianBit = 26, 60 Feature_IsBigEndianBit = 27, 61 Feature_IsPPC64Bit = 30, 62 Feature_HasOnlySwappingMemOpsBit = 29, 63 Feature_HasP8VectorBit = 13, 64 Feature_HasDirectMoveBit = 14, 65 Feature_NoP9VectorBit = 28, 66 Feature_HasP9VectorBit = 15, 67 Feature_NoP9AltivecBit = 31, 68 Feature_NoP10VectorBit = 32, 69 Feature_HasHTMBit = 33, 70 Feature_IsPPC32Bit = 36, 71 Feature_PrefixInstrsBit = 16, 72 Feature_IsISA3_1Bit = 17, 73 Feature_PairedVectorMemopsBit = 34, 74 Feature_MMABit = 19, 75}; 76 77PredicateBitset PPCInstructionSelector:: 78computeAvailableModuleFeatures(const PPCSubtarget *Subtarget) const { 79 PredicateBitset Features; 80 if (!Subtarget->isPPC64()) 81 Features.set(Feature_In32BitModeBit); 82 if (Subtarget->isPPC64()) 83 Features.set(Feature_In64BitModeBit); 84 if (Subtarget->hasOnlyMSYNC()) 85 Features.set(Feature_HasOnlyMSYNCBit); 86 if (!Subtarget->hasOnlyMSYNC()) 87 Features.set(Feature_HasSYNCBit); 88 if (Subtarget->hasSPE()) 89 Features.set(Feature_HasSPEBit); 90 if (Subtarget->hasICBT()) 91 Features.set(Feature_HasICBTBit); 92 if (Subtarget->hasBPERMD()) 93 Features.set(Feature_HasBPERMDBit); 94 if (Subtarget->hasExtDiv()) 95 Features.set(Feature_HasExtDivBit); 96 if (Subtarget->isISA2_06()) 97 Features.set(Feature_IsISA2_06Bit); 98 if (Subtarget->isISA2_07()) 99 Features.set(Feature_IsISA2_07Bit); 100 if (Subtarget->isISA3_0()) 101 Features.set(Feature_IsISA3_0Bit); 102 if (Subtarget->hasFPU()) 103 Features.set(Feature_HasFPUBit); 104 if (Subtarget->hasPCRelativeMemops()) 105 Features.set(Feature_PCRelativeMemopsBit); 106 if (!Subtarget->isISA3_1()) 107 Features.set(Feature_IsNotISA3_1Bit); 108 if (Subtarget->isAIXABI()) 109 Features.set(Feature_IsAIXBit); 110 if (!Subtarget->isAIXABI()) 111 Features.set(Feature_NotAIXBit); 112 if (Subtarget->isISAFuture()) 113 Features.set(Feature_IsISAFutureBit); 114 if (!Subtarget->isISAFuture()) 115 Features.set(Feature_IsNotISAFutureBit); 116 if (Subtarget->hasAltivec()) 117 Features.set(Feature_HasAltivecBit); 118 if (Subtarget->hasP8Altivec()) 119 Features.set(Feature_HasP8AltivecBit); 120 if (Subtarget->hasP8Crypto()) 121 Features.set(Feature_HasP8CryptoBit); 122 if (Subtarget->hasP9Altivec()) 123 Features.set(Feature_HasP9AltivecBit); 124 if (Subtarget->hasVSX()) 125 Features.set(Feature_HasVSXBit); 126 if (Subtarget->isLittleEndian()) 127 Features.set(Feature_IsLittleEndianBit); 128 if (!Subtarget->isLittleEndian()) 129 Features.set(Feature_IsBigEndianBit); 130 if (Subtarget->isPPC64()) 131 Features.set(Feature_IsPPC64Bit); 132 if (!Subtarget->hasP9Vector()) 133 Features.set(Feature_HasOnlySwappingMemOpsBit); 134 if (Subtarget->hasP8Vector()) 135 Features.set(Feature_HasP8VectorBit); 136 if (Subtarget->hasDirectMove()) 137 Features.set(Feature_HasDirectMoveBit); 138 if (!Subtarget->hasP9Vector()) 139 Features.set(Feature_NoP9VectorBit); 140 if (Subtarget->hasP9Vector()) 141 Features.set(Feature_HasP9VectorBit); 142 if (!Subtarget->hasP9Altivec()) 143 Features.set(Feature_NoP9AltivecBit); 144 if (!Subtarget->hasP10Vector()) 145 Features.set(Feature_NoP10VectorBit); 146 if (Subtarget->hasHTM()) 147 Features.set(Feature_HasHTMBit); 148 if (!Subtarget->isPPC64()) 149 Features.set(Feature_IsPPC32Bit); 150 if (Subtarget->hasPrefixInstrs()) 151 Features.set(Feature_PrefixInstrsBit); 152 if (Subtarget->isISA3_1()) 153 Features.set(Feature_IsISA3_1Bit); 154 if (Subtarget->pairedVectorMemops()) 155 Features.set(Feature_PairedVectorMemopsBit); 156 if (Subtarget->hasMMA()) 157 Features.set(Feature_MMABit); 158 return Features; 159} 160 161void PPCInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) { 162 AvailableFunctionFeatures = computeAvailableFunctionFeatures((const PPCSubtarget *)&MF.getSubtarget(), &MF); 163} 164PredicateBitset PPCInstructionSelector:: 165computeAvailableFunctionFeatures(const PPCSubtarget *Subtarget, const MachineFunction *MF) const { 166 PredicateBitset Features; 167 return Features; 168} 169 170// LLT Objects. 171enum { 172 GILLT_s1, 173 GILLT_s32, 174 GILLT_s64, 175 GILLT_s128, 176 GILLT_v2s64, 177 GILLT_v4s32, 178 GILLT_v8s16, 179 GILLT_v16s8, 180 GILLT_v256s1, 181 GILLT_v512s1, 182}; 183const static size_t NumTypeObjects = 10; 184const static LLT TypeObjects[] = { 185 LLT::scalar(1), 186 LLT::scalar(32), 187 LLT::scalar(64), 188 LLT::scalar(128), 189 LLT::vector(ElementCount::getFixed(2), 64), 190 LLT::vector(ElementCount::getFixed(4), 32), 191 LLT::vector(ElementCount::getFixed(8), 16), 192 LLT::vector(ElementCount::getFixed(16), 8), 193 LLT::vector(ElementCount::getFixed(256), 1), 194 LLT::vector(ElementCount::getFixed(512), 1), 195}; 196 197// Feature bitsets. 198enum { 199 GIFBS_Invalid, 200 GIFBS_HasAltivec, 201 GIFBS_HasBPERMD, 202 GIFBS_HasExtDiv, 203 GIFBS_HasFPU, 204 GIFBS_HasHTM, 205 GIFBS_HasOnlyMSYNC, 206 GIFBS_HasP8Altivec, 207 GIFBS_HasP8Crypto, 208 GIFBS_HasP9Altivec, 209 GIFBS_HasSPE, 210 GIFBS_HasSYNC, 211 GIFBS_HasVSX, 212 GIFBS_IsAIX, 213 GIFBS_IsISA3_0, 214 GIFBS_IsISA3_1, 215 GIFBS_NotAIX, 216 GIFBS_PrefixInstrs, 217 GIFBS_HasDirectMove_HasVSX, 218 GIFBS_HasP8Vector_HasVSX, 219 GIFBS_HasP9Vector_HasVSX, 220 GIFBS_IsISAFuture_MMA, 221 GIFBS_IsNotISAFuture_MMA, 222}; 223const static PredicateBitset FeatureBitsets[] { 224 {}, // GIFBS_Invalid 225 {Feature_HasAltivecBit, }, 226 {Feature_HasBPERMDBit, }, 227 {Feature_HasExtDivBit, }, 228 {Feature_HasFPUBit, }, 229 {Feature_HasHTMBit, }, 230 {Feature_HasOnlyMSYNCBit, }, 231 {Feature_HasP8AltivecBit, }, 232 {Feature_HasP8CryptoBit, }, 233 {Feature_HasP9AltivecBit, }, 234 {Feature_HasSPEBit, }, 235 {Feature_HasSYNCBit, }, 236 {Feature_HasVSXBit, }, 237 {Feature_IsAIXBit, }, 238 {Feature_IsISA3_0Bit, }, 239 {Feature_IsISA3_1Bit, }, 240 {Feature_NotAIXBit, }, 241 {Feature_PrefixInstrsBit, }, 242 {Feature_HasDirectMoveBit, Feature_HasVSXBit, }, 243 {Feature_HasP8VectorBit, Feature_HasVSXBit, }, 244 {Feature_HasP9VectorBit, Feature_HasVSXBit, }, 245 {Feature_IsISAFutureBit, Feature_MMABit, }, 246 {Feature_IsNotISAFutureBit, Feature_MMABit, }, 247}; 248 249// ComplexPattern predicates. 250enum { 251 GICP_Invalid, 252}; 253// See constructor for table contents 254 255// PatFrag predicates. 256enum { 257 GIPFP_I64_Predicate_Msk2Imm = GIPFP_I64_Invalid + 1, 258 GIPFP_I64_Predicate_Msk4Imm, 259 GIPFP_I64_Predicate_Msk8Imm, 260 GIPFP_I64_Predicate_i32immNonAllOneNonZero, 261 GIPFP_I64_Predicate_imm32SExt16, 262 GIPFP_I64_Predicate_imm64SExt16, 263 GIPFP_I64_Predicate_imm64ZExt32, 264 GIPFP_I64_Predicate_immNonAllOneAnyExt8, 265 GIPFP_I64_Predicate_immSExt5NonZero, 266}; 267bool PPCInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { 268 switch (PredicateID) { 269 case GIPFP_I64_Predicate_Msk2Imm: { 270 return isUInt<2>(Imm); 271 llvm_unreachable("ImmediateCode should have returned"); 272 return false; 273 } 274 case GIPFP_I64_Predicate_Msk4Imm: { 275 return isUInt<4>(Imm); 276 llvm_unreachable("ImmediateCode should have returned"); 277 return false; 278 } 279 case GIPFP_I64_Predicate_Msk8Imm: { 280 return isUInt<8>(Imm); 281 llvm_unreachable("ImmediateCode should have returned"); 282 return false; 283 } 284 case GIPFP_I64_Predicate_i32immNonAllOneNonZero: { 285 return Imm && (Imm != -1); 286 llvm_unreachable("ImmediateCode should have returned"); 287 return false; 288 } 289 case GIPFP_I64_Predicate_imm32SExt16: { 290 291 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit 292 // sign extended field. Used by instructions like 'addi'. 293 return (int32_t)Imm == (short)Imm; 294 295 llvm_unreachable("ImmediateCode should have returned"); 296 return false; 297 } 298 case GIPFP_I64_Predicate_imm64SExt16: { 299 300 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit 301 // sign extended field. Used by instructions like 'addi'. 302 return (int64_t)Imm == (short)Imm; 303 304 llvm_unreachable("ImmediateCode should have returned"); 305 return false; 306 } 307 case GIPFP_I64_Predicate_imm64ZExt32: { 308 309 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit 310 // zero extended field. 311 return isUInt<32>(Imm); 312 313 llvm_unreachable("ImmediateCode should have returned"); 314 return false; 315 } 316 case GIPFP_I64_Predicate_immNonAllOneAnyExt8: { 317 318 return (isInt<8>(Imm) && (Imm != -1)) || (isUInt<8>(Imm) && (Imm != 0xFF)); 319 320 llvm_unreachable("ImmediateCode should have returned"); 321 return false; 322 } 323 case GIPFP_I64_Predicate_immSExt5NonZero: { 324 return Imm && isInt<5>(Imm); 325 llvm_unreachable("ImmediateCode should have returned"); 326 return false; 327 } 328 } 329 llvm_unreachable("Unknown predicate"); 330 return false; 331} 332bool PPCInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { 333 llvm_unreachable("Unknown predicate"); 334 return false; 335} 336bool PPCInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { 337 llvm_unreachable("Unknown predicate"); 338 return false; 339} 340bool PPCInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const std::array<const MachineOperand *, 3> &Operands) const { 341 const MachineFunction &MF = *MI.getParent()->getParent(); 342 const MachineRegisterInfo &MRI = MF.getRegInfo(); 343 (void)MRI; 344 llvm_unreachable("Unknown predicate"); 345 return false; 346} 347 348PPCInstructionSelector::ComplexMatcherMemFn 349PPCInstructionSelector::ComplexPredicateFns[] = { 350 nullptr, // GICP_Invalid 351}; 352 353// Custom renderers. 354enum { 355 GICR_Invalid, 356}; 357PPCInstructionSelector::CustomRendererFn 358PPCInstructionSelector::CustomRenderers[] = { 359 nullptr, // GICR_Invalid 360}; 361 362bool PPCInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { 363 MachineFunction &MF = *I.getParent()->getParent(); 364 MachineRegisterInfo &MRI = MF.getRegInfo(); 365 const PredicateBitset AvailableFeatures = getAvailableFeatures(); 366 NewMIVector OutMIs; 367 State.MIs.clear(); 368 State.MIs.push_back(&I); 369 370 if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) { 371 return true; 372 } 373 374 return false; 375} 376 377const int64_t *PPCInstructionSelector::getMatchTable() const { 378 constexpr static int64_t MatchTable0[] = { 379 GIM_SwitchOpcode, /*MI*/0, /*[*/46, 227, /*)*//*default:*//*Label 57*/ 40158, 380 /*TargetOpcode::G_ADD*//*Label 0*/ 186, 381 /*TargetOpcode::G_SUB*//*Label 1*/ 436, 382 /*TargetOpcode::G_MUL*//*Label 2*/ 760, 383 /*TargetOpcode::G_SDIV*//*Label 3*/ 936, 384 /*TargetOpcode::G_UDIV*//*Label 4*/ 1064, 385 /*TargetOpcode::G_SREM*//*Label 5*/ 1192, 386 /*TargetOpcode::G_UREM*//*Label 6*/ 1324, 0, 0, 387 /*TargetOpcode::G_AND*//*Label 7*/ 1456, 388 /*TargetOpcode::G_OR*//*Label 8*/ 2072, 389 /*TargetOpcode::G_XOR*//*Label 9*/ 2688, 0, 0, 0, 0, 0, 0, 0, 0, 390 /*TargetOpcode::G_BUILD_VECTOR*//*Label 10*/ 4991, 0, 0, 0, 0, 391 /*TargetOpcode::G_BITCAST*//*Label 11*/ 5383, 0, 0, 392 /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 12*/ 6958, 393 /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 13*/ 7068, 0, 0, 394 /*TargetOpcode::G_READCYCLECOUNTER*//*Label 14*/ 7178, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 395 /*TargetOpcode::G_FENCE*//*Label 15*/ 7196, 0, 0, 0, 396 /*TargetOpcode::G_INTRINSIC*//*Label 16*/ 7303, 397 /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 17*/ 18995, 398 /*TargetOpcode::G_ANYEXT*//*Label 18*/ 21406, 399 /*TargetOpcode::G_TRUNC*//*Label 19*/ 24479, 400 /*TargetOpcode::G_CONSTANT*//*Label 20*/ 24619, 0, 0, 0, 401 /*TargetOpcode::G_SEXT*//*Label 21*/ 24741, 0, 402 /*TargetOpcode::G_ZEXT*//*Label 22*/ 27804, 0, 0, 403 /*TargetOpcode::G_ASHR*//*Label 23*/ 30765, 0, 0, 0, 404 /*TargetOpcode::G_ROTL*//*Label 24*/ 30860, 0, 405 /*TargetOpcode::G_FCMP*//*Label 25*/ 30992, 406 /*TargetOpcode::G_SELECT*//*Label 26*/ 32545, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 407 /*TargetOpcode::G_UMULH*//*Label 27*/ 32787, 408 /*TargetOpcode::G_SMULH*//*Label 28*/ 32891, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 409 /*TargetOpcode::G_FADD*//*Label 29*/ 32995, 410 /*TargetOpcode::G_FSUB*//*Label 30*/ 33226, 411 /*TargetOpcode::G_FMUL*//*Label 31*/ 33457, 412 /*TargetOpcode::G_FMA*//*Label 32*/ 33670, 0, 413 /*TargetOpcode::G_FDIV*//*Label 33*/ 34280, 0, 0, 0, 0, 0, 0, 0, 0, 414 /*TargetOpcode::G_FNEG*//*Label 34*/ 34493, 415 /*TargetOpcode::G_FPEXT*//*Label 35*/ 36771, 416 /*TargetOpcode::G_FPTRUNC*//*Label 36*/ 36820, 417 /*TargetOpcode::G_FPTOSI*//*Label 37*/ 36880, 418 /*TargetOpcode::G_FPTOUI*//*Label 38*/ 36977, 419 /*TargetOpcode::G_SITOFP*//*Label 39*/ 37074, 420 /*TargetOpcode::G_UITOFP*//*Label 40*/ 37172, 421 /*TargetOpcode::G_FABS*//*Label 41*/ 37270, 422 /*TargetOpcode::G_FCOPYSIGN*//*Label 42*/ 37442, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 423 /*TargetOpcode::G_BR*//*Label 43*/ 37670, 0, 0, 0, 0, 424 /*TargetOpcode::G_CTTZ*//*Label 44*/ 37683, 0, 425 /*TargetOpcode::G_CTLZ*//*Label 45*/ 37817, 0, 426 /*TargetOpcode::G_CTPOP*//*Label 46*/ 37947, 427 /*TargetOpcode::G_BSWAP*//*Label 47*/ 38077, 0, 428 /*TargetOpcode::G_FCEIL*//*Label 48*/ 38169, 0, 0, 429 /*TargetOpcode::G_FSQRT*//*Label 49*/ 38279, 430 /*TargetOpcode::G_FFLOOR*//*Label 50*/ 38442, 0, 0, 0, 0, 0, 0, 431 /*TargetOpcode::G_STRICT_FADD*//*Label 51*/ 38552, 432 /*TargetOpcode::G_STRICT_FSUB*//*Label 52*/ 38765, 433 /*TargetOpcode::G_STRICT_FMUL*//*Label 53*/ 38978, 434 /*TargetOpcode::G_STRICT_FDIV*//*Label 54*/ 39191, 0, 435 /*TargetOpcode::G_STRICT_FMA*//*Label 55*/ 39404, 436 /*TargetOpcode::G_STRICT_FSQRT*//*Label 56*/ 39995, 437 // Label 0: @186 438 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 8, /*)*//*default:*//*Label 65*/ 435, 439 /*GILLT_s32*//*Label 58*/ 199, 440 /*GILLT_s64*//*Label 59*/ 257, 441 /*GILLT_s128*//*Label 60*/ 315, 442 /*GILLT_v2s64*//*Label 61*/ 339, 443 /*GILLT_v4s32*//*Label 62*/ 363, 444 /*GILLT_v8s16*//*Label 63*/ 387, 445 /*GILLT_v16s8*//*Label 64*/ 411, 446 // Label 58: @199 447 GIM_Try, /*On fail goto*//*Label 66*/ 256, 448 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 449 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 451 GIM_Try, /*On fail goto*//*Label 67*/ 246, // Rule ID 104 // 452 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 453 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 454 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32SExt16, 455 // MIs[1] Operand 1 456 // No operand predicates 457 GIM_CheckIsSafeToFold, /*InsnID*/1, 458 // (add:{ *:[i32] } i32:{ *:[i32] }:$rA, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm) => (ADDI:{ *:[i32] } i32:{ *:[i32] }:$rA, (imm:{ *:[i32] }):$imm) 459 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::ADDI, 460 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rD 461 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rA 462 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 463 GIR_EraseFromParent, /*InsnID*/0, 464 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 465 // GIR_Coverage, 104, 466 GIR_Done, 467 // Label 67: @246 468 GIM_Try, /*On fail goto*//*Label 68*/ 255, // Rule ID 196 // 469 // (add:{ *:[i32] } i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) => (ADD4:{ *:[i32] } i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) 470 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::ADD4, 471 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 472 // GIR_Coverage, 196, 473 GIR_Done, 474 // Label 68: @255 475 GIM_Reject, 476 // Label 66: @256 477 GIM_Reject, 478 // Label 59: @257 479 GIM_Try, /*On fail goto*//*Label 69*/ 314, 480 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 481 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 482 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 483 GIM_Try, /*On fail goto*//*Label 70*/ 304, // Rule ID 655 // 484 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 485 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 486 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm64SExt16, 487 // MIs[1] Operand 1 488 // No operand predicates 489 GIM_CheckIsSafeToFold, /*InsnID*/1, 490 // (add:{ *:[i64] } i64:{ *:[i64] }:$rA, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm) => (ADDI8:{ *:[i64] } i64:{ *:[i64] }:$rA, (imm:{ *:[i64] }):$imm) 491 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::ADDI8, 492 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rD 493 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rA 494 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 495 GIR_EraseFromParent, /*InsnID*/0, 496 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 497 // GIR_Coverage, 655, 498 GIR_Done, 499 // Label 70: @304 500 GIM_Try, /*On fail goto*//*Label 71*/ 313, // Rule ID 651 // 501 // (add:{ *:[i64] } i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) => (ADD8:{ *:[i64] } i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) 502 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::ADD8, 503 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 504 // GIR_Coverage, 651, 505 GIR_Done, 506 // Label 71: @313 507 GIM_Reject, 508 // Label 69: @314 509 GIM_Reject, 510 // Label 60: @315 511 GIM_Try, /*On fail goto*//*Label 72*/ 338, // Rule ID 466 // 512 GIM_CheckFeatures, GIFBS_HasP8Altivec, 513 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 514 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 516 // (add:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) => (VADDUQM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) 517 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VADDUQM, 518 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 519 // GIR_Coverage, 466, 520 GIR_Done, 521 // Label 72: @338 522 GIM_Reject, 523 // Label 61: @339 524 GIM_Try, /*On fail goto*//*Label 73*/ 362, // Rule ID 465 // 525 GIM_CheckFeatures, GIFBS_HasP8Altivec, 526 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 527 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 528 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 529 // (add:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VADDUDM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 530 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VADDUDM, 531 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 532 // GIR_Coverage, 465, 533 GIR_Done, 534 // Label 73: @362 535 GIM_Reject, 536 // Label 62: @363 537 GIM_Try, /*On fail goto*//*Label 74*/ 386, // Rule ID 299 // 538 GIM_CheckFeatures, GIFBS_HasAltivec, 539 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 540 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 541 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 542 // (add:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VADDUWM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 543 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VADDUWM, 544 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 545 // GIR_Coverage, 299, 546 GIR_Done, 547 // Label 74: @386 548 GIM_Reject, 549 // Label 63: @387 550 GIM_Try, /*On fail goto*//*Label 75*/ 410, // Rule ID 298 // 551 GIM_CheckFeatures, GIFBS_HasAltivec, 552 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 553 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 555 // (add:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VADDUHM:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 556 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VADDUHM, 557 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 558 // GIR_Coverage, 298, 559 GIR_Done, 560 // Label 75: @410 561 GIM_Reject, 562 // Label 64: @411 563 GIM_Try, /*On fail goto*//*Label 76*/ 434, // Rule ID 297 // 564 GIM_CheckFeatures, GIFBS_HasAltivec, 565 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 566 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 567 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 568 // (add:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VADDUBM:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 569 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VADDUBM, 570 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 571 // GIR_Coverage, 297, 572 GIR_Done, 573 // Label 76: @434 574 GIM_Reject, 575 // Label 65: @435 576 GIM_Reject, 577 // Label 1: @436 578 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 8, /*)*//*default:*//*Label 84*/ 759, 579 /*GILLT_s32*//*Label 77*/ 449, 580 /*GILLT_s64*//*Label 78*/ 509, 581 /*GILLT_s128*//*Label 79*/ 569, 582 /*GILLT_v2s64*//*Label 80*/ 593, 583 /*GILLT_v4s32*//*Label 81*/ 652, 584 /*GILLT_v8s16*//*Label 82*/ 711, 585 /*GILLT_v16s8*//*Label 83*/ 735, 586 // Label 77: @449 587 GIM_Try, /*On fail goto*//*Label 85*/ 508, 588 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 589 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 590 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 591 GIM_Try, /*On fail goto*//*Label 86*/ 485, // Rule ID 208 // 592 GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, 593 // (sub:{ *:[i32] } 0:{ *:[i32] }, i32:{ *:[i32] }:$rA) => (NEG:{ *:[i32] } i32:{ *:[i32] }:$rA) 594 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::NEG, 595 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rT 596 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rA 597 GIR_EraseFromParent, /*InsnID*/0, 598 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 599 // GIR_Coverage, 208, 600 GIR_Done, 601 // Label 86: @485 602 GIM_Try, /*On fail goto*//*Label 87*/ 507, // Rule ID 206 // 603 // (sub:{ *:[i32] } i32:{ *:[i32] }:$rB, i32:{ *:[i32] }:$rA) => (SUBF:{ *:[i32] } i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) 604 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SUBF, 605 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rT 606 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rA 607 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rB 608 GIR_EraseFromParent, /*InsnID*/0, 609 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 610 // GIR_Coverage, 206, 611 GIR_Done, 612 // Label 87: @507 613 GIM_Reject, 614 // Label 85: @508 615 GIM_Reject, 616 // Label 78: @509 617 GIM_Try, /*On fail goto*//*Label 88*/ 568, 618 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 619 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 621 GIM_Try, /*On fail goto*//*Label 89*/ 545, // Rule ID 661 // 622 GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, 623 // (sub:{ *:[i64] } 0:{ *:[i64] }, i64:{ *:[i64] }:$rA) => (NEG8:{ *:[i64] } i64:{ *:[i64] }:$rA) 624 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::NEG8, 625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rT 626 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rA 627 GIR_EraseFromParent, /*InsnID*/0, 628 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 629 // GIR_Coverage, 661, 630 GIR_Done, 631 // Label 89: @545 632 GIM_Try, /*On fail goto*//*Label 90*/ 567, // Rule ID 660 // 633 // (sub:{ *:[i64] } i64:{ *:[i64] }:$rB, i64:{ *:[i64] }:$rA) => (SUBF8:{ *:[i64] } i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) 634 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SUBF8, 635 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rT 636 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rA 637 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rB 638 GIR_EraseFromParent, /*InsnID*/0, 639 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 640 // GIR_Coverage, 660, 641 GIR_Done, 642 // Label 90: @567 643 GIM_Reject, 644 // Label 88: @568 645 GIM_Reject, 646 // Label 79: @569 647 GIM_Try, /*On fail goto*//*Label 91*/ 592, // Rule ID 471 // 648 GIM_CheckFeatures, GIFBS_HasP8Altivec, 649 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 650 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 652 // (sub:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) => (VSUBUQM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) 653 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VSUBUQM, 654 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 655 // GIR_Coverage, 471, 656 GIR_Done, 657 // Label 91: @592 658 GIM_Reject, 659 // Label 80: @593 660 GIM_Try, /*On fail goto*//*Label 92*/ 651, 661 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 662 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 663 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 664 GIM_Try, /*On fail goto*//*Label 93*/ 639, // Rule ID 538 // 665 GIM_CheckFeatures, GIFBS_HasP9Altivec, 666 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 667 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 668 GIM_CheckIsBuildVectorAllZeros, /*MI*/1, 669 GIM_CheckIsSafeToFold, /*InsnID*/1, 670 // (sub:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, v2i64:{ *:[v2i64] }:$vB) => (VNEGD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vB) 671 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VNEGD, 672 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 673 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 674 GIR_EraseFromParent, /*InsnID*/0, 675 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 676 // GIR_Coverage, 538, 677 GIR_Done, 678 // Label 93: @639 679 GIM_Try, /*On fail goto*//*Label 94*/ 650, // Rule ID 470 // 680 GIM_CheckFeatures, GIFBS_HasP8Altivec, 681 // (sub:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VSUBUDM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 682 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VSUBUDM, 683 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 684 // GIR_Coverage, 470, 685 GIR_Done, 686 // Label 94: @650 687 GIM_Reject, 688 // Label 92: @651 689 GIM_Reject, 690 // Label 81: @652 691 GIM_Try, /*On fail goto*//*Label 95*/ 710, 692 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 693 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 694 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 695 GIM_Try, /*On fail goto*//*Label 96*/ 698, // Rule ID 537 // 696 GIM_CheckFeatures, GIFBS_HasP9Altivec, 697 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 698 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 699 GIM_CheckIsBuildVectorAllZeros, /*MI*/1, 700 GIM_CheckIsSafeToFold, /*InsnID*/1, 701 // (sub:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, v4i32:{ *:[v4i32] }:$vB) => (VNEGW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB) 702 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VNEGW, 703 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 705 GIR_EraseFromParent, /*InsnID*/0, 706 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 707 // GIR_Coverage, 537, 708 GIR_Done, 709 // Label 96: @698 710 GIM_Try, /*On fail goto*//*Label 97*/ 709, // Rule ID 369 // 711 GIM_CheckFeatures, GIFBS_HasAltivec, 712 // (sub:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSUBUWM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 713 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VSUBUWM, 714 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 715 // GIR_Coverage, 369, 716 GIR_Done, 717 // Label 97: @709 718 GIM_Reject, 719 // Label 95: @710 720 GIM_Reject, 721 // Label 82: @711 722 GIM_Try, /*On fail goto*//*Label 98*/ 734, // Rule ID 368 // 723 GIM_CheckFeatures, GIFBS_HasAltivec, 724 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 725 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 726 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 727 // (sub:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VSUBUHM:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 728 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VSUBUHM, 729 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 730 // GIR_Coverage, 368, 731 GIR_Done, 732 // Label 98: @734 733 GIM_Reject, 734 // Label 83: @735 735 GIM_Try, /*On fail goto*//*Label 99*/ 758, // Rule ID 367 // 736 GIM_CheckFeatures, GIFBS_HasAltivec, 737 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 738 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 740 // (sub:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VSUBUBM:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 741 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VSUBUBM, 742 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 743 // GIR_Coverage, 367, 744 GIR_Done, 745 // Label 99: @758 746 GIM_Reject, 747 // Label 84: @759 748 GIM_Reject, 749 // Label 2: @760 750 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 104*/ 935, 751 /*GILLT_s32*//*Label 100*/ 771, 752 /*GILLT_s64*//*Label 101*/ 829, 0, 753 /*GILLT_v2s64*//*Label 102*/ 887, 754 /*GILLT_v4s32*//*Label 103*/ 911, 755 // Label 100: @771 756 GIM_Try, /*On fail goto*//*Label 105*/ 828, 757 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 758 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 759 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 760 GIM_Try, /*On fail goto*//*Label 106*/ 818, // Rule ID 108 // 761 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 762 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 763 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32SExt16, 764 // MIs[1] Operand 1 765 // No operand predicates 766 GIM_CheckIsSafeToFold, /*InsnID*/1, 767 // (mul:{ *:[i32] } i32:{ *:[i32] }:$rA, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm) => (MULLI:{ *:[i32] } i32:{ *:[i32] }:$rA, (imm:{ *:[i32] }):$imm) 768 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MULLI, 769 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rD 770 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rA 771 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 772 GIR_EraseFromParent, /*InsnID*/0, 773 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 774 // GIR_Coverage, 108, 775 GIR_Done, 776 // Label 106: @818 777 GIM_Try, /*On fail goto*//*Label 107*/ 827, // Rule ID 205 // 778 // (mul:{ *:[i32] } i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) => (MULLW:{ *:[i32] } i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) 779 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::MULLW, 780 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 781 // GIR_Coverage, 205, 782 GIR_Done, 783 // Label 107: @827 784 GIM_Reject, 785 // Label 105: @828 786 GIM_Reject, 787 // Label 101: @829 788 GIM_Try, /*On fail goto*//*Label 108*/ 886, 789 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 790 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 791 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 792 GIM_Try, /*On fail goto*//*Label 109*/ 876, // Rule ID 695 // 793 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 794 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 795 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm64SExt16, 796 // MIs[1] Operand 1 797 // No operand predicates 798 GIM_CheckIsSafeToFold, /*InsnID*/1, 799 // (mul:{ *:[i64] } i64:{ *:[i64] }:$rA, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm) => (MULLI8:{ *:[i64] } i64:{ *:[i64] }:$rA, (imm:{ *:[i64] }):$imm) 800 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MULLI8, 801 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rD 802 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rA 803 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 804 GIR_EraseFromParent, /*InsnID*/0, 805 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 806 // GIR_Coverage, 695, 807 GIR_Done, 808 // Label 109: @876 809 GIM_Try, /*On fail goto*//*Label 110*/ 885, // Rule ID 694 // 810 // (mul:{ *:[i64] } i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) => (MULLD:{ *:[i64] } i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) 811 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::MULLD, 812 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 813 // GIR_Coverage, 694, 814 GIR_Done, 815 // Label 110: @885 816 GIM_Reject, 817 // Label 108: @886 818 GIM_Reject, 819 // Label 102: @887 820 GIM_Try, /*On fail goto*//*Label 111*/ 910, // Rule ID 1102 // 821 GIM_CheckFeatures, GIFBS_IsISA3_1, 822 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 823 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 824 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 825 // (mul:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VMULLD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 826 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VMULLD, 827 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 828 // GIR_Coverage, 1102, 829 GIR_Done, 830 // Label 111: @910 831 GIM_Reject, 832 // Label 103: @911 833 GIM_Try, /*On fail goto*//*Label 112*/ 934, // Rule ID 457 // 834 GIM_CheckFeatures, GIFBS_HasP8Altivec, 835 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 836 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 837 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 838 // (mul:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VMULUWM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 839 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VMULUWM, 840 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 841 // GIR_Coverage, 457, 842 GIR_Done, 843 // Label 112: @934 844 GIM_Reject, 845 // Label 104: @935 846 GIM_Reject, 847 // Label 3: @936 848 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 118*/ 1063, 849 /*GILLT_s32*//*Label 113*/ 947, 850 /*GILLT_s64*//*Label 114*/ 969, 851 /*GILLT_s128*//*Label 115*/ 991, 852 /*GILLT_v2s64*//*Label 116*/ 1015, 853 /*GILLT_v4s32*//*Label 117*/ 1039, 854 // Label 113: @947 855 GIM_Try, /*On fail goto*//*Label 119*/ 968, // Rule ID 199 // 856 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 857 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 858 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 859 // (sdiv:{ *:[i32] } i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) => (DIVW:{ *:[i32] } i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) 860 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::DIVW, 861 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 862 // GIR_Coverage, 199, 863 GIR_Done, 864 // Label 119: @968 865 GIM_Reject, 866 // Label 114: @969 867 GIM_Try, /*On fail goto*//*Label 120*/ 990, // Rule ID 686 // 868 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 869 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 870 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 871 // (sdiv:{ *:[i64] } i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) => (DIVD:{ *:[i64] } i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) 872 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::DIVD, 873 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 874 // GIR_Coverage, 686, 875 GIR_Done, 876 // Label 120: @990 877 GIM_Reject, 878 // Label 115: @991 879 GIM_Try, /*On fail goto*//*Label 121*/ 1014, // Rule ID 1126 // 880 GIM_CheckFeatures, GIFBS_IsISA3_1, 881 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 882 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 883 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 884 // (sdiv:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) => (VDIVSQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) 885 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VDIVSQ, 886 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 887 // GIR_Coverage, 1126, 888 GIR_Done, 889 // Label 121: @1014 890 GIM_Reject, 891 // Label 116: @1015 892 GIM_Try, /*On fail goto*//*Label 122*/ 1038, // Rule ID 1113 // 893 GIM_CheckFeatures, GIFBS_IsISA3_1, 894 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 895 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 896 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 897 // (sdiv:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VDIVSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 898 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VDIVSD, 899 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 900 // GIR_Coverage, 1113, 901 GIR_Done, 902 // Label 122: @1038 903 GIM_Reject, 904 // Label 117: @1039 905 GIM_Try, /*On fail goto*//*Label 123*/ 1062, // Rule ID 1111 // 906 GIM_CheckFeatures, GIFBS_IsISA3_1, 907 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 908 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 909 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 910 // (sdiv:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VDIVSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 911 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VDIVSW, 912 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 913 // GIR_Coverage, 1111, 914 GIR_Done, 915 // Label 123: @1062 916 GIM_Reject, 917 // Label 118: @1063 918 GIM_Reject, 919 // Label 4: @1064 920 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 129*/ 1191, 921 /*GILLT_s32*//*Label 124*/ 1075, 922 /*GILLT_s64*//*Label 125*/ 1097, 923 /*GILLT_s128*//*Label 126*/ 1119, 924 /*GILLT_v2s64*//*Label 127*/ 1143, 925 /*GILLT_v4s32*//*Label 128*/ 1167, 926 // Label 124: @1075 927 GIM_Try, /*On fail goto*//*Label 130*/ 1096, // Rule ID 200 // 928 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 929 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 930 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 931 // (udiv:{ *:[i32] } i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) => (DIVWU:{ *:[i32] } i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) 932 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::DIVWU, 933 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 934 // GIR_Coverage, 200, 935 GIR_Done, 936 // Label 130: @1096 937 GIM_Reject, 938 // Label 125: @1097 939 GIM_Try, /*On fail goto*//*Label 131*/ 1118, // Rule ID 687 // 940 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 941 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 943 // (udiv:{ *:[i64] } i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) => (DIVDU:{ *:[i64] } i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) 944 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::DIVDU, 945 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 946 // GIR_Coverage, 687, 947 GIR_Done, 948 // Label 131: @1118 949 GIM_Reject, 950 // Label 126: @1119 951 GIM_Try, /*On fail goto*//*Label 132*/ 1142, // Rule ID 1127 // 952 GIM_CheckFeatures, GIFBS_IsISA3_1, 953 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 954 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 956 // (udiv:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) => (VDIVUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) 957 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VDIVUQ, 958 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 959 // GIR_Coverage, 1127, 960 GIR_Done, 961 // Label 132: @1142 962 GIM_Reject, 963 // Label 127: @1143 964 GIM_Try, /*On fail goto*//*Label 133*/ 1166, // Rule ID 1114 // 965 GIM_CheckFeatures, GIFBS_IsISA3_1, 966 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 967 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 968 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 969 // (udiv:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VDIVUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 970 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VDIVUD, 971 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 972 // GIR_Coverage, 1114, 973 GIR_Done, 974 // Label 133: @1166 975 GIM_Reject, 976 // Label 128: @1167 977 GIM_Try, /*On fail goto*//*Label 134*/ 1190, // Rule ID 1112 // 978 GIM_CheckFeatures, GIFBS_IsISA3_1, 979 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 980 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 982 // (udiv:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VDIVUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 983 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VDIVUW, 984 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 985 // GIR_Coverage, 1112, 986 GIR_Done, 987 // Label 134: @1190 988 GIM_Reject, 989 // Label 129: @1191 990 GIM_Reject, 991 // Label 5: @1192 992 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 140*/ 1323, 993 /*GILLT_s32*//*Label 135*/ 1203, 994 /*GILLT_s64*//*Label 136*/ 1227, 995 /*GILLT_s128*//*Label 137*/ 1251, 996 /*GILLT_v2s64*//*Label 138*/ 1275, 997 /*GILLT_v4s32*//*Label 139*/ 1299, 998 // Label 135: @1203 999 GIM_Try, /*On fail goto*//*Label 141*/ 1226, // Rule ID 194 // 1000 GIM_CheckFeatures, GIFBS_IsISA3_0, 1001 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 1002 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 1003 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 1004 // (srem:{ *:[i32] } i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) => (MODSW:{ *:[i32] } i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) 1005 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::MODSW, 1006 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1007 // GIR_Coverage, 194, 1008 GIR_Done, 1009 // Label 141: @1226 1010 GIM_Reject, 1011 // Label 136: @1227 1012 GIM_Try, /*On fail goto*//*Label 142*/ 1250, // Rule ID 691 // 1013 GIM_CheckFeatures, GIFBS_IsISA3_0, 1014 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 1015 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 1016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 1017 // (srem:{ *:[i64] } i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) => (MODSD:{ *:[i64] } i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) 1018 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::MODSD, 1019 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1020 // GIR_Coverage, 691, 1021 GIR_Done, 1022 // Label 142: @1250 1023 GIM_Reject, 1024 // Label 137: @1251 1025 GIM_Try, /*On fail goto*//*Label 143*/ 1274, // Rule ID 1136 // 1026 GIM_CheckFeatures, GIFBS_IsISA3_1, 1027 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 1028 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 1029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 1030 // (srem:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) => (VMODSQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) 1031 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VMODSQ, 1032 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1033 // GIR_Coverage, 1136, 1034 GIR_Done, 1035 // Label 143: @1274 1036 GIM_Reject, 1037 // Label 138: @1275 1038 GIM_Try, /*On fail goto*//*Label 144*/ 1298, // Rule ID 1109 // 1039 GIM_CheckFeatures, GIFBS_IsISA3_1, 1040 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 1041 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 1042 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 1043 // (srem:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VMODSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 1044 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VMODSD, 1045 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1046 // GIR_Coverage, 1109, 1047 GIR_Done, 1048 // Label 144: @1298 1049 GIM_Reject, 1050 // Label 139: @1299 1051 GIM_Try, /*On fail goto*//*Label 145*/ 1322, // Rule ID 1107 // 1052 GIM_CheckFeatures, GIFBS_IsISA3_1, 1053 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 1054 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 1055 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 1056 // (srem:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VMODSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 1057 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VMODSW, 1058 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1059 // GIR_Coverage, 1107, 1060 GIR_Done, 1061 // Label 145: @1322 1062 GIM_Reject, 1063 // Label 140: @1323 1064 GIM_Reject, 1065 // Label 6: @1324 1066 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 151*/ 1455, 1067 /*GILLT_s32*//*Label 146*/ 1335, 1068 /*GILLT_s64*//*Label 147*/ 1359, 1069 /*GILLT_s128*//*Label 148*/ 1383, 1070 /*GILLT_v2s64*//*Label 149*/ 1407, 1071 /*GILLT_v4s32*//*Label 150*/ 1431, 1072 // Label 146: @1335 1073 GIM_Try, /*On fail goto*//*Label 152*/ 1358, // Rule ID 195 // 1074 GIM_CheckFeatures, GIFBS_IsISA3_0, 1075 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 1076 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 1077 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 1078 // (urem:{ *:[i32] } i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) => (MODUW:{ *:[i32] } i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) 1079 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::MODUW, 1080 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1081 // GIR_Coverage, 195, 1082 GIR_Done, 1083 // Label 152: @1358 1084 GIM_Reject, 1085 // Label 147: @1359 1086 GIM_Try, /*On fail goto*//*Label 153*/ 1382, // Rule ID 692 // 1087 GIM_CheckFeatures, GIFBS_IsISA3_0, 1088 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 1089 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 1090 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 1091 // (urem:{ *:[i64] } i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) => (MODUD:{ *:[i64] } i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) 1092 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::MODUD, 1093 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1094 // GIR_Coverage, 692, 1095 GIR_Done, 1096 // Label 153: @1382 1097 GIM_Reject, 1098 // Label 148: @1383 1099 GIM_Try, /*On fail goto*//*Label 154*/ 1406, // Rule ID 1137 // 1100 GIM_CheckFeatures, GIFBS_IsISA3_1, 1101 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 1102 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 1103 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 1104 // (urem:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) => (VMODUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) 1105 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VMODUQ, 1106 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1107 // GIR_Coverage, 1137, 1108 GIR_Done, 1109 // Label 154: @1406 1110 GIM_Reject, 1111 // Label 149: @1407 1112 GIM_Try, /*On fail goto*//*Label 155*/ 1430, // Rule ID 1110 // 1113 GIM_CheckFeatures, GIFBS_IsISA3_1, 1114 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 1115 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 1116 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 1117 // (urem:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VMODUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 1118 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VMODUD, 1119 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1120 // GIR_Coverage, 1110, 1121 GIR_Done, 1122 // Label 155: @1430 1123 GIM_Reject, 1124 // Label 150: @1431 1125 GIM_Try, /*On fail goto*//*Label 156*/ 1454, // Rule ID 1108 // 1126 GIM_CheckFeatures, GIFBS_IsISA3_1, 1127 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 1128 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 1129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 1130 // (urem:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VMODUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 1131 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VMODUW, 1132 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1133 // GIR_Coverage, 1108, 1134 GIR_Done, 1135 // Label 156: @1454 1136 GIM_Reject, 1137 // Label 151: @1455 1138 GIM_Reject, 1139 // Label 7: @1456 1140 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 6, /*)*//*default:*//*Label 161*/ 2071, 1141 /*GILLT_s1*//*Label 157*/ 1468, 1142 /*GILLT_s32*//*Label 158*/ 1579, 1143 /*GILLT_s64*//*Label 159*/ 1690, 0, 0, 1144 /*GILLT_v4s32*//*Label 160*/ 1801, 1145 // Label 157: @1468 1146 GIM_Try, /*On fail goto*//*Label 162*/ 1578, 1147 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 1148 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1, 1149 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 1150 GIM_Try, /*On fail goto*//*Label 163*/ 1525, // Rule ID 4854 // 1151 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1152 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 1153 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, 1154 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, 1155 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 1156 GIM_CheckIsSafeToFold, /*InsnID*/1, 1157 // (and:{ *:[i1] } (xor:{ *:[i1] } i1:{ *:[i1] }:$CRB, -1:{ *:[i1] }), i1:{ *:[i1] }:$CRA) => (CRANDC:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) 1158 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CRANDC, 1159 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // CRD 1160 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // CRA 1161 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRB 1162 GIR_EraseFromParent, /*InsnID*/0, 1163 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1164 // GIR_Coverage, 4854, 1165 GIR_Done, 1166 // Label 163: @1525 1167 GIM_Try, /*On fail goto*//*Label 164*/ 1568, // Rule ID 179 // 1168 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1169 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 1170 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, 1171 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, 1172 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 1173 GIM_CheckIsSafeToFold, /*InsnID*/1, 1174 // (and:{ *:[i1] } i1:{ *:[i1] }:$CRA, (xor:{ *:[i1] } i1:{ *:[i1] }:$CRB, -1:{ *:[i1] })) => (CRANDC:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) 1175 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CRANDC, 1176 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // CRD 1177 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // CRA 1178 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRB 1179 GIR_EraseFromParent, /*InsnID*/0, 1180 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1181 // GIR_Coverage, 179, 1182 GIR_Done, 1183 // Label 164: @1568 1184 GIM_Try, /*On fail goto*//*Label 165*/ 1577, // Rule ID 172 // 1185 // (and:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) => (CRAND:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) 1186 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::CRAND, 1187 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1188 // GIR_Coverage, 172, 1189 GIR_Done, 1190 // Label 165: @1577 1191 GIM_Reject, 1192 // Label 162: @1578 1193 GIM_Reject, 1194 // Label 158: @1579 1195 GIM_Try, /*On fail goto*//*Label 166*/ 1689, 1196 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 1197 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 1198 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 1199 GIM_Try, /*On fail goto*//*Label 167*/ 1636, // Rule ID 4848 // 1200 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1201 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 1202 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1203 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1204 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 1205 GIM_CheckIsSafeToFold, /*InsnID*/1, 1206 // (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$rB, -1:{ *:[i32] }), i32:{ *:[i32] }:$rS) => (ANDC:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB) 1207 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::ANDC, 1208 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 1209 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rS 1210 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rB 1211 GIR_EraseFromParent, /*InsnID*/0, 1212 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1213 // GIR_Coverage, 4848, 1214 GIR_Done, 1215 // Label 167: @1636 1216 GIM_Try, /*On fail goto*//*Label 168*/ 1679, // Rule ID 120 // 1217 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1218 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 1219 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1220 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1221 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 1222 GIM_CheckIsSafeToFold, /*InsnID*/1, 1223 // (and:{ *:[i32] } i32:{ *:[i32] }:$rS, (xor:{ *:[i32] } i32:{ *:[i32] }:$rB, -1:{ *:[i32] })) => (ANDC:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB) 1224 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::ANDC, 1225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 1226 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rS 1227 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rB 1228 GIR_EraseFromParent, /*InsnID*/0, 1229 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1230 // GIR_Coverage, 120, 1231 GIR_Done, 1232 // Label 168: @1679 1233 GIM_Try, /*On fail goto*//*Label 169*/ 1688, // Rule ID 119 // 1234 // (and:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB) => (AND:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB) 1235 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::AND, 1236 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1237 // GIR_Coverage, 119, 1238 GIR_Done, 1239 // Label 169: @1688 1240 GIM_Reject, 1241 // Label 166: @1689 1242 GIM_Reject, 1243 // Label 159: @1690 1244 GIM_Try, /*On fail goto*//*Label 170*/ 1800, 1245 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 1246 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 1247 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 1248 GIM_Try, /*On fail goto*//*Label 171*/ 1747, // Rule ID 4861 // 1249 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1250 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 1251 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 1252 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 1253 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 1254 GIM_CheckIsSafeToFold, /*InsnID*/1, 1255 // (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$rB, -1:{ *:[i64] }), i64:{ *:[i64] }:$rS) => (ANDC8:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) 1256 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::ANDC8, 1257 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 1258 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rS 1259 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rB 1260 GIR_EraseFromParent, /*InsnID*/0, 1261 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1262 // GIR_Coverage, 4861, 1263 GIR_Done, 1264 // Label 171: @1747 1265 GIM_Try, /*On fail goto*//*Label 172*/ 1790, // Rule ID 639 // 1266 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1267 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 1268 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 1269 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 1270 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 1271 GIM_CheckIsSafeToFold, /*InsnID*/1, 1272 // (and:{ *:[i64] } i64:{ *:[i64] }:$rS, (xor:{ *:[i64] } i64:{ *:[i64] }:$rB, -1:{ *:[i64] })) => (ANDC8:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) 1273 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::ANDC8, 1274 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 1275 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rS 1276 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rB 1277 GIR_EraseFromParent, /*InsnID*/0, 1278 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1279 // GIR_Coverage, 639, 1280 GIR_Done, 1281 // Label 172: @1790 1282 GIM_Try, /*On fail goto*//*Label 173*/ 1799, // Rule ID 638 // 1283 // (and:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) => (AND8:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) 1284 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::AND8, 1285 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1286 // GIR_Coverage, 638, 1287 GIR_Done, 1288 // Label 173: @1799 1289 GIM_Reject, 1290 // Label 170: @1800 1291 GIM_Reject, 1292 // Label 160: @1801 1293 GIM_Try, /*On fail goto*//*Label 174*/ 2070, 1294 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 1295 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 1296 GIM_Try, /*On fail goto*//*Label 175*/ 1868, // Rule ID 4869 // 1297 GIM_CheckFeatures, GIFBS_HasVSX, 1298 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 1299 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1300 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 1301 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 1302 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 1303 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1304 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 1305 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 1306 GIM_CheckIsSafeToFold, /*InsnID*/1, 1307 GIM_CheckIsSafeToFold, /*InsnID*/2, 1308 // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$XA) => (XXLANDC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) 1309 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XXLANDC, 1310 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 1311 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XA 1312 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB 1313 GIR_EraseFromParent, /*InsnID*/0, 1314 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1315 // GIR_Coverage, 4869, 1316 GIR_Done, 1317 // Label 175: @1868 1318 GIM_Try, /*On fail goto*//*Label 176*/ 1925, // Rule ID 921 // 1319 GIM_CheckFeatures, GIFBS_HasVSX, 1320 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 1321 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1322 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 1323 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 1324 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 1325 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1326 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 1327 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 1328 GIM_CheckIsSafeToFold, /*InsnID*/1, 1329 GIM_CheckIsSafeToFold, /*InsnID*/2, 1330 // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB, immAllOnesV:{ *:[v4i32] })) => (XXLANDC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) 1331 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XXLANDC, 1332 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 1333 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // XA 1334 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB 1335 GIR_EraseFromParent, /*InsnID*/0, 1336 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1337 // GIR_Coverage, 921, 1338 GIR_Done, 1339 // Label 176: @1925 1340 GIM_Try, /*On fail goto*//*Label 177*/ 1940, // Rule ID 920 // 1341 GIM_CheckFeatures, GIFBS_HasVSX, 1342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 1343 // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) => (XXLAND:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) 1344 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XXLAND, 1345 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1346 // GIR_Coverage, 920, 1347 GIR_Done, 1348 // Label 177: @1940 1349 GIM_Try, /*On fail goto*//*Label 178*/ 1997, // Rule ID 4857 // 1350 GIM_CheckFeatures, GIFBS_HasAltivec, 1351 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 1352 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1353 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 1354 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 1355 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 1356 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1357 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 1358 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 1359 GIM_CheckIsSafeToFold, /*InsnID*/1, 1360 GIM_CheckIsSafeToFold, /*InsnID*/2, 1361 // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$vA) => (VANDC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 1362 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VANDC, 1363 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 1364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 1365 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB 1366 GIR_EraseFromParent, /*InsnID*/0, 1367 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1368 // GIR_Coverage, 4857, 1369 GIR_Done, 1370 // Label 178: @1997 1371 GIM_Try, /*On fail goto*//*Label 179*/ 2054, // Rule ID 308 // 1372 GIM_CheckFeatures, GIFBS_HasAltivec, 1373 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 1374 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1375 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 1376 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 1377 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 1378 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1379 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 1380 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 1381 GIM_CheckIsSafeToFold, /*InsnID*/1, 1382 GIM_CheckIsSafeToFold, /*InsnID*/2, 1383 // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, immAllOnesV:{ *:[v4i32] })) => (VANDC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 1384 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VANDC, 1385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 1386 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vA 1387 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB 1388 GIR_EraseFromParent, /*InsnID*/0, 1389 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1390 // GIR_Coverage, 308, 1391 GIR_Done, 1392 // Label 179: @2054 1393 GIM_Try, /*On fail goto*//*Label 180*/ 2069, // Rule ID 307 // 1394 GIM_CheckFeatures, GIFBS_HasAltivec, 1395 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 1396 // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VAND:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 1397 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VAND, 1398 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1399 // GIR_Coverage, 307, 1400 GIR_Done, 1401 // Label 180: @2069 1402 GIM_Reject, 1403 // Label 174: @2070 1404 GIM_Reject, 1405 // Label 161: @2071 1406 GIM_Reject, 1407 // Label 8: @2072 1408 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 6, /*)*//*default:*//*Label 185*/ 2687, 1409 /*GILLT_s1*//*Label 181*/ 2084, 1410 /*GILLT_s32*//*Label 182*/ 2195, 1411 /*GILLT_s64*//*Label 183*/ 2306, 0, 0, 1412 /*GILLT_v4s32*//*Label 184*/ 2417, 1413 // Label 181: @2084 1414 GIM_Try, /*On fail goto*//*Label 186*/ 2194, 1415 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 1416 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1, 1417 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 1418 GIM_Try, /*On fail goto*//*Label 187*/ 2141, // Rule ID 4855 // 1419 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1420 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 1421 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, 1422 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, 1423 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 1424 GIM_CheckIsSafeToFold, /*InsnID*/1, 1425 // (or:{ *:[i1] } (xor:{ *:[i1] } i1:{ *:[i1] }:$CRB, -1:{ *:[i1] }), i1:{ *:[i1] }:$CRA) => (CRORC:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) 1426 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CRORC, 1427 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // CRD 1428 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // CRA 1429 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRB 1430 GIR_EraseFromParent, /*InsnID*/0, 1431 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1432 // GIR_Coverage, 4855, 1433 GIR_Done, 1434 // Label 187: @2141 1435 GIM_Try, /*On fail goto*//*Label 188*/ 2184, // Rule ID 180 // 1436 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1437 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 1438 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, 1439 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, 1440 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 1441 GIM_CheckIsSafeToFold, /*InsnID*/1, 1442 // (or:{ *:[i1] } i1:{ *:[i1] }:$CRA, (xor:{ *:[i1] } i1:{ *:[i1] }:$CRB, -1:{ *:[i1] })) => (CRORC:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) 1443 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CRORC, 1444 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // CRD 1445 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // CRA 1446 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRB 1447 GIR_EraseFromParent, /*InsnID*/0, 1448 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1449 // GIR_Coverage, 180, 1450 GIR_Done, 1451 // Label 188: @2184 1452 GIM_Try, /*On fail goto*//*Label 189*/ 2193, // Rule ID 174 // 1453 // (or:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) => (CROR:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) 1454 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::CROR, 1455 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1456 // GIR_Coverage, 174, 1457 GIR_Done, 1458 // Label 189: @2193 1459 GIM_Reject, 1460 // Label 186: @2194 1461 GIM_Reject, 1462 // Label 182: @2195 1463 GIM_Try, /*On fail goto*//*Label 190*/ 2305, 1464 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 1465 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 1466 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 1467 GIM_Try, /*On fail goto*//*Label 191*/ 2252, // Rule ID 4849 // 1468 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1469 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 1470 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1471 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1472 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 1473 GIM_CheckIsSafeToFold, /*InsnID*/1, 1474 // (or:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$rB, -1:{ *:[i32] }), i32:{ *:[i32] }:$rS) => (ORC:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB) 1475 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::ORC, 1476 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 1477 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rS 1478 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rB 1479 GIR_EraseFromParent, /*InsnID*/0, 1480 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1481 // GIR_Coverage, 4849, 1482 GIR_Done, 1483 // Label 191: @2252 1484 GIM_Try, /*On fail goto*//*Label 192*/ 2295, // Rule ID 123 // 1485 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1486 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 1487 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1488 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1489 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 1490 GIM_CheckIsSafeToFold, /*InsnID*/1, 1491 // (or:{ *:[i32] } i32:{ *:[i32] }:$rS, (xor:{ *:[i32] } i32:{ *:[i32] }:$rB, -1:{ *:[i32] })) => (ORC:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB) 1492 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::ORC, 1493 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 1494 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rS 1495 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rB 1496 GIR_EraseFromParent, /*InsnID*/0, 1497 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1498 // GIR_Coverage, 123, 1499 GIR_Done, 1500 // Label 192: @2295 1501 GIM_Try, /*On fail goto*//*Label 193*/ 2304, // Rule ID 121 // 1502 // (or:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB) => (OR:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB) 1503 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::OR, 1504 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1505 // GIR_Coverage, 121, 1506 GIR_Done, 1507 // Label 193: @2304 1508 GIM_Reject, 1509 // Label 190: @2305 1510 GIM_Reject, 1511 // Label 183: @2306 1512 GIM_Try, /*On fail goto*//*Label 194*/ 2416, 1513 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 1514 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 1515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 1516 GIM_Try, /*On fail goto*//*Label 195*/ 2363, // Rule ID 4862 // 1517 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1518 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 1519 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 1520 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 1521 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 1522 GIM_CheckIsSafeToFold, /*InsnID*/1, 1523 // (or:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$rB, -1:{ *:[i64] }), i64:{ *:[i64] }:$rS) => (ORC8:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) 1524 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::ORC8, 1525 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 1526 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rS 1527 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rB 1528 GIR_EraseFromParent, /*InsnID*/0, 1529 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1530 // GIR_Coverage, 4862, 1531 GIR_Done, 1532 // Label 195: @2363 1533 GIM_Try, /*On fail goto*//*Label 196*/ 2406, // Rule ID 642 // 1534 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1535 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 1536 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 1537 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 1538 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 1539 GIM_CheckIsSafeToFold, /*InsnID*/1, 1540 // (or:{ *:[i64] } i64:{ *:[i64] }:$rS, (xor:{ *:[i64] } i64:{ *:[i64] }:$rB, -1:{ *:[i64] })) => (ORC8:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) 1541 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::ORC8, 1542 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 1543 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rS 1544 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rB 1545 GIR_EraseFromParent, /*InsnID*/0, 1546 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1547 // GIR_Coverage, 642, 1548 GIR_Done, 1549 // Label 196: @2406 1550 GIM_Try, /*On fail goto*//*Label 197*/ 2415, // Rule ID 640 // 1551 // (or:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) => (OR8:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) 1552 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::OR8, 1553 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1554 // GIR_Coverage, 640, 1555 GIR_Done, 1556 // Label 197: @2415 1557 GIM_Reject, 1558 // Label 194: @2416 1559 GIM_Reject, 1560 // Label 184: @2417 1561 GIM_Try, /*On fail goto*//*Label 198*/ 2686, 1562 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 1563 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 1564 GIM_Try, /*On fail goto*//*Label 199*/ 2484, // Rule ID 4872 // 1565 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 1566 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 1567 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1568 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 1569 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 1570 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 1571 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1572 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 1573 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 1574 GIM_CheckIsSafeToFold, /*InsnID*/1, 1575 GIM_CheckIsSafeToFold, /*InsnID*/2, 1576 // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$XA) => (XXLORC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) 1577 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XXLORC, 1578 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 1579 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XA 1580 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB 1581 GIR_EraseFromParent, /*InsnID*/0, 1582 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1583 // GIR_Coverage, 4872, 1584 GIR_Done, 1585 // Label 199: @2484 1586 GIM_Try, /*On fail goto*//*Label 200*/ 2541, // Rule ID 934 // 1587 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 1588 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 1589 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1590 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 1591 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 1592 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 1593 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1594 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 1595 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 1596 GIM_CheckIsSafeToFold, /*InsnID*/1, 1597 GIM_CheckIsSafeToFold, /*InsnID*/2, 1598 // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB, immAllOnesV:{ *:[v4i32] })) => (XXLORC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) 1599 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XXLORC, 1600 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 1601 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // XA 1602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB 1603 GIR_EraseFromParent, /*InsnID*/0, 1604 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1605 // GIR_Coverage, 934, 1606 GIR_Done, 1607 // Label 200: @2541 1608 GIM_Try, /*On fail goto*//*Label 201*/ 2556, // Rule ID 923 // 1609 GIM_CheckFeatures, GIFBS_HasVSX, 1610 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 1611 // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) => (XXLOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) 1612 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XXLOR, 1613 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1614 // GIR_Coverage, 923, 1615 GIR_Done, 1616 // Label 201: @2556 1617 GIM_Try, /*On fail goto*//*Label 202*/ 2613, // Rule ID 4860 // 1618 GIM_CheckFeatures, GIFBS_HasP8Altivec, 1619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 1620 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1621 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 1622 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 1623 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 1624 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1625 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 1626 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 1627 GIM_CheckIsSafeToFold, /*InsnID*/1, 1628 GIM_CheckIsSafeToFold, /*InsnID*/2, 1629 // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$vA) => (VORC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 1630 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VORC, 1631 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 1632 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 1633 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB 1634 GIR_EraseFromParent, /*InsnID*/0, 1635 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1636 // GIR_Coverage, 4860, 1637 GIR_Done, 1638 // Label 202: @2613 1639 GIM_Try, /*On fail goto*//*Label 203*/ 2670, // Rule ID 485 // 1640 GIM_CheckFeatures, GIFBS_HasP8Altivec, 1641 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 1642 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1643 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 1644 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 1645 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 1646 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1647 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 1648 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 1649 GIM_CheckIsSafeToFold, /*InsnID*/1, 1650 GIM_CheckIsSafeToFold, /*InsnID*/2, 1651 // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, immAllOnesV:{ *:[v4i32] })) => (VORC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 1652 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VORC, 1653 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 1654 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vA 1655 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB 1656 GIR_EraseFromParent, /*InsnID*/0, 1657 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1658 // GIR_Coverage, 485, 1659 GIR_Done, 1660 // Label 203: @2670 1661 GIM_Try, /*On fail goto*//*Label 204*/ 2685, // Rule ID 382 // 1662 GIM_CheckFeatures, GIFBS_HasAltivec, 1663 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 1664 // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 1665 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VOR, 1666 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1667 // GIR_Coverage, 382, 1668 GIR_Done, 1669 // Label 204: @2685 1670 GIM_Reject, 1671 // Label 198: @2686 1672 GIM_Reject, 1673 // Label 185: @2687 1674 GIM_Reject, 1675 // Label 9: @2688 1676 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 6, /*)*//*default:*//*Label 209*/ 4990, 1677 /*GILLT_s1*//*Label 205*/ 2700, 1678 /*GILLT_s32*//*Label 206*/ 3898, 1679 /*GILLT_s64*//*Label 207*/ 4138, 0, 0, 1680 /*GILLT_v4s32*//*Label 208*/ 4378, 1681 // Label 205: @2700 1682 GIM_Try, /*On fail goto*//*Label 210*/ 3897, 1683 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 1684 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1, 1685 GIM_Try, /*On fail goto*//*Label 211*/ 2786, // Rule ID 3955 // 1686 GIM_CheckFeatures, GIFBS_HasFPU, 1687 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 1688 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1689 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 1690 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1691 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 1692 // MIs[1] Operand 1 1693 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 1694 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 1695 GIM_CheckIsSafeToFold, /*InsnID*/1, 1696 // (xor:{ *:[i1] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }) 1697 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 1698 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::FCMPUS, 1699 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 1700 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1 1701 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2 1702 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 1703 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 1704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1705 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_lt, 1706 GIR_EraseFromParent, /*InsnID*/0, 1707 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 1708 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 1709 // GIR_Coverage, 3955, 1710 GIR_Done, 1711 // Label 211: @2786 1712 GIM_Try, /*On fail goto*//*Label 212*/ 2862, // Rule ID 3987 // 1713 GIM_CheckFeatures, GIFBS_HasFPU, 1714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 1715 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1716 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 1717 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1718 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 1719 // MIs[1] Operand 1 1720 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 1721 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 1722 GIM_CheckIsSafeToFold, /*InsnID*/1, 1723 // (xor:{ *:[i1] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }) 1724 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 1725 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::FCMPUS, 1726 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 1727 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1 1728 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2 1729 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 1730 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 1731 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1732 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_gt, 1733 GIR_EraseFromParent, /*InsnID*/0, 1734 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 1735 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 1736 // GIR_Coverage, 3987, 1737 GIR_Done, 1738 // Label 212: @2862 1739 GIM_Try, /*On fail goto*//*Label 213*/ 2938, // Rule ID 4019 // 1740 GIM_CheckFeatures, GIFBS_HasFPU, 1741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 1742 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1743 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 1744 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1745 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 1746 // MIs[1] Operand 1 1747 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 1748 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 1749 GIM_CheckIsSafeToFold, /*InsnID*/1, 1750 // (xor:{ *:[i1] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }) 1751 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 1752 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::FCMPUS, 1753 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 1754 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1 1755 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2 1756 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 1757 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 1758 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1759 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_eq, 1760 GIR_EraseFromParent, /*InsnID*/0, 1761 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 1762 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 1763 // GIR_Coverage, 4019, 1764 GIR_Done, 1765 // Label 213: @2938 1766 GIM_Try, /*On fail goto*//*Label 214*/ 3014, // Rule ID 4051 // 1767 GIM_CheckFeatures, GIFBS_HasFPU, 1768 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 1769 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1770 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 1771 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1772 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 1773 // MIs[1] Operand 1 1774 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 1775 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 1776 GIM_CheckIsSafeToFold, /*InsnID*/1, 1777 // (xor:{ *:[i1] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_un:{ *:[i32] }) 1778 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 1779 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::FCMPUS, 1780 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 1781 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1 1782 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2 1783 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 1784 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 1785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1786 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_un, 1787 GIR_EraseFromParent, /*InsnID*/0, 1788 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 1789 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 1790 // GIR_Coverage, 4051, 1791 GIR_Done, 1792 // Label 214: @3014 1793 GIM_Try, /*On fail goto*//*Label 215*/ 3090, // Rule ID 4067 // 1794 GIM_CheckFeatures, GIFBS_HasFPU, 1795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 1796 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1797 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 1798 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 1799 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 1800 // MIs[1] Operand 1 1801 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 1802 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 1803 GIM_CheckIsSafeToFold, /*InsnID*/1, 1804 // (xor:{ *:[i1] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }) 1805 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 1806 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::FCMPUD, 1807 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 1808 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1 1809 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2 1810 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 1811 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 1812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1813 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_lt, 1814 GIR_EraseFromParent, /*InsnID*/0, 1815 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 1816 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 1817 // GIR_Coverage, 4067, 1818 GIR_Done, 1819 // Label 215: @3090 1820 GIM_Try, /*On fail goto*//*Label 216*/ 3166, // Rule ID 4099 // 1821 GIM_CheckFeatures, GIFBS_HasFPU, 1822 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 1823 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1824 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 1825 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 1826 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 1827 // MIs[1] Operand 1 1828 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 1829 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 1830 GIM_CheckIsSafeToFold, /*InsnID*/1, 1831 // (xor:{ *:[i1] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }) 1832 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 1833 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::FCMPUD, 1834 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 1835 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1 1836 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2 1837 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 1838 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 1839 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1840 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_gt, 1841 GIR_EraseFromParent, /*InsnID*/0, 1842 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 1843 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 1844 // GIR_Coverage, 4099, 1845 GIR_Done, 1846 // Label 216: @3166 1847 GIM_Try, /*On fail goto*//*Label 217*/ 3242, // Rule ID 4131 // 1848 GIM_CheckFeatures, GIFBS_HasFPU, 1849 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 1850 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1851 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 1852 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 1853 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 1854 // MIs[1] Operand 1 1855 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 1856 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 1857 GIM_CheckIsSafeToFold, /*InsnID*/1, 1858 // (xor:{ *:[i1] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }) 1859 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 1860 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::FCMPUD, 1861 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 1862 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1 1863 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2 1864 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 1865 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 1866 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1867 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_eq, 1868 GIR_EraseFromParent, /*InsnID*/0, 1869 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 1870 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 1871 // GIR_Coverage, 4131, 1872 GIR_Done, 1873 // Label 217: @3242 1874 GIM_Try, /*On fail goto*//*Label 218*/ 3318, // Rule ID 4163 // 1875 GIM_CheckFeatures, GIFBS_HasFPU, 1876 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 1877 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1878 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 1879 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 1880 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 1881 // MIs[1] Operand 1 1882 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 1883 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 1884 GIM_CheckIsSafeToFold, /*InsnID*/1, 1885 // (xor:{ *:[i1] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_un:{ *:[i32] }) 1886 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 1887 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::FCMPUD, 1888 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 1889 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1 1890 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2 1891 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 1892 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 1893 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1894 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_un, 1895 GIR_EraseFromParent, /*InsnID*/0, 1896 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 1897 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 1898 // GIR_Coverage, 4163, 1899 GIR_Done, 1900 // Label 218: @3318 1901 GIM_Try, /*On fail goto*//*Label 219*/ 3394, // Rule ID 4193 // 1902 GIM_CheckFeatures, GIFBS_HasFPU, 1903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 1904 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1905 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 1906 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 1907 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 1908 // MIs[1] Operand 1 1909 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 1910 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 1911 GIM_CheckIsSafeToFold, /*InsnID*/1, 1912 // (xor:{ *:[i1] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }) 1913 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 1914 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::XSCMPUQP, 1915 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 1916 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1 1917 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2 1918 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 1919 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 1920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1921 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_lt, 1922 GIR_EraseFromParent, /*InsnID*/0, 1923 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 1924 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 1925 // GIR_Coverage, 4193, 1926 GIR_Done, 1927 // Label 219: @3394 1928 GIM_Try, /*On fail goto*//*Label 220*/ 3470, // Rule ID 4225 // 1929 GIM_CheckFeatures, GIFBS_HasFPU, 1930 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 1931 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1932 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 1933 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 1934 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 1935 // MIs[1] Operand 1 1936 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 1937 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 1938 GIM_CheckIsSafeToFold, /*InsnID*/1, 1939 // (xor:{ *:[i1] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }) 1940 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 1941 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::XSCMPUQP, 1942 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 1943 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1 1944 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2 1945 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 1946 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 1947 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1948 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_gt, 1949 GIR_EraseFromParent, /*InsnID*/0, 1950 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 1951 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 1952 // GIR_Coverage, 4225, 1953 GIR_Done, 1954 // Label 220: @3470 1955 GIM_Try, /*On fail goto*//*Label 221*/ 3546, // Rule ID 4257 // 1956 GIM_CheckFeatures, GIFBS_HasFPU, 1957 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 1958 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1959 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 1960 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 1961 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 1962 // MIs[1] Operand 1 1963 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 1964 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 1965 GIM_CheckIsSafeToFold, /*InsnID*/1, 1966 // (xor:{ *:[i1] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }) 1967 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 1968 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::XSCMPUQP, 1969 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 1970 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1 1971 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2 1972 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 1973 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 1974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1975 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_eq, 1976 GIR_EraseFromParent, /*InsnID*/0, 1977 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 1978 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 1979 // GIR_Coverage, 4257, 1980 GIR_Done, 1981 // Label 221: @3546 1982 GIM_Try, /*On fail goto*//*Label 222*/ 3622, // Rule ID 4289 // 1983 GIM_CheckFeatures, GIFBS_HasFPU, 1984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 1985 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1986 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 1987 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 1988 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 1989 // MIs[1] Operand 1 1990 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 1991 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 1992 GIM_CheckIsSafeToFold, /*InsnID*/1, 1993 // (xor:{ *:[i1] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_un:{ *:[i32] }) 1994 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 1995 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::XSCMPUQP, 1996 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 1997 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1 1998 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2 1999 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 2000 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2001 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2002 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_un, 2003 GIR_EraseFromParent, /*InsnID*/0, 2004 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 2005 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 2006 // GIR_Coverage, 4289, 2007 GIR_Done, 2008 // Label 222: @3622 2009 GIM_Try, /*On fail goto*//*Label 223*/ 3669, // Rule ID 173 // 2010 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 2011 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2012 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, 2013 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, 2014 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, 2015 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 2016 GIM_CheckIsSafeToFold, /*InsnID*/1, 2017 // (xor:{ *:[i1] } (and:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB), -1:{ *:[i1] }) => (CRNAND:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) 2018 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CRNAND, 2019 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // CRD 2020 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRA 2021 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // CRB 2022 GIR_EraseFromParent, /*InsnID*/0, 2023 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2024 // GIR_Coverage, 173, 2025 GIR_Done, 2026 // Label 223: @3669 2027 GIM_Try, /*On fail goto*//*Label 224*/ 3716, // Rule ID 176 // 2028 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 2029 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2030 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, 2031 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, 2032 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, 2033 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 2034 GIM_CheckIsSafeToFold, /*InsnID*/1, 2035 // (xor:{ *:[i1] } (or:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB), -1:{ *:[i1] }) => (CRNOR:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) 2036 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CRNOR, 2037 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // CRD 2038 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRA 2039 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // CRB 2040 GIR_EraseFromParent, /*InsnID*/0, 2041 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2042 // GIR_Coverage, 176, 2043 GIR_Done, 2044 // Label 224: @3716 2045 GIM_Try, /*On fail goto*//*Label 225*/ 3763, // Rule ID 4852 // 2046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 2047 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2048 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 2049 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, 2050 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, 2051 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 2052 GIM_CheckIsSafeToFold, /*InsnID*/1, 2053 // (xor:{ *:[i1] } (xor:{ *:[i1] } i1:{ *:[i1] }:$CRA, -1:{ *:[i1] }), i1:{ *:[i1] }:$CRB) => (CREQV:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) 2054 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CREQV, 2055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // CRD 2056 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRA 2057 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // CRB 2058 GIR_EraseFromParent, /*InsnID*/0, 2059 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2060 // GIR_Coverage, 4852, 2061 GIR_Done, 2062 // Label 225: @3763 2063 GIM_Try, /*On fail goto*//*Label 226*/ 3810, // Rule ID 177 // 2064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 2065 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2066 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 2067 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, 2068 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, 2069 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 2070 GIM_CheckIsSafeToFold, /*InsnID*/1, 2071 // (xor:{ *:[i1] } (xor:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB), -1:{ *:[i1] }) => (CREQV:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) 2072 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CREQV, 2073 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // CRD 2074 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRA 2075 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // CRB 2076 GIR_EraseFromParent, /*InsnID*/0, 2077 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2078 // GIR_Coverage, 177, 2079 GIR_Done, 2080 // Label 226: @3810 2081 GIM_Try, /*On fail goto*//*Label 227*/ 3857, // Rule ID 4853 // 2082 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 2083 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2084 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 2085 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, 2086 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, 2087 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 2088 GIM_CheckIsSafeToFold, /*InsnID*/1, 2089 // (xor:{ *:[i1] } i1:{ *:[i1] }:$CRB, (xor:{ *:[i1] } i1:{ *:[i1] }:$CRA, -1:{ *:[i1] })) => (CREQV:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) 2090 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CREQV, 2091 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // CRD 2092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRA 2093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // CRB 2094 GIR_EraseFromParent, /*InsnID*/0, 2095 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2096 // GIR_Coverage, 4853, 2097 GIR_Done, 2098 // Label 227: @3857 2099 GIM_Try, /*On fail goto*//*Label 228*/ 3883, // Rule ID 178 // 2100 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 2101 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 2102 // (xor:{ *:[i1] } i1:{ *:[i1] }:$CRA, -1:{ *:[i1] }) => (CRNOT:{ *:[i1] } i1:{ *:[i1] }:$CRA) 2103 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CRNOT, 2104 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // CRD 2105 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // CRA 2106 GIR_EraseFromParent, /*InsnID*/0, 2107 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2108 // GIR_Coverage, 178, 2109 GIR_Done, 2110 // Label 228: @3883 2111 GIM_Try, /*On fail goto*//*Label 229*/ 3896, // Rule ID 175 // 2112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 2113 // (xor:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) => (CRXOR:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) 2114 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::CRXOR, 2115 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2116 // GIR_Coverage, 175, 2117 GIR_Done, 2118 // Label 229: @3896 2119 GIM_Reject, 2120 // Label 210: @3897 2121 GIM_Reject, 2122 // Label 206: @3898 2123 GIM_Try, /*On fail goto*//*Label 230*/ 4137, 2124 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 2125 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 2126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 2127 GIM_Try, /*On fail goto*//*Label 231*/ 3955, // Rule ID 118 // 2128 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2129 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, 2130 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 2131 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 2132 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 2133 GIM_CheckIsSafeToFold, /*InsnID*/1, 2134 // (xor:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB), -1:{ *:[i32] }) => (NAND:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB) 2135 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::NAND, 2136 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 2137 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rS 2138 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rB 2139 GIR_EraseFromParent, /*InsnID*/0, 2140 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2141 // GIR_Coverage, 118, 2142 GIR_Done, 2143 // Label 231: @3955 2144 GIM_Try, /*On fail goto*//*Label 232*/ 3998, // Rule ID 122 // 2145 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2146 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, 2147 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 2148 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 2149 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 2150 GIM_CheckIsSafeToFold, /*InsnID*/1, 2151 // (xor:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB), -1:{ *:[i32] }) => (NOR:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB) 2152 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::NOR, 2153 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 2154 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rS 2155 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rB 2156 GIR_EraseFromParent, /*InsnID*/0, 2157 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2158 // GIR_Coverage, 122, 2159 GIR_Done, 2160 // Label 232: @3998 2161 GIM_Try, /*On fail goto*//*Label 233*/ 4041, // Rule ID 4850 // 2162 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2163 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 2164 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 2165 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 2166 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 2167 GIM_CheckIsSafeToFold, /*InsnID*/1, 2168 // (xor:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$rS, -1:{ *:[i32] }), i32:{ *:[i32] }:$rB) => (EQV:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB) 2169 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::EQV, 2170 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 2171 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rS 2172 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rB 2173 GIR_EraseFromParent, /*InsnID*/0, 2174 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2175 // GIR_Coverage, 4850, 2176 GIR_Done, 2177 // Label 233: @4041 2178 GIM_Try, /*On fail goto*//*Label 234*/ 4084, // Rule ID 124 // 2179 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2180 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 2181 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 2182 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 2183 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 2184 GIM_CheckIsSafeToFold, /*InsnID*/1, 2185 // (xor:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB), -1:{ *:[i32] }) => (EQV:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB) 2186 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::EQV, 2187 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 2188 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rS 2189 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rB 2190 GIR_EraseFromParent, /*InsnID*/0, 2191 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2192 // GIR_Coverage, 124, 2193 GIR_Done, 2194 // Label 234: @4084 2195 GIM_Try, /*On fail goto*//*Label 235*/ 4127, // Rule ID 4851 // 2196 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2197 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 2198 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 2199 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 2200 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 2201 GIM_CheckIsSafeToFold, /*InsnID*/1, 2202 // (xor:{ *:[i32] } i32:{ *:[i32] }:$rB, (xor:{ *:[i32] } i32:{ *:[i32] }:$rS, -1:{ *:[i32] })) => (EQV:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB) 2203 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::EQV, 2204 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 2205 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rS 2206 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rB 2207 GIR_EraseFromParent, /*InsnID*/0, 2208 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2209 // GIR_Coverage, 4851, 2210 GIR_Done, 2211 // Label 235: @4127 2212 GIM_Try, /*On fail goto*//*Label 236*/ 4136, // Rule ID 125 // 2213 // (xor:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB) => (XOR:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB) 2214 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XOR, 2215 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2216 // GIR_Coverage, 125, 2217 GIR_Done, 2218 // Label 236: @4136 2219 GIM_Reject, 2220 // Label 230: @4137 2221 GIM_Reject, 2222 // Label 207: @4138 2223 GIM_Try, /*On fail goto*//*Label 237*/ 4377, 2224 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 2225 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 2226 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 2227 GIM_Try, /*On fail goto*//*Label 238*/ 4195, // Rule ID 637 // 2228 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2229 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, 2230 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 2231 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 2232 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 2233 GIM_CheckIsSafeToFold, /*InsnID*/1, 2234 // (xor:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB), -1:{ *:[i64] }) => (NAND8:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) 2235 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::NAND8, 2236 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 2237 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rS 2238 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rB 2239 GIR_EraseFromParent, /*InsnID*/0, 2240 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2241 // GIR_Coverage, 637, 2242 GIR_Done, 2243 // Label 238: @4195 2244 GIM_Try, /*On fail goto*//*Label 239*/ 4238, // Rule ID 641 // 2245 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2246 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, 2247 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 2248 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 2249 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 2250 GIM_CheckIsSafeToFold, /*InsnID*/1, 2251 // (xor:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB), -1:{ *:[i64] }) => (NOR8:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) 2252 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::NOR8, 2253 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 2254 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rS 2255 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rB 2256 GIR_EraseFromParent, /*InsnID*/0, 2257 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2258 // GIR_Coverage, 641, 2259 GIR_Done, 2260 // Label 239: @4238 2261 GIM_Try, /*On fail goto*//*Label 240*/ 4281, // Rule ID 4863 // 2262 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2263 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 2264 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 2265 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 2266 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 2267 GIM_CheckIsSafeToFold, /*InsnID*/1, 2268 // (xor:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$rS, -1:{ *:[i64] }), i64:{ *:[i64] }:$rB) => (EQV8:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) 2269 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::EQV8, 2270 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 2271 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rS 2272 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rB 2273 GIR_EraseFromParent, /*InsnID*/0, 2274 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2275 // GIR_Coverage, 4863, 2276 GIR_Done, 2277 // Label 240: @4281 2278 GIM_Try, /*On fail goto*//*Label 241*/ 4324, // Rule ID 643 // 2279 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2280 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 2281 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 2282 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 2283 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 2284 GIM_CheckIsSafeToFold, /*InsnID*/1, 2285 // (xor:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB), -1:{ *:[i64] }) => (EQV8:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) 2286 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::EQV8, 2287 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 2288 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rS 2289 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rB 2290 GIR_EraseFromParent, /*InsnID*/0, 2291 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2292 // GIR_Coverage, 643, 2293 GIR_Done, 2294 // Label 241: @4324 2295 GIM_Try, /*On fail goto*//*Label 242*/ 4367, // Rule ID 4864 // 2296 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2297 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 2298 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 2299 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 2300 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 2301 GIM_CheckIsSafeToFold, /*InsnID*/1, 2302 // (xor:{ *:[i64] } i64:{ *:[i64] }:$rB, (xor:{ *:[i64] } i64:{ *:[i64] }:$rS, -1:{ *:[i64] })) => (EQV8:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) 2303 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::EQV8, 2304 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 2305 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rS 2306 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rB 2307 GIR_EraseFromParent, /*InsnID*/0, 2308 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2309 // GIR_Coverage, 4864, 2310 GIR_Done, 2311 // Label 242: @4367 2312 GIM_Try, /*On fail goto*//*Label 243*/ 4376, // Rule ID 644 // 2313 // (xor:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) => (XOR8:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) 2314 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XOR8, 2315 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2316 // GIR_Coverage, 644, 2317 GIR_Done, 2318 // Label 243: @4376 2319 GIM_Reject, 2320 // Label 237: @4377 2321 GIM_Reject, 2322 // Label 208: @4378 2323 GIM_Try, /*On fail goto*//*Label 244*/ 4989, 2324 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 2325 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 2326 GIM_Try, /*On fail goto*//*Label 245*/ 4445, // Rule ID 932 // 2327 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 2328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 2329 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2330 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, 2331 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 2332 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 2333 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 2334 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 2335 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 2336 GIM_CheckIsSafeToFold, /*InsnID*/1, 2337 GIM_CheckIsSafeToFold, /*InsnID*/2, 2338 // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB), immAllOnesV:{ *:[v4i32] }) => (XXLNAND:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) 2339 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XXLNAND, 2340 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 2341 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA 2342 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB 2343 GIR_EraseFromParent, /*InsnID*/0, 2344 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2345 // GIR_Coverage, 932, 2346 GIR_Done, 2347 // Label 245: @4445 2348 GIM_Try, /*On fail goto*//*Label 246*/ 4502, // Rule ID 922 // 2349 GIM_CheckFeatures, GIFBS_HasVSX, 2350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 2351 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2352 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, 2353 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 2354 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 2355 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 2356 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 2357 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 2358 GIM_CheckIsSafeToFold, /*InsnID*/1, 2359 GIM_CheckIsSafeToFold, /*InsnID*/2, 2360 // (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB), immAllOnesV:{ *:[v4i32] }) => (XXLNOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) 2361 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XXLNOR, 2362 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 2363 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA 2364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB 2365 GIR_EraseFromParent, /*InsnID*/0, 2366 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2367 // GIR_Coverage, 922, 2368 GIR_Done, 2369 // Label 246: @4502 2370 GIM_Try, /*On fail goto*//*Label 247*/ 4559, // Rule ID 4870 // 2371 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 2372 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 2373 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2374 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 2375 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 2376 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 2377 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 2378 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 2379 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 2380 GIM_CheckIsSafeToFold, /*InsnID*/1, 2381 GIM_CheckIsSafeToFold, /*InsnID*/2, 2382 // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$XB) => (XXLEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) 2383 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XXLEQV, 2384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 2385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA 2386 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 2387 GIR_EraseFromParent, /*InsnID*/0, 2388 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2389 // GIR_Coverage, 4870, 2390 GIR_Done, 2391 // Label 247: @4559 2392 GIM_Try, /*On fail goto*//*Label 248*/ 4616, // Rule ID 931 // 2393 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 2394 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 2395 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2396 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 2397 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 2398 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 2399 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 2400 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 2401 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 2402 GIM_CheckIsSafeToFold, /*InsnID*/1, 2403 GIM_CheckIsSafeToFold, /*InsnID*/2, 2404 // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB), immAllOnesV:{ *:[v4i32] }) => (XXLEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) 2405 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XXLEQV, 2406 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 2407 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA 2408 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB 2409 GIR_EraseFromParent, /*InsnID*/0, 2410 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2411 // GIR_Coverage, 931, 2412 GIR_Done, 2413 // Label 248: @4616 2414 GIM_Try, /*On fail goto*//*Label 249*/ 4673, // Rule ID 4871 // 2415 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 2416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 2417 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2418 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 2419 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 2420 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 2421 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 2422 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 2423 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 2424 GIM_CheckIsSafeToFold, /*InsnID*/1, 2425 GIM_CheckIsSafeToFold, /*InsnID*/2, 2426 // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, immAllOnesV:{ *:[v4i32] })) => (XXLEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) 2427 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XXLEQV, 2428 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 2429 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA 2430 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // XB 2431 GIR_EraseFromParent, /*InsnID*/0, 2432 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2433 // GIR_Coverage, 4871, 2434 GIR_Done, 2435 // Label 249: @4673 2436 GIM_Try, /*On fail goto*//*Label 250*/ 4688, // Rule ID 924 // 2437 GIM_CheckFeatures, GIFBS_HasVSX, 2438 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 2439 // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) => (XXLXOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) 2440 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XXLXOR, 2441 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2442 // GIR_Coverage, 924, 2443 GIR_Done, 2444 // Label 250: @4688 2445 GIM_Try, /*On fail goto*//*Label 251*/ 4745, // Rule ID 484 // 2446 GIM_CheckFeatures, GIFBS_HasP8Altivec, 2447 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2448 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2449 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, 2450 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 2451 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 2452 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 2453 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 2454 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 2455 GIM_CheckIsSafeToFold, /*InsnID*/1, 2456 GIM_CheckIsSafeToFold, /*InsnID*/2, 2457 // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }) => (VNAND:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 2458 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VNAND, 2459 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 2460 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA 2461 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB 2462 GIR_EraseFromParent, /*InsnID*/0, 2463 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2464 // GIR_Coverage, 484, 2465 GIR_Done, 2466 // Label 251: @4745 2467 GIM_Try, /*On fail goto*//*Label 252*/ 4802, // Rule ID 381 // 2468 GIM_CheckFeatures, GIFBS_HasAltivec, 2469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2470 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2471 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, 2472 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 2473 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 2474 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 2475 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 2476 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 2477 GIM_CheckIsSafeToFold, /*InsnID*/1, 2478 GIM_CheckIsSafeToFold, /*InsnID*/2, 2479 // (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }) => (VNOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 2480 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VNOR, 2481 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 2482 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA 2483 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB 2484 GIR_EraseFromParent, /*InsnID*/0, 2485 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2486 // GIR_Coverage, 381, 2487 GIR_Done, 2488 // Label 252: @4802 2489 GIM_Try, /*On fail goto*//*Label 253*/ 4859, // Rule ID 4858 // 2490 GIM_CheckFeatures, GIFBS_HasP8Altivec, 2491 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2492 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2493 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 2494 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 2495 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 2496 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 2497 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 2498 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 2499 GIM_CheckIsSafeToFold, /*InsnID*/1, 2500 GIM_CheckIsSafeToFold, /*InsnID*/2, 2501 // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$vB) => (VEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 2502 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEQV, 2503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 2504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA 2505 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 2506 GIR_EraseFromParent, /*InsnID*/0, 2507 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2508 // GIR_Coverage, 4858, 2509 GIR_Done, 2510 // Label 253: @4859 2511 GIM_Try, /*On fail goto*//*Label 254*/ 4916, // Rule ID 483 // 2512 GIM_CheckFeatures, GIFBS_HasP8Altivec, 2513 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2514 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2515 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 2516 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 2517 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 2518 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 2519 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 2520 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 2521 GIM_CheckIsSafeToFold, /*InsnID*/1, 2522 GIM_CheckIsSafeToFold, /*InsnID*/2, 2523 // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }) => (VEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 2524 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEQV, 2525 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 2526 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA 2527 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB 2528 GIR_EraseFromParent, /*InsnID*/0, 2529 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2530 // GIR_Coverage, 483, 2531 GIR_Done, 2532 // Label 254: @4916 2533 GIM_Try, /*On fail goto*//*Label 255*/ 4973, // Rule ID 4859 // 2534 GIM_CheckFeatures, GIFBS_HasP8Altivec, 2535 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2536 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2537 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 2538 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 2539 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 2540 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 2541 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 2542 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 2543 GIM_CheckIsSafeToFold, /*InsnID*/1, 2544 GIM_CheckIsSafeToFold, /*InsnID*/2, 2545 // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] })) => (VEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 2546 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEQV, 2547 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 2548 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA 2549 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vB 2550 GIR_EraseFromParent, /*InsnID*/0, 2551 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2552 // GIR_Coverage, 4859, 2553 GIR_Done, 2554 // Label 255: @4973 2555 GIM_Try, /*On fail goto*//*Label 256*/ 4988, // Rule ID 383 // 2556 GIM_CheckFeatures, GIFBS_HasAltivec, 2557 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2558 // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VXOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 2559 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VXOR, 2560 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2561 // GIR_Coverage, 383, 2562 GIR_Done, 2563 // Label 256: @4988 2564 GIM_Reject, 2565 // Label 244: @4989 2566 GIM_Reject, 2567 // Label 209: @4990 2568 GIM_Reject, 2569 // Label 10: @4991 2570 GIM_Try, /*On fail goto*//*Label 257*/ 5243, 2571 GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, 2572 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 2573 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 2574 GIM_Try, /*On fail goto*//*Label 258*/ 5054, // Rule ID 2001 // 2575 GIM_CheckFeatures, GIFBS_HasDirectMove_HasVSX, 2576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2577 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2578 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 2579 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExt5NonZero, 2580 // MIs[1] Operand 1 2581 // No operand predicates 2582 // MIs[0] A 2583 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, 2584 // MIs[0] A 2585 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, 2586 // MIs[0] A 2587 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, 2588 GIM_CheckIsSafeToFold, /*InsnID*/1, 2589 // (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immSExt5NonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_immSExt5NonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_immSExt5NonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_immSExt5NonZero>>:$A) => (VSPLTISW:{ *:[v4i32] } (imm:{ *:[i32] }):$A) 2590 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSPLTISW, 2591 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 2592 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // A 2593 GIR_EraseFromParent, /*InsnID*/0, 2594 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2595 // GIR_Coverage, 2001, 2596 GIR_Done, 2597 // Label 258: @5054 2598 GIM_Try, /*On fail goto*//*Label 259*/ 5104, // Rule ID 3346 // 2599 GIM_CheckFeatures, GIFBS_PrefixInstrs, 2600 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 2601 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2602 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 2603 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immNonAllOneNonZero, 2604 // MIs[1] Operand 1 2605 // No operand predicates 2606 // MIs[0] A 2607 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, 2608 // MIs[0] A 2609 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, 2610 // MIs[0] A 2611 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, 2612 GIM_CheckIsSafeToFold, /*InsnID*/1, 2613 // (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_i32immNonAllOneNonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_i32immNonAllOneNonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_i32immNonAllOneNonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_i32immNonAllOneNonZero>>:$A) => (XXSPLTIW:{ *:[v4i32] } (imm:{ *:[i32] }):$A) 2614 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XXSPLTIW, 2615 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 2616 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // A 2617 GIR_EraseFromParent, /*InsnID*/0, 2618 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2619 // GIR_Coverage, 3346, 2620 GIR_Done, 2621 // Label 259: @5104 2622 GIM_Try, /*On fail goto*//*Label 260*/ 5242, // Rule ID 1701 // 2623 GIM_CheckFeatures, GIFBS_HasVSX, 2624 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 2625 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 2626 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 2627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 2628 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2629 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FPTRUNC, 2630 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 2631 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 2632 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FPTRUNC, 2633 // MIs[2] A 2634 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 2635 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3] 2636 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FPTRUNC, 2637 // MIs[3] A 2638 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 2639 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/4, // MIs[4] 2640 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_FPTRUNC, 2641 // MIs[4] A 2642 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 2643 GIM_CheckIsSafeToFold, /*InsnID*/1, 2644 GIM_CheckIsSafeToFold, /*InsnID*/2, 2645 GIM_CheckIsSafeToFold, /*InsnID*/3, 2646 GIM_CheckIsSafeToFold, /*InsnID*/4, 2647 // (build_vector:{ *:[v4f32] } (fpround:{ *:[f32] } f64:{ *:[f64] }:$A), (fpround:{ *:[f32] } f64:{ *:[f64] }:$A), (fpround:{ *:[f32] } f64:{ *:[f64] }:$A), (fpround:{ *:[f32] } f64:{ *:[f64] }:$A)) => (XXSPLTW:{ *:[v4f32] } (SUBREG_TO_REG:{ *:[v4i32] } 1:{ *:[i64] }, (XSCVDPSP:{ *:[f64] } f64:{ *:[f64] }:$A), sub_64:{ *:[i32] }), 0:{ *:[i32] }) 2648 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, 2649 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 2650 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCVDPSP, 2651 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 2652 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // A 2653 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 2654 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, 2655 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 2656 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 2657 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 2658 GIR_AddImm, /*InsnID*/1, /*Imm*/2, 2659 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::VSRCRegClassID, 2660 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, PPC::VSFRCRegClassID, 2661 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XXSPLTW, 2662 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 2663 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 2664 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2665 GIR_EraseFromParent, /*InsnID*/0, 2666 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2667 // GIR_Coverage, 1701, 2668 GIR_Done, 2669 // Label 260: @5242 2670 GIM_Reject, 2671 // Label 257: @5243 2672 GIM_Try, /*On fail goto*//*Label 261*/ 5382, // Rule ID 2236 // 2673 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 2674 GIM_CheckNumOperands, /*MI*/0, /*Expected*/17, 2675 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 2676 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 2677 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 2678 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2679 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 2680 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immNonAllOneAnyExt8, 2681 // MIs[1] Operand 1 2682 // No operand predicates 2683 // MIs[0] A 2684 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, 2685 // MIs[0] A 2686 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, 2687 // MIs[0] A 2688 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, 2689 // MIs[0] A 2690 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1, 2691 // MIs[0] A 2692 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1, 2693 // MIs[0] A 2694 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1, 2695 // MIs[0] A 2696 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1, 2697 // MIs[0] A 2698 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/9, /*OtherMI*/0, /*OtherOpIdx*/1, 2699 // MIs[0] A 2700 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/10, /*OtherMI*/0, /*OtherOpIdx*/1, 2701 // MIs[0] A 2702 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/11, /*OtherMI*/0, /*OtherOpIdx*/1, 2703 // MIs[0] A 2704 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/12, /*OtherMI*/0, /*OtherOpIdx*/1, 2705 // MIs[0] A 2706 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/13, /*OtherMI*/0, /*OtherOpIdx*/1, 2707 // MIs[0] A 2708 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/14, /*OtherMI*/0, /*OtherOpIdx*/1, 2709 // MIs[0] A 2710 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/15, /*OtherMI*/0, /*OtherOpIdx*/1, 2711 // MIs[0] A 2712 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/16, /*OtherMI*/0, /*OtherOpIdx*/1, 2713 GIM_CheckIsSafeToFold, /*InsnID*/1, 2714 // (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A) => (COPY_TO_REGCLASS:{ *:[v16i8] } (XXSPLTIB:{ *:[v4i32] } (imm:{ *:[i32] }):$A), VSRC:{ *:[i32] }) 2715 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, 2716 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::XXSPLTIB, 2717 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 2718 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // A 2719 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 2720 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2721 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2722 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 2723 GIR_EraseFromParent, /*InsnID*/0, 2724 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VSRCRegClassID, 2725 // GIR_Coverage, 2236, 2726 GIR_Done, 2727 // Label 261: @5382 2728 GIM_Reject, 2729 // Label 11: @5383 2730 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 8, /*)*//*default:*//*Label 267*/ 6957, 2731 /*GILLT_s128*//*Label 262*/ 5394, 2732 /*GILLT_v2s64*//*Label 263*/ 5789, 2733 /*GILLT_v4s32*//*Label 264*/ 6048, 2734 /*GILLT_v8s16*//*Label 265*/ 6493, 2735 /*GILLT_v16s8*//*Label 266*/ 6752, 2736 // Label 262: @5394 2737 GIM_Try, /*On fail goto*//*Label 268*/ 5448, // Rule ID 1893 // 2738 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 2739 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 2740 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 2741 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2742 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 2743 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 2744 GIM_CheckIsSafeToFold, /*InsnID*/1, 2745 // (bitconvert:{ *:[v1i128] } immAllOnesV:{ *:[v16i8] }) => (COPY_TO_REGCLASS:{ *:[v1i128] } (XXLEQVOnes:{ *:[v4i32] }), VSRC:{ *:[i32] }) 2746 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, 2747 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::XXLEQVOnes, 2748 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 2749 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 2750 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2751 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2752 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 2753 GIR_EraseFromParent, /*InsnID*/0, 2754 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VSRCRegClassID, 2755 // GIR_Coverage, 1893, 2756 GIR_Done, 2757 // Label 268: @5448 2758 GIM_Try, /*On fail goto*//*Label 269*/ 5482, // Rule ID 1305 // 2759 GIM_CheckFeatures, GIFBS_HasAltivec, 2760 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 2761 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2762 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 2763 // (bitconvert:{ *:[v1i128] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[v1i128] }:$src 2764 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2765 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2766 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 2767 GIR_EraseFromParent, /*InsnID*/0, 2768 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 2769 // GIR_Coverage, 1305, 2770 GIR_Done, 2771 // Label 269: @5482 2772 GIM_Try, /*On fail goto*//*Label 270*/ 5516, // Rule ID 1306 // 2773 GIM_CheckFeatures, GIFBS_HasAltivec, 2774 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 2775 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2776 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 2777 // (bitconvert:{ *:[v1i128] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[v1i128] }:$src 2778 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2779 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2780 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 2781 GIR_EraseFromParent, /*InsnID*/0, 2782 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 2783 // GIR_Coverage, 1306, 2784 GIR_Done, 2785 // Label 270: @5516 2786 GIM_Try, /*On fail goto*//*Label 271*/ 5550, // Rule ID 1307 // 2787 GIM_CheckFeatures, GIFBS_HasAltivec, 2788 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 2789 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2790 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 2791 // (bitconvert:{ *:[v1i128] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[v1i128] }:$src 2792 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2793 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2794 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 2795 GIR_EraseFromParent, /*InsnID*/0, 2796 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 2797 // GIR_Coverage, 1307, 2798 GIR_Done, 2799 // Label 271: @5550 2800 GIM_Try, /*On fail goto*//*Label 272*/ 5584, // Rule ID 1308 // 2801 GIM_CheckFeatures, GIFBS_HasAltivec, 2802 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 2803 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2804 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 2805 // (bitconvert:{ *:[v1i128] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[v1i128] }:$src 2806 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2808 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 2809 GIR_EraseFromParent, /*InsnID*/0, 2810 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 2811 // GIR_Coverage, 1308, 2812 GIR_Done, 2813 // Label 272: @5584 2814 GIM_Try, /*On fail goto*//*Label 273*/ 5618, // Rule ID 1309 // 2815 GIM_CheckFeatures, GIFBS_HasAltivec, 2816 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 2817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2818 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 2819 // (bitconvert:{ *:[v1i128] } VRRC:{ *:[v2i64] }:$src) => VRRC:{ *:[v1i128] }:$src 2820 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2821 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2822 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 2823 GIR_EraseFromParent, /*InsnID*/0, 2824 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 2825 // GIR_Coverage, 1309, 2826 GIR_Done, 2827 // Label 273: @5618 2828 GIM_Try, /*On fail goto*//*Label 274*/ 5652, // Rule ID 1310 // 2829 GIM_CheckFeatures, GIFBS_HasAltivec, 2830 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 2831 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2832 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 2833 // (bitconvert:{ *:[f128] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[f128] }:$src 2834 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2835 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2836 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 2837 GIR_EraseFromParent, /*InsnID*/0, 2838 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 2839 // GIR_Coverage, 1310, 2840 GIR_Done, 2841 // Label 274: @5652 2842 GIM_Try, /*On fail goto*//*Label 275*/ 5686, // Rule ID 1311 // 2843 GIM_CheckFeatures, GIFBS_HasAltivec, 2844 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 2845 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 2847 // (bitconvert:{ *:[f128] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[f128] }:$src 2848 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2849 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2850 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 2851 GIR_EraseFromParent, /*InsnID*/0, 2852 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 2853 // GIR_Coverage, 1311, 2854 GIR_Done, 2855 // Label 275: @5686 2856 GIM_Try, /*On fail goto*//*Label 276*/ 5720, // Rule ID 1312 // 2857 GIM_CheckFeatures, GIFBS_HasAltivec, 2858 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 2859 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 2861 // (bitconvert:{ *:[f128] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[f128] }:$src 2862 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2863 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2864 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 2865 GIR_EraseFromParent, /*InsnID*/0, 2866 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 2867 // GIR_Coverage, 1312, 2868 GIR_Done, 2869 // Label 276: @5720 2870 GIM_Try, /*On fail goto*//*Label 277*/ 5754, // Rule ID 1313 // 2871 GIM_CheckFeatures, GIFBS_HasAltivec, 2872 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 2873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2874 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 2875 // (bitconvert:{ *:[f128] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[f128] }:$src 2876 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2877 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 2879 GIR_EraseFromParent, /*InsnID*/0, 2880 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 2881 // GIR_Coverage, 1313, 2882 GIR_Done, 2883 // Label 277: @5754 2884 GIM_Try, /*On fail goto*//*Label 278*/ 5788, // Rule ID 1314 // 2885 GIM_CheckFeatures, GIFBS_HasAltivec, 2886 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 2887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2888 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 2889 // (bitconvert:{ *:[f128] } VRRC:{ *:[v2f64] }:$src) => VRRC:{ *:[f128] }:$src 2890 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2891 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2892 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 2893 GIR_EraseFromParent, /*InsnID*/0, 2894 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 2895 // GIR_Coverage, 1314, 2896 GIR_Done, 2897 // Label 278: @5788 2898 GIM_Reject, 2899 // Label 263: @5789 2900 GIM_Try, /*On fail goto*//*Label 279*/ 5843, // Rule ID 1894 // 2901 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 2902 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 2903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 2904 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2905 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 2906 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 2907 GIM_CheckIsSafeToFold, /*InsnID*/1, 2908 // (bitconvert:{ *:[v2i64] } immAllOnesV:{ *:[v16i8] }) => (COPY_TO_REGCLASS:{ *:[v2i64] } (XXLEQVOnes:{ *:[v4i32] }), VSRC:{ *:[i32] }) 2909 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, 2910 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::XXLEQVOnes, 2911 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 2912 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 2913 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2914 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2915 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 2916 GIR_EraseFromParent, /*InsnID*/0, 2917 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VSRCRegClassID, 2918 // GIR_Coverage, 1894, 2919 GIR_Done, 2920 // Label 279: @5843 2921 GIM_Try, /*On fail goto*//*Label 280*/ 5877, // Rule ID 1300 // 2922 GIM_CheckFeatures, GIFBS_HasAltivec, 2923 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 2924 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2925 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 2926 // (bitconvert:{ *:[v2i64] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[v2i64] }:$src 2927 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2928 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2929 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 2930 GIR_EraseFromParent, /*InsnID*/0, 2931 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 2932 // GIR_Coverage, 1300, 2933 GIR_Done, 2934 // Label 280: @5877 2935 GIM_Try, /*On fail goto*//*Label 281*/ 5911, // Rule ID 1301 // 2936 GIM_CheckFeatures, GIFBS_HasAltivec, 2937 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 2938 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2939 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 2940 // (bitconvert:{ *:[v2i64] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[v2i64] }:$src 2941 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2942 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2943 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 2944 GIR_EraseFromParent, /*InsnID*/0, 2945 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 2946 // GIR_Coverage, 1301, 2947 GIR_Done, 2948 // Label 281: @5911 2949 GIM_Try, /*On fail goto*//*Label 282*/ 5945, // Rule ID 1302 // 2950 GIM_CheckFeatures, GIFBS_HasAltivec, 2951 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 2952 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2953 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 2954 // (bitconvert:{ *:[v2i64] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[v2i64] }:$src 2955 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2956 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2957 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 2958 GIR_EraseFromParent, /*InsnID*/0, 2959 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 2960 // GIR_Coverage, 1302, 2961 GIR_Done, 2962 // Label 282: @5945 2963 GIM_Try, /*On fail goto*//*Label 283*/ 5979, // Rule ID 1303 // 2964 GIM_CheckFeatures, GIFBS_HasAltivec, 2965 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 2966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 2968 // (bitconvert:{ *:[v2i64] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[v2i64] }:$src 2969 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2970 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2971 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 2972 GIR_EraseFromParent, /*InsnID*/0, 2973 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 2974 // GIR_Coverage, 1303, 2975 GIR_Done, 2976 // Label 283: @5979 2977 GIM_Try, /*On fail goto*//*Label 284*/ 6013, // Rule ID 1304 // 2978 GIM_CheckFeatures, GIFBS_HasAltivec, 2979 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 2980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 2982 // (bitconvert:{ *:[v2i64] } VRRC:{ *:[v1i128] }:$src) => VRRC:{ *:[v2i64] }:$src 2983 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2984 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2985 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 2986 GIR_EraseFromParent, /*InsnID*/0, 2987 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 2988 // GIR_Coverage, 1304, 2989 GIR_Done, 2990 // Label 284: @6013 2991 GIM_Try, /*On fail goto*//*Label 285*/ 6047, // Rule ID 1319 // 2992 GIM_CheckFeatures, GIFBS_HasAltivec, 2993 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 2994 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 2995 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 2996 // (bitconvert:{ *:[v2f64] } VRRC:{ *:[f128] }:$src) => VRRC:{ *:[v2f64] }:$src 2997 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2998 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2999 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3000 GIR_EraseFromParent, /*InsnID*/0, 3001 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3002 // GIR_Coverage, 1319, 3003 GIR_Done, 3004 // Label 285: @6047 3005 GIM_Reject, 3006 // Label 264: @6048 3007 GIM_Try, /*On fail goto*//*Label 286*/ 6084, // Rule ID 933 // 3008 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 3009 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 3010 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 3011 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3012 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 3013 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 3014 GIM_CheckIsSafeToFold, /*InsnID*/1, 3015 // (bitconvert:{ *:[v4i32] } immAllOnesV:{ *:[v16i8] }) => (XXLEQVOnes:{ *:[v4i32] }) 3016 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XXLEQVOnes, 3017 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 3018 GIR_EraseFromParent, /*InsnID*/0, 3019 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3020 // GIR_Coverage, 933, 3021 GIR_Done, 3022 // Label 286: @6084 3023 GIM_Try, /*On fail goto*//*Label 287*/ 6118, // Rule ID 1290 // 3024 GIM_CheckFeatures, GIFBS_HasAltivec, 3025 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 3026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3027 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3028 // (bitconvert:{ *:[v4i32] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[v4i32] }:$src 3029 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3030 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3031 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3032 GIR_EraseFromParent, /*InsnID*/0, 3033 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3034 // GIR_Coverage, 1290, 3035 GIR_Done, 3036 // Label 287: @6118 3037 GIM_Try, /*On fail goto*//*Label 288*/ 6152, // Rule ID 1291 // 3038 GIM_CheckFeatures, GIFBS_HasAltivec, 3039 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 3040 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3041 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3042 // (bitconvert:{ *:[v4i32] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[v4i32] }:$src 3043 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3044 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3045 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3046 GIR_EraseFromParent, /*InsnID*/0, 3047 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3048 // GIR_Coverage, 1291, 3049 GIR_Done, 3050 // Label 288: @6152 3051 GIM_Try, /*On fail goto*//*Label 289*/ 6186, // Rule ID 1292 // 3052 GIM_CheckFeatures, GIFBS_HasAltivec, 3053 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 3054 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3055 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3056 // (bitconvert:{ *:[v4i32] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[v4i32] }:$src 3057 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3058 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3059 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3060 GIR_EraseFromParent, /*InsnID*/0, 3061 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3062 // GIR_Coverage, 1292, 3063 GIR_Done, 3064 // Label 289: @6186 3065 GIM_Try, /*On fail goto*//*Label 290*/ 6220, // Rule ID 1293 // 3066 GIM_CheckFeatures, GIFBS_HasAltivec, 3067 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 3068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3069 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3070 // (bitconvert:{ *:[v4i32] } VRRC:{ *:[v2i64] }:$src) => VRRC:{ *:[v4i32] }:$src 3071 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3072 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3073 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3074 GIR_EraseFromParent, /*InsnID*/0, 3075 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3076 // GIR_Coverage, 1293, 3077 GIR_Done, 3078 // Label 290: @6220 3079 GIM_Try, /*On fail goto*//*Label 291*/ 6254, // Rule ID 1294 // 3080 GIM_CheckFeatures, GIFBS_HasAltivec, 3081 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 3082 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3083 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3084 // (bitconvert:{ *:[v4i32] } VRRC:{ *:[v1i128] }:$src) => VRRC:{ *:[v4i32] }:$src 3085 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3086 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3087 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3088 GIR_EraseFromParent, /*InsnID*/0, 3089 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3090 // GIR_Coverage, 1294, 3091 GIR_Done, 3092 // Label 291: @6254 3093 GIM_Try, /*On fail goto*//*Label 292*/ 6288, // Rule ID 1295 // 3094 GIM_CheckFeatures, GIFBS_HasAltivec, 3095 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 3096 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3097 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3098 // (bitconvert:{ *:[v4f32] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[v4f32] }:$src 3099 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3100 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3101 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3102 GIR_EraseFromParent, /*InsnID*/0, 3103 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3104 // GIR_Coverage, 1295, 3105 GIR_Done, 3106 // Label 292: @6288 3107 GIM_Try, /*On fail goto*//*Label 293*/ 6322, // Rule ID 1296 // 3108 GIM_CheckFeatures, GIFBS_HasAltivec, 3109 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 3110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3112 // (bitconvert:{ *:[v4f32] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[v4f32] }:$src 3113 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3114 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3116 GIR_EraseFromParent, /*InsnID*/0, 3117 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3118 // GIR_Coverage, 1296, 3119 GIR_Done, 3120 // Label 293: @6322 3121 GIM_Try, /*On fail goto*//*Label 294*/ 6356, // Rule ID 1297 // 3122 GIM_CheckFeatures, GIFBS_HasAltivec, 3123 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 3124 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3126 // (bitconvert:{ *:[v4f32] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[v4f32] }:$src 3127 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3128 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3129 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3130 GIR_EraseFromParent, /*InsnID*/0, 3131 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3132 // GIR_Coverage, 1297, 3133 GIR_Done, 3134 // Label 294: @6356 3135 GIM_Try, /*On fail goto*//*Label 295*/ 6390, // Rule ID 1298 // 3136 GIM_CheckFeatures, GIFBS_HasAltivec, 3137 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 3138 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3140 // (bitconvert:{ *:[v4f32] } VRRC:{ *:[v2i64] }:$src) => VRRC:{ *:[v4f32] }:$src 3141 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3142 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3144 GIR_EraseFromParent, /*InsnID*/0, 3145 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3146 // GIR_Coverage, 1298, 3147 GIR_Done, 3148 // Label 295: @6390 3149 GIM_Try, /*On fail goto*//*Label 296*/ 6424, // Rule ID 1299 // 3150 GIM_CheckFeatures, GIFBS_HasAltivec, 3151 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 3152 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3153 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3154 // (bitconvert:{ *:[v4f32] } VRRC:{ *:[v1i128] }:$src) => VRRC:{ *:[v4f32] }:$src 3155 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3156 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3157 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3158 GIR_EraseFromParent, /*InsnID*/0, 3159 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3160 // GIR_Coverage, 1299, 3161 GIR_Done, 3162 // Label 296: @6424 3163 GIM_Try, /*On fail goto*//*Label 297*/ 6458, // Rule ID 1317 // 3164 GIM_CheckFeatures, GIFBS_HasAltivec, 3165 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 3166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3167 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3168 // (bitconvert:{ *:[v4i32] } VRRC:{ *:[f128] }:$src) => VRRC:{ *:[v4i32] }:$src 3169 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3170 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3171 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3172 GIR_EraseFromParent, /*InsnID*/0, 3173 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3174 // GIR_Coverage, 1317, 3175 GIR_Done, 3176 // Label 297: @6458 3177 GIM_Try, /*On fail goto*//*Label 298*/ 6492, // Rule ID 1318 // 3178 GIM_CheckFeatures, GIFBS_HasAltivec, 3179 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 3180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3182 // (bitconvert:{ *:[v4f32] } VRRC:{ *:[f128] }:$src) => VRRC:{ *:[v4f32] }:$src 3183 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3184 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3185 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3186 GIR_EraseFromParent, /*InsnID*/0, 3187 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3188 // GIR_Coverage, 1318, 3189 GIR_Done, 3190 // Label 298: @6492 3191 GIM_Reject, 3192 // Label 265: @6493 3193 GIM_Try, /*On fail goto*//*Label 299*/ 6547, // Rule ID 1895 // 3194 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 3195 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 3196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 3197 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3198 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 3199 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 3200 GIM_CheckIsSafeToFold, /*InsnID*/1, 3201 // (bitconvert:{ *:[v8i16] } immAllOnesV:{ *:[v16i8] }) => (COPY_TO_REGCLASS:{ *:[v8i16] } (XXLEQVOnes:{ *:[v4i32] }), VSRC:{ *:[i32] }) 3202 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, 3203 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::XXLEQVOnes, 3204 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3205 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3206 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3207 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3208 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3209 GIR_EraseFromParent, /*InsnID*/0, 3210 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VSRCRegClassID, 3211 // GIR_Coverage, 1895, 3212 GIR_Done, 3213 // Label 299: @6547 3214 GIM_Try, /*On fail goto*//*Label 300*/ 6581, // Rule ID 1285 // 3215 GIM_CheckFeatures, GIFBS_HasAltivec, 3216 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 3217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3219 // (bitconvert:{ *:[v8i16] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[v8i16] }:$src 3220 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3221 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3222 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3223 GIR_EraseFromParent, /*InsnID*/0, 3224 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3225 // GIR_Coverage, 1285, 3226 GIR_Done, 3227 // Label 300: @6581 3228 GIM_Try, /*On fail goto*//*Label 301*/ 6615, // Rule ID 1286 // 3229 GIM_CheckFeatures, GIFBS_HasAltivec, 3230 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 3231 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3232 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3233 // (bitconvert:{ *:[v8i16] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[v8i16] }:$src 3234 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3235 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3236 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3237 GIR_EraseFromParent, /*InsnID*/0, 3238 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3239 // GIR_Coverage, 1286, 3240 GIR_Done, 3241 // Label 301: @6615 3242 GIM_Try, /*On fail goto*//*Label 302*/ 6649, // Rule ID 1287 // 3243 GIM_CheckFeatures, GIFBS_HasAltivec, 3244 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 3245 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3247 // (bitconvert:{ *:[v8i16] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[v8i16] }:$src 3248 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3249 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3250 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3251 GIR_EraseFromParent, /*InsnID*/0, 3252 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3253 // GIR_Coverage, 1287, 3254 GIR_Done, 3255 // Label 302: @6649 3256 GIM_Try, /*On fail goto*//*Label 303*/ 6683, // Rule ID 1288 // 3257 GIM_CheckFeatures, GIFBS_HasAltivec, 3258 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 3259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3260 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3261 // (bitconvert:{ *:[v8i16] } VRRC:{ *:[v2i64] }:$src) => VRRC:{ *:[v8i16] }:$src 3262 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3263 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3264 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3265 GIR_EraseFromParent, /*InsnID*/0, 3266 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3267 // GIR_Coverage, 1288, 3268 GIR_Done, 3269 // Label 303: @6683 3270 GIM_Try, /*On fail goto*//*Label 304*/ 6717, // Rule ID 1289 // 3271 GIM_CheckFeatures, GIFBS_HasAltivec, 3272 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 3273 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3274 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3275 // (bitconvert:{ *:[v8i16] } VRRC:{ *:[v1i128] }:$src) => VRRC:{ *:[v8i16] }:$src 3276 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3277 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3278 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3279 GIR_EraseFromParent, /*InsnID*/0, 3280 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3281 // GIR_Coverage, 1289, 3282 GIR_Done, 3283 // Label 304: @6717 3284 GIM_Try, /*On fail goto*//*Label 305*/ 6751, // Rule ID 1316 // 3285 GIM_CheckFeatures, GIFBS_HasAltivec, 3286 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 3287 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3289 // (bitconvert:{ *:[v8i16] } VRRC:{ *:[f128] }:$src) => VRRC:{ *:[v8i16] }:$src 3290 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3293 GIR_EraseFromParent, /*InsnID*/0, 3294 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3295 // GIR_Coverage, 1316, 3296 GIR_Done, 3297 // Label 305: @6751 3298 GIM_Reject, 3299 // Label 266: @6752 3300 GIM_Try, /*On fail goto*//*Label 306*/ 6786, // Rule ID 1280 // 3301 GIM_CheckFeatures, GIFBS_HasAltivec, 3302 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 3303 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3304 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3305 // (bitconvert:{ *:[v16i8] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[v16i8] }:$src 3306 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3307 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3308 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3309 GIR_EraseFromParent, /*InsnID*/0, 3310 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3311 // GIR_Coverage, 1280, 3312 GIR_Done, 3313 // Label 306: @6786 3314 GIM_Try, /*On fail goto*//*Label 307*/ 6820, // Rule ID 1281 // 3315 GIM_CheckFeatures, GIFBS_HasAltivec, 3316 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 3317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3319 // (bitconvert:{ *:[v16i8] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[v16i8] }:$src 3320 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3321 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3322 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3323 GIR_EraseFromParent, /*InsnID*/0, 3324 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3325 // GIR_Coverage, 1281, 3326 GIR_Done, 3327 // Label 307: @6820 3328 GIM_Try, /*On fail goto*//*Label 308*/ 6854, // Rule ID 1282 // 3329 GIM_CheckFeatures, GIFBS_HasAltivec, 3330 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 3331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3333 // (bitconvert:{ *:[v16i8] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[v16i8] }:$src 3334 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3335 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3336 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3337 GIR_EraseFromParent, /*InsnID*/0, 3338 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3339 // GIR_Coverage, 1282, 3340 GIR_Done, 3341 // Label 308: @6854 3342 GIM_Try, /*On fail goto*//*Label 309*/ 6888, // Rule ID 1283 // 3343 GIM_CheckFeatures, GIFBS_HasAltivec, 3344 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 3345 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3346 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3347 // (bitconvert:{ *:[v16i8] } VRRC:{ *:[v2i64] }:$src) => VRRC:{ *:[v16i8] }:$src 3348 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3349 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3350 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3351 GIR_EraseFromParent, /*InsnID*/0, 3352 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3353 // GIR_Coverage, 1283, 3354 GIR_Done, 3355 // Label 309: @6888 3356 GIM_Try, /*On fail goto*//*Label 310*/ 6922, // Rule ID 1284 // 3357 GIM_CheckFeatures, GIFBS_HasAltivec, 3358 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 3359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3361 // (bitconvert:{ *:[v16i8] } VRRC:{ *:[v1i128] }:$src) => VRRC:{ *:[v16i8] }:$src 3362 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3363 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3365 GIR_EraseFromParent, /*InsnID*/0, 3366 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3367 // GIR_Coverage, 1284, 3368 GIR_Done, 3369 // Label 310: @6922 3370 GIM_Try, /*On fail goto*//*Label 311*/ 6956, // Rule ID 1315 // 3371 GIM_CheckFeatures, GIFBS_HasAltivec, 3372 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 3373 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3374 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/PPC::VRRCRegClassID, 3375 // (bitconvert:{ *:[v16i8] } VRRC:{ *:[f128] }:$src) => VRRC:{ *:[v16i8] }:$src 3376 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3377 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3378 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3379 GIR_EraseFromParent, /*InsnID*/0, 3380 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::VRRCRegClassID, 3381 // GIR_Coverage, 1315, 3382 GIR_Done, 3383 // Label 311: @6956 3384 GIM_Reject, 3385 // Label 267: @6957 3386 GIM_Reject, 3387 // Label 12: @6958 3388 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 316*/ 7067, 3389 /*GILLT_s32*//*Label 312*/ 6969, 3390 /*GILLT_s64*//*Label 313*/ 6989, 0, 3391 /*GILLT_v2s64*//*Label 314*/ 7027, 3392 /*GILLT_v4s32*//*Label 315*/ 7047, 3393 // Label 312: @6969 3394 GIM_Try, /*On fail goto*//*Label 317*/ 6988, // Rule ID 147 // 3395 GIM_CheckFeatures, GIFBS_HasFPU, 3396 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 3397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 3398 // (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$frB) => (FRIZS:{ *:[f32] } f32:{ *:[f32] }:$frB) 3399 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FRIZS, 3400 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3401 // GIR_Coverage, 147, 3402 GIR_Done, 3403 // Label 317: @6988 3404 GIM_Reject, 3405 // Label 313: @6989 3406 GIM_Try, /*On fail goto*//*Label 318*/ 7026, 3407 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 3408 GIM_Try, /*On fail goto*//*Label 319*/ 7010, // Rule ID 903 // 3409 GIM_CheckFeatures, GIFBS_HasVSX, 3410 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 3411 // (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSRDPIZ:{ *:[f64] } f64:{ *:[f64] }:$XB) 3412 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSRDPIZ, 3413 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3414 // GIR_Coverage, 903, 3415 GIR_Done, 3416 // Label 319: @7010 3417 GIM_Try, /*On fail goto*//*Label 320*/ 7025, // Rule ID 145 // 3418 GIM_CheckFeatures, GIFBS_HasFPU, 3419 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 3420 // (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$frB) => (FRIZD:{ *:[f64] } f64:{ *:[f64] }:$frB) 3421 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FRIZD, 3422 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3423 // GIR_Coverage, 145, 3424 GIR_Done, 3425 // Label 320: @7025 3426 GIM_Reject, 3427 // Label 318: @7026 3428 GIM_Reject, 3429 // Label 314: @7027 3430 GIM_Try, /*On fail goto*//*Label 321*/ 7046, // Rule ID 911 // 3431 GIM_CheckFeatures, GIFBS_HasVSX, 3432 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 3433 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 3434 // (ftrunc:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVRDPIZ:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) 3435 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVRDPIZ, 3436 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3437 // GIR_Coverage, 911, 3438 GIR_Done, 3439 // Label 321: @7046 3440 GIM_Reject, 3441 // Label 315: @7047 3442 GIM_Try, /*On fail goto*//*Label 322*/ 7066, // Rule ID 919 // 3443 GIM_CheckFeatures, GIFBS_HasVSX, 3444 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 3445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 3446 // (ftrunc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVRSPIZ:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) 3447 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVRSPIZ, 3448 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3449 // GIR_Coverage, 919, 3450 GIR_Done, 3451 // Label 322: @7066 3452 GIM_Reject, 3453 // Label 316: @7067 3454 GIM_Reject, 3455 // Label 13: @7068 3456 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 327*/ 7177, 3457 /*GILLT_s32*//*Label 323*/ 7079, 3458 /*GILLT_s64*//*Label 324*/ 7099, 0, 3459 /*GILLT_v2s64*//*Label 325*/ 7137, 3460 /*GILLT_v4s32*//*Label 326*/ 7157, 3461 // Label 323: @7079 3462 GIM_Try, /*On fail goto*//*Label 328*/ 7098, // Rule ID 139 // 3463 GIM_CheckFeatures, GIFBS_HasFPU, 3464 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 3465 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 3466 // (fround:{ *:[f32] } f32:{ *:[f32] }:$frB) => (FRINS:{ *:[f32] } f32:{ *:[f32] }:$frB) 3467 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FRINS, 3468 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3469 // GIR_Coverage, 139, 3470 GIR_Done, 3471 // Label 328: @7098 3472 GIM_Reject, 3473 // Label 324: @7099 3474 GIM_Try, /*On fail goto*//*Label 329*/ 7136, 3475 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 3476 GIM_Try, /*On fail goto*//*Label 330*/ 7120, // Rule ID 897 // 3477 GIM_CheckFeatures, GIFBS_HasVSX, 3478 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 3479 // (fround:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSRDPI:{ *:[f64] } f64:{ *:[f64] }:$XB) 3480 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSRDPI, 3481 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3482 // GIR_Coverage, 897, 3483 GIR_Done, 3484 // Label 330: @7120 3485 GIM_Try, /*On fail goto*//*Label 331*/ 7135, // Rule ID 137 // 3486 GIM_CheckFeatures, GIFBS_HasFPU, 3487 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 3488 // (fround:{ *:[f64] } f64:{ *:[f64] }:$frB) => (FRIND:{ *:[f64] } f64:{ *:[f64] }:$frB) 3489 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FRIND, 3490 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3491 // GIR_Coverage, 137, 3492 GIR_Done, 3493 // Label 331: @7135 3494 GIM_Reject, 3495 // Label 329: @7136 3496 GIM_Reject, 3497 // Label 325: @7137 3498 GIM_Try, /*On fail goto*//*Label 332*/ 7156, // Rule ID 905 // 3499 GIM_CheckFeatures, GIFBS_HasVSX, 3500 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 3501 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 3502 // (fround:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVRDPI:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) 3503 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVRDPI, 3504 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3505 // GIR_Coverage, 905, 3506 GIR_Done, 3507 // Label 332: @7156 3508 GIM_Reject, 3509 // Label 326: @7157 3510 GIM_Try, /*On fail goto*//*Label 333*/ 7176, // Rule ID 913 // 3511 GIM_CheckFeatures, GIFBS_HasVSX, 3512 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 3513 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 3514 // (fround:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVRSPI:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) 3515 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVRSPI, 3516 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3517 // GIR_Coverage, 913, 3518 GIR_Done, 3519 // Label 333: @7176 3520 GIM_Reject, 3521 // Label 327: @7177 3522 GIM_Reject, 3523 // Label 14: @7178 3524 GIM_Try, /*On fail goto*//*Label 334*/ 7195, // Rule ID 631 // 3525 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 3526 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 3527 // (readcyclecounter:{ *:[i64] }) => (MFTB8:{ *:[i64] }) 3528 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::MFTB8, 3529 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3530 // GIR_Coverage, 631, 3531 GIR_Done, 3532 // Label 334: @7195 3533 GIM_Reject, 3534 // Label 15: @7196 3535 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 337*/ 7258, 3536 /*GILLT_s32*//*Label 335*/ 7204, 3537 /*GILLT_s64*//*Label 336*/ 7231, 3538 // Label 335: @7204 3539 GIM_Try, /*On fail goto*//*Label 338*/ 7230, // Rule ID 1240 // 3540 GIM_CheckFeatures, GIFBS_HasSYNC, 3541 GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 7, 3542 // MIs[0] Operand 1 3543 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 3544 // (atomic_fence 7:{ *:[i32] }, (timm:{ *:[i32] })) => (SYNC 0:{ *:[i32] }) 3545 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SYNC, 3546 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 3547 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3548 GIR_EraseFromParent, /*InsnID*/0, 3549 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3550 // GIR_Coverage, 1240, 3551 GIR_Done, 3552 // Label 338: @7230 3553 GIM_Reject, 3554 // Label 336: @7231 3555 GIM_Try, /*On fail goto*//*Label 339*/ 7257, // Rule ID 1239 // 3556 GIM_CheckFeatures, GIFBS_HasSYNC, 3557 GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 7, 3558 // MIs[0] Operand 1 3559 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 3560 // (atomic_fence 7:{ *:[i64] }, (timm:{ *:[i64] })) => (SYNC 0:{ *:[i32] }) 3561 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SYNC, 3562 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 3563 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3564 GIR_EraseFromParent, /*InsnID*/0, 3565 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3566 // GIR_Coverage, 1239, 3567 GIR_Done, 3568 // Label 339: @7257 3569 GIM_Reject, 3570 // Label 337: @7258 3571 GIM_Try, /*On fail goto*//*Label 340*/ 7302, 3572 GIM_CheckIsImm, /*MI*/0, /*Op*/0, 3573 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 3574 GIM_Try, /*On fail goto*//*Label 341*/ 7285, // Rule ID 1241 // 3575 GIM_CheckFeatures, GIFBS_HasSYNC, 3576 // (atomic_fence (timm:{ *:[iPTR] }), (timm:{ *:[iPTR] })) => (SYNC 1:{ *:[i32] }) 3577 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SYNC, 3578 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 3579 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3580 GIR_EraseFromParent, /*InsnID*/0, 3581 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3582 // GIR_Coverage, 1241, 3583 GIR_Done, 3584 // Label 341: @7285 3585 GIM_Try, /*On fail goto*//*Label 342*/ 7301, // Rule ID 1242 // 3586 GIM_CheckFeatures, GIFBS_HasOnlyMSYNC, 3587 // (atomic_fence (timm:{ *:[iPTR] }), (timm:{ *:[iPTR] })) => (MSYNC) 3588 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MSYNC, 3589 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3590 GIR_EraseFromParent, /*InsnID*/0, 3591 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3592 // GIR_Coverage, 1242, 3593 GIR_Done, 3594 // Label 342: @7301 3595 GIM_Reject, 3596 // Label 340: @7302 3597 GIM_Reject, 3598 // Label 16: @7303 3599 GIM_Try, /*On fail goto*//*Label 343*/ 7420, 3600 GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, 3601 GIM_Try, /*On fail goto*//*Label 344*/ 7336, // Rule ID 1145 // 3602 GIM_CheckFeatures, GIFBS_IsNotISAFuture_MMA, 3603 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_mma_xxsetaccz, 3604 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v512s1, 3605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::ACCRCRegClassID, 3606 // (intrinsic_wo_chain:{ *:[v512i1] } 7588:{ *:[iPTR] }) => (XXSETACCZ:{ *:[v512i1] }) 3607 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XXSETACCZ, 3608 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // AT 3609 GIR_EraseFromParent, /*InsnID*/0, 3610 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3611 // GIR_Coverage, 1145, 3612 GIR_Done, 3613 // Label 344: @7336 3614 GIM_Try, /*On fail goto*//*Label 345*/ 7364, // Rule ID 1146 // 3615 GIM_CheckFeatures, GIFBS_IsISAFuture_MMA, 3616 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_mma_xxsetaccz, 3617 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v512s1, 3618 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::WACCRCRegClassID, 3619 // (intrinsic_wo_chain:{ *:[v512i1] } 7588:{ *:[iPTR] }) => (XXSETACCZW:{ *:[v512i1] }) 3620 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XXSETACCZW, 3621 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // AT 3622 GIR_EraseFromParent, /*InsnID*/0, 3623 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3624 // GIR_Coverage, 1146, 3625 GIR_Done, 3626 // Label 345: @7364 3627 GIM_Try, /*On fail goto*//*Label 346*/ 7390, // Rule ID 4837 // 3628 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_mfmsr, 3629 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 3630 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 3631 // (intrinsic_wo_chain:{ *:[i32] } 7520:{ *:[iPTR] }) => (MFMSR:{ *:[i32] }) 3632 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MFMSR, 3633 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RT 3634 GIR_EraseFromParent, /*InsnID*/0, 3635 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3636 // GIR_Coverage, 4837, 3637 GIR_Done, 3638 // Label 346: @7390 3639 GIM_Try, /*On fail goto*//*Label 347*/ 7419, // Rule ID 4838 // 3640 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_mftbu, 3641 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 3642 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 3643 // (intrinsic_wo_chain:{ *:[i32] } 7522:{ *:[iPTR] }) => (MFTB:{ *:[i32] } 269:{ *:[i32] }) 3644 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MFTB, 3645 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RT 3646 GIR_AddImm, /*InsnID*/0, /*Imm*/269, 3647 GIR_EraseFromParent, /*InsnID*/0, 3648 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3649 // GIR_Coverage, 4838, 3650 GIR_Done, 3651 // Label 347: @7419 3652 GIM_Reject, 3653 // Label 343: @7420 3654 GIM_Try, /*On fail goto*//*Label 348*/ 9950, 3655 GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, 3656 GIM_Try, /*On fail goto*//*Label 349*/ 7461, // Rule ID 864 // 3657 GIM_CheckFeatures, GIFBS_HasVSX, 3658 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvcvdpsp, 3659 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 3660 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 3661 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 3662 // (intrinsic_wo_chain:{ *:[v4f32] } 7678:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB) => (XVCVDPSP:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$XB) 3663 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVCVDPSP, 3664 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 3665 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 3666 GIR_EraseFromParent, /*InsnID*/0, 3667 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3668 // GIR_Coverage, 864, 3669 GIR_Done, 3670 // Label 349: @7461 3671 GIM_Try, /*On fail goto*//*Label 350*/ 7497, // Rule ID 867 // 3672 GIM_CheckFeatures, GIFBS_HasVSX, 3673 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvcvdpsxws, 3674 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 3675 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 3676 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 3677 // (intrinsic_wo_chain:{ *:[v4i32] } 7679:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB) => (XVCVDPSXWS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$XB) 3678 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVCVDPSXWS, 3679 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 3680 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 3681 GIR_EraseFromParent, /*InsnID*/0, 3682 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3683 // GIR_Coverage, 867, 3684 GIR_Done, 3685 // Label 350: @7497 3686 GIM_Try, /*On fail goto*//*Label 351*/ 7533, // Rule ID 870 // 3687 GIM_CheckFeatures, GIFBS_HasVSX, 3688 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvcvdpuxws, 3689 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 3690 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 3691 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 3692 // (intrinsic_wo_chain:{ *:[v4i32] } 7680:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB) => (XVCVDPUXWS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$XB) 3693 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVCVDPUXWS, 3694 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 3695 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 3696 GIR_EraseFromParent, /*InsnID*/0, 3697 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3698 // GIR_Coverage, 870, 3699 GIR_Done, 3700 // Label 351: @7533 3701 GIM_Try, /*On fail goto*//*Label 352*/ 7569, // Rule ID 871 // 3702 GIM_CheckFeatures, GIFBS_HasVSX, 3703 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvcvspdp, 3704 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 3705 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 3706 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 3707 // (intrinsic_wo_chain:{ *:[v2f64] } 7683:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVCVSPDP:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$XB) 3708 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVCVSPDP, 3709 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 3710 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 3711 GIR_EraseFromParent, /*InsnID*/0, 3712 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3713 // GIR_Coverage, 871, 3714 GIR_Done, 3715 // Label 352: @7569 3716 GIM_Try, /*On fail goto*//*Label 353*/ 7605, // Rule ID 872 // 3717 GIM_CheckFeatures, GIFBS_HasVSX, 3718 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvcvspsxds, 3719 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 3720 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 3721 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 3722 // (intrinsic_wo_chain:{ *:[v2i64] } 7685:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVCVSPSXDS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$XB) 3723 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVCVSPSXDS, 3724 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 3725 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 3726 GIR_EraseFromParent, /*InsnID*/0, 3727 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3728 // GIR_Coverage, 872, 3729 GIR_Done, 3730 // Label 353: @7605 3731 GIM_Try, /*On fail goto*//*Label 354*/ 7641, // Rule ID 875 // 3732 GIM_CheckFeatures, GIFBS_HasVSX, 3733 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvcvspuxds, 3734 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 3735 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 3736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 3737 // (intrinsic_wo_chain:{ *:[v2i64] } 7686:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVCVSPUXDS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$XB) 3738 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVCVSPUXDS, 3739 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 3740 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 3741 GIR_EraseFromParent, /*InsnID*/0, 3742 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3743 // GIR_Coverage, 875, 3744 GIR_Done, 3745 // Label 354: @7641 3746 GIM_Try, /*On fail goto*//*Label 355*/ 7677, // Rule ID 880 // 3747 GIM_CheckFeatures, GIFBS_HasVSX, 3748 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvcvsxdsp, 3749 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 3750 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 3751 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 3752 // (intrinsic_wo_chain:{ *:[v4f32] } 7687:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$XB) => (XVCVSXDSP:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$XB) 3753 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVCVSXDSP, 3754 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 3755 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 3756 GIR_EraseFromParent, /*InsnID*/0, 3757 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3758 // GIR_Coverage, 880, 3759 GIR_Done, 3760 // Label 355: @7677 3761 GIM_Try, /*On fail goto*//*Label 356*/ 7713, // Rule ID 885 // 3762 GIM_CheckFeatures, GIFBS_HasVSX, 3763 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvcvuxdsp, 3764 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 3765 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 3766 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 3767 // (intrinsic_wo_chain:{ *:[v4f32] } 7689:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$XB) => (XVCVUXDSP:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$XB) 3768 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVCVUXDSP, 3769 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 3770 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 3771 GIR_EraseFromParent, /*InsnID*/0, 3772 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3773 // GIR_Coverage, 885, 3774 GIR_Done, 3775 // Label 356: @7713 3776 GIM_Try, /*On fail goto*//*Label 357*/ 7749, // Rule ID 888 // 3777 GIM_CheckFeatures, GIFBS_HasVSX, 3778 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvcvsxwdp, 3779 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 3780 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 3781 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 3782 // (intrinsic_wo_chain:{ *:[v2f64] } 7688:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$XB) => (XVCVSXWDP:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$XB) 3783 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVCVSXWDP, 3784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 3785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 3786 GIR_EraseFromParent, /*InsnID*/0, 3787 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3788 // GIR_Coverage, 888, 3789 GIR_Done, 3790 // Label 357: @7749 3791 GIM_Try, /*On fail goto*//*Label 358*/ 7785, // Rule ID 889 // 3792 GIM_CheckFeatures, GIFBS_HasVSX, 3793 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvcvuxwdp, 3794 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 3795 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 3796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 3797 // (intrinsic_wo_chain:{ *:[v2f64] } 7690:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$XB) => (XVCVUXWDP:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$XB) 3798 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVCVUXWDP, 3799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 3800 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 3801 GIR_EraseFromParent, /*InsnID*/0, 3802 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3803 // GIR_Coverage, 889, 3804 GIR_Done, 3805 // Label 358: @7785 3806 GIM_Try, /*On fail goto*//*Label 359*/ 7821, // Rule ID 997 // 3807 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 3808 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_sqrtf128_round_to_odd, 3809 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 3810 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 3811 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3812 // (intrinsic_wo_chain:{ *:[f128] } 7614:{ *:[iPTR] }, f128:{ *:[f128] }:$vB) => (XSSQRTQPO:{ *:[f128] } f128:{ *:[f128] }:$vB) 3813 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSSQRTQPO, 3814 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 3815 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 3816 GIR_EraseFromParent, /*InsnID*/0, 3817 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3818 // GIR_Coverage, 997, 3819 GIR_Done, 3820 // Label 359: @7821 3821 GIM_Try, /*On fail goto*//*Label 360*/ 7857, // Rule ID 1004 // 3822 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 3823 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_truncf128_round_to_odd, 3824 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 3825 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 3826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VFRCRegClassID, 3827 // (intrinsic_wo_chain:{ *:[f64] } 7641:{ *:[iPTR] }, f128:{ *:[f128] }:$vB) => (XSCVQPDPO:{ *:[f64] } f128:{ *:[f128] }:$vB) 3828 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSCVQPDPO, 3829 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 3830 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 3831 GIR_EraseFromParent, /*InsnID*/0, 3832 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3833 // GIR_Coverage, 1004, 3834 GIR_Done, 3835 // Label 360: @7857 3836 GIM_Try, /*On fail goto*//*Label 361*/ 7893, // Rule ID 1005 // 3837 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 3838 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvcvsphp, 3839 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 3840 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 3841 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 3842 // (intrinsic_wo_chain:{ *:[v4f32] } 7684:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVCVSPHP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) 3843 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVCVSPHP, 3844 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 3845 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 3846 GIR_EraseFromParent, /*InsnID*/0, 3847 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3848 // GIR_Coverage, 1005, 3849 GIR_Done, 3850 // Label 361: @7893 3851 GIM_Try, /*On fail goto*//*Label 362*/ 7929, // Rule ID 1009 // 3852 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 3853 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvxexpdp, 3854 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 3855 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 3856 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 3857 // (intrinsic_wo_chain:{ *:[v2i64] } 7712:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB) => (XVXEXPDP:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XB) 3858 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVXEXPDP, 3859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 3860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 3861 GIR_EraseFromParent, /*InsnID*/0, 3862 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3863 // GIR_Coverage, 1009, 3864 GIR_Done, 3865 // Label 362: @7929 3866 GIM_Try, /*On fail goto*//*Label 363*/ 7965, // Rule ID 1010 // 3867 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 3868 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvxexpsp, 3869 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 3870 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 3871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 3872 // (intrinsic_wo_chain:{ *:[v4i32] } 7713:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVXEXPSP:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XB) 3873 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVXEXPSP, 3874 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 3875 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 3876 GIR_EraseFromParent, /*InsnID*/0, 3877 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3878 // GIR_Coverage, 1010, 3879 GIR_Done, 3880 // Label 363: @7965 3881 GIM_Try, /*On fail goto*//*Label 364*/ 8001, // Rule ID 1011 // 3882 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 3883 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvxsigdp, 3884 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 3885 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 3886 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 3887 // (intrinsic_wo_chain:{ *:[v2i64] } 7714:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB) => (XVXSIGDP:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XB) 3888 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVXSIGDP, 3889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 3890 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 3891 GIR_EraseFromParent, /*InsnID*/0, 3892 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3893 // GIR_Coverage, 1011, 3894 GIR_Done, 3895 // Label 364: @8001 3896 GIM_Try, /*On fail goto*//*Label 365*/ 8037, // Rule ID 1012 // 3897 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 3898 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvxsigsp, 3899 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 3900 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 3901 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 3902 // (intrinsic_wo_chain:{ *:[v4i32] } 7715:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVXSIGSP:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XB) 3903 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVXSIGSP, 3904 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 3905 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 3906 GIR_EraseFromParent, /*InsnID*/0, 3907 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3908 // GIR_Coverage, 1012, 3909 GIR_Done, 3910 // Label 365: @8037 3911 GIM_Try, /*On fail goto*//*Label 366*/ 8081, // Rule ID 1075 // 3912 GIM_CheckFeatures, GIFBS_IsISA3_1, 3913 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_mtvsrbm, 3914 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 3915 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3917 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3918 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 3919 // MIs[1] Operand 1 3920 // No operand predicates 3921 GIM_CheckIsSafeToFold, /*InsnID*/1, 3922 // (intrinsic_wo_chain:{ *:[v16i8] } 7145:{ *:[iPTR] }, (imm:{ *:[i64] }):$D) => (MTVSRBMI:{ *:[v16i8] } (imm:{ *:[i64] }):$D) 3923 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MTVSRBMI, 3924 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 3925 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // D 3926 GIR_EraseFromParent, /*InsnID*/0, 3927 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3928 // GIR_Coverage, 1075, 3929 GIR_Done, 3930 // Label 366: @8081 3931 GIM_Try, /*On fail goto*//*Label 367*/ 8115, // Rule ID 73 // 3932 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_popcntb, 3933 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 3934 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3935 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 3936 // (intrinsic_wo_chain:{ *:[i32] } 7603:{ *:[iPTR] }, i32:{ *:[i32] }:$rS) => (POPCNTB:{ *:[i32] } i32:{ *:[i32] }:$rS) 3937 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::POPCNTB, 3938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 3939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rS 3940 GIR_EraseFromParent, /*InsnID*/0, 3941 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3942 // GIR_Coverage, 73, 3943 GIR_Done, 3944 // Label 367: @8115 3945 GIM_Try, /*On fail goto*//*Label 368*/ 8151, // Rule ID 317 // 3946 GIM_CheckFeatures, GIFBS_HasAltivec, 3947 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vexptefp, 3948 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 3949 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 3950 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3951 // (intrinsic_wo_chain:{ *:[v4f32] } 7252:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$vB) => (VEXPTEFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vB) 3952 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXPTEFP, 3953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 3954 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 3955 GIR_EraseFromParent, /*InsnID*/0, 3956 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3957 // GIR_Coverage, 317, 3958 GIR_Done, 3959 // Label 368: @8151 3960 GIM_Try, /*On fail goto*//*Label 369*/ 8187, // Rule ID 318 // 3961 GIM_CheckFeatures, GIFBS_HasAltivec, 3962 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vlogefp, 3963 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 3964 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 3965 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3966 // (intrinsic_wo_chain:{ *:[v4f32] } 7290:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$vB) => (VLOGEFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vB) 3967 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VLOGEFP, 3968 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 3969 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 3970 GIR_EraseFromParent, /*InsnID*/0, 3971 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3972 // GIR_Coverage, 318, 3973 GIR_Done, 3974 // Label 369: @8187 3975 GIM_Try, /*On fail goto*//*Label 370*/ 8223, // Rule ID 359 // 3976 GIM_CheckFeatures, GIFBS_HasAltivec, 3977 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vrefp, 3978 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 3979 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 3980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3981 // (intrinsic_wo_chain:{ *:[v4f32] } 7358:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$vB) => (VREFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vB) 3982 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VREFP, 3983 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 3984 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 3985 GIR_EraseFromParent, /*InsnID*/0, 3986 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3987 // GIR_Coverage, 359, 3988 GIR_Done, 3989 // Label 370: @8223 3990 GIM_Try, /*On fail goto*//*Label 371*/ 8259, // Rule ID 360 // 3991 GIM_CheckFeatures, GIFBS_HasAltivec, 3992 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vrfim, 3993 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 3994 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 3995 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 3996 // (intrinsic_wo_chain:{ *:[v4f32] } 7359:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$vB) => (VRFIM:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vB) 3997 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VRFIM, 3998 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 3999 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4000 GIR_EraseFromParent, /*InsnID*/0, 4001 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4002 // GIR_Coverage, 360, 4003 GIR_Done, 4004 // Label 371: @8259 4005 GIM_Try, /*On fail goto*//*Label 372*/ 8295, // Rule ID 361 // 4006 GIM_CheckFeatures, GIFBS_HasAltivec, 4007 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vrfin, 4008 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4009 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4010 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4011 // (intrinsic_wo_chain:{ *:[v4f32] } 7360:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$vB) => (VRFIN:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vB) 4012 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VRFIN, 4013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4014 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4015 GIR_EraseFromParent, /*InsnID*/0, 4016 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4017 // GIR_Coverage, 361, 4018 GIR_Done, 4019 // Label 372: @8295 4020 GIM_Try, /*On fail goto*//*Label 373*/ 8331, // Rule ID 362 // 4021 GIM_CheckFeatures, GIFBS_HasAltivec, 4022 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vrfip, 4023 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4024 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4025 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4026 // (intrinsic_wo_chain:{ *:[v4f32] } 7361:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$vB) => (VRFIP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vB) 4027 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VRFIP, 4028 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4030 GIR_EraseFromParent, /*InsnID*/0, 4031 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4032 // GIR_Coverage, 362, 4033 GIR_Done, 4034 // Label 373: @8331 4035 GIM_Try, /*On fail goto*//*Label 374*/ 8367, // Rule ID 363 // 4036 GIM_CheckFeatures, GIFBS_HasAltivec, 4037 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vrfiz, 4038 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4039 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4040 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4041 // (intrinsic_wo_chain:{ *:[v4f32] } 7362:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$vB) => (VRFIZ:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vB) 4042 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VRFIZ, 4043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4044 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4045 GIR_EraseFromParent, /*InsnID*/0, 4046 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4047 // GIR_Coverage, 363, 4048 GIR_Done, 4049 // Label 374: @8367 4050 GIM_Try, /*On fail goto*//*Label 375*/ 8403, // Rule ID 364 // 4051 GIM_CheckFeatures, GIFBS_HasAltivec, 4052 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vrsqrtefp, 4053 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4054 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4055 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4056 // (intrinsic_wo_chain:{ *:[v4f32] } 7373:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$vB) => (VRSQRTEFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vB) 4057 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VRSQRTEFP, 4058 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4059 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4060 GIR_EraseFromParent, /*InsnID*/0, 4061 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4062 // GIR_Coverage, 364, 4063 GIR_Done, 4064 // Label 375: @8403 4065 GIM_Try, /*On fail goto*//*Label 376*/ 8439, // Rule ID 415 // 4066 GIM_CheckFeatures, GIFBS_HasAltivec, 4067 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vupkhpx, 4068 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4069 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 4070 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4071 // (intrinsic_wo_chain:{ *:[v4i32] } 7415:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vB) => (VUPKHPX:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$vB) 4072 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VUPKHPX, 4073 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4074 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4075 GIR_EraseFromParent, /*InsnID*/0, 4076 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4077 // GIR_Coverage, 415, 4078 GIR_Done, 4079 // Label 376: @8439 4080 GIM_Try, /*On fail goto*//*Label 377*/ 8475, // Rule ID 416 // 4081 GIM_CheckFeatures, GIFBS_HasAltivec, 4082 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vupkhsb, 4083 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 4084 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 4085 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4086 // (intrinsic_wo_chain:{ *:[v8i16] } 7416:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vB) => (VUPKHSB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$vB) 4087 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VUPKHSB, 4088 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4089 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4090 GIR_EraseFromParent, /*InsnID*/0, 4091 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4092 // GIR_Coverage, 416, 4093 GIR_Done, 4094 // Label 377: @8475 4095 GIM_Try, /*On fail goto*//*Label 378*/ 8511, // Rule ID 417 // 4096 GIM_CheckFeatures, GIFBS_HasAltivec, 4097 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vupkhsh, 4098 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4099 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 4100 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4101 // (intrinsic_wo_chain:{ *:[v4i32] } 7417:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vB) => (VUPKHSH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$vB) 4102 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VUPKHSH, 4103 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4104 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4105 GIR_EraseFromParent, /*InsnID*/0, 4106 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4107 // GIR_Coverage, 417, 4108 GIR_Done, 4109 // Label 378: @8511 4110 GIM_Try, /*On fail goto*//*Label 379*/ 8547, // Rule ID 418 // 4111 GIM_CheckFeatures, GIFBS_HasAltivec, 4112 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vupklpx, 4113 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4114 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 4115 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4116 // (intrinsic_wo_chain:{ *:[v4i32] } 7419:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vB) => (VUPKLPX:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$vB) 4117 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VUPKLPX, 4118 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4119 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4120 GIR_EraseFromParent, /*InsnID*/0, 4121 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4122 // GIR_Coverage, 418, 4123 GIR_Done, 4124 // Label 379: @8547 4125 GIM_Try, /*On fail goto*//*Label 380*/ 8583, // Rule ID 419 // 4126 GIM_CheckFeatures, GIFBS_HasAltivec, 4127 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vupklsb, 4128 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 4129 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 4130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4131 // (intrinsic_wo_chain:{ *:[v8i16] } 7420:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vB) => (VUPKLSB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$vB) 4132 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VUPKLSB, 4133 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4134 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4135 GIR_EraseFromParent, /*InsnID*/0, 4136 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4137 // GIR_Coverage, 419, 4138 GIR_Done, 4139 // Label 380: @8583 4140 GIM_Try, /*On fail goto*//*Label 381*/ 8619, // Rule ID 420 // 4141 GIM_CheckFeatures, GIFBS_HasAltivec, 4142 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vupklsh, 4143 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4144 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 4145 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4146 // (intrinsic_wo_chain:{ *:[v4i32] } 7421:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vB) => (VUPKLSH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$vB) 4147 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VUPKLSH, 4148 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4149 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4150 GIR_EraseFromParent, /*InsnID*/0, 4151 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4152 // GIR_Coverage, 420, 4153 GIR_Done, 4154 // Label 381: @8619 4155 GIM_Try, /*On fail goto*//*Label 382*/ 8655, // Rule ID 500 // 4156 GIM_CheckFeatures, GIFBS_HasP8Altivec, 4157 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vupkhsw, 4158 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4159 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4161 // (intrinsic_wo_chain:{ *:[v2i64] } 7418:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vB) => (VUPKHSW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$vB) 4162 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VUPKHSW, 4163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4164 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4165 GIR_EraseFromParent, /*InsnID*/0, 4166 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4167 // GIR_Coverage, 500, 4168 GIR_Done, 4169 // Label 382: @8655 4170 GIM_Try, /*On fail goto*//*Label 383*/ 8691, // Rule ID 501 // 4171 GIM_CheckFeatures, GIFBS_HasP8Altivec, 4172 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vupklsw, 4173 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4174 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4175 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4176 // (intrinsic_wo_chain:{ *:[v2i64] } 7422:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vB) => (VUPKLSW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$vB) 4177 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VUPKLSW, 4178 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4179 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4180 GIR_EraseFromParent, /*InsnID*/0, 4181 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4182 // GIR_Coverage, 501, 4183 GIR_Done, 4184 // Label 383: @8691 4185 GIM_Try, /*On fail goto*//*Label 384*/ 8727, // Rule ID 502 // 4186 GIM_CheckFeatures, GIFBS_HasP8Altivec, 4187 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vgbbd, 4188 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 4189 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 4190 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4191 // (intrinsic_wo_chain:{ *:[v16i8] } 7272:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vB) => (VGBBD:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vB) 4192 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VGBBD, 4193 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4194 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4195 GIR_EraseFromParent, /*InsnID*/0, 4196 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4197 // GIR_Coverage, 502, 4198 GIR_Done, 4199 // Label 384: @8727 4200 GIM_Try, /*On fail goto*//*Label 385*/ 8763, // Rule ID 510 // 4201 GIM_CheckFeatures, GIFBS_HasP8Crypto, 4202 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_crypto_vsbox, 4203 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4204 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 4205 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4206 // (intrinsic_wo_chain:{ *:[v2i64] } 7127:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA) => (VSBOX:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA) 4207 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSBOX, 4208 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4209 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 4210 GIR_EraseFromParent, /*InsnID*/0, 4211 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4212 // GIR_Coverage, 510, 4213 GIR_Done, 4214 // Label 385: @8763 4215 GIM_Try, /*On fail goto*//*Label 386*/ 8799, // Rule ID 526 // 4216 GIM_CheckFeatures, GIFBS_HasP9Altivec, 4217 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vclzlsbb, 4218 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 4219 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 4220 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 4221 // (intrinsic_wo_chain:{ *:[i32] } 7182:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vB) => (VCLZLSBB:{ *:[i32] } v16i8:{ *:[v16i8] }:$vB) 4222 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VCLZLSBB, 4223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rD 4224 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4225 GIR_EraseFromParent, /*InsnID*/0, 4226 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4227 // GIR_Coverage, 526, 4228 GIR_Done, 4229 // Label 386: @8799 4230 GIM_Try, /*On fail goto*//*Label 387*/ 8835, // Rule ID 527 // 4231 GIM_CheckFeatures, GIFBS_HasP9Altivec, 4232 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vctzlsbb, 4233 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 4234 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 4235 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 4236 // (intrinsic_wo_chain:{ *:[i32] } 7240:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vB) => (VCTZLSBB:{ *:[i32] } v16i8:{ *:[v16i8] }:$vB) 4237 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VCTZLSBB, 4238 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rD 4239 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4240 GIR_EraseFromParent, /*InsnID*/0, 4241 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4242 // GIR_Coverage, 527, 4243 GIR_Done, 4244 // Label 387: @8835 4245 GIM_Try, /*On fail goto*//*Label 388*/ 8871, // Rule ID 532 // 4246 GIM_CheckFeatures, GIFBS_HasP9Altivec, 4247 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vextsb2w, 4248 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4249 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 4250 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4251 // (intrinsic_wo_chain:{ *:[v4i32] } 7267:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vB) => (VEXTSB2W:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$vB) 4252 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXTSB2W, 4253 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4254 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4255 GIR_EraseFromParent, /*InsnID*/0, 4256 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4257 // GIR_Coverage, 532, 4258 GIR_Done, 4259 // Label 388: @8871 4260 GIM_Try, /*On fail goto*//*Label 389*/ 8907, // Rule ID 533 // 4261 GIM_CheckFeatures, GIFBS_HasP9Altivec, 4262 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vextsh2w, 4263 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4264 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 4265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4266 // (intrinsic_wo_chain:{ *:[v4i32] } 7270:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vB) => (VEXTSH2W:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$vB) 4267 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXTSH2W, 4268 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4270 GIR_EraseFromParent, /*InsnID*/0, 4271 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4272 // GIR_Coverage, 533, 4273 GIR_Done, 4274 // Label 389: @8907 4275 GIM_Try, /*On fail goto*//*Label 390*/ 8943, // Rule ID 534 // 4276 GIM_CheckFeatures, GIFBS_HasP9Altivec, 4277 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vextsb2d, 4278 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4279 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 4280 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4281 // (intrinsic_wo_chain:{ *:[v2i64] } 7266:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vB) => (VEXTSB2D:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$vB) 4282 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXTSB2D, 4283 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4284 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4285 GIR_EraseFromParent, /*InsnID*/0, 4286 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4287 // GIR_Coverage, 534, 4288 GIR_Done, 4289 // Label 390: @8943 4290 GIM_Try, /*On fail goto*//*Label 391*/ 8979, // Rule ID 535 // 4291 GIM_CheckFeatures, GIFBS_HasP9Altivec, 4292 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vextsh2d, 4293 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4294 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 4295 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4296 // (intrinsic_wo_chain:{ *:[v2i64] } 7269:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vB) => (VEXTSH2D:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$vB) 4297 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXTSH2D, 4298 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4299 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4300 GIR_EraseFromParent, /*InsnID*/0, 4301 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4302 // GIR_Coverage, 535, 4303 GIR_Done, 4304 // Label 391: @8979 4305 GIM_Try, /*On fail goto*//*Label 392*/ 9015, // Rule ID 536 // 4306 GIM_CheckFeatures, GIFBS_HasP9Altivec, 4307 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vextsw2d, 4308 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4309 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4310 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4311 // (intrinsic_wo_chain:{ *:[v2i64] } 7271:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vB) => (VEXTSW2D:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$vB) 4312 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXTSW2D, 4313 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4314 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4315 GIR_EraseFromParent, /*InsnID*/0, 4316 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4317 // GIR_Coverage, 536, 4318 GIR_Done, 4319 // Label 392: @9015 4320 GIM_Try, /*On fail goto*//*Label 393*/ 9051, // Rule ID 539 // 4321 GIM_CheckFeatures, GIFBS_HasP9Altivec, 4322 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vprtybw, 4323 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4324 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4325 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4326 // (intrinsic_wo_chain:{ *:[v4i32] } 7357:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vB) => (VPRTYBW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB) 4327 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VPRTYBW, 4328 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4329 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4330 GIR_EraseFromParent, /*InsnID*/0, 4331 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4332 // GIR_Coverage, 539, 4333 GIR_Done, 4334 // Label 393: @9051 4335 GIM_Try, /*On fail goto*//*Label 394*/ 9087, // Rule ID 540 // 4336 GIM_CheckFeatures, GIFBS_HasP9Altivec, 4337 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vprtybd, 4338 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4339 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 4340 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4341 // (intrinsic_wo_chain:{ *:[v2i64] } 7355:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vB) => (VPRTYBD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vB) 4342 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VPRTYBD, 4343 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4344 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4345 GIR_EraseFromParent, /*InsnID*/0, 4346 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4347 // GIR_Coverage, 540, 4348 GIR_Done, 4349 // Label 394: @9087 4350 GIM_Try, /*On fail goto*//*Label 395*/ 9123, // Rule ID 541 // 4351 GIM_CheckFeatures, GIFBS_HasP9Altivec, 4352 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vprtybq, 4353 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 4354 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 4355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4356 // (intrinsic_wo_chain:{ *:[v1i128] } 7356:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$vB) => (VPRTYBQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vB) 4357 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VPRTYBQ, 4358 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4359 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4360 GIR_EraseFromParent, /*InsnID*/0, 4361 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4362 // GIR_Coverage, 541, 4363 GIR_Done, 4364 // Label 395: @9123 4365 GIM_Try, /*On fail goto*//*Label 396*/ 9157, // Rule ID 685 // 4366 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_popcntb, 4367 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 4368 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 4370 // (intrinsic_wo_chain:{ *:[i64] } 7603:{ *:[iPTR] }, i64:{ *:[i64] }:$rS) => (POPCNTB8:{ *:[i64] } i64:{ *:[i64] }:$rS) 4371 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::POPCNTB8, 4372 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 4373 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rS 4374 GIR_EraseFromParent, /*InsnID*/0, 4375 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4376 // GIR_Coverage, 685, 4377 GIR_Done, 4378 // Label 396: @9157 4379 GIM_Try, /*On fail goto*//*Label 397*/ 9193, // Rule ID 1040 // 4380 GIM_CheckFeatures, GIFBS_IsISA3_1, 4381 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vstribr, 4382 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 4383 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 4384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4385 // (intrinsic_wo_chain:{ *:[v16i8] } 7394:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vB) => (VSTRIBR:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vB) 4386 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSTRIBR, 4387 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 4388 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4389 GIR_EraseFromParent, /*InsnID*/0, 4390 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4391 // GIR_Coverage, 1040, 4392 GIR_Done, 4393 // Label 397: @9193 4394 GIM_Try, /*On fail goto*//*Label 398*/ 9229, // Rule ID 1041 // 4395 GIM_CheckFeatures, GIFBS_IsISA3_1, 4396 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vstribl, 4397 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 4398 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 4399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4400 // (intrinsic_wo_chain:{ *:[v16i8] } 7392:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vB) => (VSTRIBL:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vB) 4401 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSTRIBL, 4402 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 4403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4404 GIR_EraseFromParent, /*InsnID*/0, 4405 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4406 // GIR_Coverage, 1041, 4407 GIR_Done, 4408 // Label 398: @9229 4409 GIM_Try, /*On fail goto*//*Label 399*/ 9265, // Rule ID 1042 // 4410 GIM_CheckFeatures, GIFBS_IsISA3_1, 4411 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vstrihr, 4412 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 4413 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 4414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4415 // (intrinsic_wo_chain:{ *:[v8i16] } 7398:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vB) => (VSTRIHR:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vB) 4416 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSTRIHR, 4417 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 4418 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4419 GIR_EraseFromParent, /*InsnID*/0, 4420 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4421 // GIR_Coverage, 1042, 4422 GIR_Done, 4423 // Label 399: @9265 4424 GIM_Try, /*On fail goto*//*Label 400*/ 9301, // Rule ID 1043 // 4425 GIM_CheckFeatures, GIFBS_IsISA3_1, 4426 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vstrihl, 4427 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 4428 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 4429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4430 // (intrinsic_wo_chain:{ *:[v8i16] } 7396:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vB) => (VSTRIHL:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vB) 4431 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSTRIHL, 4432 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 4433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4434 GIR_EraseFromParent, /*InsnID*/0, 4435 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4436 // GIR_Coverage, 1043, 4437 GIR_Done, 4438 // Label 400: @9301 4439 GIM_Try, /*On fail goto*//*Label 401*/ 9337, // Rule ID 1060 // 4440 GIM_CheckFeatures, GIFBS_IsISA3_1, 4441 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vextractbm, 4442 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 4443 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 4444 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 4445 // (intrinsic_wo_chain:{ *:[i32] } 7261:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vB) => (VEXTRACTBM:{ *:[i32] } v16i8:{ *:[v16i8] }:$vB) 4446 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXTRACTBM, 4447 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rD 4448 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4449 GIR_EraseFromParent, /*InsnID*/0, 4450 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4451 // GIR_Coverage, 1060, 4452 GIR_Done, 4453 // Label 401: @9337 4454 GIM_Try, /*On fail goto*//*Label 402*/ 9373, // Rule ID 1061 // 4455 GIM_CheckFeatures, GIFBS_IsISA3_1, 4456 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vextracthm, 4457 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 4458 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 4459 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 4460 // (intrinsic_wo_chain:{ *:[i32] } 7263:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vB) => (VEXTRACTHM:{ *:[i32] } v8i16:{ *:[v8i16] }:$vB) 4461 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXTRACTHM, 4462 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rD 4463 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4464 GIR_EraseFromParent, /*InsnID*/0, 4465 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4466 // GIR_Coverage, 1061, 4467 GIR_Done, 4468 // Label 402: @9373 4469 GIM_Try, /*On fail goto*//*Label 403*/ 9409, // Rule ID 1062 // 4470 GIM_CheckFeatures, GIFBS_IsISA3_1, 4471 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vextractwm, 4472 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 4473 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 4475 // (intrinsic_wo_chain:{ *:[i32] } 7265:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vB) => (VEXTRACTWM:{ *:[i32] } v4i32:{ *:[v4i32] }:$vB) 4476 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXTRACTWM, 4477 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rD 4478 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4479 GIR_EraseFromParent, /*InsnID*/0, 4480 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4481 // GIR_Coverage, 1062, 4482 GIR_Done, 4483 // Label 403: @9409 4484 GIM_Try, /*On fail goto*//*Label 404*/ 9445, // Rule ID 1063 // 4485 GIM_CheckFeatures, GIFBS_IsISA3_1, 4486 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vextractdm, 4487 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 4488 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 4489 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 4490 // (intrinsic_wo_chain:{ *:[i32] } 7262:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vB) => (VEXTRACTDM:{ *:[i32] } v2i64:{ *:[v2i64] }:$vB) 4491 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXTRACTDM, 4492 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rD 4493 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4494 GIR_EraseFromParent, /*InsnID*/0, 4495 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4496 // GIR_Coverage, 1063, 4497 GIR_Done, 4498 // Label 404: @9445 4499 GIM_Try, /*On fail goto*//*Label 405*/ 9481, // Rule ID 1064 // 4500 GIM_CheckFeatures, GIFBS_IsISA3_1, 4501 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vextractqm, 4502 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 4503 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 4504 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 4505 // (intrinsic_wo_chain:{ *:[i32] } 7264:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$vB) => (VEXTRACTQM:{ *:[i32] } v1i128:{ *:[v1i128] }:$vB) 4506 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXTRACTQM, 4507 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rD 4508 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4509 GIR_EraseFromParent, /*InsnID*/0, 4510 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4511 // GIR_Coverage, 1064, 4512 GIR_Done, 4513 // Label 405: @9481 4514 GIM_Try, /*On fail goto*//*Label 406*/ 9517, // Rule ID 1065 // 4515 GIM_CheckFeatures, GIFBS_IsISA3_1, 4516 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vexpandbm, 4517 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 4518 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 4519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4520 // (intrinsic_wo_chain:{ *:[v16i8] } 7247:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vB) => (VEXPANDBM:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vB) 4521 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXPANDBM, 4522 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4523 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4524 GIR_EraseFromParent, /*InsnID*/0, 4525 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4526 // GIR_Coverage, 1065, 4527 GIR_Done, 4528 // Label 406: @9517 4529 GIM_Try, /*On fail goto*//*Label 407*/ 9553, // Rule ID 1066 // 4530 GIM_CheckFeatures, GIFBS_IsISA3_1, 4531 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vexpandhm, 4532 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 4533 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 4534 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4535 // (intrinsic_wo_chain:{ *:[v8i16] } 7249:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vB) => (VEXPANDHM:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vB) 4536 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXPANDHM, 4537 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4538 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4539 GIR_EraseFromParent, /*InsnID*/0, 4540 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4541 // GIR_Coverage, 1066, 4542 GIR_Done, 4543 // Label 407: @9553 4544 GIM_Try, /*On fail goto*//*Label 408*/ 9589, // Rule ID 1067 // 4545 GIM_CheckFeatures, GIFBS_IsISA3_1, 4546 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vexpandwm, 4547 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4548 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4549 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4550 // (intrinsic_wo_chain:{ *:[v4i32] } 7251:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vB) => (VEXPANDWM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB) 4551 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXPANDWM, 4552 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4553 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4554 GIR_EraseFromParent, /*InsnID*/0, 4555 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4556 // GIR_Coverage, 1067, 4557 GIR_Done, 4558 // Label 408: @9589 4559 GIM_Try, /*On fail goto*//*Label 409*/ 9625, // Rule ID 1068 // 4560 GIM_CheckFeatures, GIFBS_IsISA3_1, 4561 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vexpanddm, 4562 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4563 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 4564 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4565 // (intrinsic_wo_chain:{ *:[v2i64] } 7248:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vB) => (VEXPANDDM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vB) 4566 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXPANDDM, 4567 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4568 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4569 GIR_EraseFromParent, /*InsnID*/0, 4570 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4571 // GIR_Coverage, 1068, 4572 GIR_Done, 4573 // Label 409: @9625 4574 GIM_Try, /*On fail goto*//*Label 410*/ 9661, // Rule ID 1069 // 4575 GIM_CheckFeatures, GIFBS_IsISA3_1, 4576 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vexpandqm, 4577 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 4578 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 4579 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4580 // (intrinsic_wo_chain:{ *:[v1i128] } 7250:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$vB) => (VEXPANDQM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vB) 4581 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXPANDQM, 4582 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4583 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4584 GIR_EraseFromParent, /*InsnID*/0, 4585 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4586 // GIR_Coverage, 1069, 4587 GIR_Done, 4588 // Label 410: @9661 4589 GIM_Try, /*On fail goto*//*Label 411*/ 9697, // Rule ID 1070 // 4590 GIM_CheckFeatures, GIFBS_IsISA3_1, 4591 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_mtvsrbm, 4592 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 4593 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4594 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4595 // (intrinsic_wo_chain:{ *:[v16i8] } 7145:{ *:[iPTR] }, i64:{ *:[i64] }:$rB) => (MTVSRBM:{ *:[v16i8] } i64:{ *:[i64] }:$rB) 4596 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MTVSRBM, 4597 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4598 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rB 4599 GIR_EraseFromParent, /*InsnID*/0, 4600 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4601 // GIR_Coverage, 1070, 4602 GIR_Done, 4603 // Label 411: @9697 4604 GIM_Try, /*On fail goto*//*Label 412*/ 9733, // Rule ID 1071 // 4605 GIM_CheckFeatures, GIFBS_IsISA3_1, 4606 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_mtvsrhm, 4607 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 4608 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4609 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4610 // (intrinsic_wo_chain:{ *:[v8i16] } 7147:{ *:[iPTR] }, i64:{ *:[i64] }:$rB) => (MTVSRHM:{ *:[v8i16] } i64:{ *:[i64] }:$rB) 4611 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MTVSRHM, 4612 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4613 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rB 4614 GIR_EraseFromParent, /*InsnID*/0, 4615 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4616 // GIR_Coverage, 1071, 4617 GIR_Done, 4618 // Label 412: @9733 4619 GIM_Try, /*On fail goto*//*Label 413*/ 9769, // Rule ID 1072 // 4620 GIM_CheckFeatures, GIFBS_IsISA3_1, 4621 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_mtvsrwm, 4622 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4623 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4624 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4625 // (intrinsic_wo_chain:{ *:[v4i32] } 7149:{ *:[iPTR] }, i64:{ *:[i64] }:$rB) => (MTVSRWM:{ *:[v4i32] } i64:{ *:[i64] }:$rB) 4626 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MTVSRWM, 4627 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4628 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rB 4629 GIR_EraseFromParent, /*InsnID*/0, 4630 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4631 // GIR_Coverage, 1072, 4632 GIR_Done, 4633 // Label 413: @9769 4634 GIM_Try, /*On fail goto*//*Label 414*/ 9805, // Rule ID 1073 // 4635 GIM_CheckFeatures, GIFBS_IsISA3_1, 4636 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_mtvsrdm, 4637 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4638 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4639 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4640 // (intrinsic_wo_chain:{ *:[v2i64] } 7146:{ *:[iPTR] }, i64:{ *:[i64] }:$rB) => (MTVSRDM:{ *:[v2i64] } i64:{ *:[i64] }:$rB) 4641 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MTVSRDM, 4642 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4643 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rB 4644 GIR_EraseFromParent, /*InsnID*/0, 4645 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4646 // GIR_Coverage, 1073, 4647 GIR_Done, 4648 // Label 414: @9805 4649 GIM_Try, /*On fail goto*//*Label 415*/ 9841, // Rule ID 1074 // 4650 GIM_CheckFeatures, GIFBS_IsISA3_1, 4651 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_mtvsrqm, 4652 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 4653 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4654 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4655 // (intrinsic_wo_chain:{ *:[v1i128] } 7148:{ *:[iPTR] }, i64:{ *:[i64] }:$rB) => (MTVSRQM:{ *:[v1i128] } i64:{ *:[i64] }:$rB) 4656 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MTVSRQM, 4657 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4658 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rB 4659 GIR_EraseFromParent, /*InsnID*/0, 4660 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4661 // GIR_Coverage, 1074, 4662 GIR_Done, 4663 // Label 415: @9841 4664 GIM_Try, /*On fail goto*//*Label 416*/ 9877, // Rule ID 1138 // 4665 GIM_CheckFeatures, GIFBS_IsISA3_1, 4666 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vextsd2q, 4667 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 4668 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 4669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4670 // (intrinsic_wo_chain:{ *:[v1i128] } 7268:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vB) => (VEXTSD2Q:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$vB) 4671 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXTSD2Q, 4672 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 4673 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 4674 GIR_EraseFromParent, /*InsnID*/0, 4675 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4676 // GIR_Coverage, 1138, 4677 GIR_Done, 4678 // Label 416: @9877 4679 GIM_Try, /*On fail goto*//*Label 417*/ 9913, // Rule ID 1143 // 4680 GIM_CheckFeatures, GIFBS_IsNotISAFuture_MMA, 4681 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_mma_xxmfacc, 4682 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v512s1, 4683 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v512s1, 4684 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::ACCRCRegClassID, 4685 // (intrinsic_wo_chain:{ *:[v512i1] } 7586:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$AS) => (XXMFACC:{ *:[v512i1] } v512i1:{ *:[v512i1] }:$AS) 4686 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XXMFACC, 4687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // ASo 4688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // AS 4689 GIR_EraseFromParent, /*InsnID*/0, 4690 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4691 // GIR_Coverage, 1143, 4692 GIR_Done, 4693 // Label 417: @9913 4694 GIM_Try, /*On fail goto*//*Label 418*/ 9949, // Rule ID 1144 // 4695 GIM_CheckFeatures, GIFBS_IsNotISAFuture_MMA, 4696 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_mma_xxmtacc, 4697 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v512s1, 4698 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v512s1, 4699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::ACCRCRegClassID, 4700 // (intrinsic_wo_chain:{ *:[v512i1] } 7587:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi) => (XXMTACC:{ *:[v512i1] } v512i1:{ *:[v512i1] }:$ATi) 4701 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XXMTACC, 4702 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // AT 4703 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ATi 4704 GIR_EraseFromParent, /*InsnID*/0, 4705 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4706 // GIR_Coverage, 1144, 4707 GIR_Done, 4708 // Label 418: @9949 4709 GIM_Reject, 4710 // Label 348: @9950 4711 GIM_Try, /*On fail goto*//*Label 419*/ 16529, 4712 GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, 4713 GIM_Try, /*On fail goto*//*Label 420*/ 9998, // Rule ID 1013 // 4714 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 4715 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvtstdcsp, 4716 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4717 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4718 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 4719 // MIs[0] DCMX 4720 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 4721 // (intrinsic_wo_chain:{ *:[v4i32] } 7711:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB, (timm:{ *:[i32] }):$DCMX) => (XVTSTDCSP:{ *:[v4i32] } (timm:{ *:[i32] }):$DCMX, v4f32:{ *:[v4f32] }:$XB) 4722 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVTSTDCSP, 4723 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 4724 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // DCMX 4725 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 4726 GIR_EraseFromParent, /*InsnID*/0, 4727 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4728 // GIR_Coverage, 1013, 4729 GIR_Done, 4730 // Label 420: @9998 4731 GIM_Try, /*On fail goto*//*Label 421*/ 10041, // Rule ID 1014 // 4732 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 4733 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvtstdcdp, 4734 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4735 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 4736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 4737 // MIs[0] DCMX 4738 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 4739 // (intrinsic_wo_chain:{ *:[v2i64] } 7710:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB, (timm:{ *:[i32] }):$DCMX) => (XVTSTDCDP:{ *:[v2i64] } (timm:{ *:[i32] }):$DCMX, v2f64:{ *:[v2f64] }:$XB) 4740 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVTSTDCDP, 4741 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 4742 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // DCMX 4743 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 4744 GIR_EraseFromParent, /*InsnID*/0, 4745 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4746 // GIR_Coverage, 1014, 4747 GIR_Done, 4748 // Label 421: @10041 4749 GIM_Try, /*On fail goto*//*Label 422*/ 10093, // Rule ID 890 // 4750 GIM_CheckFeatures, GIFBS_HasVSX, 4751 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xsmaxdp, 4752 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 4753 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4754 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 4755 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 4756 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/PPC::VSFRCRegClassID, 4757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/PPC::VSFRCRegClassID, 4758 // (intrinsic_wo_chain:{ *:[f64] } 7663:{ *:[iPTR] }, vsfrc:{ *:[f64] }:$XA, vsfrc:{ *:[f64] }:$XB) => (XSMAXDP:{ *:[f64] } vsfrc:{ *:[f64] }:$XA, vsfrc:{ *:[f64] }:$XB) 4759 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSMAXDP, 4760 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 4761 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XA 4762 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XB 4763 GIR_EraseFromParent, /*InsnID*/0, 4764 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4765 // GIR_Coverage, 890, 4766 GIR_Done, 4767 // Label 422: @10093 4768 GIM_Try, /*On fail goto*//*Label 423*/ 10145, // Rule ID 891 // 4769 GIM_CheckFeatures, GIFBS_HasVSX, 4770 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xsmindp, 4771 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 4772 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4773 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 4774 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 4775 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/PPC::VSFRCRegClassID, 4776 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/PPC::VSFRCRegClassID, 4777 // (intrinsic_wo_chain:{ *:[f64] } 7664:{ *:[iPTR] }, vsfrc:{ *:[f64] }:$XA, vsfrc:{ *:[f64] }:$XB) => (XSMINDP:{ *:[f64] } vsfrc:{ *:[f64] }:$XA, vsfrc:{ *:[f64] }:$XB) 4778 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSMINDP, 4779 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 4780 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XA 4781 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XB 4782 GIR_EraseFromParent, /*InsnID*/0, 4783 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4784 // GIR_Coverage, 891, 4785 GIR_Done, 4786 // Label 423: @10145 4787 GIM_Try, /*On fail goto*//*Label 424*/ 10197, // Rule ID 892 // 4788 GIM_CheckFeatures, GIFBS_HasVSX, 4789 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvmaxdp, 4790 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4791 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 4792 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 4793 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 4794 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/PPC::VSRCRegClassID, 4795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/PPC::VSRCRegClassID, 4796 // (intrinsic_wo_chain:{ *:[v2f64] } 7695:{ *:[iPTR] }, vsrc:{ *:[v2f64] }:$XA, vsrc:{ *:[v2f64] }:$XB) => (XVMAXDP:{ *:[v2f64] } vsrc:{ *:[v2f64] }:$XA, vsrc:{ *:[v2f64] }:$XB) 4797 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVMAXDP, 4798 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 4799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XA 4800 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XB 4801 GIR_EraseFromParent, /*InsnID*/0, 4802 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4803 // GIR_Coverage, 892, 4804 GIR_Done, 4805 // Label 424: @10197 4806 GIM_Try, /*On fail goto*//*Label 425*/ 10249, // Rule ID 893 // 4807 GIM_CheckFeatures, GIFBS_HasVSX, 4808 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvmindp, 4809 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4810 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 4811 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 4812 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 4813 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/PPC::VSRCRegClassID, 4814 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/PPC::VSRCRegClassID, 4815 // (intrinsic_wo_chain:{ *:[v2f64] } 7697:{ *:[iPTR] }, vsrc:{ *:[v2f64] }:$XA, vsrc:{ *:[v2f64] }:$XB) => (XVMINDP:{ *:[v2f64] } vsrc:{ *:[v2f64] }:$XA, vsrc:{ *:[v2f64] }:$XB) 4816 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVMINDP, 4817 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 4818 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XA 4819 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XB 4820 GIR_EraseFromParent, /*InsnID*/0, 4821 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4822 // GIR_Coverage, 893, 4823 GIR_Done, 4824 // Label 425: @10249 4825 GIM_Try, /*On fail goto*//*Label 426*/ 10301, // Rule ID 894 // 4826 GIM_CheckFeatures, GIFBS_HasVSX, 4827 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvmaxsp, 4828 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4829 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4830 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 4831 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 4832 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/PPC::VSRCRegClassID, 4833 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/PPC::VSRCRegClassID, 4834 // (intrinsic_wo_chain:{ *:[v4f32] } 7696:{ *:[iPTR] }, vsrc:{ *:[v4f32] }:$XA, vsrc:{ *:[v4f32] }:$XB) => (XVMAXSP:{ *:[v4f32] } vsrc:{ *:[v4f32] }:$XA, vsrc:{ *:[v4f32] }:$XB) 4835 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVMAXSP, 4836 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 4837 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XA 4838 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XB 4839 GIR_EraseFromParent, /*InsnID*/0, 4840 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4841 // GIR_Coverage, 894, 4842 GIR_Done, 4843 // Label 426: @10301 4844 GIM_Try, /*On fail goto*//*Label 427*/ 10353, // Rule ID 895 // 4845 GIM_CheckFeatures, GIFBS_HasVSX, 4846 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvminsp, 4847 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4848 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4849 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 4850 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 4851 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/PPC::VSRCRegClassID, 4852 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/PPC::VSRCRegClassID, 4853 // (intrinsic_wo_chain:{ *:[v4f32] } 7698:{ *:[iPTR] }, vsrc:{ *:[v4f32] }:$XA, vsrc:{ *:[v4f32] }:$XB) => (XVMINSP:{ *:[v4f32] } vsrc:{ *:[v4f32] }:$XA, vsrc:{ *:[v4f32] }:$XB) 4854 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVMINSP, 4855 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 4856 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XA 4857 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XB 4858 GIR_EraseFromParent, /*InsnID*/0, 4859 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4860 // GIR_Coverage, 895, 4861 GIR_Done, 4862 // Label 427: @10353 4863 GIM_Try, /*On fail goto*//*Label 428*/ 10397, // Rule ID 819 // 4864 GIM_CheckFeatures, GIFBS_HasVSX, 4865 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvcmpeqdp, 4866 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4867 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 4868 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 4869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 4870 // (intrinsic_wo_chain:{ *:[v2i64] } 7665:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVCMPEQDP:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) 4871 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVCMPEQDP, 4872 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 4873 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XA 4874 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XB 4875 GIR_EraseFromParent, /*InsnID*/0, 4876 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4877 // GIR_Coverage, 819, 4878 GIR_Done, 4879 // Label 428: @10397 4880 GIM_Try, /*On fail goto*//*Label 429*/ 10441, // Rule ID 821 // 4881 GIM_CheckFeatures, GIFBS_HasVSX, 4882 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvcmpeqsp, 4883 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4884 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4885 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 4886 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 4887 // (intrinsic_wo_chain:{ *:[v4i32] } 7667:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVCMPEQSP:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) 4888 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVCMPEQSP, 4889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 4890 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XA 4891 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XB 4892 GIR_EraseFromParent, /*InsnID*/0, 4893 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4894 // GIR_Coverage, 821, 4895 GIR_Done, 4896 // Label 429: @10441 4897 GIM_Try, /*On fail goto*//*Label 430*/ 10485, // Rule ID 823 // 4898 GIM_CheckFeatures, GIFBS_HasVSX, 4899 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvcmpgedp, 4900 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4901 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 4902 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 4903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 4904 // (intrinsic_wo_chain:{ *:[v2i64] } 7669:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVCMPGEDP:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) 4905 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVCMPGEDP, 4906 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 4907 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XA 4908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XB 4909 GIR_EraseFromParent, /*InsnID*/0, 4910 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4911 // GIR_Coverage, 823, 4912 GIR_Done, 4913 // Label 430: @10485 4914 GIM_Try, /*On fail goto*//*Label 431*/ 10529, // Rule ID 825 // 4915 GIM_CheckFeatures, GIFBS_HasVSX, 4916 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvcmpgesp, 4917 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4918 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4919 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 4920 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 4921 // (intrinsic_wo_chain:{ *:[v4i32] } 7671:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVCMPGESP:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) 4922 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVCMPGESP, 4923 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 4924 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XA 4925 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XB 4926 GIR_EraseFromParent, /*InsnID*/0, 4927 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4928 // GIR_Coverage, 825, 4929 GIR_Done, 4930 // Label 431: @10529 4931 GIM_Try, /*On fail goto*//*Label 432*/ 10573, // Rule ID 827 // 4932 GIM_CheckFeatures, GIFBS_HasVSX, 4933 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvcmpgtdp, 4934 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4935 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 4936 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 4937 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 4938 // (intrinsic_wo_chain:{ *:[v2i64] } 7673:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVCMPGTDP:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) 4939 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVCMPGTDP, 4940 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 4941 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XA 4942 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XB 4943 GIR_EraseFromParent, /*InsnID*/0, 4944 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4945 // GIR_Coverage, 827, 4946 GIR_Done, 4947 // Label 432: @10573 4948 GIM_Try, /*On fail goto*//*Label 433*/ 10617, // Rule ID 829 // 4949 GIM_CheckFeatures, GIFBS_HasVSX, 4950 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xvcmpgtsp, 4951 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4952 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4953 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 4954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 4955 // (intrinsic_wo_chain:{ *:[v4i32] } 7675:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVCMPGTSP:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) 4956 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVCMPGTSP, 4957 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 4958 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XA 4959 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XB 4960 GIR_EraseFromParent, /*InsnID*/0, 4961 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4962 // GIR_Coverage, 829, 4963 GIR_Done, 4964 // Label 433: @10617 4965 GIM_Try, /*On fail goto*//*Label 434*/ 10661, // Rule ID 993 // 4966 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 4967 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_addf128_round_to_odd, 4968 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 4969 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 4970 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s128, 4971 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4972 // (intrinsic_wo_chain:{ *:[f128] } 7116:{ *:[iPTR] }, f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) => (XSADDQPO:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 4973 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSADDQPO, 4974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 4975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 4976 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 4977 GIR_EraseFromParent, /*InsnID*/0, 4978 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4979 // GIR_Coverage, 993, 4980 GIR_Done, 4981 // Label 434: @10661 4982 GIM_Try, /*On fail goto*//*Label 435*/ 10705, // Rule ID 994 // 4983 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 4984 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_mulf128_round_to_odd, 4985 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 4986 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 4987 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s128, 4988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 4989 // (intrinsic_wo_chain:{ *:[f128] } 7595:{ *:[iPTR] }, f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) => (XSMULQPO:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 4990 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSMULQPO, 4991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 4992 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 4993 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 4994 GIR_EraseFromParent, /*InsnID*/0, 4995 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4996 // GIR_Coverage, 994, 4997 GIR_Done, 4998 // Label 435: @10705 4999 GIM_Try, /*On fail goto*//*Label 436*/ 10749, // Rule ID 995 // 5000 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 5001 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_subf128_round_to_odd, 5002 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 5003 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 5004 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s128, 5005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5006 // (intrinsic_wo_chain:{ *:[f128] } 7623:{ *:[iPTR] }, f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) => (XSSUBQPO:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 5007 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSSUBQPO, 5008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 5009 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5011 GIR_EraseFromParent, /*InsnID*/0, 5012 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5013 // GIR_Coverage, 995, 5014 GIR_Done, 5015 // Label 436: @10749 5016 GIM_Try, /*On fail goto*//*Label 437*/ 10793, // Rule ID 996 // 5017 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 5018 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_divf128_round_to_odd, 5019 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 5020 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 5021 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s128, 5022 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5023 // (intrinsic_wo_chain:{ *:[f128] } 7472:{ *:[iPTR] }, f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) => (XSDIVQPO:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 5024 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSDIVQPO, 5025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 5026 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5027 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5028 GIR_EraseFromParent, /*InsnID*/0, 5029 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5030 // GIR_Coverage, 996, 5031 GIR_Done, 5032 // Label 437: @10793 5033 GIM_Try, /*On fail goto*//*Label 438*/ 10837, // Rule ID 1007 // 5034 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 5035 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xviexpdp, 5036 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 5037 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 5038 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 5039 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 5040 // (intrinsic_wo_chain:{ *:[v2f64] } 7693:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$XA, v2i64:{ *:[v2i64] }:$XB) => (XVIEXPDP:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$XA, v2i64:{ *:[v2i64] }:$XB) 5041 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVIEXPDP, 5042 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 5043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XA 5044 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XB 5045 GIR_EraseFromParent, /*InsnID*/0, 5046 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5047 // GIR_Coverage, 1007, 5048 GIR_Done, 5049 // Label 438: @10837 5050 GIM_Try, /*On fail goto*//*Label 439*/ 10881, // Rule ID 1008 // 5051 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 5052 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xviexpsp, 5053 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5054 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5055 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 5056 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 5057 // (intrinsic_wo_chain:{ *:[v4f32] } 7694:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) => (XVIEXPSP:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) 5058 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVIEXPSP, 5059 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 5060 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XA 5061 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XB 5062 GIR_EraseFromParent, /*InsnID*/0, 5063 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5064 // GIR_Coverage, 1008, 5065 GIR_Done, 5066 // Label 439: @10881 5067 GIM_Try, /*On fail goto*//*Label 440*/ 10921, // Rule ID 313 // 5068 GIM_CheckFeatures, GIFBS_HasAltivec, 5069 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vcfsx, 5070 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5071 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5072 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5073 // MIs[0] Operand 3 5074 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, 0, 5075 // (intrinsic_wo_chain:{ *:[v4f32] } 7176:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vB, 0:{ *:[i32] }) => (VCFSX_0:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$vB) 5076 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VCFSX_0, 5077 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5078 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 5079 GIR_EraseFromParent, /*InsnID*/0, 5080 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5081 // GIR_Coverage, 313, 5082 GIR_Done, 5083 // Label 440: @10921 5084 GIM_Try, /*On fail goto*//*Label 441*/ 10961, // Rule ID 314 // 5085 GIM_CheckFeatures, GIFBS_HasAltivec, 5086 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vctuxs, 5087 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5088 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5090 // MIs[0] Operand 3 5091 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, 0, 5092 // (intrinsic_wo_chain:{ *:[v4i32] } 7238:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$vB, 0:{ *:[i32] }) => (VCTUXS_0:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$vB) 5093 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VCTUXS_0, 5094 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5095 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 5096 GIR_EraseFromParent, /*InsnID*/0, 5097 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5098 // GIR_Coverage, 314, 5099 GIR_Done, 5100 // Label 441: @10961 5101 GIM_Try, /*On fail goto*//*Label 442*/ 11001, // Rule ID 315 // 5102 GIM_CheckFeatures, GIFBS_HasAltivec, 5103 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vcfux, 5104 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5105 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5107 // MIs[0] Operand 3 5108 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, 0, 5109 // (intrinsic_wo_chain:{ *:[v4f32] } 7178:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vB, 0:{ *:[i32] }) => (VCFUX_0:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$vB) 5110 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VCFUX_0, 5111 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5112 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 5113 GIR_EraseFromParent, /*InsnID*/0, 5114 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5115 // GIR_Coverage, 315, 5116 GIR_Done, 5117 // Label 442: @11001 5118 GIM_Try, /*On fail goto*//*Label 443*/ 11041, // Rule ID 316 // 5119 GIM_CheckFeatures, GIFBS_HasAltivec, 5120 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vctsxs, 5121 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5122 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5123 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5124 // MIs[0] Operand 3 5125 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, 0, 5126 // (intrinsic_wo_chain:{ *:[v4i32] } 7237:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$vB, 0:{ *:[i32] }) => (VCTSXS_0:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$vB) 5127 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VCTSXS_0, 5128 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5129 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 5130 GIR_EraseFromParent, /*InsnID*/0, 5131 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5132 // GIR_Coverage, 316, 5133 GIR_Done, 5134 // Label 443: @11041 5135 GIM_Try, /*On fail goto*//*Label 444*/ 11084, // Rule ID 309 // 5136 GIM_CheckFeatures, GIFBS_HasAltivec, 5137 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vcfsx, 5138 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5139 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5140 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5141 // MIs[0] UIMM 5142 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 5143 // (intrinsic_wo_chain:{ *:[v4f32] } 7176:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vB, (timm:{ *:[i32] }):$UIMM) => (VCFSX:{ *:[v4f32] } (timm:{ *:[i32] }):$UIMM, v4i32:{ *:[v4i32] }:$vB) 5144 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VCFSX, 5145 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5146 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // UIMM 5147 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 5148 GIR_EraseFromParent, /*InsnID*/0, 5149 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5150 // GIR_Coverage, 309, 5151 GIR_Done, 5152 // Label 444: @11084 5153 GIM_Try, /*On fail goto*//*Label 445*/ 11127, // Rule ID 310 // 5154 GIM_CheckFeatures, GIFBS_HasAltivec, 5155 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vcfux, 5156 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5157 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5159 // MIs[0] UIMM 5160 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 5161 // (intrinsic_wo_chain:{ *:[v4f32] } 7178:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vB, (timm:{ *:[i32] }):$UIMM) => (VCFUX:{ *:[v4f32] } (timm:{ *:[i32] }):$UIMM, v4i32:{ *:[v4i32] }:$vB) 5162 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VCFUX, 5163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5164 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // UIMM 5165 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 5166 GIR_EraseFromParent, /*InsnID*/0, 5167 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5168 // GIR_Coverage, 310, 5169 GIR_Done, 5170 // Label 445: @11127 5171 GIM_Try, /*On fail goto*//*Label 446*/ 11170, // Rule ID 311 // 5172 GIM_CheckFeatures, GIFBS_HasAltivec, 5173 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vctsxs, 5174 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5175 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5177 // MIs[0] UIMM 5178 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 5179 // (intrinsic_wo_chain:{ *:[v4i32] } 7237:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$vB, (timm:{ *:[i32] }):$UIMM) => (VCTSXS:{ *:[v4i32] } (timm:{ *:[i32] }):$UIMM, v4f32:{ *:[v4f32] }:$vB) 5180 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VCTSXS, 5181 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5182 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // UIMM 5183 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 5184 GIR_EraseFromParent, /*InsnID*/0, 5185 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5186 // GIR_Coverage, 311, 5187 GIR_Done, 5188 // Label 446: @11170 5189 GIM_Try, /*On fail goto*//*Label 447*/ 11213, // Rule ID 312 // 5190 GIM_CheckFeatures, GIFBS_HasAltivec, 5191 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vctuxs, 5192 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5193 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5194 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5195 // MIs[0] UIMM 5196 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 5197 // (intrinsic_wo_chain:{ *:[v4i32] } 7238:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$vB, (timm:{ *:[i32] }):$UIMM) => (VCTUXS:{ *:[v4i32] } (timm:{ *:[i32] }):$UIMM, v4f32:{ *:[v4f32] }:$vB) 5198 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VCTUXS, 5199 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5200 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // UIMM 5201 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 5202 GIR_EraseFromParent, /*InsnID*/0, 5203 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5204 // GIR_Coverage, 312, 5205 GIR_Done, 5206 // Label 447: @11213 5207 GIM_Try, /*On fail goto*//*Label 448*/ 11256, // Rule ID 1076 // 5208 GIM_CheckFeatures, GIFBS_IsISA3_1, 5209 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vcntmbb, 5210 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 5211 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 5212 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 5213 // MIs[0] MP 5214 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 5215 // (intrinsic_wo_chain:{ *:[i64] } 7233:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vB, (timm:{ *:[i32] }):$MP) => (VCNTMBB:{ *:[i64] } v16i8:{ *:[v16i8] }:$vB, (timm:{ *:[i32] }):$MP) 5216 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VCNTMBB, 5217 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rD 5218 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 5219 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // MP 5220 GIR_EraseFromParent, /*InsnID*/0, 5221 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5222 // GIR_Coverage, 1076, 5223 GIR_Done, 5224 // Label 448: @11256 5225 GIM_Try, /*On fail goto*//*Label 449*/ 11299, // Rule ID 1077 // 5226 GIM_CheckFeatures, GIFBS_IsISA3_1, 5227 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vcntmbh, 5228 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 5229 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 5230 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 5231 // MIs[0] MP 5232 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 5233 // (intrinsic_wo_chain:{ *:[i64] } 7235:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vB, (timm:{ *:[i32] }):$MP) => (VCNTMBH:{ *:[i64] } v8i16:{ *:[v8i16] }:$vB, (timm:{ *:[i32] }):$MP) 5234 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VCNTMBH, 5235 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rD 5236 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 5237 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // MP 5238 GIR_EraseFromParent, /*InsnID*/0, 5239 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5240 // GIR_Coverage, 1077, 5241 GIR_Done, 5242 // Label 449: @11299 5243 GIM_Try, /*On fail goto*//*Label 450*/ 11342, // Rule ID 1078 // 5244 GIM_CheckFeatures, GIFBS_IsISA3_1, 5245 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vcntmbw, 5246 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 5247 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5248 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 5249 // MIs[0] MP 5250 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 5251 // (intrinsic_wo_chain:{ *:[i64] } 7236:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vB, (timm:{ *:[i32] }):$MP) => (VCNTMBW:{ *:[i64] } v4i32:{ *:[v4i32] }:$vB, (timm:{ *:[i32] }):$MP) 5252 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VCNTMBW, 5253 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rD 5254 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 5255 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // MP 5256 GIR_EraseFromParent, /*InsnID*/0, 5257 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5258 // GIR_Coverage, 1078, 5259 GIR_Done, 5260 // Label 450: @11342 5261 GIM_Try, /*On fail goto*//*Label 451*/ 11385, // Rule ID 1079 // 5262 GIM_CheckFeatures, GIFBS_IsISA3_1, 5263 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vcntmbd, 5264 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 5265 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 5266 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 5267 // MIs[0] MP 5268 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 5269 // (intrinsic_wo_chain:{ *:[i64] } 7234:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vB, (timm:{ *:[i32] }):$MP) => (VCNTMBD:{ *:[i64] } v2i64:{ *:[v2i64] }:$vB, (timm:{ *:[i32] }):$MP) 5270 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VCNTMBD, 5271 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rD 5272 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 5273 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // MP 5274 GIR_EraseFromParent, /*InsnID*/0, 5275 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5276 // GIR_Coverage, 1079, 5277 GIR_Done, 5278 // Label 451: @11385 5279 GIM_Try, /*On fail goto*//*Label 452*/ 11428, // Rule ID 1093 // 5280 GIM_CheckFeatures, GIFBS_IsISA3_1, 5281 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vgnb, 5282 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 5283 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 5284 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 5285 // MIs[0] N 5286 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 5287 // (intrinsic_wo_chain:{ *:[i64] } 7273:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$vB, (timm:{ *:[i32] }):$N) => (VGNB:{ *:[i64] } v1i128:{ *:[v1i128] }:$vB, (timm:{ *:[i32] }):$N) 5288 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VGNB, 5289 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rD 5290 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 5291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // N 5292 GIR_EraseFromParent, /*InsnID*/0, 5293 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5294 // GIR_Coverage, 1093, 5295 GIR_Done, 5296 // Label 452: @11428 5297 GIM_Try, /*On fail goto*//*Label 453*/ 11480, // Rule ID 201 // 5298 GIM_CheckFeatures, GIFBS_HasExtDiv, 5299 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_divwe, 5300 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 5301 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5302 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5303 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 5304 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/PPC::GPRCRegClassID, 5305 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/PPC::GPRCRegClassID, 5306 // (intrinsic_wo_chain:{ *:[i32] } 7473:{ *:[iPTR] }, gprc:{ *:[i32] }:$rA, gprc:{ *:[i32] }:$rB) => (DIVWE:{ *:[i32] } gprc:{ *:[i32] }:$rA, gprc:{ *:[i32] }:$rB) 5307 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::DIVWE, 5308 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rT 5309 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rA 5310 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rB 5311 GIR_EraseFromParent, /*InsnID*/0, 5312 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5313 // GIR_Coverage, 201, 5314 GIR_Done, 5315 // Label 453: @11480 5316 GIM_Try, /*On fail goto*//*Label 454*/ 11532, // Rule ID 202 // 5317 GIM_CheckFeatures, GIFBS_HasExtDiv, 5318 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_divweu, 5319 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 5320 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5321 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5322 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 5323 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/PPC::GPRCRegClassID, 5324 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/PPC::GPRCRegClassID, 5325 // (intrinsic_wo_chain:{ *:[i32] } 7474:{ *:[iPTR] }, gprc:{ *:[i32] }:$rA, gprc:{ *:[i32] }:$rB) => (DIVWEU:{ *:[i32] } gprc:{ *:[i32] }:$rA, gprc:{ *:[i32] }:$rB) 5326 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::DIVWEU, 5327 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rT 5328 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rA 5329 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rB 5330 GIR_EraseFromParent, /*InsnID*/0, 5331 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5332 // GIR_Coverage, 202, 5333 GIR_Done, 5334 // Label 454: @11532 5335 GIM_Try, /*On fail goto*//*Label 455*/ 11584, // Rule ID 682 // 5336 GIM_CheckFeatures, GIFBS_HasBPERMD, 5337 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_bpermd, 5338 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 5339 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5340 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 5341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 5342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/PPC::G8RCRegClassID, 5343 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/PPC::G8RCRegClassID, 5344 // (intrinsic_wo_chain:{ *:[i64] } 7436:{ *:[iPTR] }, g8rc:{ *:[i64] }:$rS, g8rc:{ *:[i64] }:$rB) => (BPERMD:{ *:[i64] } g8rc:{ *:[i64] }:$rS, g8rc:{ *:[i64] }:$rB) 5345 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::BPERMD, 5346 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 5347 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rS 5348 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rB 5349 GIR_EraseFromParent, /*InsnID*/0, 5350 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5351 // GIR_Coverage, 682, 5352 GIR_Done, 5353 // Label 455: @11584 5354 GIM_Try, /*On fail goto*//*Label 456*/ 11636, // Rule ID 688 // 5355 GIM_CheckFeatures, GIFBS_HasExtDiv, 5356 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_divde, 5357 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 5358 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5359 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 5360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 5361 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/PPC::G8RCRegClassID, 5362 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/PPC::G8RCRegClassID, 5363 // (intrinsic_wo_chain:{ *:[i64] } 7470:{ *:[iPTR] }, g8rc:{ *:[i64] }:$rA, g8rc:{ *:[i64] }:$rB) => (DIVDE:{ *:[i64] } g8rc:{ *:[i64] }:$rA, g8rc:{ *:[i64] }:$rB) 5364 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::DIVDE, 5365 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rT 5366 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rA 5367 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rB 5368 GIR_EraseFromParent, /*InsnID*/0, 5369 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5370 // GIR_Coverage, 688, 5371 GIR_Done, 5372 // Label 456: @11636 5373 GIM_Try, /*On fail goto*//*Label 457*/ 11688, // Rule ID 693 // 5374 GIM_CheckFeatures, GIFBS_HasExtDiv, 5375 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_divdeu, 5376 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 5377 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5378 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 5379 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 5380 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/PPC::G8RCRegClassID, 5381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/PPC::G8RCRegClassID, 5382 // (intrinsic_wo_chain:{ *:[i64] } 7471:{ *:[iPTR] }, g8rc:{ *:[i64] }:$rA, g8rc:{ *:[i64] }:$rB) => (DIVDEU:{ *:[i64] } g8rc:{ *:[i64] }:$rA, g8rc:{ *:[i64] }:$rB) 5383 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::DIVDEU, 5384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rT 5385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rA 5386 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rB 5387 GIR_EraseFromParent, /*InsnID*/0, 5388 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5389 // GIR_Coverage, 693, 5390 GIR_Done, 5391 // Label 457: @11688 5392 GIM_Try, /*On fail goto*//*Label 458*/ 11732, // Rule ID 300 // 5393 GIM_CheckFeatures, GIFBS_HasAltivec, 5394 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vaddcuw, 5395 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5396 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5397 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 5398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5399 // (intrinsic_wo_chain:{ *:[v4i32] } 7159:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VADDCUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 5400 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VADDCUW, 5401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5402 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5404 GIR_EraseFromParent, /*InsnID*/0, 5405 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5406 // GIR_Coverage, 300, 5407 GIR_Done, 5408 // Label 458: @11732 5409 GIM_Try, /*On fail goto*//*Label 459*/ 11776, // Rule ID 301 // 5410 GIM_CheckFeatures, GIFBS_HasAltivec, 5411 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vaddsbs, 5412 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 5413 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 5414 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 5415 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5416 // (intrinsic_wo_chain:{ *:[v16i8] } 7162:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VADDSBS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 5417 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VADDSBS, 5418 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5419 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5420 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5421 GIR_EraseFromParent, /*InsnID*/0, 5422 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5423 // GIR_Coverage, 301, 5424 GIR_Done, 5425 // Label 459: @11776 5426 GIM_Try, /*On fail goto*//*Label 460*/ 11820, // Rule ID 302 // 5427 GIM_CheckFeatures, GIFBS_HasAltivec, 5428 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vaddshs, 5429 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 5430 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 5431 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 5432 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5433 // (intrinsic_wo_chain:{ *:[v8i16] } 7163:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VADDSHS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 5434 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VADDSHS, 5435 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5436 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5437 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5438 GIR_EraseFromParent, /*InsnID*/0, 5439 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5440 // GIR_Coverage, 302, 5441 GIR_Done, 5442 // Label 460: @11820 5443 GIM_Try, /*On fail goto*//*Label 461*/ 11864, // Rule ID 303 // 5444 GIM_CheckFeatures, GIFBS_HasAltivec, 5445 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vaddsws, 5446 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5447 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5448 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 5449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5450 // (intrinsic_wo_chain:{ *:[v4i32] } 7164:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VADDSWS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 5451 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VADDSWS, 5452 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5453 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5454 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5455 GIR_EraseFromParent, /*InsnID*/0, 5456 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5457 // GIR_Coverage, 303, 5458 GIR_Done, 5459 // Label 461: @11864 5460 GIM_Try, /*On fail goto*//*Label 462*/ 11908, // Rule ID 304 // 5461 GIM_CheckFeatures, GIFBS_HasAltivec, 5462 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vaddubs, 5463 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 5464 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 5465 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 5466 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5467 // (intrinsic_wo_chain:{ *:[v16i8] } 7165:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VADDUBS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 5468 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VADDUBS, 5469 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5470 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5471 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5472 GIR_EraseFromParent, /*InsnID*/0, 5473 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5474 // GIR_Coverage, 304, 5475 GIR_Done, 5476 // Label 462: @11908 5477 GIM_Try, /*On fail goto*//*Label 463*/ 11952, // Rule ID 305 // 5478 GIM_CheckFeatures, GIFBS_HasAltivec, 5479 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vadduhs, 5480 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 5481 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 5482 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 5483 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5484 // (intrinsic_wo_chain:{ *:[v8i16] } 7166:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VADDUHS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 5485 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VADDUHS, 5486 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5487 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5488 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5489 GIR_EraseFromParent, /*InsnID*/0, 5490 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5491 // GIR_Coverage, 305, 5492 GIR_Done, 5493 // Label 463: @11952 5494 GIM_Try, /*On fail goto*//*Label 464*/ 11996, // Rule ID 306 // 5495 GIM_CheckFeatures, GIFBS_HasAltivec, 5496 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vadduws, 5497 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5498 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5499 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 5500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5501 // (intrinsic_wo_chain:{ *:[v4i32] } 7167:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VADDUWS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 5502 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VADDUWS, 5503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5505 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5506 GIR_EraseFromParent, /*InsnID*/0, 5507 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5508 // GIR_Coverage, 306, 5509 GIR_Done, 5510 // Label 464: @11996 5511 GIM_Try, /*On fail goto*//*Label 465*/ 12040, // Rule ID 319 // 5512 GIM_CheckFeatures, GIFBS_HasAltivec, 5513 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vavgsb, 5514 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 5515 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 5516 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 5517 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5518 // (intrinsic_wo_chain:{ *:[v16i8] } 7168:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VAVGSB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 5519 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VAVGSB, 5520 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5521 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5522 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5523 GIR_EraseFromParent, /*InsnID*/0, 5524 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5525 // GIR_Coverage, 319, 5526 GIR_Done, 5527 // Label 465: @12040 5528 GIM_Try, /*On fail goto*//*Label 466*/ 12084, // Rule ID 320 // 5529 GIM_CheckFeatures, GIFBS_HasAltivec, 5530 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vavgsh, 5531 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 5532 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 5533 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 5534 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5535 // (intrinsic_wo_chain:{ *:[v8i16] } 7169:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VAVGSH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 5536 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VAVGSH, 5537 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5538 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5539 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5540 GIR_EraseFromParent, /*InsnID*/0, 5541 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5542 // GIR_Coverage, 320, 5543 GIR_Done, 5544 // Label 466: @12084 5545 GIM_Try, /*On fail goto*//*Label 467*/ 12128, // Rule ID 321 // 5546 GIM_CheckFeatures, GIFBS_HasAltivec, 5547 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vavgsw, 5548 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5549 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5550 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 5551 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5552 // (intrinsic_wo_chain:{ *:[v4i32] } 7170:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VAVGSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 5553 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VAVGSW, 5554 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5555 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5556 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5557 GIR_EraseFromParent, /*InsnID*/0, 5558 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5559 // GIR_Coverage, 321, 5560 GIR_Done, 5561 // Label 467: @12128 5562 GIM_Try, /*On fail goto*//*Label 468*/ 12172, // Rule ID 322 // 5563 GIM_CheckFeatures, GIFBS_HasAltivec, 5564 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vavgub, 5565 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 5566 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 5567 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 5568 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5569 // (intrinsic_wo_chain:{ *:[v16i8] } 7171:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VAVGUB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 5570 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VAVGUB, 5571 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5572 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5573 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5574 GIR_EraseFromParent, /*InsnID*/0, 5575 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5576 // GIR_Coverage, 322, 5577 GIR_Done, 5578 // Label 468: @12172 5579 GIM_Try, /*On fail goto*//*Label 469*/ 12216, // Rule ID 323 // 5580 GIM_CheckFeatures, GIFBS_HasAltivec, 5581 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vavguh, 5582 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 5583 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 5584 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 5585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5586 // (intrinsic_wo_chain:{ *:[v8i16] } 7172:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VAVGUH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 5587 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VAVGUH, 5588 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5589 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5590 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5591 GIR_EraseFromParent, /*InsnID*/0, 5592 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5593 // GIR_Coverage, 323, 5594 GIR_Done, 5595 // Label 469: @12216 5596 GIM_Try, /*On fail goto*//*Label 470*/ 12260, // Rule ID 324 // 5597 GIM_CheckFeatures, GIFBS_HasAltivec, 5598 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vavguw, 5599 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5600 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5601 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 5602 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5603 // (intrinsic_wo_chain:{ *:[v4i32] } 7173:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VAVGUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 5604 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VAVGUW, 5605 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5606 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5607 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5608 GIR_EraseFromParent, /*InsnID*/0, 5609 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5610 // GIR_Coverage, 324, 5611 GIR_Done, 5612 // Label 470: @12260 5613 GIM_Try, /*On fail goto*//*Label 471*/ 12304, // Rule ID 325 // 5614 GIM_CheckFeatures, GIFBS_HasAltivec, 5615 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmaxfp, 5616 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5617 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5618 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 5619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5620 // (intrinsic_wo_chain:{ *:[v4f32] } 7292:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$vA, v4f32:{ *:[v4f32] }:$vB) => (VMAXFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vA, v4f32:{ *:[v4f32] }:$vB) 5621 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMAXFP, 5622 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5625 GIR_EraseFromParent, /*InsnID*/0, 5626 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5627 // GIR_Coverage, 325, 5628 GIR_Done, 5629 // Label 471: @12304 5630 GIM_Try, /*On fail goto*//*Label 472*/ 12348, // Rule ID 326 // 5631 GIM_CheckFeatures, GIFBS_HasAltivec, 5632 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmaxsb, 5633 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 5634 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 5635 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 5636 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5637 // (intrinsic_wo_chain:{ *:[v16i8] } 7293:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VMAXSB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 5638 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMAXSB, 5639 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5640 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5641 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5642 GIR_EraseFromParent, /*InsnID*/0, 5643 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5644 // GIR_Coverage, 326, 5645 GIR_Done, 5646 // Label 472: @12348 5647 GIM_Try, /*On fail goto*//*Label 473*/ 12392, // Rule ID 327 // 5648 GIM_CheckFeatures, GIFBS_HasAltivec, 5649 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmaxsh, 5650 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 5651 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 5652 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 5653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5654 // (intrinsic_wo_chain:{ *:[v8i16] } 7295:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VMAXSH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 5655 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMAXSH, 5656 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5657 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5658 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5659 GIR_EraseFromParent, /*InsnID*/0, 5660 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5661 // GIR_Coverage, 327, 5662 GIR_Done, 5663 // Label 473: @12392 5664 GIM_Try, /*On fail goto*//*Label 474*/ 12436, // Rule ID 328 // 5665 GIM_CheckFeatures, GIFBS_HasAltivec, 5666 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmaxsw, 5667 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5668 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5669 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 5670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5671 // (intrinsic_wo_chain:{ *:[v4i32] } 7296:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VMAXSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 5672 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMAXSW, 5673 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5676 GIR_EraseFromParent, /*InsnID*/0, 5677 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5678 // GIR_Coverage, 328, 5679 GIR_Done, 5680 // Label 474: @12436 5681 GIM_Try, /*On fail goto*//*Label 475*/ 12480, // Rule ID 329 // 5682 GIM_CheckFeatures, GIFBS_HasAltivec, 5683 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmaxub, 5684 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 5685 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 5686 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 5687 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5688 // (intrinsic_wo_chain:{ *:[v16i8] } 7297:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VMAXUB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 5689 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMAXUB, 5690 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5691 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5692 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5693 GIR_EraseFromParent, /*InsnID*/0, 5694 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5695 // GIR_Coverage, 329, 5696 GIR_Done, 5697 // Label 475: @12480 5698 GIM_Try, /*On fail goto*//*Label 476*/ 12524, // Rule ID 330 // 5699 GIM_CheckFeatures, GIFBS_HasAltivec, 5700 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmaxuh, 5701 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 5702 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 5703 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 5704 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5705 // (intrinsic_wo_chain:{ *:[v8i16] } 7299:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VMAXUH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 5706 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMAXUH, 5707 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5708 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5709 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5710 GIR_EraseFromParent, /*InsnID*/0, 5711 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5712 // GIR_Coverage, 330, 5713 GIR_Done, 5714 // Label 476: @12524 5715 GIM_Try, /*On fail goto*//*Label 477*/ 12568, // Rule ID 331 // 5716 GIM_CheckFeatures, GIFBS_HasAltivec, 5717 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmaxuw, 5718 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5719 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5720 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 5721 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5722 // (intrinsic_wo_chain:{ *:[v4i32] } 7300:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VMAXUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 5723 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMAXUW, 5724 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5725 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5726 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5727 GIR_EraseFromParent, /*InsnID*/0, 5728 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5729 // GIR_Coverage, 331, 5730 GIR_Done, 5731 // Label 477: @12568 5732 GIM_Try, /*On fail goto*//*Label 478*/ 12612, // Rule ID 332 // 5733 GIM_CheckFeatures, GIFBS_HasAltivec, 5734 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vminfp, 5735 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5736 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5737 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 5738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5739 // (intrinsic_wo_chain:{ *:[v4f32] } 7303:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$vA, v4f32:{ *:[v4f32] }:$vB) => (VMINFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vA, v4f32:{ *:[v4f32] }:$vB) 5740 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMINFP, 5741 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5742 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5743 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5744 GIR_EraseFromParent, /*InsnID*/0, 5745 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5746 // GIR_Coverage, 332, 5747 GIR_Done, 5748 // Label 478: @12612 5749 GIM_Try, /*On fail goto*//*Label 479*/ 12656, // Rule ID 333 // 5750 GIM_CheckFeatures, GIFBS_HasAltivec, 5751 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vminsb, 5752 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 5753 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 5754 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 5755 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5756 // (intrinsic_wo_chain:{ *:[v16i8] } 7304:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VMINSB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 5757 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMINSB, 5758 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5759 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5760 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5761 GIR_EraseFromParent, /*InsnID*/0, 5762 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5763 // GIR_Coverage, 333, 5764 GIR_Done, 5765 // Label 479: @12656 5766 GIM_Try, /*On fail goto*//*Label 480*/ 12700, // Rule ID 334 // 5767 GIM_CheckFeatures, GIFBS_HasAltivec, 5768 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vminsh, 5769 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 5770 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 5771 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 5772 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5773 // (intrinsic_wo_chain:{ *:[v8i16] } 7306:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VMINSH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 5774 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMINSH, 5775 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5776 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5777 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5778 GIR_EraseFromParent, /*InsnID*/0, 5779 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5780 // GIR_Coverage, 334, 5781 GIR_Done, 5782 // Label 480: @12700 5783 GIM_Try, /*On fail goto*//*Label 481*/ 12744, // Rule ID 335 // 5784 GIM_CheckFeatures, GIFBS_HasAltivec, 5785 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vminsw, 5786 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5787 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5788 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 5789 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5790 // (intrinsic_wo_chain:{ *:[v4i32] } 7307:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VMINSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 5791 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMINSW, 5792 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5793 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5794 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5795 GIR_EraseFromParent, /*InsnID*/0, 5796 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5797 // GIR_Coverage, 335, 5798 GIR_Done, 5799 // Label 481: @12744 5800 GIM_Try, /*On fail goto*//*Label 482*/ 12788, // Rule ID 336 // 5801 GIM_CheckFeatures, GIFBS_HasAltivec, 5802 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vminub, 5803 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 5804 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 5805 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 5806 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5807 // (intrinsic_wo_chain:{ *:[v16i8] } 7308:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VMINUB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 5808 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMINUB, 5809 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5810 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5811 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5812 GIR_EraseFromParent, /*InsnID*/0, 5813 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5814 // GIR_Coverage, 336, 5815 GIR_Done, 5816 // Label 482: @12788 5817 GIM_Try, /*On fail goto*//*Label 483*/ 12832, // Rule ID 337 // 5818 GIM_CheckFeatures, GIFBS_HasAltivec, 5819 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vminuh, 5820 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 5821 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 5822 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 5823 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5824 // (intrinsic_wo_chain:{ *:[v8i16] } 7310:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VMINUH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 5825 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMINUH, 5826 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5828 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5829 GIR_EraseFromParent, /*InsnID*/0, 5830 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5831 // GIR_Coverage, 337, 5832 GIR_Done, 5833 // Label 483: @12832 5834 GIM_Try, /*On fail goto*//*Label 484*/ 12876, // Rule ID 338 // 5835 GIM_CheckFeatures, GIFBS_HasAltivec, 5836 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vminuw, 5837 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5838 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5839 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 5840 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5841 // (intrinsic_wo_chain:{ *:[v4i32] } 7311:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VMINUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 5842 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMINUW, 5843 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5844 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5845 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5846 GIR_EraseFromParent, /*InsnID*/0, 5847 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5848 // GIR_Coverage, 338, 5849 GIR_Done, 5850 // Label 484: @12876 5851 GIM_Try, /*On fail goto*//*Label 485*/ 12920, // Rule ID 351 // 5852 GIM_CheckFeatures, GIFBS_HasAltivec, 5853 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmulesb, 5854 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 5855 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 5856 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 5857 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5858 // (intrinsic_wo_chain:{ *:[v8i16] } 7321:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VMULESB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 5859 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMULESB, 5860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5861 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5862 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5863 GIR_EraseFromParent, /*InsnID*/0, 5864 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5865 // GIR_Coverage, 351, 5866 GIR_Done, 5867 // Label 485: @12920 5868 GIM_Try, /*On fail goto*//*Label 486*/ 12964, // Rule ID 352 // 5869 GIM_CheckFeatures, GIFBS_HasAltivec, 5870 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmulesh, 5871 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5872 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 5873 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 5874 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5875 // (intrinsic_wo_chain:{ *:[v4i32] } 7323:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VMULESH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 5876 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMULESH, 5877 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5879 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5880 GIR_EraseFromParent, /*InsnID*/0, 5881 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5882 // GIR_Coverage, 352, 5883 GIR_Done, 5884 // Label 486: @12964 5885 GIM_Try, /*On fail goto*//*Label 487*/ 13008, // Rule ID 353 // 5886 GIM_CheckFeatures, GIFBS_HasAltivec, 5887 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmuleub, 5888 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 5889 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 5890 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 5891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5892 // (intrinsic_wo_chain:{ *:[v8i16] } 7325:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VMULEUB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 5893 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMULEUB, 5894 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5897 GIR_EraseFromParent, /*InsnID*/0, 5898 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5899 // GIR_Coverage, 353, 5900 GIR_Done, 5901 // Label 487: @13008 5902 GIM_Try, /*On fail goto*//*Label 488*/ 13052, // Rule ID 354 // 5903 GIM_CheckFeatures, GIFBS_HasAltivec, 5904 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmuleuh, 5905 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5906 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 5907 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 5908 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5909 // (intrinsic_wo_chain:{ *:[v4i32] } 7327:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VMULEUH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 5910 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMULEUH, 5911 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5912 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5913 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5914 GIR_EraseFromParent, /*InsnID*/0, 5915 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5916 // GIR_Coverage, 354, 5917 GIR_Done, 5918 // Label 488: @13052 5919 GIM_Try, /*On fail goto*//*Label 489*/ 13096, // Rule ID 355 // 5920 GIM_CheckFeatures, GIFBS_HasAltivec, 5921 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmulosb, 5922 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 5923 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 5924 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 5925 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5926 // (intrinsic_wo_chain:{ *:[v8i16] } 7333:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VMULOSB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 5927 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMULOSB, 5928 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5929 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5930 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5931 GIR_EraseFromParent, /*InsnID*/0, 5932 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5933 // GIR_Coverage, 355, 5934 GIR_Done, 5935 // Label 489: @13096 5936 GIM_Try, /*On fail goto*//*Label 490*/ 13140, // Rule ID 356 // 5937 GIM_CheckFeatures, GIFBS_HasAltivec, 5938 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmulosh, 5939 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5940 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 5941 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 5942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5943 // (intrinsic_wo_chain:{ *:[v4i32] } 7335:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VMULOSH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 5944 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMULOSH, 5945 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5946 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5947 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5948 GIR_EraseFromParent, /*InsnID*/0, 5949 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5950 // GIR_Coverage, 356, 5951 GIR_Done, 5952 // Label 490: @13140 5953 GIM_Try, /*On fail goto*//*Label 491*/ 13184, // Rule ID 357 // 5954 GIM_CheckFeatures, GIFBS_HasAltivec, 5955 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmuloub, 5956 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 5957 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 5958 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 5959 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5960 // (intrinsic_wo_chain:{ *:[v8i16] } 7337:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VMULOUB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 5961 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMULOUB, 5962 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5963 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5965 GIR_EraseFromParent, /*InsnID*/0, 5966 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5967 // GIR_Coverage, 357, 5968 GIR_Done, 5969 // Label 491: @13184 5970 GIM_Try, /*On fail goto*//*Label 492*/ 13228, // Rule ID 358 // 5971 GIM_CheckFeatures, GIFBS_HasAltivec, 5972 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmulouh, 5973 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5974 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 5975 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 5976 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5977 // (intrinsic_wo_chain:{ *:[v4i32] } 7339:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VMULOUH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 5978 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMULOUH, 5979 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5980 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5981 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5982 GIR_EraseFromParent, /*InsnID*/0, 5983 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5984 // GIR_Coverage, 358, 5985 GIR_Done, 5986 // Label 492: @13228 5987 GIM_Try, /*On fail goto*//*Label 493*/ 13272, // Rule ID 365 // 5988 GIM_CheckFeatures, GIFBS_HasAltivec, 5989 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsubcuw, 5990 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5991 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5992 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 5993 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 5994 // (intrinsic_wo_chain:{ *:[v4i32] } 7401:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSUBCUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 5995 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSUBCUW, 5996 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 5997 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 5998 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 5999 GIR_EraseFromParent, /*InsnID*/0, 6000 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6001 // GIR_Coverage, 365, 6002 GIR_Done, 6003 // Label 493: @13272 6004 GIM_Try, /*On fail goto*//*Label 494*/ 13316, // Rule ID 370 // 6005 GIM_CheckFeatures, GIFBS_HasAltivec, 6006 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsubsbs, 6007 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 6008 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6009 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 6010 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6011 // (intrinsic_wo_chain:{ *:[v16i8] } 7404:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VSUBSBS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 6012 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSUBSBS, 6013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6014 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6015 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6016 GIR_EraseFromParent, /*InsnID*/0, 6017 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6018 // GIR_Coverage, 370, 6019 GIR_Done, 6020 // Label 494: @13316 6021 GIM_Try, /*On fail goto*//*Label 495*/ 13360, // Rule ID 371 // 6022 GIM_CheckFeatures, GIFBS_HasAltivec, 6023 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsubshs, 6024 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 6025 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 6026 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 6027 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6028 // (intrinsic_wo_chain:{ *:[v8i16] } 7405:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VSUBSHS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 6029 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSUBSHS, 6030 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6031 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6032 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6033 GIR_EraseFromParent, /*InsnID*/0, 6034 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6035 // GIR_Coverage, 371, 6036 GIR_Done, 6037 // Label 495: @13360 6038 GIM_Try, /*On fail goto*//*Label 496*/ 13404, // Rule ID 372 // 6039 GIM_CheckFeatures, GIFBS_HasAltivec, 6040 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsubsws, 6041 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 6042 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6043 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6045 // (intrinsic_wo_chain:{ *:[v4i32] } 7406:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSUBSWS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 6046 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSUBSWS, 6047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6050 GIR_EraseFromParent, /*InsnID*/0, 6051 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6052 // GIR_Coverage, 372, 6053 GIR_Done, 6054 // Label 496: @13404 6055 GIM_Try, /*On fail goto*//*Label 497*/ 13448, // Rule ID 373 // 6056 GIM_CheckFeatures, GIFBS_HasAltivec, 6057 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsububs, 6058 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 6059 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6060 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 6061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6062 // (intrinsic_wo_chain:{ *:[v16i8] } 7407:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VSUBUBS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 6063 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSUBUBS, 6064 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6065 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6066 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6067 GIR_EraseFromParent, /*InsnID*/0, 6068 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6069 // GIR_Coverage, 373, 6070 GIR_Done, 6071 // Label 497: @13448 6072 GIM_Try, /*On fail goto*//*Label 498*/ 13492, // Rule ID 374 // 6073 GIM_CheckFeatures, GIFBS_HasAltivec, 6074 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsubuhs, 6075 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 6076 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 6077 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 6078 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6079 // (intrinsic_wo_chain:{ *:[v8i16] } 7408:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VSUBUHS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 6080 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSUBUHS, 6081 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6082 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6083 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6084 GIR_EraseFromParent, /*InsnID*/0, 6085 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6086 // GIR_Coverage, 374, 6087 GIR_Done, 6088 // Label 498: @13492 6089 GIM_Try, /*On fail goto*//*Label 499*/ 13536, // Rule ID 375 // 6090 GIM_CheckFeatures, GIFBS_HasAltivec, 6091 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsubuws, 6092 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 6093 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6094 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6095 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6096 // (intrinsic_wo_chain:{ *:[v4i32] } 7409:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSUBUWS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 6097 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSUBUWS, 6098 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6099 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6100 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6101 GIR_EraseFromParent, /*InsnID*/0, 6102 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6103 // GIR_Coverage, 375, 6104 GIR_Done, 6105 // Label 499: @13536 6106 GIM_Try, /*On fail goto*//*Label 500*/ 13580, // Rule ID 384 // 6107 GIM_CheckFeatures, GIFBS_HasAltivec, 6108 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vrlb, 6109 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 6110 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6111 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 6112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6113 // (intrinsic_wo_chain:{ *:[v16i8] } 7363:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VRLB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 6114 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VRLB, 6115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6117 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6118 GIR_EraseFromParent, /*InsnID*/0, 6119 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6120 // GIR_Coverage, 384, 6121 GIR_Done, 6122 // Label 500: @13580 6123 GIM_Try, /*On fail goto*//*Label 501*/ 13624, // Rule ID 385 // 6124 GIM_CheckFeatures, GIFBS_HasAltivec, 6125 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vrlh, 6126 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 6127 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 6128 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 6129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6130 // (intrinsic_wo_chain:{ *:[v8i16] } 7367:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VRLH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 6131 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VRLH, 6132 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6133 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6134 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6135 GIR_EraseFromParent, /*InsnID*/0, 6136 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6137 // GIR_Coverage, 385, 6138 GIR_Done, 6139 // Label 501: @13624 6140 GIM_Try, /*On fail goto*//*Label 502*/ 13668, // Rule ID 386 // 6141 GIM_CheckFeatures, GIFBS_HasAltivec, 6142 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vrlw, 6143 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 6144 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6145 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6146 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6147 // (intrinsic_wo_chain:{ *:[v4i32] } 7370:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VRLW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 6148 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VRLW, 6149 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6150 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6151 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6152 GIR_EraseFromParent, /*InsnID*/0, 6153 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6154 // GIR_Coverage, 386, 6155 GIR_Done, 6156 // Label 502: @13668 6157 GIM_Try, /*On fail goto*//*Label 503*/ 13712, // Rule ID 387 // 6158 GIM_CheckFeatures, GIFBS_HasAltivec, 6159 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsl, 6160 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 6161 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6162 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6163 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6164 // (intrinsic_wo_chain:{ *:[v4i32] } 7375:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSL:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 6165 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSL, 6166 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6167 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6168 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6169 GIR_EraseFromParent, /*InsnID*/0, 6170 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6171 // GIR_Coverage, 387, 6172 GIR_Done, 6173 // Label 503: @13712 6174 GIM_Try, /*On fail goto*//*Label 504*/ 13756, // Rule ID 388 // 6175 GIM_CheckFeatures, GIFBS_HasAltivec, 6176 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vslo, 6177 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 6178 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6179 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6181 // (intrinsic_wo_chain:{ *:[v4i32] } 7379:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSLO:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 6182 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSLO, 6183 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6184 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6185 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6186 GIR_EraseFromParent, /*InsnID*/0, 6187 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6188 // GIR_Coverage, 388, 6189 GIR_Done, 6190 // Label 504: @13756 6191 GIM_Try, /*On fail goto*//*Label 505*/ 13800, // Rule ID 389 // 6192 GIM_CheckFeatures, GIFBS_HasAltivec, 6193 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vslb, 6194 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 6195 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6196 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 6197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6198 // (intrinsic_wo_chain:{ *:[v16i8] } 7376:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VSLB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 6199 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSLB, 6200 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6201 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6202 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6203 GIR_EraseFromParent, /*InsnID*/0, 6204 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6205 // GIR_Coverage, 389, 6206 GIR_Done, 6207 // Label 505: @13800 6208 GIM_Try, /*On fail goto*//*Label 506*/ 13844, // Rule ID 390 // 6209 GIM_CheckFeatures, GIFBS_HasAltivec, 6210 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vslh, 6211 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 6212 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 6213 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 6214 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6215 // (intrinsic_wo_chain:{ *:[v8i16] } 7378:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VSLH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 6216 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSLH, 6217 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6218 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6219 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6220 GIR_EraseFromParent, /*InsnID*/0, 6221 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6222 // GIR_Coverage, 390, 6223 GIR_Done, 6224 // Label 506: @13844 6225 GIM_Try, /*On fail goto*//*Label 507*/ 13888, // Rule ID 391 // 6226 GIM_CheckFeatures, GIFBS_HasAltivec, 6227 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vslw, 6228 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 6229 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6230 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6231 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6232 // (intrinsic_wo_chain:{ *:[v4i32] } 7381:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSLW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 6233 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSLW, 6234 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6235 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6236 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6237 GIR_EraseFromParent, /*InsnID*/0, 6238 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6239 // GIR_Coverage, 391, 6240 GIR_Done, 6241 // Label 507: @13888 6242 GIM_Try, /*On fail goto*//*Label 508*/ 13932, // Rule ID 395 // 6243 GIM_CheckFeatures, GIFBS_HasAltivec, 6244 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsr, 6245 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 6246 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6247 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6248 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6249 // (intrinsic_wo_chain:{ *:[v4i32] } 7382:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 6250 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSR, 6251 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6252 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6253 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6254 GIR_EraseFromParent, /*InsnID*/0, 6255 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6256 // GIR_Coverage, 395, 6257 GIR_Done, 6258 // Label 508: @13932 6259 GIM_Try, /*On fail goto*//*Label 509*/ 13976, // Rule ID 396 // 6260 GIM_CheckFeatures, GIFBS_HasAltivec, 6261 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsro, 6262 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 6263 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6264 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6266 // (intrinsic_wo_chain:{ *:[v4i32] } 7389:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSRO:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 6267 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSRO, 6268 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6270 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6271 GIR_EraseFromParent, /*InsnID*/0, 6272 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6273 // GIR_Coverage, 396, 6274 GIR_Done, 6275 // Label 509: @13976 6276 GIM_Try, /*On fail goto*//*Label 510*/ 14020, // Rule ID 397 // 6277 GIM_CheckFeatures, GIFBS_HasAltivec, 6278 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsrab, 6279 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 6280 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6281 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 6282 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6283 // (intrinsic_wo_chain:{ *:[v16i8] } 7383:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VSRAB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 6284 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSRAB, 6285 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6286 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6287 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6288 GIR_EraseFromParent, /*InsnID*/0, 6289 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6290 // GIR_Coverage, 397, 6291 GIR_Done, 6292 // Label 510: @14020 6293 GIM_Try, /*On fail goto*//*Label 511*/ 14064, // Rule ID 398 // 6294 GIM_CheckFeatures, GIFBS_HasAltivec, 6295 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsrah, 6296 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 6297 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 6298 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 6299 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6300 // (intrinsic_wo_chain:{ *:[v8i16] } 7384:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VSRAH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 6301 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSRAH, 6302 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6303 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6304 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6305 GIR_EraseFromParent, /*InsnID*/0, 6306 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6307 // GIR_Coverage, 398, 6308 GIR_Done, 6309 // Label 511: @14064 6310 GIM_Try, /*On fail goto*//*Label 512*/ 14108, // Rule ID 399 // 6311 GIM_CheckFeatures, GIFBS_HasAltivec, 6312 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsraw, 6313 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 6314 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6315 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6316 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6317 // (intrinsic_wo_chain:{ *:[v4i32] } 7385:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSRAW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 6318 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSRAW, 6319 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6320 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6321 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6322 GIR_EraseFromParent, /*InsnID*/0, 6323 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6324 // GIR_Coverage, 399, 6325 GIR_Done, 6326 // Label 512: @14108 6327 GIM_Try, /*On fail goto*//*Label 513*/ 14152, // Rule ID 400 // 6328 GIM_CheckFeatures, GIFBS_HasAltivec, 6329 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsrb, 6330 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 6331 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6332 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 6333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6334 // (intrinsic_wo_chain:{ *:[v16i8] } 7386:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VSRB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 6335 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSRB, 6336 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6337 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6338 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6339 GIR_EraseFromParent, /*InsnID*/0, 6340 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6341 // GIR_Coverage, 400, 6342 GIR_Done, 6343 // Label 513: @14152 6344 GIM_Try, /*On fail goto*//*Label 514*/ 14196, // Rule ID 401 // 6345 GIM_CheckFeatures, GIFBS_HasAltivec, 6346 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsrh, 6347 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 6348 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 6349 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 6350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6351 // (intrinsic_wo_chain:{ *:[v8i16] } 7388:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VSRH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 6352 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSRH, 6353 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6354 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6355 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6356 GIR_EraseFromParent, /*InsnID*/0, 6357 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6358 // GIR_Coverage, 401, 6359 GIR_Done, 6360 // Label 514: @14196 6361 GIM_Try, /*On fail goto*//*Label 515*/ 14240, // Rule ID 402 // 6362 GIM_CheckFeatures, GIFBS_HasAltivec, 6363 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsrw, 6364 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 6365 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6366 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6367 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6368 // (intrinsic_wo_chain:{ *:[v4i32] } 7391:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSRW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 6369 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSRW, 6370 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6371 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6372 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6373 GIR_EraseFromParent, /*InsnID*/0, 6374 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6375 // GIR_Coverage, 402, 6376 GIR_Done, 6377 // Label 515: @14240 6378 GIM_Try, /*On fail goto*//*Label 516*/ 14284, // Rule ID 406 // 6379 GIM_CheckFeatures, GIFBS_HasAltivec, 6380 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vpkpx, 6381 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 6382 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6383 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6385 // (intrinsic_wo_chain:{ *:[v8i16] } 7345:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VPKPX:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 6386 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VPKPX, 6387 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6388 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6389 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6390 GIR_EraseFromParent, /*InsnID*/0, 6391 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6392 // GIR_Coverage, 406, 6393 GIR_Done, 6394 // Label 516: @14284 6395 GIM_Try, /*On fail goto*//*Label 517*/ 14328, // Rule ID 453 // 6396 GIM_CheckFeatures, GIFBS_HasP8Altivec, 6397 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmulesw, 6398 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6399 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6400 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6401 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6402 // (intrinsic_wo_chain:{ *:[v2i64] } 7324:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VMULESW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 6403 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMULESW, 6404 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6405 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6406 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6407 GIR_EraseFromParent, /*InsnID*/0, 6408 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6409 // GIR_Coverage, 453, 6410 GIR_Done, 6411 // Label 517: @14328 6412 GIM_Try, /*On fail goto*//*Label 518*/ 14372, // Rule ID 454 // 6413 GIM_CheckFeatures, GIFBS_HasP8Altivec, 6414 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmuleuw, 6415 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6416 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6417 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6418 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6419 // (intrinsic_wo_chain:{ *:[v2i64] } 7328:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VMULEUW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 6420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMULEUW, 6421 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6422 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6423 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6424 GIR_EraseFromParent, /*InsnID*/0, 6425 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6426 // GIR_Coverage, 454, 6427 GIR_Done, 6428 // Label 518: @14372 6429 GIM_Try, /*On fail goto*//*Label 519*/ 14416, // Rule ID 455 // 6430 GIM_CheckFeatures, GIFBS_HasP8Altivec, 6431 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmulosw, 6432 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6433 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6434 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6436 // (intrinsic_wo_chain:{ *:[v2i64] } 7336:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VMULOSW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 6437 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMULOSW, 6438 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6439 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6440 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6441 GIR_EraseFromParent, /*InsnID*/0, 6442 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6443 // GIR_Coverage, 455, 6444 GIR_Done, 6445 // Label 519: @14416 6446 GIM_Try, /*On fail goto*//*Label 520*/ 14460, // Rule ID 456 // 6447 GIM_CheckFeatures, GIFBS_HasP8Altivec, 6448 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmulouw, 6449 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6450 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6451 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6452 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6453 // (intrinsic_wo_chain:{ *:[v2i64] } 7340:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VMULOUW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 6454 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMULOUW, 6455 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6456 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6457 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6458 GIR_EraseFromParent, /*InsnID*/0, 6459 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6460 // GIR_Coverage, 456, 6461 GIR_Done, 6462 // Label 520: @14460 6463 GIM_Try, /*On fail goto*//*Label 521*/ 14504, // Rule ID 458 // 6464 GIM_CheckFeatures, GIFBS_HasP8Altivec, 6465 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmaxsd, 6466 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6467 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6468 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6470 // (intrinsic_wo_chain:{ *:[v2i64] } 7294:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VMAXSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 6471 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMAXSD, 6472 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6474 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6475 GIR_EraseFromParent, /*InsnID*/0, 6476 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6477 // GIR_Coverage, 458, 6478 GIR_Done, 6479 // Label 521: @14504 6480 GIM_Try, /*On fail goto*//*Label 522*/ 14548, // Rule ID 459 // 6481 GIM_CheckFeatures, GIFBS_HasP8Altivec, 6482 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmaxud, 6483 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6484 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6485 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6486 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6487 // (intrinsic_wo_chain:{ *:[v2i64] } 7298:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VMAXUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 6488 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMAXUD, 6489 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6490 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6491 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6492 GIR_EraseFromParent, /*InsnID*/0, 6493 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6494 // GIR_Coverage, 459, 6495 GIR_Done, 6496 // Label 522: @14548 6497 GIM_Try, /*On fail goto*//*Label 523*/ 14592, // Rule ID 460 // 6498 GIM_CheckFeatures, GIFBS_HasP8Altivec, 6499 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vminsd, 6500 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6501 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6502 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6503 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6504 // (intrinsic_wo_chain:{ *:[v2i64] } 7305:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VMINSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 6505 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMINSD, 6506 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6507 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6508 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6509 GIR_EraseFromParent, /*InsnID*/0, 6510 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6511 // GIR_Coverage, 460, 6512 GIR_Done, 6513 // Label 523: @14592 6514 GIM_Try, /*On fail goto*//*Label 524*/ 14636, // Rule ID 461 // 6515 GIM_CheckFeatures, GIFBS_HasP8Altivec, 6516 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vminud, 6517 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6518 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6519 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6521 // (intrinsic_wo_chain:{ *:[v2i64] } 7309:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VMINUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 6522 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMINUD, 6523 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6524 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6525 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6526 GIR_EraseFromParent, /*InsnID*/0, 6527 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6528 // GIR_Coverage, 461, 6529 GIR_Done, 6530 // Label 524: @14636 6531 GIM_Try, /*On fail goto*//*Label 525*/ 14680, // Rule ID 464 // 6532 GIM_CheckFeatures, GIFBS_HasP8Altivec, 6533 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vrld, 6534 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6535 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6536 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6538 // (intrinsic_wo_chain:{ *:[v2i64] } 7364:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VRLD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 6539 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VRLD, 6540 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6541 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6542 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6543 GIR_EraseFromParent, /*InsnID*/0, 6544 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6545 // GIR_Coverage, 464, 6546 GIR_Done, 6547 // Label 525: @14680 6548 GIM_Try, /*On fail goto*//*Label 526*/ 14724, // Rule ID 468 // 6549 GIM_CheckFeatures, GIFBS_HasP8Altivec, 6550 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vaddcuq, 6551 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 6552 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 6553 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s128, 6554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6555 // (intrinsic_wo_chain:{ *:[v1i128] } 7158:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) => (VADDCUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) 6556 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VADDCUQ, 6557 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6558 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6559 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6560 GIR_EraseFromParent, /*InsnID*/0, 6561 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6562 // GIR_Coverage, 468, 6563 GIR_Done, 6564 // Label 526: @14724 6565 GIM_Try, /*On fail goto*//*Label 527*/ 14768, // Rule ID 473 // 6566 GIM_CheckFeatures, GIFBS_HasP8Altivec, 6567 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsubcuq, 6568 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 6569 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 6570 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s128, 6571 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6572 // (intrinsic_wo_chain:{ *:[v1i128] } 7400:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) => (VSUBCUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) 6573 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSUBCUQ, 6574 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6575 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6576 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6577 GIR_EraseFromParent, /*InsnID*/0, 6578 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6579 // GIR_Coverage, 473, 6580 GIR_Done, 6581 // Label 527: @14768 6582 GIM_Try, /*On fail goto*//*Label 528*/ 14812, // Rule ID 492 // 6583 GIM_CheckFeatures, GIFBS_HasP8Altivec, 6584 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_crypto_vpmsumb, 6585 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 6586 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6587 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 6588 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6589 // (intrinsic_wo_chain:{ *:[v16i8] } 7123:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VPMSUMB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 6590 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VPMSUMB, 6591 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6592 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6593 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6594 GIR_EraseFromParent, /*InsnID*/0, 6595 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6596 // GIR_Coverage, 492, 6597 GIR_Done, 6598 // Label 528: @14812 6599 GIM_Try, /*On fail goto*//*Label 529*/ 14856, // Rule ID 493 // 6600 GIM_CheckFeatures, GIFBS_HasP8Altivec, 6601 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_crypto_vpmsumh, 6602 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 6603 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 6604 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 6605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6606 // (intrinsic_wo_chain:{ *:[v8i16] } 7125:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VPMSUMH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 6607 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VPMSUMH, 6608 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6609 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6610 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6611 GIR_EraseFromParent, /*InsnID*/0, 6612 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6613 // GIR_Coverage, 493, 6614 GIR_Done, 6615 // Label 529: @14856 6616 GIM_Try, /*On fail goto*//*Label 530*/ 14900, // Rule ID 494 // 6617 GIM_CheckFeatures, GIFBS_HasP8Altivec, 6618 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_crypto_vpmsumw, 6619 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 6620 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6621 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6622 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6623 // (intrinsic_wo_chain:{ *:[v4i32] } 7126:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VPMSUMW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 6624 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VPMSUMW, 6625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6626 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6627 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6628 GIR_EraseFromParent, /*InsnID*/0, 6629 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6630 // GIR_Coverage, 494, 6631 GIR_Done, 6632 // Label 530: @14900 6633 GIM_Try, /*On fail goto*//*Label 531*/ 14944, // Rule ID 495 // 6634 GIM_CheckFeatures, GIFBS_HasP8Altivec, 6635 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_crypto_vpmsumd, 6636 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6637 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6638 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6639 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6640 // (intrinsic_wo_chain:{ *:[v2i64] } 7124:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VPMSUMD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 6641 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VPMSUMD, 6642 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6643 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6645 GIR_EraseFromParent, /*InsnID*/0, 6646 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6647 // GIR_Coverage, 495, 6648 GIR_Done, 6649 // Label 531: @14944 6650 GIM_Try, /*On fail goto*//*Label 532*/ 14988, // Rule ID 503 // 6651 GIM_CheckFeatures, GIFBS_HasP8Altivec, 6652 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vbpermq, 6653 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6654 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6655 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 6656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6657 // (intrinsic_wo_chain:{ *:[v2i64] } 7175:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VBPERMQ:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 6658 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VBPERMQ, 6659 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6660 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6661 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6662 GIR_EraseFromParent, /*InsnID*/0, 6663 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6664 // GIR_Coverage, 503, 6665 GIR_Done, 6666 // Label 532: @14988 6667 GIM_Try, /*On fail goto*//*Label 533*/ 15032, // Rule ID 506 // 6668 GIM_CheckFeatures, GIFBS_HasP8Crypto, 6669 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_crypto_vcipher, 6670 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6671 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6672 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6673 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6674 // (intrinsic_wo_chain:{ *:[v2i64] } 7117:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VCIPHER:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 6675 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VCIPHER, 6676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6677 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6679 GIR_EraseFromParent, /*InsnID*/0, 6680 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6681 // GIR_Coverage, 506, 6682 GIR_Done, 6683 // Label 533: @15032 6684 GIM_Try, /*On fail goto*//*Label 534*/ 15076, // Rule ID 507 // 6685 GIM_CheckFeatures, GIFBS_HasP8Crypto, 6686 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_crypto_vcipherlast, 6687 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6688 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6689 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6690 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6691 // (intrinsic_wo_chain:{ *:[v2i64] } 7118:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VCIPHERLAST:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 6692 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VCIPHERLAST, 6693 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6694 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6695 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6696 GIR_EraseFromParent, /*InsnID*/0, 6697 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6698 // GIR_Coverage, 507, 6699 GIR_Done, 6700 // Label 534: @15076 6701 GIM_Try, /*On fail goto*//*Label 535*/ 15120, // Rule ID 508 // 6702 GIM_CheckFeatures, GIFBS_HasP8Crypto, 6703 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_crypto_vncipher, 6704 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6705 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6706 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6707 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6708 // (intrinsic_wo_chain:{ *:[v2i64] } 7119:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VNCIPHER:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 6709 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VNCIPHER, 6710 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6711 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6712 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6713 GIR_EraseFromParent, /*InsnID*/0, 6714 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6715 // GIR_Coverage, 508, 6716 GIR_Done, 6717 // Label 535: @15120 6718 GIM_Try, /*On fail goto*//*Label 536*/ 15164, // Rule ID 509 // 6719 GIM_CheckFeatures, GIFBS_HasP8Crypto, 6720 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_crypto_vncipherlast, 6721 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6722 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6723 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6725 // (intrinsic_wo_chain:{ *:[v2i64] } 7120:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VNCIPHERLAST:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 6726 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VNCIPHERLAST, 6727 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6728 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6729 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6730 GIR_EraseFromParent, /*InsnID*/0, 6731 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6732 // GIR_Coverage, 509, 6733 GIR_Done, 6734 // Label 536: @15164 6735 GIM_Try, /*On fail goto*//*Label 537*/ 15208, // Rule ID 542 // 6736 GIM_CheckFeatures, GIFBS_HasP9Altivec, 6737 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vbpermd, 6738 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6739 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6740 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 6741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6742 // (intrinsic_wo_chain:{ *:[v2i64] } 7174:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VBPERMD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v16i8:{ *:[v16i8] }:$vB) 6743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VBPERMD, 6744 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6745 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6746 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6747 GIR_EraseFromParent, /*InsnID*/0, 6748 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6749 // GIR_Coverage, 542, 6750 GIR_Done, 6751 // Label 537: @15208 6752 GIM_Try, /*On fail goto*//*Label 538*/ 15252, // Rule ID 543 // 6753 GIM_CheckFeatures, GIFBS_HasP9Altivec, 6754 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vrlwnm, 6755 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 6756 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6757 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6759 // (intrinsic_wo_chain:{ *:[v4i32] } 7372:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VRLWNM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 6760 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VRLWNM, 6761 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6762 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6763 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6764 GIR_EraseFromParent, /*InsnID*/0, 6765 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6766 // GIR_Coverage, 543, 6767 GIR_Done, 6768 // Label 538: @15252 6769 GIM_Try, /*On fail goto*//*Label 539*/ 15296, // Rule ID 545 // 6770 GIM_CheckFeatures, GIFBS_HasP9Altivec, 6771 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vrldnm, 6772 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6773 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6774 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6775 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6776 // (intrinsic_wo_chain:{ *:[v2i64] } 7366:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VRLDNM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 6777 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VRLDNM, 6778 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6779 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6780 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6781 GIR_EraseFromParent, /*InsnID*/0, 6782 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6783 // GIR_Coverage, 545, 6784 GIR_Done, 6785 // Label 539: @15296 6786 GIM_Try, /*On fail goto*//*Label 540*/ 15340, // Rule ID 547 // 6787 GIM_CheckFeatures, GIFBS_HasP9Altivec, 6788 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vslv, 6789 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 6790 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6791 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 6792 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6793 // (intrinsic_wo_chain:{ *:[v16i8] } 7380:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VSLV:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 6794 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSLV, 6795 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6796 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6797 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6798 GIR_EraseFromParent, /*InsnID*/0, 6799 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6800 // GIR_Coverage, 547, 6801 GIR_Done, 6802 // Label 540: @15340 6803 GIM_Try, /*On fail goto*//*Label 541*/ 15384, // Rule ID 548 // 6804 GIM_CheckFeatures, GIFBS_HasP9Altivec, 6805 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsrv, 6806 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 6807 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6808 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 6809 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6810 // (intrinsic_wo_chain:{ *:[v16i8] } 7390:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VSRV:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 6811 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSRV, 6812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6814 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6815 GIR_EraseFromParent, /*InsnID*/0, 6816 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6817 // GIR_Coverage, 548, 6818 GIR_Done, 6819 // Label 541: @15384 6820 GIM_Try, /*On fail goto*//*Label 542*/ 15428, // Rule ID 549 // 6821 GIM_CheckFeatures, GIFBS_HasP9Altivec, 6822 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vabsdub, 6823 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 6824 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6825 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 6826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6827 // (intrinsic_wo_chain:{ *:[v16i8] } 7155:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VABSDUB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 6828 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VABSDUB, 6829 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6830 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6832 GIR_EraseFromParent, /*InsnID*/0, 6833 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6834 // GIR_Coverage, 549, 6835 GIR_Done, 6836 // Label 542: @15428 6837 GIM_Try, /*On fail goto*//*Label 543*/ 15472, // Rule ID 550 // 6838 GIM_CheckFeatures, GIFBS_HasP9Altivec, 6839 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vabsduh, 6840 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 6841 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 6842 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 6843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6844 // (intrinsic_wo_chain:{ *:[v8i16] } 7156:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VABSDUH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 6845 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VABSDUH, 6846 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6847 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6848 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6849 GIR_EraseFromParent, /*InsnID*/0, 6850 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6851 // GIR_Coverage, 550, 6852 GIR_Done, 6853 // Label 543: @15472 6854 GIM_Try, /*On fail goto*//*Label 544*/ 15516, // Rule ID 551 // 6855 GIM_CheckFeatures, GIFBS_HasP9Altivec, 6856 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vabsduw, 6857 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 6858 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6859 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6861 // (intrinsic_wo_chain:{ *:[v4i32] } 7157:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VABSDUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 6862 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VABSDUW, 6863 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6864 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6865 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6866 GIR_EraseFromParent, /*InsnID*/0, 6867 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6868 // GIR_Coverage, 551, 6869 GIR_Done, 6870 // Label 544: @15516 6871 GIM_Try, /*On fail goto*//*Label 545*/ 15560, // Rule ID 1088 // 6872 GIM_CheckFeatures, GIFBS_IsISA3_1, 6873 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vpdepd, 6874 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6875 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6876 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6877 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6878 // (intrinsic_wo_chain:{ *:[v2i64] } 7342:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VPDEPD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 6879 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VPDEPD, 6880 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6882 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6883 GIR_EraseFromParent, /*InsnID*/0, 6884 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6885 // GIR_Coverage, 1088, 6886 GIR_Done, 6887 // Label 545: @15560 6888 GIM_Try, /*On fail goto*//*Label 546*/ 15604, // Rule ID 1089 // 6889 GIM_CheckFeatures, GIFBS_IsISA3_1, 6890 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vpextd, 6891 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6892 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6893 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6894 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6895 // (intrinsic_wo_chain:{ *:[v2i64] } 7344:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VPEXTD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 6896 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VPEXTD, 6897 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6898 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6899 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6900 GIR_EraseFromParent, /*InsnID*/0, 6901 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6902 // GIR_Coverage, 1089, 6903 GIR_Done, 6904 // Label 546: @15604 6905 GIM_Try, /*On fail goto*//*Label 547*/ 15648, // Rule ID 1090 // 6906 GIM_CheckFeatures, GIFBS_IsISA3_1, 6907 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_pdepd, 6908 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 6909 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 6910 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 6911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 6912 // (intrinsic_wo_chain:{ *:[i64] } 7601:{ *:[iPTR] }, i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) => (PDEPD:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) 6913 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::PDEPD, 6914 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 6915 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rS 6916 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rB 6917 GIR_EraseFromParent, /*InsnID*/0, 6918 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6919 // GIR_Coverage, 1090, 6920 GIR_Done, 6921 // Label 547: @15648 6922 GIM_Try, /*On fail goto*//*Label 548*/ 15692, // Rule ID 1091 // 6923 GIM_CheckFeatures, GIFBS_IsISA3_1, 6924 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_pextd, 6925 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 6926 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 6927 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 6928 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 6929 // (intrinsic_wo_chain:{ *:[i64] } 7602:{ *:[iPTR] }, i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) => (PEXTD:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) 6930 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::PEXTD, 6931 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 6932 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rS 6933 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rB 6934 GIR_EraseFromParent, /*InsnID*/0, 6935 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6936 // GIR_Coverage, 1091, 6937 GIR_Done, 6938 // Label 548: @15692 6939 GIM_Try, /*On fail goto*//*Label 549*/ 15736, // Rule ID 1092 // 6940 GIM_CheckFeatures, GIFBS_IsISA3_1, 6941 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vcfuged, 6942 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6943 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6944 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6945 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6946 // (intrinsic_wo_chain:{ *:[v2i64] } 7177:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VCFUGED:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 6947 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VCFUGED, 6948 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6949 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6950 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6951 GIR_EraseFromParent, /*InsnID*/0, 6952 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6953 // GIR_Coverage, 1092, 6954 GIR_Done, 6955 // Label 549: @15736 6956 GIM_Try, /*On fail goto*//*Label 550*/ 15780, // Rule ID 1094 // 6957 GIM_CheckFeatures, GIFBS_IsISA3_1, 6958 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_cfuged, 6959 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 6960 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 6961 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 6962 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 6963 // (intrinsic_wo_chain:{ *:[i64] } 7438:{ *:[iPTR] }, i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) => (CFUGED:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) 6964 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CFUGED, 6965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 6966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rS 6967 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rB 6968 GIR_EraseFromParent, /*InsnID*/0, 6969 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6970 // GIR_Coverage, 1094, 6971 GIR_Done, 6972 // Label 550: @15780 6973 GIM_Try, /*On fail goto*//*Label 551*/ 15824, // Rule ID 1096 // 6974 GIM_CheckFeatures, GIFBS_IsISA3_1, 6975 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vclzdm, 6976 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6977 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6978 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6979 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6980 // (intrinsic_wo_chain:{ *:[v2i64] } 7181:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VCLZDM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 6981 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VCLZDM, 6982 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 6983 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 6984 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 6985 GIR_EraseFromParent, /*InsnID*/0, 6986 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6987 // GIR_Coverage, 1096, 6988 GIR_Done, 6989 // Label 551: @15824 6990 GIM_Try, /*On fail goto*//*Label 552*/ 15868, // Rule ID 1097 // 6991 GIM_CheckFeatures, GIFBS_IsISA3_1, 6992 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vctzdm, 6993 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6994 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6995 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6996 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 6997 // (intrinsic_wo_chain:{ *:[v2i64] } 7239:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VCTZDM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 6998 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VCTZDM, 6999 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7000 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7001 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7002 GIR_EraseFromParent, /*InsnID*/0, 7003 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7004 // GIR_Coverage, 1097, 7005 GIR_Done, 7006 // Label 552: @15868 7007 GIM_Try, /*On fail goto*//*Label 553*/ 15912, // Rule ID 1098 // 7008 GIM_CheckFeatures, GIFBS_IsISA3_1, 7009 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_cntlzdm, 7010 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 7011 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 7012 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 7013 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 7014 // (intrinsic_wo_chain:{ *:[i64] } 7443:{ *:[iPTR] }, i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) => (CNTLZDM:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) 7015 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CNTLZDM, 7016 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 7017 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rS 7018 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rB 7019 GIR_EraseFromParent, /*InsnID*/0, 7020 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7021 // GIR_Coverage, 1098, 7022 GIR_Done, 7023 // Label 553: @15912 7024 GIM_Try, /*On fail goto*//*Label 554*/ 15956, // Rule ID 1099 // 7025 GIM_CheckFeatures, GIFBS_IsISA3_1, 7026 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_cnttzdm, 7027 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 7028 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 7029 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 7030 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 7031 // (intrinsic_wo_chain:{ *:[i64] } 7444:{ *:[iPTR] }, i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) => (CNTTZDM:{ *:[i64] } i64:{ *:[i64] }:$rS, i64:{ *:[i64] }:$rB) 7032 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CNTTZDM, 7033 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 7034 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rS 7035 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rB 7036 GIR_EraseFromParent, /*InsnID*/0, 7037 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7038 // GIR_Coverage, 1099, 7039 GIR_Done, 7040 // Label 554: @15956 7041 GIM_Try, /*On fail goto*//*Label 555*/ 16000, // Rule ID 1100 // 7042 GIM_CheckFeatures, GIFBS_IsISA3_1, 7043 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vclrlb, 7044 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 7045 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7046 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 7047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7048 // (intrinsic_wo_chain:{ *:[v16i8] } 7179:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, i32:{ *:[i32] }:$rB) => (VCLRLB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, i32:{ *:[i32] }:$rB) 7049 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VCLRLB, 7050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7051 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7052 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rB 7053 GIR_EraseFromParent, /*InsnID*/0, 7054 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7055 // GIR_Coverage, 1100, 7056 GIR_Done, 7057 // Label 555: @16000 7058 GIM_Try, /*On fail goto*//*Label 556*/ 16044, // Rule ID 1101 // 7059 GIM_CheckFeatures, GIFBS_IsISA3_1, 7060 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vclrrb, 7061 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 7062 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7063 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 7064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7065 // (intrinsic_wo_chain:{ *:[v16i8] } 7180:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, i32:{ *:[i32] }:$rB) => (VCLRRB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, i32:{ *:[i32] }:$rB) 7066 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VCLRRB, 7067 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7068 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7069 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rB 7070 GIR_EraseFromParent, /*InsnID*/0, 7071 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7072 // GIR_Coverage, 1101, 7073 GIR_Done, 7074 // Label 556: @16044 7075 GIM_Try, /*On fail goto*//*Label 557*/ 16088, // Rule ID 1115 // 7076 GIM_CheckFeatures, GIFBS_IsISA3_1, 7077 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vdivesw, 7078 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7079 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7080 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7081 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7082 // (intrinsic_wo_chain:{ *:[v4i32] } 7243:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VDIVESW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 7083 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VDIVESW, 7084 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7085 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7086 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7087 GIR_EraseFromParent, /*InsnID*/0, 7088 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7089 // GIR_Coverage, 1115, 7090 GIR_Done, 7091 // Label 557: @16088 7092 GIM_Try, /*On fail goto*//*Label 558*/ 16132, // Rule ID 1116 // 7093 GIM_CheckFeatures, GIFBS_IsISA3_1, 7094 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vdiveuw, 7095 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7096 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7097 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7098 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7099 // (intrinsic_wo_chain:{ *:[v4i32] } 7246:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VDIVEUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 7100 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VDIVEUW, 7101 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7102 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7103 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7104 GIR_EraseFromParent, /*InsnID*/0, 7105 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7106 // GIR_Coverage, 1116, 7107 GIR_Done, 7108 // Label 558: @16132 7109 GIM_Try, /*On fail goto*//*Label 559*/ 16176, // Rule ID 1117 // 7110 GIM_CheckFeatures, GIFBS_IsISA3_1, 7111 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vdivesd, 7112 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7113 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7114 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7115 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7116 // (intrinsic_wo_chain:{ *:[v2i64] } 7241:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VDIVESD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 7117 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VDIVESD, 7118 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7119 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7120 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7121 GIR_EraseFromParent, /*InsnID*/0, 7122 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7123 // GIR_Coverage, 1117, 7124 GIR_Done, 7125 // Label 559: @16176 7126 GIM_Try, /*On fail goto*//*Label 560*/ 16220, // Rule ID 1118 // 7127 GIM_CheckFeatures, GIFBS_IsISA3_1, 7128 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vdiveud, 7129 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7130 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7131 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7133 // (intrinsic_wo_chain:{ *:[v2i64] } 7244:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VDIVEUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 7134 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VDIVEUD, 7135 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7136 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7137 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7138 GIR_EraseFromParent, /*InsnID*/0, 7139 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7140 // GIR_Coverage, 1118, 7141 GIR_Done, 7142 // Label 560: @16220 7143 GIM_Try, /*On fail goto*//*Label 561*/ 16264, // Rule ID 1121 // 7144 GIM_CheckFeatures, GIFBS_IsISA3_1, 7145 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmulesd, 7146 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 7147 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7148 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7149 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7150 // (intrinsic_wo_chain:{ *:[v1i128] } 7322:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VMULESD:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 7151 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMULESD, 7152 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7153 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7154 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7155 GIR_EraseFromParent, /*InsnID*/0, 7156 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7157 // GIR_Coverage, 1121, 7158 GIR_Done, 7159 // Label 561: @16264 7160 GIM_Try, /*On fail goto*//*Label 562*/ 16308, // Rule ID 1122 // 7161 GIM_CheckFeatures, GIFBS_IsISA3_1, 7162 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmuleud, 7163 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 7164 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7165 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7167 // (intrinsic_wo_chain:{ *:[v1i128] } 7326:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VMULEUD:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 7168 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMULEUD, 7169 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7170 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7171 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7172 GIR_EraseFromParent, /*InsnID*/0, 7173 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7174 // GIR_Coverage, 1122, 7175 GIR_Done, 7176 // Label 562: @16308 7177 GIM_Try, /*On fail goto*//*Label 563*/ 16352, // Rule ID 1123 // 7178 GIM_CheckFeatures, GIFBS_IsISA3_1, 7179 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmulosd, 7180 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 7181 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7182 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7183 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7184 // (intrinsic_wo_chain:{ *:[v1i128] } 7334:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VMULOSD:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 7185 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMULOSD, 7186 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7187 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7188 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7189 GIR_EraseFromParent, /*InsnID*/0, 7190 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7191 // GIR_Coverage, 1123, 7192 GIR_Done, 7193 // Label 563: @16352 7194 GIM_Try, /*On fail goto*//*Label 564*/ 16396, // Rule ID 1124 // 7195 GIM_CheckFeatures, GIFBS_IsISA3_1, 7196 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmuloud, 7197 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 7198 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7199 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7201 // (intrinsic_wo_chain:{ *:[v1i128] } 7338:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VMULOUD:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 7202 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMULOUD, 7203 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7204 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7205 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7206 GIR_EraseFromParent, /*InsnID*/0, 7207 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7208 // GIR_Coverage, 1124, 7209 GIR_Done, 7210 // Label 564: @16396 7211 GIM_Try, /*On fail goto*//*Label 565*/ 16440, // Rule ID 1128 // 7212 GIM_CheckFeatures, GIFBS_IsISA3_1, 7213 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vdivesq, 7214 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 7215 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 7216 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s128, 7217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7218 // (intrinsic_wo_chain:{ *:[v1i128] } 7242:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) => (VDIVESQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) 7219 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VDIVESQ, 7220 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7221 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7222 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7223 GIR_EraseFromParent, /*InsnID*/0, 7224 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7225 // GIR_Coverage, 1128, 7226 GIR_Done, 7227 // Label 565: @16440 7228 GIM_Try, /*On fail goto*//*Label 566*/ 16484, // Rule ID 1129 // 7229 GIM_CheckFeatures, GIFBS_IsISA3_1, 7230 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vdiveuq, 7231 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 7232 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 7233 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s128, 7234 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7235 // (intrinsic_wo_chain:{ *:[v1i128] } 7245:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) => (VDIVEUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) 7236 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VDIVEUQ, 7237 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7238 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7239 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7240 GIR_EraseFromParent, /*InsnID*/0, 7241 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7242 // GIR_Coverage, 1129, 7243 GIR_Done, 7244 // Label 566: @16484 7245 GIM_Try, /*On fail goto*//*Label 567*/ 16528, // Rule ID 1139 // 7246 GIM_CheckFeatures, GIFBS_IsISA3_1, 7247 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vrlqnm, 7248 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 7249 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 7250 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s128, 7251 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7252 // (intrinsic_wo_chain:{ *:[v1i128] } 7369:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) => (VRLQNM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) 7253 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VRLQNM, 7254 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7255 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7256 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7257 GIR_EraseFromParent, /*InsnID*/0, 7258 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7259 // GIR_Coverage, 1139, 7260 GIR_Done, 7261 // Label 567: @16528 7262 GIM_Reject, 7263 // Label 419: @16529 7264 GIM_Try, /*On fail goto*//*Label 568*/ 18932, 7265 GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, 7266 GIM_Try, /*On fail goto*//*Label 569*/ 16599, // Rule ID 999 // 7267 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 7268 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_fmaf128_round_to_odd, 7269 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 7270 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 7271 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s128, 7272 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s128, 7273 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7274 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 7275 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 7276 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128, 7277 GIM_CheckIsSafeToFold, /*InsnID*/1, 7278 // (intrinsic_wo_chain:{ *:[f128] } 7486:{ *:[iPTR] }, f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB, (fneg:{ *:[f128] } f128:{ *:[f128] }:$vTi)) => (XSMSUBQPO:{ *:[f128] } f128:{ *:[f128] }:$vTi, f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 7279 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSMSUBQPO, 7280 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 7281 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vTi 7282 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7283 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7284 GIR_EraseFromParent, /*InsnID*/0, 7285 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7286 // GIR_Coverage, 999, 7287 GIR_Done, 7288 // Label 569: @16599 7289 GIM_Try, /*On fail goto*//*Label 570*/ 16651, // Rule ID 998 // 7290 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 7291 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_fmaf128_round_to_odd, 7292 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 7293 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 7294 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s128, 7295 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s128, 7296 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7297 // (intrinsic_wo_chain:{ *:[f128] } 7486:{ *:[iPTR] }, f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB, f128:{ *:[f128] }:$vTi) => (XSMADDQPO:{ *:[f128] } f128:{ *:[f128] }:$vTi, f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 7298 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSMADDQPO, 7299 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 7300 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vTi 7301 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7302 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7303 GIR_EraseFromParent, /*InsnID*/0, 7304 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7305 // GIR_Coverage, 998, 7306 GIR_Done, 7307 // Label 570: @16651 7308 GIM_Try, /*On fail goto*//*Label 571*/ 16701, // Rule ID 504 // 7309 GIM_CheckFeatures, GIFBS_HasP8Crypto, 7310 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_crypto_vshasigmaw, 7311 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7312 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7314 // MIs[0] ST 7315 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 7316 // MIs[0] SIX 7317 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 7318 // (intrinsic_wo_chain:{ *:[v4i32] } 7129:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, (timm:{ *:[i32] }):$ST, (timm:{ *:[i32] }):$SIX) => (VSHASIGMAW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (timm:{ *:[i32] }):$ST, (timm:{ *:[i32] }):$SIX) 7319 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSHASIGMAW, 7320 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7321 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7322 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ST 7323 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // SIX 7324 GIR_EraseFromParent, /*InsnID*/0, 7325 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7326 // GIR_Coverage, 504, 7327 GIR_Done, 7328 // Label 571: @16701 7329 GIM_Try, /*On fail goto*//*Label 572*/ 16751, // Rule ID 505 // 7330 GIM_CheckFeatures, GIFBS_HasP8Crypto, 7331 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_crypto_vshasigmad, 7332 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7333 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7334 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7335 // MIs[0] ST 7336 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 7337 // MIs[0] SIX 7338 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 7339 // (intrinsic_wo_chain:{ *:[v2i64] } 7128:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, (timm:{ *:[i32] }):$ST, (timm:{ *:[i32] }):$SIX) => (VSHASIGMAD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, (timm:{ *:[i32] }):$ST, (timm:{ *:[i32] }):$SIX) 7340 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSHASIGMAD, 7341 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7342 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7343 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ST 7344 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // SIX 7345 GIR_EraseFromParent, /*InsnID*/0, 7346 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7347 // GIR_Coverage, 505, 7348 GIR_Done, 7349 // Label 572: @16751 7350 GIM_Try, /*On fail goto*//*Label 573*/ 16802, // Rule ID 1038 // 7351 GIM_CheckFeatures, GIFBS_IsISA3_1, 7352 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsldbi, 7353 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 7354 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7355 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 7356 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7357 // MIs[0] SH 7358 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 7359 // (intrinsic_wo_chain:{ *:[v16i8] } 7377:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VRA, v16i8:{ *:[v16i8] }:$VRB, (timm:{ *:[i32] }):$SH) => (VSLDBI:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VRA, v16i8:{ *:[v16i8] }:$VRB, (timm:{ *:[i32] }):$SH) 7360 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSLDBI, 7361 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // VRT 7362 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // VRA 7363 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // VRB 7364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // SH 7365 GIR_EraseFromParent, /*InsnID*/0, 7366 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7367 // GIR_Coverage, 1038, 7368 GIR_Done, 7369 // Label 573: @16802 7370 GIM_Try, /*On fail goto*//*Label 574*/ 16853, // Rule ID 1039 // 7371 GIM_CheckFeatures, GIFBS_IsISA3_1, 7372 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsrdbi, 7373 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 7374 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7375 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 7376 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7377 // MIs[0] SH 7378 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 7379 // (intrinsic_wo_chain:{ *:[v16i8] } 7387:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VRA, v16i8:{ *:[v16i8] }:$VRB, (timm:{ *:[i32] }):$SH) => (VSRDBI:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VRA, v16i8:{ *:[v16i8] }:$VRB, (timm:{ *:[i32] }):$SH) 7380 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSRDBI, 7381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // VRT 7382 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // VRA 7383 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // VRB 7384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // SH 7385 GIR_EraseFromParent, /*InsnID*/0, 7386 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7387 // GIR_Coverage, 1039, 7388 GIR_Done, 7389 // Label 574: @16853 7390 GIM_Try, /*On fail goto*//*Label 575*/ 16904, // Rule ID 1044 // 7391 GIM_CheckFeatures, GIFBS_IsISA3_1, 7392 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vinsw, 7393 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7394 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7395 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 7396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7397 // MIs[0] UIM 7398 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 7399 // (intrinsic_wo_chain:{ *:[v4i32] } 7285:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vDi, i32:{ *:[i32] }:$rB, (timm:{ *:[i32] }):$UIM) => (VINSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vDi, (timm:{ *:[i32] }):$UIM, i32:{ *:[i32] }:$rB) 7400 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VINSW, 7401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7402 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vDi 7403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // UIM 7404 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rB 7405 GIR_EraseFromParent, /*InsnID*/0, 7406 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7407 // GIR_Coverage, 1044, 7408 GIR_Done, 7409 // Label 575: @16904 7410 GIM_Try, /*On fail goto*//*Label 576*/ 16955, // Rule ID 1045 // 7411 GIM_CheckFeatures, GIFBS_IsISA3_1, 7412 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vinsd, 7413 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7414 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7415 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 7416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7417 // MIs[0] UIM 7418 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 7419 // (intrinsic_wo_chain:{ *:[v2i64] } 7278:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vDi, i64:{ *:[i64] }:$rB, (timm:{ *:[i32] }):$UIM) => (VINSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vDi, (timm:{ *:[i32] }):$UIM, i64:{ *:[i64] }:$rB) 7420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VINSD, 7421 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7422 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vDi 7423 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // UIM 7424 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rB 7425 GIR_EraseFromParent, /*InsnID*/0, 7426 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7427 // GIR_Coverage, 1045, 7428 GIR_Done, 7429 // Label 576: @16955 7430 GIM_Try, /*On fail goto*//*Label 577*/ 17007, // Rule ID 292 // 7431 GIM_CheckFeatures, GIFBS_HasAltivec, 7432 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmladduhm, 7433 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 7434 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 7435 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 7436 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, 7437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7438 // (intrinsic_wo_chain:{ *:[v8i16] } 7312:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB, v8i16:{ *:[v8i16] }:$vC) => (VMLADDUHM:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB, v8i16:{ *:[v8i16] }:$vC) 7439 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMLADDUHM, 7440 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7441 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7442 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7443 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vC 7444 GIR_EraseFromParent, /*InsnID*/0, 7445 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7446 // GIR_Coverage, 292, 7447 GIR_Done, 7448 // Label 577: @17007 7449 GIM_Try, /*On fail goto*//*Label 578*/ 17059, // Rule ID 293 // 7450 GIM_CheckFeatures, GIFBS_HasAltivec, 7451 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vperm, 7452 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7453 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7454 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7455 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, 7456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7457 // (intrinsic_wo_chain:{ *:[v4i32] } 7343:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB, v16i8:{ *:[v16i8] }:$vC) => (VPERM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB, v16i8:{ *:[v16i8] }:$vC) 7458 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VPERM, 7459 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7460 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7461 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7462 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vC 7463 GIR_EraseFromParent, /*InsnID*/0, 7464 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7465 // GIR_Coverage, 293, 7466 GIR_Done, 7467 // Label 578: @17059 7468 GIM_Try, /*On fail goto*//*Label 579*/ 17111, // Rule ID 294 // 7469 GIM_CheckFeatures, GIFBS_HasAltivec, 7470 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsel, 7471 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7472 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7473 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7474 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 7475 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7476 // (intrinsic_wo_chain:{ *:[v4i32] } 7374:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC) => (VSEL:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC) 7477 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSEL, 7478 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7479 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7480 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7481 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vC 7482 GIR_EraseFromParent, /*InsnID*/0, 7483 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7484 // GIR_Coverage, 294, 7485 GIR_Done, 7486 // Label 579: @17111 7487 GIM_Try, /*On fail goto*//*Label 580*/ 17163, // Rule ID 345 // 7488 GIM_CheckFeatures, GIFBS_HasAltivec, 7489 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmsummbm, 7490 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7491 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7492 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 7493 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 7494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7495 // (intrinsic_wo_chain:{ *:[v4i32] } 7314:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB, v4i32:{ *:[v4i32] }:$vC) => (VMSUMMBM:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB, v4i32:{ *:[v4i32] }:$vC) 7496 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMSUMMBM, 7497 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7498 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7499 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7500 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vC 7501 GIR_EraseFromParent, /*InsnID*/0, 7502 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7503 // GIR_Coverage, 345, 7504 GIR_Done, 7505 // Label 580: @17163 7506 GIM_Try, /*On fail goto*//*Label 581*/ 17215, // Rule ID 346 // 7507 GIM_CheckFeatures, GIFBS_HasAltivec, 7508 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmsumshm, 7509 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7510 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 7511 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 7512 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 7513 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7514 // (intrinsic_wo_chain:{ *:[v4i32] } 7315:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB, v4i32:{ *:[v4i32] }:$vC) => (VMSUMSHM:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB, v4i32:{ *:[v4i32] }:$vC) 7515 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMSUMSHM, 7516 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7517 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7518 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7519 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vC 7520 GIR_EraseFromParent, /*InsnID*/0, 7521 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7522 // GIR_Coverage, 346, 7523 GIR_Done, 7524 // Label 581: @17215 7525 GIM_Try, /*On fail goto*//*Label 582*/ 17267, // Rule ID 347 // 7526 GIM_CheckFeatures, GIFBS_HasAltivec, 7527 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmsumubm, 7528 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7529 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7530 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 7531 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 7532 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7533 // (intrinsic_wo_chain:{ *:[v4i32] } 7317:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB, v4i32:{ *:[v4i32] }:$vC) => (VMSUMUBM:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB, v4i32:{ *:[v4i32] }:$vC) 7534 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMSUMUBM, 7535 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7536 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7537 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7538 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vC 7539 GIR_EraseFromParent, /*InsnID*/0, 7540 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7541 // GIR_Coverage, 347, 7542 GIR_Done, 7543 // Label 582: @17267 7544 GIM_Try, /*On fail goto*//*Label 583*/ 17319, // Rule ID 348 // 7545 GIM_CheckFeatures, GIFBS_HasAltivec, 7546 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmsumuhm, 7547 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7548 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 7549 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 7550 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 7551 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7552 // (intrinsic_wo_chain:{ *:[v4i32] } 7319:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB, v4i32:{ *:[v4i32] }:$vC) => (VMSUMUHM:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB, v4i32:{ *:[v4i32] }:$vC) 7553 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMSUMUHM, 7554 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7555 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7556 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7557 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vC 7558 GIR_EraseFromParent, /*InsnID*/0, 7559 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7560 // GIR_Coverage, 348, 7561 GIR_Done, 7562 // Label 583: @17319 7563 GIM_Try, /*On fail goto*//*Label 584*/ 17371, // Rule ID 467 // 7564 GIM_CheckFeatures, GIFBS_HasP8Altivec, 7565 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vaddeuqm, 7566 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 7567 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 7568 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s128, 7569 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s128, 7570 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7571 // (intrinsic_wo_chain:{ *:[v1i128] } 7161:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB, v1i128:{ *:[v1i128] }:$vC) => (VADDEUQM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB, v1i128:{ *:[v1i128] }:$vC) 7572 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VADDEUQM, 7573 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7574 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7575 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7576 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vC 7577 GIR_EraseFromParent, /*InsnID*/0, 7578 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7579 // GIR_Coverage, 467, 7580 GIR_Done, 7581 // Label 584: @17371 7582 GIM_Try, /*On fail goto*//*Label 585*/ 17423, // Rule ID 469 // 7583 GIM_CheckFeatures, GIFBS_HasP8Altivec, 7584 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vaddecuq, 7585 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 7586 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 7587 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s128, 7588 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s128, 7589 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7590 // (intrinsic_wo_chain:{ *:[v1i128] } 7160:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB, v1i128:{ *:[v1i128] }:$vC) => (VADDECUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB, v1i128:{ *:[v1i128] }:$vC) 7591 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VADDECUQ, 7592 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7593 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7594 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7595 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vC 7596 GIR_EraseFromParent, /*InsnID*/0, 7597 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7598 // GIR_Coverage, 469, 7599 GIR_Done, 7600 // Label 585: @17423 7601 GIM_Try, /*On fail goto*//*Label 586*/ 17475, // Rule ID 472 // 7602 GIM_CheckFeatures, GIFBS_HasP8Altivec, 7603 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsubeuqm, 7604 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 7605 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 7606 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s128, 7607 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s128, 7608 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7609 // (intrinsic_wo_chain:{ *:[v1i128] } 7403:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB, v1i128:{ *:[v1i128] }:$vC) => (VSUBEUQM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB, v1i128:{ *:[v1i128] }:$vC) 7610 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSUBEUQM, 7611 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7612 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7613 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7614 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vC 7615 GIR_EraseFromParent, /*InsnID*/0, 7616 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7617 // GIR_Coverage, 472, 7618 GIR_Done, 7619 // Label 586: @17475 7620 GIM_Try, /*On fail goto*//*Label 587*/ 17527, // Rule ID 474 // 7621 GIM_CheckFeatures, GIFBS_HasP8Altivec, 7622 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsubecuq, 7623 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 7624 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 7625 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s128, 7626 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s128, 7627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7628 // (intrinsic_wo_chain:{ *:[v1i128] } 7402:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB, v1i128:{ *:[v1i128] }:$vC) => (VSUBECUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB, v1i128:{ *:[v1i128] }:$vC) 7629 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSUBECUQ, 7630 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7631 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7632 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7633 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vC 7634 GIR_EraseFromParent, /*InsnID*/0, 7635 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7636 // GIR_Coverage, 474, 7637 GIR_Done, 7638 // Label 587: @17527 7639 GIM_Try, /*On fail goto*//*Label 588*/ 17579, // Rule ID 511 // 7640 GIM_CheckFeatures, GIFBS_HasP9Altivec, 7641 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmsumudm, 7642 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 7643 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7644 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7645 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s128, 7646 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7647 // (intrinsic_wo_chain:{ *:[v1i128] } 7318:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB, v1i128:{ *:[v1i128] }:$vC) => (VMSUMUDM:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB, v1i128:{ *:[v1i128] }:$vC) 7648 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMSUMUDM, 7649 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7650 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7651 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7652 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vC 7653 GIR_EraseFromParent, /*InsnID*/0, 7654 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7655 // GIR_Coverage, 511, 7656 GIR_Done, 7657 // Label 588: @17579 7658 GIM_Try, /*On fail goto*//*Label 589*/ 17631, // Rule ID 544 // 7659 GIM_CheckFeatures, GIFBS_HasP9Altivec, 7660 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vrlwmi, 7661 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7662 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7663 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7664 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 7665 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7666 // (intrinsic_wo_chain:{ *:[v4i32] } 7371:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vDi) => (VRLWMI:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vDi) 7667 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VRLWMI, 7668 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7669 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7670 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7671 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vDi 7672 GIR_EraseFromParent, /*InsnID*/0, 7673 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7674 // GIR_Coverage, 544, 7675 GIR_Done, 7676 // Label 589: @17631 7677 GIM_Try, /*On fail goto*//*Label 590*/ 17683, // Rule ID 546 // 7678 GIM_CheckFeatures, GIFBS_HasP9Altivec, 7679 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vrldmi, 7680 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7681 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7682 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7683 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, 7684 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7685 // (intrinsic_wo_chain:{ *:[v2i64] } 7365:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB, v2i64:{ *:[v2i64] }:$vDi) => (VRLDMI:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB, v2i64:{ *:[v2i64] }:$vDi) 7686 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VRLDMI, 7687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7689 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7690 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vDi 7691 GIR_EraseFromParent, /*InsnID*/0, 7692 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7693 // GIR_Coverage, 546, 7694 GIR_Done, 7695 // Label 590: @17683 7696 GIM_Try, /*On fail goto*//*Label 591*/ 17735, // Rule ID 1046 // 7697 GIM_CheckFeatures, GIFBS_IsISA3_1, 7698 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vinsbvlx, 7699 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 7700 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7701 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 7702 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, 7703 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7704 // (intrinsic_wo_chain:{ *:[v16i8] } 7276:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vDi, i32:{ *:[i32] }:$rA, v16i8:{ *:[v16i8] }:$vB) => (VINSBVLX:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vDi, i32:{ *:[i32] }:$rA, v16i8:{ *:[v16i8] }:$vB) 7705 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VINSBVLX, 7706 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7707 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vDi 7708 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rA 7709 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vB 7710 GIR_EraseFromParent, /*InsnID*/0, 7711 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7712 // GIR_Coverage, 1046, 7713 GIR_Done, 7714 // Label 591: @17735 7715 GIM_Try, /*On fail goto*//*Label 592*/ 17787, // Rule ID 1047 // 7716 GIM_CheckFeatures, GIFBS_IsISA3_1, 7717 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vinsbvrx, 7718 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 7719 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7720 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 7721 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, 7722 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7723 // (intrinsic_wo_chain:{ *:[v16i8] } 7277:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vDi, i32:{ *:[i32] }:$rA, v16i8:{ *:[v16i8] }:$vB) => (VINSBVRX:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vDi, i32:{ *:[i32] }:$rA, v16i8:{ *:[v16i8] }:$vB) 7724 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VINSBVRX, 7725 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7726 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vDi 7727 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rA 7728 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vB 7729 GIR_EraseFromParent, /*InsnID*/0, 7730 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7731 // GIR_Coverage, 1047, 7732 GIR_Done, 7733 // Label 592: @17787 7734 GIM_Try, /*On fail goto*//*Label 593*/ 17839, // Rule ID 1048 // 7735 GIM_CheckFeatures, GIFBS_IsISA3_1, 7736 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vinshvlx, 7737 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 7738 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 7739 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 7740 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, 7741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7742 // (intrinsic_wo_chain:{ *:[v8i16] } 7283:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vDi, i32:{ *:[i32] }:$rA, v8i16:{ *:[v8i16] }:$vB) => (VINSHVLX:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vDi, i32:{ *:[i32] }:$rA, v8i16:{ *:[v8i16] }:$vB) 7743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VINSHVLX, 7744 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7745 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vDi 7746 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rA 7747 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vB 7748 GIR_EraseFromParent, /*InsnID*/0, 7749 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7750 // GIR_Coverage, 1048, 7751 GIR_Done, 7752 // Label 593: @17839 7753 GIM_Try, /*On fail goto*//*Label 594*/ 17891, // Rule ID 1049 // 7754 GIM_CheckFeatures, GIFBS_IsISA3_1, 7755 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vinshvrx, 7756 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 7757 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 7758 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 7759 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, 7760 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7761 // (intrinsic_wo_chain:{ *:[v8i16] } 7284:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vDi, i32:{ *:[i32] }:$rA, v8i16:{ *:[v8i16] }:$vB) => (VINSHVRX:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vDi, i32:{ *:[i32] }:$rA, v8i16:{ *:[v8i16] }:$vB) 7762 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VINSHVRX, 7763 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7764 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vDi 7765 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rA 7766 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vB 7767 GIR_EraseFromParent, /*InsnID*/0, 7768 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7769 // GIR_Coverage, 1049, 7770 GIR_Done, 7771 // Label 594: @17891 7772 GIM_Try, /*On fail goto*//*Label 595*/ 17943, // Rule ID 1050 // 7773 GIM_CheckFeatures, GIFBS_IsISA3_1, 7774 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vinswvlx, 7775 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7776 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7777 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 7778 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 7779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7780 // (intrinsic_wo_chain:{ *:[v4i32] } 7288:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vDi, i32:{ *:[i32] }:$rA, v4i32:{ *:[v4i32] }:$vB) => (VINSWVLX:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vDi, i32:{ *:[i32] }:$rA, v4i32:{ *:[v4i32] }:$vB) 7781 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VINSWVLX, 7782 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7783 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vDi 7784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rA 7785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vB 7786 GIR_EraseFromParent, /*InsnID*/0, 7787 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7788 // GIR_Coverage, 1050, 7789 GIR_Done, 7790 // Label 595: @17943 7791 GIM_Try, /*On fail goto*//*Label 596*/ 17995, // Rule ID 1051 // 7792 GIM_CheckFeatures, GIFBS_IsISA3_1, 7793 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vinswvrx, 7794 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7795 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7796 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 7797 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 7798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7799 // (intrinsic_wo_chain:{ *:[v4i32] } 7289:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vDi, i32:{ *:[i32] }:$rA, v4i32:{ *:[v4i32] }:$vB) => (VINSWVRX:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vDi, i32:{ *:[i32] }:$rA, v4i32:{ *:[v4i32] }:$vB) 7800 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VINSWVRX, 7801 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7802 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vDi 7803 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rA 7804 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vB 7805 GIR_EraseFromParent, /*InsnID*/0, 7806 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7807 // GIR_Coverage, 1051, 7808 GIR_Done, 7809 // Label 596: @17995 7810 GIM_Try, /*On fail goto*//*Label 597*/ 18047, // Rule ID 1052 // 7811 GIM_CheckFeatures, GIFBS_IsISA3_1, 7812 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vinsblx, 7813 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 7814 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7815 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 7816 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 7817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7818 // (intrinsic_wo_chain:{ *:[v16i8] } 7274:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vDi, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) => (VINSBLX:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vDi, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) 7819 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VINSBLX, 7820 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7821 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vDi 7822 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rA 7823 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rB 7824 GIR_EraseFromParent, /*InsnID*/0, 7825 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7826 // GIR_Coverage, 1052, 7827 GIR_Done, 7828 // Label 597: @18047 7829 GIM_Try, /*On fail goto*//*Label 598*/ 18099, // Rule ID 1053 // 7830 GIM_CheckFeatures, GIFBS_IsISA3_1, 7831 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vinsbrx, 7832 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 7833 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7834 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 7835 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 7836 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7837 // (intrinsic_wo_chain:{ *:[v16i8] } 7275:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vDi, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) => (VINSBRX:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vDi, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) 7838 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VINSBRX, 7839 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7840 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vDi 7841 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rA 7842 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rB 7843 GIR_EraseFromParent, /*InsnID*/0, 7844 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7845 // GIR_Coverage, 1053, 7846 GIR_Done, 7847 // Label 598: @18099 7848 GIM_Try, /*On fail goto*//*Label 599*/ 18151, // Rule ID 1054 // 7849 GIM_CheckFeatures, GIFBS_IsISA3_1, 7850 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vinshlx, 7851 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 7852 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 7853 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 7854 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 7855 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7856 // (intrinsic_wo_chain:{ *:[v8i16] } 7281:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vDi, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) => (VINSHLX:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vDi, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) 7857 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VINSHLX, 7858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vDi 7860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rA 7861 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rB 7862 GIR_EraseFromParent, /*InsnID*/0, 7863 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7864 // GIR_Coverage, 1054, 7865 GIR_Done, 7866 // Label 599: @18151 7867 GIM_Try, /*On fail goto*//*Label 600*/ 18203, // Rule ID 1055 // 7868 GIM_CheckFeatures, GIFBS_IsISA3_1, 7869 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vinshrx, 7870 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 7871 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 7872 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 7873 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 7874 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7875 // (intrinsic_wo_chain:{ *:[v8i16] } 7282:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vDi, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) => (VINSHRX:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vDi, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) 7876 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VINSHRX, 7877 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vDi 7879 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rA 7880 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rB 7881 GIR_EraseFromParent, /*InsnID*/0, 7882 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7883 // GIR_Coverage, 1055, 7884 GIR_Done, 7885 // Label 600: @18203 7886 GIM_Try, /*On fail goto*//*Label 601*/ 18255, // Rule ID 1056 // 7887 GIM_CheckFeatures, GIFBS_IsISA3_1, 7888 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vinswlx, 7889 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7890 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7891 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 7892 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 7893 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7894 // (intrinsic_wo_chain:{ *:[v4i32] } 7286:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vDi, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) => (VINSWLX:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vDi, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) 7895 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VINSWLX, 7896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7897 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vDi 7898 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rA 7899 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rB 7900 GIR_EraseFromParent, /*InsnID*/0, 7901 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7902 // GIR_Coverage, 1056, 7903 GIR_Done, 7904 // Label 601: @18255 7905 GIM_Try, /*On fail goto*//*Label 602*/ 18307, // Rule ID 1057 // 7906 GIM_CheckFeatures, GIFBS_IsISA3_1, 7907 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vinswrx, 7908 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7909 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7910 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 7911 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 7912 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7913 // (intrinsic_wo_chain:{ *:[v4i32] } 7287:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vDi, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) => (VINSWRX:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vDi, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) 7914 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VINSWRX, 7915 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7916 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vDi 7917 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rA 7918 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rB 7919 GIR_EraseFromParent, /*InsnID*/0, 7920 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7921 // GIR_Coverage, 1057, 7922 GIR_Done, 7923 // Label 602: @18307 7924 GIM_Try, /*On fail goto*//*Label 603*/ 18359, // Rule ID 1058 // 7925 GIM_CheckFeatures, GIFBS_IsISA3_1, 7926 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vinsdlx, 7927 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7928 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7929 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 7930 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64, 7931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7932 // (intrinsic_wo_chain:{ *:[v2i64] } 7279:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vDi, i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) => (VINSDLX:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vDi, i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) 7933 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VINSDLX, 7934 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7935 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vDi 7936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rA 7937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rB 7938 GIR_EraseFromParent, /*InsnID*/0, 7939 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7940 // GIR_Coverage, 1058, 7941 GIR_Done, 7942 // Label 603: @18359 7943 GIM_Try, /*On fail goto*//*Label 604*/ 18411, // Rule ID 1059 // 7944 GIM_CheckFeatures, GIFBS_IsISA3_1, 7945 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vinsdrx, 7946 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7947 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7948 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 7949 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64, 7950 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7951 // (intrinsic_wo_chain:{ *:[v2i64] } 7280:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vDi, i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) => (VINSDRX:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vDi, i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) 7952 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VINSDRX, 7953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7954 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vDi 7955 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rA 7956 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rB 7957 GIR_EraseFromParent, /*InsnID*/0, 7958 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7959 // GIR_Coverage, 1059, 7960 GIR_Done, 7961 // Label 604: @18411 7962 GIM_Try, /*On fail goto*//*Label 605*/ 18463, // Rule ID 1080 // 7963 GIM_CheckFeatures, GIFBS_IsISA3_1, 7964 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vextdubvlx, 7965 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7966 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7967 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 7968 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 7969 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7970 // (intrinsic_wo_chain:{ *:[v2i64] } 7255:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB, i32:{ *:[i32] }:$rC) => (VEXTDUBVLX:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB, i32:{ *:[i32] }:$rC) 7971 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXTDUBVLX, 7972 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7973 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rC 7976 GIR_EraseFromParent, /*InsnID*/0, 7977 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7978 // GIR_Coverage, 1080, 7979 GIR_Done, 7980 // Label 605: @18463 7981 GIM_Try, /*On fail goto*//*Label 606*/ 18515, // Rule ID 1081 // 7982 GIM_CheckFeatures, GIFBS_IsISA3_1, 7983 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vextdubvrx, 7984 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7985 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7986 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 7987 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 7988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 7989 // (intrinsic_wo_chain:{ *:[v2i64] } 7256:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB, i32:{ *:[i32] }:$rC) => (VEXTDUBVRX:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB, i32:{ *:[i32] }:$rC) 7990 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXTDUBVRX, 7991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 7992 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 7993 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 7994 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rC 7995 GIR_EraseFromParent, /*InsnID*/0, 7996 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7997 // GIR_Coverage, 1081, 7998 GIR_Done, 7999 // Label 606: @18515 8000 GIM_Try, /*On fail goto*//*Label 607*/ 18567, // Rule ID 1082 // 8001 GIM_CheckFeatures, GIFBS_IsISA3_1, 8002 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vextduhvlx, 8003 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8004 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 8005 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 8006 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 8007 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 8008 // (intrinsic_wo_chain:{ *:[v2i64] } 7257:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB, i32:{ *:[i32] }:$rC) => (VEXTDUHVLX:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB, i32:{ *:[i32] }:$rC) 8009 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXTDUHVLX, 8010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 8011 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 8012 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 8013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rC 8014 GIR_EraseFromParent, /*InsnID*/0, 8015 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8016 // GIR_Coverage, 1082, 8017 GIR_Done, 8018 // Label 607: @18567 8019 GIM_Try, /*On fail goto*//*Label 608*/ 18619, // Rule ID 1083 // 8020 GIM_CheckFeatures, GIFBS_IsISA3_1, 8021 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vextduhvrx, 8022 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8023 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 8024 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 8025 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 8026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 8027 // (intrinsic_wo_chain:{ *:[v2i64] } 7258:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB, i32:{ *:[i32] }:$rC) => (VEXTDUHVRX:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB, i32:{ *:[i32] }:$rC) 8028 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXTDUHVRX, 8029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 8030 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 8031 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 8032 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rC 8033 GIR_EraseFromParent, /*InsnID*/0, 8034 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8035 // GIR_Coverage, 1083, 8036 GIR_Done, 8037 // Label 608: @18619 8038 GIM_Try, /*On fail goto*//*Label 609*/ 18671, // Rule ID 1084 // 8039 GIM_CheckFeatures, GIFBS_IsISA3_1, 8040 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vextduwvlx, 8041 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8042 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8043 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8044 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 8045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 8046 // (intrinsic_wo_chain:{ *:[v2i64] } 7259:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB, i32:{ *:[i32] }:$rC) => (VEXTDUWVLX:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB, i32:{ *:[i32] }:$rC) 8047 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXTDUWVLX, 8048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 8049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 8050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 8051 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rC 8052 GIR_EraseFromParent, /*InsnID*/0, 8053 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8054 // GIR_Coverage, 1084, 8055 GIR_Done, 8056 // Label 609: @18671 8057 GIM_Try, /*On fail goto*//*Label 610*/ 18723, // Rule ID 1085 // 8058 GIM_CheckFeatures, GIFBS_IsISA3_1, 8059 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vextduwvrx, 8060 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8061 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8062 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8063 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 8064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 8065 // (intrinsic_wo_chain:{ *:[v2i64] } 7260:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB, i32:{ *:[i32] }:$rC) => (VEXTDUWVRX:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB, i32:{ *:[i32] }:$rC) 8066 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXTDUWVRX, 8067 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 8068 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 8069 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 8070 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rC 8071 GIR_EraseFromParent, /*InsnID*/0, 8072 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8073 // GIR_Coverage, 1085, 8074 GIR_Done, 8075 // Label 610: @18723 8076 GIM_Try, /*On fail goto*//*Label 611*/ 18775, // Rule ID 1086 // 8077 GIM_CheckFeatures, GIFBS_IsISA3_1, 8078 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vextddvlx, 8079 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8080 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8081 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8082 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 8083 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 8084 // (intrinsic_wo_chain:{ *:[v2i64] } 7253:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB, i32:{ *:[i32] }:$rC) => (VEXTDDVLX:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB, i32:{ *:[i32] }:$rC) 8085 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXTDDVLX, 8086 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 8087 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 8088 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 8089 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rC 8090 GIR_EraseFromParent, /*InsnID*/0, 8091 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8092 // GIR_Coverage, 1086, 8093 GIR_Done, 8094 // Label 611: @18775 8095 GIM_Try, /*On fail goto*//*Label 612*/ 18827, // Rule ID 1087 // 8096 GIM_CheckFeatures, GIFBS_IsISA3_1, 8097 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vextddvrx, 8098 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8099 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8100 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8101 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 8102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 8103 // (intrinsic_wo_chain:{ *:[v2i64] } 7254:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB, i32:{ *:[i32] }:$rC) => (VEXTDDVRX:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB, i32:{ *:[i32] }:$rC) 8104 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VEXTDDVRX, 8105 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 8106 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 8107 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 8108 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rC 8109 GIR_EraseFromParent, /*InsnID*/0, 8110 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8111 // GIR_Coverage, 1087, 8112 GIR_Done, 8113 // Label 612: @18827 8114 GIM_Try, /*On fail goto*//*Label 613*/ 18879, // Rule ID 1125 // 8115 GIM_CheckFeatures, GIFBS_IsISA3_1, 8116 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmsumcud, 8117 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 8118 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8119 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8120 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s128, 8121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 8122 // (intrinsic_wo_chain:{ *:[v1i128] } 7313:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB, v1i128:{ *:[v1i128] }:$vC) => (VMSUMCUD:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB, v1i128:{ *:[v1i128] }:$vC) 8123 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMSUMCUD, 8124 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 8125 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 8126 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 8127 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vC 8128 GIR_EraseFromParent, /*InsnID*/0, 8129 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8130 // GIR_Coverage, 1125, 8131 GIR_Done, 8132 // Label 613: @18879 8133 GIM_Try, /*On fail goto*//*Label 614*/ 18931, // Rule ID 1140 // 8134 GIM_CheckFeatures, GIFBS_IsISA3_1, 8135 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vrlqmi, 8136 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s128, 8137 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 8138 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s128, 8139 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s128, 8140 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 8141 // (intrinsic_wo_chain:{ *:[v1i128] } 7368:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB, v1i128:{ *:[v1i128] }:$vDi) => (VRLQMI:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB, v1i128:{ *:[v1i128] }:$vDi) 8142 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VRLQMI, 8143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 8144 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 8145 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 8146 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vDi 8147 GIR_EraseFromParent, /*InsnID*/0, 8148 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8149 // GIR_Coverage, 1140, 8150 GIR_Done, 8151 // Label 614: @18931 8152 GIM_Reject, 8153 // Label 568: @18932 8154 GIM_Try, /*On fail goto*//*Label 615*/ 18994, // Rule ID 1095 // 8155 GIM_CheckFeatures, GIFBS_IsISA3_1, 8156 GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, 8157 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_vsx_xxeval, 8158 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8159 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8160 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8161 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, 8162 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 8163 // MIs[0] IMM 8164 GIM_CheckIsImm, /*MI*/0, /*Op*/5, 8165 // (intrinsic_wo_chain:{ *:[v2i64] } 7720:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$XA, v2i64:{ *:[v2i64] }:$XB, v2i64:{ *:[v2i64] }:$XC, (timm:{ *:[i32] }):$IMM) => (XXEVAL:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$XA, v2i64:{ *:[v2i64] }:$XB, v2i64:{ *:[v2i64] }:$XC, (timm:{ *:[i32] }):$IMM) 8166 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XXEVAL, 8167 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 8168 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XA 8169 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XB 8170 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // XC 8171 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // IMM 8172 GIR_EraseFromParent, /*InsnID*/0, 8173 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8174 // GIR_Coverage, 1095, 8175 GIR_Done, 8176 // Label 615: @18994 8177 GIM_Reject, 8178 // Label 17: @18995 8179 GIM_Try, /*On fail goto*//*Label 616*/ 19285, 8180 GIM_CheckNumOperands, /*MI*/0, /*Expected*/1, 8181 GIM_Try, /*On fail goto*//*Label 617*/ 19018, // Rule ID 103 // 8182 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_eieio, 8183 // (intrinsic_void 7475:{ *:[iPTR] }) => (PseudoEIEIO) 8184 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::PseudoEIEIO, 8185 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8186 GIR_EraseFromParent, /*InsnID*/0, 8187 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8188 // GIR_Coverage, 103, 8189 GIR_Done, 8190 // Label 617: @19018 8191 GIM_Try, /*On fail goto*//*Label 618*/ 19041, // Rule ID 1173 // 8192 GIM_CheckFeatures, GIFBS_HasSYNC, 8193 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_sync, 8194 // (intrinsic_void 7624:{ *:[iPTR] }) => (SYNC 0:{ *:[i32] }) 8195 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SYNC, 8196 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 8197 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8198 GIR_EraseFromParent, /*InsnID*/0, 8199 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8200 // GIR_Coverage, 1173, 8201 GIR_Done, 8202 // Label 618: @19041 8203 GIM_Try, /*On fail goto*//*Label 619*/ 19064, // Rule ID 1174 // 8204 GIM_CheckFeatures, GIFBS_HasSYNC, 8205 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_iospace_sync, 8206 // (intrinsic_void 7508:{ *:[iPTR] }) => (SYNC 0:{ *:[i32] }) 8207 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SYNC, 8208 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 8209 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8210 GIR_EraseFromParent, /*InsnID*/0, 8211 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8212 // GIR_Coverage, 1174, 8213 GIR_Done, 8214 // Label 619: @19064 8215 GIM_Try, /*On fail goto*//*Label 620*/ 19087, // Rule ID 1175 // 8216 GIM_CheckFeatures, GIFBS_HasSYNC, 8217 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_lwsync, 8218 // (intrinsic_void 7513:{ *:[iPTR] }) => (SYNC 1:{ *:[i32] }) 8219 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SYNC, 8220 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 8221 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8222 GIR_EraseFromParent, /*InsnID*/0, 8223 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8224 // GIR_Coverage, 1175, 8225 GIR_Done, 8226 // Label 620: @19087 8227 GIM_Try, /*On fail goto*//*Label 621*/ 19110, // Rule ID 1176 // 8228 GIM_CheckFeatures, GIFBS_HasSYNC, 8229 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_iospace_lwsync, 8230 // (intrinsic_void 7507:{ *:[iPTR] }) => (SYNC 1:{ *:[i32] }) 8231 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SYNC, 8232 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 8233 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8234 GIR_EraseFromParent, /*InsnID*/0, 8235 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8236 // GIR_Coverage, 1176, 8237 GIR_Done, 8238 // Label 621: @19110 8239 GIM_Try, /*On fail goto*//*Label 622*/ 19130, // Rule ID 1177 // 8240 GIM_CheckFeatures, GIFBS_HasOnlyMSYNC, 8241 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_sync, 8242 // (intrinsic_void 7624:{ *:[iPTR] }) => (MSYNC) 8243 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MSYNC, 8244 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8245 GIR_EraseFromParent, /*InsnID*/0, 8246 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8247 // GIR_Coverage, 1177, 8248 GIR_Done, 8249 // Label 622: @19130 8250 GIM_Try, /*On fail goto*//*Label 623*/ 19150, // Rule ID 1178 // 8251 GIM_CheckFeatures, GIFBS_HasOnlyMSYNC, 8252 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_iospace_sync, 8253 // (intrinsic_void 7508:{ *:[iPTR] }) => (MSYNC) 8254 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MSYNC, 8255 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8256 GIR_EraseFromParent, /*InsnID*/0, 8257 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8258 // GIR_Coverage, 1178, 8259 GIR_Done, 8260 // Label 623: @19150 8261 GIM_Try, /*On fail goto*//*Label 624*/ 19170, // Rule ID 1179 // 8262 GIM_CheckFeatures, GIFBS_HasOnlyMSYNC, 8263 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_lwsync, 8264 // (intrinsic_void 7513:{ *:[iPTR] }) => (MSYNC) 8265 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MSYNC, 8266 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8267 GIR_EraseFromParent, /*InsnID*/0, 8268 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8269 // GIR_Coverage, 1179, 8270 GIR_Done, 8271 // Label 624: @19170 8272 GIM_Try, /*On fail goto*//*Label 625*/ 19190, // Rule ID 1180 // 8273 GIM_CheckFeatures, GIFBS_HasOnlyMSYNC, 8274 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_iospace_lwsync, 8275 // (intrinsic_void 7507:{ *:[iPTR] }) => (MSYNC) 8276 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MSYNC, 8277 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8278 GIR_EraseFromParent, /*InsnID*/0, 8279 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8280 // GIR_Coverage, 1180, 8281 GIR_Done, 8282 // Label 625: @19190 8283 GIM_Try, /*On fail goto*//*Label 626*/ 19208, // Rule ID 1181 // 8284 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_eieio, 8285 // (intrinsic_void 7475:{ *:[iPTR] }) => (PseudoEIEIO) 8286 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::PseudoEIEIO, 8287 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8288 GIR_EraseFromParent, /*InsnID*/0, 8289 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8290 // GIR_Coverage, 1181, 8291 GIR_Done, 8292 // Label 626: @19208 8293 GIM_Try, /*On fail goto*//*Label 627*/ 19226, // Rule ID 1182 // 8294 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_iospace_eieio, 8295 // (intrinsic_void 7506:{ *:[iPTR] }) => (PseudoEIEIO) 8296 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::PseudoEIEIO, 8297 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8298 GIR_EraseFromParent, /*InsnID*/0, 8299 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8300 // GIR_Coverage, 1182, 8301 GIR_Done, 8302 // Label 627: @19226 8303 GIM_Try, /*On fail goto*//*Label 628*/ 19246, // Rule ID 1259 // 8304 GIM_CheckFeatures, GIFBS_IsAIX, 8305 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_altivec_dssall, 8306 // (intrinsic_void 7131:{ *:[iPTR] }) => (NOP) 8307 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::NOP, 8308 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8309 GIR_EraseFromParent, /*InsnID*/0, 8310 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8311 // GIR_Coverage, 1259, 8312 GIR_Done, 8313 // Label 628: @19246 8314 GIM_Try, /*On fail goto*//*Label 629*/ 19266, // Rule ID 1260 // 8315 GIM_CheckFeatures, GIFBS_NotAIX, 8316 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_altivec_dssall, 8317 // (intrinsic_void 7131:{ *:[iPTR] }) => (DSSALL) 8318 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::DSSALL, 8319 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8320 GIR_EraseFromParent, /*InsnID*/0, 8321 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8322 // GIR_Coverage, 1260, 8323 GIR_Done, 8324 // Label 629: @19266 8325 GIM_Try, /*On fail goto*//*Label 630*/ 19284, // Rule ID 4797 // 8326 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_isync, 8327 // (intrinsic_void 7509:{ *:[iPTR] }) => (ISYNC) 8328 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::ISYNC, 8329 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8330 GIR_EraseFromParent, /*InsnID*/0, 8331 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8332 // GIR_Coverage, 4797, 8333 GIR_Done, 8334 // Label 630: @19284 8335 GIM_Reject, 8336 // Label 616: @19285 8337 GIM_Try, /*On fail goto*//*Label 631*/ 19804, 8338 GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, 8339 GIM_Try, /*On fail goto*//*Label 632*/ 19327, // Rule ID 265 // 8340 GIM_CheckFeatures, GIFBS_HasAltivec, 8341 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_altivec_dss, 8342 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 8343 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 8344 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 8345 // MIs[1] Operand 1 8346 // No operand predicates 8347 GIM_CheckIsSafeToFold, /*InsnID*/1, 8348 // (intrinsic_void 7130:{ *:[iPTR] }, (imm:{ *:[i32] }):$STRM) => (DSS (imm:{ *:[i32] }):$STRM) 8349 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::DSS, 8350 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM 8351 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 8352 GIR_EraseFromParent, /*InsnID*/0, 8353 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8354 // GIR_Coverage, 265, 8355 GIR_Done, 8356 // Label 632: @19327 8357 GIM_Try, /*On fail goto*//*Label 633*/ 19350, // Rule ID 190 // 8358 GIM_CheckFeatures, GIFBS_HasFPU, 8359 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_mtfsb0, 8360 // MIs[0] FM 8361 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 8362 // (intrinsic_void 7589:{ *:[iPTR] }, (timm:{ *:[i32] }):$FM) => (MTFSB0 (timm:{ *:[i32] }):$FM) 8363 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MTFSB0, 8364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // FM 8365 GIR_EraseFromParent, /*InsnID*/0, 8366 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8367 // GIR_Coverage, 190, 8368 GIR_Done, 8369 // Label 633: @19350 8370 GIM_Try, /*On fail goto*//*Label 634*/ 19373, // Rule ID 191 // 8371 GIM_CheckFeatures, GIFBS_HasFPU, 8372 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_mtfsb1, 8373 // MIs[0] FM 8374 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 8375 // (intrinsic_void 7590:{ *:[iPTR] }, (timm:{ *:[i32] }):$FM) => (MTFSB1 (timm:{ *:[i32] }):$FM) 8376 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MTFSB1, 8377 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // FM 8378 GIR_EraseFromParent, /*InsnID*/0, 8379 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8380 // GIR_Coverage, 191, 8381 GIR_Done, 8382 // Label 634: @19373 8383 GIM_Try, /*On fail goto*//*Label 635*/ 19401, // Rule ID 274 // 8384 GIM_CheckFeatures, GIFBS_HasAltivec, 8385 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_mfvscr, 8386 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 8387 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 8388 // (intrinsic_w_chain:{ *:[v8i16] } 7143:{ *:[iPTR] }) => (MFVSCR:{ *:[v8i16] }) 8389 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MFVSCR, 8390 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 8391 GIR_EraseFromParent, /*InsnID*/0, 8392 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8393 // GIR_Coverage, 274, 8394 GIR_Done, 8395 // Label 635: @19401 8396 GIM_Try, /*On fail goto*//*Label 636*/ 19427, // Rule ID 1208 // 8397 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_readflm, 8398 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 8399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 8400 // (intrinsic_w_chain:{ *:[f64] } 7604:{ *:[iPTR] }) => (MFFS:{ *:[f64] }) 8401 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MFFS, 8402 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rT 8403 GIR_EraseFromParent, /*InsnID*/0, 8404 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8405 // GIR_Coverage, 1208, 8406 GIR_Done, 8407 // Label 636: @19427 8408 GIM_Try, /*On fail goto*//*Label 637*/ 19485, // Rule ID 1539 // 8409 GIM_CheckFeatures, GIFBS_IsISA3_0, 8410 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_darn32, 8411 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 8412 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 8413 // (intrinsic_w_chain:{ *:[i32] } 7452:{ *:[iPTR] }) => (EXTRACT_SUBREG:{ *:[i32] } (DARN:{ *:[i64] } 0:{ *:[i32] }), sub_32:{ *:[i32] }) 8414 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 8415 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::DARN, 8416 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 8417 GIR_AddImm, /*InsnID*/1, /*Imm*/0, 8418 GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8419 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 8420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8421 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8422 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_32, 8423 GIR_EraseFromParent, /*InsnID*/0, 8424 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::GPRCRegClassID, 8425 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::G8RCRegClassID, 8426 // GIR_Coverage, 1539, 8427 GIR_Done, 8428 // Label 637: @19485 8429 GIM_Try, /*On fail goto*//*Label 638*/ 19520, // Rule ID 1540 // 8430 GIM_CheckFeatures, GIFBS_IsISA3_0, 8431 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_darn, 8432 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 8433 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 8434 // (intrinsic_w_chain:{ *:[i64] } 7451:{ *:[iPTR] }) => (DARN:{ *:[i64] } 1:{ *:[i32] }) 8435 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::DARN, 8436 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RT 8437 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 8438 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8439 GIR_EraseFromParent, /*InsnID*/0, 8440 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8441 // GIR_Coverage, 1540, 8442 GIR_Done, 8443 // Label 638: @19520 8444 GIM_Try, /*On fail goto*//*Label 639*/ 19555, // Rule ID 1541 // 8445 GIM_CheckFeatures, GIFBS_IsISA3_0, 8446 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_darnraw, 8447 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 8448 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 8449 // (intrinsic_w_chain:{ *:[i64] } 7453:{ *:[iPTR] }) => (DARN:{ *:[i64] } 2:{ *:[i32] }) 8450 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::DARN, 8451 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RT 8452 GIR_AddImm, /*InsnID*/0, /*Imm*/2, 8453 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8454 GIR_EraseFromParent, /*InsnID*/0, 8455 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8456 // GIR_Coverage, 1541, 8457 GIR_Done, 8458 // Label 639: @19555 8459 GIM_Try, /*On fail goto*//*Label 640*/ 19587, // Rule ID 2859 // 8460 GIM_CheckFeatures, GIFBS_HasHTM, 8461 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_tcheck, 8462 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 8463 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 8464 // (intrinsic_w_chain:{ *:[i32] } 7631:{ *:[iPTR] }) => (TCHECK_RET:{ *:[i32] }) 8465 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::TCHECK_RET, 8466 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out 8467 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8468 GIR_EraseFromParent, /*InsnID*/0, 8469 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8470 // GIR_Coverage, 2859, 8471 GIR_Done, 8472 // Label 640: @19587 8473 GIM_Try, /*On fail goto*//*Label 641*/ 19622, // Rule ID 2863 // 8474 GIM_CheckFeatures, GIFBS_HasHTM, 8475 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_get_texasr, 8476 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 8477 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 8478 // (intrinsic_w_chain:{ *:[i64] } 7500:{ *:[iPTR] }) => (MFSPR8:{ *:[i64] } 130:{ *:[i32] }) 8479 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MFSPR8, 8480 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RT 8481 GIR_AddImm, /*InsnID*/0, /*Imm*/130, 8482 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8483 GIR_EraseFromParent, /*InsnID*/0, 8484 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8485 // GIR_Coverage, 2863, 8486 GIR_Done, 8487 // Label 641: @19622 8488 GIM_Try, /*On fail goto*//*Label 642*/ 19657, // Rule ID 2864 // 8489 GIM_CheckFeatures, GIFBS_HasHTM, 8490 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_get_texasru, 8491 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 8492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 8493 // (intrinsic_w_chain:{ *:[i64] } 7501:{ *:[iPTR] }) => (MFSPR8:{ *:[i64] } 131:{ *:[i32] }) 8494 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MFSPR8, 8495 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RT 8496 GIR_AddImm, /*InsnID*/0, /*Imm*/131, 8497 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8498 GIR_EraseFromParent, /*InsnID*/0, 8499 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8500 // GIR_Coverage, 2864, 8501 GIR_Done, 8502 // Label 642: @19657 8503 GIM_Try, /*On fail goto*//*Label 643*/ 19692, // Rule ID 2865 // 8504 GIM_CheckFeatures, GIFBS_HasHTM, 8505 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_get_tfhar, 8506 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 8507 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 8508 // (intrinsic_w_chain:{ *:[i64] } 7502:{ *:[iPTR] }) => (MFSPR8:{ *:[i64] } 128:{ *:[i32] }) 8509 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MFSPR8, 8510 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RT 8511 GIR_AddImm, /*InsnID*/0, /*Imm*/128, 8512 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8513 GIR_EraseFromParent, /*InsnID*/0, 8514 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8515 // GIR_Coverage, 2865, 8516 GIR_Done, 8517 // Label 643: @19692 8518 GIM_Try, /*On fail goto*//*Label 644*/ 19727, // Rule ID 2866 // 8519 GIM_CheckFeatures, GIFBS_HasHTM, 8520 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_get_tfiar, 8521 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 8522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 8523 // (intrinsic_w_chain:{ *:[i64] } 7503:{ *:[iPTR] }) => (MFSPR8:{ *:[i64] } 129:{ *:[i32] }) 8524 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MFSPR8, 8525 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RT 8526 GIR_AddImm, /*InsnID*/0, /*Imm*/129, 8527 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8528 GIR_EraseFromParent, /*InsnID*/0, 8529 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8530 // GIR_Coverage, 2866, 8531 GIR_Done, 8532 // Label 644: @19727 8533 GIM_Try, /*On fail goto*//*Label 645*/ 19753, // Rule ID 186 // 8534 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::set_loop_iterations, 8535 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 8536 // (intrinsic_void 269:{ *:[iPTR] }, i32:{ *:[i32] }:$rS) => (MTCTRloop:{ *:[i32] } i32:{ *:[i32] }:$rS) 8537 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MTCTRloop, 8538 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rS 8539 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8540 GIR_EraseFromParent, /*InsnID*/0, 8541 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8542 // GIR_Coverage, 186, 8543 GIR_Done, 8544 // Label 645: @19753 8545 GIM_Try, /*On fail goto*//*Label 646*/ 19777, // Rule ID 275 // 8546 GIM_CheckFeatures, GIFBS_HasAltivec, 8547 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_altivec_mtvscr, 8548 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 8549 // (intrinsic_void 7144:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vB) => (MTVSCR v4i32:{ *:[v4i32] }:$vB) 8550 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MTVSCR, 8551 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vB 8552 GIR_EraseFromParent, /*InsnID*/0, 8553 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8554 // GIR_Coverage, 275, 8555 GIR_Done, 8556 // Label 646: @19777 8557 GIM_Try, /*On fail goto*//*Label 647*/ 19803, // Rule ID 629 // 8558 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::set_loop_iterations, 8559 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 8560 // (intrinsic_void 269:{ *:[iPTR] }, i64:{ *:[i64] }:$rS) => (MTCTR8loop:{ *:[i64] } i64:{ *:[i64] }:$rS) 8561 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MTCTR8loop, 8562 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rS 8563 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8564 GIR_EraseFromParent, /*InsnID*/0, 8565 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8566 // GIR_Coverage, 629, 8567 GIR_Done, 8568 // Label 647: @19803 8569 GIM_Reject, 8570 // Label 631: @19804 8571 GIM_Try, /*On fail goto*//*Label 648*/ 20096, 8572 GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, 8573 GIM_Try, /*On fail goto*//*Label 649*/ 19839, // Rule ID 1151 // 8574 GIM_CheckFeatures, GIFBS_HasFPU, 8575 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_mtfsfi, 8576 // MIs[0] BF 8577 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 8578 // MIs[0] U 8579 GIM_CheckIsImm, /*MI*/0, /*Op*/2, 8580 // (intrinsic_void 7592:{ *:[iPTR] }, (timm:{ *:[i32] }):$BF, (timm:{ *:[i32] }):$U) => (MTFSFIb (timm:{ *:[i32] }):$BF, (timm:{ *:[i32] }):$U) 8581 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MTFSFIb, 8582 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // BF 8583 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // U 8584 GIR_EraseFromParent, /*InsnID*/0, 8585 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8586 // GIR_Coverage, 1151, 8587 GIR_Done, 8588 // Label 649: @19839 8589 GIM_Try, /*On fail goto*//*Label 650*/ 19886, // Rule ID 12 // 8590 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_setrnd, 8591 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 8592 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 8593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 8594 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 8595 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 8596 // MIs[1] Operand 1 8597 // No operand predicates 8598 GIM_CheckIsSafeToFold, /*InsnID*/1, 8599 // (intrinsic_w_chain:{ *:[f64] } 7613:{ *:[iPTR] }, (imm:{ *:[i32] }):$RND) => (SETRNDi:{ *:[f64] } (imm:{ *:[i32] }):$RND) 8600 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SETRNDi, 8601 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // FRT 8602 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // RND 8603 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 8604 GIR_EraseFromParent, /*InsnID*/0, 8605 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8606 // GIR_Coverage, 12, 8607 GIR_Done, 8608 // Label 650: @19886 8609 GIM_Try, /*On fail goto*//*Label 651*/ 19933, // Rule ID 187 // 8610 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::loop_decrement, 8611 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1, 8612 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 8613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 8614 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 8615 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 8616 // MIs[1] Operand 1 8617 // No operand predicates 8618 GIM_CheckIsSafeToFold, /*InsnID*/1, 8619 // (intrinsic_w_chain:{ *:[i1] } 178:{ *:[iPTR] }, (imm:{ *:[i32] }):$stride) => (DecreaseCTRloop:{ *:[i1] }:{ *:[i32] } (imm:{ *:[i32] }):$stride) 8620 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::DecreaseCTRloop, 8621 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rT 8622 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // stride 8623 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 8624 GIR_EraseFromParent, /*InsnID*/0, 8625 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8626 // GIR_Coverage, 187, 8627 GIR_Done, 8628 // Label 651: @19933 8629 GIM_Try, /*On fail goto*//*Label 652*/ 19980, // Rule ID 630 // 8630 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::loop_decrement, 8631 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1, 8632 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 8633 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 8634 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 8635 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 8636 // MIs[1] Operand 1 8637 // No operand predicates 8638 GIM_CheckIsSafeToFold, /*InsnID*/1, 8639 // (intrinsic_w_chain:{ *:[i1] } 178:{ *:[iPTR] }, (imm:{ *:[i64] }):$stride) => (DecreaseCTR8loop:{ *:[i1] }:{ *:[i64] } (imm:{ *:[i64] }):$stride) 8640 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::DecreaseCTR8loop, 8641 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rT 8642 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // stride 8643 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 8644 GIR_EraseFromParent, /*InsnID*/0, 8645 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8646 // GIR_Coverage, 630, 8647 GIR_Done, 8648 // Label 652: @19980 8649 GIM_Try, /*On fail goto*//*Label 653*/ 20011, // Rule ID 192 // 8650 GIM_CheckFeatures, GIFBS_HasFPU, 8651 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_mtfsf, 8652 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 8653 // MIs[0] FM 8654 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 8655 // (intrinsic_void 7591:{ *:[iPTR] }, (timm:{ *:[i32] }):$FM, f64:{ *:[f64] }:$rT) => (MTFSFb (timm:{ *:[i32] }):$FM, f64:{ *:[f64] }:$rT) 8656 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::MTFSFb, 8657 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // FM 8658 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rT 8659 GIR_EraseFromParent, /*InsnID*/0, 8660 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8661 // GIR_Coverage, 192, 8662 GIR_Done, 8663 // Label 653: @20011 8664 GIM_Try, /*On fail goto*//*Label 654*/ 20053, // Rule ID 13 // 8665 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_setrnd, 8666 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 8667 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 8668 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 8669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/PPC::GPRCRegClassID, 8670 // (intrinsic_w_chain:{ *:[f64] } 7613:{ *:[iPTR] }, gprc:{ *:[i32] }:$in) => (SETRND:{ *:[f64] } gprc:{ *:[i32] }:$in) 8671 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SETRND, 8672 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // FRT 8673 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in 8674 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8675 GIR_EraseFromParent, /*InsnID*/0, 8676 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8677 // GIR_Coverage, 13, 8678 GIR_Done, 8679 // Label 654: @20053 8680 GIM_Try, /*On fail goto*//*Label 655*/ 20095, // Rule ID 14 // 8681 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_setflm, 8682 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 8683 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 8684 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 8685 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/PPC::F8RCRegClassID, 8686 // (intrinsic_w_chain:{ *:[f64] } 7612:{ *:[iPTR] }, f8rc:{ *:[f64] }:$FLM) => (SETFLM:{ *:[f64] } f8rc:{ *:[f64] }:$FLM) 8687 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SETFLM, 8688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // FRT 8689 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // FLM 8690 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 8691 GIR_EraseFromParent, /*InsnID*/0, 8692 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8693 // GIR_Coverage, 14, 8694 GIR_Done, 8695 // Label 655: @20095 8696 GIM_Reject, 8697 // Label 648: @20096 8698 GIM_Try, /*On fail goto*//*Label 656*/ 21142, 8699 GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, 8700 GIM_Try, /*On fail goto*//*Label 657*/ 20154, // Rule ID 266 // 8701 GIM_CheckFeatures, GIFBS_HasAltivec, 8702 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_altivec_dst, 8703 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 8704 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 8705 // MIs[0] rA 8706 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8707 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 8708 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 8709 // MIs[1] Operand 1 8710 // No operand predicates 8711 GIM_CheckIsSafeToFold, /*InsnID*/1, 8712 // (intrinsic_void 7132:{ *:[iPTR] }, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB, (imm:{ *:[i32] }):$STRM) => (DST (imm:{ *:[i32] }):$STRM, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) 8713 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::DST, 8714 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM 8715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rA 8716 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rB 8717 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 8718 GIR_EraseFromParent, /*InsnID*/0, 8719 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8720 // GIR_Coverage, 266, 8721 GIR_Done, 8722 // Label 657: @20154 8723 GIM_Try, /*On fail goto*//*Label 658*/ 20207, // Rule ID 267 // 8724 GIM_CheckFeatures, GIFBS_HasAltivec, 8725 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_altivec_dstt, 8726 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 8727 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 8728 // MIs[0] rA 8729 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8730 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 8731 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 8732 // MIs[1] Operand 1 8733 // No operand predicates 8734 GIM_CheckIsSafeToFold, /*InsnID*/1, 8735 // (intrinsic_void 7135:{ *:[iPTR] }, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB, (imm:{ *:[i32] }):$STRM) => (DSTT (imm:{ *:[i32] }):$STRM, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) 8736 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::DSTT, 8737 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM 8738 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rA 8739 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rB 8740 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 8741 GIR_EraseFromParent, /*InsnID*/0, 8742 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8743 // GIR_Coverage, 267, 8744 GIR_Done, 8745 // Label 658: @20207 8746 GIM_Try, /*On fail goto*//*Label 659*/ 20260, // Rule ID 268 // 8747 GIM_CheckFeatures, GIFBS_HasAltivec, 8748 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_altivec_dstst, 8749 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 8750 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 8751 // MIs[0] rA 8752 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8753 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 8754 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 8755 // MIs[1] Operand 1 8756 // No operand predicates 8757 GIM_CheckIsSafeToFold, /*InsnID*/1, 8758 // (intrinsic_void 7133:{ *:[iPTR] }, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB, (imm:{ *:[i32] }):$STRM) => (DSTST (imm:{ *:[i32] }):$STRM, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) 8759 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::DSTST, 8760 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM 8761 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rA 8762 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rB 8763 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 8764 GIR_EraseFromParent, /*InsnID*/0, 8765 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8766 // GIR_Coverage, 268, 8767 GIR_Done, 8768 // Label 659: @20260 8769 GIM_Try, /*On fail goto*//*Label 660*/ 20313, // Rule ID 269 // 8770 GIM_CheckFeatures, GIFBS_HasAltivec, 8771 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_altivec_dststt, 8772 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 8773 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 8774 // MIs[0] rA 8775 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8776 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 8777 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 8778 // MIs[1] Operand 1 8779 // No operand predicates 8780 GIM_CheckIsSafeToFold, /*InsnID*/1, 8781 // (intrinsic_void 7134:{ *:[iPTR] }, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB, (imm:{ *:[i32] }):$STRM) => (DSTSTT (imm:{ *:[i32] }):$STRM, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) 8782 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::DSTSTT, 8783 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM 8784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rA 8785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rB 8786 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 8787 GIR_EraseFromParent, /*InsnID*/0, 8788 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8789 // GIR_Coverage, 269, 8790 GIR_Done, 8791 // Label 660: @20313 8792 GIM_Try, /*On fail goto*//*Label 661*/ 20366, // Rule ID 270 // 8793 GIM_CheckFeatures, GIFBS_HasAltivec, 8794 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_altivec_dst, 8795 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 8796 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 8797 // MIs[0] rA 8798 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8799 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 8800 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 8801 // MIs[1] Operand 1 8802 // No operand predicates 8803 GIM_CheckIsSafeToFold, /*InsnID*/1, 8804 // (intrinsic_void 7132:{ *:[iPTR] }, i64:{ *:[i64] }:$rA, i32:{ *:[i32] }:$rB, (imm:{ *:[i32] }):$STRM) => (DST64 (imm:{ *:[i32] }):$STRM, i64:{ *:[i64] }:$rA, i32:{ *:[i32] }:$rB) 8805 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::DST64, 8806 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM 8807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rA 8808 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rB 8809 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 8810 GIR_EraseFromParent, /*InsnID*/0, 8811 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8812 // GIR_Coverage, 270, 8813 GIR_Done, 8814 // Label 661: @20366 8815 GIM_Try, /*On fail goto*//*Label 662*/ 20419, // Rule ID 271 // 8816 GIM_CheckFeatures, GIFBS_HasAltivec, 8817 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_altivec_dstt, 8818 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 8819 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 8820 // MIs[0] rA 8821 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8822 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 8823 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 8824 // MIs[1] Operand 1 8825 // No operand predicates 8826 GIM_CheckIsSafeToFold, /*InsnID*/1, 8827 // (intrinsic_void 7135:{ *:[iPTR] }, i64:{ *:[i64] }:$rA, i32:{ *:[i32] }:$rB, (imm:{ *:[i32] }):$STRM) => (DSTT64 (imm:{ *:[i32] }):$STRM, i64:{ *:[i64] }:$rA, i32:{ *:[i32] }:$rB) 8828 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::DSTT64, 8829 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM 8830 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rA 8831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rB 8832 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 8833 GIR_EraseFromParent, /*InsnID*/0, 8834 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8835 // GIR_Coverage, 271, 8836 GIR_Done, 8837 // Label 662: @20419 8838 GIM_Try, /*On fail goto*//*Label 663*/ 20472, // Rule ID 272 // 8839 GIM_CheckFeatures, GIFBS_HasAltivec, 8840 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_altivec_dstst, 8841 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 8842 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 8843 // MIs[0] rA 8844 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8845 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 8846 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 8847 // MIs[1] Operand 1 8848 // No operand predicates 8849 GIM_CheckIsSafeToFold, /*InsnID*/1, 8850 // (intrinsic_void 7133:{ *:[iPTR] }, i64:{ *:[i64] }:$rA, i32:{ *:[i32] }:$rB, (imm:{ *:[i32] }):$STRM) => (DSTST64 (imm:{ *:[i32] }):$STRM, i64:{ *:[i64] }:$rA, i32:{ *:[i32] }:$rB) 8851 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::DSTST64, 8852 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM 8853 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rA 8854 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rB 8855 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 8856 GIR_EraseFromParent, /*InsnID*/0, 8857 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8858 // GIR_Coverage, 272, 8859 GIR_Done, 8860 // Label 663: @20472 8861 GIM_Try, /*On fail goto*//*Label 664*/ 20525, // Rule ID 273 // 8862 GIM_CheckFeatures, GIFBS_HasAltivec, 8863 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::ppc_altivec_dststt, 8864 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 8865 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 8866 // MIs[0] rA 8867 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8868 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 8869 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 8870 // MIs[1] Operand 1 8871 // No operand predicates 8872 GIM_CheckIsSafeToFold, /*InsnID*/1, 8873 // (intrinsic_void 7134:{ *:[iPTR] }, i64:{ *:[i64] }:$rA, i32:{ *:[i32] }:$rB, (imm:{ *:[i32] }):$STRM) => (DSTSTT64 (imm:{ *:[i32] }):$STRM, i64:{ *:[i64] }:$rA, i32:{ *:[i32] }:$rB) 8874 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::DSTSTT64, 8875 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM 8876 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rA 8877 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rB 8878 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 8879 GIR_EraseFromParent, /*InsnID*/0, 8880 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8881 // GIR_Coverage, 273, 8882 GIR_Done, 8883 // Label 664: @20525 8884 GIM_Try, /*On fail goto*//*Label 665*/ 20569, // Rule ID 376 // 8885 GIM_CheckFeatures, GIFBS_HasAltivec, 8886 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsumsws, 8887 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8888 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8889 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8890 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 8891 // (intrinsic_w_chain:{ *:[v4i32] } 7414:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSUMSWS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 8892 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSUMSWS, 8893 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 8894 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 8895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 8896 GIR_EraseFromParent, /*InsnID*/0, 8897 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8898 // GIR_Coverage, 376, 8899 GIR_Done, 8900 // Label 665: @20569 8901 GIM_Try, /*On fail goto*//*Label 666*/ 20613, // Rule ID 377 // 8902 GIM_CheckFeatures, GIFBS_HasAltivec, 8903 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsum2sws, 8904 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8905 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8906 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8907 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 8908 // (intrinsic_w_chain:{ *:[v4i32] } 7410:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSUM2SWS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 8909 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSUM2SWS, 8910 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 8911 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 8912 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 8913 GIR_EraseFromParent, /*InsnID*/0, 8914 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8915 // GIR_Coverage, 377, 8916 GIR_Done, 8917 // Label 666: @20613 8918 GIM_Try, /*On fail goto*//*Label 667*/ 20657, // Rule ID 378 // 8919 GIM_CheckFeatures, GIFBS_HasAltivec, 8920 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsum4sbs, 8921 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8922 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 8923 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8924 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 8925 // (intrinsic_w_chain:{ *:[v4i32] } 7411:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSUM4SBS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$vA, v4i32:{ *:[v4i32] }:$vB) 8926 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSUM4SBS, 8927 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 8928 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 8929 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 8930 GIR_EraseFromParent, /*InsnID*/0, 8931 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8932 // GIR_Coverage, 378, 8933 GIR_Done, 8934 // Label 667: @20657 8935 GIM_Try, /*On fail goto*//*Label 668*/ 20701, // Rule ID 379 // 8936 GIM_CheckFeatures, GIFBS_HasAltivec, 8937 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsum4shs, 8938 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8939 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 8940 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8941 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 8942 // (intrinsic_w_chain:{ *:[v4i32] } 7412:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSUM4SHS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$vA, v4i32:{ *:[v4i32] }:$vB) 8943 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSUM4SHS, 8944 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 8945 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 8946 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 8947 GIR_EraseFromParent, /*InsnID*/0, 8948 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8949 // GIR_Coverage, 379, 8950 GIR_Done, 8951 // Label 668: @20701 8952 GIM_Try, /*On fail goto*//*Label 669*/ 20745, // Rule ID 380 // 8953 GIM_CheckFeatures, GIFBS_HasAltivec, 8954 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vsum4ubs, 8955 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8956 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 8957 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8958 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 8959 // (intrinsic_w_chain:{ *:[v4i32] } 7413:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSUM4UBS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$vA, v4i32:{ *:[v4i32] }:$vB) 8960 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VSUM4UBS, 8961 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 8962 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 8963 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 8964 GIR_EraseFromParent, /*InsnID*/0, 8965 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8966 // GIR_Coverage, 380, 8967 GIR_Done, 8968 // Label 669: @20745 8969 GIM_Try, /*On fail goto*//*Label 670*/ 20789, // Rule ID 407 // 8970 GIM_CheckFeatures, GIFBS_HasAltivec, 8971 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vpkshss, 8972 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 8973 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 8974 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 8975 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 8976 // (intrinsic_w_chain:{ *:[v16i8] } 7348:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VPKSHSS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 8977 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VPKSHSS, 8978 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 8979 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 8980 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 8981 GIR_EraseFromParent, /*InsnID*/0, 8982 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8983 // GIR_Coverage, 407, 8984 GIR_Done, 8985 // Label 670: @20789 8986 GIM_Try, /*On fail goto*//*Label 671*/ 20833, // Rule ID 408 // 8987 GIM_CheckFeatures, GIFBS_HasAltivec, 8988 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vpkshus, 8989 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 8990 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 8991 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 8992 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 8993 // (intrinsic_w_chain:{ *:[v16i8] } 7349:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VPKSHUS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 8994 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VPKSHUS, 8995 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 8996 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 8997 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 8998 GIR_EraseFromParent, /*InsnID*/0, 8999 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9000 // GIR_Coverage, 408, 9001 GIR_Done, 9002 // Label 671: @20833 9003 GIM_Try, /*On fail goto*//*Label 672*/ 20877, // Rule ID 409 // 9004 GIM_CheckFeatures, GIFBS_HasAltivec, 9005 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vpkswss, 9006 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 9007 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 9008 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 9009 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 9010 // (intrinsic_w_chain:{ *:[v8i16] } 7350:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VPKSWSS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 9011 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VPKSWSS, 9012 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 9013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 9014 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 9015 GIR_EraseFromParent, /*InsnID*/0, 9016 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9017 // GIR_Coverage, 409, 9018 GIR_Done, 9019 // Label 672: @20877 9020 GIM_Try, /*On fail goto*//*Label 673*/ 20921, // Rule ID 410 // 9021 GIM_CheckFeatures, GIFBS_HasAltivec, 9022 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vpkswus, 9023 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 9024 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 9025 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 9026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 9027 // (intrinsic_w_chain:{ *:[v8i16] } 7351:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VPKSWUS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 9028 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VPKSWUS, 9029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 9030 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 9031 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 9032 GIR_EraseFromParent, /*InsnID*/0, 9033 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9034 // GIR_Coverage, 410, 9035 GIR_Done, 9036 // Label 673: @20921 9037 GIM_Try, /*On fail goto*//*Label 674*/ 20965, // Rule ID 411 // 9038 GIM_CheckFeatures, GIFBS_HasAltivec, 9039 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vpkuhus, 9040 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 9041 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 9042 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 9043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 9044 // (intrinsic_w_chain:{ *:[v16i8] } 7353:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VPKUHUS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 9045 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VPKUHUS, 9046 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 9047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 9048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 9049 GIR_EraseFromParent, /*InsnID*/0, 9050 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9051 // GIR_Coverage, 411, 9052 GIR_Done, 9053 // Label 674: @20965 9054 GIM_Try, /*On fail goto*//*Label 675*/ 21009, // Rule ID 412 // 9055 GIM_CheckFeatures, GIFBS_HasAltivec, 9056 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vpkuwus, 9057 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 9058 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 9059 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 9060 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 9061 // (intrinsic_w_chain:{ *:[v8i16] } 7354:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VPKUWUS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 9062 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VPKUWUS, 9063 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 9064 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 9065 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 9066 GIR_EraseFromParent, /*InsnID*/0, 9067 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9068 // GIR_Coverage, 412, 9069 GIR_Done, 9070 // Label 675: @21009 9071 GIM_Try, /*On fail goto*//*Label 676*/ 21053, // Rule ID 496 // 9072 GIM_CheckFeatures, GIFBS_HasP8Altivec, 9073 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vpksdss, 9074 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 9075 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 9076 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 9077 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 9078 // (intrinsic_w_chain:{ *:[v4i32] } 7346:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VPKSDSS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 9079 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VPKSDSS, 9080 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 9081 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 9082 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 9083 GIR_EraseFromParent, /*InsnID*/0, 9084 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9085 // GIR_Coverage, 496, 9086 GIR_Done, 9087 // Label 676: @21053 9088 GIM_Try, /*On fail goto*//*Label 677*/ 21097, // Rule ID 497 // 9089 GIM_CheckFeatures, GIFBS_HasP8Altivec, 9090 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vpksdus, 9091 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 9092 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 9093 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 9094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 9095 // (intrinsic_w_chain:{ *:[v4i32] } 7347:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VPKSDUS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 9096 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VPKSDUS, 9097 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 9098 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 9099 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 9100 GIR_EraseFromParent, /*InsnID*/0, 9101 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9102 // GIR_Coverage, 497, 9103 GIR_Done, 9104 // Label 677: @21097 9105 GIM_Try, /*On fail goto*//*Label 678*/ 21141, // Rule ID 498 // 9106 GIM_CheckFeatures, GIFBS_HasP8Altivec, 9107 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vpkudus, 9108 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 9109 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 9110 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 9111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 9112 // (intrinsic_w_chain:{ *:[v4i32] } 7352:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VPKUDUS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 9113 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VPKUDUS, 9114 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 9115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 9116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 9117 GIR_EraseFromParent, /*InsnID*/0, 9118 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9119 // GIR_Coverage, 498, 9120 GIR_Done, 9121 // Label 678: @21141 9122 GIM_Reject, 9123 // Label 656: @21142 9124 GIM_Try, /*On fail goto*//*Label 679*/ 21405, 9125 GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, 9126 GIM_Try, /*On fail goto*//*Label 680*/ 21196, // Rule ID 754 // 9127 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_addex, 9128 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 9129 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 9130 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 9131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 9132 // MIs[0] CY 9133 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 9134 // (intrinsic_w_chain:{ *:[i64] } 7115:{ *:[iPTR] }, i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB, (timm:{ *:[i32] }):$CY) => (ADDEX8:{ *:[i64] } i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB, (timm:{ *:[i32] }):$CY) 9135 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::ADDEX8, 9136 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rT 9137 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rA 9138 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rB 9139 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CY 9140 GIR_EraseFromParent, /*InsnID*/0, 9141 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9142 // GIR_Coverage, 754, 9143 GIR_Done, 9144 // Label 680: @21196 9145 GIM_Try, /*On fail goto*//*Label 681*/ 21248, // Rule ID 290 // 9146 GIM_CheckFeatures, GIFBS_HasAltivec, 9147 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmhaddshs, 9148 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 9149 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 9150 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 9151 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, 9152 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 9153 // (intrinsic_w_chain:{ *:[v8i16] } 7301:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB, v8i16:{ *:[v8i16] }:$vC) => (VMHADDSHS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB, v8i16:{ *:[v8i16] }:$vC) 9154 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMHADDSHS, 9155 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 9156 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 9157 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 9158 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vC 9159 GIR_EraseFromParent, /*InsnID*/0, 9160 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9161 // GIR_Coverage, 290, 9162 GIR_Done, 9163 // Label 681: @21248 9164 GIM_Try, /*On fail goto*//*Label 682*/ 21300, // Rule ID 291 // 9165 GIM_CheckFeatures, GIFBS_HasAltivec, 9166 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmhraddshs, 9167 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 9168 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 9169 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 9170 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, 9171 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 9172 // (intrinsic_w_chain:{ *:[v8i16] } 7302:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB, v8i16:{ *:[v8i16] }:$vC) => (VMHRADDSHS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB, v8i16:{ *:[v8i16] }:$vC) 9173 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMHRADDSHS, 9174 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 9175 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 9176 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 9177 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vC 9178 GIR_EraseFromParent, /*InsnID*/0, 9179 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9180 // GIR_Coverage, 291, 9181 GIR_Done, 9182 // Label 682: @21300 9183 GIM_Try, /*On fail goto*//*Label 683*/ 21352, // Rule ID 349 // 9184 GIM_CheckFeatures, GIFBS_HasAltivec, 9185 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmsumshs, 9186 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 9187 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 9188 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 9189 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 9190 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 9191 // (intrinsic_w_chain:{ *:[v4i32] } 7316:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB, v4i32:{ *:[v4i32] }:$vC) => (VMSUMSHS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB, v4i32:{ *:[v4i32] }:$vC) 9192 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMSUMSHS, 9193 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 9194 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 9195 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 9196 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vC 9197 GIR_EraseFromParent, /*InsnID*/0, 9198 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9199 // GIR_Coverage, 349, 9200 GIR_Done, 9201 // Label 683: @21352 9202 GIM_Try, /*On fail goto*//*Label 684*/ 21404, // Rule ID 350 // 9203 GIM_CheckFeatures, GIFBS_HasAltivec, 9204 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ppc_altivec_vmsumuhs, 9205 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 9206 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 9207 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 9208 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 9209 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 9210 // (intrinsic_w_chain:{ *:[v4i32] } 7320:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB, v4i32:{ *:[v4i32] }:$vC) => (VMSUMUHS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB, v4i32:{ *:[v4i32] }:$vC) 9211 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VMSUMUHS, 9212 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 9213 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 9214 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vB 9215 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vC 9216 GIR_EraseFromParent, /*InsnID*/0, 9217 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9218 // GIR_Coverage, 350, 9219 GIR_Done, 9220 // Label 684: @21404 9221 GIM_Reject, 9222 // Label 679: @21405 9223 GIM_Reject, 9224 // Label 18: @21406 9225 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 687*/ 24478, 9226 /*GILLT_s32*//*Label 685*/ 21414, 9227 /*GILLT_s64*//*Label 686*/ 22946, 9228 // Label 685: @21414 9229 GIM_Try, /*On fail goto*//*Label 688*/ 22945, 9230 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 9231 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 9232 GIM_Try, /*On fail goto*//*Label 689*/ 21546, // Rule ID 3965 // 9233 GIM_CheckFeatures, GIFBS_HasFPU, 9234 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 9235 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 9236 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 9237 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 9238 // MIs[1] Operand 1 9239 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 9240 GIM_CheckIsSafeToFold, /*InsnID*/1, 9241 // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 9242 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 9243 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 9244 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 9245 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9246 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 9247 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 9248 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9249 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 9250 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 9251 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 9252 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 9253 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 9254 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 9255 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 9256 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 9257 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 9258 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 9259 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 9260 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9261 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_lt, 9262 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 9263 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 9264 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 9265 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9266 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9267 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 9268 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 9269 GIR_EraseFromParent, /*InsnID*/0, 9270 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9271 // GIR_Coverage, 3965, 9272 GIR_Done, 9273 // Label 689: @21546 9274 GIM_Try, /*On fail goto*//*Label 690*/ 21668, // Rule ID 3997 // 9275 GIM_CheckFeatures, GIFBS_HasFPU, 9276 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 9277 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 9278 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 9279 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 9280 // MIs[1] Operand 1 9281 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 9282 GIM_CheckIsSafeToFold, /*InsnID*/1, 9283 // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 9284 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 9285 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 9286 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 9287 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9288 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 9289 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 9290 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9291 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 9292 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 9293 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 9294 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 9295 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 9296 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 9297 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 9298 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 9299 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 9300 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 9301 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 9302 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9303 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_gt, 9304 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 9305 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 9306 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 9307 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9308 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9309 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 9310 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 9311 GIR_EraseFromParent, /*InsnID*/0, 9312 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9313 // GIR_Coverage, 3997, 9314 GIR_Done, 9315 // Label 690: @21668 9316 GIM_Try, /*On fail goto*//*Label 691*/ 21790, // Rule ID 4029 // 9317 GIM_CheckFeatures, GIFBS_HasFPU, 9318 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 9319 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 9320 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 9321 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 9322 // MIs[1] Operand 1 9323 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 9324 GIM_CheckIsSafeToFold, /*InsnID*/1, 9325 // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 9326 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 9327 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 9328 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 9329 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9330 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 9331 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 9332 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9333 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 9334 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 9335 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 9336 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 9337 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 9338 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 9339 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 9340 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 9341 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 9342 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 9343 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 9344 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9345 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_eq, 9346 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 9347 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 9348 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 9349 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9350 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9351 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 9352 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 9353 GIR_EraseFromParent, /*InsnID*/0, 9354 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9355 // GIR_Coverage, 4029, 9356 GIR_Done, 9357 // Label 691: @21790 9358 GIM_Try, /*On fail goto*//*Label 692*/ 21912, // Rule ID 4061 // 9359 GIM_CheckFeatures, GIFBS_HasFPU, 9360 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 9361 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 9362 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 9363 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 9364 // MIs[1] Operand 1 9365 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 9366 GIM_CheckIsSafeToFold, /*InsnID*/1, 9367 // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_un:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 9368 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 9369 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 9370 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 9371 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9372 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 9373 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 9374 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9375 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 9376 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 9377 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 9378 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 9379 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 9380 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 9381 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 9382 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 9383 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 9384 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 9385 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 9386 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9387 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_un, 9388 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 9389 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 9390 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 9391 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9392 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9393 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 9394 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 9395 GIR_EraseFromParent, /*InsnID*/0, 9396 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9397 // GIR_Coverage, 4061, 9398 GIR_Done, 9399 // Label 692: @21912 9400 GIM_Try, /*On fail goto*//*Label 693*/ 22034, // Rule ID 4077 // 9401 GIM_CheckFeatures, GIFBS_HasFPU, 9402 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 9403 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 9404 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 9405 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 9406 // MIs[1] Operand 1 9407 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 9408 GIM_CheckIsSafeToFold, /*InsnID*/1, 9409 // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 9410 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 9411 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 9412 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 9413 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9414 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 9415 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 9416 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9417 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 9418 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 9419 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 9420 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 9421 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 9422 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 9423 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 9424 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 9425 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 9426 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 9427 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 9428 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9429 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_lt, 9430 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 9431 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 9432 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 9433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9434 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9435 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 9436 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 9437 GIR_EraseFromParent, /*InsnID*/0, 9438 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9439 // GIR_Coverage, 4077, 9440 GIR_Done, 9441 // Label 693: @22034 9442 GIM_Try, /*On fail goto*//*Label 694*/ 22156, // Rule ID 4109 // 9443 GIM_CheckFeatures, GIFBS_HasFPU, 9444 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 9445 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 9446 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 9447 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 9448 // MIs[1] Operand 1 9449 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 9450 GIM_CheckIsSafeToFold, /*InsnID*/1, 9451 // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 9452 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 9453 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 9454 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 9455 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9456 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 9457 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 9458 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9459 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 9460 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 9461 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 9462 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 9463 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 9464 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 9465 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 9466 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 9467 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 9468 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 9469 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 9470 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9471 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_gt, 9472 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 9473 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 9474 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 9475 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9476 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9477 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 9478 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 9479 GIR_EraseFromParent, /*InsnID*/0, 9480 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9481 // GIR_Coverage, 4109, 9482 GIR_Done, 9483 // Label 694: @22156 9484 GIM_Try, /*On fail goto*//*Label 695*/ 22278, // Rule ID 4141 // 9485 GIM_CheckFeatures, GIFBS_HasFPU, 9486 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 9487 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 9488 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 9489 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 9490 // MIs[1] Operand 1 9491 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 9492 GIM_CheckIsSafeToFold, /*InsnID*/1, 9493 // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 9494 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 9495 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 9496 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 9497 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9498 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 9499 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 9500 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9501 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 9502 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 9503 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 9504 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 9505 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 9506 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 9507 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 9508 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 9509 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 9510 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 9511 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 9512 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9513 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_eq, 9514 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 9515 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 9516 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 9517 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9518 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9519 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 9520 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 9521 GIR_EraseFromParent, /*InsnID*/0, 9522 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9523 // GIR_Coverage, 4141, 9524 GIR_Done, 9525 // Label 695: @22278 9526 GIM_Try, /*On fail goto*//*Label 696*/ 22400, // Rule ID 4173 // 9527 GIM_CheckFeatures, GIFBS_HasFPU, 9528 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 9529 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 9530 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 9531 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 9532 // MIs[1] Operand 1 9533 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 9534 GIM_CheckIsSafeToFold, /*InsnID*/1, 9535 // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_un:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 9536 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 9537 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 9538 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 9539 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9540 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 9541 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 9542 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9543 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 9544 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 9545 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 9546 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 9547 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 9548 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 9549 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 9550 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 9551 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 9552 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 9553 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 9554 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9555 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_un, 9556 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 9557 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 9558 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 9559 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9560 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9561 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 9562 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 9563 GIR_EraseFromParent, /*InsnID*/0, 9564 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9565 // GIR_Coverage, 4173, 9566 GIR_Done, 9567 // Label 696: @22400 9568 GIM_Try, /*On fail goto*//*Label 697*/ 22522, // Rule ID 4203 // 9569 GIM_CheckFeatures, GIFBS_HasFPU, 9570 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 9571 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 9572 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 9573 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 9574 // MIs[1] Operand 1 9575 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 9576 GIM_CheckIsSafeToFold, /*InsnID*/1, 9577 // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 9578 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 9579 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 9580 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 9581 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9582 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 9583 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 9584 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9585 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 9586 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 9587 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 9588 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 9589 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 9590 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 9591 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 9592 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 9593 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 9594 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 9595 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 9596 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9597 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_lt, 9598 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 9599 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 9600 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 9601 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9602 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9603 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 9604 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 9605 GIR_EraseFromParent, /*InsnID*/0, 9606 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9607 // GIR_Coverage, 4203, 9608 GIR_Done, 9609 // Label 697: @22522 9610 GIM_Try, /*On fail goto*//*Label 698*/ 22644, // Rule ID 4235 // 9611 GIM_CheckFeatures, GIFBS_HasFPU, 9612 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 9613 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 9614 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 9615 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 9616 // MIs[1] Operand 1 9617 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 9618 GIM_CheckIsSafeToFold, /*InsnID*/1, 9619 // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 9620 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 9621 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 9622 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 9623 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9624 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 9625 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 9626 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9627 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 9628 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 9629 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 9630 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 9631 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 9632 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 9633 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 9634 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 9635 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 9636 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 9637 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 9638 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9639 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_gt, 9640 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 9641 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 9642 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 9643 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9644 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9645 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 9646 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 9647 GIR_EraseFromParent, /*InsnID*/0, 9648 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9649 // GIR_Coverage, 4235, 9650 GIR_Done, 9651 // Label 698: @22644 9652 GIM_Try, /*On fail goto*//*Label 699*/ 22766, // Rule ID 4267 // 9653 GIM_CheckFeatures, GIFBS_HasFPU, 9654 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 9655 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 9656 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 9657 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 9658 // MIs[1] Operand 1 9659 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 9660 GIM_CheckIsSafeToFold, /*InsnID*/1, 9661 // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 9662 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 9663 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 9664 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 9665 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9666 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 9667 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 9668 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9669 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 9670 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 9671 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 9672 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 9673 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 9674 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 9675 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 9676 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 9677 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 9678 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 9679 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 9680 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9681 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_eq, 9682 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 9683 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 9684 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 9685 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9686 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9687 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 9688 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 9689 GIR_EraseFromParent, /*InsnID*/0, 9690 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9691 // GIR_Coverage, 4267, 9692 GIR_Done, 9693 // Label 699: @22766 9694 GIM_Try, /*On fail goto*//*Label 700*/ 22888, // Rule ID 4299 // 9695 GIM_CheckFeatures, GIFBS_HasFPU, 9696 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 9697 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 9698 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 9699 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 9700 // MIs[1] Operand 1 9701 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 9702 GIM_CheckIsSafeToFold, /*InsnID*/1, 9703 // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_un:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 9704 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 9705 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 9706 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 9707 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9708 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 9709 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 9710 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9711 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 9712 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 9713 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 9714 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 9715 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 9716 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 9717 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 9718 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 9719 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 9720 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 9721 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 9722 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9723 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_un, 9724 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 9725 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 9726 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 9727 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9728 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9729 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 9730 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 9731 GIR_EraseFromParent, /*InsnID*/0, 9732 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9733 // GIR_Coverage, 4299, 9734 GIR_Done, 9735 // Label 700: @22888 9736 GIM_Try, /*On fail goto*//*Label 701*/ 22944, // Rule ID 3614 // 9737 // (anyext:{ *:[i32] } i1:{ *:[i1] }:$in) => (SELECT_I4:{ *:[i32] } crbitrc:{ *:[i1] }:$in, (LI:{ *:[i32] } 1:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] })) 9738 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 9739 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 9740 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::LI, 9741 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9742 GIR_AddImm, /*InsnID*/2, /*Imm*/0, 9743 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9744 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::LI, 9745 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9746 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 9747 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 9748 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 9749 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9750 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in 9751 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9752 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, 9753 GIR_EraseFromParent, /*InsnID*/0, 9754 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9755 // GIR_Coverage, 3614, 9756 GIR_Done, 9757 // Label 701: @22944 9758 GIM_Reject, 9759 // Label 688: @22945 9760 GIM_Reject, 9761 // Label 686: @22946 9762 GIM_Try, /*On fail goto*//*Label 702*/ 24477, 9763 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 9764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 9765 GIM_Try, /*On fail goto*//*Label 703*/ 23078, // Rule ID 3967 // 9766 GIM_CheckFeatures, GIFBS_HasFPU, 9767 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 9768 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 9769 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 9770 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 9771 // MIs[1] Operand 1 9772 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 9773 GIM_CheckIsSafeToFold, /*InsnID*/1, 9774 // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 9775 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 9776 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 9777 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 9778 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9779 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 9780 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 9781 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9782 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 9783 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 9784 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 9785 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 9786 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 9787 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 9788 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 9789 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 9790 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 9791 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 9792 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 9793 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9794 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_lt, 9795 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 9796 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 9797 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 9798 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9799 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9800 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 9801 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 9802 GIR_EraseFromParent, /*InsnID*/0, 9803 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9804 // GIR_Coverage, 3967, 9805 GIR_Done, 9806 // Label 703: @23078 9807 GIM_Try, /*On fail goto*//*Label 704*/ 23200, // Rule ID 3999 // 9808 GIM_CheckFeatures, GIFBS_HasFPU, 9809 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 9810 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 9811 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 9812 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 9813 // MIs[1] Operand 1 9814 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 9815 GIM_CheckIsSafeToFold, /*InsnID*/1, 9816 // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 9817 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 9818 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 9819 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 9820 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9821 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 9822 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 9823 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9824 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 9825 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 9826 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 9827 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 9828 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 9829 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 9830 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 9831 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 9832 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 9833 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 9834 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 9835 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9836 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_gt, 9837 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 9838 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 9839 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 9840 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9841 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9842 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 9843 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 9844 GIR_EraseFromParent, /*InsnID*/0, 9845 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9846 // GIR_Coverage, 3999, 9847 GIR_Done, 9848 // Label 704: @23200 9849 GIM_Try, /*On fail goto*//*Label 705*/ 23322, // Rule ID 4031 // 9850 GIM_CheckFeatures, GIFBS_HasFPU, 9851 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 9852 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 9853 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 9854 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 9855 // MIs[1] Operand 1 9856 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 9857 GIM_CheckIsSafeToFold, /*InsnID*/1, 9858 // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 9859 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 9860 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 9861 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 9862 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9863 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 9864 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 9865 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9866 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 9867 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 9868 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 9869 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 9870 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 9871 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 9872 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 9873 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 9874 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 9875 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 9876 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 9877 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9878 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_eq, 9879 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 9880 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 9881 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 9882 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9883 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9884 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 9885 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 9886 GIR_EraseFromParent, /*InsnID*/0, 9887 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9888 // GIR_Coverage, 4031, 9889 GIR_Done, 9890 // Label 705: @23322 9891 GIM_Try, /*On fail goto*//*Label 706*/ 23444, // Rule ID 4063 // 9892 GIM_CheckFeatures, GIFBS_HasFPU, 9893 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 9894 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 9895 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 9896 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 9897 // MIs[1] Operand 1 9898 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 9899 GIM_CheckIsSafeToFold, /*InsnID*/1, 9900 // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_un:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 9901 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 9902 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 9903 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 9904 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9905 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 9906 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 9907 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9908 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 9909 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 9910 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 9911 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 9912 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 9913 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 9914 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 9915 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 9916 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 9917 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 9918 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 9919 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9920 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_un, 9921 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 9922 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 9923 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 9924 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9925 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9926 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 9927 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 9928 GIR_EraseFromParent, /*InsnID*/0, 9929 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9930 // GIR_Coverage, 4063, 9931 GIR_Done, 9932 // Label 706: @23444 9933 GIM_Try, /*On fail goto*//*Label 707*/ 23566, // Rule ID 4079 // 9934 GIM_CheckFeatures, GIFBS_HasFPU, 9935 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 9936 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 9937 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 9938 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 9939 // MIs[1] Operand 1 9940 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 9941 GIM_CheckIsSafeToFold, /*InsnID*/1, 9942 // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 9943 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 9944 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 9945 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 9946 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9947 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 9948 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 9949 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9950 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 9951 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 9952 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 9953 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 9954 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 9955 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 9956 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 9957 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 9958 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 9959 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 9960 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 9961 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9962 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_lt, 9963 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 9964 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 9965 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 9966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9967 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9968 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 9969 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 9970 GIR_EraseFromParent, /*InsnID*/0, 9971 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9972 // GIR_Coverage, 4079, 9973 GIR_Done, 9974 // Label 707: @23566 9975 GIM_Try, /*On fail goto*//*Label 708*/ 23688, // Rule ID 4111 // 9976 GIM_CheckFeatures, GIFBS_HasFPU, 9977 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 9978 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 9979 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 9980 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 9981 // MIs[1] Operand 1 9982 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 9983 GIM_CheckIsSafeToFold, /*InsnID*/1, 9984 // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 9985 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 9986 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 9987 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 9988 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9989 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 9990 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 9991 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9992 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 9993 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 9994 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 9995 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 9996 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 9997 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 9998 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 9999 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 10000 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 10001 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 10002 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10003 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10004 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_gt, 10005 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 10006 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 10007 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 10008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10009 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10010 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 10011 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 10012 GIR_EraseFromParent, /*InsnID*/0, 10013 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10014 // GIR_Coverage, 4111, 10015 GIR_Done, 10016 // Label 708: @23688 10017 GIM_Try, /*On fail goto*//*Label 709*/ 23810, // Rule ID 4143 // 10018 GIM_CheckFeatures, GIFBS_HasFPU, 10019 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10020 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 10021 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 10022 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 10023 // MIs[1] Operand 1 10024 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 10025 GIM_CheckIsSafeToFold, /*InsnID*/1, 10026 // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 10027 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 10028 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 10029 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 10030 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 10031 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 10032 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 10033 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 10034 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 10035 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 10036 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 10037 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 10038 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 10039 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 10040 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 10041 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 10042 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 10043 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 10044 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10045 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10046 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_eq, 10047 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 10048 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 10049 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 10050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10051 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10052 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 10053 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 10054 GIR_EraseFromParent, /*InsnID*/0, 10055 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10056 // GIR_Coverage, 4143, 10057 GIR_Done, 10058 // Label 709: @23810 10059 GIM_Try, /*On fail goto*//*Label 710*/ 23932, // Rule ID 4175 // 10060 GIM_CheckFeatures, GIFBS_HasFPU, 10061 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10062 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 10063 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 10064 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 10065 // MIs[1] Operand 1 10066 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 10067 GIM_CheckIsSafeToFold, /*InsnID*/1, 10068 // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_un:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 10069 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 10070 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 10071 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 10072 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 10073 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 10074 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 10075 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 10076 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 10077 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 10078 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 10079 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 10080 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 10081 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 10082 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 10083 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 10084 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 10085 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 10086 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10087 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10088 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_un, 10089 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 10090 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 10091 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 10092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10093 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10094 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 10095 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 10096 GIR_EraseFromParent, /*InsnID*/0, 10097 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10098 // GIR_Coverage, 4175, 10099 GIR_Done, 10100 // Label 710: @23932 10101 GIM_Try, /*On fail goto*//*Label 711*/ 24054, // Rule ID 4205 // 10102 GIM_CheckFeatures, GIFBS_HasFPU, 10103 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10104 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 10105 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 10106 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 10107 // MIs[1] Operand 1 10108 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 10109 GIM_CheckIsSafeToFold, /*InsnID*/1, 10110 // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 10111 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 10112 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 10113 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 10114 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 10115 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 10116 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 10117 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 10118 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 10119 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 10120 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 10121 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 10122 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 10123 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 10124 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 10125 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 10126 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 10127 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 10128 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10129 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10130 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_lt, 10131 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 10132 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 10133 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 10134 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10135 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10136 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 10137 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 10138 GIR_EraseFromParent, /*InsnID*/0, 10139 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10140 // GIR_Coverage, 4205, 10141 GIR_Done, 10142 // Label 711: @24054 10143 GIM_Try, /*On fail goto*//*Label 712*/ 24176, // Rule ID 4237 // 10144 GIM_CheckFeatures, GIFBS_HasFPU, 10145 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10146 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 10147 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 10148 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 10149 // MIs[1] Operand 1 10150 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 10151 GIM_CheckIsSafeToFold, /*InsnID*/1, 10152 // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 10153 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 10154 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 10155 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 10156 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 10157 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 10158 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 10159 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 10160 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 10161 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 10162 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 10163 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 10164 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 10165 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 10166 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 10167 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 10168 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 10169 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 10170 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10171 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10172 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_gt, 10173 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 10174 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 10175 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 10176 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10177 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10178 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 10179 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 10180 GIR_EraseFromParent, /*InsnID*/0, 10181 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10182 // GIR_Coverage, 4237, 10183 GIR_Done, 10184 // Label 712: @24176 10185 GIM_Try, /*On fail goto*//*Label 713*/ 24298, // Rule ID 4269 // 10186 GIM_CheckFeatures, GIFBS_HasFPU, 10187 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10188 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 10189 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 10190 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 10191 // MIs[1] Operand 1 10192 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 10193 GIM_CheckIsSafeToFold, /*InsnID*/1, 10194 // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 10195 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 10196 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 10197 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 10198 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 10199 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 10200 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 10201 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 10202 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 10203 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 10204 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 10205 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 10206 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 10207 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 10208 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 10209 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 10210 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 10211 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 10212 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10213 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10214 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_eq, 10215 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 10216 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 10217 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 10218 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10219 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10220 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 10221 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 10222 GIR_EraseFromParent, /*InsnID*/0, 10223 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10224 // GIR_Coverage, 4269, 10225 GIR_Done, 10226 // Label 713: @24298 10227 GIM_Try, /*On fail goto*//*Label 714*/ 24420, // Rule ID 4301 // 10228 GIM_CheckFeatures, GIFBS_HasFPU, 10229 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10230 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 10231 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 10232 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 10233 // MIs[1] Operand 1 10234 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 10235 GIM_CheckIsSafeToFold, /*InsnID*/1, 10236 // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_un:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 10237 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 10238 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 10239 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 10240 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 10241 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 10242 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 10243 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 10244 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 10245 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 10246 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 10247 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 10248 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 10249 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 10250 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 10251 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 10252 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 10253 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 10254 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10255 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10256 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_un, 10257 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 10258 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 10259 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 10260 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10261 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10262 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 10263 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 10264 GIR_EraseFromParent, /*InsnID*/0, 10265 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10266 // GIR_Coverage, 4301, 10267 GIR_Done, 10268 // Label 714: @24420 10269 GIM_Try, /*On fail goto*//*Label 715*/ 24476, // Rule ID 3615 // 10270 // (anyext:{ *:[i64] } i1:{ *:[i1] }:$in) => (SELECT_I8:{ *:[i64] } crbitrc:{ *:[i1] }:$in, (LI8:{ *:[i64] } 1:{ *:[i64] }), (LI8:{ *:[i64] } 0:{ *:[i64] })) 10271 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 10272 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 10273 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::LI8, 10274 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 10275 GIR_AddImm, /*InsnID*/2, /*Imm*/0, 10276 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 10277 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::LI8, 10278 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10279 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 10280 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10281 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 10282 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10283 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in 10284 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10285 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, 10286 GIR_EraseFromParent, /*InsnID*/0, 10287 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10288 // GIR_Coverage, 3615, 10289 GIR_Done, 10290 // Label 715: @24476 10291 GIM_Reject, 10292 // Label 702: @24477 10293 GIM_Reject, 10294 // Label 687: @24478 10295 GIM_Reject, 10296 // Label 19: @24479 10297 GIM_Try, /*On fail goto*//*Label 716*/ 24618, 10298 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1, 10299 GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/1, 3, /*)*//*default:*//*Label 719*/ 24581, 10300 /*GILLT_s32*//*Label 717*/ 24493, 10301 /*GILLT_s64*//*Label 718*/ 24537, 10302 // Label 717: @24493 10303 GIM_Try, /*On fail goto*//*Label 720*/ 24536, // Rule ID 1147 // 10304 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 10305 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10306 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 10307 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 10308 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 10309 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 10310 GIM_CheckIsSafeToFold, /*InsnID*/1, 10311 // (trunc:{ *:[i1] } (xor:{ *:[i32] } i32:{ *:[i32] }:$in, -1:{ *:[i32] })) => (ANDI_rec_1_EQ_BIT:{ *:[i1] } i32:{ *:[i32] }:$in) 10312 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::ANDI_rec_1_EQ_BIT, 10313 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10314 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // in 10315 GIR_EraseFromParent, /*InsnID*/0, 10316 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10317 // GIR_Coverage, 1147, 10318 GIR_Done, 10319 // Label 720: @24536 10320 GIM_Reject, 10321 // Label 718: @24537 10322 GIM_Try, /*On fail goto*//*Label 721*/ 24580, // Rule ID 1149 // 10323 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 10324 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10325 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 10326 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 10327 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 10328 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 10329 GIM_CheckIsSafeToFold, /*InsnID*/1, 10330 // (trunc:{ *:[i1] } (xor:{ *:[i64] } i64:{ *:[i64] }:$in, -1:{ *:[i64] })) => (ANDI_rec_1_EQ_BIT8:{ *:[i1] } i64:{ *:[i64] }:$in) 10331 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::ANDI_rec_1_EQ_BIT8, 10332 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10333 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // in 10334 GIR_EraseFromParent, /*InsnID*/0, 10335 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10336 // GIR_Coverage, 1149, 10337 GIR_Done, 10338 // Label 721: @24580 10339 GIM_Reject, 10340 // Label 719: @24581 10341 GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/1, 3, /*)*//*default:*//*Label 724*/ 24617, 10342 /*GILLT_s32*//*Label 722*/ 24589, 10343 /*GILLT_s64*//*Label 723*/ 24603, 10344 // Label 722: @24589 10345 GIM_Try, /*On fail goto*//*Label 725*/ 24602, // Rule ID 1148 // 10346 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 10347 // (trunc:{ *:[i1] } i32:{ *:[i32] }:$in) => (ANDI_rec_1_GT_BIT:{ *:[i1] } i32:{ *:[i32] }:$in) 10348 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::ANDI_rec_1_GT_BIT, 10349 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10350 // GIR_Coverage, 1148, 10351 GIR_Done, 10352 // Label 725: @24602 10353 GIM_Reject, 10354 // Label 723: @24603 10355 GIM_Try, /*On fail goto*//*Label 726*/ 24616, // Rule ID 1150 // 10356 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 10357 // (trunc:{ *:[i1] } i64:{ *:[i64] }:$in) => (ANDI_rec_1_GT_BIT8:{ *:[i1] } i64:{ *:[i64] }:$in) 10358 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::ANDI_rec_1_GT_BIT8, 10359 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10360 // GIR_Coverage, 1150, 10361 GIR_Done, 10362 // Label 726: @24616 10363 GIM_Reject, 10364 // Label 724: @24617 10365 GIM_Reject, 10366 // Label 716: @24618 10367 GIM_Reject, 10368 // Label 20: @24619 10369 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 730*/ 24740, 10370 /*GILLT_s1*//*Label 727*/ 24628, 10371 /*GILLT_s32*//*Label 728*/ 24690, 10372 /*GILLT_s64*//*Label 729*/ 24715, 10373 // Label 727: @24628 10374 GIM_Try, /*On fail goto*//*Label 731*/ 24689, 10375 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 10376 GIM_Try, /*On fail goto*//*Label 732*/ 24652, // Rule ID 181 // 10377 // MIs[0] Operand 1 10378 GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, 1, 10379 // 1:{ *:[i1] } => (CRSET:{ *:[i1] }) 10380 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CRSET, 10381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10382 GIR_EraseFromParent, /*InsnID*/0, 10383 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10384 // GIR_Coverage, 181, 10385 GIR_Done, 10386 // Label 732: @24652 10387 GIM_Try, /*On fail goto*//*Label 733*/ 24670, // Rule ID 182 // 10388 // MIs[0] Operand 1 10389 GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, 0, 10390 // 0:{ *:[i1] } => (CRUNSET:{ *:[i1] }) 10391 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CRUNSET, 10392 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10393 GIR_EraseFromParent, /*InsnID*/0, 10394 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10395 // GIR_Coverage, 182, 10396 GIR_Done, 10397 // Label 733: @24670 10398 GIM_Try, /*On fail goto*//*Label 734*/ 24688, // Rule ID 3609 // 10399 // MIs[0] Operand 1 10400 GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, -1, 10401 // -1:{ *:[i1] } => (CRSET:{ *:[i1] }) 10402 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CRSET, 10403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10404 GIR_EraseFromParent, /*InsnID*/0, 10405 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10406 // GIR_Coverage, 3609, 10407 GIR_Done, 10408 // Label 734: @24688 10409 GIM_Reject, 10410 // Label 731: @24689 10411 GIM_Reject, 10412 // Label 728: @24690 10413 GIM_Try, /*On fail goto*//*Label 735*/ 24714, // Rule ID 110 // 10414 GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_imm32SExt16, 10415 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 10416 // MIs[0] Operand 1 10417 // No operand predicates 10418 // (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm => (LI:{ *:[i32] } (imm:{ *:[i32] }):$imm) 10419 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::LI, 10420 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rD 10421 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm 10422 GIR_EraseFromParent, /*InsnID*/0, 10423 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10424 // GIR_Coverage, 110, 10425 GIR_Done, 10426 // Label 735: @24714 10427 GIM_Reject, 10428 // Label 729: @24715 10429 GIM_Try, /*On fail goto*//*Label 736*/ 24739, // Rule ID 635 // 10430 GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_imm64SExt16, 10431 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 10432 // MIs[0] Operand 1 10433 // No operand predicates 10434 // (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm => (LI8:{ *:[i64] } (imm:{ *:[i64] }):$imm) 10435 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::LI8, 10436 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rD 10437 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm 10438 GIR_EraseFromParent, /*InsnID*/0, 10439 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10440 // GIR_Coverage, 635, 10441 GIR_Done, 10442 // Label 736: @24739 10443 GIM_Reject, 10444 // Label 730: @24740 10445 GIM_Reject, 10446 // Label 21: @24741 10447 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 739*/ 27803, 10448 /*GILLT_s32*//*Label 737*/ 24749, 10449 /*GILLT_s64*//*Label 738*/ 26225, 10450 // Label 737: @24749 10451 GIM_Try, /*On fail goto*//*Label 740*/ 26224, 10452 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 10453 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 10454 GIM_Try, /*On fail goto*//*Label 741*/ 24881, // Rule ID 3959 // 10455 GIM_CheckFeatures, GIFBS_HasFPU, 10456 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10457 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 10458 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 10459 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 10460 // MIs[1] Operand 1 10461 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 10462 GIM_CheckIsSafeToFold, /*InsnID*/1, 10463 // (sext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] })) 10464 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 10465 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 10466 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 10467 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 10468 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 10469 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 10470 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 10471 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 10472 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 10473 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 10474 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 10475 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 10476 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 10477 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 10478 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 10479 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 10480 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 10481 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10482 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10483 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_lt, 10484 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 10485 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 10486 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 10487 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10488 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10489 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 10490 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 10491 GIR_EraseFromParent, /*InsnID*/0, 10492 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10493 // GIR_Coverage, 3959, 10494 GIR_Done, 10495 // Label 741: @24881 10496 GIM_Try, /*On fail goto*//*Label 742*/ 25003, // Rule ID 3991 // 10497 GIM_CheckFeatures, GIFBS_HasFPU, 10498 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10499 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 10500 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 10501 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 10502 // MIs[1] Operand 1 10503 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 10504 GIM_CheckIsSafeToFold, /*InsnID*/1, 10505 // (sext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] })) 10506 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 10507 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 10508 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 10509 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 10510 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 10511 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 10512 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 10513 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 10514 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 10515 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 10516 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 10517 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 10518 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 10519 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 10520 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 10521 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 10522 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 10523 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10524 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10525 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_gt, 10526 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 10527 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 10528 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 10529 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10530 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10531 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 10532 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 10533 GIR_EraseFromParent, /*InsnID*/0, 10534 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10535 // GIR_Coverage, 3991, 10536 GIR_Done, 10537 // Label 742: @25003 10538 GIM_Try, /*On fail goto*//*Label 743*/ 25125, // Rule ID 4023 // 10539 GIM_CheckFeatures, GIFBS_HasFPU, 10540 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10541 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 10542 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 10543 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 10544 // MIs[1] Operand 1 10545 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 10546 GIM_CheckIsSafeToFold, /*InsnID*/1, 10547 // (sext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] })) 10548 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 10549 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 10550 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 10551 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 10552 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 10553 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 10554 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 10555 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 10556 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 10557 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 10558 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 10559 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 10560 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 10561 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 10562 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 10563 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 10564 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 10565 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10566 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10567 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_eq, 10568 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 10569 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 10570 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 10571 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10572 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10573 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 10574 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 10575 GIR_EraseFromParent, /*InsnID*/0, 10576 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10577 // GIR_Coverage, 4023, 10578 GIR_Done, 10579 // Label 743: @25125 10580 GIM_Try, /*On fail goto*//*Label 744*/ 25247, // Rule ID 4055 // 10581 GIM_CheckFeatures, GIFBS_HasFPU, 10582 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10583 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 10584 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 10585 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 10586 // MIs[1] Operand 1 10587 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 10588 GIM_CheckIsSafeToFold, /*InsnID*/1, 10589 // (sext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_un:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] })) 10590 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 10591 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 10592 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 10593 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 10594 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 10595 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 10596 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 10597 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 10598 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 10599 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 10600 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 10601 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 10602 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 10603 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 10604 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 10605 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 10606 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 10607 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10608 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10609 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_un, 10610 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 10611 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 10612 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 10613 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10614 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10615 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 10616 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 10617 GIR_EraseFromParent, /*InsnID*/0, 10618 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10619 // GIR_Coverage, 4055, 10620 GIR_Done, 10621 // Label 744: @25247 10622 GIM_Try, /*On fail goto*//*Label 745*/ 25369, // Rule ID 4071 // 10623 GIM_CheckFeatures, GIFBS_HasFPU, 10624 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10625 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 10626 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 10627 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 10628 // MIs[1] Operand 1 10629 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 10630 GIM_CheckIsSafeToFold, /*InsnID*/1, 10631 // (sext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] })) 10632 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 10633 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 10634 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 10635 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 10636 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 10637 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 10638 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 10639 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 10640 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 10641 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 10642 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 10643 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 10644 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 10645 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 10646 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 10647 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 10648 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 10649 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10650 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10651 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_lt, 10652 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 10653 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 10654 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 10655 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10656 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10657 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 10658 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 10659 GIR_EraseFromParent, /*InsnID*/0, 10660 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10661 // GIR_Coverage, 4071, 10662 GIR_Done, 10663 // Label 745: @25369 10664 GIM_Try, /*On fail goto*//*Label 746*/ 25491, // Rule ID 4103 // 10665 GIM_CheckFeatures, GIFBS_HasFPU, 10666 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10667 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 10668 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 10669 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 10670 // MIs[1] Operand 1 10671 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 10672 GIM_CheckIsSafeToFold, /*InsnID*/1, 10673 // (sext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] })) 10674 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 10675 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 10676 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 10677 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 10678 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 10679 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 10680 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 10681 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 10682 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 10683 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 10684 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 10685 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 10686 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 10687 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 10688 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 10689 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 10690 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 10691 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10692 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10693 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_gt, 10694 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 10695 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 10696 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 10697 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10698 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10699 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 10700 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 10701 GIR_EraseFromParent, /*InsnID*/0, 10702 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10703 // GIR_Coverage, 4103, 10704 GIR_Done, 10705 // Label 746: @25491 10706 GIM_Try, /*On fail goto*//*Label 747*/ 25613, // Rule ID 4135 // 10707 GIM_CheckFeatures, GIFBS_HasFPU, 10708 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10709 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 10710 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 10711 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 10712 // MIs[1] Operand 1 10713 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 10714 GIM_CheckIsSafeToFold, /*InsnID*/1, 10715 // (sext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] })) 10716 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 10717 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 10718 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 10719 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 10720 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 10721 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 10722 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 10723 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 10724 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 10725 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 10726 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 10727 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 10728 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 10729 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 10730 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 10731 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 10732 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 10733 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10734 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10735 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_eq, 10736 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 10737 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 10738 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 10739 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10740 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10741 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 10742 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 10743 GIR_EraseFromParent, /*InsnID*/0, 10744 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10745 // GIR_Coverage, 4135, 10746 GIR_Done, 10747 // Label 747: @25613 10748 GIM_Try, /*On fail goto*//*Label 748*/ 25735, // Rule ID 4167 // 10749 GIM_CheckFeatures, GIFBS_HasFPU, 10750 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10751 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 10752 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 10753 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 10754 // MIs[1] Operand 1 10755 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 10756 GIM_CheckIsSafeToFold, /*InsnID*/1, 10757 // (sext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_un:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] })) 10758 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 10759 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 10760 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 10761 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 10762 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 10763 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 10764 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 10765 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 10766 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 10767 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 10768 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 10769 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 10770 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 10771 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 10772 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 10773 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 10774 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 10775 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10776 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10777 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_un, 10778 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 10779 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 10780 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 10781 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10782 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10783 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 10784 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 10785 GIR_EraseFromParent, /*InsnID*/0, 10786 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10787 // GIR_Coverage, 4167, 10788 GIR_Done, 10789 // Label 748: @25735 10790 GIM_Try, /*On fail goto*//*Label 749*/ 25857, // Rule ID 4197 // 10791 GIM_CheckFeatures, GIFBS_HasFPU, 10792 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10793 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 10794 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 10795 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 10796 // MIs[1] Operand 1 10797 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 10798 GIM_CheckIsSafeToFold, /*InsnID*/1, 10799 // (sext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] })) 10800 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 10801 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 10802 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 10803 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 10804 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 10805 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 10806 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 10807 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 10808 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 10809 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 10810 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 10811 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 10812 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 10813 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 10814 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 10815 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 10816 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 10817 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10818 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10819 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_lt, 10820 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 10821 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 10822 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 10823 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10824 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10825 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 10826 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 10827 GIR_EraseFromParent, /*InsnID*/0, 10828 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10829 // GIR_Coverage, 4197, 10830 GIR_Done, 10831 // Label 749: @25857 10832 GIM_Try, /*On fail goto*//*Label 750*/ 25979, // Rule ID 4229 // 10833 GIM_CheckFeatures, GIFBS_HasFPU, 10834 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10835 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 10836 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 10837 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 10838 // MIs[1] Operand 1 10839 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 10840 GIM_CheckIsSafeToFold, /*InsnID*/1, 10841 // (sext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] })) 10842 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 10843 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 10844 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 10845 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 10846 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 10847 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 10848 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 10849 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 10850 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 10851 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 10852 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 10853 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 10854 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 10855 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 10856 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 10857 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 10858 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 10859 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10860 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10861 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_gt, 10862 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 10863 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 10864 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 10865 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10866 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10867 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 10868 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 10869 GIR_EraseFromParent, /*InsnID*/0, 10870 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10871 // GIR_Coverage, 4229, 10872 GIR_Done, 10873 // Label 750: @25979 10874 GIM_Try, /*On fail goto*//*Label 751*/ 26101, // Rule ID 4261 // 10875 GIM_CheckFeatures, GIFBS_HasFPU, 10876 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10877 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 10878 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 10879 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 10880 // MIs[1] Operand 1 10881 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 10882 GIM_CheckIsSafeToFold, /*InsnID*/1, 10883 // (sext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] })) 10884 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 10885 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 10886 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 10887 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 10888 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 10889 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 10890 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 10891 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 10892 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 10893 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 10894 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 10895 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 10896 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 10897 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 10898 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 10899 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 10900 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 10901 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10902 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10903 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_eq, 10904 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 10905 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 10906 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 10907 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10908 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10909 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 10910 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 10911 GIR_EraseFromParent, /*InsnID*/0, 10912 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10913 // GIR_Coverage, 4261, 10914 GIR_Done, 10915 // Label 751: @26101 10916 GIM_Try, /*On fail goto*//*Label 752*/ 26223, // Rule ID 4293 // 10917 GIM_CheckFeatures, GIFBS_HasFPU, 10918 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10919 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 10920 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 10921 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 10922 // MIs[1] Operand 1 10923 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 10924 GIM_CheckIsSafeToFold, /*InsnID*/1, 10925 // (sext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_un:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] })) 10926 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 10927 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 10928 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 10929 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 10930 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 10931 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 10932 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 10933 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 10934 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 10935 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 10936 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 10937 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 10938 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 10939 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 10940 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 10941 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 10942 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 10943 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10944 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10945 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_un, 10946 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 10947 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 10948 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 10949 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10950 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10951 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 10952 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 10953 GIR_EraseFromParent, /*InsnID*/0, 10954 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10955 // GIR_Coverage, 4293, 10956 GIR_Done, 10957 // Label 752: @26223 10958 GIM_Reject, 10959 // Label 740: @26224 10960 GIM_Reject, 10961 // Label 738: @26225 10962 GIM_Try, /*On fail goto*//*Label 753*/ 26355, // Rule ID 3963 // 10963 GIM_CheckFeatures, GIFBS_HasFPU, 10964 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 10965 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 10966 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10967 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 10968 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 10969 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 10970 // MIs[1] Operand 1 10971 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 10972 GIM_CheckIsSafeToFold, /*InsnID*/1, 10973 // (sext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] })) 10974 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 10975 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 10976 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 10977 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 10978 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 10979 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 10980 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 10981 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 10982 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 10983 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 10984 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 10985 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 10986 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 10987 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 10988 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 10989 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 10990 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 10991 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10992 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10993 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_lt, 10994 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 10995 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 10996 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 10997 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10998 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10999 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11000 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11001 GIR_EraseFromParent, /*InsnID*/0, 11002 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11003 // GIR_Coverage, 3963, 11004 GIR_Done, 11005 // Label 753: @26355 11006 GIM_Try, /*On fail goto*//*Label 754*/ 26485, // Rule ID 3995 // 11007 GIM_CheckFeatures, GIFBS_HasFPU, 11008 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 11009 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 11010 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11011 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11012 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 11013 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 11014 // MIs[1] Operand 1 11015 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 11016 GIM_CheckIsSafeToFold, /*InsnID*/1, 11017 // (sext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] })) 11018 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11019 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11020 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 11021 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11022 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11023 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11024 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11025 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 11026 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 11027 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 11028 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11029 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 11030 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11031 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 11032 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11033 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11034 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11035 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11036 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11037 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_gt, 11038 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 11039 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 11040 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 11041 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11042 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11043 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11044 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11045 GIR_EraseFromParent, /*InsnID*/0, 11046 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11047 // GIR_Coverage, 3995, 11048 GIR_Done, 11049 // Label 754: @26485 11050 GIM_Try, /*On fail goto*//*Label 755*/ 26615, // Rule ID 4027 // 11051 GIM_CheckFeatures, GIFBS_HasFPU, 11052 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 11053 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 11054 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11055 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11056 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 11057 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 11058 // MIs[1] Operand 1 11059 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 11060 GIM_CheckIsSafeToFold, /*InsnID*/1, 11061 // (sext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] })) 11062 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11063 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11064 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 11065 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11066 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11067 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11068 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11069 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 11070 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 11071 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 11072 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11073 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 11074 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11075 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 11076 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11077 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11078 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11079 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11080 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11081 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_eq, 11082 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 11083 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 11084 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 11085 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11086 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11087 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11088 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11089 GIR_EraseFromParent, /*InsnID*/0, 11090 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11091 // GIR_Coverage, 4027, 11092 GIR_Done, 11093 // Label 755: @26615 11094 GIM_Try, /*On fail goto*//*Label 756*/ 26745, // Rule ID 4059 // 11095 GIM_CheckFeatures, GIFBS_HasFPU, 11096 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 11097 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 11098 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11099 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11100 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 11101 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 11102 // MIs[1] Operand 1 11103 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 11104 GIM_CheckIsSafeToFold, /*InsnID*/1, 11105 // (sext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_un:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] })) 11106 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11107 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11108 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 11109 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11110 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11111 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11112 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11113 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 11114 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 11115 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 11116 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11117 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 11118 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11119 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 11120 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11121 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11122 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11123 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11124 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11125 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_un, 11126 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 11127 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 11128 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 11129 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11130 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11131 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11132 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11133 GIR_EraseFromParent, /*InsnID*/0, 11134 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11135 // GIR_Coverage, 4059, 11136 GIR_Done, 11137 // Label 756: @26745 11138 GIM_Try, /*On fail goto*//*Label 757*/ 26875, // Rule ID 4075 // 11139 GIM_CheckFeatures, GIFBS_HasFPU, 11140 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 11141 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 11142 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11143 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11144 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 11145 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 11146 // MIs[1] Operand 1 11147 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 11148 GIM_CheckIsSafeToFold, /*InsnID*/1, 11149 // (sext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] })) 11150 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11151 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11152 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 11153 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11154 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11155 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11156 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11157 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 11158 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 11159 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 11160 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11161 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 11162 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11163 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 11164 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11165 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11166 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11167 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11168 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11169 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_lt, 11170 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 11171 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 11172 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 11173 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11174 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11175 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11176 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11177 GIR_EraseFromParent, /*InsnID*/0, 11178 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11179 // GIR_Coverage, 4075, 11180 GIR_Done, 11181 // Label 757: @26875 11182 GIM_Try, /*On fail goto*//*Label 758*/ 27005, // Rule ID 4107 // 11183 GIM_CheckFeatures, GIFBS_HasFPU, 11184 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 11185 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 11186 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11187 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11188 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 11189 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 11190 // MIs[1] Operand 1 11191 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 11192 GIM_CheckIsSafeToFold, /*InsnID*/1, 11193 // (sext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] })) 11194 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11195 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11196 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 11197 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11198 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11199 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11200 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11201 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 11202 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 11203 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 11204 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11205 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 11206 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11207 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 11208 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11209 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11210 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11211 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11212 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11213 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_gt, 11214 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 11215 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 11216 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 11217 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11218 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11219 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11220 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11221 GIR_EraseFromParent, /*InsnID*/0, 11222 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11223 // GIR_Coverage, 4107, 11224 GIR_Done, 11225 // Label 758: @27005 11226 GIM_Try, /*On fail goto*//*Label 759*/ 27135, // Rule ID 4139 // 11227 GIM_CheckFeatures, GIFBS_HasFPU, 11228 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 11229 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 11230 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11231 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11232 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 11233 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 11234 // MIs[1] Operand 1 11235 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 11236 GIM_CheckIsSafeToFold, /*InsnID*/1, 11237 // (sext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] })) 11238 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11239 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11240 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 11241 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11242 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11243 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11244 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11245 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 11246 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 11247 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 11248 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11249 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 11250 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11251 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 11252 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11253 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11254 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11255 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11256 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11257 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_eq, 11258 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 11259 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 11260 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 11261 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11262 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11263 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11264 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11265 GIR_EraseFromParent, /*InsnID*/0, 11266 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11267 // GIR_Coverage, 4139, 11268 GIR_Done, 11269 // Label 759: @27135 11270 GIM_Try, /*On fail goto*//*Label 760*/ 27265, // Rule ID 4171 // 11271 GIM_CheckFeatures, GIFBS_HasFPU, 11272 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 11273 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 11274 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11275 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11276 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 11277 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 11278 // MIs[1] Operand 1 11279 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 11280 GIM_CheckIsSafeToFold, /*InsnID*/1, 11281 // (sext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_un:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] })) 11282 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11283 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11284 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 11285 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11286 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11287 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11288 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11289 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 11290 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 11291 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 11292 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11293 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 11294 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11295 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 11296 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11297 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11298 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11299 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11300 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11301 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_un, 11302 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 11303 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 11304 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 11305 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11306 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11307 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11308 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11309 GIR_EraseFromParent, /*InsnID*/0, 11310 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11311 // GIR_Coverage, 4171, 11312 GIR_Done, 11313 // Label 760: @27265 11314 GIM_Try, /*On fail goto*//*Label 761*/ 27395, // Rule ID 4201 // 11315 GIM_CheckFeatures, GIFBS_HasFPU, 11316 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 11317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 11318 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11319 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11320 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 11321 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 11322 // MIs[1] Operand 1 11323 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 11324 GIM_CheckIsSafeToFold, /*InsnID*/1, 11325 // (sext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] })) 11326 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11327 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11328 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 11329 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11330 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11331 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11332 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11333 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 11334 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 11335 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 11336 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11337 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 11338 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11339 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 11340 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11341 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11342 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11343 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11344 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11345 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_lt, 11346 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 11347 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 11348 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 11349 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11350 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11351 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11352 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11353 GIR_EraseFromParent, /*InsnID*/0, 11354 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11355 // GIR_Coverage, 4201, 11356 GIR_Done, 11357 // Label 761: @27395 11358 GIM_Try, /*On fail goto*//*Label 762*/ 27525, // Rule ID 4233 // 11359 GIM_CheckFeatures, GIFBS_HasFPU, 11360 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 11361 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 11362 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11363 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11364 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 11365 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 11366 // MIs[1] Operand 1 11367 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 11368 GIM_CheckIsSafeToFold, /*InsnID*/1, 11369 // (sext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] })) 11370 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11371 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11372 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 11373 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11374 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11375 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11376 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11377 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 11378 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 11379 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 11380 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11381 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 11382 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11383 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 11384 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11385 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11386 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11387 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11388 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11389 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_gt, 11390 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 11391 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 11392 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 11393 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11394 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11395 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11396 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11397 GIR_EraseFromParent, /*InsnID*/0, 11398 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11399 // GIR_Coverage, 4233, 11400 GIR_Done, 11401 // Label 762: @27525 11402 GIM_Try, /*On fail goto*//*Label 763*/ 27655, // Rule ID 4265 // 11403 GIM_CheckFeatures, GIFBS_HasFPU, 11404 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 11405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 11406 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11407 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11408 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 11409 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 11410 // MIs[1] Operand 1 11411 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 11412 GIM_CheckIsSafeToFold, /*InsnID*/1, 11413 // (sext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] })) 11414 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11415 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11416 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 11417 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11418 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11419 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11420 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11421 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 11422 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 11423 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 11424 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11425 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 11426 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11427 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 11428 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11429 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11430 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11431 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11432 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11433 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_eq, 11434 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 11435 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 11436 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 11437 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11438 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11439 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11440 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11441 GIR_EraseFromParent, /*InsnID*/0, 11442 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11443 // GIR_Coverage, 4265, 11444 GIR_Done, 11445 // Label 763: @27655 11446 GIM_Try, /*On fail goto*//*Label 764*/ 27785, // Rule ID 4297 // 11447 GIM_CheckFeatures, GIFBS_HasFPU, 11448 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 11449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 11450 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11451 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11452 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 11453 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 11454 // MIs[1] Operand 1 11455 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 11456 GIM_CheckIsSafeToFold, /*InsnID*/1, 11457 // (sext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_un:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] })) 11458 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11459 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11460 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 11461 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11462 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11463 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11464 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11465 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 11466 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 11467 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 11468 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11469 GIR_AddImm, /*InsnID*/4, /*Imm*/-1, 11470 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11471 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 11472 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11473 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11474 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11475 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11476 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11477 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_un, 11478 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 11479 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 11480 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 11481 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11482 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11483 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11484 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11485 GIR_EraseFromParent, /*InsnID*/0, 11486 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11487 // GIR_Coverage, 4297, 11488 GIR_Done, 11489 // Label 764: @27785 11490 GIM_Try, /*On fail goto*//*Label 765*/ 27802, // Rule ID 676 // 11491 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 11492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 11493 // (sext:{ *:[i64] } i32:{ *:[i32] }:$rS) => (EXTSW_32_64:{ *:[i64] } i32:{ *:[i32] }:$rS) 11494 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EXTSW_32_64, 11495 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11496 // GIR_Coverage, 676, 11497 GIR_Done, 11498 // Label 765: @27802 11499 GIM_Reject, 11500 // Label 739: @27803 11501 GIM_Reject, 11502 // Label 22: @27804 11503 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 768*/ 30764, 11504 /*GILLT_s32*//*Label 766*/ 27812, 11505 /*GILLT_s64*//*Label 767*/ 29288, 11506 // Label 766: @27812 11507 GIM_Try, /*On fail goto*//*Label 769*/ 29287, 11508 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 11509 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 11510 GIM_Try, /*On fail goto*//*Label 770*/ 27944, // Rule ID 3957 // 11511 GIM_CheckFeatures, GIFBS_HasFPU, 11512 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11513 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11514 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 11515 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 11516 // MIs[1] Operand 1 11517 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 11518 GIM_CheckIsSafeToFold, /*InsnID*/1, 11519 // (zext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 11520 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11521 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11522 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 11523 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11524 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11525 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11526 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11527 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 11528 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 11529 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 11530 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11531 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 11532 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11533 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 11534 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11535 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11536 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11537 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11538 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11539 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_lt, 11540 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 11541 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 11542 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 11543 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11544 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11545 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11546 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11547 GIR_EraseFromParent, /*InsnID*/0, 11548 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11549 // GIR_Coverage, 3957, 11550 GIR_Done, 11551 // Label 770: @27944 11552 GIM_Try, /*On fail goto*//*Label 771*/ 28066, // Rule ID 3989 // 11553 GIM_CheckFeatures, GIFBS_HasFPU, 11554 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11555 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11556 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 11557 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 11558 // MIs[1] Operand 1 11559 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 11560 GIM_CheckIsSafeToFold, /*InsnID*/1, 11561 // (zext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 11562 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11563 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11564 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 11565 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11566 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11567 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11568 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11569 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 11570 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 11571 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 11572 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11573 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 11574 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11575 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 11576 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11577 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11578 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11579 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11580 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11581 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_gt, 11582 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 11583 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 11584 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 11585 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11586 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11587 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11588 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11589 GIR_EraseFromParent, /*InsnID*/0, 11590 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11591 // GIR_Coverage, 3989, 11592 GIR_Done, 11593 // Label 771: @28066 11594 GIM_Try, /*On fail goto*//*Label 772*/ 28188, // Rule ID 4021 // 11595 GIM_CheckFeatures, GIFBS_HasFPU, 11596 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11597 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11598 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 11599 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 11600 // MIs[1] Operand 1 11601 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 11602 GIM_CheckIsSafeToFold, /*InsnID*/1, 11603 // (zext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 11604 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11605 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11606 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 11607 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11608 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11609 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11610 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11611 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 11612 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 11613 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 11614 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11615 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 11616 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11617 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 11618 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11619 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11620 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11621 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11622 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11623 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_eq, 11624 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 11625 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 11626 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 11627 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11628 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11629 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11630 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11631 GIR_EraseFromParent, /*InsnID*/0, 11632 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11633 // GIR_Coverage, 4021, 11634 GIR_Done, 11635 // Label 772: @28188 11636 GIM_Try, /*On fail goto*//*Label 773*/ 28310, // Rule ID 4053 // 11637 GIM_CheckFeatures, GIFBS_HasFPU, 11638 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11639 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11640 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 11641 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 11642 // MIs[1] Operand 1 11643 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 11644 GIM_CheckIsSafeToFold, /*InsnID*/1, 11645 // (zext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_un:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 11646 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11647 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11648 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 11649 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11650 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11651 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11652 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11653 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 11654 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 11655 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 11656 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11657 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 11658 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11659 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 11660 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11661 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11662 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11663 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11664 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11665 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_un, 11666 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 11667 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 11668 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 11669 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11670 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11671 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11672 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11673 GIR_EraseFromParent, /*InsnID*/0, 11674 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11675 // GIR_Coverage, 4053, 11676 GIR_Done, 11677 // Label 773: @28310 11678 GIM_Try, /*On fail goto*//*Label 774*/ 28432, // Rule ID 4069 // 11679 GIM_CheckFeatures, GIFBS_HasFPU, 11680 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11681 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11682 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 11683 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 11684 // MIs[1] Operand 1 11685 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 11686 GIM_CheckIsSafeToFold, /*InsnID*/1, 11687 // (zext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 11688 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11689 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11690 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 11691 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11692 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11693 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11694 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11695 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 11696 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 11697 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 11698 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11699 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 11700 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11701 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 11702 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11703 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11704 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11705 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11706 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11707 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_lt, 11708 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 11709 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 11710 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 11711 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11712 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11713 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11714 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11715 GIR_EraseFromParent, /*InsnID*/0, 11716 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11717 // GIR_Coverage, 4069, 11718 GIR_Done, 11719 // Label 774: @28432 11720 GIM_Try, /*On fail goto*//*Label 775*/ 28554, // Rule ID 4101 // 11721 GIM_CheckFeatures, GIFBS_HasFPU, 11722 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11723 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11724 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 11725 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 11726 // MIs[1] Operand 1 11727 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 11728 GIM_CheckIsSafeToFold, /*InsnID*/1, 11729 // (zext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 11730 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11731 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11732 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 11733 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11734 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11735 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11736 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11737 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 11738 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 11739 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 11740 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11741 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 11742 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11743 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 11744 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11745 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11746 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11747 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11748 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11749 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_gt, 11750 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 11751 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 11752 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 11753 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11754 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11755 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11756 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11757 GIR_EraseFromParent, /*InsnID*/0, 11758 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11759 // GIR_Coverage, 4101, 11760 GIR_Done, 11761 // Label 775: @28554 11762 GIM_Try, /*On fail goto*//*Label 776*/ 28676, // Rule ID 4133 // 11763 GIM_CheckFeatures, GIFBS_HasFPU, 11764 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11765 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11766 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 11767 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 11768 // MIs[1] Operand 1 11769 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 11770 GIM_CheckIsSafeToFold, /*InsnID*/1, 11771 // (zext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 11772 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11773 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11774 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 11775 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11776 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11777 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11778 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11779 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 11780 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 11781 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 11782 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11783 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 11784 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11785 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 11786 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11787 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11788 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11789 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11790 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11791 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_eq, 11792 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 11793 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 11794 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 11795 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11796 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11797 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11798 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11799 GIR_EraseFromParent, /*InsnID*/0, 11800 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11801 // GIR_Coverage, 4133, 11802 GIR_Done, 11803 // Label 776: @28676 11804 GIM_Try, /*On fail goto*//*Label 777*/ 28798, // Rule ID 4165 // 11805 GIM_CheckFeatures, GIFBS_HasFPU, 11806 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11807 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11808 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 11809 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 11810 // MIs[1] Operand 1 11811 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 11812 GIM_CheckIsSafeToFold, /*InsnID*/1, 11813 // (zext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_un:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 11814 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11815 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11816 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 11817 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11818 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11819 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11820 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11821 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 11822 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 11823 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 11824 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11825 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 11826 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11827 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 11828 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11829 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11830 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11831 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11832 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11833 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_un, 11834 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 11835 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 11836 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 11837 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11838 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11839 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11840 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11841 GIR_EraseFromParent, /*InsnID*/0, 11842 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11843 // GIR_Coverage, 4165, 11844 GIR_Done, 11845 // Label 777: @28798 11846 GIM_Try, /*On fail goto*//*Label 778*/ 28920, // Rule ID 4195 // 11847 GIM_CheckFeatures, GIFBS_HasFPU, 11848 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11849 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11850 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 11851 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 11852 // MIs[1] Operand 1 11853 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 11854 GIM_CheckIsSafeToFold, /*InsnID*/1, 11855 // (zext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 11856 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11857 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11858 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 11859 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11860 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11861 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11862 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11863 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 11864 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 11865 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 11866 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11867 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 11868 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11869 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 11870 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11871 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11872 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11873 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11874 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11875 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_lt, 11876 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 11877 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 11878 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 11879 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11880 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11881 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11882 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11883 GIR_EraseFromParent, /*InsnID*/0, 11884 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11885 // GIR_Coverage, 4195, 11886 GIR_Done, 11887 // Label 778: @28920 11888 GIM_Try, /*On fail goto*//*Label 779*/ 29042, // Rule ID 4227 // 11889 GIM_CheckFeatures, GIFBS_HasFPU, 11890 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11891 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11892 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 11893 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 11894 // MIs[1] Operand 1 11895 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 11896 GIM_CheckIsSafeToFold, /*InsnID*/1, 11897 // (zext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 11898 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11899 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11900 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 11901 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11902 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11903 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11904 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11905 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 11906 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 11907 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 11908 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11909 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 11910 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11911 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 11912 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11913 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11914 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11915 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11916 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11917 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_gt, 11918 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 11919 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 11920 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 11921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11922 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11923 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11924 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11925 GIR_EraseFromParent, /*InsnID*/0, 11926 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11927 // GIR_Coverage, 4227, 11928 GIR_Done, 11929 // Label 779: @29042 11930 GIM_Try, /*On fail goto*//*Label 780*/ 29164, // Rule ID 4259 // 11931 GIM_CheckFeatures, GIFBS_HasFPU, 11932 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11933 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11934 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 11935 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 11936 // MIs[1] Operand 1 11937 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 11938 GIM_CheckIsSafeToFold, /*InsnID*/1, 11939 // (zext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 11940 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11941 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11942 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 11943 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11944 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11945 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11946 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11947 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 11948 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 11949 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 11950 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11951 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 11952 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11953 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 11954 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11955 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11956 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11957 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11958 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11959 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_eq, 11960 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 11961 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 11962 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 11963 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11964 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11965 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 11966 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 11967 GIR_EraseFromParent, /*InsnID*/0, 11968 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11969 // GIR_Coverage, 4259, 11970 GIR_Done, 11971 // Label 780: @29164 11972 GIM_Try, /*On fail goto*//*Label 781*/ 29286, // Rule ID 4291 // 11973 GIM_CheckFeatures, GIFBS_HasFPU, 11974 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11975 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 11976 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 11977 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 11978 // MIs[1] Operand 1 11979 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 11980 GIM_CheckIsSafeToFold, /*InsnID*/1, 11981 // (zext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_un:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] })) 11982 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 11983 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11984 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 11985 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11986 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 11987 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 11988 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11989 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 11990 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 11991 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI, 11992 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 11993 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 11994 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 11995 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI, 11996 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11997 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 11998 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11999 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12000 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12001 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_un, 12002 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 12003 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 12004 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I4, 12005 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12006 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12007 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 12008 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 12009 GIR_EraseFromParent, /*InsnID*/0, 12010 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12011 // GIR_Coverage, 4291, 12012 GIR_Done, 12013 // Label 781: @29286 12014 GIM_Reject, 12015 // Label 769: @29287 12016 GIM_Reject, 12017 // Label 767: @29288 12018 GIM_Try, /*On fail goto*//*Label 782*/ 30763, 12019 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 12020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 12021 GIM_Try, /*On fail goto*//*Label 783*/ 29420, // Rule ID 3961 // 12022 GIM_CheckFeatures, GIFBS_HasFPU, 12023 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 12024 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 12025 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 12026 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 12027 // MIs[1] Operand 1 12028 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 12029 GIM_CheckIsSafeToFold, /*InsnID*/1, 12030 // (zext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 12031 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 12032 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 12033 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 12034 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12035 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 12036 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 12037 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12038 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 12039 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 12040 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 12041 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 12042 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 12043 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 12044 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 12045 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 12046 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 12047 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 12048 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12049 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12050 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_lt, 12051 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 12052 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 12053 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 12054 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12055 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12056 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 12057 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 12058 GIR_EraseFromParent, /*InsnID*/0, 12059 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12060 // GIR_Coverage, 3961, 12061 GIR_Done, 12062 // Label 783: @29420 12063 GIM_Try, /*On fail goto*//*Label 784*/ 29542, // Rule ID 3993 // 12064 GIM_CheckFeatures, GIFBS_HasFPU, 12065 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 12066 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 12067 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 12068 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 12069 // MIs[1] Operand 1 12070 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 12071 GIM_CheckIsSafeToFold, /*InsnID*/1, 12072 // (zext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 12073 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 12074 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 12075 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 12076 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12077 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 12078 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 12079 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12080 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 12081 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 12082 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 12083 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 12084 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 12085 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 12086 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 12087 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 12088 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 12089 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 12090 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12091 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12092 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_gt, 12093 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 12094 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 12095 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 12096 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12097 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12098 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 12099 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 12100 GIR_EraseFromParent, /*InsnID*/0, 12101 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12102 // GIR_Coverage, 3993, 12103 GIR_Done, 12104 // Label 784: @29542 12105 GIM_Try, /*On fail goto*//*Label 785*/ 29664, // Rule ID 4025 // 12106 GIM_CheckFeatures, GIFBS_HasFPU, 12107 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 12108 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 12109 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 12110 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 12111 // MIs[1] Operand 1 12112 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 12113 GIM_CheckIsSafeToFold, /*InsnID*/1, 12114 // (zext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 12115 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 12116 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 12117 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 12118 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12119 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 12120 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 12121 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12122 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 12123 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 12124 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 12125 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 12126 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 12127 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 12128 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 12129 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 12130 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 12131 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 12132 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12133 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12134 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_eq, 12135 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 12136 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 12137 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 12138 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12139 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12140 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 12141 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 12142 GIR_EraseFromParent, /*InsnID*/0, 12143 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12144 // GIR_Coverage, 4025, 12145 GIR_Done, 12146 // Label 785: @29664 12147 GIM_Try, /*On fail goto*//*Label 786*/ 29786, // Rule ID 4057 // 12148 GIM_CheckFeatures, GIFBS_HasFPU, 12149 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 12150 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 12151 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 12152 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 12153 // MIs[1] Operand 1 12154 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 12155 GIM_CheckIsSafeToFold, /*InsnID*/1, 12156 // (zext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_un:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 12157 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 12158 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 12159 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 12160 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12161 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 12162 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 12163 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12164 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 12165 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 12166 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 12167 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 12168 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 12169 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 12170 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 12171 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 12172 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 12173 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 12174 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12175 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12176 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_un, 12177 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 12178 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 12179 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 12180 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12181 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12182 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 12183 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 12184 GIR_EraseFromParent, /*InsnID*/0, 12185 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12186 // GIR_Coverage, 4057, 12187 GIR_Done, 12188 // Label 786: @29786 12189 GIM_Try, /*On fail goto*//*Label 787*/ 29908, // Rule ID 4073 // 12190 GIM_CheckFeatures, GIFBS_HasFPU, 12191 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 12192 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 12193 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 12194 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 12195 // MIs[1] Operand 1 12196 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 12197 GIM_CheckIsSafeToFold, /*InsnID*/1, 12198 // (zext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 12199 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 12200 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 12201 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 12202 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12203 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 12204 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 12205 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12206 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 12207 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 12208 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 12209 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 12210 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 12211 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 12212 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 12213 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 12214 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 12215 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 12216 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12217 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12218 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_lt, 12219 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 12220 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 12221 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 12222 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12223 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12224 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 12225 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 12226 GIR_EraseFromParent, /*InsnID*/0, 12227 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12228 // GIR_Coverage, 4073, 12229 GIR_Done, 12230 // Label 787: @29908 12231 GIM_Try, /*On fail goto*//*Label 788*/ 30030, // Rule ID 4105 // 12232 GIM_CheckFeatures, GIFBS_HasFPU, 12233 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 12234 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 12235 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 12236 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 12237 // MIs[1] Operand 1 12238 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 12239 GIM_CheckIsSafeToFold, /*InsnID*/1, 12240 // (zext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 12241 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 12242 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 12243 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 12244 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12245 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 12246 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 12247 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12248 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 12249 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 12250 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 12251 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 12252 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 12253 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 12254 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 12255 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 12256 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 12257 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 12258 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12259 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12260 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_gt, 12261 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 12262 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 12263 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 12264 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12265 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12266 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 12267 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 12268 GIR_EraseFromParent, /*InsnID*/0, 12269 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12270 // GIR_Coverage, 4105, 12271 GIR_Done, 12272 // Label 788: @30030 12273 GIM_Try, /*On fail goto*//*Label 789*/ 30152, // Rule ID 4137 // 12274 GIM_CheckFeatures, GIFBS_HasFPU, 12275 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 12276 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 12277 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 12278 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 12279 // MIs[1] Operand 1 12280 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 12281 GIM_CheckIsSafeToFold, /*InsnID*/1, 12282 // (zext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 12283 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 12284 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 12285 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 12286 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12287 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 12288 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 12289 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12290 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 12291 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 12292 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 12293 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 12294 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 12295 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 12296 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 12297 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 12298 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 12299 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 12300 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12301 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12302 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_eq, 12303 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 12304 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 12305 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 12306 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12307 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12308 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 12309 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 12310 GIR_EraseFromParent, /*InsnID*/0, 12311 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12312 // GIR_Coverage, 4137, 12313 GIR_Done, 12314 // Label 789: @30152 12315 GIM_Try, /*On fail goto*//*Label 790*/ 30274, // Rule ID 4169 // 12316 GIM_CheckFeatures, GIFBS_HasFPU, 12317 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 12318 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 12319 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 12320 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 12321 // MIs[1] Operand 1 12322 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 12323 GIM_CheckIsSafeToFold, /*InsnID*/1, 12324 // (zext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_un:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 12325 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 12326 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 12327 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 12328 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12329 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 12330 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 12331 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12332 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 12333 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 12334 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 12335 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 12336 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 12337 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 12338 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 12339 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 12340 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 12341 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 12342 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12343 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12344 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_un, 12345 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 12346 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 12347 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 12348 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12349 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12350 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 12351 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 12352 GIR_EraseFromParent, /*InsnID*/0, 12353 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12354 // GIR_Coverage, 4169, 12355 GIR_Done, 12356 // Label 790: @30274 12357 GIM_Try, /*On fail goto*//*Label 791*/ 30396, // Rule ID 4199 // 12358 GIM_CheckFeatures, GIFBS_HasFPU, 12359 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 12360 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 12361 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 12362 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 12363 // MIs[1] Operand 1 12364 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 12365 GIM_CheckIsSafeToFold, /*InsnID*/1, 12366 // (zext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 12367 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 12368 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 12369 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 12370 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12371 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 12372 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 12373 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12374 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 12375 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 12376 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 12377 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 12378 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 12379 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 12380 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 12381 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 12382 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 12383 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 12384 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12385 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12386 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_lt, 12387 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 12388 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 12389 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 12390 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12391 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12392 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 12393 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 12394 GIR_EraseFromParent, /*InsnID*/0, 12395 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12396 // GIR_Coverage, 4199, 12397 GIR_Done, 12398 // Label 791: @30396 12399 GIM_Try, /*On fail goto*//*Label 792*/ 30518, // Rule ID 4231 // 12400 GIM_CheckFeatures, GIFBS_HasFPU, 12401 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 12402 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 12403 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 12404 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 12405 // MIs[1] Operand 1 12406 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 12407 GIM_CheckIsSafeToFold, /*InsnID*/1, 12408 // (zext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 12409 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 12410 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 12411 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 12412 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12413 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 12414 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 12415 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12416 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 12417 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 12418 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 12419 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 12420 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 12421 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 12422 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 12423 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 12424 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 12425 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 12426 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12427 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12428 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_gt, 12429 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 12430 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 12431 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 12432 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12433 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12434 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 12435 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 12436 GIR_EraseFromParent, /*InsnID*/0, 12437 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12438 // GIR_Coverage, 4231, 12439 GIR_Done, 12440 // Label 792: @30518 12441 GIM_Try, /*On fail goto*//*Label 793*/ 30640, // Rule ID 4263 // 12442 GIM_CheckFeatures, GIFBS_HasFPU, 12443 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 12444 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 12445 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 12446 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 12447 // MIs[1] Operand 1 12448 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 12449 GIM_CheckIsSafeToFold, /*InsnID*/1, 12450 // (zext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 12451 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 12452 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 12453 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 12454 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12455 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 12456 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 12457 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12458 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 12459 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 12460 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 12461 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 12462 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 12463 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 12464 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 12465 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 12466 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 12467 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 12468 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12469 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12470 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_eq, 12471 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 12472 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 12473 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 12474 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12475 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12476 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 12477 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 12478 GIR_EraseFromParent, /*InsnID*/0, 12479 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12480 // GIR_Coverage, 4263, 12481 GIR_Done, 12482 // Label 793: @30640 12483 GIM_Try, /*On fail goto*//*Label 794*/ 30762, // Rule ID 4295 // 12484 GIM_CheckFeatures, GIFBS_HasFPU, 12485 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 12486 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCMP, 12487 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 12488 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 12489 // MIs[1] Operand 1 12490 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 12491 GIM_CheckIsSafeToFold, /*InsnID*/1, 12492 // (zext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_un:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] })) 12493 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 12494 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 12495 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 12496 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12497 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1 12498 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2 12499 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12500 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 12501 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 12502 GIR_BuildMI, /*InsnID*/4, /*Opcode*/PPC::LI8, 12503 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 12504 GIR_AddImm, /*InsnID*/4, /*Imm*/1, 12505 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 12506 GIR_BuildMI, /*InsnID*/3, /*Opcode*/PPC::LI8, 12507 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 12508 GIR_AddImm, /*InsnID*/3, /*Imm*/0, 12509 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 12510 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12511 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12512 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_un, 12513 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 12514 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 12515 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SELECT_I8, 12516 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12517 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12518 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 12519 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, 12520 GIR_EraseFromParent, /*InsnID*/0, 12521 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12522 // GIR_Coverage, 4295, 12523 GIR_Done, 12524 // Label 794: @30762 12525 GIM_Reject, 12526 // Label 782: @30763 12527 GIM_Reject, 12528 // Label 768: @30764 12529 GIM_Reject, 12530 // Label 23: @30765 12531 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 797*/ 30859, 12532 /*GILLT_s32*//*Label 795*/ 30773, 12533 /*GILLT_s64*//*Label 796*/ 30816, 12534 // Label 795: @30773 12535 GIM_Try, /*On fail goto*//*Label 798*/ 30815, // Rule ID 129 // 12536 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 12537 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 12538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 12539 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12540 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12541 // MIs[1] Operand 1 12542 // No operand predicates 12543 GIM_CheckIsSafeToFold, /*InsnID*/1, 12544 // (sra:{ *:[i32] } i32:{ *:[i32] }:$rS, (imm:{ *:[i32] }):$SH) => (SRAWI:{ *:[i32] }:{ *:[i32] } i32:{ *:[i32] }:$rS, (imm:{ *:[i32] }):$SH) 12545 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SRAWI, 12546 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 12547 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rS 12548 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SH 12549 GIR_EraseFromParent, /*InsnID*/0, 12550 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12551 // GIR_Coverage, 129, 12552 GIR_Done, 12553 // Label 798: @30815 12554 GIM_Reject, 12555 // Label 796: @30816 12556 GIM_Try, /*On fail goto*//*Label 799*/ 30858, // Rule ID 677 // 12557 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 12558 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 12559 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 12560 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12561 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12562 // MIs[1] Operand 1 12563 // No operand predicates 12564 GIM_CheckIsSafeToFold, /*InsnID*/1, 12565 // (sra:{ *:[i64] } i64:{ *:[i64] }:$rS, (imm:{ *:[i32] }):$SH) => (SRADI:{ *:[i64] }:{ *:[i32] } i64:{ *:[i64] }:$rS, (imm:{ *:[i32] }):$SH) 12566 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::SRADI, 12567 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rA 12568 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rS 12569 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SH 12570 GIR_EraseFromParent, /*InsnID*/0, 12571 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12572 // GIR_Coverage, 677, 12573 GIR_Done, 12574 // Label 799: @30858 12575 GIM_Reject, 12576 // Label 797: @30859 12577 GIM_Reject, 12578 // Label 24: @30860 12579 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 8, /*)*//*default:*//*Label 805*/ 30991, 12580 /*GILLT_s128*//*Label 800*/ 30871, 12581 /*GILLT_v2s64*//*Label 801*/ 30895, 12582 /*GILLT_v4s32*//*Label 802*/ 30919, 12583 /*GILLT_v8s16*//*Label 803*/ 30943, 12584 /*GILLT_v16s8*//*Label 804*/ 30967, 12585 // Label 800: @30871 12586 GIM_Try, /*On fail goto*//*Label 806*/ 30894, // Rule ID 3328 // 12587 GIM_CheckFeatures, GIFBS_IsISA3_1, 12588 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 12589 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 12590 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 12591 // (rotl:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) => (VRLQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) 12592 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VRLQ, 12593 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12594 // GIR_Coverage, 3328, 12595 GIR_Done, 12596 // Label 806: @30894 12597 GIM_Reject, 12598 // Label 801: @30895 12599 GIM_Try, /*On fail goto*//*Label 807*/ 30918, // Rule ID 1409 // 12600 GIM_CheckFeatures, GIFBS_HasP8Altivec, 12601 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 12602 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 12603 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 12604 // (rotl:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VRLD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 12605 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VRLD, 12606 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12607 // GIR_Coverage, 1409, 12608 GIR_Done, 12609 // Label 807: @30918 12610 GIM_Reject, 12611 // Label 802: @30919 12612 GIM_Try, /*On fail goto*//*Label 808*/ 30942, // Rule ID 1263 // 12613 GIM_CheckFeatures, GIFBS_HasAltivec, 12614 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 12615 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 12616 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 12617 // (rotl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VRLW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 12618 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VRLW, 12619 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12620 // GIR_Coverage, 1263, 12621 GIR_Done, 12622 // Label 808: @30942 12623 GIM_Reject, 12624 // Label 803: @30943 12625 GIM_Try, /*On fail goto*//*Label 809*/ 30966, // Rule ID 1262 // 12626 GIM_CheckFeatures, GIFBS_HasAltivec, 12627 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 12628 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 12629 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 12630 // (rotl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VRLH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) 12631 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VRLH, 12632 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12633 // GIR_Coverage, 1262, 12634 GIR_Done, 12635 // Label 809: @30966 12636 GIM_Reject, 12637 // Label 804: @30967 12638 GIM_Try, /*On fail goto*//*Label 810*/ 30990, // Rule ID 1261 // 12639 GIM_CheckFeatures, GIFBS_HasAltivec, 12640 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 12641 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 12642 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 12643 // (rotl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VRLB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) 12644 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VRLB, 12645 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12646 // GIR_Coverage, 1261, 12647 GIR_Done, 12648 // Label 810: @30990 12649 GIM_Reject, 12650 // Label 805: @30991 12651 GIM_Reject, 12652 // Label 25: @30992 12653 GIM_Try, /*On fail goto*//*Label 811*/ 32544, 12654 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1, 12655 GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 4, /*)*//*default:*//*Label 815*/ 32543, 12656 /*GILLT_s32*//*Label 812*/ 31007, 12657 /*GILLT_s64*//*Label 813*/ 31519, 12658 /*GILLT_s128*//*Label 814*/ 32031, 12659 // Label 812: @31007 12660 GIM_Try, /*On fail goto*//*Label 816*/ 31518, 12661 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 12662 GIM_Try, /*On fail goto*//*Label 817*/ 31068, // Rule ID 3939 // 12663 GIM_CheckFeatures, GIFBS_HasFPU, 12664 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 12665 // MIs[0] Operand 1 12666 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT, 12667 // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETOLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }) 12668 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12669 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::FCMPUS, 12670 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12671 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 12672 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 12673 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12674 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 12675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12676 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_lt, 12677 GIR_EraseFromParent, /*InsnID*/0, 12678 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 12679 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 12680 // GIR_Coverage, 3939, 12681 GIR_Done, 12682 // Label 817: @31068 12683 GIM_Try, /*On fail goto*//*Label 818*/ 31123, // Rule ID 3943 // 12684 GIM_CheckFeatures, GIFBS_HasFPU, 12685 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 12686 // MIs[0] Operand 1 12687 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OGT, 12688 // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETOGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }) 12689 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12690 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::FCMPUS, 12691 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12692 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 12693 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 12694 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12695 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 12696 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12697 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_gt, 12698 GIR_EraseFromParent, /*InsnID*/0, 12699 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 12700 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 12701 // GIR_Coverage, 3943, 12702 GIR_Done, 12703 // Label 818: @31123 12704 GIM_Try, /*On fail goto*//*Label 819*/ 31178, // Rule ID 3947 // 12705 GIM_CheckFeatures, GIFBS_HasFPU, 12706 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 12707 // MIs[0] Operand 1 12708 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ, 12709 // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETOEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }) 12710 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12711 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::FCMPUS, 12712 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12713 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 12714 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 12715 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12716 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 12717 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12718 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_eq, 12719 GIR_EraseFromParent, /*InsnID*/0, 12720 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 12721 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 12722 // GIR_Coverage, 3947, 12723 GIR_Done, 12724 // Label 819: @31178 12725 GIM_Try, /*On fail goto*//*Label 820*/ 31233, // Rule ID 3951 // 12726 GIM_CheckFeatures, GIFBS_HasFPU, 12727 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 12728 // MIs[0] Operand 1 12729 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO, 12730 // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUO:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_un:{ *:[i32] }) 12731 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12732 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::FCMPUS, 12733 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12734 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 12735 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 12736 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12737 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 12738 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12739 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_un, 12740 GIR_EraseFromParent, /*InsnID*/0, 12741 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 12742 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 12743 // GIR_Coverage, 3951, 12744 GIR_Done, 12745 // Label 820: @31233 12746 GIM_Try, /*On fail goto*//*Label 821*/ 31304, // Rule ID 3953 // 12747 GIM_CheckFeatures, GIFBS_HasFPU, 12748 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 12749 // MIs[0] Operand 1 12750 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 12751 // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_lt:{ *:[i32] })) 12752 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 12753 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 12754 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 12755 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12756 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 12757 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 12758 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12759 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12760 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12761 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_lt, 12762 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 12763 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 12764 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CRNOT, 12765 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // CRD 12766 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12767 GIR_EraseFromParent, /*InsnID*/0, 12768 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12769 // GIR_Coverage, 3953, 12770 GIR_Done, 12771 // Label 821: @31304 12772 GIM_Try, /*On fail goto*//*Label 822*/ 31375, // Rule ID 3985 // 12773 GIM_CheckFeatures, GIFBS_HasFPU, 12774 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 12775 // MIs[0] Operand 1 12776 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 12777 // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_gt:{ *:[i32] })) 12778 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 12779 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 12780 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 12781 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12782 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 12783 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 12784 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12785 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12786 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12787 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_gt, 12788 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 12789 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 12790 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CRNOT, 12791 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // CRD 12792 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12793 GIR_EraseFromParent, /*InsnID*/0, 12794 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12795 // GIR_Coverage, 3985, 12796 GIR_Done, 12797 // Label 822: @31375 12798 GIM_Try, /*On fail goto*//*Label 823*/ 31446, // Rule ID 4017 // 12799 GIM_CheckFeatures, GIFBS_HasFPU, 12800 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 12801 // MIs[0] Operand 1 12802 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 12803 // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_eq:{ *:[i32] })) 12804 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 12805 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 12806 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 12807 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12808 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 12809 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 12810 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12811 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12812 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12813 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_eq, 12814 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 12815 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 12816 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CRNOT, 12817 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // CRD 12818 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12819 GIR_EraseFromParent, /*InsnID*/0, 12820 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12821 // GIR_Coverage, 4017, 12822 GIR_Done, 12823 // Label 823: @31446 12824 GIM_Try, /*On fail goto*//*Label 824*/ 31517, // Rule ID 4049 // 12825 GIM_CheckFeatures, GIFBS_HasFPU, 12826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 12827 // MIs[0] Operand 1 12828 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 12829 // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2), sub_un:{ *:[i32] })) 12830 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 12831 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 12832 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUS, 12833 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12834 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 12835 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 12836 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12837 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12838 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12839 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_un, 12840 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 12841 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 12842 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CRNOT, 12843 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // CRD 12844 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12845 GIR_EraseFromParent, /*InsnID*/0, 12846 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12847 // GIR_Coverage, 4049, 12848 GIR_Done, 12849 // Label 824: @31517 12850 GIM_Reject, 12851 // Label 816: @31518 12852 GIM_Reject, 12853 // Label 813: @31519 12854 GIM_Try, /*On fail goto*//*Label 825*/ 32030, 12855 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 12856 GIM_Try, /*On fail goto*//*Label 826*/ 31596, // Rule ID 4065 // 12857 GIM_CheckFeatures, GIFBS_HasFPU, 12858 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 12859 // MIs[0] Operand 1 12860 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 12861 // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_lt:{ *:[i32] })) 12862 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 12863 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 12864 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 12865 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12866 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 12867 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 12868 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12869 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12870 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12871 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_lt, 12872 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 12873 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 12874 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CRNOT, 12875 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // CRD 12876 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12877 GIR_EraseFromParent, /*InsnID*/0, 12878 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12879 // GIR_Coverage, 4065, 12880 GIR_Done, 12881 // Label 826: @31596 12882 GIM_Try, /*On fail goto*//*Label 827*/ 31667, // Rule ID 4097 // 12883 GIM_CheckFeatures, GIFBS_HasFPU, 12884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 12885 // MIs[0] Operand 1 12886 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 12887 // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_gt:{ *:[i32] })) 12888 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 12889 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 12890 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 12891 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12892 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 12893 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 12894 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12895 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12896 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12897 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_gt, 12898 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 12899 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 12900 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CRNOT, 12901 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // CRD 12902 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12903 GIR_EraseFromParent, /*InsnID*/0, 12904 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12905 // GIR_Coverage, 4097, 12906 GIR_Done, 12907 // Label 827: @31667 12908 GIM_Try, /*On fail goto*//*Label 828*/ 31738, // Rule ID 4129 // 12909 GIM_CheckFeatures, GIFBS_HasFPU, 12910 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 12911 // MIs[0] Operand 1 12912 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 12913 // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_eq:{ *:[i32] })) 12914 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 12915 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 12916 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 12917 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12918 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 12919 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 12920 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12921 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12922 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12923 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_eq, 12924 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 12925 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 12926 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CRNOT, 12927 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // CRD 12928 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12929 GIR_EraseFromParent, /*InsnID*/0, 12930 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12931 // GIR_Coverage, 4129, 12932 GIR_Done, 12933 // Label 828: @31738 12934 GIM_Try, /*On fail goto*//*Label 829*/ 31809, // Rule ID 4161 // 12935 GIM_CheckFeatures, GIFBS_HasFPU, 12936 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 12937 // MIs[0] Operand 1 12938 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 12939 // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_un:{ *:[i32] })) 12940 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 12941 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 12942 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::FCMPUD, 12943 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12944 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 12945 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 12946 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12947 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12948 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12949 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_un, 12950 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 12951 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 12952 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CRNOT, 12953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // CRD 12954 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12955 GIR_EraseFromParent, /*InsnID*/0, 12956 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12957 // GIR_Coverage, 4161, 12958 GIR_Done, 12959 // Label 829: @31809 12960 GIM_Try, /*On fail goto*//*Label 830*/ 31864, // Rule ID 4177 // 12961 GIM_CheckFeatures, GIFBS_HasFPU, 12962 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 12963 // MIs[0] Operand 1 12964 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT, 12965 // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETOLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }) 12966 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12967 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::FCMPUD, 12968 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12969 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 12970 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 12971 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12972 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 12973 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12974 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_lt, 12975 GIR_EraseFromParent, /*InsnID*/0, 12976 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 12977 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 12978 // GIR_Coverage, 4177, 12979 GIR_Done, 12980 // Label 830: @31864 12981 GIM_Try, /*On fail goto*//*Label 831*/ 31919, // Rule ID 4181 // 12982 GIM_CheckFeatures, GIFBS_HasFPU, 12983 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 12984 // MIs[0] Operand 1 12985 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OGT, 12986 // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETOGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }) 12987 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12988 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::FCMPUD, 12989 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12990 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 12991 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 12992 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12993 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 12994 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12995 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_gt, 12996 GIR_EraseFromParent, /*InsnID*/0, 12997 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 12998 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 12999 // GIR_Coverage, 4181, 13000 GIR_Done, 13001 // Label 831: @31919 13002 GIM_Try, /*On fail goto*//*Label 832*/ 31974, // Rule ID 4185 // 13003 GIM_CheckFeatures, GIFBS_HasFPU, 13004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 13005 // MIs[0] Operand 1 13006 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ, 13007 // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETOEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }) 13008 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 13009 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::FCMPUD, 13010 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13011 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 13012 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 13013 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13014 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 13015 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13016 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_eq, 13017 GIR_EraseFromParent, /*InsnID*/0, 13018 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 13019 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 13020 // GIR_Coverage, 4185, 13021 GIR_Done, 13022 // Label 832: @31974 13023 GIM_Try, /*On fail goto*//*Label 833*/ 32029, // Rule ID 4189 // 13024 GIM_CheckFeatures, GIFBS_HasFPU, 13025 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 13026 // MIs[0] Operand 1 13027 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO, 13028 // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUO:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2), sub_un:{ *:[i32] }) 13029 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 13030 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::FCMPUD, 13031 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13032 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 13033 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 13034 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13035 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 13036 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13037 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_un, 13038 GIR_EraseFromParent, /*InsnID*/0, 13039 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 13040 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 13041 // GIR_Coverage, 4189, 13042 GIR_Done, 13043 // Label 833: @32029 13044 GIM_Reject, 13045 // Label 825: @32030 13046 GIM_Reject, 13047 // Label 814: @32031 13048 GIM_Try, /*On fail goto*//*Label 834*/ 32542, 13049 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s128, 13050 GIM_Try, /*On fail goto*//*Label 835*/ 32108, // Rule ID 4191 // 13051 GIM_CheckFeatures, GIFBS_HasFPU, 13052 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 13053 // MIs[0] Operand 1 13054 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UGE, 13055 // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_lt:{ *:[i32] })) 13056 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 13057 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 13058 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 13059 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 13060 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 13061 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 13062 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 13063 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 13064 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13065 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_lt, 13066 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 13067 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 13068 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CRNOT, 13069 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // CRD 13070 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13071 GIR_EraseFromParent, /*InsnID*/0, 13072 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13073 // GIR_Coverage, 4191, 13074 GIR_Done, 13075 // Label 835: @32108 13076 GIM_Try, /*On fail goto*//*Label 836*/ 32179, // Rule ID 4223 // 13077 GIM_CheckFeatures, GIFBS_HasFPU, 13078 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 13079 // MIs[0] Operand 1 13080 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, 13081 // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_gt:{ *:[i32] })) 13082 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 13083 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 13084 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 13085 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 13086 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 13087 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 13088 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 13089 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 13090 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13091 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_gt, 13092 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 13093 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 13094 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CRNOT, 13095 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // CRD 13096 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13097 GIR_EraseFromParent, /*InsnID*/0, 13098 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13099 // GIR_Coverage, 4223, 13100 GIR_Done, 13101 // Label 836: @32179 13102 GIM_Try, /*On fail goto*//*Label 837*/ 32250, // Rule ID 4255 // 13103 GIM_CheckFeatures, GIFBS_HasFPU, 13104 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 13105 // MIs[0] Operand 1 13106 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, 13107 // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_eq:{ *:[i32] })) 13108 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 13109 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 13110 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 13111 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 13112 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 13113 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 13114 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 13115 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 13116 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13117 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_eq, 13118 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 13119 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 13120 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CRNOT, 13121 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // CRD 13122 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13123 GIR_EraseFromParent, /*InsnID*/0, 13124 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13125 // GIR_Coverage, 4255, 13126 GIR_Done, 13127 // Label 837: @32250 13128 GIM_Try, /*On fail goto*//*Label 838*/ 32321, // Rule ID 4287 // 13129 GIM_CheckFeatures, GIFBS_HasFPU, 13130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRBITRCRegClassID, 13131 // MIs[0] Operand 1 13132 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 13133 // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_un:{ *:[i32] })) 13134 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, 13135 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 13136 GIR_BuildMI, /*InsnID*/2, /*Opcode*/PPC::XSCMPUQP, 13137 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 13138 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 13139 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 13140 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 13141 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 13142 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13143 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, PPC::sub_un, 13144 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, PPC::CRBITRCRegClassID, 13145 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, PPC::CRRCRegClassID, 13146 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::CRNOT, 13147 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // CRD 13148 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13149 GIR_EraseFromParent, /*InsnID*/0, 13150 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13151 // GIR_Coverage, 4287, 13152 GIR_Done, 13153 // Label 838: @32321 13154 GIM_Try, /*On fail goto*//*Label 839*/ 32376, // Rule ID 4303 // 13155 GIM_CheckFeatures, GIFBS_HasFPU, 13156 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 13157 // MIs[0] Operand 1 13158 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT, 13159 // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETOLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }) 13160 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 13161 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::XSCMPUQP, 13162 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13163 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 13164 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 13165 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13166 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 13167 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13168 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_lt, 13169 GIR_EraseFromParent, /*InsnID*/0, 13170 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 13171 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 13172 // GIR_Coverage, 4303, 13173 GIR_Done, 13174 // Label 839: @32376 13175 GIM_Try, /*On fail goto*//*Label 840*/ 32431, // Rule ID 4307 // 13176 GIM_CheckFeatures, GIFBS_HasFPU, 13177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 13178 // MIs[0] Operand 1 13179 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OGT, 13180 // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETOGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }) 13181 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 13182 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::XSCMPUQP, 13183 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13184 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 13185 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 13186 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13187 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 13188 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13189 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_gt, 13190 GIR_EraseFromParent, /*InsnID*/0, 13191 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 13192 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 13193 // GIR_Coverage, 4307, 13194 GIR_Done, 13195 // Label 840: @32431 13196 GIM_Try, /*On fail goto*//*Label 841*/ 32486, // Rule ID 4311 // 13197 GIM_CheckFeatures, GIFBS_HasFPU, 13198 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 13199 // MIs[0] Operand 1 13200 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ, 13201 // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETOEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }) 13202 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 13203 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::XSCMPUQP, 13204 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13205 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 13206 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 13207 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13208 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 13209 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13210 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_eq, 13211 GIR_EraseFromParent, /*InsnID*/0, 13212 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 13213 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 13214 // GIR_Coverage, 4311, 13215 GIR_Done, 13216 // Label 841: @32486 13217 GIM_Try, /*On fail goto*//*Label 842*/ 32541, // Rule ID 4315 // 13218 GIM_CheckFeatures, GIFBS_HasFPU, 13219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::CRRCRegClassID, 13220 // MIs[0] Operand 1 13221 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO, 13222 // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUO:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2), sub_un:{ *:[i32] }) 13223 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 13224 GIR_BuildMI, /*InsnID*/1, /*Opcode*/PPC::XSCMPUQP, 13225 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13226 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 13227 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 13228 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13229 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 13230 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13231 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, PPC::sub_un, 13232 GIR_EraseFromParent, /*InsnID*/0, 13233 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, PPC::CRBITRCRegClassID, 13234 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, PPC::CRRCRegClassID, 13235 // GIR_Coverage, 4315, 13236 GIR_Done, 13237 // Label 842: @32541 13238 GIM_Reject, 13239 // Label 834: @32542 13240 GIM_Reject, 13241 // Label 815: @32543 13242 GIM_Reject, 13243 // Label 811: @32544 13244 GIM_Reject, 13245 // Label 26: @32545 13246 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 848*/ 32786, 13247 /*GILLT_s32*//*Label 843*/ 32556, 13248 /*GILLT_s64*//*Label 844*/ 32630, 13249 /*GILLT_s128*//*Label 845*/ 32704, 13250 /*GILLT_v2s64*//*Label 846*/ 32732, 13251 /*GILLT_v4s32*//*Label 847*/ 32760, 13252 // Label 843: @32556 13253 GIM_Try, /*On fail goto*//*Label 849*/ 32629, 13254 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 13255 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13256 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 13257 GIM_Try, /*On fail goto*//*Label 850*/ 32585, // Rule ID 1035 // 13258 GIM_CheckFeatures, GIFBS_HasVSX, 13259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 13260 // (select:{ *:[f32] } i1:{ *:[i1] }:$cond, f32:{ *:[f32] }:$T, f32:{ *:[f32] }:$F) => (SELECT_VSSRC:{ *:[f32] } i1:{ *:[i1] }:$cond, f32:{ *:[f32] }:$T, f32:{ *:[f32] }:$F) 13261 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::SELECT_VSSRC, 13262 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13263 // GIR_Coverage, 1035, 13264 GIR_Done, 13265 // Label 850: @32585 13266 GIM_Try, /*On fail goto*//*Label 851*/ 32598, // Rule ID 5 // 13267 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 13268 // (select:{ *:[i32] } i1:{ *:[i1] }:$cond, i32:{ *:[i32] }:$T, i32:{ *:[i32] }:$F) => (SELECT_I4:{ *:[i32] } i1:{ *:[i1] }:$cond, i32:{ *:[i32] }:$T, i32:{ *:[i32] }:$F) 13269 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::SELECT_I4, 13270 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13271 // GIR_Coverage, 5, 13272 GIR_Done, 13273 // Label 851: @32598 13274 GIM_Try, /*On fail goto*//*Label 852*/ 32613, // Rule ID 7 // 13275 GIM_CheckFeatures, GIFBS_HasFPU, 13276 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 13277 // (select:{ *:[f32] } i1:{ *:[i1] }:$cond, f32:{ *:[f32] }:$T, f32:{ *:[f32] }:$F) => (SELECT_F4:{ *:[f32] } i1:{ *:[i1] }:$cond, f32:{ *:[f32] }:$T, f32:{ *:[f32] }:$F) 13278 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::SELECT_F4, 13279 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13280 // GIR_Coverage, 7, 13281 GIR_Done, 13282 // Label 852: @32613 13283 GIM_Try, /*On fail goto*//*Label 853*/ 32628, // Rule ID 602 // 13284 GIM_CheckFeatures, GIFBS_HasSPE, 13285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 13286 // (select:{ *:[f32] } i1:{ *:[i1] }:$cond, f32:{ *:[f32] }:$T, f32:{ *:[f32] }:$F) => (SELECT_SPE4:{ *:[f32] } i1:{ *:[i1] }:$cond, f32:{ *:[f32] }:$T, f32:{ *:[f32] }:$F) 13287 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::SELECT_SPE4, 13288 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13289 // GIR_Coverage, 602, 13290 GIR_Done, 13291 // Label 853: @32628 13292 GIM_Reject, 13293 // Label 849: @32629 13294 GIM_Reject, 13295 // Label 844: @32630 13296 GIM_Try, /*On fail goto*//*Label 854*/ 32703, 13297 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 13298 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13299 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 13300 GIM_Try, /*On fail goto*//*Label 855*/ 32659, // Rule ID 1034 // 13301 GIM_CheckFeatures, GIFBS_HasVSX, 13302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 13303 // (select:{ *:[f64] } i1:{ *:[i1] }:$cond, f64:{ *:[f64] }:$T, f64:{ *:[f64] }:$F) => (SELECT_VSFRC:{ *:[f64] } i1:{ *:[i1] }:$cond, f64:{ *:[f64] }:$T, f64:{ *:[f64] }:$F) 13304 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::SELECT_VSFRC, 13305 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13306 // GIR_Coverage, 1034, 13307 GIR_Done, 13308 // Label 855: @32659 13309 GIM_Try, /*On fail goto*//*Label 856*/ 32672, // Rule ID 6 // 13310 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 13311 // (select:{ *:[i64] } i1:{ *:[i1] }:$cond, i64:{ *:[i64] }:$T, i64:{ *:[i64] }:$F) => (SELECT_I8:{ *:[i64] } i1:{ *:[i1] }:$cond, i64:{ *:[i64] }:$T, i64:{ *:[i64] }:$F) 13312 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::SELECT_I8, 13313 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13314 // GIR_Coverage, 6, 13315 GIR_Done, 13316 // Label 856: @32672 13317 GIM_Try, /*On fail goto*//*Label 857*/ 32687, // Rule ID 8 // 13318 GIM_CheckFeatures, GIFBS_HasFPU, 13319 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 13320 // (select:{ *:[f64] } i1:{ *:[i1] }:$cond, f64:{ *:[f64] }:$T, f64:{ *:[f64] }:$F) => (SELECT_F8:{ *:[f64] } i1:{ *:[i1] }:$cond, f64:{ *:[f64] }:$T, f64:{ *:[f64] }:$F) 13321 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::SELECT_F8, 13322 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13323 // GIR_Coverage, 8, 13324 GIR_Done, 13325 // Label 857: @32687 13326 GIM_Try, /*On fail goto*//*Label 858*/ 32702, // Rule ID 603 // 13327 GIM_CheckFeatures, GIFBS_HasSPE, 13328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::SPERCRegClassID, 13329 // (select:{ *:[f64] } i1:{ *:[i1] }:$cond, f64:{ *:[f64] }:$T, f64:{ *:[f64] }:$F) => (SELECT_SPE:{ *:[f64] } i1:{ *:[i1] }:$cond, f64:{ *:[f64] }:$T, f64:{ *:[f64] }:$F) 13330 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::SELECT_SPE, 13331 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13332 // GIR_Coverage, 603, 13333 GIR_Done, 13334 // Label 858: @32702 13335 GIM_Reject, 13336 // Label 854: @32703 13337 GIM_Reject, 13338 // Label 845: @32704 13339 GIM_Try, /*On fail goto*//*Label 859*/ 32731, // Rule ID 9 // 13340 GIM_CheckFeatures, GIFBS_HasFPU, 13341 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 13342 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 13343 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s128, 13344 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 13345 // (select:{ *:[f128] } i1:{ *:[i1] }:$cond, f128:{ *:[f128] }:$T, f128:{ *:[f128] }:$F) => (SELECT_F16:{ *:[f128] } i1:{ *:[i1] }:$cond, f128:{ *:[f128] }:$T, f128:{ *:[f128] }:$F) 13346 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::SELECT_F16, 13347 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13348 // GIR_Coverage, 9, 13349 GIR_Done, 13350 // Label 859: @32731 13351 GIM_Reject, 13352 // Label 846: @32732 13353 GIM_Try, /*On fail goto*//*Label 860*/ 32759, // Rule ID 1033 // 13354 GIM_CheckFeatures, GIFBS_HasVSX, 13355 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 13356 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 13357 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 13358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 13359 // (select:{ *:[v2f64] } i1:{ *:[i1] }:$cond, v2f64:{ *:[v2f64] }:$T, v2f64:{ *:[v2f64] }:$F) => (SELECT_VSRC:{ *:[v2f64] } i1:{ *:[i1] }:$cond, v2f64:{ *:[v2f64] }:$T, v2f64:{ *:[v2f64] }:$F) 13360 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::SELECT_VSRC, 13361 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13362 // GIR_Coverage, 1033, 13363 GIR_Done, 13364 // Label 860: @32759 13365 GIM_Reject, 13366 // Label 847: @32760 13367 GIM_Try, /*On fail goto*//*Label 861*/ 32785, // Rule ID 10 // 13368 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 13369 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 13370 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 13371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 13372 // (select:{ *:[v4i32] } i1:{ *:[i1] }:$cond, v4i32:{ *:[v4i32] }:$T, v4i32:{ *:[v4i32] }:$F) => (SELECT_VRRC:{ *:[v4i32] } i1:{ *:[i1] }:$cond, v4i32:{ *:[v4i32] }:$T, v4i32:{ *:[v4i32] }:$F) 13373 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::SELECT_VRRC, 13374 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13375 // GIR_Coverage, 10, 13376 GIR_Done, 13377 // Label 861: @32785 13378 GIM_Reject, 13379 // Label 848: @32786 13380 GIM_Reject, 13381 // Label 27: @32787 13382 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 866*/ 32890, 13383 /*GILLT_s32*//*Label 862*/ 32798, 13384 /*GILLT_s64*//*Label 863*/ 32820, 0, 13385 /*GILLT_v2s64*//*Label 864*/ 32842, 13386 /*GILLT_v4s32*//*Label 865*/ 32866, 13387 // Label 862: @32798 13388 GIM_Try, /*On fail goto*//*Label 867*/ 32819, // Rule ID 204 // 13389 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13390 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13391 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 13392 // (mulhu:{ *:[i32] } i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) => (MULHWU:{ *:[i32] } i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) 13393 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::MULHWU, 13394 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13395 // GIR_Coverage, 204, 13396 GIR_Done, 13397 // Label 867: @32819 13398 GIM_Reject, 13399 // Label 863: @32820 13400 GIM_Try, /*On fail goto*//*Label 868*/ 32841, // Rule ID 669 // 13401 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 13402 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 13404 // (mulhu:{ *:[i64] } i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) => (MULHDU:{ *:[i64] } i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) 13405 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::MULHDU, 13406 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13407 // GIR_Coverage, 669, 13408 GIR_Done, 13409 // Label 868: @32841 13410 GIM_Reject, 13411 // Label 864: @32842 13412 GIM_Try, /*On fail goto*//*Label 869*/ 32865, // Rule ID 1106 // 13413 GIM_CheckFeatures, GIFBS_IsISA3_1, 13414 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 13415 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 13416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 13417 // (mulhu:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VMULHUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 13418 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VMULHUD, 13419 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13420 // GIR_Coverage, 1106, 13421 GIR_Done, 13422 // Label 869: @32865 13423 GIM_Reject, 13424 // Label 865: @32866 13425 GIM_Try, /*On fail goto*//*Label 870*/ 32889, // Rule ID 1104 // 13426 GIM_CheckFeatures, GIFBS_IsISA3_1, 13427 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 13428 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 13429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 13430 // (mulhu:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VMULHUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 13431 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VMULHUW, 13432 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13433 // GIR_Coverage, 1104, 13434 GIR_Done, 13435 // Label 870: @32889 13436 GIM_Reject, 13437 // Label 866: @32890 13438 GIM_Reject, 13439 // Label 28: @32891 13440 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 875*/ 32994, 13441 /*GILLT_s32*//*Label 871*/ 32902, 13442 /*GILLT_s64*//*Label 872*/ 32924, 0, 13443 /*GILLT_v2s64*//*Label 873*/ 32946, 13444 /*GILLT_v4s32*//*Label 874*/ 32970, 13445 // Label 871: @32902 13446 GIM_Try, /*On fail goto*//*Label 876*/ 32923, // Rule ID 203 // 13447 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13448 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 13450 // (mulhs:{ *:[i32] } i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) => (MULHW:{ *:[i32] } i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) 13451 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::MULHW, 13452 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13453 // GIR_Coverage, 203, 13454 GIR_Done, 13455 // Label 876: @32923 13456 GIM_Reject, 13457 // Label 872: @32924 13458 GIM_Try, /*On fail goto*//*Label 877*/ 32945, // Rule ID 668 // 13459 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 13460 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13461 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 13462 // (mulhs:{ *:[i64] } i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) => (MULHD:{ *:[i64] } i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) 13463 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::MULHD, 13464 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13465 // GIR_Coverage, 668, 13466 GIR_Done, 13467 // Label 877: @32945 13468 GIM_Reject, 13469 // Label 873: @32946 13470 GIM_Try, /*On fail goto*//*Label 878*/ 32969, // Rule ID 1105 // 13471 GIM_CheckFeatures, GIFBS_IsISA3_1, 13472 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 13473 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 13474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 13475 // (mulhs:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VMULHSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) 13476 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VMULHSD, 13477 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13478 // GIR_Coverage, 1105, 13479 GIR_Done, 13480 // Label 878: @32969 13481 GIM_Reject, 13482 // Label 874: @32970 13483 GIM_Try, /*On fail goto*//*Label 879*/ 32993, // Rule ID 1103 // 13484 GIM_CheckFeatures, GIFBS_IsISA3_1, 13485 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 13486 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 13487 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 13488 // (mulhs:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VMULHSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) 13489 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VMULHSW, 13490 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13491 // GIR_Coverage, 1103, 13492 GIR_Done, 13493 // Label 879: @32993 13494 GIM_Reject, 13495 // Label 875: @32994 13496 GIM_Reject, 13497 // Label 29: @32995 13498 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 885*/ 33225, 13499 /*GILLT_s32*//*Label 880*/ 33006, 13500 /*GILLT_s64*//*Label 881*/ 33066, 13501 /*GILLT_s128*//*Label 882*/ 33129, 13502 /*GILLT_v2s64*//*Label 883*/ 33153, 13503 /*GILLT_v4s32*//*Label 884*/ 33180, 13504 // Label 880: @33006 13505 GIM_Try, /*On fail goto*//*Label 886*/ 33065, 13506 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13507 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13508 GIM_Try, /*On fail goto*//*Label 887*/ 33031, // Rule ID 941 // 13509 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 13510 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSSRCRegClassID, 13511 // (fadd:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSADDSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) 13512 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSADDSP, 13513 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13514 // GIR_Coverage, 941, 13515 GIR_Done, 13516 // Label 887: @33031 13517 GIM_Try, /*On fail goto*//*Label 888*/ 33049, // Rule ID 236 // 13518 GIM_CheckFeatures, GIFBS_HasFPU, 13519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 13520 // (fadd:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) => (FADDS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) 13521 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FADDS, 13522 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 13523 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13524 // GIR_Coverage, 236, 13525 GIR_Done, 13526 // Label 888: @33049 13527 GIM_Try, /*On fail goto*//*Label 889*/ 33064, // Rule ID 575 // 13528 GIM_CheckFeatures, GIFBS_HasSPE, 13529 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 13530 // (fadd:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSADD:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) 13531 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFSADD, 13532 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13533 // GIR_Coverage, 575, 13534 GIR_Done, 13535 // Label 889: @33064 13536 GIM_Reject, 13537 // Label 886: @33065 13538 GIM_Reject, 13539 // Label 881: @33066 13540 GIM_Try, /*On fail goto*//*Label 890*/ 33128, 13541 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 13542 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13543 GIM_Try, /*On fail goto*//*Label 891*/ 33094, // Rule ID 758 // 13544 GIM_CheckFeatures, GIFBS_HasVSX, 13545 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 13546 // (fadd:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSADDDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) 13547 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSADDDP, 13548 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 13549 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13550 // GIR_Coverage, 758, 13551 GIR_Done, 13552 // Label 891: @33094 13553 GIM_Try, /*On fail goto*//*Label 892*/ 33112, // Rule ID 234 // 13554 GIM_CheckFeatures, GIFBS_HasFPU, 13555 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 13556 // (fadd:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) => (FADD:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) 13557 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FADD, 13558 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 13559 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13560 // GIR_Coverage, 234, 13561 GIR_Done, 13562 // Label 892: @33112 13563 GIM_Try, /*On fail goto*//*Label 893*/ 33127, // Rule ID 554 // 13564 GIM_CheckFeatures, GIFBS_HasSPE, 13565 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::SPERCRegClassID, 13566 // (fadd:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDADD:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) 13567 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFDADD, 13568 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13569 // GIR_Coverage, 554, 13570 GIR_Done, 13571 // Label 893: @33127 13572 GIM_Reject, 13573 // Label 890: @33128 13574 GIM_Reject, 13575 // Label 882: @33129 13576 GIM_Try, /*On fail goto*//*Label 894*/ 33152, // Rule ID 976 // 13577 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 13578 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 13579 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 13580 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 13581 // (fadd:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) => (XSADDQP:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 13582 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSADDQP, 13583 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13584 // GIR_Coverage, 976, 13585 GIR_Done, 13586 // Label 894: @33152 13587 GIM_Reject, 13588 // Label 883: @33153 13589 GIM_Try, /*On fail goto*//*Label 895*/ 33179, // Rule ID 762 // 13590 GIM_CheckFeatures, GIFBS_HasVSX, 13591 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 13592 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 13593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 13594 // (fadd:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVADDDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) 13595 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVADDDP, 13596 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 13597 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13598 // GIR_Coverage, 762, 13599 GIR_Done, 13600 // Label 895: @33179 13601 GIM_Reject, 13602 // Label 884: @33180 13603 GIM_Try, /*On fail goto*//*Label 896*/ 33224, 13604 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 13605 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 13606 GIM_Try, /*On fail goto*//*Label 897*/ 33208, // Rule ID 764 // 13607 GIM_CheckFeatures, GIFBS_HasVSX, 13608 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 13609 // (fadd:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVADDSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) 13610 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVADDSP, 13611 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 13612 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13613 // GIR_Coverage, 764, 13614 GIR_Done, 13615 // Label 897: @33208 13616 GIM_Try, /*On fail goto*//*Label 898*/ 33223, // Rule ID 296 // 13617 GIM_CheckFeatures, GIFBS_HasAltivec, 13618 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 13619 // (fadd:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vA, v4f32:{ *:[v4f32] }:$vB) => (VADDFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vA, v4f32:{ *:[v4f32] }:$vB) 13620 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VADDFP, 13621 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13622 // GIR_Coverage, 296, 13623 GIR_Done, 13624 // Label 898: @33223 13625 GIM_Reject, 13626 // Label 896: @33224 13627 GIM_Reject, 13628 // Label 885: @33225 13629 GIM_Reject, 13630 // Label 30: @33226 13631 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 904*/ 33456, 13632 /*GILLT_s32*//*Label 899*/ 33237, 13633 /*GILLT_s64*//*Label 900*/ 33297, 13634 /*GILLT_s128*//*Label 901*/ 33360, 13635 /*GILLT_v2s64*//*Label 902*/ 33384, 13636 /*GILLT_v4s32*//*Label 903*/ 33411, 13637 // Label 899: @33237 13638 GIM_Try, /*On fail goto*//*Label 905*/ 33296, 13639 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13640 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13641 GIM_Try, /*On fail goto*//*Label 906*/ 33262, // Rule ID 945 // 13642 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 13643 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSSRCRegClassID, 13644 // (fsub:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSSUBSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) 13645 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSSUBSP, 13646 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13647 // GIR_Coverage, 945, 13648 GIR_Done, 13649 // Label 906: @33262 13650 GIM_Try, /*On fail goto*//*Label 907*/ 33280, // Rule ID 248 // 13651 GIM_CheckFeatures, GIFBS_HasFPU, 13652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 13653 // (fsub:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) => (FSUBS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) 13654 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FSUBS, 13655 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 13656 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13657 // GIR_Coverage, 248, 13658 GIR_Done, 13659 // Label 907: @33280 13660 GIM_Try, /*On fail goto*//*Label 908*/ 33295, // Rule ID 593 // 13661 GIM_CheckFeatures, GIFBS_HasSPE, 13662 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 13663 // (fsub:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSSUB:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) 13664 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFSSUB, 13665 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13666 // GIR_Coverage, 593, 13667 GIR_Done, 13668 // Label 908: @33295 13669 GIM_Reject, 13670 // Label 905: @33296 13671 GIM_Reject, 13672 // Label 900: @33297 13673 GIM_Try, /*On fail goto*//*Label 909*/ 33359, 13674 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 13675 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13676 GIM_Try, /*On fail goto*//*Label 910*/ 33325, // Rule ID 770 // 13677 GIM_CheckFeatures, GIFBS_HasVSX, 13678 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 13679 // (fsub:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSSUBDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) 13680 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSSUBDP, 13681 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 13682 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13683 // GIR_Coverage, 770, 13684 GIR_Done, 13685 // Label 910: @33325 13686 GIM_Try, /*On fail goto*//*Label 911*/ 33343, // Rule ID 246 // 13687 GIM_CheckFeatures, GIFBS_HasFPU, 13688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 13689 // (fsub:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) => (FSUB:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) 13690 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FSUB, 13691 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 13692 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13693 // GIR_Coverage, 246, 13694 GIR_Done, 13695 // Label 911: @33343 13696 GIM_Try, /*On fail goto*//*Label 912*/ 33358, // Rule ID 572 // 13697 GIM_CheckFeatures, GIFBS_HasSPE, 13698 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::SPERCRegClassID, 13699 // (fsub:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDSUB:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) 13700 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFDSUB, 13701 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13702 // GIR_Coverage, 572, 13703 GIR_Done, 13704 // Label 912: @33358 13705 GIM_Reject, 13706 // Label 909: @33359 13707 GIM_Reject, 13708 // Label 901: @33360 13709 GIM_Try, /*On fail goto*//*Label 913*/ 33383, // Rule ID 980 // 13710 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 13711 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 13712 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 13713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 13714 // (fsub:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) => (XSSUBQP:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 13715 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSSUBQP, 13716 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13717 // GIR_Coverage, 980, 13718 GIR_Done, 13719 // Label 913: @33383 13720 GIM_Reject, 13721 // Label 902: @33384 13722 GIM_Try, /*On fail goto*//*Label 914*/ 33410, // Rule ID 772 // 13723 GIM_CheckFeatures, GIFBS_HasVSX, 13724 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 13725 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 13726 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 13727 // (fsub:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVSUBDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) 13728 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVSUBDP, 13729 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 13730 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13731 // GIR_Coverage, 772, 13732 GIR_Done, 13733 // Label 914: @33410 13734 GIM_Reject, 13735 // Label 903: @33411 13736 GIM_Try, /*On fail goto*//*Label 915*/ 33455, 13737 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 13738 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 13739 GIM_Try, /*On fail goto*//*Label 916*/ 33439, // Rule ID 774 // 13740 GIM_CheckFeatures, GIFBS_HasVSX, 13741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 13742 // (fsub:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVSUBSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) 13743 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVSUBSP, 13744 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 13745 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13746 // GIR_Coverage, 774, 13747 GIR_Done, 13748 // Label 916: @33439 13749 GIM_Try, /*On fail goto*//*Label 917*/ 33454, // Rule ID 366 // 13750 GIM_CheckFeatures, GIFBS_HasAltivec, 13751 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 13752 // (fsub:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vA, v4f32:{ *:[v4f32] }:$vB) => (VSUBFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vA, v4f32:{ *:[v4f32] }:$vB) 13753 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VSUBFP, 13754 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13755 // GIR_Coverage, 366, 13756 GIR_Done, 13757 // Label 917: @33454 13758 GIM_Reject, 13759 // Label 915: @33455 13760 GIM_Reject, 13761 // Label 904: @33456 13762 GIM_Reject, 13763 // Label 31: @33457 13764 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 923*/ 33669, 13765 /*GILLT_s32*//*Label 918*/ 33468, 13766 /*GILLT_s64*//*Label 919*/ 33528, 13767 /*GILLT_s128*//*Label 920*/ 33591, 13768 /*GILLT_v2s64*//*Label 921*/ 33615, 13769 /*GILLT_v4s32*//*Label 922*/ 33642, 13770 // Label 918: @33468 13771 GIM_Try, /*On fail goto*//*Label 924*/ 33527, 13772 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13773 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13774 GIM_Try, /*On fail goto*//*Label 925*/ 33493, // Rule ID 943 // 13775 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 13776 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSSRCRegClassID, 13777 // (fmul:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSMULSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) 13778 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSMULSP, 13779 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13780 // GIR_Coverage, 943, 13781 GIR_Done, 13782 // Label 925: @33493 13783 GIM_Try, /*On fail goto*//*Label 926*/ 33511, // Rule ID 244 // 13784 GIM_CheckFeatures, GIFBS_HasFPU, 13785 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 13786 // (fmul:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC) => (FMULS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC) 13787 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FMULS, 13788 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 13789 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13790 // GIR_Coverage, 244, 13791 GIR_Done, 13792 // Label 926: @33511 13793 GIM_Try, /*On fail goto*//*Label 927*/ 33526, // Rule ID 589 // 13794 GIM_CheckFeatures, GIFBS_HasSPE, 13795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 13796 // (fmul:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSMUL:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) 13797 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFSMUL, 13798 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13799 // GIR_Coverage, 589, 13800 GIR_Done, 13801 // Label 927: @33526 13802 GIM_Reject, 13803 // Label 924: @33527 13804 GIM_Reject, 13805 // Label 919: @33528 13806 GIM_Try, /*On fail goto*//*Label 928*/ 33590, 13807 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 13808 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13809 GIM_Try, /*On fail goto*//*Label 929*/ 33556, // Rule ID 760 // 13810 GIM_CheckFeatures, GIFBS_HasVSX, 13811 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 13812 // (fmul:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSMULDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) 13813 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSMULDP, 13814 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 13815 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13816 // GIR_Coverage, 760, 13817 GIR_Done, 13818 // Label 929: @33556 13819 GIM_Try, /*On fail goto*//*Label 930*/ 33574, // Rule ID 242 // 13820 GIM_CheckFeatures, GIFBS_HasFPU, 13821 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 13822 // (fmul:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC) => (FMUL:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC) 13823 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FMUL, 13824 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 13825 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13826 // GIR_Coverage, 242, 13827 GIR_Done, 13828 // Label 930: @33574 13829 GIM_Try, /*On fail goto*//*Label 931*/ 33589, // Rule ID 568 // 13830 GIM_CheckFeatures, GIFBS_HasSPE, 13831 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::SPERCRegClassID, 13832 // (fmul:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDMUL:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) 13833 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFDMUL, 13834 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13835 // GIR_Coverage, 568, 13836 GIR_Done, 13837 // Label 931: @33589 13838 GIM_Reject, 13839 // Label 928: @33590 13840 GIM_Reject, 13841 // Label 920: @33591 13842 GIM_Try, /*On fail goto*//*Label 932*/ 33614, // Rule ID 978 // 13843 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 13844 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 13845 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 13846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 13847 // (fmul:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) => (XSMULQP:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 13848 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSMULQP, 13849 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13850 // GIR_Coverage, 978, 13851 GIR_Done, 13852 // Label 932: @33614 13853 GIM_Reject, 13854 // Label 921: @33615 13855 GIM_Try, /*On fail goto*//*Label 933*/ 33641, // Rule ID 766 // 13856 GIM_CheckFeatures, GIFBS_HasVSX, 13857 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 13858 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 13859 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 13860 // (fmul:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVMULDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) 13861 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVMULDP, 13862 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 13863 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13864 // GIR_Coverage, 766, 13865 GIR_Done, 13866 // Label 933: @33641 13867 GIM_Reject, 13868 // Label 922: @33642 13869 GIM_Try, /*On fail goto*//*Label 934*/ 33668, // Rule ID 768 // 13870 GIM_CheckFeatures, GIFBS_HasVSX, 13871 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 13872 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 13873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 13874 // (fmul:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVMULSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) 13875 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVMULSP, 13876 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 13877 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13878 // GIR_Coverage, 768, 13879 GIR_Done, 13880 // Label 934: @33668 13881 GIM_Reject, 13882 // Label 923: @33669 13883 GIM_Reject, 13884 // Label 32: @33670 13885 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 940*/ 34279, 13886 /*GILLT_s32*//*Label 935*/ 33681, 13887 /*GILLT_s64*//*Label 936*/ 33837, 13888 /*GILLT_s128*//*Label 937*/ 33993, 13889 /*GILLT_v2s64*//*Label 938*/ 34082, 13890 /*GILLT_v4s32*//*Label 939*/ 34171, 13891 // Label 935: @33681 13892 GIM_Try, /*On fail goto*//*Label 941*/ 33836, 13893 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13894 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13895 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 13896 GIM_Try, /*On fail goto*//*Label 942*/ 33740, // Rule ID 957 // 13897 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 13898 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSSRCRegClassID, 13899 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 13900 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 13901 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 13902 GIM_CheckIsSafeToFold, /*InsnID*/1, 13903 // (fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, (fneg:{ *:[f32] } f32:{ *:[f32] }:$XTi)) => (XSMSUBASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) 13904 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSMSUBASP, 13905 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 13906 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi 13907 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // XA 13908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 13909 GIR_EraseFromParent, /*InsnID*/0, 13910 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13911 // GIR_Coverage, 957, 13912 GIR_Done, 13913 // Label 942: @33740 13914 GIM_Try, /*On fail goto*//*Label 943*/ 33772, // Rule ID 955 // 13915 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 13916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSSRCRegClassID, 13917 // (fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, f32:{ *:[f32] }:$XTi) => (XSMADDASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) 13918 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSMADDASP, 13919 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 13920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XTi 13921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // XA 13922 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 13923 GIR_EraseFromParent, /*InsnID*/0, 13924 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13925 // GIR_Coverage, 955, 13926 GIR_Done, 13927 // Label 943: @33772 13928 GIM_Try, /*On fail goto*//*Label 944*/ 33817, // Rule ID 222 // 13929 GIM_CheckFeatures, GIFBS_HasFPU, 13930 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 13931 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 13932 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 13933 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 13934 GIM_CheckIsSafeToFold, /*InsnID*/1, 13935 // (fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, (fneg:{ *:[f32] } f32:{ *:[f32] }:$FRB)) => (FMSUBS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB) 13936 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::FMSUBS, 13937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // FRT 13938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // FRA 13939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // FRC 13940 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRB 13941 GIR_EraseFromParent, /*InsnID*/0, 13942 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13943 // GIR_Coverage, 222, 13944 GIR_Done, 13945 // Label 944: @33817 13946 GIM_Try, /*On fail goto*//*Label 945*/ 33835, // Rule ID 218 // 13947 GIM_CheckFeatures, GIFBS_HasFPU, 13948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 13949 // (fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB) => (FMADDS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB) 13950 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FMADDS, 13951 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 13952 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13953 // GIR_Coverage, 218, 13954 GIR_Done, 13955 // Label 945: @33835 13956 GIM_Reject, 13957 // Label 941: @33836 13958 GIM_Reject, 13959 // Label 936: @33837 13960 GIM_Try, /*On fail goto*//*Label 946*/ 33992, 13961 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 13962 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13963 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 13964 GIM_Try, /*On fail goto*//*Label 947*/ 33896, // Rule ID 778 // 13965 GIM_CheckFeatures, GIFBS_HasVSX, 13966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 13967 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 13968 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 13969 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 13970 GIM_CheckIsSafeToFold, /*InsnID*/1, 13971 // (fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, (fneg:{ *:[f64] } f64:{ *:[f64] }:$XTi)) => (XSMSUBADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) 13972 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSMSUBADP, 13973 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 13974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi 13975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // XA 13976 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 13977 GIR_EraseFromParent, /*InsnID*/0, 13978 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13979 // GIR_Coverage, 778, 13980 GIR_Done, 13981 // Label 947: @33896 13982 GIM_Try, /*On fail goto*//*Label 948*/ 33928, // Rule ID 776 // 13983 GIM_CheckFeatures, GIFBS_HasVSX, 13984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 13985 // (fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, f64:{ *:[f64] }:$XTi) => (XSMADDADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) 13986 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSMADDADP, 13987 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 13988 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XTi 13989 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // XA 13990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 13991 GIR_EraseFromParent, /*InsnID*/0, 13992 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13993 // GIR_Coverage, 776, 13994 GIR_Done, 13995 // Label 948: @33928 13996 GIM_Try, /*On fail goto*//*Label 949*/ 33973, // Rule ID 220 // 13997 GIM_CheckFeatures, GIFBS_HasFPU, 13998 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 13999 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 14000 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 14001 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 14002 GIM_CheckIsSafeToFold, /*InsnID*/1, 14003 // (fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, (fneg:{ *:[f64] } f64:{ *:[f64] }:$FRB)) => (FMSUB:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB) 14004 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::FMSUB, 14005 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // FRT 14006 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // FRA 14007 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // FRC 14008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRB 14009 GIR_EraseFromParent, /*InsnID*/0, 14010 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14011 // GIR_Coverage, 220, 14012 GIR_Done, 14013 // Label 949: @33973 14014 GIM_Try, /*On fail goto*//*Label 950*/ 33991, // Rule ID 216 // 14015 GIM_CheckFeatures, GIFBS_HasFPU, 14016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 14017 // (fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB) => (FMADD:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB) 14018 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FMADD, 14019 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 14020 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14021 // GIR_Coverage, 216, 14022 GIR_Done, 14023 // Label 950: @33991 14024 GIM_Reject, 14025 // Label 946: @33992 14026 GIM_Reject, 14027 // Label 937: @33993 14028 GIM_Try, /*On fail goto*//*Label 951*/ 34081, 14029 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 14030 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 14031 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s128, 14032 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 14033 GIM_Try, /*On fail goto*//*Label 952*/ 34052, // Rule ID 988 // 14034 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 14035 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 14036 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 14037 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128, 14038 GIM_CheckIsSafeToFold, /*InsnID*/1, 14039 // (fma:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB, (fneg:{ *:[f128] } f128:{ *:[f128] }:$vTi)) => (XSMSUBQP:{ *:[f128] } f128:{ *:[f128] }:$vTi, f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 14040 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSMSUBQP, 14041 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 14042 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vTi 14043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vA 14044 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 14045 GIR_EraseFromParent, /*InsnID*/0, 14046 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14047 // GIR_Coverage, 988, 14048 GIR_Done, 14049 // Label 952: @34052 14050 GIM_Try, /*On fail goto*//*Label 953*/ 34080, // Rule ID 986 // 14051 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 14052 // (fma:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB, f128:{ *:[f128] }:$vTi) => (XSMADDQP:{ *:[f128] } f128:{ *:[f128] }:$vTi, f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 14053 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSMADDQP, 14054 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 14055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vTi 14056 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vA 14057 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 14058 GIR_EraseFromParent, /*InsnID*/0, 14059 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14060 // GIR_Coverage, 986, 14061 GIR_Done, 14062 // Label 953: @34080 14063 GIM_Reject, 14064 // Label 951: @34081 14065 GIM_Reject, 14066 // Label 938: @34082 14067 GIM_Try, /*On fail goto*//*Label 954*/ 34170, 14068 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 14069 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 14070 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 14071 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 14072 GIM_Try, /*On fail goto*//*Label 955*/ 34141, // Rule ID 788 // 14073 GIM_CheckFeatures, GIFBS_HasVSX, 14074 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 14075 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 14076 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, 14077 GIM_CheckIsSafeToFold, /*InsnID*/1, 14078 // (fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, (fneg:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi)) => (XVMSUBADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) 14079 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVMSUBADP, 14080 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 14081 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi 14082 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // XA 14083 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 14084 GIR_EraseFromParent, /*InsnID*/0, 14085 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14086 // GIR_Coverage, 788, 14087 GIR_Done, 14088 // Label 955: @34141 14089 GIM_Try, /*On fail goto*//*Label 956*/ 34169, // Rule ID 784 // 14090 GIM_CheckFeatures, GIFBS_HasVSX, 14091 // (fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, v2f64:{ *:[v2f64] }:$XTi) => (XVMADDADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) 14092 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVMADDADP, 14093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 14094 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XTi 14095 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // XA 14096 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 14097 GIR_EraseFromParent, /*InsnID*/0, 14098 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14099 // GIR_Coverage, 784, 14100 GIR_Done, 14101 // Label 956: @34169 14102 GIM_Reject, 14103 // Label 954: @34170 14104 GIM_Reject, 14105 // Label 939: @34171 14106 GIM_Try, /*On fail goto*//*Label 957*/ 34278, 14107 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 14108 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 14109 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 14110 GIM_Try, /*On fail goto*//*Label 958*/ 34230, // Rule ID 790 // 14111 GIM_CheckFeatures, GIFBS_HasVSX, 14112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 14113 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 14114 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 14115 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 14116 GIM_CheckIsSafeToFold, /*InsnID*/1, 14117 // (fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB, (fneg:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi)) => (XVMSUBASP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) 14118 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVMSUBASP, 14119 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 14120 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi 14121 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // XA 14122 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 14123 GIR_EraseFromParent, /*InsnID*/0, 14124 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14125 // GIR_Coverage, 790, 14126 GIR_Done, 14127 // Label 958: @34230 14128 GIM_Try, /*On fail goto*//*Label 959*/ 34262, // Rule ID 786 // 14129 GIM_CheckFeatures, GIFBS_HasVSX, 14130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 14131 // (fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB, v4f32:{ *:[v4f32] }:$XTi) => (XVMADDASP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) 14132 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVMADDASP, 14133 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 14134 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XTi 14135 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // XA 14136 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 14137 GIR_EraseFromParent, /*InsnID*/0, 14138 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14139 // GIR_Coverage, 786, 14140 GIR_Done, 14141 // Label 959: @34262 14142 GIM_Try, /*On fail goto*//*Label 960*/ 34277, // Rule ID 288 // 14143 GIM_CheckFeatures, GIFBS_HasAltivec, 14144 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 14145 // (fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vA, v4f32:{ *:[v4f32] }:$vC, v4f32:{ *:[v4f32] }:$vB) => (VMADDFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vA, v4f32:{ *:[v4f32] }:$vC, v4f32:{ *:[v4f32] }:$vB) 14146 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VMADDFP, 14147 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14148 // GIR_Coverage, 288, 14149 GIR_Done, 14150 // Label 960: @34277 14151 GIM_Reject, 14152 // Label 957: @34278 14153 GIM_Reject, 14154 // Label 940: @34279 14155 GIM_Reject, 14156 // Label 33: @34280 14157 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 966*/ 34492, 14158 /*GILLT_s32*//*Label 961*/ 34291, 14159 /*GILLT_s64*//*Label 962*/ 34351, 14160 /*GILLT_s128*//*Label 963*/ 34414, 14161 /*GILLT_v2s64*//*Label 964*/ 34438, 14162 /*GILLT_v4s32*//*Label 965*/ 34465, 14163 // Label 961: @34291 14164 GIM_Try, /*On fail goto*//*Label 967*/ 34350, 14165 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14166 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 14167 GIM_Try, /*On fail goto*//*Label 968*/ 34316, // Rule ID 947 // 14168 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 14169 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSSRCRegClassID, 14170 // (fdiv:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSDIVSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) 14171 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSDIVSP, 14172 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14173 // GIR_Coverage, 947, 14174 GIR_Done, 14175 // Label 968: @34316 14176 GIM_Try, /*On fail goto*//*Label 969*/ 34334, // Rule ID 240 // 14177 GIM_CheckFeatures, GIFBS_HasFPU, 14178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 14179 // (fdiv:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) => (FDIVS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) 14180 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FDIVS, 14181 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 14182 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14183 // GIR_Coverage, 240, 14184 GIR_Done, 14185 // Label 969: @34334 14186 GIM_Try, /*On fail goto*//*Label 970*/ 34349, // Rule ID 587 // 14187 GIM_CheckFeatures, GIFBS_HasSPE, 14188 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 14189 // (fdiv:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSDIV:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) 14190 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFSDIV, 14191 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14192 // GIR_Coverage, 587, 14193 GIR_Done, 14194 // Label 970: @34349 14195 GIM_Reject, 14196 // Label 967: @34350 14197 GIM_Reject, 14198 // Label 962: @34351 14199 GIM_Try, /*On fail goto*//*Label 971*/ 34413, 14200 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14201 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 14202 GIM_Try, /*On fail goto*//*Label 972*/ 34379, // Rule ID 799 // 14203 GIM_CheckFeatures, GIFBS_HasVSX, 14204 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 14205 // (fdiv:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSDIVDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) 14206 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSDIVDP, 14207 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 14208 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14209 // GIR_Coverage, 799, 14210 GIR_Done, 14211 // Label 972: @34379 14212 GIM_Try, /*On fail goto*//*Label 973*/ 34397, // Rule ID 238 // 14213 GIM_CheckFeatures, GIFBS_HasFPU, 14214 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 14215 // (fdiv:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) => (FDIV:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) 14216 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FDIV, 14217 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 14218 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14219 // GIR_Coverage, 238, 14220 GIR_Done, 14221 // Label 973: @34397 14222 GIM_Try, /*On fail goto*//*Label 974*/ 34412, // Rule ID 566 // 14223 GIM_CheckFeatures, GIFBS_HasSPE, 14224 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::SPERCRegClassID, 14225 // (fdiv:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDDIV:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) 14226 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFDDIV, 14227 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14228 // GIR_Coverage, 566, 14229 GIR_Done, 14230 // Label 974: @34412 14231 GIM_Reject, 14232 // Label 971: @34413 14233 GIM_Reject, 14234 // Label 963: @34414 14235 GIM_Try, /*On fail goto*//*Label 975*/ 34437, // Rule ID 982 // 14236 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 14237 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 14238 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 14239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 14240 // (fdiv:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) => (XSDIVQP:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 14241 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSDIVQP, 14242 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14243 // GIR_Coverage, 982, 14244 GIR_Done, 14245 // Label 975: @34437 14246 GIM_Reject, 14247 // Label 964: @34438 14248 GIM_Try, /*On fail goto*//*Label 976*/ 34464, // Rule ID 808 // 14249 GIM_CheckFeatures, GIFBS_HasVSX, 14250 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 14251 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 14252 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 14253 // (fdiv:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVDIVDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) 14254 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVDIVDP, 14255 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 14256 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14257 // GIR_Coverage, 808, 14258 GIR_Done, 14259 // Label 976: @34464 14260 GIM_Reject, 14261 // Label 965: @34465 14262 GIM_Try, /*On fail goto*//*Label 977*/ 34491, // Rule ID 810 // 14263 GIM_CheckFeatures, GIFBS_HasVSX, 14264 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 14265 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 14266 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 14267 // (fdiv:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVDIVSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) 14268 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVDIVSP, 14269 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 14270 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14271 // GIR_Coverage, 810, 14272 GIR_Done, 14273 // Label 977: @34491 14274 GIM_Reject, 14275 // Label 966: @34492 14276 GIM_Reject, 14277 // Label 34: @34493 14278 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 983*/ 36770, 14279 /*GILLT_s32*//*Label 978*/ 34504, 14280 /*GILLT_s64*//*Label 979*/ 35129, 14281 /*GILLT_s128*//*Label 980*/ 35772, 14282 /*GILLT_v2s64*//*Label 981*/ 36175, 14283 /*GILLT_v4s32*//*Label 982*/ 36456, 14284 // Label 978: @34504 14285 GIM_Try, /*On fail goto*//*Label 984*/ 35128, 14286 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14287 GIM_Try, /*On fail goto*//*Label 985*/ 34576, // Rule ID 961 // 14288 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 14289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSSRCRegClassID, 14290 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14291 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, 14292 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 14293 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 14294 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 14295 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] 14296 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 14297 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 14298 GIM_CheckIsSafeToFold, /*InsnID*/1, 14299 GIM_CheckIsSafeToFold, /*InsnID*/2, 14300 // (fneg:{ *:[f32] } (fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, (fneg:{ *:[f32] } f32:{ *:[f32] }:$XTi))) => (XSNMSUBASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) 14301 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSNMSUBASP, 14302 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 14303 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi 14304 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA 14305 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB 14306 GIR_EraseFromParent, /*InsnID*/0, 14307 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14308 // GIR_Coverage, 961, 14309 GIR_Done, 14310 // Label 985: @34576 14311 GIM_Try, /*On fail goto*//*Label 986*/ 34642, // Rule ID 960 // 14312 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 14313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSSRCRegClassID, 14314 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14315 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_STRICT_FMA, 14316 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 14317 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 14318 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 14319 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] 14320 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 14321 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 14322 GIM_CheckIsSafeToFold, /*InsnID*/1, 14323 GIM_CheckIsSafeToFold, /*InsnID*/2, 14324 // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, (fneg:{ *:[f32] } f32:{ *:[f32] }:$XTi))) => (XSNMSUBASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) 14325 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSNMSUBASP, 14326 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 14327 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi 14328 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA 14329 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB 14330 GIR_EraseFromParent, /*InsnID*/0, 14331 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14332 // GIR_Coverage, 960, 14333 GIR_Done, 14334 // Label 986: @34642 14335 GIM_Try, /*On fail goto*//*Label 987*/ 34695, // Rule ID 959 // 14336 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 14337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSSRCRegClassID, 14338 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14339 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, 14340 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 14341 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 14342 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 14343 GIM_CheckIsSafeToFold, /*InsnID*/1, 14344 // (fneg:{ *:[f32] } (fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, f32:{ *:[f32] }:$XTi)) => (XSNMADDASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) 14345 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSNMADDASP, 14346 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 14347 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // XTi 14348 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA 14349 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB 14350 GIR_EraseFromParent, /*InsnID*/0, 14351 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14352 // GIR_Coverage, 959, 14353 GIR_Done, 14354 // Label 987: @34695 14355 GIM_Try, /*On fail goto*//*Label 988*/ 34748, // Rule ID 958 // 14356 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 14357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSSRCRegClassID, 14358 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14359 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_STRICT_FMA, 14360 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 14361 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 14362 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 14363 GIM_CheckIsSafeToFold, /*InsnID*/1, 14364 // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, f32:{ *:[f32] }:$XTi)) => (XSNMADDASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) 14365 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSNMADDASP, 14366 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 14367 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // XTi 14368 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA 14369 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB 14370 GIR_EraseFromParent, /*InsnID*/0, 14371 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14372 // GIR_Coverage, 958, 14373 GIR_Done, 14374 // Label 988: @34748 14375 GIM_Try, /*On fail goto*//*Label 989*/ 34785, // Rule ID 833 // 14376 GIM_CheckFeatures, GIFBS_HasVSX, 14377 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSSRCRegClassID, 14378 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14379 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FABS, 14380 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 14381 GIM_CheckIsSafeToFold, /*InsnID*/1, 14382 // (fneg:{ *:[f32] } (fabs:{ *:[f32] } f32:{ *:[f32] }:$XB)) => (XSNABSDPs:{ *:[f32] } f32:{ *:[f32] }:$XB) 14383 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSNABSDPs, 14384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 14385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB 14386 GIR_EraseFromParent, /*InsnID*/0, 14387 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14388 // GIR_Coverage, 833, 14389 GIR_Done, 14390 // Label 989: @34785 14391 GIM_Try, /*On fail goto*//*Label 990*/ 34851, // Rule ID 230 // 14392 GIM_CheckFeatures, GIFBS_HasFPU, 14393 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 14394 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14395 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, 14396 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 14397 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 14398 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 14399 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] 14400 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 14401 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 14402 GIM_CheckIsSafeToFold, /*InsnID*/1, 14403 GIM_CheckIsSafeToFold, /*InsnID*/2, 14404 // (fneg:{ *:[f32] } (fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, (fneg:{ *:[f32] } f32:{ *:[f32] }:$FRB))) => (FNMSUBS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB) 14405 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::FNMSUBS, 14406 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // FRT 14407 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA 14408 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC 14409 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // FRB 14410 GIR_EraseFromParent, /*InsnID*/0, 14411 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14412 // GIR_Coverage, 230, 14413 GIR_Done, 14414 // Label 990: @34851 14415 GIM_Try, /*On fail goto*//*Label 991*/ 34917, // Rule ID 229 // 14416 GIM_CheckFeatures, GIFBS_HasFPU, 14417 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 14418 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14419 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_STRICT_FMA, 14420 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 14421 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 14422 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 14423 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] 14424 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 14425 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 14426 GIM_CheckIsSafeToFold, /*InsnID*/1, 14427 GIM_CheckIsSafeToFold, /*InsnID*/2, 14428 // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, (fneg:{ *:[f32] } f32:{ *:[f32] }:$FRB))) => (FNMSUBS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB) 14429 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::FNMSUBS, 14430 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // FRT 14431 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA 14432 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC 14433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // FRB 14434 GIR_EraseFromParent, /*InsnID*/0, 14435 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14436 // GIR_Coverage, 229, 14437 GIR_Done, 14438 // Label 991: @34917 14439 GIM_Try, /*On fail goto*//*Label 992*/ 34970, // Rule ID 226 // 14440 GIM_CheckFeatures, GIFBS_HasFPU, 14441 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 14442 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14443 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, 14444 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 14445 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 14446 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 14447 GIM_CheckIsSafeToFold, /*InsnID*/1, 14448 // (fneg:{ *:[f32] } (fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB)) => (FNMADDS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB) 14449 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::FNMADDS, 14450 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // FRT 14451 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA 14452 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC 14453 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // FRB 14454 GIR_EraseFromParent, /*InsnID*/0, 14455 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14456 // GIR_Coverage, 226, 14457 GIR_Done, 14458 // Label 992: @34970 14459 GIM_Try, /*On fail goto*//*Label 993*/ 35023, // Rule ID 225 // 14460 GIM_CheckFeatures, GIFBS_HasFPU, 14461 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 14462 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14463 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_STRICT_FMA, 14464 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 14465 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 14466 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 14467 GIM_CheckIsSafeToFold, /*InsnID*/1, 14468 // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB)) => (FNMADDS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB) 14469 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::FNMADDS, 14470 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // FRT 14471 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA 14472 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC 14473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // FRB 14474 GIR_EraseFromParent, /*InsnID*/0, 14475 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14476 // GIR_Coverage, 225, 14477 GIR_Done, 14478 // Label 993: @35023 14479 GIM_Try, /*On fail goto*//*Label 994*/ 35060, // Rule ID 162 // 14480 GIM_CheckFeatures, GIFBS_HasFPU, 14481 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 14482 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14483 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FABS, 14484 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 14485 GIM_CheckIsSafeToFold, /*InsnID*/1, 14486 // (fneg:{ *:[f32] } (fabs:{ *:[f32] } f32:{ *:[f32] }:$frB)) => (FNABSS:{ *:[f32] } f32:{ *:[f32] }:$frB) 14487 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::FNABSS, 14488 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // frD 14489 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // frB 14490 GIR_EraseFromParent, /*InsnID*/0, 14491 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14492 // GIR_Coverage, 162, 14493 GIR_Done, 14494 // Label 994: @35060 14495 GIM_Try, /*On fail goto*//*Label 995*/ 35097, // Rule ID 590 // 14496 GIM_CheckFeatures, GIFBS_HasSPE, 14497 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 14498 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14499 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FABS, 14500 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 14501 GIM_CheckIsSafeToFold, /*InsnID*/1, 14502 // (fneg:{ *:[f32] } (fabs:{ *:[f32] } f32:{ *:[f32] }:$RA)) => (EFSNABS:{ *:[f32] } f32:{ *:[f32] }:$RA) 14503 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::EFSNABS, 14504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RT 14505 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RA 14506 GIR_EraseFromParent, /*InsnID*/0, 14507 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14508 // GIR_Coverage, 590, 14509 GIR_Done, 14510 // Label 995: @35097 14511 GIM_Try, /*On fail goto*//*Label 996*/ 35112, // Rule ID 164 // 14512 GIM_CheckFeatures, GIFBS_HasFPU, 14513 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 14514 // (fneg:{ *:[f32] } f32:{ *:[f32] }:$frB) => (FNEGS:{ *:[f32] } f32:{ *:[f32] }:$frB) 14515 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FNEGS, 14516 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14517 // GIR_Coverage, 164, 14518 GIR_Done, 14519 // Label 996: @35112 14520 GIM_Try, /*On fail goto*//*Label 997*/ 35127, // Rule ID 591 // 14521 GIM_CheckFeatures, GIFBS_HasSPE, 14522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 14523 // (fneg:{ *:[f32] } f32:{ *:[f32] }:$RA) => (EFSNEG:{ *:[f32] } f32:{ *:[f32] }:$RA) 14524 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFSNEG, 14525 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14526 // GIR_Coverage, 591, 14527 GIR_Done, 14528 // Label 997: @35127 14529 GIM_Reject, 14530 // Label 984: @35128 14531 GIM_Reject, 14532 // Label 979: @35129 14533 GIM_Try, /*On fail goto*//*Label 998*/ 35771, 14534 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14535 GIM_Try, /*On fail goto*//*Label 999*/ 35201, // Rule ID 782 // 14536 GIM_CheckFeatures, GIFBS_HasVSX, 14537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 14538 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14539 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, 14540 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 14541 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 14542 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 14543 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] 14544 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 14545 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, 14546 GIM_CheckIsSafeToFold, /*InsnID*/1, 14547 GIM_CheckIsSafeToFold, /*InsnID*/2, 14548 // (fneg:{ *:[f64] } (fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, (fneg:{ *:[f64] } f64:{ *:[f64] }:$XTi))) => (XSNMSUBADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) 14549 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSNMSUBADP, 14550 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 14551 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi 14552 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA 14553 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB 14554 GIR_EraseFromParent, /*InsnID*/0, 14555 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14556 // GIR_Coverage, 782, 14557 GIR_Done, 14558 // Label 999: @35201 14559 GIM_Try, /*On fail goto*//*Label 1000*/ 35267, // Rule ID 781 // 14560 GIM_CheckFeatures, GIFBS_HasVSX, 14561 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 14562 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14563 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_STRICT_FMA, 14564 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 14565 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 14566 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 14567 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] 14568 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 14569 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, 14570 GIM_CheckIsSafeToFold, /*InsnID*/1, 14571 GIM_CheckIsSafeToFold, /*InsnID*/2, 14572 // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, (fneg:{ *:[f64] } f64:{ *:[f64] }:$XTi))) => (XSNMSUBADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) 14573 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSNMSUBADP, 14574 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 14575 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi 14576 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA 14577 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB 14578 GIR_EraseFromParent, /*InsnID*/0, 14579 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14580 // GIR_Coverage, 781, 14581 GIR_Done, 14582 // Label 1000: @35267 14583 GIM_Try, /*On fail goto*//*Label 1001*/ 35320, // Rule ID 780 // 14584 GIM_CheckFeatures, GIFBS_HasVSX, 14585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 14586 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14587 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, 14588 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 14589 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 14590 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 14591 GIM_CheckIsSafeToFold, /*InsnID*/1, 14592 // (fneg:{ *:[f64] } (fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, f64:{ *:[f64] }:$XTi)) => (XSNMADDADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) 14593 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSNMADDADP, 14594 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 14595 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // XTi 14596 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA 14597 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB 14598 GIR_EraseFromParent, /*InsnID*/0, 14599 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14600 // GIR_Coverage, 780, 14601 GIR_Done, 14602 // Label 1001: @35320 14603 GIM_Try, /*On fail goto*//*Label 1002*/ 35373, // Rule ID 779 // 14604 GIM_CheckFeatures, GIFBS_HasVSX, 14605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 14606 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14607 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_STRICT_FMA, 14608 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 14609 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 14610 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 14611 GIM_CheckIsSafeToFold, /*InsnID*/1, 14612 // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, f64:{ *:[f64] }:$XTi)) => (XSNMADDADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) 14613 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSNMADDADP, 14614 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 14615 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // XTi 14616 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA 14617 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB 14618 GIR_EraseFromParent, /*InsnID*/0, 14619 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14620 // GIR_Coverage, 779, 14621 GIR_Done, 14622 // Label 1002: @35373 14623 GIM_Try, /*On fail goto*//*Label 1003*/ 35410, // Rule ID 832 // 14624 GIM_CheckFeatures, GIFBS_HasVSX, 14625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 14626 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14627 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FABS, 14628 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 14629 GIM_CheckIsSafeToFold, /*InsnID*/1, 14630 // (fneg:{ *:[f64] } (fabs:{ *:[f64] } f64:{ *:[f64] }:$XB)) => (XSNABSDP:{ *:[f64] } f64:{ *:[f64] }:$XB) 14631 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSNABSDP, 14632 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 14633 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB 14634 GIR_EraseFromParent, /*InsnID*/0, 14635 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14636 // GIR_Coverage, 832, 14637 GIR_Done, 14638 // Label 1003: @35410 14639 GIM_Try, /*On fail goto*//*Label 1004*/ 35428, // Rule ID 834 // 14640 GIM_CheckFeatures, GIFBS_HasVSX, 14641 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 14642 // (fneg:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSNEGDP:{ *:[f64] } f64:{ *:[f64] }:$XB) 14643 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSNEGDP, 14644 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 14645 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14646 // GIR_Coverage, 834, 14647 GIR_Done, 14648 // Label 1004: @35428 14649 GIM_Try, /*On fail goto*//*Label 1005*/ 35494, // Rule ID 228 // 14650 GIM_CheckFeatures, GIFBS_HasFPU, 14651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 14652 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14653 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, 14654 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 14655 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 14656 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 14657 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] 14658 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 14659 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, 14660 GIM_CheckIsSafeToFold, /*InsnID*/1, 14661 GIM_CheckIsSafeToFold, /*InsnID*/2, 14662 // (fneg:{ *:[f64] } (fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, (fneg:{ *:[f64] } f64:{ *:[f64] }:$FRB))) => (FNMSUB:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB) 14663 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::FNMSUB, 14664 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // FRT 14665 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA 14666 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC 14667 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // FRB 14668 GIR_EraseFromParent, /*InsnID*/0, 14669 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14670 // GIR_Coverage, 228, 14671 GIR_Done, 14672 // Label 1005: @35494 14673 GIM_Try, /*On fail goto*//*Label 1006*/ 35560, // Rule ID 227 // 14674 GIM_CheckFeatures, GIFBS_HasFPU, 14675 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 14676 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14677 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_STRICT_FMA, 14678 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 14679 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 14680 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 14681 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] 14682 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 14683 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, 14684 GIM_CheckIsSafeToFold, /*InsnID*/1, 14685 GIM_CheckIsSafeToFold, /*InsnID*/2, 14686 // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, (fneg:{ *:[f64] } f64:{ *:[f64] }:$FRB))) => (FNMSUB:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB) 14687 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::FNMSUB, 14688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // FRT 14689 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA 14690 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC 14691 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // FRB 14692 GIR_EraseFromParent, /*InsnID*/0, 14693 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14694 // GIR_Coverage, 227, 14695 GIR_Done, 14696 // Label 1006: @35560 14697 GIM_Try, /*On fail goto*//*Label 1007*/ 35613, // Rule ID 224 // 14698 GIM_CheckFeatures, GIFBS_HasFPU, 14699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 14700 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14701 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, 14702 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 14703 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 14704 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 14705 GIM_CheckIsSafeToFold, /*InsnID*/1, 14706 // (fneg:{ *:[f64] } (fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB)) => (FNMADD:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB) 14707 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::FNMADD, 14708 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // FRT 14709 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA 14710 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC 14711 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // FRB 14712 GIR_EraseFromParent, /*InsnID*/0, 14713 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14714 // GIR_Coverage, 224, 14715 GIR_Done, 14716 // Label 1007: @35613 14717 GIM_Try, /*On fail goto*//*Label 1008*/ 35666, // Rule ID 223 // 14718 GIM_CheckFeatures, GIFBS_HasFPU, 14719 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 14720 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14721 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_STRICT_FMA, 14722 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 14723 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 14724 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 14725 GIM_CheckIsSafeToFold, /*InsnID*/1, 14726 // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB)) => (FNMADD:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB) 14727 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::FNMADD, 14728 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // FRT 14729 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA 14730 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC 14731 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // FRB 14732 GIR_EraseFromParent, /*InsnID*/0, 14733 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14734 // GIR_Coverage, 223, 14735 GIR_Done, 14736 // Label 1008: @35666 14737 GIM_Try, /*On fail goto*//*Label 1009*/ 35703, // Rule ID 163 // 14738 GIM_CheckFeatures, GIFBS_HasFPU, 14739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 14740 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14741 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FABS, 14742 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 14743 GIM_CheckIsSafeToFold, /*InsnID*/1, 14744 // (fneg:{ *:[f64] } (fabs:{ *:[f64] } f64:{ *:[f64] }:$frB)) => (FNABSD:{ *:[f64] } f64:{ *:[f64] }:$frB) 14745 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::FNABSD, 14746 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // frD 14747 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // frB 14748 GIR_EraseFromParent, /*InsnID*/0, 14749 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14750 // GIR_Coverage, 163, 14751 GIR_Done, 14752 // Label 1009: @35703 14753 GIM_Try, /*On fail goto*//*Label 1010*/ 35740, // Rule ID 569 // 14754 GIM_CheckFeatures, GIFBS_HasSPE, 14755 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::SPERCRegClassID, 14756 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14757 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FABS, 14758 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 14759 GIM_CheckIsSafeToFold, /*InsnID*/1, 14760 // (fneg:{ *:[f64] } (fabs:{ *:[f64] } f64:{ *:[f64] }:$RA)) => (EFDNABS:{ *:[f64] } f64:{ *:[f64] }:$RA) 14761 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::EFDNABS, 14762 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RT 14763 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RA 14764 GIR_EraseFromParent, /*InsnID*/0, 14765 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14766 // GIR_Coverage, 569, 14767 GIR_Done, 14768 // Label 1010: @35740 14769 GIM_Try, /*On fail goto*//*Label 1011*/ 35755, // Rule ID 165 // 14770 GIM_CheckFeatures, GIFBS_HasFPU, 14771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 14772 // (fneg:{ *:[f64] } f64:{ *:[f64] }:$frB) => (FNEGD:{ *:[f64] } f64:{ *:[f64] }:$frB) 14773 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FNEGD, 14774 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14775 // GIR_Coverage, 165, 14776 GIR_Done, 14777 // Label 1011: @35755 14778 GIM_Try, /*On fail goto*//*Label 1012*/ 35770, // Rule ID 570 // 14779 GIM_CheckFeatures, GIFBS_HasSPE, 14780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::SPERCRegClassID, 14781 // (fneg:{ *:[f64] } f64:{ *:[f64] }:$RA) => (EFDNEG:{ *:[f64] } f64:{ *:[f64] }:$RA) 14782 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFDNEG, 14783 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14784 // GIR_Coverage, 570, 14785 GIR_Done, 14786 // Label 1012: @35770 14787 GIM_Reject, 14788 // Label 998: @35771 14789 GIM_Reject, 14790 // Label 980: @35772 14791 GIM_Try, /*On fail goto*//*Label 1013*/ 36174, 14792 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 14793 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 14794 GIM_Try, /*On fail goto*//*Label 1014*/ 35851, // Rule ID 1001 // 14795 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 14796 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14797 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 14798 GIM_CheckNumOperands, /*MI*/1, /*Expected*/5, 14799 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::ppc_fmaf128_round_to_odd, 14800 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 14801 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 14802 GIM_CheckType, /*MI*/1, /*Op*/4, /*Type*/GILLT_s128, 14803 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/4, // MIs[2] 14804 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 14805 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s128, 14806 GIM_CheckIsSafeToFold, /*InsnID*/1, 14807 GIM_CheckIsSafeToFold, /*InsnID*/2, 14808 // (fneg:{ *:[f128] } (intrinsic_wo_chain:{ *:[f128] } 7486:{ *:[iPTR] }, f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB, (fneg:{ *:[f128] } f128:{ *:[f128] }:$vTi))) => (XSNMSUBQPO:{ *:[f128] } f128:{ *:[f128] }:$vTi, f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 14809 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSNMSUBQPO, 14810 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 14811 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vTi 14812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA 14813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // vB 14814 GIR_EraseFromParent, /*InsnID*/0, 14815 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14816 // GIR_Coverage, 1001, 14817 GIR_Done, 14818 // Label 1014: @35851 14819 GIM_Try, /*On fail goto*//*Label 1015*/ 35907, // Rule ID 1000 // 14820 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 14821 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14822 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 14823 GIM_CheckNumOperands, /*MI*/1, /*Expected*/5, 14824 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::ppc_fmaf128_round_to_odd, 14825 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 14826 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 14827 GIM_CheckType, /*MI*/1, /*Op*/4, /*Type*/GILLT_s128, 14828 GIM_CheckIsSafeToFold, /*InsnID*/1, 14829 // (fneg:{ *:[f128] } (intrinsic_wo_chain:{ *:[f128] } 7486:{ *:[iPTR] }, f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB, f128:{ *:[f128] }:$vTi)) => (XSNMADDQPO:{ *:[f128] } f128:{ *:[f128] }:$vTi, f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 14830 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSNMADDQPO, 14831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 14832 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/4, // vTi 14833 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA 14834 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // vB 14835 GIR_EraseFromParent, /*InsnID*/0, 14836 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14837 // GIR_Coverage, 1000, 14838 GIR_Done, 14839 // Label 1015: @35907 14840 GIM_Try, /*On fail goto*//*Label 1016*/ 35969, // Rule ID 992 // 14841 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 14842 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14843 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, 14844 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128, 14845 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 14846 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 14847 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] 14848 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 14849 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s128, 14850 GIM_CheckIsSafeToFold, /*InsnID*/1, 14851 GIM_CheckIsSafeToFold, /*InsnID*/2, 14852 // (fneg:{ *:[f128] } (fma:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB, (fneg:{ *:[f128] } f128:{ *:[f128] }:$vTi))) => (XSNMSUBQP:{ *:[f128] } f128:{ *:[f128] }:$vTi, f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 14853 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSNMSUBQP, 14854 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 14855 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vTi 14856 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA 14857 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB 14858 GIR_EraseFromParent, /*InsnID*/0, 14859 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14860 // GIR_Coverage, 992, 14861 GIR_Done, 14862 // Label 1016: @35969 14863 GIM_Try, /*On fail goto*//*Label 1017*/ 36031, // Rule ID 991 // 14864 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 14865 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14866 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_STRICT_FMA, 14867 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128, 14868 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 14869 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 14870 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] 14871 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 14872 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s128, 14873 GIM_CheckIsSafeToFold, /*InsnID*/1, 14874 GIM_CheckIsSafeToFold, /*InsnID*/2, 14875 // (fneg:{ *:[f128] } (strict_fma:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB, (fneg:{ *:[f128] } f128:{ *:[f128] }:$vTi))) => (XSNMSUBQP:{ *:[f128] } f128:{ *:[f128] }:$vTi, f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 14876 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSNMSUBQP, 14877 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 14878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vTi 14879 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA 14880 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB 14881 GIR_EraseFromParent, /*InsnID*/0, 14882 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14883 // GIR_Coverage, 991, 14884 GIR_Done, 14885 // Label 1017: @36031 14886 GIM_Try, /*On fail goto*//*Label 1018*/ 36080, // Rule ID 990 // 14887 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 14888 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14889 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, 14890 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128, 14891 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 14892 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 14893 GIM_CheckIsSafeToFold, /*InsnID*/1, 14894 // (fneg:{ *:[f128] } (fma:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB, f128:{ *:[f128] }:$vTi)) => (XSNMADDQP:{ *:[f128] } f128:{ *:[f128] }:$vTi, f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 14895 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSNMADDQP, 14896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 14897 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // vTi 14898 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA 14899 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB 14900 GIR_EraseFromParent, /*InsnID*/0, 14901 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14902 // GIR_Coverage, 990, 14903 GIR_Done, 14904 // Label 1018: @36080 14905 GIM_Try, /*On fail goto*//*Label 1019*/ 36129, // Rule ID 989 // 14906 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 14907 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14908 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_STRICT_FMA, 14909 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128, 14910 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, 14911 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, 14912 GIM_CheckIsSafeToFold, /*InsnID*/1, 14913 // (fneg:{ *:[f128] } (strict_fma:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB, f128:{ *:[f128] }:$vTi)) => (XSNMADDQP:{ *:[f128] } f128:{ *:[f128] }:$vTi, f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 14914 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSNMADDQP, 14915 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 14916 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // vTi 14917 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA 14918 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB 14919 GIR_EraseFromParent, /*InsnID*/0, 14920 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14921 // GIR_Coverage, 989, 14922 GIR_Done, 14923 // Label 1019: @36129 14924 GIM_Try, /*On fail goto*//*Label 1020*/ 36162, // Rule ID 973 // 14925 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 14926 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14927 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FABS, 14928 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128, 14929 GIM_CheckIsSafeToFold, /*InsnID*/1, 14930 // (fneg:{ *:[f128] } (fabs:{ *:[f128] } f128:{ *:[f128] }:$vB)) => (XSNABSQP:{ *:[f128] } f128:{ *:[f128] }:$vB) 14931 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSNABSQP, 14932 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 14933 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB 14934 GIR_EraseFromParent, /*InsnID*/0, 14935 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14936 // GIR_Coverage, 973, 14937 GIR_Done, 14938 // Label 1020: @36162 14939 GIM_Try, /*On fail goto*//*Label 1021*/ 36173, // Rule ID 974 // 14940 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 14941 // (fneg:{ *:[f128] } f128:{ *:[f128] }:$vB) => (XSNEGQP:{ *:[f128] } f128:{ *:[f128] }:$vB) 14942 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSNEGQP, 14943 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14944 // GIR_Coverage, 974, 14945 GIR_Done, 14946 // Label 1021: @36173 14947 GIM_Reject, 14948 // Label 1013: @36174 14949 GIM_Reject, 14950 // Label 981: @36175 14951 GIM_Try, /*On fail goto*//*Label 1022*/ 36455, 14952 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 14953 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 14954 GIM_Try, /*On fail goto*//*Label 1023*/ 36247, // Rule ID 795 // 14955 GIM_CheckFeatures, GIFBS_HasVSX, 14956 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14957 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, 14958 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, 14959 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, 14960 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64, 14961 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] 14962 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 14963 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, 14964 GIM_CheckIsSafeToFold, /*InsnID*/1, 14965 GIM_CheckIsSafeToFold, /*InsnID*/2, 14966 // (fneg:{ *:[v2f64] } (fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, (fneg:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi))) => (XVNMSUBADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) 14967 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVNMSUBADP, 14968 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 14969 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi 14970 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA 14971 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB 14972 GIR_EraseFromParent, /*InsnID*/0, 14973 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14974 // GIR_Coverage, 795, 14975 GIR_Done, 14976 // Label 1023: @36247 14977 GIM_Try, /*On fail goto*//*Label 1024*/ 36309, // Rule ID 794 // 14978 GIM_CheckFeatures, GIFBS_HasVSX, 14979 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14980 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_STRICT_FMA, 14981 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, 14982 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, 14983 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64, 14984 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] 14985 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 14986 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, 14987 GIM_CheckIsSafeToFold, /*InsnID*/1, 14988 GIM_CheckIsSafeToFold, /*InsnID*/2, 14989 // (fneg:{ *:[v2f64] } (strict_fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, (fneg:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi))) => (XVNMSUBADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) 14990 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVNMSUBADP, 14991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 14992 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi 14993 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA 14994 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB 14995 GIR_EraseFromParent, /*InsnID*/0, 14996 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14997 // GIR_Coverage, 794, 14998 GIR_Done, 14999 // Label 1024: @36309 15000 GIM_Try, /*On fail goto*//*Label 1025*/ 36358, // Rule ID 792 // 15001 GIM_CheckFeatures, GIFBS_HasVSX, 15002 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 15003 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, 15004 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, 15005 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, 15006 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64, 15007 GIM_CheckIsSafeToFold, /*InsnID*/1, 15008 // (fneg:{ *:[v2f64] } (fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, v2f64:{ *:[v2f64] }:$XTi)) => (XVNMADDADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) 15009 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVNMADDADP, 15010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 15011 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // XTi 15012 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA 15013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB 15014 GIR_EraseFromParent, /*InsnID*/0, 15015 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15016 // GIR_Coverage, 792, 15017 GIR_Done, 15018 // Label 1025: @36358 15019 GIM_Try, /*On fail goto*//*Label 1026*/ 36407, // Rule ID 791 // 15020 GIM_CheckFeatures, GIFBS_HasVSX, 15021 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 15022 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_STRICT_FMA, 15023 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, 15024 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, 15025 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64, 15026 GIM_CheckIsSafeToFold, /*InsnID*/1, 15027 // (fneg:{ *:[v2f64] } (strict_fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, v2f64:{ *:[v2f64] }:$XTi)) => (XVNMADDADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) 15028 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVNMADDADP, 15029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 15030 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // XTi 15031 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA 15032 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB 15033 GIR_EraseFromParent, /*InsnID*/0, 15034 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15035 // GIR_Coverage, 791, 15036 GIR_Done, 15037 // Label 1026: @36407 15038 GIM_Try, /*On fail goto*//*Label 1027*/ 36440, // Rule ID 840 // 15039 GIM_CheckFeatures, GIFBS_HasVSX, 15040 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 15041 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FABS, 15042 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, 15043 GIM_CheckIsSafeToFold, /*InsnID*/1, 15044 // (fneg:{ *:[v2f64] } (fabs:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB)) => (XVNABSDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) 15045 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVNABSDP, 15046 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 15047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB 15048 GIR_EraseFromParent, /*InsnID*/0, 15049 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15050 // GIR_Coverage, 840, 15051 GIR_Done, 15052 // Label 1027: @36440 15053 GIM_Try, /*On fail goto*//*Label 1028*/ 36454, // Rule ID 842 // 15054 GIM_CheckFeatures, GIFBS_HasVSX, 15055 // (fneg:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVNEGDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) 15056 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVNEGDP, 15057 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 15058 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15059 // GIR_Coverage, 842, 15060 GIR_Done, 15061 // Label 1028: @36454 15062 GIM_Reject, 15063 // Label 1022: @36455 15064 GIM_Reject, 15065 // Label 982: @36456 15066 GIM_Try, /*On fail goto*//*Label 1029*/ 36769, 15067 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 15068 GIM_Try, /*On fail goto*//*Label 1030*/ 36528, // Rule ID 797 // 15069 GIM_CheckFeatures, GIFBS_HasVSX, 15070 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 15071 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 15072 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, 15073 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 15074 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 15075 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, 15076 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] 15077 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 15078 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, 15079 GIM_CheckIsSafeToFold, /*InsnID*/1, 15080 GIM_CheckIsSafeToFold, /*InsnID*/2, 15081 // (fneg:{ *:[v4f32] } (fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB, (fneg:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi))) => (XVNMSUBASP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) 15082 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVNMSUBASP, 15083 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 15084 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi 15085 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA 15086 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB 15087 GIR_EraseFromParent, /*InsnID*/0, 15088 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15089 // GIR_Coverage, 797, 15090 GIR_Done, 15091 // Label 1030: @36528 15092 GIM_Try, /*On fail goto*//*Label 1031*/ 36594, // Rule ID 796 // 15093 GIM_CheckFeatures, GIFBS_HasVSX, 15094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 15095 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 15096 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_STRICT_FMA, 15097 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 15098 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 15099 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, 15100 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] 15101 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 15102 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, 15103 GIM_CheckIsSafeToFold, /*InsnID*/1, 15104 GIM_CheckIsSafeToFold, /*InsnID*/2, 15105 // (fneg:{ *:[v4f32] } (strict_fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB, (fneg:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi))) => (XVNMSUBASP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) 15106 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVNMSUBASP, 15107 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 15108 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi 15109 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA 15110 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB 15111 GIR_EraseFromParent, /*InsnID*/0, 15112 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15113 // GIR_Coverage, 796, 15114 GIR_Done, 15115 // Label 1031: @36594 15116 GIM_Try, /*On fail goto*//*Label 1032*/ 36647, // Rule ID 793 // 15117 GIM_CheckFeatures, GIFBS_HasVSX, 15118 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 15119 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 15120 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, 15121 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 15122 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 15123 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, 15124 GIM_CheckIsSafeToFold, /*InsnID*/1, 15125 // (fneg:{ *:[v4f32] } (fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB, v4f32:{ *:[v4f32] }:$XTi)) => (XVNMADDASP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) 15126 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVNMADDASP, 15127 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 15128 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // XTi 15129 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA 15130 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB 15131 GIR_EraseFromParent, /*InsnID*/0, 15132 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15133 // GIR_Coverage, 793, 15134 GIR_Done, 15135 // Label 1032: @36647 15136 GIM_Try, /*On fail goto*//*Label 1033*/ 36684, // Rule ID 841 // 15137 GIM_CheckFeatures, GIFBS_HasVSX, 15138 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 15139 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 15140 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FABS, 15141 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 15142 GIM_CheckIsSafeToFold, /*InsnID*/1, 15143 // (fneg:{ *:[v4f32] } (fabs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB)) => (XVNABSSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) 15144 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVNABSSP, 15145 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 15146 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB 15147 GIR_EraseFromParent, /*InsnID*/0, 15148 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15149 // GIR_Coverage, 841, 15150 GIR_Done, 15151 // Label 1033: @36684 15152 GIM_Try, /*On fail goto*//*Label 1034*/ 36702, // Rule ID 843 // 15153 GIM_CheckFeatures, GIFBS_HasVSX, 15154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 15155 // (fneg:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVNEGSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) 15156 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVNEGSP, 15157 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 15158 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15159 // GIR_Coverage, 843, 15160 GIR_Done, 15161 // Label 1034: @36702 15162 GIM_Try, /*On fail goto*//*Label 1035*/ 36768, // Rule ID 289 // 15163 GIM_CheckFeatures, GIFBS_HasAltivec, 15164 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 15165 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 15166 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, 15167 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 15168 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 15169 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, 15170 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] 15171 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 15172 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, 15173 GIM_CheckIsSafeToFold, /*InsnID*/1, 15174 GIM_CheckIsSafeToFold, /*InsnID*/2, 15175 // (fneg:{ *:[v4f32] } (fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vA, v4f32:{ *:[v4f32] }:$vC, (fneg:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vB))) => (VNMSUBFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vA, v4f32:{ *:[v4f32] }:$vC, v4f32:{ *:[v4f32] }:$vB) 15176 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::VNMSUBFP, 15177 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vD 15178 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA 15179 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC 15180 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB 15181 GIR_EraseFromParent, /*InsnID*/0, 15182 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15183 // GIR_Coverage, 289, 15184 GIR_Done, 15185 // Label 1035: @36768 15186 GIM_Reject, 15187 // Label 1029: @36769 15188 GIM_Reject, 15189 // Label 983: @36770 15190 GIM_Reject, 15191 // Label 35: @36771 15192 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 4, /*)*//*default:*//*Label 1038*/ 36819, 15193 /*GILLT_s64*//*Label 1036*/ 36779, 15194 /*GILLT_s128*//*Label 1037*/ 36799, 15195 // Label 1036: @36779 15196 GIM_Try, /*On fail goto*//*Label 1039*/ 36798, // Rule ID 556 // 15197 GIM_CheckFeatures, GIFBS_HasSPE, 15198 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15199 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::SPERCRegClassID, 15200 // (fpextend:{ *:[f64] } f32:{ *:[f32] }:$RB) => (EFDCFS:{ *:[f64] } f32:{ *:[f32] }:$RB) 15201 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFDCFS, 15202 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15203 // GIR_Coverage, 556, 15204 GIR_Done, 15205 // Label 1039: @36798 15206 GIM_Reject, 15207 // Label 1037: @36799 15208 GIM_Try, /*On fail goto*//*Label 1040*/ 36818, // Rule ID 1003 // 15209 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 15210 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 15211 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 15212 // (fpextend:{ *:[f128] } f64:{ *:[f64] }:$vB) => (XSCVDPQP:{ *:[f128] } f64:{ *:[f64] }:$vB) 15213 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSCVDPQP, 15214 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15215 // GIR_Coverage, 1003, 15216 GIR_Done, 15217 // Label 1040: @36818 15218 GIM_Reject, 15219 // Label 1038: @36819 15220 GIM_Reject, 15221 // Label 36: @36820 15222 GIM_Try, /*On fail goto*//*Label 1041*/ 36879, 15223 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 15224 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 15225 GIM_Try, /*On fail goto*//*Label 1042*/ 36845, // Rule ID 950 // 15226 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 15227 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSSRCRegClassID, 15228 // (fpround:{ *:[f32] } f64:{ *:[f64] }:$XB) => (XSRSP:{ *:[f32] } f64:{ *:[f64] }:$XB) 15229 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSRSP, 15230 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15231 // GIR_Coverage, 950, 15232 GIR_Done, 15233 // Label 1042: @36845 15234 GIM_Try, /*On fail goto*//*Label 1043*/ 36863, // Rule ID 155 // 15235 GIM_CheckFeatures, GIFBS_HasFPU, 15236 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 15237 // (fpround:{ *:[f32] } f64:{ *:[f64] }:$frB) => (FRSP:{ *:[f32] } f64:{ *:[f64] }:$frB) 15238 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FRSP, 15239 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 15240 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15241 // GIR_Coverage, 155, 15242 GIR_Done, 15243 // Label 1043: @36863 15244 GIM_Try, /*On fail goto*//*Label 1044*/ 36878, // Rule ID 577 // 15245 GIM_CheckFeatures, GIFBS_HasSPE, 15246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 15247 // (fpround:{ *:[f32] } f64:{ *:[f64] }:$RB) => (EFSCFD:{ *:[f32] } f64:{ *:[f64] }:$RB) 15248 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFSCFD, 15249 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15250 // GIR_Coverage, 577, 15251 GIR_Done, 15252 // Label 1044: @36878 15253 GIM_Reject, 15254 // Label 1041: @36879 15255 GIM_Reject, 15256 // Label 37: @36880 15257 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 1048*/ 36976, 15258 /*GILLT_s32*//*Label 1045*/ 36891, 0, 0, 15259 /*GILLT_v2s64*//*Label 1046*/ 36930, 15260 /*GILLT_v4s32*//*Label 1047*/ 36953, 15261 // Label 1045: @36891 15262 GIM_Try, /*On fail goto*//*Label 1049*/ 36910, // Rule ID 562 // 15263 GIM_CheckFeatures, GIFBS_HasSPE, 15264 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 15265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 15266 // (fp_to_sint:{ *:[i32] } f64:{ *:[f64] }:$RB) => (EFDCTSIZ:{ *:[i32] } f64:{ *:[f64] }:$RB) 15267 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFDCTSIZ, 15268 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15269 // GIR_Coverage, 562, 15270 GIR_Done, 15271 // Label 1049: @36910 15272 GIM_Try, /*On fail goto*//*Label 1050*/ 36929, // Rule ID 583 // 15273 GIM_CheckFeatures, GIFBS_HasSPE, 15274 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15275 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 15276 // (fp_to_sint:{ *:[i32] } f32:{ *:[f32] }:$RB) => (EFSCTSIZ:{ *:[i32] } f32:{ *:[f32] }:$RB) 15277 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFSCTSIZ, 15278 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15279 // GIR_Coverage, 583, 15280 GIR_Done, 15281 // Label 1050: @36929 15282 GIM_Reject, 15283 // Label 1046: @36930 15284 GIM_Try, /*On fail goto*//*Label 1051*/ 36952, // Rule ID 866 // 15285 GIM_CheckFeatures, GIFBS_HasVSX, 15286 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 15287 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 15288 // (fp_to_sint:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XB) => (XVCVDPSXDS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XB) 15289 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVCVDPSXDS, 15290 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 15291 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15292 // GIR_Coverage, 866, 15293 GIR_Done, 15294 // Label 1051: @36952 15295 GIM_Reject, 15296 // Label 1047: @36953 15297 GIM_Try, /*On fail goto*//*Label 1052*/ 36975, // Rule ID 874 // 15298 GIM_CheckFeatures, GIFBS_HasVSX, 15299 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 15300 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 15301 // (fp_to_sint:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XB) => (XVCVSPSXWS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XB) 15302 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVCVSPSXWS, 15303 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 15304 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15305 // GIR_Coverage, 874, 15306 GIR_Done, 15307 // Label 1052: @36975 15308 GIM_Reject, 15309 // Label 1048: @36976 15310 GIM_Reject, 15311 // Label 38: @36977 15312 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 1056*/ 37073, 15313 /*GILLT_s32*//*Label 1053*/ 36988, 0, 0, 15314 /*GILLT_v2s64*//*Label 1054*/ 37027, 15315 /*GILLT_v4s32*//*Label 1055*/ 37050, 15316 // Label 1053: @36988 15317 GIM_Try, /*On fail goto*//*Label 1057*/ 37007, // Rule ID 564 // 15318 GIM_CheckFeatures, GIFBS_HasSPE, 15319 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 15320 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 15321 // (fp_to_uint:{ *:[i32] } f64:{ *:[f64] }:$RB) => (EFDCTUIZ:{ *:[i32] } f64:{ *:[f64] }:$RB) 15322 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFDCTUIZ, 15323 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15324 // GIR_Coverage, 564, 15325 GIR_Done, 15326 // Label 1057: @37007 15327 GIM_Try, /*On fail goto*//*Label 1058*/ 37026, // Rule ID 585 // 15328 GIM_CheckFeatures, GIFBS_HasSPE, 15329 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 15331 // (fp_to_uint:{ *:[i32] } f32:{ *:[f32] }:$RB) => (EFSCTUIZ:{ *:[i32] } f32:{ *:[f32] }:$RB) 15332 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFSCTUIZ, 15333 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15334 // GIR_Coverage, 585, 15335 GIR_Done, 15336 // Label 1058: @37026 15337 GIM_Reject, 15338 // Label 1054: @37027 15339 GIM_Try, /*On fail goto*//*Label 1059*/ 37049, // Rule ID 869 // 15340 GIM_CheckFeatures, GIFBS_HasVSX, 15341 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 15342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 15343 // (fp_to_uint:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XB) => (XVCVDPUXDS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XB) 15344 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVCVDPUXDS, 15345 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 15346 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15347 // GIR_Coverage, 869, 15348 GIR_Done, 15349 // Label 1059: @37049 15350 GIM_Reject, 15351 // Label 1055: @37050 15352 GIM_Try, /*On fail goto*//*Label 1060*/ 37072, // Rule ID 877 // 15353 GIM_CheckFeatures, GIFBS_HasVSX, 15354 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 15355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 15356 // (fp_to_uint:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XB) => (XVCVSPUXWS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XB) 15357 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVCVSPUXWS, 15358 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 15359 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15360 // GIR_Coverage, 877, 15361 GIR_Done, 15362 // Label 1060: @37072 15363 GIM_Reject, 15364 // Label 1056: @37073 15365 GIM_Reject, 15366 // Label 39: @37074 15367 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 1065*/ 37171, 15368 /*GILLT_s32*//*Label 1061*/ 37085, 15369 /*GILLT_s64*//*Label 1062*/ 37105, 0, 15370 /*GILLT_v2s64*//*Label 1063*/ 37125, 15371 /*GILLT_v4s32*//*Label 1064*/ 37148, 15372 // Label 1061: @37085 15373 GIM_Try, /*On fail goto*//*Label 1066*/ 37104, // Rule ID 579 // 15374 GIM_CheckFeatures, GIFBS_HasSPE, 15375 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15376 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 15377 // (sint_to_fp:{ *:[f32] } i32:{ *:[i32] }:$RB) => (EFSCFSI:{ *:[f32] } i32:{ *:[i32] }:$RB) 15378 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFSCFSI, 15379 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15380 // GIR_Coverage, 579, 15381 GIR_Done, 15382 // Label 1066: @37104 15383 GIM_Reject, 15384 // Label 1062: @37105 15385 GIM_Try, /*On fail goto*//*Label 1067*/ 37124, // Rule ID 558 // 15386 GIM_CheckFeatures, GIFBS_HasSPE, 15387 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15388 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::SPERCRegClassID, 15389 // (sint_to_fp:{ *:[f64] } i32:{ *:[i32] }:$RB) => (EFDCFSI:{ *:[f64] } i32:{ *:[i32] }:$RB) 15390 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFDCFSI, 15391 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15392 // GIR_Coverage, 558, 15393 GIR_Done, 15394 // Label 1067: @37124 15395 GIM_Reject, 15396 // Label 1063: @37125 15397 GIM_Try, /*On fail goto*//*Label 1068*/ 37147, // Rule ID 879 // 15398 GIM_CheckFeatures, GIFBS_HasVSX, 15399 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 15400 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 15401 // (sint_to_fp:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$XB) => (XVCVSXDDP:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$XB) 15402 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVCVSXDDP, 15403 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 15404 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15405 // GIR_Coverage, 879, 15406 GIR_Done, 15407 // Label 1068: @37147 15408 GIM_Reject, 15409 // Label 1064: @37148 15410 GIM_Try, /*On fail goto*//*Label 1069*/ 37170, // Rule ID 882 // 15411 GIM_CheckFeatures, GIFBS_HasVSX, 15412 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 15413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 15414 // (sint_to_fp:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$XB) => (XVCVSXWSP:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$XB) 15415 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVCVSXWSP, 15416 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 15417 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15418 // GIR_Coverage, 882, 15419 GIR_Done, 15420 // Label 1069: @37170 15421 GIM_Reject, 15422 // Label 1065: @37171 15423 GIM_Reject, 15424 // Label 40: @37172 15425 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 1074*/ 37269, 15426 /*GILLT_s32*//*Label 1070*/ 37183, 15427 /*GILLT_s64*//*Label 1071*/ 37203, 0, 15428 /*GILLT_v2s64*//*Label 1072*/ 37223, 15429 /*GILLT_v4s32*//*Label 1073*/ 37246, 15430 // Label 1070: @37183 15431 GIM_Try, /*On fail goto*//*Label 1075*/ 37202, // Rule ID 581 // 15432 GIM_CheckFeatures, GIFBS_HasSPE, 15433 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15434 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 15435 // (uint_to_fp:{ *:[f32] } i32:{ *:[i32] }:$RB) => (EFSCFUI:{ *:[f32] } i32:{ *:[i32] }:$RB) 15436 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFSCFUI, 15437 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15438 // GIR_Coverage, 581, 15439 GIR_Done, 15440 // Label 1075: @37202 15441 GIM_Reject, 15442 // Label 1071: @37203 15443 GIM_Try, /*On fail goto*//*Label 1076*/ 37222, // Rule ID 560 // 15444 GIM_CheckFeatures, GIFBS_HasSPE, 15445 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::SPERCRegClassID, 15447 // (uint_to_fp:{ *:[f64] } i32:{ *:[i32] }:$RB) => (EFDCFUI:{ *:[f64] } i32:{ *:[i32] }:$RB) 15448 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFDCFUI, 15449 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15450 // GIR_Coverage, 560, 15451 GIR_Done, 15452 // Label 1076: @37222 15453 GIM_Reject, 15454 // Label 1072: @37223 15455 GIM_Try, /*On fail goto*//*Label 1077*/ 37245, // Rule ID 884 // 15456 GIM_CheckFeatures, GIFBS_HasVSX, 15457 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 15458 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 15459 // (uint_to_fp:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$XB) => (XVCVUXDDP:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$XB) 15460 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVCVUXDDP, 15461 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 15462 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15463 // GIR_Coverage, 884, 15464 GIR_Done, 15465 // Label 1077: @37245 15466 GIM_Reject, 15467 // Label 1073: @37246 15468 GIM_Try, /*On fail goto*//*Label 1078*/ 37268, // Rule ID 887 // 15469 GIM_CheckFeatures, GIFBS_HasVSX, 15470 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 15471 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 15472 // (uint_to_fp:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$XB) => (XVCVUXWSP:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$XB) 15473 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVCVUXWSP, 15474 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 15475 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15476 // GIR_Coverage, 887, 15477 GIR_Done, 15478 // Label 1078: @37268 15479 GIM_Reject, 15480 // Label 1074: @37269 15481 GIM_Reject, 15482 // Label 41: @37270 15483 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 1084*/ 37441, 15484 /*GILLT_s32*//*Label 1079*/ 37281, 15485 /*GILLT_s64*//*Label 1080*/ 37319, 15486 /*GILLT_s128*//*Label 1081*/ 37375, 15487 /*GILLT_v2s64*//*Label 1082*/ 37395, 15488 /*GILLT_v4s32*//*Label 1083*/ 37418, 15489 // Label 1079: @37281 15490 GIM_Try, /*On fail goto*//*Label 1085*/ 37318, 15491 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15492 GIM_Try, /*On fail goto*//*Label 1086*/ 37302, // Rule ID 160 // 15493 GIM_CheckFeatures, GIFBS_HasFPU, 15494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 15495 // (fabs:{ *:[f32] } f32:{ *:[f32] }:$frB) => (FABSS:{ *:[f32] } f32:{ *:[f32] }:$frB) 15496 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FABSS, 15497 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15498 // GIR_Coverage, 160, 15499 GIR_Done, 15500 // Label 1086: @37302 15501 GIM_Try, /*On fail goto*//*Label 1087*/ 37317, // Rule ID 573 // 15502 GIM_CheckFeatures, GIFBS_HasSPE, 15503 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 15504 // (fabs:{ *:[f32] } f32:{ *:[f32] }:$RA) => (EFSABS:{ *:[f32] } f32:{ *:[f32] }:$RA) 15505 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFSABS, 15506 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15507 // GIR_Coverage, 573, 15508 GIR_Done, 15509 // Label 1087: @37317 15510 GIM_Reject, 15511 // Label 1085: @37318 15512 GIM_Reject, 15513 // Label 1080: @37319 15514 GIM_Try, /*On fail goto*//*Label 1088*/ 37374, 15515 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 15516 GIM_Try, /*On fail goto*//*Label 1089*/ 37343, // Rule ID 831 // 15517 GIM_CheckFeatures, GIFBS_HasVSX, 15518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 15519 // (fabs:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSABSDP:{ *:[f64] } f64:{ *:[f64] }:$XB) 15520 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSABSDP, 15521 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 15522 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15523 // GIR_Coverage, 831, 15524 GIR_Done, 15525 // Label 1089: @37343 15526 GIM_Try, /*On fail goto*//*Label 1090*/ 37358, // Rule ID 161 // 15527 GIM_CheckFeatures, GIFBS_HasFPU, 15528 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 15529 // (fabs:{ *:[f64] } f64:{ *:[f64] }:$frB) => (FABSD:{ *:[f64] } f64:{ *:[f64] }:$frB) 15530 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FABSD, 15531 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15532 // GIR_Coverage, 161, 15533 GIR_Done, 15534 // Label 1090: @37358 15535 GIM_Try, /*On fail goto*//*Label 1091*/ 37373, // Rule ID 552 // 15536 GIM_CheckFeatures, GIFBS_HasSPE, 15537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::SPERCRegClassID, 15538 // (fabs:{ *:[f64] } f64:{ *:[f64] }:$RA) => (EFDABS:{ *:[f64] } f64:{ *:[f64] }:$RA) 15539 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFDABS, 15540 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15541 // GIR_Coverage, 552, 15542 GIR_Done, 15543 // Label 1091: @37373 15544 GIM_Reject, 15545 // Label 1088: @37374 15546 GIM_Reject, 15547 // Label 1081: @37375 15548 GIM_Try, /*On fail goto*//*Label 1092*/ 37394, // Rule ID 972 // 15549 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 15550 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 15551 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 15552 // (fabs:{ *:[f128] } f128:{ *:[f128] }:$vB) => (XSABSQP:{ *:[f128] } f128:{ *:[f128] }:$vB) 15553 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSABSQP, 15554 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15555 // GIR_Coverage, 972, 15556 GIR_Done, 15557 // Label 1092: @37394 15558 GIM_Reject, 15559 // Label 1082: @37395 15560 GIM_Try, /*On fail goto*//*Label 1093*/ 37417, // Rule ID 836 // 15561 GIM_CheckFeatures, GIFBS_HasVSX, 15562 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 15563 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 15564 // (fabs:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVABSDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) 15565 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVABSDP, 15566 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 15567 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15568 // GIR_Coverage, 836, 15569 GIR_Done, 15570 // Label 1093: @37417 15571 GIM_Reject, 15572 // Label 1083: @37418 15573 GIM_Try, /*On fail goto*//*Label 1094*/ 37440, // Rule ID 837 // 15574 GIM_CheckFeatures, GIFBS_HasVSX, 15575 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 15576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 15577 // (fabs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVABSSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) 15578 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVABSSP, 15579 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 15580 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15581 // GIR_Coverage, 837, 15582 GIR_Done, 15583 // Label 1094: @37440 15584 GIM_Reject, 15585 // Label 1084: @37441 15586 GIM_Reject, 15587 // Label 42: @37442 15588 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 1100*/ 37669, 15589 /*GILLT_s32*//*Label 1095*/ 37453, 15590 /*GILLT_s64*//*Label 1096*/ 37490, 15591 /*GILLT_s128*//*Label 1097*/ 37558, 15592 /*GILLT_v2s64*//*Label 1098*/ 37595, 15593 /*GILLT_v4s32*//*Label 1099*/ 37632, 15594 // Label 1095: @37453 15595 GIM_Try, /*On fail goto*//*Label 1101*/ 37489, // Rule ID 166 // 15596 GIM_CheckFeatures, GIFBS_HasFPU, 15597 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15598 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 15599 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 15600 // (fcopysign:{ *:[f32] } f32:{ *:[f32] }:$frB, f32:{ *:[f32] }:$frA) => (FCPSGNS:{ *:[f32] } f32:{ *:[f32] }:$frA, f32:{ *:[f32] }:$frB) 15601 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::FCPSGNS, 15602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // frD 15603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // frA 15604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // frB 15605 GIR_EraseFromParent, /*InsnID*/0, 15606 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15607 // GIR_Coverage, 166, 15608 GIR_Done, 15609 // Label 1101: @37489 15610 GIM_Reject, 15611 // Label 1096: @37490 15612 GIM_Try, /*On fail goto*//*Label 1102*/ 37557, 15613 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 15614 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 15615 GIM_Try, /*On fail goto*//*Label 1103*/ 37528, // Rule ID 835 // 15616 GIM_CheckFeatures, GIFBS_HasVSX, 15617 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 15618 // (fcopysign:{ *:[f64] } f64:{ *:[f64] }:$XB, f64:{ *:[f64] }:$XA) => (XSCPSGNDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) 15619 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSCPSGNDP, 15620 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 15621 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XA 15622 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // XB 15623 GIR_EraseFromParent, /*InsnID*/0, 15624 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15625 // GIR_Coverage, 835, 15626 GIR_Done, 15627 // Label 1103: @37528 15628 GIM_Try, /*On fail goto*//*Label 1104*/ 37556, // Rule ID 167 // 15629 GIM_CheckFeatures, GIFBS_HasFPU, 15630 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 15631 // (fcopysign:{ *:[f64] } f64:{ *:[f64] }:$frB, f64:{ *:[f64] }:$frA) => (FCPSGND:{ *:[f64] } f64:{ *:[f64] }:$frA, f64:{ *:[f64] }:$frB) 15632 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::FCPSGND, 15633 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // frD 15634 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // frA 15635 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // frB 15636 GIR_EraseFromParent, /*InsnID*/0, 15637 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15638 // GIR_Coverage, 167, 15639 GIR_Done, 15640 // Label 1104: @37556 15641 GIM_Reject, 15642 // Label 1102: @37557 15643 GIM_Reject, 15644 // Label 1097: @37558 15645 GIM_Try, /*On fail goto*//*Label 1105*/ 37594, // Rule ID 971 // 15646 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 15647 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 15648 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 15649 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 15650 // (fcopysign:{ *:[f128] } f128:{ *:[f128] }:$vB, f128:{ *:[f128] }:$vA) => (XSCPSGNQP:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 15651 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSCPSGNQP, 15652 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 15653 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vA 15654 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vB 15655 GIR_EraseFromParent, /*InsnID*/0, 15656 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15657 // GIR_Coverage, 971, 15658 GIR_Done, 15659 // Label 1105: @37594 15660 GIM_Reject, 15661 // Label 1098: @37595 15662 GIM_Try, /*On fail goto*//*Label 1106*/ 37631, // Rule ID 838 // 15663 GIM_CheckFeatures, GIFBS_HasVSX, 15664 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 15665 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 15666 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 15667 // (fcopysign:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB, v2f64:{ *:[v2f64] }:$XA) => (XVCPSGNDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) 15668 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVCPSGNDP, 15669 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 15670 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XA 15671 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // XB 15672 GIR_EraseFromParent, /*InsnID*/0, 15673 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15674 // GIR_Coverage, 838, 15675 GIR_Done, 15676 // Label 1106: @37631 15677 GIM_Reject, 15678 // Label 1099: @37632 15679 GIM_Try, /*On fail goto*//*Label 1107*/ 37668, // Rule ID 839 // 15680 GIM_CheckFeatures, GIFBS_HasVSX, 15681 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 15682 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 15683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 15684 // (fcopysign:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB, v4f32:{ *:[v4f32] }:$XA) => (XVCPSGNSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) 15685 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVCPSGNSP, 15686 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 15687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XA 15688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // XB 15689 GIR_EraseFromParent, /*InsnID*/0, 15690 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15691 // GIR_Coverage, 839, 15692 GIR_Done, 15693 // Label 1107: @37668 15694 GIM_Reject, 15695 // Label 1100: @37669 15696 GIM_Reject, 15697 // Label 43: @37670 15698 GIM_Try, /*On fail goto*//*Label 1108*/ 37682, // Rule ID 15 // 15699 // MIs[0] dst 15700 GIM_CheckIsMBB, /*MI*/0, /*Op*/0, 15701 // (br (bb:{ *:[Other] }):$dst) => (B (bb:{ *:[Other] }):$dst) 15702 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::B, 15703 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15704 // GIR_Coverage, 15, 15705 GIR_Done, 15706 // Label 1108: @37682 15707 GIM_Reject, 15708 // Label 44: @37683 15709 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 8, /*)*//*default:*//*Label 1115*/ 37816, 15710 /*GILLT_s32*//*Label 1109*/ 37696, 15711 /*GILLT_s64*//*Label 1110*/ 37716, 0, 15712 /*GILLT_v2s64*//*Label 1111*/ 37736, 15713 /*GILLT_v4s32*//*Label 1112*/ 37756, 15714 /*GILLT_v8s16*//*Label 1113*/ 37776, 15715 /*GILLT_v16s8*//*Label 1114*/ 37796, 15716 // Label 1109: @37696 15717 GIM_Try, /*On fail goto*//*Label 1116*/ 37715, // Rule ID 131 // 15718 GIM_CheckFeatures, GIFBS_IsISA3_0, 15719 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15720 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 15721 // (cttz:{ *:[i32] } i32:{ *:[i32] }:$rS) => (CNTTZW:{ *:[i32] } i32:{ *:[i32] }:$rS) 15722 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::CNTTZW, 15723 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15724 // GIR_Coverage, 131, 15725 GIR_Done, 15726 // Label 1116: @37715 15727 GIM_Reject, 15728 // Label 1110: @37716 15729 GIM_Try, /*On fail goto*//*Label 1117*/ 37735, // Rule ID 680 // 15730 GIM_CheckFeatures, GIFBS_IsISA3_0, 15731 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 15732 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 15733 // (cttz:{ *:[i64] } i64:{ *:[i64] }:$rS) => (CNTTZD:{ *:[i64] } i64:{ *:[i64] }:$rS) 15734 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::CNTTZD, 15735 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15736 // GIR_Coverage, 680, 15737 GIR_Done, 15738 // Label 1117: @37735 15739 GIM_Reject, 15740 // Label 1111: @37736 15741 GIM_Try, /*On fail goto*//*Label 1118*/ 37755, // Rule ID 531 // 15742 GIM_CheckFeatures, GIFBS_HasP9Altivec, 15743 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 15744 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 15745 // (cttz:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vB) => (VCTZD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vB) 15746 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VCTZD, 15747 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15748 // GIR_Coverage, 531, 15749 GIR_Done, 15750 // Label 1118: @37755 15751 GIM_Reject, 15752 // Label 1112: @37756 15753 GIM_Try, /*On fail goto*//*Label 1119*/ 37775, // Rule ID 530 // 15754 GIM_CheckFeatures, GIFBS_HasP9Altivec, 15755 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 15756 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 15757 // (cttz:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB) => (VCTZW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB) 15758 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VCTZW, 15759 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15760 // GIR_Coverage, 530, 15761 GIR_Done, 15762 // Label 1119: @37775 15763 GIM_Reject, 15764 // Label 1113: @37776 15765 GIM_Try, /*On fail goto*//*Label 1120*/ 37795, // Rule ID 529 // 15766 GIM_CheckFeatures, GIFBS_HasP9Altivec, 15767 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 15768 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 15769 // (cttz:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vB) => (VCTZH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vB) 15770 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VCTZH, 15771 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15772 // GIR_Coverage, 529, 15773 GIR_Done, 15774 // Label 1120: @37795 15775 GIM_Reject, 15776 // Label 1114: @37796 15777 GIM_Try, /*On fail goto*//*Label 1121*/ 37815, // Rule ID 528 // 15778 GIM_CheckFeatures, GIFBS_HasP9Altivec, 15779 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 15780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 15781 // (cttz:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vB) => (VCTZB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vB) 15782 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VCTZB, 15783 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15784 // GIR_Coverage, 528, 15785 GIR_Done, 15786 // Label 1121: @37815 15787 GIM_Reject, 15788 // Label 1115: @37816 15789 GIM_Reject, 15790 // Label 45: @37817 15791 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 8, /*)*//*default:*//*Label 1128*/ 37946, 15792 /*GILLT_s32*//*Label 1122*/ 37830, 15793 /*GILLT_s64*//*Label 1123*/ 37848, 0, 15794 /*GILLT_v2s64*//*Label 1124*/ 37866, 15795 /*GILLT_v4s32*//*Label 1125*/ 37886, 15796 /*GILLT_v8s16*//*Label 1126*/ 37906, 15797 /*GILLT_v16s8*//*Label 1127*/ 37926, 15798 // Label 1122: @37830 15799 GIM_Try, /*On fail goto*//*Label 1129*/ 37847, // Rule ID 130 // 15800 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15801 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 15802 // (ctlz:{ *:[i32] } i32:{ *:[i32] }:$rS) => (CNTLZW:{ *:[i32] } i32:{ *:[i32] }:$rS) 15803 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::CNTLZW, 15804 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15805 // GIR_Coverage, 130, 15806 GIR_Done, 15807 // Label 1129: @37847 15808 GIM_Reject, 15809 // Label 1123: @37848 15810 GIM_Try, /*On fail goto*//*Label 1130*/ 37865, // Rule ID 679 // 15811 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 15812 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 15813 // (ctlz:{ *:[i64] } i64:{ *:[i64] }:$rS) => (CNTLZD:{ *:[i64] } i64:{ *:[i64] }:$rS) 15814 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::CNTLZD, 15815 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15816 // GIR_Coverage, 679, 15817 GIR_Done, 15818 // Label 1130: @37865 15819 GIM_Reject, 15820 // Label 1124: @37866 15821 GIM_Try, /*On fail goto*//*Label 1131*/ 37885, // Rule ID 478 // 15822 GIM_CheckFeatures, GIFBS_HasP8Altivec, 15823 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 15824 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 15825 // (ctlz:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vB) => (VCLZD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vB) 15826 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VCLZD, 15827 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15828 // GIR_Coverage, 478, 15829 GIR_Done, 15830 // Label 1131: @37885 15831 GIM_Reject, 15832 // Label 1125: @37886 15833 GIM_Try, /*On fail goto*//*Label 1132*/ 37905, // Rule ID 477 // 15834 GIM_CheckFeatures, GIFBS_HasP8Altivec, 15835 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 15836 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 15837 // (ctlz:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB) => (VCLZW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB) 15838 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VCLZW, 15839 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15840 // GIR_Coverage, 477, 15841 GIR_Done, 15842 // Label 1132: @37905 15843 GIM_Reject, 15844 // Label 1126: @37906 15845 GIM_Try, /*On fail goto*//*Label 1133*/ 37925, // Rule ID 476 // 15846 GIM_CheckFeatures, GIFBS_HasP8Altivec, 15847 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 15848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 15849 // (ctlz:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vB) => (VCLZH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vB) 15850 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VCLZH, 15851 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15852 // GIR_Coverage, 476, 15853 GIR_Done, 15854 // Label 1133: @37925 15855 GIM_Reject, 15856 // Label 1127: @37926 15857 GIM_Try, /*On fail goto*//*Label 1134*/ 37945, // Rule ID 475 // 15858 GIM_CheckFeatures, GIFBS_HasP8Altivec, 15859 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 15860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 15861 // (ctlz:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vB) => (VCLZB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vB) 15862 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VCLZB, 15863 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15864 // GIR_Coverage, 475, 15865 GIR_Done, 15866 // Label 1134: @37945 15867 GIM_Reject, 15868 // Label 1128: @37946 15869 GIM_Reject, 15870 // Label 46: @37947 15871 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 8, /*)*//*default:*//*Label 1141*/ 38076, 15872 /*GILLT_s32*//*Label 1135*/ 37960, 15873 /*GILLT_s64*//*Label 1136*/ 37978, 0, 15874 /*GILLT_v2s64*//*Label 1137*/ 37996, 15875 /*GILLT_v4s32*//*Label 1138*/ 38016, 15876 /*GILLT_v8s16*//*Label 1139*/ 38036, 15877 /*GILLT_v16s8*//*Label 1140*/ 38056, 15878 // Label 1135: @37960 15879 GIM_Try, /*On fail goto*//*Label 1142*/ 37977, // Rule ID 684 // 15880 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15881 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 15882 // (ctpop:{ *:[i32] } i32:{ *:[i32] }:$rS) => (POPCNTW:{ *:[i32] } i32:{ *:[i32] }:$rS) 15883 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::POPCNTW, 15884 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15885 // GIR_Coverage, 684, 15886 GIR_Done, 15887 // Label 1142: @37977 15888 GIM_Reject, 15889 // Label 1136: @37978 15890 GIM_Try, /*On fail goto*//*Label 1143*/ 37995, // Rule ID 681 // 15891 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 15892 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 15893 // (ctpop:{ *:[i64] } i64:{ *:[i64] }:$rS) => (POPCNTD:{ *:[i64] } i64:{ *:[i64] }:$rS) 15894 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::POPCNTD, 15895 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15896 // GIR_Coverage, 681, 15897 GIR_Done, 15898 // Label 1143: @37995 15899 GIM_Reject, 15900 // Label 1137: @37996 15901 GIM_Try, /*On fail goto*//*Label 1144*/ 38015, // Rule ID 482 // 15902 GIM_CheckFeatures, GIFBS_HasP8Altivec, 15903 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 15904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 15905 // (ctpop:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vB) => (VPOPCNTD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vB) 15906 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VPOPCNTD, 15907 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15908 // GIR_Coverage, 482, 15909 GIR_Done, 15910 // Label 1144: @38015 15911 GIM_Reject, 15912 // Label 1138: @38016 15913 GIM_Try, /*On fail goto*//*Label 1145*/ 38035, // Rule ID 481 // 15914 GIM_CheckFeatures, GIFBS_HasP8Altivec, 15915 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 15916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 15917 // (ctpop:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB) => (VPOPCNTW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB) 15918 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VPOPCNTW, 15919 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15920 // GIR_Coverage, 481, 15921 GIR_Done, 15922 // Label 1145: @38035 15923 GIM_Reject, 15924 // Label 1139: @38036 15925 GIM_Try, /*On fail goto*//*Label 1146*/ 38055, // Rule ID 480 // 15926 GIM_CheckFeatures, GIFBS_HasP8Altivec, 15927 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 15928 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 15929 // (ctpop:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vB) => (VPOPCNTH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vB) 15930 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VPOPCNTH, 15931 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15932 // GIR_Coverage, 480, 15933 GIR_Done, 15934 // Label 1146: @38055 15935 GIM_Reject, 15936 // Label 1140: @38056 15937 GIM_Try, /*On fail goto*//*Label 1147*/ 38075, // Rule ID 479 // 15938 GIM_CheckFeatures, GIFBS_HasP8Altivec, 15939 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 15940 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 15941 // (ctpop:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vB) => (VPOPCNTB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vB) 15942 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::VPOPCNTB, 15943 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15944 // GIR_Coverage, 479, 15945 GIR_Done, 15946 // Label 1147: @38075 15947 GIM_Reject, 15948 // Label 1141: @38076 15949 GIM_Reject, 15950 // Label 47: @38077 15951 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 1152*/ 38168, 15952 /*GILLT_s32*//*Label 1148*/ 38088, 15953 /*GILLT_s64*//*Label 1149*/ 38108, 0, 15954 /*GILLT_v2s64*//*Label 1150*/ 38128, 15955 /*GILLT_v4s32*//*Label 1151*/ 38148, 15956 // Label 1148: @38088 15957 GIM_Try, /*On fail goto*//*Label 1153*/ 38107, // Rule ID 1119 // 15958 GIM_CheckFeatures, GIFBS_IsISA3_1, 15959 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15960 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 15961 // (bswap:{ *:[i32] } i32:{ *:[i32] }:$RS) => (BRW:{ *:[i32] } i32:{ *:[i32] }:$RS) 15962 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::BRW, 15963 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15964 // GIR_Coverage, 1119, 15965 GIR_Done, 15966 // Label 1153: @38107 15967 GIM_Reject, 15968 // Label 1149: @38108 15969 GIM_Try, /*On fail goto*//*Label 1154*/ 38127, // Rule ID 1120 // 15970 GIM_CheckFeatures, GIFBS_IsISA3_1, 15971 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 15972 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::G8RCRegClassID, 15973 // (bswap:{ *:[i64] } i64:{ *:[i64] }:$RS) => (BRD:{ *:[i64] } i64:{ *:[i64] }:$RS) 15974 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::BRD, 15975 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15976 // GIR_Coverage, 1120, 15977 GIR_Done, 15978 // Label 1154: @38127 15979 GIM_Reject, 15980 // Label 1150: @38128 15981 GIM_Try, /*On fail goto*//*Label 1155*/ 38147, // Rule ID 1018 // 15982 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 15983 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 15984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 15985 // (bswap:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$XB) => (XXBRD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$XB) 15986 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XXBRD, 15987 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15988 // GIR_Coverage, 1018, 15989 GIR_Done, 15990 // Label 1155: @38147 15991 GIM_Reject, 15992 // Label 1151: @38148 15993 GIM_Try, /*On fail goto*//*Label 1156*/ 38167, // Rule ID 1017 // 15994 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 15995 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 15996 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 15997 // (bswap:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB) => (XXBRW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB) 15998 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XXBRW, 15999 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16000 // GIR_Coverage, 1017, 16001 GIR_Done, 16002 // Label 1156: @38167 16003 GIM_Reject, 16004 // Label 1152: @38168 16005 GIM_Reject, 16006 // Label 48: @38169 16007 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 1161*/ 38278, 16008 /*GILLT_s32*//*Label 1157*/ 38180, 16009 /*GILLT_s64*//*Label 1158*/ 38200, 0, 16010 /*GILLT_v2s64*//*Label 1159*/ 38238, 16011 /*GILLT_v4s32*//*Label 1160*/ 38258, 16012 // Label 1157: @38180 16013 GIM_Try, /*On fail goto*//*Label 1162*/ 38199, // Rule ID 143 // 16014 GIM_CheckFeatures, GIFBS_HasFPU, 16015 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 16016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 16017 // (fceil:{ *:[f32] } f32:{ *:[f32] }:$frB) => (FRIPS:{ *:[f32] } f32:{ *:[f32] }:$frB) 16018 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FRIPS, 16019 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16020 // GIR_Coverage, 143, 16021 GIR_Done, 16022 // Label 1162: @38199 16023 GIM_Reject, 16024 // Label 1158: @38200 16025 GIM_Try, /*On fail goto*//*Label 1163*/ 38237, 16026 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 16027 GIM_Try, /*On fail goto*//*Label 1164*/ 38221, // Rule ID 901 // 16028 GIM_CheckFeatures, GIFBS_HasVSX, 16029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 16030 // (fceil:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSRDPIP:{ *:[f64] } f64:{ *:[f64] }:$XB) 16031 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSRDPIP, 16032 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16033 // GIR_Coverage, 901, 16034 GIR_Done, 16035 // Label 1164: @38221 16036 GIM_Try, /*On fail goto*//*Label 1165*/ 38236, // Rule ID 141 // 16037 GIM_CheckFeatures, GIFBS_HasFPU, 16038 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 16039 // (fceil:{ *:[f64] } f64:{ *:[f64] }:$frB) => (FRIPD:{ *:[f64] } f64:{ *:[f64] }:$frB) 16040 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FRIPD, 16041 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16042 // GIR_Coverage, 141, 16043 GIR_Done, 16044 // Label 1165: @38236 16045 GIM_Reject, 16046 // Label 1163: @38237 16047 GIM_Reject, 16048 // Label 1159: @38238 16049 GIM_Try, /*On fail goto*//*Label 1166*/ 38257, // Rule ID 909 // 16050 GIM_CheckFeatures, GIFBS_HasVSX, 16051 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 16052 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 16053 // (fceil:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVRDPIP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) 16054 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVRDPIP, 16055 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16056 // GIR_Coverage, 909, 16057 GIR_Done, 16058 // Label 1166: @38257 16059 GIM_Reject, 16060 // Label 1160: @38258 16061 GIM_Try, /*On fail goto*//*Label 1167*/ 38277, // Rule ID 917 // 16062 GIM_CheckFeatures, GIFBS_HasVSX, 16063 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 16064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 16065 // (fceil:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVRSPIP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) 16066 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVRSPIP, 16067 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16068 // GIR_Coverage, 917, 16069 GIR_Done, 16070 // Label 1167: @38277 16071 GIM_Reject, 16072 // Label 1161: @38278 16073 GIM_Reject, 16074 // Label 49: @38279 16075 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 1173*/ 38441, 16076 /*GILLT_s32*//*Label 1168*/ 38290, 16077 /*GILLT_s64*//*Label 1169*/ 38331, 16078 /*GILLT_s128*//*Label 1170*/ 38375, 16079 /*GILLT_v2s64*//*Label 1171*/ 38395, 16080 /*GILLT_v4s32*//*Label 1172*/ 38418, 16081 // Label 1168: @38290 16082 GIM_Try, /*On fail goto*//*Label 1174*/ 38330, 16083 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 16084 GIM_Try, /*On fail goto*//*Label 1175*/ 38311, // Rule ID 952 // 16085 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 16086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSSRCRegClassID, 16087 // (fsqrt:{ *:[f32] } f32:{ *:[f32] }:$XB) => (XSSQRTSP:{ *:[f32] } f32:{ *:[f32] }:$XB) 16088 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSSQRTSP, 16089 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16090 // GIR_Coverage, 952, 16091 GIR_Done, 16092 // Label 1175: @38311 16093 GIM_Try, /*On fail goto*//*Label 1176*/ 38329, // Rule ID 159 // 16094 GIM_CheckFeatures, GIFBS_HasFPU, 16095 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 16096 // (fsqrt:{ *:[f32] } f32:{ *:[f32] }:$frB) => (FSQRTS:{ *:[f32] } f32:{ *:[f32] }:$frB) 16097 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FSQRTS, 16098 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16099 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16100 // GIR_Coverage, 159, 16101 GIR_Done, 16102 // Label 1176: @38329 16103 GIM_Reject, 16104 // Label 1174: @38330 16105 GIM_Reject, 16106 // Label 1169: @38331 16107 GIM_Try, /*On fail goto*//*Label 1177*/ 38374, 16108 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 16109 GIM_Try, /*On fail goto*//*Label 1178*/ 38355, // Rule ID 801 // 16110 GIM_CheckFeatures, GIFBS_HasVSX, 16111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 16112 // (fsqrt:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSSQRTDP:{ *:[f64] } f64:{ *:[f64] }:$XB) 16113 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSSQRTDP, 16114 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16115 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16116 // GIR_Coverage, 801, 16117 GIR_Done, 16118 // Label 1178: @38355 16119 GIM_Try, /*On fail goto*//*Label 1179*/ 38373, // Rule ID 157 // 16120 GIM_CheckFeatures, GIFBS_HasFPU, 16121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 16122 // (fsqrt:{ *:[f64] } f64:{ *:[f64] }:$frB) => (FSQRT:{ *:[f64] } f64:{ *:[f64] }:$frB) 16123 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FSQRT, 16124 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16125 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16126 // GIR_Coverage, 157, 16127 GIR_Done, 16128 // Label 1179: @38373 16129 GIM_Reject, 16130 // Label 1177: @38374 16131 GIM_Reject, 16132 // Label 1170: @38375 16133 GIM_Try, /*On fail goto*//*Label 1180*/ 38394, // Rule ID 984 // 16134 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 16135 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 16136 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 16137 // (fsqrt:{ *:[f128] } f128:{ *:[f128] }:$vB) => (XSSQRTQP:{ *:[f128] } f128:{ *:[f128] }:$vB) 16138 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSSQRTQP, 16139 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16140 // GIR_Coverage, 984, 16141 GIR_Done, 16142 // Label 1180: @38394 16143 GIM_Reject, 16144 // Label 1171: @38395 16145 GIM_Try, /*On fail goto*//*Label 1181*/ 38417, // Rule ID 812 // 16146 GIM_CheckFeatures, GIFBS_HasVSX, 16147 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 16148 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 16149 // (fsqrt:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVSQRTDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) 16150 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVSQRTDP, 16151 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16152 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16153 // GIR_Coverage, 812, 16154 GIR_Done, 16155 // Label 1181: @38417 16156 GIM_Reject, 16157 // Label 1172: @38418 16158 GIM_Try, /*On fail goto*//*Label 1182*/ 38440, // Rule ID 814 // 16159 GIM_CheckFeatures, GIFBS_HasVSX, 16160 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 16161 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 16162 // (fsqrt:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVSQRTSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) 16163 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVSQRTSP, 16164 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16165 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16166 // GIR_Coverage, 814, 16167 GIR_Done, 16168 // Label 1182: @38440 16169 GIM_Reject, 16170 // Label 1173: @38441 16171 GIM_Reject, 16172 // Label 50: @38442 16173 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 1187*/ 38551, 16174 /*GILLT_s32*//*Label 1183*/ 38453, 16175 /*GILLT_s64*//*Label 1184*/ 38473, 0, 16176 /*GILLT_v2s64*//*Label 1185*/ 38511, 16177 /*GILLT_v4s32*//*Label 1186*/ 38531, 16178 // Label 1183: @38453 16179 GIM_Try, /*On fail goto*//*Label 1188*/ 38472, // Rule ID 151 // 16180 GIM_CheckFeatures, GIFBS_HasFPU, 16181 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 16182 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 16183 // (ffloor:{ *:[f32] } f32:{ *:[f32] }:$frB) => (FRIMS:{ *:[f32] } f32:{ *:[f32] }:$frB) 16184 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FRIMS, 16185 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16186 // GIR_Coverage, 151, 16187 GIR_Done, 16188 // Label 1188: @38472 16189 GIM_Reject, 16190 // Label 1184: @38473 16191 GIM_Try, /*On fail goto*//*Label 1189*/ 38510, 16192 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 16193 GIM_Try, /*On fail goto*//*Label 1190*/ 38494, // Rule ID 899 // 16194 GIM_CheckFeatures, GIFBS_HasVSX, 16195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 16196 // (ffloor:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSRDPIM:{ *:[f64] } f64:{ *:[f64] }:$XB) 16197 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSRDPIM, 16198 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16199 // GIR_Coverage, 899, 16200 GIR_Done, 16201 // Label 1190: @38494 16202 GIM_Try, /*On fail goto*//*Label 1191*/ 38509, // Rule ID 149 // 16203 GIM_CheckFeatures, GIFBS_HasFPU, 16204 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 16205 // (ffloor:{ *:[f64] } f64:{ *:[f64] }:$frB) => (FRIMD:{ *:[f64] } f64:{ *:[f64] }:$frB) 16206 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FRIMD, 16207 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16208 // GIR_Coverage, 149, 16209 GIR_Done, 16210 // Label 1191: @38509 16211 GIM_Reject, 16212 // Label 1189: @38510 16213 GIM_Reject, 16214 // Label 1185: @38511 16215 GIM_Try, /*On fail goto*//*Label 1192*/ 38530, // Rule ID 907 // 16216 GIM_CheckFeatures, GIFBS_HasVSX, 16217 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 16218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 16219 // (ffloor:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVRDPIM:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) 16220 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVRDPIM, 16221 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16222 // GIR_Coverage, 907, 16223 GIR_Done, 16224 // Label 1192: @38530 16225 GIM_Reject, 16226 // Label 1186: @38531 16227 GIM_Try, /*On fail goto*//*Label 1193*/ 38550, // Rule ID 915 // 16228 GIM_CheckFeatures, GIFBS_HasVSX, 16229 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 16230 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 16231 // (ffloor:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVRSPIM:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) 16232 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVRSPIM, 16233 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16234 // GIR_Coverage, 915, 16235 GIR_Done, 16236 // Label 1193: @38550 16237 GIM_Reject, 16238 // Label 1187: @38551 16239 GIM_Reject, 16240 // Label 51: @38552 16241 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 1199*/ 38764, 16242 /*GILLT_s32*//*Label 1194*/ 38563, 16243 /*GILLT_s64*//*Label 1195*/ 38623, 16244 /*GILLT_s128*//*Label 1196*/ 38686, 16245 /*GILLT_v2s64*//*Label 1197*/ 38710, 16246 /*GILLT_v4s32*//*Label 1198*/ 38737, 16247 // Label 1194: @38563 16248 GIM_Try, /*On fail goto*//*Label 1200*/ 38622, 16249 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 16250 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 16251 GIM_Try, /*On fail goto*//*Label 1201*/ 38588, // Rule ID 940 // 16252 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 16253 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSSRCRegClassID, 16254 // (strict_fadd:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSADDSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) 16255 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSADDSP, 16256 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16257 // GIR_Coverage, 940, 16258 GIR_Done, 16259 // Label 1201: @38588 16260 GIM_Try, /*On fail goto*//*Label 1202*/ 38606, // Rule ID 235 // 16261 GIM_CheckFeatures, GIFBS_HasFPU, 16262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 16263 // (strict_fadd:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) => (FADDS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) 16264 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FADDS, 16265 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16266 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16267 // GIR_Coverage, 235, 16268 GIR_Done, 16269 // Label 1202: @38606 16270 GIM_Try, /*On fail goto*//*Label 1203*/ 38621, // Rule ID 574 // 16271 GIM_CheckFeatures, GIFBS_HasSPE, 16272 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 16273 // (strict_fadd:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSADD:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) 16274 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFSADD, 16275 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16276 // GIR_Coverage, 574, 16277 GIR_Done, 16278 // Label 1203: @38621 16279 GIM_Reject, 16280 // Label 1200: @38622 16281 GIM_Reject, 16282 // Label 1195: @38623 16283 GIM_Try, /*On fail goto*//*Label 1204*/ 38685, 16284 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 16285 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 16286 GIM_Try, /*On fail goto*//*Label 1205*/ 38651, // Rule ID 757 // 16287 GIM_CheckFeatures, GIFBS_HasVSX, 16288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 16289 // (strict_fadd:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSADDDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) 16290 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSADDDP, 16291 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16292 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16293 // GIR_Coverage, 757, 16294 GIR_Done, 16295 // Label 1205: @38651 16296 GIM_Try, /*On fail goto*//*Label 1206*/ 38669, // Rule ID 233 // 16297 GIM_CheckFeatures, GIFBS_HasFPU, 16298 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 16299 // (strict_fadd:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) => (FADD:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) 16300 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FADD, 16301 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16302 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16303 // GIR_Coverage, 233, 16304 GIR_Done, 16305 // Label 1206: @38669 16306 GIM_Try, /*On fail goto*//*Label 1207*/ 38684, // Rule ID 553 // 16307 GIM_CheckFeatures, GIFBS_HasSPE, 16308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::SPERCRegClassID, 16309 // (strict_fadd:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDADD:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) 16310 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFDADD, 16311 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16312 // GIR_Coverage, 553, 16313 GIR_Done, 16314 // Label 1207: @38684 16315 GIM_Reject, 16316 // Label 1204: @38685 16317 GIM_Reject, 16318 // Label 1196: @38686 16319 GIM_Try, /*On fail goto*//*Label 1208*/ 38709, // Rule ID 975 // 16320 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 16321 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 16322 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 16323 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 16324 // (strict_fadd:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) => (XSADDQP:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 16325 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSADDQP, 16326 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16327 // GIR_Coverage, 975, 16328 GIR_Done, 16329 // Label 1208: @38709 16330 GIM_Reject, 16331 // Label 1197: @38710 16332 GIM_Try, /*On fail goto*//*Label 1209*/ 38736, // Rule ID 761 // 16333 GIM_CheckFeatures, GIFBS_HasVSX, 16334 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 16335 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 16336 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 16337 // (strict_fadd:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVADDDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) 16338 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVADDDP, 16339 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16340 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16341 // GIR_Coverage, 761, 16342 GIR_Done, 16343 // Label 1209: @38736 16344 GIM_Reject, 16345 // Label 1198: @38737 16346 GIM_Try, /*On fail goto*//*Label 1210*/ 38763, // Rule ID 763 // 16347 GIM_CheckFeatures, GIFBS_HasVSX, 16348 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 16349 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 16350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 16351 // (strict_fadd:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVADDSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) 16352 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVADDSP, 16353 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16354 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16355 // GIR_Coverage, 763, 16356 GIR_Done, 16357 // Label 1210: @38763 16358 GIM_Reject, 16359 // Label 1199: @38764 16360 GIM_Reject, 16361 // Label 52: @38765 16362 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 1216*/ 38977, 16363 /*GILLT_s32*//*Label 1211*/ 38776, 16364 /*GILLT_s64*//*Label 1212*/ 38836, 16365 /*GILLT_s128*//*Label 1213*/ 38899, 16366 /*GILLT_v2s64*//*Label 1214*/ 38923, 16367 /*GILLT_v4s32*//*Label 1215*/ 38950, 16368 // Label 1211: @38776 16369 GIM_Try, /*On fail goto*//*Label 1217*/ 38835, 16370 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 16371 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 16372 GIM_Try, /*On fail goto*//*Label 1218*/ 38801, // Rule ID 944 // 16373 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 16374 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSSRCRegClassID, 16375 // (strict_fsub:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSSUBSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) 16376 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSSUBSP, 16377 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16378 // GIR_Coverage, 944, 16379 GIR_Done, 16380 // Label 1218: @38801 16381 GIM_Try, /*On fail goto*//*Label 1219*/ 38819, // Rule ID 247 // 16382 GIM_CheckFeatures, GIFBS_HasFPU, 16383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 16384 // (strict_fsub:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) => (FSUBS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) 16385 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FSUBS, 16386 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16387 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16388 // GIR_Coverage, 247, 16389 GIR_Done, 16390 // Label 1219: @38819 16391 GIM_Try, /*On fail goto*//*Label 1220*/ 38834, // Rule ID 592 // 16392 GIM_CheckFeatures, GIFBS_HasSPE, 16393 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 16394 // (strict_fsub:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSSUB:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) 16395 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFSSUB, 16396 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16397 // GIR_Coverage, 592, 16398 GIR_Done, 16399 // Label 1220: @38834 16400 GIM_Reject, 16401 // Label 1217: @38835 16402 GIM_Reject, 16403 // Label 1212: @38836 16404 GIM_Try, /*On fail goto*//*Label 1221*/ 38898, 16405 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 16406 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 16407 GIM_Try, /*On fail goto*//*Label 1222*/ 38864, // Rule ID 769 // 16408 GIM_CheckFeatures, GIFBS_HasVSX, 16409 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 16410 // (strict_fsub:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSSUBDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) 16411 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSSUBDP, 16412 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16413 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16414 // GIR_Coverage, 769, 16415 GIR_Done, 16416 // Label 1222: @38864 16417 GIM_Try, /*On fail goto*//*Label 1223*/ 38882, // Rule ID 245 // 16418 GIM_CheckFeatures, GIFBS_HasFPU, 16419 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 16420 // (strict_fsub:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) => (FSUB:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) 16421 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FSUB, 16422 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16423 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16424 // GIR_Coverage, 245, 16425 GIR_Done, 16426 // Label 1223: @38882 16427 GIM_Try, /*On fail goto*//*Label 1224*/ 38897, // Rule ID 571 // 16428 GIM_CheckFeatures, GIFBS_HasSPE, 16429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::SPERCRegClassID, 16430 // (strict_fsub:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDSUB:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) 16431 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFDSUB, 16432 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16433 // GIR_Coverage, 571, 16434 GIR_Done, 16435 // Label 1224: @38897 16436 GIM_Reject, 16437 // Label 1221: @38898 16438 GIM_Reject, 16439 // Label 1213: @38899 16440 GIM_Try, /*On fail goto*//*Label 1225*/ 38922, // Rule ID 979 // 16441 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 16442 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 16443 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 16444 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 16445 // (strict_fsub:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) => (XSSUBQP:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 16446 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSSUBQP, 16447 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16448 // GIR_Coverage, 979, 16449 GIR_Done, 16450 // Label 1225: @38922 16451 GIM_Reject, 16452 // Label 1214: @38923 16453 GIM_Try, /*On fail goto*//*Label 1226*/ 38949, // Rule ID 771 // 16454 GIM_CheckFeatures, GIFBS_HasVSX, 16455 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 16456 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 16457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 16458 // (strict_fsub:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVSUBDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) 16459 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVSUBDP, 16460 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16461 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16462 // GIR_Coverage, 771, 16463 GIR_Done, 16464 // Label 1226: @38949 16465 GIM_Reject, 16466 // Label 1215: @38950 16467 GIM_Try, /*On fail goto*//*Label 1227*/ 38976, // Rule ID 773 // 16468 GIM_CheckFeatures, GIFBS_HasVSX, 16469 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 16470 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 16471 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 16472 // (strict_fsub:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVSUBSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) 16473 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVSUBSP, 16474 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16475 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16476 // GIR_Coverage, 773, 16477 GIR_Done, 16478 // Label 1227: @38976 16479 GIM_Reject, 16480 // Label 1216: @38977 16481 GIM_Reject, 16482 // Label 53: @38978 16483 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 1233*/ 39190, 16484 /*GILLT_s32*//*Label 1228*/ 38989, 16485 /*GILLT_s64*//*Label 1229*/ 39049, 16486 /*GILLT_s128*//*Label 1230*/ 39112, 16487 /*GILLT_v2s64*//*Label 1231*/ 39136, 16488 /*GILLT_v4s32*//*Label 1232*/ 39163, 16489 // Label 1228: @38989 16490 GIM_Try, /*On fail goto*//*Label 1234*/ 39048, 16491 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 16492 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 16493 GIM_Try, /*On fail goto*//*Label 1235*/ 39014, // Rule ID 942 // 16494 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 16495 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSSRCRegClassID, 16496 // (strict_fmul:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSMULSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) 16497 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSMULSP, 16498 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16499 // GIR_Coverage, 942, 16500 GIR_Done, 16501 // Label 1235: @39014 16502 GIM_Try, /*On fail goto*//*Label 1236*/ 39032, // Rule ID 243 // 16503 GIM_CheckFeatures, GIFBS_HasFPU, 16504 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 16505 // (strict_fmul:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC) => (FMULS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC) 16506 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FMULS, 16507 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16508 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16509 // GIR_Coverage, 243, 16510 GIR_Done, 16511 // Label 1236: @39032 16512 GIM_Try, /*On fail goto*//*Label 1237*/ 39047, // Rule ID 588 // 16513 GIM_CheckFeatures, GIFBS_HasSPE, 16514 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 16515 // (strict_fmul:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSMUL:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) 16516 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFSMUL, 16517 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16518 // GIR_Coverage, 588, 16519 GIR_Done, 16520 // Label 1237: @39047 16521 GIM_Reject, 16522 // Label 1234: @39048 16523 GIM_Reject, 16524 // Label 1229: @39049 16525 GIM_Try, /*On fail goto*//*Label 1238*/ 39111, 16526 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 16527 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 16528 GIM_Try, /*On fail goto*//*Label 1239*/ 39077, // Rule ID 759 // 16529 GIM_CheckFeatures, GIFBS_HasVSX, 16530 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 16531 // (strict_fmul:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSMULDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) 16532 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSMULDP, 16533 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16534 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16535 // GIR_Coverage, 759, 16536 GIR_Done, 16537 // Label 1239: @39077 16538 GIM_Try, /*On fail goto*//*Label 1240*/ 39095, // Rule ID 241 // 16539 GIM_CheckFeatures, GIFBS_HasFPU, 16540 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 16541 // (strict_fmul:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC) => (FMUL:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC) 16542 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FMUL, 16543 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16544 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16545 // GIR_Coverage, 241, 16546 GIR_Done, 16547 // Label 1240: @39095 16548 GIM_Try, /*On fail goto*//*Label 1241*/ 39110, // Rule ID 567 // 16549 GIM_CheckFeatures, GIFBS_HasSPE, 16550 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::SPERCRegClassID, 16551 // (strict_fmul:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDMUL:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) 16552 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFDMUL, 16553 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16554 // GIR_Coverage, 567, 16555 GIR_Done, 16556 // Label 1241: @39110 16557 GIM_Reject, 16558 // Label 1238: @39111 16559 GIM_Reject, 16560 // Label 1230: @39112 16561 GIM_Try, /*On fail goto*//*Label 1242*/ 39135, // Rule ID 977 // 16562 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 16563 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 16564 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 16565 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 16566 // (strict_fmul:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) => (XSMULQP:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 16567 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSMULQP, 16568 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16569 // GIR_Coverage, 977, 16570 GIR_Done, 16571 // Label 1242: @39135 16572 GIM_Reject, 16573 // Label 1231: @39136 16574 GIM_Try, /*On fail goto*//*Label 1243*/ 39162, // Rule ID 765 // 16575 GIM_CheckFeatures, GIFBS_HasVSX, 16576 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 16577 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 16578 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 16579 // (strict_fmul:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVMULDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) 16580 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVMULDP, 16581 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16582 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16583 // GIR_Coverage, 765, 16584 GIR_Done, 16585 // Label 1243: @39162 16586 GIM_Reject, 16587 // Label 1232: @39163 16588 GIM_Try, /*On fail goto*//*Label 1244*/ 39189, // Rule ID 767 // 16589 GIM_CheckFeatures, GIFBS_HasVSX, 16590 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 16591 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 16592 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 16593 // (strict_fmul:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVMULSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) 16594 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVMULSP, 16595 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16596 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16597 // GIR_Coverage, 767, 16598 GIR_Done, 16599 // Label 1244: @39189 16600 GIM_Reject, 16601 // Label 1233: @39190 16602 GIM_Reject, 16603 // Label 54: @39191 16604 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 1250*/ 39403, 16605 /*GILLT_s32*//*Label 1245*/ 39202, 16606 /*GILLT_s64*//*Label 1246*/ 39262, 16607 /*GILLT_s128*//*Label 1247*/ 39325, 16608 /*GILLT_v2s64*//*Label 1248*/ 39349, 16609 /*GILLT_v4s32*//*Label 1249*/ 39376, 16610 // Label 1245: @39202 16611 GIM_Try, /*On fail goto*//*Label 1251*/ 39261, 16612 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 16613 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 16614 GIM_Try, /*On fail goto*//*Label 1252*/ 39227, // Rule ID 946 // 16615 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 16616 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSSRCRegClassID, 16617 // (strict_fdiv:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSDIVSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) 16618 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSDIVSP, 16619 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16620 // GIR_Coverage, 946, 16621 GIR_Done, 16622 // Label 1252: @39227 16623 GIM_Try, /*On fail goto*//*Label 1253*/ 39245, // Rule ID 239 // 16624 GIM_CheckFeatures, GIFBS_HasFPU, 16625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 16626 // (strict_fdiv:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) => (FDIVS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) 16627 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FDIVS, 16628 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16629 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16630 // GIR_Coverage, 239, 16631 GIR_Done, 16632 // Label 1253: @39245 16633 GIM_Try, /*On fail goto*//*Label 1254*/ 39260, // Rule ID 586 // 16634 GIM_CheckFeatures, GIFBS_HasSPE, 16635 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::GPRCRegClassID, 16636 // (strict_fdiv:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSDIV:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) 16637 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFSDIV, 16638 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16639 // GIR_Coverage, 586, 16640 GIR_Done, 16641 // Label 1254: @39260 16642 GIM_Reject, 16643 // Label 1251: @39261 16644 GIM_Reject, 16645 // Label 1246: @39262 16646 GIM_Try, /*On fail goto*//*Label 1255*/ 39324, 16647 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 16648 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 16649 GIM_Try, /*On fail goto*//*Label 1256*/ 39290, // Rule ID 798 // 16650 GIM_CheckFeatures, GIFBS_HasVSX, 16651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 16652 // (strict_fdiv:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSDIVDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) 16653 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSDIVDP, 16654 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16655 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16656 // GIR_Coverage, 798, 16657 GIR_Done, 16658 // Label 1256: @39290 16659 GIM_Try, /*On fail goto*//*Label 1257*/ 39308, // Rule ID 237 // 16660 GIM_CheckFeatures, GIFBS_HasFPU, 16661 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 16662 // (strict_fdiv:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) => (FDIV:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) 16663 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FDIV, 16664 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16665 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16666 // GIR_Coverage, 237, 16667 GIR_Done, 16668 // Label 1257: @39308 16669 GIM_Try, /*On fail goto*//*Label 1258*/ 39323, // Rule ID 565 // 16670 GIM_CheckFeatures, GIFBS_HasSPE, 16671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::SPERCRegClassID, 16672 // (strict_fdiv:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDDIV:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) 16673 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::EFDDIV, 16674 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16675 // GIR_Coverage, 565, 16676 GIR_Done, 16677 // Label 1258: @39323 16678 GIM_Reject, 16679 // Label 1255: @39324 16680 GIM_Reject, 16681 // Label 1247: @39325 16682 GIM_Try, /*On fail goto*//*Label 1259*/ 39348, // Rule ID 981 // 16683 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 16684 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 16685 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 16686 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 16687 // (strict_fdiv:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) => (XSDIVQP:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 16688 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSDIVQP, 16689 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16690 // GIR_Coverage, 981, 16691 GIR_Done, 16692 // Label 1259: @39348 16693 GIM_Reject, 16694 // Label 1248: @39349 16695 GIM_Try, /*On fail goto*//*Label 1260*/ 39375, // Rule ID 807 // 16696 GIM_CheckFeatures, GIFBS_HasVSX, 16697 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 16698 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 16699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 16700 // (strict_fdiv:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVDIVDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) 16701 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVDIVDP, 16702 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16703 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16704 // GIR_Coverage, 807, 16705 GIR_Done, 16706 // Label 1260: @39375 16707 GIM_Reject, 16708 // Label 1249: @39376 16709 GIM_Try, /*On fail goto*//*Label 1261*/ 39402, // Rule ID 809 // 16710 GIM_CheckFeatures, GIFBS_HasVSX, 16711 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 16712 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 16713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 16714 // (strict_fdiv:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVDIVSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) 16715 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVDIVSP, 16716 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16717 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16718 // GIR_Coverage, 809, 16719 GIR_Done, 16720 // Label 1261: @39402 16721 GIM_Reject, 16722 // Label 1250: @39403 16723 GIM_Reject, 16724 // Label 55: @39404 16725 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 1267*/ 39994, 16726 /*GILLT_s32*//*Label 1262*/ 39415, 16727 /*GILLT_s64*//*Label 1263*/ 39571, 16728 /*GILLT_s128*//*Label 1264*/ 39727, 16729 /*GILLT_v2s64*//*Label 1265*/ 39816, 16730 /*GILLT_v4s32*//*Label 1266*/ 39905, 16731 // Label 1262: @39415 16732 GIM_Try, /*On fail goto*//*Label 1268*/ 39570, 16733 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 16734 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 16735 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 16736 GIM_Try, /*On fail goto*//*Label 1269*/ 39474, // Rule ID 956 // 16737 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 16738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSSRCRegClassID, 16739 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 16740 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 16741 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 16742 GIM_CheckIsSafeToFold, /*InsnID*/1, 16743 // (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, (fneg:{ *:[f32] } f32:{ *:[f32] }:$XTi)) => (XSMSUBASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) 16744 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSMSUBASP, 16745 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 16746 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi 16747 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // XA 16748 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 16749 GIR_EraseFromParent, /*InsnID*/0, 16750 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16751 // GIR_Coverage, 956, 16752 GIR_Done, 16753 // Label 1269: @39474 16754 GIM_Try, /*On fail goto*//*Label 1270*/ 39506, // Rule ID 954 // 16755 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 16756 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSSRCRegClassID, 16757 // (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, f32:{ *:[f32] }:$XTi) => (XSMADDASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) 16758 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSMADDASP, 16759 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 16760 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XTi 16761 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // XA 16762 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 16763 GIR_EraseFromParent, /*InsnID*/0, 16764 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16765 // GIR_Coverage, 954, 16766 GIR_Done, 16767 // Label 1270: @39506 16768 GIM_Try, /*On fail goto*//*Label 1271*/ 39551, // Rule ID 221 // 16769 GIM_CheckFeatures, GIFBS_HasFPU, 16770 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 16771 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 16772 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 16773 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 16774 GIM_CheckIsSafeToFold, /*InsnID*/1, 16775 // (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, (fneg:{ *:[f32] } f32:{ *:[f32] }:$FRB)) => (FMSUBS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB) 16776 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::FMSUBS, 16777 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // FRT 16778 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // FRA 16779 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // FRC 16780 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRB 16781 GIR_EraseFromParent, /*InsnID*/0, 16782 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16783 // GIR_Coverage, 221, 16784 GIR_Done, 16785 // Label 1271: @39551 16786 GIM_Try, /*On fail goto*//*Label 1272*/ 39569, // Rule ID 217 // 16787 GIM_CheckFeatures, GIFBS_HasFPU, 16788 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 16789 // (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB) => (FMADDS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB) 16790 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FMADDS, 16791 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16792 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16793 // GIR_Coverage, 217, 16794 GIR_Done, 16795 // Label 1272: @39569 16796 GIM_Reject, 16797 // Label 1268: @39570 16798 GIM_Reject, 16799 // Label 1263: @39571 16800 GIM_Try, /*On fail goto*//*Label 1273*/ 39726, 16801 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 16802 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 16803 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 16804 GIM_Try, /*On fail goto*//*Label 1274*/ 39630, // Rule ID 777 // 16805 GIM_CheckFeatures, GIFBS_HasVSX, 16806 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 16807 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 16808 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 16809 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 16810 GIM_CheckIsSafeToFold, /*InsnID*/1, 16811 // (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, (fneg:{ *:[f64] } f64:{ *:[f64] }:$XTi)) => (XSMSUBADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) 16812 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSMSUBADP, 16813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 16814 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi 16815 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // XA 16816 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 16817 GIR_EraseFromParent, /*InsnID*/0, 16818 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16819 // GIR_Coverage, 777, 16820 GIR_Done, 16821 // Label 1274: @39630 16822 GIM_Try, /*On fail goto*//*Label 1275*/ 39662, // Rule ID 775 // 16823 GIM_CheckFeatures, GIFBS_HasVSX, 16824 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 16825 // (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, f64:{ *:[f64] }:$XTi) => (XSMADDADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) 16826 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSMADDADP, 16827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 16828 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XTi 16829 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // XA 16830 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 16831 GIR_EraseFromParent, /*InsnID*/0, 16832 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16833 // GIR_Coverage, 775, 16834 GIR_Done, 16835 // Label 1275: @39662 16836 GIM_Try, /*On fail goto*//*Label 1276*/ 39707, // Rule ID 219 // 16837 GIM_CheckFeatures, GIFBS_HasFPU, 16838 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 16839 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 16840 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 16841 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 16842 GIM_CheckIsSafeToFold, /*InsnID*/1, 16843 // (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, (fneg:{ *:[f64] } f64:{ *:[f64] }:$FRB)) => (FMSUB:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB) 16844 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::FMSUB, 16845 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // FRT 16846 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // FRA 16847 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // FRC 16848 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRB 16849 GIR_EraseFromParent, /*InsnID*/0, 16850 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16851 // GIR_Coverage, 219, 16852 GIR_Done, 16853 // Label 1276: @39707 16854 GIM_Try, /*On fail goto*//*Label 1277*/ 39725, // Rule ID 215 // 16855 GIM_CheckFeatures, GIFBS_HasFPU, 16856 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 16857 // (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB) => (FMADD:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB) 16858 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FMADD, 16859 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 16860 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16861 // GIR_Coverage, 215, 16862 GIR_Done, 16863 // Label 1277: @39725 16864 GIM_Reject, 16865 // Label 1273: @39726 16866 GIM_Reject, 16867 // Label 1264: @39727 16868 GIM_Try, /*On fail goto*//*Label 1278*/ 39815, 16869 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 16870 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s128, 16871 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s128, 16872 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 16873 GIM_Try, /*On fail goto*//*Label 1279*/ 39786, // Rule ID 987 // 16874 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 16875 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 16876 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 16877 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128, 16878 GIM_CheckIsSafeToFold, /*InsnID*/1, 16879 // (strict_fma:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB, (fneg:{ *:[f128] } f128:{ *:[f128] }:$vTi)) => (XSMSUBQP:{ *:[f128] } f128:{ *:[f128] }:$vTi, f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 16880 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSMSUBQP, 16881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 16882 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vTi 16883 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vA 16884 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 16885 GIR_EraseFromParent, /*InsnID*/0, 16886 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16887 // GIR_Coverage, 987, 16888 GIR_Done, 16889 // Label 1279: @39786 16890 GIM_Try, /*On fail goto*//*Label 1280*/ 39814, // Rule ID 985 // 16891 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 16892 // (strict_fma:{ *:[f128] } f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB, f128:{ *:[f128] }:$vTi) => (XSMADDQP:{ *:[f128] } f128:{ *:[f128] }:$vTi, f128:{ *:[f128] }:$vA, f128:{ *:[f128] }:$vB) 16893 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XSMADDQP, 16894 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vT 16895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vTi 16896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vA 16897 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vB 16898 GIR_EraseFromParent, /*InsnID*/0, 16899 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16900 // GIR_Coverage, 985, 16901 GIR_Done, 16902 // Label 1280: @39814 16903 GIM_Reject, 16904 // Label 1278: @39815 16905 GIM_Reject, 16906 // Label 1265: @39816 16907 GIM_Try, /*On fail goto*//*Label 1281*/ 39904, 16908 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 16909 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 16910 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 16911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 16912 GIM_Try, /*On fail goto*//*Label 1282*/ 39875, // Rule ID 787 // 16913 GIM_CheckFeatures, GIFBS_HasVSX, 16914 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 16915 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 16916 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, 16917 GIM_CheckIsSafeToFold, /*InsnID*/1, 16918 // (strict_fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, (fneg:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi)) => (XVMSUBADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) 16919 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVMSUBADP, 16920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 16921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi 16922 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // XA 16923 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 16924 GIR_EraseFromParent, /*InsnID*/0, 16925 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16926 // GIR_Coverage, 787, 16927 GIR_Done, 16928 // Label 1282: @39875 16929 GIM_Try, /*On fail goto*//*Label 1283*/ 39903, // Rule ID 783 // 16930 GIM_CheckFeatures, GIFBS_HasVSX, 16931 // (strict_fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, v2f64:{ *:[v2f64] }:$XTi) => (XVMADDADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) 16932 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVMADDADP, 16933 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 16934 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XTi 16935 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // XA 16936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 16937 GIR_EraseFromParent, /*InsnID*/0, 16938 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16939 // GIR_Coverage, 783, 16940 GIR_Done, 16941 // Label 1283: @39903 16942 GIM_Reject, 16943 // Label 1281: @39904 16944 GIM_Reject, 16945 // Label 1266: @39905 16946 GIM_Try, /*On fail goto*//*Label 1284*/ 39993, 16947 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 16948 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 16949 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 16950 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 16951 GIM_Try, /*On fail goto*//*Label 1285*/ 39964, // Rule ID 789 // 16952 GIM_CheckFeatures, GIFBS_HasVSX, 16953 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 16954 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 16955 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 16956 GIM_CheckIsSafeToFold, /*InsnID*/1, 16957 // (strict_fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB, (fneg:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi)) => (XVMSUBASP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) 16958 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVMSUBASP, 16959 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 16960 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi 16961 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // XA 16962 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 16963 GIR_EraseFromParent, /*InsnID*/0, 16964 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16965 // GIR_Coverage, 789, 16966 GIR_Done, 16967 // Label 1285: @39964 16968 GIM_Try, /*On fail goto*//*Label 1286*/ 39992, // Rule ID 785 // 16969 GIM_CheckFeatures, GIFBS_HasVSX, 16970 // (strict_fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB, v4f32:{ *:[v4f32] }:$XTi) => (XVMADDASP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) 16971 GIR_BuildMI, /*InsnID*/0, /*Opcode*/PPC::XVMADDASP, 16972 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // XT 16973 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // XTi 16974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // XA 16975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // XB 16976 GIR_EraseFromParent, /*InsnID*/0, 16977 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16978 // GIR_Coverage, 785, 16979 GIR_Done, 16980 // Label 1286: @39992 16981 GIM_Reject, 16982 // Label 1284: @39993 16983 GIM_Reject, 16984 // Label 1267: @39994 16985 GIM_Reject, 16986 // Label 56: @39995 16987 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 6, /*)*//*default:*//*Label 1292*/ 40157, 16988 /*GILLT_s32*//*Label 1287*/ 40006, 16989 /*GILLT_s64*//*Label 1288*/ 40047, 16990 /*GILLT_s128*//*Label 1289*/ 40091, 16991 /*GILLT_v2s64*//*Label 1290*/ 40111, 16992 /*GILLT_v4s32*//*Label 1291*/ 40134, 16993 // Label 1287: @40006 16994 GIM_Try, /*On fail goto*//*Label 1293*/ 40046, 16995 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 16996 GIM_Try, /*On fail goto*//*Label 1294*/ 40027, // Rule ID 951 // 16997 GIM_CheckFeatures, GIFBS_HasP8Vector_HasVSX, 16998 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSSRCRegClassID, 16999 // (strict_fsqrt:{ *:[f32] } f32:{ *:[f32] }:$XB) => (XSSQRTSP:{ *:[f32] } f32:{ *:[f32] }:$XB) 17000 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSSQRTSP, 17001 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17002 // GIR_Coverage, 951, 17003 GIR_Done, 17004 // Label 1294: @40027 17005 GIM_Try, /*On fail goto*//*Label 1295*/ 40045, // Rule ID 158 // 17006 GIM_CheckFeatures, GIFBS_HasFPU, 17007 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F4RCRegClassID, 17008 // (strict_fsqrt:{ *:[f32] } f32:{ *:[f32] }:$frB) => (FSQRTS:{ *:[f32] } f32:{ *:[f32] }:$frB) 17009 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FSQRTS, 17010 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 17011 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17012 // GIR_Coverage, 158, 17013 GIR_Done, 17014 // Label 1295: @40045 17015 GIM_Reject, 17016 // Label 1293: @40046 17017 GIM_Reject, 17018 // Label 1288: @40047 17019 GIM_Try, /*On fail goto*//*Label 1296*/ 40090, 17020 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 17021 GIM_Try, /*On fail goto*//*Label 1297*/ 40071, // Rule ID 800 // 17022 GIM_CheckFeatures, GIFBS_HasVSX, 17023 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSFRCRegClassID, 17024 // (strict_fsqrt:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSSQRTDP:{ *:[f64] } f64:{ *:[f64] }:$XB) 17025 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSSQRTDP, 17026 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 17027 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17028 // GIR_Coverage, 800, 17029 GIR_Done, 17030 // Label 1297: @40071 17031 GIM_Try, /*On fail goto*//*Label 1298*/ 40089, // Rule ID 156 // 17032 GIM_CheckFeatures, GIFBS_HasFPU, 17033 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::F8RCRegClassID, 17034 // (strict_fsqrt:{ *:[f64] } f64:{ *:[f64] }:$frB) => (FSQRT:{ *:[f64] } f64:{ *:[f64] }:$frB) 17035 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::FSQRT, 17036 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 17037 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17038 // GIR_Coverage, 156, 17039 GIR_Done, 17040 // Label 1298: @40089 17041 GIM_Reject, 17042 // Label 1296: @40090 17043 GIM_Reject, 17044 // Label 1289: @40091 17045 GIM_Try, /*On fail goto*//*Label 1299*/ 40110, // Rule ID 983 // 17046 GIM_CheckFeatures, GIFBS_HasP9Vector_HasVSX, 17047 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 17048 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VRRCRegClassID, 17049 // (strict_fsqrt:{ *:[f128] } f128:{ *:[f128] }:$vB) => (XSSQRTQP:{ *:[f128] } f128:{ *:[f128] }:$vB) 17050 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XSSQRTQP, 17051 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17052 // GIR_Coverage, 983, 17053 GIR_Done, 17054 // Label 1299: @40110 17055 GIM_Reject, 17056 // Label 1290: @40111 17057 GIM_Try, /*On fail goto*//*Label 1300*/ 40133, // Rule ID 811 // 17058 GIM_CheckFeatures, GIFBS_HasVSX, 17059 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 17060 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 17061 // (strict_fsqrt:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVSQRTDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) 17062 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVSQRTDP, 17063 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 17064 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17065 // GIR_Coverage, 811, 17066 GIR_Done, 17067 // Label 1300: @40133 17068 GIM_Reject, 17069 // Label 1291: @40134 17070 GIM_Try, /*On fail goto*//*Label 1301*/ 40156, // Rule ID 813 // 17071 GIM_CheckFeatures, GIFBS_HasVSX, 17072 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 17073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/PPC::VSRCRegClassID, 17074 // (strict_fsqrt:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVSQRTSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) 17075 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/PPC::XVSQRTSP, 17076 GIR_AddImplicitUse, /*InsnID*/0, PPC::RM, 17077 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17078 // GIR_Coverage, 813, 17079 GIR_Done, 17080 // Label 1301: @40156 17081 GIM_Reject, 17082 // Label 1292: @40157 17083 GIM_Reject, 17084 // Label 57: @40158 17085 GIM_Reject, 17086 }; 17087 return MatchTable0; 17088} 17089#endif // ifdef GET_GLOBALISEL_IMPL 17090#ifdef GET_GLOBALISEL_PREDICATES_DECL 17091PredicateBitset AvailableModuleFeatures; 17092mutable PredicateBitset AvailableFunctionFeatures; 17093PredicateBitset getAvailableFeatures() const { 17094 return AvailableModuleFeatures | AvailableFunctionFeatures; 17095} 17096PredicateBitset 17097computeAvailableModuleFeatures(const PPCSubtarget *Subtarget) const; 17098PredicateBitset 17099computeAvailableFunctionFeatures(const PPCSubtarget *Subtarget, 17100 const MachineFunction *MF) const; 17101void setupGeneratedPerFunctionState(MachineFunction &MF) override; 17102#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL 17103#ifdef GET_GLOBALISEL_PREDICATES_INIT 17104AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)), 17105AvailableFunctionFeatures() 17106#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT 17107