1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Assembly Matcher Source Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10#ifdef GET_ASSEMBLER_HEADER 11#undef GET_ASSEMBLER_HEADER 12 // This should be included into the middle of the declaration of 13 // your subclasses implementation of MCTargetAsmParser. 14 FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const; 15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, 16 const OperandVector &Operands, 17 const SmallBitVector &OptionalOperandsMask); 18 void convertToMapAndConstraints(unsigned Kind, 19 const OperandVector &Operands) override; 20 unsigned MatchInstructionImpl(const OperandVector &Operands, 21 MCInst &Inst, 22 uint64_t &ErrorInfo, 23 FeatureBitset &MissingFeatures, 24 bool matchingInlineAsm, 25 unsigned VariantID = 0); 26 unsigned MatchInstructionImpl(const OperandVector &Operands, 27 MCInst &Inst, 28 uint64_t &ErrorInfo, 29 bool matchingInlineAsm, 30 unsigned VariantID = 0) { 31 FeatureBitset MissingFeatures; 32 return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures, 33 matchingInlineAsm, VariantID); 34 } 35 36 OperandMatchResultTy MatchOperandParserImpl( 37 OperandVector &Operands, 38 StringRef Mnemonic, 39 bool ParseForAllFeatures = false); 40 OperandMatchResultTy tryCustomParseOperand( 41 OperandVector &Operands, 42 unsigned MCK); 43 44#endif // GET_ASSEMBLER_HEADER_INFO 45 46 47#ifdef GET_OPERAND_DIAGNOSTIC_TYPES 48#undef GET_OPERAND_DIAGNOSTIC_TYPES 49 50 Match_InvalidBareSymbol, 51 Match_InvalidCLUIImm, 52 Match_InvalidCSRSystemRegister, 53 Match_InvalidCallSymbol, 54 Match_InvalidFRMArg, 55 Match_InvalidFenceArg, 56 Match_InvalidImmXLenLI, 57 Match_InvalidImmZero, 58 Match_InvalidPseudoJumpSymbol, 59 Match_InvalidRnumArg, 60 Match_InvalidSImm10Lsb0000NonZero, 61 Match_InvalidSImm12, 62 Match_InvalidSImm12Lsb0, 63 Match_InvalidSImm12Lsb00000, 64 Match_InvalidSImm13Lsb0, 65 Match_InvalidSImm21Lsb0JAL, 66 Match_InvalidSImm5, 67 Match_InvalidSImm5Plus1, 68 Match_InvalidSImm6, 69 Match_InvalidSImm6NonZero, 70 Match_InvalidSImm9Lsb0, 71 Match_InvalidTPRelAddSymbol, 72 Match_InvalidUImm10Lsb00NonZero, 73 Match_InvalidUImm2, 74 Match_InvalidUImm20AUIPC, 75 Match_InvalidUImm20LUI, 76 Match_InvalidUImm3, 77 Match_InvalidUImm5, 78 Match_InvalidUImm7, 79 Match_InvalidUImm7Lsb00, 80 Match_InvalidUImm8Lsb00, 81 Match_InvalidUImm8Lsb000, 82 Match_InvalidUImm9Lsb000, 83 Match_InvalidUImmLog2XLen, 84 Match_InvalidUImmLog2XLenHalf, 85 Match_InvalidUImmLog2XLenNonZero, 86 Match_InvalidVMaskRegister, 87 Match_InvalidVTypeI, 88 END_OPERAND_DIAGNOSTIC_TYPES 89#endif // GET_OPERAND_DIAGNOSTIC_TYPES 90 91 92#ifdef GET_REGISTER_MATCHER 93#undef GET_REGISTER_MATCHER 94 95// Bits for subtarget features that participate in instruction matching. 96enum SubtargetFeatureBits : uint8_t { 97 Feature_HasStdExtMBit = 9, 98 Feature_HasStdExtMOrZmmulBit = 10, 99 Feature_HasStdExtABit = 1, 100 Feature_HasStdExtFBit = 7, 101 Feature_HasStdExtDBit = 6, 102 Feature_HasStdExtHBit = 8, 103 Feature_HasStdExtZihintpauseBit = 34, 104 Feature_HasStdExtZihintntlBit = 33, 105 Feature_HasStdExtZfhminBit = 25, 106 Feature_HasStdExtZfhBit = 23, 107 Feature_HasStdExtZfhOrZfhminBit = 24, 108 Feature_HasStdExtZfinxBit = 26, 109 Feature_HasStdExtZdinxBit = 22, 110 Feature_HasStdExtZhinxminBit = 29, 111 Feature_HasStdExtZhinxBit = 27, 112 Feature_HasStdExtZhinxOrZhinxminBit = 28, 113 Feature_HasStdExtCBit = 2, 114 Feature_HasStdExtZbaBit = 13, 115 Feature_HasStdExtZbbBit = 14, 116 Feature_HasStdExtZbcBit = 16, 117 Feature_HasStdExtZbsBit = 21, 118 Feature_HasStdExtZbkbBit = 18, 119 Feature_HasStdExtZbkxBit = 20, 120 Feature_HasStdExtZbbOrZbkbBit = 15, 121 Feature_HasStdExtZbkcBit = 19, 122 Feature_HasStdExtZbcOrZbkcBit = 17, 123 Feature_HasStdExtZkndBit = 35, 124 Feature_HasStdExtZkneBit = 37, 125 Feature_HasStdExtZkndOrZkneBit = 36, 126 Feature_HasStdExtZknhBit = 38, 127 Feature_HasStdExtZksedBit = 40, 128 Feature_HasStdExtZkshBit = 41, 129 Feature_HasStdExtZkrBit = 39, 130 Feature_HasStdExtCOrZcaBit = 3, 131 Feature_HasStdExtCOrZcdBit = 4, 132 Feature_HasStdExtCOrZcfBit = 5, 133 Feature_HasRVCHintsBit = 0, 134 Feature_HasVInstructionsBit = 43, 135 Feature_HasVInstructionsI64Bit = 45, 136 Feature_HasVInstructionsAnyFBit = 44, 137 Feature_HasStdExtZicbomBit = 30, 138 Feature_HasStdExtZicbozBit = 32, 139 Feature_HasStdExtZicbopBit = 31, 140 Feature_HasStdExtSvinvalBit = 11, 141 Feature_HasStdExtZtsoBit = 42, 142 Feature_HasStdExtZawrsBit = 12, 143 Feature_HasVendorXVentanaCondOpsBit = 47, 144 Feature_HasVendorXTHeadVdotBit = 46, 145 Feature_IsRV64Bit = 50, 146 Feature_IsRV32Bit = 48, 147 Feature_IsRV32EBit = 49, 148}; 149 150static unsigned MatchRegisterName(StringRef Name) { 151 switch (Name.size()) { 152 default: break; 153 case 2: // 66 strings to match. 154 switch (Name[0]) { 155 default: break; 156 case 'f': // 30 strings to match. 157 switch (Name[1]) { 158 default: break; 159 case '0': // 3 strings to match. 160 return 72; // "f0" 161 case '1': // 3 strings to match. 162 return 73; // "f1" 163 case '2': // 3 strings to match. 164 return 74; // "f2" 165 case '3': // 3 strings to match. 166 return 75; // "f3" 167 case '4': // 3 strings to match. 168 return 76; // "f4" 169 case '5': // 3 strings to match. 170 return 77; // "f5" 171 case '6': // 3 strings to match. 172 return 78; // "f6" 173 case '7': // 3 strings to match. 174 return 79; // "f7" 175 case '8': // 3 strings to match. 176 return 80; // "f8" 177 case '9': // 3 strings to match. 178 return 81; // "f9" 179 } 180 break; 181 case 'v': // 21 strings to match. 182 switch (Name[1]) { 183 default: break; 184 case '0': // 4 strings to match. 185 return 8; // "v0" 186 case '1': // 1 string to match. 187 return 9; // "v1" 188 case '2': // 2 strings to match. 189 return 10; // "v2" 190 case '3': // 1 string to match. 191 return 11; // "v3" 192 case '4': // 3 strings to match. 193 return 12; // "v4" 194 case '5': // 1 string to match. 195 return 13; // "v5" 196 case '6': // 2 strings to match. 197 return 14; // "v6" 198 case '7': // 1 string to match. 199 return 15; // "v7" 200 case '8': // 4 strings to match. 201 return 16; // "v8" 202 case '9': // 1 string to match. 203 return 17; // "v9" 204 case 'l': // 1 string to match. 205 return 3; // "vl" 206 } 207 break; 208 case 'x': // 15 strings to match. 209 switch (Name[1]) { 210 default: break; 211 case '0': // 2 strings to match. 212 return 40; // "x0" 213 case '1': // 1 string to match. 214 return 41; // "x1" 215 case '2': // 2 strings to match. 216 return 42; // "x2" 217 case '3': // 1 string to match. 218 return 43; // "x3" 219 case '4': // 2 strings to match. 220 return 44; // "x4" 221 case '5': // 1 string to match. 222 return 45; // "x5" 223 case '6': // 2 strings to match. 224 return 46; // "x6" 225 case '7': // 1 string to match. 226 return 47; // "x7" 227 case '8': // 2 strings to match. 228 return 48; // "x8" 229 case '9': // 1 string to match. 230 return 49; // "x9" 231 } 232 break; 233 } 234 break; 235 case 3: // 140 strings to match. 236 switch (Name[0]) { 237 default: break; 238 case 'f': // 67 strings to match. 239 switch (Name[1]) { 240 default: break; 241 case '1': // 30 strings to match. 242 switch (Name[2]) { 243 default: break; 244 case '0': // 3 strings to match. 245 return 82; // "f10" 246 case '1': // 3 strings to match. 247 return 83; // "f11" 248 case '2': // 3 strings to match. 249 return 84; // "f12" 250 case '3': // 3 strings to match. 251 return 85; // "f13" 252 case '4': // 3 strings to match. 253 return 86; // "f14" 254 case '5': // 3 strings to match. 255 return 87; // "f15" 256 case '6': // 3 strings to match. 257 return 88; // "f16" 258 case '7': // 3 strings to match. 259 return 89; // "f17" 260 case '8': // 3 strings to match. 261 return 90; // "f18" 262 case '9': // 3 strings to match. 263 return 91; // "f19" 264 } 265 break; 266 case '2': // 30 strings to match. 267 switch (Name[2]) { 268 default: break; 269 case '0': // 3 strings to match. 270 return 92; // "f20" 271 case '1': // 3 strings to match. 272 return 93; // "f21" 273 case '2': // 3 strings to match. 274 return 94; // "f22" 275 case '3': // 3 strings to match. 276 return 95; // "f23" 277 case '4': // 3 strings to match. 278 return 96; // "f24" 279 case '5': // 3 strings to match. 280 return 97; // "f25" 281 case '6': // 3 strings to match. 282 return 98; // "f26" 283 case '7': // 3 strings to match. 284 return 99; // "f27" 285 case '8': // 3 strings to match. 286 return 100; // "f28" 287 case '9': // 3 strings to match. 288 return 101; // "f29" 289 } 290 break; 291 case '3': // 6 strings to match. 292 switch (Name[2]) { 293 default: break; 294 case '0': // 3 strings to match. 295 return 102; // "f30" 296 case '1': // 3 strings to match. 297 return 103; // "f31" 298 } 299 break; 300 case 'r': // 1 string to match. 301 if (Name[2] != 'm') 302 break; 303 return 2; // "frm" 304 } 305 break; 306 case 'v': // 40 strings to match. 307 switch (Name[1]) { 308 default: break; 309 case '1': // 18 strings to match. 310 switch (Name[2]) { 311 default: break; 312 case '0': // 2 strings to match. 313 return 18; // "v10" 314 case '1': // 1 string to match. 315 return 19; // "v11" 316 case '2': // 3 strings to match. 317 return 20; // "v12" 318 case '3': // 1 string to match. 319 return 21; // "v13" 320 case '4': // 2 strings to match. 321 return 22; // "v14" 322 case '5': // 1 string to match. 323 return 23; // "v15" 324 case '6': // 4 strings to match. 325 return 24; // "v16" 326 case '7': // 1 string to match. 327 return 25; // "v17" 328 case '8': // 2 strings to match. 329 return 26; // "v18" 330 case '9': // 1 string to match. 331 return 27; // "v19" 332 } 333 break; 334 case '2': // 19 strings to match. 335 switch (Name[2]) { 336 default: break; 337 case '0': // 3 strings to match. 338 return 28; // "v20" 339 case '1': // 1 string to match. 340 return 29; // "v21" 341 case '2': // 2 strings to match. 342 return 30; // "v22" 343 case '3': // 1 string to match. 344 return 31; // "v23" 345 case '4': // 4 strings to match. 346 return 32; // "v24" 347 case '5': // 1 string to match. 348 return 33; // "v25" 349 case '6': // 2 strings to match. 350 return 34; // "v26" 351 case '7': // 1 string to match. 352 return 35; // "v27" 353 case '8': // 3 strings to match. 354 return 36; // "v28" 355 case '9': // 1 string to match. 356 return 37; // "v29" 357 } 358 break; 359 case '3': // 3 strings to match. 360 switch (Name[2]) { 361 default: break; 362 case '0': // 2 strings to match. 363 return 38; // "v30" 364 case '1': // 1 string to match. 365 return 39; // "v31" 366 } 367 break; 368 } 369 break; 370 case 'x': // 33 strings to match. 371 switch (Name[1]) { 372 default: break; 373 case '1': // 15 strings to match. 374 switch (Name[2]) { 375 default: break; 376 case '0': // 2 strings to match. 377 return 50; // "x10" 378 case '1': // 1 string to match. 379 return 51; // "x11" 380 case '2': // 2 strings to match. 381 return 52; // "x12" 382 case '3': // 1 string to match. 383 return 53; // "x13" 384 case '4': // 2 strings to match. 385 return 54; // "x14" 386 case '5': // 1 string to match. 387 return 55; // "x15" 388 case '6': // 2 strings to match. 389 return 56; // "x16" 390 case '7': // 1 string to match. 391 return 57; // "x17" 392 case '8': // 2 strings to match. 393 return 58; // "x18" 394 case '9': // 1 string to match. 395 return 59; // "x19" 396 } 397 break; 398 case '2': // 15 strings to match. 399 switch (Name[2]) { 400 default: break; 401 case '0': // 2 strings to match. 402 return 60; // "x20" 403 case '1': // 1 string to match. 404 return 61; // "x21" 405 case '2': // 2 strings to match. 406 return 62; // "x22" 407 case '3': // 1 string to match. 408 return 63; // "x23" 409 case '4': // 2 strings to match. 410 return 64; // "x24" 411 case '5': // 1 string to match. 412 return 65; // "x25" 413 case '6': // 2 strings to match. 414 return 66; // "x26" 415 case '7': // 1 string to match. 416 return 67; // "x27" 417 case '8': // 2 strings to match. 418 return 68; // "x28" 419 case '9': // 1 string to match. 420 return 69; // "x29" 421 } 422 break; 423 case '3': // 3 strings to match. 424 switch (Name[2]) { 425 default: break; 426 case '0': // 2 strings to match. 427 return 70; // "x30" 428 case '1': // 1 string to match. 429 return 71; // "x31" 430 } 431 break; 432 } 433 break; 434 } 435 break; 436 case 4: // 1 string to match. 437 if (memcmp(Name.data()+0, "vxrm", 4) != 0) 438 break; 439 return 6; // "vxrm" 440 case 5: // 3 strings to match. 441 if (Name[0] != 'v') 442 break; 443 switch (Name[1]) { 444 default: break; 445 case 'l': // 1 string to match. 446 if (memcmp(Name.data()+2, "enb", 3) != 0) 447 break; 448 return 4; // "vlenb" 449 case 't': // 1 string to match. 450 if (memcmp(Name.data()+2, "ype", 3) != 0) 451 break; 452 return 5; // "vtype" 453 case 'x': // 1 string to match. 454 if (memcmp(Name.data()+2, "sat", 3) != 0) 455 break; 456 return 7; // "vxsat" 457 } 458 break; 459 case 6: // 1 string to match. 460 if (memcmp(Name.data()+0, "fflags", 6) != 0) 461 break; 462 return 1; // "fflags" 463 } 464 return 0; 465} 466 467static unsigned MatchRegisterAltName(StringRef Name) { 468 switch (Name.size()) { 469 default: break; 470 case 2: // 154 strings to match. 471 switch (Name[0]) { 472 default: break; 473 case 'a': // 12 strings to match. 474 switch (Name[1]) { 475 default: break; 476 case '0': // 2 strings to match. 477 return 50; // "a0" 478 case '1': // 1 string to match. 479 return 51; // "a1" 480 case '2': // 2 strings to match. 481 return 52; // "a2" 482 case '3': // 1 string to match. 483 return 53; // "a3" 484 case '4': // 2 strings to match. 485 return 54; // "a4" 486 case '5': // 1 string to match. 487 return 55; // "a5" 488 case '6': // 2 strings to match. 489 return 56; // "a6" 490 case '7': // 1 string to match. 491 return 57; // "a7" 492 } 493 break; 494 case 'f': // 2 strings to match. 495 if (Name[1] != 'p') 496 break; 497 return 48; // "fp" 498 case 'g': // 1 string to match. 499 if (Name[1] != 'p') 500 break; 501 return 43; // "gp" 502 case 'r': // 1 string to match. 503 if (Name[1] != 'a') 504 break; 505 return 41; // "ra" 506 case 's': // 17 strings to match. 507 switch (Name[1]) { 508 default: break; 509 case '0': // 2 strings to match. 510 return 48; // "s0" 511 case '1': // 1 string to match. 512 return 49; // "s1" 513 case '2': // 2 strings to match. 514 return 58; // "s2" 515 case '3': // 1 string to match. 516 return 59; // "s3" 517 case '4': // 2 strings to match. 518 return 60; // "s4" 519 case '5': // 1 string to match. 520 return 61; // "s5" 521 case '6': // 2 strings to match. 522 return 62; // "s6" 523 case '7': // 1 string to match. 524 return 63; // "s7" 525 case '8': // 2 strings to match. 526 return 64; // "s8" 527 case '9': // 1 string to match. 528 return 65; // "s9" 529 case 'p': // 2 strings to match. 530 return 42; // "sp" 531 } 532 break; 533 case 't': // 12 strings to match. 534 switch (Name[1]) { 535 default: break; 536 case '0': // 1 string to match. 537 return 45; // "t0" 538 case '1': // 2 strings to match. 539 return 46; // "t1" 540 case '2': // 1 string to match. 541 return 47; // "t2" 542 case '3': // 2 strings to match. 543 return 68; // "t3" 544 case '4': // 1 string to match. 545 return 69; // "t4" 546 case '5': // 2 strings to match. 547 return 70; // "t5" 548 case '6': // 1 string to match. 549 return 71; // "t6" 550 case 'p': // 2 strings to match. 551 return 44; // "tp" 552 } 553 break; 554 case 'v': // 109 strings to match. 555 switch (Name[1]) { 556 default: break; 557 case '0': // 15 strings to match. 558 return 8; // "v0" 559 case '1': // 8 strings to match. 560 return 9; // "v1" 561 case '2': // 12 strings to match. 562 return 10; // "v2" 563 case '3': // 8 strings to match. 564 return 11; // "v3" 565 case '4': // 14 strings to match. 566 return 12; // "v4" 567 case '5': // 8 strings to match. 568 return 13; // "v5" 569 case '6': // 12 strings to match. 570 return 14; // "v6" 571 case '7': // 8 strings to match. 572 return 15; // "v7" 573 case '8': // 15 strings to match. 574 return 16; // "v8" 575 case '9': // 8 strings to match. 576 return 17; // "v9" 577 case 'l': // 1 string to match. 578 return 3; // "vl" 579 } 580 break; 581 } 582 break; 583 case 3: // 284 strings to match. 584 switch (Name[0]) { 585 default: break; 586 case 'f': // 84 strings to match. 587 switch (Name[1]) { 588 default: break; 589 case 'a': // 24 strings to match. 590 switch (Name[2]) { 591 default: break; 592 case '0': // 3 strings to match. 593 return 82; // "fa0" 594 case '1': // 3 strings to match. 595 return 83; // "fa1" 596 case '2': // 3 strings to match. 597 return 84; // "fa2" 598 case '3': // 3 strings to match. 599 return 85; // "fa3" 600 case '4': // 3 strings to match. 601 return 86; // "fa4" 602 case '5': // 3 strings to match. 603 return 87; // "fa5" 604 case '6': // 3 strings to match. 605 return 88; // "fa6" 606 case '7': // 3 strings to match. 607 return 89; // "fa7" 608 } 609 break; 610 case 's': // 30 strings to match. 611 switch (Name[2]) { 612 default: break; 613 case '0': // 3 strings to match. 614 return 80; // "fs0" 615 case '1': // 3 strings to match. 616 return 81; // "fs1" 617 case '2': // 3 strings to match. 618 return 90; // "fs2" 619 case '3': // 3 strings to match. 620 return 91; // "fs3" 621 case '4': // 3 strings to match. 622 return 92; // "fs4" 623 case '5': // 3 strings to match. 624 return 93; // "fs5" 625 case '6': // 3 strings to match. 626 return 94; // "fs6" 627 case '7': // 3 strings to match. 628 return 95; // "fs7" 629 case '8': // 3 strings to match. 630 return 96; // "fs8" 631 case '9': // 3 strings to match. 632 return 97; // "fs9" 633 } 634 break; 635 case 't': // 30 strings to match. 636 switch (Name[2]) { 637 default: break; 638 case '0': // 3 strings to match. 639 return 72; // "ft0" 640 case '1': // 3 strings to match. 641 return 73; // "ft1" 642 case '2': // 3 strings to match. 643 return 74; // "ft2" 644 case '3': // 3 strings to match. 645 return 75; // "ft3" 646 case '4': // 3 strings to match. 647 return 76; // "ft4" 648 case '5': // 3 strings to match. 649 return 77; // "ft5" 650 case '6': // 3 strings to match. 651 return 78; // "ft6" 652 case '7': // 3 strings to match. 653 return 79; // "ft7" 654 case '8': // 3 strings to match. 655 return 100; // "ft8" 656 case '9': // 3 strings to match. 657 return 101; // "ft9" 658 } 659 break; 660 } 661 break; 662 case 's': // 3 strings to match. 663 if (Name[1] != '1') 664 break; 665 switch (Name[2]) { 666 default: break; 667 case '0': // 2 strings to match. 668 return 66; // "s10" 669 case '1': // 1 string to match. 670 return 67; // "s11" 671 } 672 break; 673 case 'v': // 197 strings to match. 674 switch (Name[1]) { 675 default: break; 676 case '1': // 105 strings to match. 677 switch (Name[2]) { 678 default: break; 679 case '0': // 12 strings to match. 680 return 18; // "v10" 681 case '1': // 8 strings to match. 682 return 19; // "v11" 683 case '2': // 14 strings to match. 684 return 20; // "v12" 685 case '3': // 8 strings to match. 686 return 21; // "v13" 687 case '4': // 12 strings to match. 688 return 22; // "v14" 689 case '5': // 8 strings to match. 690 return 23; // "v15" 691 case '6': // 15 strings to match. 692 return 24; // "v16" 693 case '7': // 8 strings to match. 694 return 25; // "v17" 695 case '8': // 12 strings to match. 696 return 26; // "v18" 697 case '9': // 8 strings to match. 698 return 27; // "v19" 699 } 700 break; 701 case '2': // 88 strings to match. 702 switch (Name[2]) { 703 default: break; 704 case '0': // 14 strings to match. 705 return 28; // "v20" 706 case '1': // 8 strings to match. 707 return 29; // "v21" 708 case '2': // 12 strings to match. 709 return 30; // "v22" 710 case '3': // 8 strings to match. 711 return 31; // "v23" 712 case '4': // 15 strings to match. 713 return 32; // "v24" 714 case '5': // 7 strings to match. 715 return 33; // "v25" 716 case '6': // 9 strings to match. 717 return 34; // "v26" 718 case '7': // 5 strings to match. 719 return 35; // "v27" 720 case '8': // 7 strings to match. 721 return 36; // "v28" 722 case '9': // 3 strings to match. 723 return 37; // "v29" 724 } 725 break; 726 case '3': // 4 strings to match. 727 switch (Name[2]) { 728 default: break; 729 case '0': // 3 strings to match. 730 return 38; // "v30" 731 case '1': // 1 string to match. 732 return 39; // "v31" 733 } 734 break; 735 } 736 break; 737 } 738 break; 739 case 4: // 15 strings to match. 740 switch (Name[0]) { 741 default: break; 742 case 'f': // 12 strings to match. 743 switch (Name[1]) { 744 default: break; 745 case 's': // 6 strings to match. 746 if (Name[2] != '1') 747 break; 748 switch (Name[3]) { 749 default: break; 750 case '0': // 3 strings to match. 751 return 98; // "fs10" 752 case '1': // 3 strings to match. 753 return 99; // "fs11" 754 } 755 break; 756 case 't': // 6 strings to match. 757 if (Name[2] != '1') 758 break; 759 switch (Name[3]) { 760 default: break; 761 case '0': // 3 strings to match. 762 return 102; // "ft10" 763 case '1': // 3 strings to match. 764 return 103; // "ft11" 765 } 766 break; 767 } 768 break; 769 case 'v': // 1 string to match. 770 if (memcmp(Name.data()+1, "xrm", 3) != 0) 771 break; 772 return 6; // "vxrm" 773 case 'z': // 2 strings to match. 774 if (memcmp(Name.data()+1, "ero", 3) != 0) 775 break; 776 return 40; // "zero" 777 } 778 break; 779 case 5: // 3 strings to match. 780 if (Name[0] != 'v') 781 break; 782 switch (Name[1]) { 783 default: break; 784 case 'l': // 1 string to match. 785 if (memcmp(Name.data()+2, "enb", 3) != 0) 786 break; 787 return 4; // "vlenb" 788 case 't': // 1 string to match. 789 if (memcmp(Name.data()+2, "ype", 3) != 0) 790 break; 791 return 5; // "vtype" 792 case 'x': // 1 string to match. 793 if (memcmp(Name.data()+2, "sat", 3) != 0) 794 break; 795 return 7; // "vxsat" 796 } 797 break; 798 } 799 return 0; 800} 801 802#endif // GET_REGISTER_MATCHER 803 804 805#ifdef GET_SUBTARGET_FEATURE_NAME 806#undef GET_SUBTARGET_FEATURE_NAME 807 808// User-level names for subtarget features that participate in 809// instruction matching. 810static const char *getSubtargetFeatureName(uint64_t Val) { 811 switch(Val) { 812 case Feature_HasStdExtMBit: return "'M' (Integer Multiplication and Division)"; 813 case Feature_HasStdExtMOrZmmulBit: return "'M' (Integer Multiplication and Division) or 'Zmmul' (Integer Multiplication)"; 814 case Feature_HasStdExtABit: return "'A' (Atomic Instructions)"; 815 case Feature_HasStdExtFBit: return "'F' (Single-Precision Floating-Point)"; 816 case Feature_HasStdExtDBit: return "'D' (Double-Precision Floating-Point)"; 817 case Feature_HasStdExtHBit: return "'H' (Hypervisor)"; 818 case Feature_HasStdExtZihintpauseBit: return "'Zihintpause' (Pause Hint)"; 819 case Feature_HasStdExtZihintntlBit: return "'Zihintntl' (Non-Temporal Locality Hints)"; 820 case Feature_HasStdExtZfhminBit: return "'Zfhmin' (Half-Precision Floating-Point Minimal)"; 821 case Feature_HasStdExtZfhBit: return "'Zfh' (Half-Precision Floating-Point)"; 822 case Feature_HasStdExtZfhOrZfhminBit: return "'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal)"; 823 case Feature_HasStdExtZfinxBit: return "'Zfinx' (Float in Integer)"; 824 case Feature_HasStdExtZdinxBit: return "'Zdinx' (Double in Integer)"; 825 case Feature_HasStdExtZhinxminBit: return "'Zhinxmin' (Half Float in Integer Minimal)"; 826 case Feature_HasStdExtZhinxBit: return "'Zhinx' (Half Float in Integer)"; 827 case Feature_HasStdExtZhinxOrZhinxminBit: return "'Zhinx' (Half Float in Integer) or 'Zhinxmin' (Half Float in Integer Minimal)"; 828 case Feature_HasStdExtCBit: return "'C' (Compressed Instructions)"; 829 case Feature_HasStdExtZbaBit: return "'Zba' (Address Generation Instructions)"; 830 case Feature_HasStdExtZbbBit: return "'Zbb' (Basic Bit-Manipulation)"; 831 case Feature_HasStdExtZbcBit: return "'Zbc' (Carry-Less Multiplication)"; 832 case Feature_HasStdExtZbsBit: return "'Zbs' (Single-Bit Instructions)"; 833 case Feature_HasStdExtZbkbBit: return "'Zbkb' (Bitmanip instructions for Cryptography)"; 834 case Feature_HasStdExtZbkxBit: return "'Zbkx' (Crossbar permutation instructions)"; 835 case Feature_HasStdExtZbbOrZbkbBit: return "'Zbb' (Basic Bit-Manipulation) or 'Zbkb' (Bitmanip instructions for Cryptography)"; 836 case Feature_HasStdExtZbkcBit: return "'Zbkc' (Carry-less multiply instructions for Cryptography)"; 837 case Feature_HasStdExtZbcOrZbkcBit: return "'Zbc' (Carry-Less Multiplication) or 'Zbkc' (Carry-less multiply instructions for Cryptography)"; 838 case Feature_HasStdExtZkndBit: return "'Zknd' (NIST Suite: AES Decryption)"; 839 case Feature_HasStdExtZkneBit: return "'Zkne' (NIST Suite: AES Encryption)"; 840 case Feature_HasStdExtZkndOrZkneBit: return "'Zknd' (NIST Suite: AES Decryption) or 'Zkne' (NIST Suite: AES Encryption)"; 841 case Feature_HasStdExtZknhBit: return "'Zknh' (NIST Suite: Hash Function Instructions)"; 842 case Feature_HasStdExtZksedBit: return "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)"; 843 case Feature_HasStdExtZkshBit: return "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)"; 844 case Feature_HasStdExtZkrBit: return "'Zkr' (Entropy Source Extension)"; 845 case Feature_HasStdExtCOrZcaBit: return "'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores)"; 846 case Feature_HasStdExtCOrZcdBit: return "'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions)"; 847 case Feature_HasStdExtCOrZcfBit: return "'C' (Compressed Instructions) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions)"; 848 case Feature_HasRVCHintsBit: return "RVC Hint Instructions"; 849 case Feature_HasVInstructionsBit: return "'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)"; 850 case Feature_HasVInstructionsI64Bit: return "'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors)"; 851 case Feature_HasVInstructionsAnyFBit: return "'V' (Vector Extension for Application Processors), 'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors)"; 852 case Feature_HasStdExtZicbomBit: return "'Zicbom' (Cache-Block Management Instructions)"; 853 case Feature_HasStdExtZicbozBit: return "'Zicboz' (Cache-Block Zero Instructions)"; 854 case Feature_HasStdExtZicbopBit: return "'Zicbop' (Cache-Block Prefetch Instructions)"; 855 case Feature_HasStdExtSvinvalBit: return "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)"; 856 case Feature_HasStdExtZtsoBit: return "'Ztso' (Memory Model - Total Store Order)"; 857 case Feature_HasStdExtZawrsBit: return "'Zawrs' (Wait on Reservation Set)"; 858 case Feature_HasVendorXVentanaCondOpsBit: return "'XVentanaCondOps' (Ventana Conditional Ops)"; 859 case Feature_HasVendorXTHeadVdotBit: return "'xtheadvdot' (T-Head Vector Extensions for Dot)"; 860 case Feature_IsRV64Bit: return "RV64I Base Instruction Set"; 861 case Feature_IsRV32Bit: return "RV32I Base Instruction Set"; 862 case Feature_IsRV32EBit: return ""; 863 default: return "(unknown)"; 864 } 865} 866 867#endif // GET_SUBTARGET_FEATURE_NAME 868 869 870#ifdef GET_MATCHER_IMPLEMENTATION 871#undef GET_MATCHER_IMPLEMENTATION 872 873static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) { 874 switch (VariantID) { 875 case 0: 876 switch (Mnemonic.size()) { 877 default: break; 878 case 4: // 1 string to match. 879 if (memcmp(Mnemonic.data()+0, "move", 4) != 0) 880 break; 881 Mnemonic = "mv"; // "move" 882 return; 883 case 5: // 1 string to match. 884 if (memcmp(Mnemonic.data()+0, "scall", 5) != 0) 885 break; 886 Mnemonic = "ecall"; // "scall" 887 return; 888 case 6: // 1 string to match. 889 if (memcmp(Mnemonic.data()+0, "sbreak", 6) != 0) 890 break; 891 Mnemonic = "ebreak"; // "sbreak" 892 return; 893 case 7: // 2 strings to match. 894 if (memcmp(Mnemonic.data()+0, "fmv.", 4) != 0) 895 break; 896 switch (Mnemonic[4]) { 897 default: break; 898 case 's': // 1 string to match. 899 if (memcmp(Mnemonic.data()+5, ".x", 2) != 0) 900 break; 901 if (Features.test(Feature_HasStdExtFBit)) // "fmv.s.x" 902 Mnemonic = "fmv.w.x"; 903 return; 904 case 'x': // 1 string to match. 905 if (memcmp(Mnemonic.data()+5, ".s", 2) != 0) 906 break; 907 if (Features.test(Feature_HasStdExtFBit)) // "fmv.x.s" 908 Mnemonic = "fmv.x.w"; 909 return; 910 } 911 break; 912 } 913 break; 914 } 915 switch (Mnemonic.size()) { 916 default: break; 917 case 4: // 1 string to match. 918 if (memcmp(Mnemonic.data()+0, "move", 4) != 0) 919 break; 920 Mnemonic = "mv"; // "move" 921 return; 922 case 5: // 1 string to match. 923 if (memcmp(Mnemonic.data()+0, "scall", 5) != 0) 924 break; 925 Mnemonic = "ecall"; // "scall" 926 return; 927 case 6: // 1 string to match. 928 if (memcmp(Mnemonic.data()+0, "sbreak", 6) != 0) 929 break; 930 Mnemonic = "ebreak"; // "sbreak" 931 return; 932 case 7: // 2 strings to match. 933 if (memcmp(Mnemonic.data()+0, "fmv.", 4) != 0) 934 break; 935 switch (Mnemonic[4]) { 936 default: break; 937 case 's': // 1 string to match. 938 if (memcmp(Mnemonic.data()+5, ".x", 2) != 0) 939 break; 940 if (Features.test(Feature_HasStdExtFBit)) // "fmv.s.x" 941 Mnemonic = "fmv.w.x"; 942 return; 943 case 'x': // 1 string to match. 944 if (memcmp(Mnemonic.data()+5, ".s", 2) != 0) 945 break; 946 if (Features.test(Feature_HasStdExtFBit)) // "fmv.x.s" 947 Mnemonic = "fmv.x.w"; 948 return; 949 } 950 break; 951 } 952} 953 954enum { 955 Tie0_1_1, 956}; 957 958static const uint8_t TiedAsmOperandTable[][3] = { 959 /* Tie0_1_1 */ { 0, 1, 1 }, 960}; 961 962namespace { 963enum OperatorConversionKind { 964 CVT_Done, 965 CVT_Reg, 966 CVT_Tied, 967 CVT_95_addImmOperands, 968 CVT_95_Reg, 969 CVT_95_addRegOperands, 970 CVT_regX0, 971 CVT_imm_95_0, 972 CVT_regX5, 973 CVT_regX2, 974 CVT_regX3, 975 CVT_regX4, 976 CVT_95_addCSRSystemRegisterOperands, 977 CVT_imm_95_7, 978 CVT_95_addFRMArgOperands, 979 CVT_imm_95_15, 980 CVT_95_addFenceArgOperands, 981 CVT_imm_95_3, 982 CVT_imm_95_1, 983 CVT_imm_95_2, 984 CVT_regX1, 985 CVT_imm_95__MINUS_1, 986 CVT_imm_95_3072, 987 CVT_imm_95_3200, 988 CVT_imm_95_3074, 989 CVT_imm_95_3202, 990 CVT_imm_95_3073, 991 CVT_imm_95_3201, 992 CVT_95_addRegOperands_95_defaultMaskRegOp, 993 CVT_reg0, 994 CVT_95_addVTypeIOperands, 995 CVT_imm_95_255, 996 CVT_NUM_CONVERTERS 997}; 998 999enum InstructionConversionKind { 1000 Convert__InsnDirectiveOpcode1_0__UImm31_1__Reg1_2__Reg1_3__SImm13Lsb01_4, 1001 Convert__Reg1_2__InsnDirectiveOpcode1_0__UImm31_1__Reg1_3__SImm121_4, 1002 Convert__Reg1_2__InsnDirectiveOpcode1_0__UImm31_1__Reg1_5__SImm121_3, 1003 Convert__Reg1_1__InsnDirectiveOpcode1_0__SImm21Lsb0JAL1_2, 1004 Convert__Reg1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm71_2__Reg1_4__Reg1_5, 1005 Convert__Reg1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__Reg1_4__Reg1_5__Reg1_6, 1006 Convert__InsnDirectiveOpcode1_0__UImm31_1__Reg1_2__Reg1_5__SImm121_3, 1007 Convert__Reg1_1__InsnDirectiveOpcode1_0__UImm20LUI1_2, 1008 Convert__Reg1_0__Reg1_1__Reg1_2, 1009 Convert__Reg1_0__Reg1_1__SImm121_2, 1010 Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3, 1011 Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, 1012 Convert__Reg1_0__Reg1_1, 1013 Convert__Reg1_0__Reg1_1__RnumArg1_2, 1014 Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, 1015 Convert__Reg1_0__UImm20AUIPC1_1, 1016 Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, 1017 Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, 1018 Convert__Reg1_0__regX0__SImm13Lsb01_1, 1019 Convert__Reg1_1__Reg1_0__SImm13Lsb01_2, 1020 Convert__regX0__Reg1_0__SImm13Lsb01_1, 1021 Convert__Reg1_0__Tie0_1_1__Reg1_1, 1022 Convert__Reg1_0__Tie0_1_1__ImmZero1_1, 1023 Convert__Reg1_0__Tie0_1_1__SImm6NonZero1_1, 1024 Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1, 1025 Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2, 1026 Convert__Reg1_0__Tie0_1_1__SImm61_1, 1027 Convert__Reg1_0__SImm9Lsb01_1, 1028 Convert_NoOperands, 1029 Convert__Reg1_0__Reg1_2__imm_95_0, 1030 Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, 1031 Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, 1032 Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, 1033 Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, 1034 Convert__SImm12Lsb01_0, 1035 Convert__Reg1_0, 1036 Convert__Reg1_0__SImm61_1, 1037 Convert__Reg1_0__CLUIImm1_1, 1038 Convert__SImm6NonZero1_0, 1039 Convert__regX0__Tie0_1_1__regX5, 1040 Convert__regX0__Tie0_1_1__regX2, 1041 Convert__regX0__Tie0_1_1__regX3, 1042 Convert__regX0__Tie0_1_1__regX4, 1043 Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, 1044 Convert__Reg1_0__Tie0_1_1, 1045 Convert__CallSymbol1_0, 1046 Convert__Reg1_0__CallSymbol1_1, 1047 Convert__ZeroOffsetMemOpOperand1_0, 1048 Convert__regX0__CSRSystemRegister1_0__Reg1_1, 1049 Convert__regX0__CSRSystemRegister1_0__UImm51_1, 1050 Convert__Reg1_0__CSRSystemRegister1_1__regX0, 1051 Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, 1052 Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, 1053 Convert__imm_95_0__imm_95_0, 1054 Convert__Reg1_0__Reg1_1__Reg1_1, 1055 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1, 1056 Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_1, 1057 Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_1, 1058 Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, 1059 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__imm_95_7, 1060 Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__imm_95_7, 1061 Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, 1062 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, 1063 Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__FRMArg1_3, 1064 Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__imm_95_7, 1065 Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__FRMArg1_3, 1066 Convert__Reg1_0__GPRF64AsFPR1_1, 1067 Convert__Reg1_0__GPRPF64AsFPR1_1, 1068 Convert__Reg1_0__GPRAsFPR1_1, 1069 Convert__GPRF64AsFPR1_0__GPRAsFPR1_1, 1070 Convert__Reg1_0__Reg1_1__imm_95_7, 1071 Convert__GPRF64AsFPR1_0__Reg1_1__imm_95_7, 1072 Convert__Reg1_0__Reg1_1__FRMArg1_2, 1073 Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2, 1074 Convert__GPRPF64AsFPR1_0__GPRAsFPR1_1, 1075 Convert__GPRF64AsFPR1_0__Reg1_1, 1076 Convert__GPRPF64AsFPR1_0__Reg1_1, 1077 Convert__GPRAsFPR1_0__GPRF64AsFPR1_1__imm_95_7, 1078 Convert__GPRAsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2, 1079 Convert__GPRAsFPR1_0__Reg1_1__imm_95_7, 1080 Convert__GPRAsFPR1_0__Reg1_1__FRMArg1_2, 1081 Convert__GPRAsFPR1_0__GPRAsFPR1_1__imm_95_7, 1082 Convert__GPRAsFPR1_0__GPRAsFPR1_1__FRMArg1_2, 1083 Convert__Reg1_0__GPRF64AsFPR1_1__imm_95_7, 1084 Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, 1085 Convert__Reg1_0__GPRAsFPR1_1__imm_95_7, 1086 Convert__Reg1_0__GPRAsFPR1_1__FRMArg1_2, 1087 Convert__GPRAsFPR1_0__GPRPF64AsFPR1_1__imm_95_7, 1088 Convert__GPRAsFPR1_0__GPRPF64AsFPR1_1__FRMArg1_2, 1089 Convert__GPRAsFPR1_0__GPRAsFPR1_1, 1090 Convert__Reg1_0__GPRPF64AsFPR1_1__imm_95_7, 1091 Convert__Reg1_0__GPRPF64AsFPR1_1__FRMArg1_2, 1092 Convert__imm_95_15__imm_95_15, 1093 Convert__FenceArg1_0__FenceArg1_1, 1094 Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, 1095 Convert__Reg1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2, 1096 Convert__Reg1_0__GPRAsFPR1_1__GPRAsFPR1_2, 1097 Convert__Reg1_0__Reg1_2__Reg1_1, 1098 Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1, 1099 Convert__Reg1_0__GPRPF64AsFPR1_2__GPRPF64AsFPR1_1, 1100 Convert__Reg1_0__GPRAsFPR1_2__GPRAsFPR1_1, 1101 Convert__Reg1_2__Reg1_0__BareSymbol1_1, 1102 Convert__Reg1_0__Reg1_3__SImm121_1, 1103 Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, 1104 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__imm_95_7, 1105 Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__GPRPF64AsFPR1_3__imm_95_7, 1106 Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, 1107 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, 1108 Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__GPRPF64AsFPR1_3__FRMArg1_4, 1109 Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__imm_95_7, 1110 Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__FRMArg1_4, 1111 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, 1112 Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2, 1113 Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2, 1114 Convert__Reg1_0__imm_95_3__regX0, 1115 Convert__Reg1_0__imm_95_1__regX0, 1116 Convert__Reg1_0__imm_95_2__regX0, 1117 Convert__regX0__imm_95_3__Reg1_0, 1118 Convert__Reg1_0__imm_95_3__Reg1_1, 1119 Convert__regX0__imm_95_1__Reg1_0, 1120 Convert__Reg1_0__imm_95_1__Reg1_1, 1121 Convert__regX0__imm_95_1__UImm51_0, 1122 Convert__Reg1_0__imm_95_1__UImm51_1, 1123 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__imm_95_7, 1124 Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__imm_95_7, 1125 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2, 1126 Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__FRMArg1_2, 1127 Convert__regX0__imm_95_2__Reg1_0, 1128 Convert__Reg1_0__imm_95_2__Reg1_1, 1129 Convert__regX0__imm_95_2__UImm51_0, 1130 Convert__Reg1_0__imm_95_2__UImm51_1, 1131 Convert__regX0__regX0, 1132 Convert__Reg1_0__regX0, 1133 Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, 1134 Convert__regX0__SImm21Lsb0JAL1_0, 1135 Convert__regX1__SImm21Lsb0JAL1_0, 1136 Convert__Reg1_0__SImm21Lsb0JAL1_1, 1137 Convert__regX1__Reg1_0__imm_95_0, 1138 Convert__Reg1_0__Reg1_1__imm_95_0, 1139 Convert__regX1__Reg1_0__SImm121_1, 1140 Convert__regX1__Reg1_2__SImm121_0, 1141 Convert__regX0__Reg1_0__imm_95_0, 1142 Convert__regX0__Reg1_0__SImm121_1, 1143 Convert__regX0__Reg1_2__SImm121_0, 1144 Convert__Reg1_1__PseudoJumpSymbol1_0, 1145 Convert__Reg1_0__BareSymbol1_1, 1146 Convert__Reg1_0__regX0__SImm121_1, 1147 Convert__Reg1_0__ImmXLenLI1_1, 1148 Convert__Reg1_0__UImm20LUI1_1, 1149 Convert__Reg1_0__regX0__Reg1_1, 1150 Convert__regX0__regX0__imm_95_0, 1151 Convert__Reg1_0__Reg1_1__imm_95__MINUS_1, 1152 Convert__regX0__regX0__regX5, 1153 Convert__regX0__regX0__regX2, 1154 Convert__regX0__regX0__regX3, 1155 Convert__regX0__regX0__regX4, 1156 Convert__imm_95_1__imm_95_0, 1157 Convert__Reg1_2__SImm12Lsb000001_0, 1158 Convert__Reg1_0__imm_95_3072__regX0, 1159 Convert__Reg1_0__imm_95_3200__regX0, 1160 Convert__Reg1_0__imm_95_3074__regX0, 1161 Convert__Reg1_0__imm_95_3202__regX0, 1162 Convert__Reg1_0__imm_95_3073__regX0, 1163 Convert__Reg1_0__imm_95_3201__regX0, 1164 Convert__regX0__regX1__imm_95_0, 1165 Convert__Reg1_0__Reg1_1__UImm51_2, 1166 Convert__Reg1_0__Reg1_1__imm_95_1, 1167 Convert__Reg1_0__Reg1_1__regX0, 1168 Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, 1169 Convert__Reg1_0__Reg1_1__SImm51_2__imm_95_0, 1170 Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, 1171 Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, 1172 Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, 1173 Convert__Reg1_0__Reg1_1__Reg1_1__reg0, 1174 Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2, 1175 Convert__Reg1_0__RVVMaskRegOpOperand1_1, 1176 Convert__Reg1_0__Reg1_2, 1177 Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, 1178 Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, 1179 Convert__Reg1_0__Reg1_1__SImm51_2, 1180 Convert__Reg1_0__Reg1_0__Reg1_0, 1181 Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, 1182 Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, 1183 Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, 1184 Convert__Reg1_0__SImm51_1, 1185 Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, 1186 Convert__Reg1_0__Reg1_1__regX0__reg0, 1187 Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, 1188 Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__reg0, 1189 Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__RVVMaskRegOpOperand1_2, 1190 Convert__Reg1_0__UImm51_1__VTypeI101_2, 1191 Convert__Reg1_0__Reg1_1__VTypeI111_2, 1192 Convert__Reg1_0__Reg1_1__imm_95_255, 1193 CVT_NUM_SIGNATURES 1194}; 1195 1196} // end anonymous namespace 1197 1198static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][15] = { 1199 // Convert__InsnDirectiveOpcode1_0__UImm31_1__Reg1_2__Reg1_3__SImm13Lsb01_4 1200 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done }, 1201 // Convert__Reg1_2__InsnDirectiveOpcode1_0__UImm31_1__Reg1_3__SImm121_4 1202 { CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done }, 1203 // Convert__Reg1_2__InsnDirectiveOpcode1_0__UImm31_1__Reg1_5__SImm121_3 1204 { CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 6, CVT_95_addImmOperands, 4, CVT_Done }, 1205 // Convert__Reg1_1__InsnDirectiveOpcode1_0__SImm21Lsb0JAL1_2 1206 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 3, CVT_Done }, 1207 // Convert__Reg1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm71_2__Reg1_4__Reg1_5 1208 { CVT_95_Reg, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Done }, 1209 // Convert__Reg1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__Reg1_4__Reg1_5__Reg1_6 1210 { CVT_95_Reg, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_Done }, 1211 // Convert__InsnDirectiveOpcode1_0__UImm31_1__Reg1_2__Reg1_5__SImm121_3 1212 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addImmOperands, 4, CVT_Done }, 1213 // Convert__Reg1_1__InsnDirectiveOpcode1_0__UImm20LUI1_2 1214 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 3, CVT_Done }, 1215 // Convert__Reg1_0__Reg1_1__Reg1_2 1216 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done }, 1217 // Convert__Reg1_0__Reg1_1__SImm121_2 1218 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done }, 1219 // Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3 1220 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done }, 1221 // Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3 1222 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done }, 1223 // Convert__Reg1_0__Reg1_1 1224 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done }, 1225 // Convert__Reg1_0__Reg1_1__RnumArg1_2 1226 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done }, 1227 // Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1 1228 { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_Reg, 2, CVT_Done }, 1229 // Convert__Reg1_0__UImm20AUIPC1_1 1230 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1231 // Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2 1232 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done }, 1233 // Convert__Reg1_0__Reg1_1__SImm13Lsb01_2 1234 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done }, 1235 // Convert__Reg1_0__regX0__SImm13Lsb01_1 1236 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_addImmOperands, 2, CVT_Done }, 1237 // Convert__Reg1_1__Reg1_0__SImm13Lsb01_2 1238 { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_Done }, 1239 // Convert__regX0__Reg1_0__SImm13Lsb01_1 1240 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1241 // Convert__Reg1_0__Tie0_1_1__Reg1_1 1242 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done }, 1243 // Convert__Reg1_0__Tie0_1_1__ImmZero1_1 1244 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done }, 1245 // Convert__Reg1_0__Tie0_1_1__SImm6NonZero1_1 1246 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done }, 1247 // Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1 1248 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done }, 1249 // Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2 1250 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done }, 1251 // Convert__Reg1_0__Tie0_1_1__SImm61_1 1252 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done }, 1253 // Convert__Reg1_0__SImm9Lsb01_1 1254 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1255 // Convert_NoOperands 1256 { CVT_Done }, 1257 // Convert__Reg1_0__Reg1_2__imm_95_0 1258 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done }, 1259 // Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1 1260 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done }, 1261 // Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1 1262 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done }, 1263 // Convert__Reg1_0__Reg1_3__UImm7Lsb001_1 1264 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done }, 1265 // Convert__Reg1_0__Reg1_3__UImm8Lsb001_1 1266 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done }, 1267 // Convert__SImm12Lsb01_0 1268 { CVT_95_addImmOperands, 1, CVT_Done }, 1269 // Convert__Reg1_0 1270 { CVT_95_Reg, 1, CVT_Done }, 1271 // Convert__Reg1_0__SImm61_1 1272 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1273 // Convert__Reg1_0__CLUIImm1_1 1274 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1275 // Convert__SImm6NonZero1_0 1276 { CVT_95_addImmOperands, 1, CVT_Done }, 1277 // Convert__regX0__Tie0_1_1__regX5 1278 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX5, 0, CVT_Done }, 1279 // Convert__regX0__Tie0_1_1__regX2 1280 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX2, 0, CVT_Done }, 1281 // Convert__regX0__Tie0_1_1__regX3 1282 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX3, 0, CVT_Done }, 1283 // Convert__regX0__Tie0_1_1__regX4 1284 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX4, 0, CVT_Done }, 1285 // Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1 1286 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done }, 1287 // Convert__Reg1_0__Tie0_1_1 1288 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done }, 1289 // Convert__CallSymbol1_0 1290 { CVT_95_addImmOperands, 1, CVT_Done }, 1291 // Convert__Reg1_0__CallSymbol1_1 1292 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1293 // Convert__ZeroOffsetMemOpOperand1_0 1294 { CVT_95_addRegOperands, 1, CVT_Done }, 1295 // Convert__regX0__CSRSystemRegister1_0__Reg1_1 1296 { CVT_regX0, 0, CVT_95_addCSRSystemRegisterOperands, 1, CVT_95_Reg, 2, CVT_Done }, 1297 // Convert__regX0__CSRSystemRegister1_0__UImm51_1 1298 { CVT_regX0, 0, CVT_95_addCSRSystemRegisterOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1299 // Convert__Reg1_0__CSRSystemRegister1_1__regX0 1300 { CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_regX0, 0, CVT_Done }, 1301 // Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2 1302 { CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_95_Reg, 3, CVT_Done }, 1303 // Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2 1304 { CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, 1305 // Convert__imm_95_0__imm_95_0 1306 { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done }, 1307 // Convert__Reg1_0__Reg1_1__Reg1_1 1308 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_Done }, 1309 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1 1310 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done }, 1311 // Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_1 1312 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done }, 1313 // Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_1 1314 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done }, 1315 // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7 1316 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_7, 0, CVT_Done }, 1317 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__imm_95_7 1318 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_imm_95_7, 0, CVT_Done }, 1319 // Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__imm_95_7 1320 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_imm_95_7, 0, CVT_Done }, 1321 // Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3 1322 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addFRMArgOperands, 4, CVT_Done }, 1323 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3 1324 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands, 4, CVT_Done }, 1325 // Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__FRMArg1_3 1326 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands, 4, CVT_Done }, 1327 // Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__imm_95_7 1328 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_imm_95_7, 0, CVT_Done }, 1329 // Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__FRMArg1_3 1330 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands, 4, CVT_Done }, 1331 // Convert__Reg1_0__GPRF64AsFPR1_1 1332 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done }, 1333 // Convert__Reg1_0__GPRPF64AsFPR1_1 1334 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done }, 1335 // Convert__Reg1_0__GPRAsFPR1_1 1336 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done }, 1337 // Convert__GPRF64AsFPR1_0__GPRAsFPR1_1 1338 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done }, 1339 // Convert__Reg1_0__Reg1_1__imm_95_7 1340 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_7, 0, CVT_Done }, 1341 // Convert__GPRF64AsFPR1_0__Reg1_1__imm_95_7 1342 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_imm_95_7, 0, CVT_Done }, 1343 // Convert__Reg1_0__Reg1_1__FRMArg1_2 1344 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands, 3, CVT_Done }, 1345 // Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2 1346 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands, 3, CVT_Done }, 1347 // Convert__GPRPF64AsFPR1_0__GPRAsFPR1_1 1348 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done }, 1349 // Convert__GPRF64AsFPR1_0__Reg1_1 1350 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_Done }, 1351 // Convert__GPRPF64AsFPR1_0__Reg1_1 1352 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_Done }, 1353 // Convert__GPRAsFPR1_0__GPRF64AsFPR1_1__imm_95_7 1354 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_imm_95_7, 0, CVT_Done }, 1355 // Convert__GPRAsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2 1356 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands, 3, CVT_Done }, 1357 // Convert__GPRAsFPR1_0__Reg1_1__imm_95_7 1358 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_imm_95_7, 0, CVT_Done }, 1359 // Convert__GPRAsFPR1_0__Reg1_1__FRMArg1_2 1360 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands, 3, CVT_Done }, 1361 // Convert__GPRAsFPR1_0__GPRAsFPR1_1__imm_95_7 1362 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_imm_95_7, 0, CVT_Done }, 1363 // Convert__GPRAsFPR1_0__GPRAsFPR1_1__FRMArg1_2 1364 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands, 3, CVT_Done }, 1365 // Convert__Reg1_0__GPRF64AsFPR1_1__imm_95_7 1366 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_imm_95_7, 0, CVT_Done }, 1367 // Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2 1368 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands, 3, CVT_Done }, 1369 // Convert__Reg1_0__GPRAsFPR1_1__imm_95_7 1370 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_imm_95_7, 0, CVT_Done }, 1371 // Convert__Reg1_0__GPRAsFPR1_1__FRMArg1_2 1372 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands, 3, CVT_Done }, 1373 // Convert__GPRAsFPR1_0__GPRPF64AsFPR1_1__imm_95_7 1374 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_imm_95_7, 0, CVT_Done }, 1375 // Convert__GPRAsFPR1_0__GPRPF64AsFPR1_1__FRMArg1_2 1376 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands, 3, CVT_Done }, 1377 // Convert__GPRAsFPR1_0__GPRAsFPR1_1 1378 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done }, 1379 // Convert__Reg1_0__GPRPF64AsFPR1_1__imm_95_7 1380 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_imm_95_7, 0, CVT_Done }, 1381 // Convert__Reg1_0__GPRPF64AsFPR1_1__FRMArg1_2 1382 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands, 3, CVT_Done }, 1383 // Convert__imm_95_15__imm_95_15 1384 { CVT_imm_95_15, 0, CVT_imm_95_15, 0, CVT_Done }, 1385 // Convert__FenceArg1_0__FenceArg1_1 1386 { CVT_95_addFenceArgOperands, 1, CVT_95_addFenceArgOperands, 2, CVT_Done }, 1387 // Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2 1388 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done }, 1389 // Convert__Reg1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2 1390 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done }, 1391 // Convert__Reg1_0__GPRAsFPR1_1__GPRAsFPR1_2 1392 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done }, 1393 // Convert__Reg1_0__Reg1_2__Reg1_1 1394 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done }, 1395 // Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1 1396 { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done }, 1397 // Convert__Reg1_0__GPRPF64AsFPR1_2__GPRPF64AsFPR1_1 1398 { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done }, 1399 // Convert__Reg1_0__GPRAsFPR1_2__GPRAsFPR1_1 1400 { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done }, 1401 // Convert__Reg1_2__Reg1_0__BareSymbol1_1 1402 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1403 // Convert__Reg1_0__Reg1_3__SImm121_1 1404 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done }, 1405 // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7 1406 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_7, 0, CVT_Done }, 1407 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__imm_95_7 1408 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_imm_95_7, 0, CVT_Done }, 1409 // Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__GPRPF64AsFPR1_3__imm_95_7 1410 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_imm_95_7, 0, CVT_Done }, 1411 // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4 1412 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addFRMArgOperands, 5, CVT_Done }, 1413 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4 1414 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands, 5, CVT_Done }, 1415 // Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__GPRPF64AsFPR1_3__FRMArg1_4 1416 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands, 5, CVT_Done }, 1417 // Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__imm_95_7 1418 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_imm_95_7, 0, CVT_Done }, 1419 // Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__FRMArg1_4 1420 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands, 5, CVT_Done }, 1421 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2 1422 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done }, 1423 // Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2 1424 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done }, 1425 // Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2 1426 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done }, 1427 // Convert__Reg1_0__imm_95_3__regX0 1428 { CVT_95_Reg, 1, CVT_imm_95_3, 0, CVT_regX0, 0, CVT_Done }, 1429 // Convert__Reg1_0__imm_95_1__regX0 1430 { CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_regX0, 0, CVT_Done }, 1431 // Convert__Reg1_0__imm_95_2__regX0 1432 { CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_regX0, 0, CVT_Done }, 1433 // Convert__regX0__imm_95_3__Reg1_0 1434 { CVT_regX0, 0, CVT_imm_95_3, 0, CVT_95_Reg, 1, CVT_Done }, 1435 // Convert__Reg1_0__imm_95_3__Reg1_1 1436 { CVT_95_Reg, 1, CVT_imm_95_3, 0, CVT_95_Reg, 2, CVT_Done }, 1437 // Convert__regX0__imm_95_1__Reg1_0 1438 { CVT_regX0, 0, CVT_imm_95_1, 0, CVT_95_Reg, 1, CVT_Done }, 1439 // Convert__Reg1_0__imm_95_1__Reg1_1 1440 { CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_95_Reg, 2, CVT_Done }, 1441 // Convert__regX0__imm_95_1__UImm51_0 1442 { CVT_regX0, 0, CVT_imm_95_1, 0, CVT_95_addImmOperands, 1, CVT_Done }, 1443 // Convert__Reg1_0__imm_95_1__UImm51_1 1444 { CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_95_addImmOperands, 2, CVT_Done }, 1445 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__imm_95_7 1446 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_imm_95_7, 0, CVT_Done }, 1447 // Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__imm_95_7 1448 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_imm_95_7, 0, CVT_Done }, 1449 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2 1450 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands, 3, CVT_Done }, 1451 // Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__FRMArg1_2 1452 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands, 3, CVT_Done }, 1453 // Convert__regX0__imm_95_2__Reg1_0 1454 { CVT_regX0, 0, CVT_imm_95_2, 0, CVT_95_Reg, 1, CVT_Done }, 1455 // Convert__Reg1_0__imm_95_2__Reg1_1 1456 { CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_95_Reg, 2, CVT_Done }, 1457 // Convert__regX0__imm_95_2__UImm51_0 1458 { CVT_regX0, 0, CVT_imm_95_2, 0, CVT_95_addImmOperands, 1, CVT_Done }, 1459 // Convert__Reg1_0__imm_95_2__UImm51_1 1460 { CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_95_addImmOperands, 2, CVT_Done }, 1461 // Convert__regX0__regX0 1462 { CVT_regX0, 0, CVT_regX0, 0, CVT_Done }, 1463 // Convert__Reg1_0__regX0 1464 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_Done }, 1465 // Convert__Reg1_0__ZeroOffsetMemOpOperand1_1 1466 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done }, 1467 // Convert__regX0__SImm21Lsb0JAL1_0 1468 { CVT_regX0, 0, CVT_95_addImmOperands, 1, CVT_Done }, 1469 // Convert__regX1__SImm21Lsb0JAL1_0 1470 { CVT_regX1, 0, CVT_95_addImmOperands, 1, CVT_Done }, 1471 // Convert__Reg1_0__SImm21Lsb0JAL1_1 1472 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1473 // Convert__regX1__Reg1_0__imm_95_0 1474 { CVT_regX1, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done }, 1475 // Convert__Reg1_0__Reg1_1__imm_95_0 1476 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done }, 1477 // Convert__regX1__Reg1_0__SImm121_1 1478 { CVT_regX1, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1479 // Convert__regX1__Reg1_2__SImm121_0 1480 { CVT_regX1, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done }, 1481 // Convert__regX0__Reg1_0__imm_95_0 1482 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done }, 1483 // Convert__regX0__Reg1_0__SImm121_1 1484 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1485 // Convert__regX0__Reg1_2__SImm121_0 1486 { CVT_regX0, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done }, 1487 // Convert__Reg1_1__PseudoJumpSymbol1_0 1488 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done }, 1489 // Convert__Reg1_0__BareSymbol1_1 1490 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1491 // Convert__Reg1_0__regX0__SImm121_1 1492 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_addImmOperands, 2, CVT_Done }, 1493 // Convert__Reg1_0__ImmXLenLI1_1 1494 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1495 // Convert__Reg1_0__UImm20LUI1_1 1496 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1497 // Convert__Reg1_0__regX0__Reg1_1 1498 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_Reg, 2, CVT_Done }, 1499 // Convert__regX0__regX0__imm_95_0 1500 { CVT_regX0, 0, CVT_regX0, 0, CVT_imm_95_0, 0, CVT_Done }, 1501 // Convert__Reg1_0__Reg1_1__imm_95__MINUS_1 1502 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_Done }, 1503 // Convert__regX0__regX0__regX5 1504 { CVT_regX0, 0, CVT_regX0, 0, CVT_regX5, 0, CVT_Done }, 1505 // Convert__regX0__regX0__regX2 1506 { CVT_regX0, 0, CVT_regX0, 0, CVT_regX2, 0, CVT_Done }, 1507 // Convert__regX0__regX0__regX3 1508 { CVT_regX0, 0, CVT_regX0, 0, CVT_regX3, 0, CVT_Done }, 1509 // Convert__regX0__regX0__regX4 1510 { CVT_regX0, 0, CVT_regX0, 0, CVT_regX4, 0, CVT_Done }, 1511 // Convert__imm_95_1__imm_95_0 1512 { CVT_imm_95_1, 0, CVT_imm_95_0, 0, CVT_Done }, 1513 // Convert__Reg1_2__SImm12Lsb000001_0 1514 { CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done }, 1515 // Convert__Reg1_0__imm_95_3072__regX0 1516 { CVT_95_Reg, 1, CVT_imm_95_3072, 0, CVT_regX0, 0, CVT_Done }, 1517 // Convert__Reg1_0__imm_95_3200__regX0 1518 { CVT_95_Reg, 1, CVT_imm_95_3200, 0, CVT_regX0, 0, CVT_Done }, 1519 // Convert__Reg1_0__imm_95_3074__regX0 1520 { CVT_95_Reg, 1, CVT_imm_95_3074, 0, CVT_regX0, 0, CVT_Done }, 1521 // Convert__Reg1_0__imm_95_3202__regX0 1522 { CVT_95_Reg, 1, CVT_imm_95_3202, 0, CVT_regX0, 0, CVT_Done }, 1523 // Convert__Reg1_0__imm_95_3073__regX0 1524 { CVT_95_Reg, 1, CVT_imm_95_3073, 0, CVT_regX0, 0, CVT_Done }, 1525 // Convert__Reg1_0__imm_95_3201__regX0 1526 { CVT_95_Reg, 1, CVT_imm_95_3201, 0, CVT_regX0, 0, CVT_Done }, 1527 // Convert__regX0__regX1__imm_95_0 1528 { CVT_regX0, 0, CVT_regX1, 0, CVT_imm_95_0, 0, CVT_Done }, 1529 // Convert__Reg1_0__Reg1_1__UImm51_2 1530 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done }, 1531 // Convert__Reg1_0__Reg1_1__imm_95_1 1532 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_1, 0, CVT_Done }, 1533 // Convert__Reg1_0__Reg1_1__regX0 1534 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_Done }, 1535 // Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3 1536 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done }, 1537 // Convert__Reg1_0__Reg1_1__SImm51_2__imm_95_0 1538 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done }, 1539 // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0 1540 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done }, 1541 // Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3 1542 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done }, 1543 // Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2 1544 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done }, 1545 // Convert__Reg1_0__Reg1_1__Reg1_1__reg0 1546 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_reg0, 0, CVT_Done }, 1547 // Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2 1548 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done }, 1549 // Convert__Reg1_0__RVVMaskRegOpOperand1_1 1550 { CVT_95_Reg, 1, CVT_95_addRegOperands_95_defaultMaskRegOp, 2, CVT_Done }, 1551 // Convert__Reg1_0__Reg1_2 1552 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Done }, 1553 // Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4 1554 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 5, CVT_Done }, 1555 // Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5 1556 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addRegOperands_95_defaultMaskRegOp, 6, CVT_Done }, 1557 // Convert__Reg1_0__Reg1_1__SImm51_2 1558 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done }, 1559 // Convert__Reg1_0__Reg1_0__Reg1_0 1560 { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_Done }, 1561 // Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3 1562 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done }, 1563 // Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3 1564 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done }, 1565 // Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3 1566 { CVT_95_Reg, 1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done }, 1567 // Convert__Reg1_0__SImm51_1 1568 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1569 // Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3 1570 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done }, 1571 // Convert__Reg1_0__Reg1_1__regX0__reg0 1572 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_reg0, 0, CVT_Done }, 1573 // Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2 1574 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done }, 1575 // Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__reg0 1576 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_reg0, 0, CVT_Done }, 1577 // Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__RVVMaskRegOpOperand1_2 1578 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done }, 1579 // Convert__Reg1_0__UImm51_1__VTypeI101_2 1580 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addVTypeIOperands, 3, CVT_Done }, 1581 // Convert__Reg1_0__Reg1_1__VTypeI111_2 1582 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addVTypeIOperands, 3, CVT_Done }, 1583 // Convert__Reg1_0__Reg1_1__imm_95_255 1584 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_255, 0, CVT_Done }, 1585}; 1586 1587void RISCVAsmParser:: 1588convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, 1589 const OperandVector &Operands, 1590 const SmallBitVector &OptionalOperandsMask) { 1591 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); 1592 const uint8_t *Converter = ConversionTable[Kind]; 1593 unsigned DefaultsOffset[8] = { 0 }; 1594 assert(OptionalOperandsMask.size() == 7); 1595 for (unsigned i = 0, NumDefaults = 0; i < 7; ++i) { 1596 DefaultsOffset[i + 1] = NumDefaults; 1597 NumDefaults += (OptionalOperandsMask[i] ? 1 : 0); 1598 } 1599 unsigned OpIdx; 1600 Inst.setOpcode(Opcode); 1601 for (const uint8_t *p = Converter; *p; p += 2) { 1602 OpIdx = *(p + 1) - DefaultsOffset[*(p + 1)]; 1603 switch (*p) { 1604 default: llvm_unreachable("invalid conversion entry!"); 1605 case CVT_Reg: 1606 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1); 1607 break; 1608 case CVT_Tied: { 1609 assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) - 1610 std::begin(TiedAsmOperandTable)) && 1611 "Tied operand not found"); 1612 unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0]; 1613 if (TiedResOpnd != (uint8_t)-1) 1614 Inst.addOperand(Inst.getOperand(TiedResOpnd)); 1615 break; 1616 } 1617 case CVT_95_addImmOperands: 1618 static_cast<RISCVOperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1); 1619 break; 1620 case CVT_95_Reg: 1621 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1); 1622 break; 1623 case CVT_95_addRegOperands: 1624 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1); 1625 break; 1626 case CVT_regX0: 1627 Inst.addOperand(MCOperand::createReg(RISCV::X0)); 1628 break; 1629 case CVT_imm_95_0: 1630 Inst.addOperand(MCOperand::createImm(0)); 1631 break; 1632 case CVT_regX5: 1633 Inst.addOperand(MCOperand::createReg(RISCV::X5)); 1634 break; 1635 case CVT_regX2: 1636 Inst.addOperand(MCOperand::createReg(RISCV::X2)); 1637 break; 1638 case CVT_regX3: 1639 Inst.addOperand(MCOperand::createReg(RISCV::X3)); 1640 break; 1641 case CVT_regX4: 1642 Inst.addOperand(MCOperand::createReg(RISCV::X4)); 1643 break; 1644 case CVT_95_addCSRSystemRegisterOperands: 1645 static_cast<RISCVOperand &>(*Operands[OpIdx]).addCSRSystemRegisterOperands(Inst, 1); 1646 break; 1647 case CVT_imm_95_7: 1648 Inst.addOperand(MCOperand::createImm(7)); 1649 break; 1650 case CVT_95_addFRMArgOperands: 1651 static_cast<RISCVOperand &>(*Operands[OpIdx]).addFRMArgOperands(Inst, 1); 1652 break; 1653 case CVT_imm_95_15: 1654 Inst.addOperand(MCOperand::createImm(15)); 1655 break; 1656 case CVT_95_addFenceArgOperands: 1657 static_cast<RISCVOperand &>(*Operands[OpIdx]).addFenceArgOperands(Inst, 1); 1658 break; 1659 case CVT_imm_95_3: 1660 Inst.addOperand(MCOperand::createImm(3)); 1661 break; 1662 case CVT_imm_95_1: 1663 Inst.addOperand(MCOperand::createImm(1)); 1664 break; 1665 case CVT_imm_95_2: 1666 Inst.addOperand(MCOperand::createImm(2)); 1667 break; 1668 case CVT_regX1: 1669 Inst.addOperand(MCOperand::createReg(RISCV::X1)); 1670 break; 1671 case CVT_imm_95__MINUS_1: 1672 Inst.addOperand(MCOperand::createImm(-1)); 1673 break; 1674 case CVT_imm_95_3072: 1675 Inst.addOperand(MCOperand::createImm(3072)); 1676 break; 1677 case CVT_imm_95_3200: 1678 Inst.addOperand(MCOperand::createImm(3200)); 1679 break; 1680 case CVT_imm_95_3074: 1681 Inst.addOperand(MCOperand::createImm(3074)); 1682 break; 1683 case CVT_imm_95_3202: 1684 Inst.addOperand(MCOperand::createImm(3202)); 1685 break; 1686 case CVT_imm_95_3073: 1687 Inst.addOperand(MCOperand::createImm(3073)); 1688 break; 1689 case CVT_imm_95_3201: 1690 Inst.addOperand(MCOperand::createImm(3201)); 1691 break; 1692 case CVT_95_addRegOperands_95_defaultMaskRegOp: 1693 if (OptionalOperandsMask[*(p + 1) - 1]) { 1694 defaultMaskRegOp()->addRegOperands(Inst, 1); 1695 } else { 1696 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1); 1697 } 1698 break; 1699 case CVT_reg0: 1700 Inst.addOperand(MCOperand::createReg(0)); 1701 break; 1702 case CVT_95_addVTypeIOperands: 1703 static_cast<RISCVOperand &>(*Operands[OpIdx]).addVTypeIOperands(Inst, 1); 1704 break; 1705 case CVT_imm_95_255: 1706 Inst.addOperand(MCOperand::createImm(255)); 1707 break; 1708 } 1709 } 1710} 1711 1712void RISCVAsmParser:: 1713convertToMapAndConstraints(unsigned Kind, 1714 const OperandVector &Operands) { 1715 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); 1716 unsigned NumMCOperands = 0; 1717 const uint8_t *Converter = ConversionTable[Kind]; 1718 for (const uint8_t *p = Converter; *p; p += 2) { 1719 switch (*p) { 1720 default: llvm_unreachable("invalid conversion entry!"); 1721 case CVT_Reg: 1722 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1723 Operands[*(p + 1)]->setConstraint("r"); 1724 ++NumMCOperands; 1725 break; 1726 case CVT_Tied: 1727 ++NumMCOperands; 1728 break; 1729 case CVT_95_addImmOperands: 1730 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1731 Operands[*(p + 1)]->setConstraint("m"); 1732 NumMCOperands += 1; 1733 break; 1734 case CVT_95_Reg: 1735 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1736 Operands[*(p + 1)]->setConstraint("r"); 1737 NumMCOperands += 1; 1738 break; 1739 case CVT_95_addRegOperands: 1740 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1741 Operands[*(p + 1)]->setConstraint("m"); 1742 NumMCOperands += 1; 1743 break; 1744 case CVT_regX0: 1745 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1746 Operands[*(p + 1)]->setConstraint("m"); 1747 ++NumMCOperands; 1748 break; 1749 case CVT_imm_95_0: 1750 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1751 Operands[*(p + 1)]->setConstraint(""); 1752 ++NumMCOperands; 1753 break; 1754 case CVT_regX5: 1755 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1756 Operands[*(p + 1)]->setConstraint("m"); 1757 ++NumMCOperands; 1758 break; 1759 case CVT_regX2: 1760 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1761 Operands[*(p + 1)]->setConstraint("m"); 1762 ++NumMCOperands; 1763 break; 1764 case CVT_regX3: 1765 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1766 Operands[*(p + 1)]->setConstraint("m"); 1767 ++NumMCOperands; 1768 break; 1769 case CVT_regX4: 1770 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1771 Operands[*(p + 1)]->setConstraint("m"); 1772 ++NumMCOperands; 1773 break; 1774 case CVT_95_addCSRSystemRegisterOperands: 1775 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1776 Operands[*(p + 1)]->setConstraint("m"); 1777 NumMCOperands += 1; 1778 break; 1779 case CVT_imm_95_7: 1780 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1781 Operands[*(p + 1)]->setConstraint(""); 1782 ++NumMCOperands; 1783 break; 1784 case CVT_95_addFRMArgOperands: 1785 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1786 Operands[*(p + 1)]->setConstraint("m"); 1787 NumMCOperands += 1; 1788 break; 1789 case CVT_imm_95_15: 1790 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1791 Operands[*(p + 1)]->setConstraint(""); 1792 ++NumMCOperands; 1793 break; 1794 case CVT_95_addFenceArgOperands: 1795 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1796 Operands[*(p + 1)]->setConstraint("m"); 1797 NumMCOperands += 1; 1798 break; 1799 case CVT_imm_95_3: 1800 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1801 Operands[*(p + 1)]->setConstraint(""); 1802 ++NumMCOperands; 1803 break; 1804 case CVT_imm_95_1: 1805 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1806 Operands[*(p + 1)]->setConstraint(""); 1807 ++NumMCOperands; 1808 break; 1809 case CVT_imm_95_2: 1810 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1811 Operands[*(p + 1)]->setConstraint(""); 1812 ++NumMCOperands; 1813 break; 1814 case CVT_regX1: 1815 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1816 Operands[*(p + 1)]->setConstraint("m"); 1817 ++NumMCOperands; 1818 break; 1819 case CVT_imm_95__MINUS_1: 1820 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1821 Operands[*(p + 1)]->setConstraint(""); 1822 ++NumMCOperands; 1823 break; 1824 case CVT_imm_95_3072: 1825 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1826 Operands[*(p + 1)]->setConstraint(""); 1827 ++NumMCOperands; 1828 break; 1829 case CVT_imm_95_3200: 1830 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1831 Operands[*(p + 1)]->setConstraint(""); 1832 ++NumMCOperands; 1833 break; 1834 case CVT_imm_95_3074: 1835 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1836 Operands[*(p + 1)]->setConstraint(""); 1837 ++NumMCOperands; 1838 break; 1839 case CVT_imm_95_3202: 1840 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1841 Operands[*(p + 1)]->setConstraint(""); 1842 ++NumMCOperands; 1843 break; 1844 case CVT_imm_95_3073: 1845 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1846 Operands[*(p + 1)]->setConstraint(""); 1847 ++NumMCOperands; 1848 break; 1849 case CVT_imm_95_3201: 1850 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1851 Operands[*(p + 1)]->setConstraint(""); 1852 ++NumMCOperands; 1853 break; 1854 case CVT_95_addRegOperands_95_defaultMaskRegOp: 1855 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1856 Operands[*(p + 1)]->setConstraint("m"); 1857 NumMCOperands += 1; 1858 break; 1859 case CVT_reg0: 1860 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1861 Operands[*(p + 1)]->setConstraint("m"); 1862 ++NumMCOperands; 1863 break; 1864 case CVT_95_addVTypeIOperands: 1865 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1866 Operands[*(p + 1)]->setConstraint("m"); 1867 NumMCOperands += 1; 1868 break; 1869 case CVT_imm_95_255: 1870 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1871 Operands[*(p + 1)]->setConstraint(""); 1872 ++NumMCOperands; 1873 break; 1874 } 1875 } 1876} 1877 1878namespace { 1879 1880/// MatchClassKind - The kinds of classes which participate in 1881/// instruction matching. 1882enum MatchClassKind { 1883 InvalidMatchClass = 0, 1884 OptionalMatchClass = 1, 1885 MCK__40_, // '(' 1886 MCK__41_, // ')' 1887 MCK_LAST_TOKEN = MCK__41_, 1888 MCK_Reg69, // derived register class 1889 MCK_Reg66, // derived register class 1890 MCK_Reg63, // derived register class 1891 MCK_Reg60, // derived register class 1892 MCK_Reg57, // derived register class 1893 MCK_Reg54, // derived register class 1894 MCK_Reg51, // derived register class 1895 MCK_Reg48, // derived register class 1896 MCK_Reg45, // derived register class 1897 MCK_Reg42, // derived register class 1898 MCK_Reg39, // derived register class 1899 MCK_Reg30, // derived register class 1900 MCK_Reg28, // derived register class 1901 MCK_Reg24, // derived register class 1902 MCK_Reg21, // derived register class 1903 MCK_Reg18, // derived register class 1904 MCK_GPRX0, // register class 'GPRX0' 1905 MCK_SP, // register class 'SP' 1906 MCK_VMV0, // register class 'VMV0,V0' 1907 MCK_Reg36, // derived register class 1908 MCK_VCSR, // register class 'VCSR' 1909 MCK_VRM8NoV0, // register class 'VRM8NoV0' 1910 MCK_Reg35, // derived register class 1911 MCK_VRM8, // register class 'VRM8' 1912 MCK_Reg9, // derived register class 1913 MCK_VRN2M4NoV0, // register class 'VRN2M4NoV0' 1914 MCK_Reg34, // derived register class 1915 MCK_VRM4NoV0, // register class 'VRM4NoV0' 1916 MCK_VRN2M4, // register class 'VRN2M4' 1917 MCK_FPR32C, // register class 'FPR32C' 1918 MCK_FPR64C, // register class 'FPR64C' 1919 MCK_GPRC, // register class 'GPRC' 1920 MCK_VRM4, // register class 'VRM4' 1921 MCK_VRN4M2NoV0, // register class 'VRN4M2NoV0' 1922 MCK_Reg33, // derived register class 1923 MCK_VRN3M2NoV0, // register class 'VRN3M2NoV0' 1924 MCK_VRN4M2, // register class 'VRN4M2' 1925 MCK_Reg32, // derived register class 1926 MCK_GPRTC, // register class 'GPRTC' 1927 MCK_VRN2M2NoV0, // register class 'VRN2M2NoV0' 1928 MCK_VRN3M2, // register class 'VRN3M2' 1929 MCK_Reg31, // derived register class 1930 MCK_VRM2NoV0, // register class 'VRM2NoV0' 1931 MCK_VRN2M2, // register class 'VRN2M2' 1932 MCK_GPRPF64, // register class 'GPRPF64' 1933 MCK_VRM2, // register class 'VRM2' 1934 MCK_VRN8M1NoV0, // register class 'VRN8M1NoV0' 1935 MCK_VRN7M1NoV0, // register class 'VRN7M1NoV0' 1936 MCK_VRN8M1, // register class 'VRN8M1' 1937 MCK_GPRJALR, // register class 'GPRJALR' 1938 MCK_VRN6M1NoV0, // register class 'VRN6M1NoV0' 1939 MCK_VRN7M1, // register class 'VRN7M1' 1940 MCK_VRN5M1NoV0, // register class 'VRN5M1NoV0' 1941 MCK_VRN6M1, // register class 'VRN6M1' 1942 MCK_VRN4M1NoV0, // register class 'VRN4M1NoV0' 1943 MCK_VRN5M1, // register class 'VRN5M1' 1944 MCK_VRN3M1NoV0, // register class 'VRN3M1NoV0' 1945 MCK_VRN4M1, // register class 'VRN4M1' 1946 MCK_GPRNoX0X2, // register class 'GPRNoX0X2' 1947 MCK_VRN2M1NoV0, // register class 'VRN2M1NoV0' 1948 MCK_VRN3M1, // register class 'VRN3M1' 1949 MCK_GPRNoX0, // register class 'GPRNoX0' 1950 MCK_VRN2M1, // register class 'VRN2M1' 1951 MCK_VRNoV0, // register class 'VRNoV0' 1952 MCK_FPR16, // register class 'FPR16' 1953 MCK_FPR32, // register class 'FPR32' 1954 MCK_FPR64, // register class 'FPR64' 1955 MCK_GPR, // register class 'GPR,GPRF16,GPRF32,GPRF64' 1956 MCK_VM, // register class 'VM,VR' 1957 MCK_AnyReg, // register class 'AnyReg' 1958 MCK_LAST_REGISTER = MCK_AnyReg, 1959 MCK_BareSymbol, // user defined class 'BareSymbol' 1960 MCK_CLUIImm, // user defined class 'CLUIImmAsmOperand' 1961 MCK_CSRSystemRegister, // user defined class 'CSRSystemRegister' 1962 MCK_CallSymbol, // user defined class 'CallSymbol' 1963 MCK_FRMArg, // user defined class 'FRMArg' 1964 MCK_FenceArg, // user defined class 'FenceArg' 1965 MCK_GPRAsFPR, // user defined class 'GPRAsFPR' 1966 MCK_GPRF64AsFPR, // user defined class 'GPRF64AsFPR' 1967 MCK_GPRPF64AsFPR, // user defined class 'GPRPF64AsFPR' 1968 MCK_Imm, // user defined class 'ImmAsmOperand' 1969 MCK_ImmZero, // user defined class 'ImmZeroAsmOperand' 1970 MCK_InsnDirectiveOpcode, // user defined class 'InsnDirectiveOpcode' 1971 MCK_PseudoJumpSymbol, // user defined class 'PseudoJumpSymbol' 1972 MCK_RnumArg, // user defined class 'RnumArg' 1973 MCK_SImm5Plus1, // user defined class 'SImm5Plus1AsmOperand' 1974 MCK_SImm21Lsb0JAL, // user defined class 'Simm21Lsb0JALAsmOperand' 1975 MCK_TPRelAddSymbol, // user defined class 'TPRelAddSymbol' 1976 MCK_UImmLog2XLen, // user defined class 'UImmLog2XLenAsmOperand' 1977 MCK_UImmLog2XLenHalf, // user defined class 'UImmLog2XLenHalfAsmOperand' 1978 MCK_UImmLog2XLenNonZero, // user defined class 'UImmLog2XLenNonZeroAsmOperand' 1979 MCK_RVVMaskRegOpOperand, // user defined class 'VMaskAsmOperand' 1980 MCK_ZeroOffsetMemOpOperand, // user defined class 'ZeroOffsetMemOpOperand' 1981 MCK_UImm2, // user defined class 'anonymous_4648' 1982 MCK_UImm3, // user defined class 'anonymous_4649' 1983 MCK_UImm5, // user defined class 'anonymous_4650' 1984 MCK_UImm7, // user defined class 'anonymous_4651' 1985 MCK_SImm12, // user defined class 'anonymous_4652' 1986 MCK_SImm13Lsb0, // user defined class 'anonymous_4653' 1987 MCK_UImm20LUI, // user defined class 'anonymous_4654' 1988 MCK_UImm20AUIPC, // user defined class 'anonymous_4655' 1989 MCK_ImmXLenLI, // user defined class 'anonymous_4656' 1990 MCK_SImm12Lsb00000, // user defined class 'anonymous_49973' 1991 MCK_SImm6, // user defined class 'anonymous_5403' 1992 MCK_SImm6NonZero, // user defined class 'anonymous_5404' 1993 MCK_UImm7Lsb00, // user defined class 'anonymous_5405' 1994 MCK_UImm8Lsb00, // user defined class 'anonymous_5406' 1995 MCK_UImm8Lsb000, // user defined class 'anonymous_5407' 1996 MCK_SImm9Lsb0, // user defined class 'anonymous_5408' 1997 MCK_UImm9Lsb000, // user defined class 'anonymous_5409' 1998 MCK_UImm10Lsb00NonZero, // user defined class 'anonymous_5410' 1999 MCK_SImm10Lsb0000NonZero, // user defined class 'anonymous_5411' 2000 MCK_SImm12Lsb0, // user defined class 'anonymous_5412' 2001 MCK_VTypeI10, // user defined class 'anonymous_5639' 2002 MCK_VTypeI11, // user defined class 'anonymous_5640' 2003 MCK_SImm5, // user defined class 'anonymous_5641' 2004 NumMatchClassKinds 2005}; 2006 2007} // end anonymous namespace 2008 2009static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) { 2010 return MCTargetAsmParser::Match_InvalidOperand; 2011} 2012 2013static MatchClassKind matchTokenString(StringRef Name) { 2014 switch (Name.size()) { 2015 default: break; 2016 case 1: // 2 strings to match. 2017 switch (Name[0]) { 2018 default: break; 2019 case '(': // 1 string to match. 2020 return MCK__40_; // "(" 2021 case ')': // 1 string to match. 2022 return MCK__41_; // ")" 2023 } 2024 break; 2025 } 2026 return InvalidMatchClass; 2027} 2028 2029/// isSubclass - Compute whether \p A is a subclass of \p B. 2030static bool isSubclass(MatchClassKind A, MatchClassKind B) { 2031 if (A == B) 2032 return true; 2033 2034 switch (A) { 2035 default: 2036 return false; 2037 2038 case MCK_Reg69: 2039 return B == MCK_VRN8M1; 2040 2041 case MCK_Reg66: 2042 return B == MCK_VRN7M1; 2043 2044 case MCK_Reg63: 2045 return B == MCK_VRN6M1; 2046 2047 case MCK_Reg60: 2048 return B == MCK_VRN5M1; 2049 2050 case MCK_Reg57: 2051 return B == MCK_VRN4M2; 2052 2053 case MCK_Reg54: 2054 return B == MCK_VRN4M1; 2055 2056 case MCK_Reg51: 2057 return B == MCK_VRN3M2; 2058 2059 case MCK_Reg48: 2060 return B == MCK_VRN3M1; 2061 2062 case MCK_Reg45: 2063 return B == MCK_VRN2M4; 2064 2065 case MCK_Reg42: 2066 return B == MCK_VRN2M2; 2067 2068 case MCK_Reg39: 2069 return B == MCK_VRN2M1; 2070 2071 case MCK_Reg30: 2072 switch (B) { 2073 default: return false; 2074 case MCK_Reg31: return true; 2075 case MCK_GPRPF64: return true; 2076 } 2077 2078 case MCK_Reg28: 2079 return B == MCK_GPRPF64; 2080 2081 case MCK_Reg24: 2082 return B == MCK_VRM8; 2083 2084 case MCK_Reg21: 2085 return B == MCK_VRM4; 2086 2087 case MCK_Reg18: 2088 return B == MCK_VRM2; 2089 2090 case MCK_GPRX0: 2091 switch (B) { 2092 default: return false; 2093 case MCK_GPR: return true; 2094 case MCK_AnyReg: return true; 2095 } 2096 2097 case MCK_SP: 2098 switch (B) { 2099 default: return false; 2100 case MCK_GPRNoX0: return true; 2101 case MCK_GPR: return true; 2102 case MCK_AnyReg: return true; 2103 } 2104 2105 case MCK_VMV0: 2106 switch (B) { 2107 default: return false; 2108 case MCK_VM: return true; 2109 case MCK_AnyReg: return true; 2110 } 2111 2112 case MCK_Reg36: 2113 switch (B) { 2114 default: return false; 2115 case MCK_Reg35: return true; 2116 case MCK_Reg34: return true; 2117 case MCK_Reg33: return true; 2118 case MCK_Reg32: return true; 2119 case MCK_Reg31: return true; 2120 case MCK_GPRPF64: return true; 2121 } 2122 2123 case MCK_VRM8NoV0: 2124 return B == MCK_VRM8; 2125 2126 case MCK_Reg35: 2127 switch (B) { 2128 default: return false; 2129 case MCK_Reg33: return true; 2130 case MCK_Reg32: return true; 2131 case MCK_Reg31: return true; 2132 case MCK_GPRPF64: return true; 2133 } 2134 2135 case MCK_Reg9: 2136 switch (B) { 2137 default: return false; 2138 case MCK_GPRC: return true; 2139 case MCK_GPRTC: return true; 2140 case MCK_GPRJALR: return true; 2141 case MCK_GPRNoX0X2: return true; 2142 case MCK_GPRNoX0: return true; 2143 case MCK_GPR: return true; 2144 case MCK_AnyReg: return true; 2145 } 2146 2147 case MCK_VRN2M4NoV0: 2148 return B == MCK_VRN2M4; 2149 2150 case MCK_Reg34: 2151 switch (B) { 2152 default: return false; 2153 case MCK_Reg33: return true; 2154 case MCK_Reg32: return true; 2155 case MCK_Reg31: return true; 2156 case MCK_GPRPF64: return true; 2157 } 2158 2159 case MCK_VRM4NoV0: 2160 return B == MCK_VRM4; 2161 2162 case MCK_FPR32C: 2163 return B == MCK_FPR32; 2164 2165 case MCK_FPR64C: 2166 switch (B) { 2167 default: return false; 2168 case MCK_FPR64: return true; 2169 case MCK_AnyReg: return true; 2170 } 2171 2172 case MCK_GPRC: 2173 switch (B) { 2174 default: return false; 2175 case MCK_GPRJALR: return true; 2176 case MCK_GPRNoX0X2: return true; 2177 case MCK_GPRNoX0: return true; 2178 case MCK_GPR: return true; 2179 case MCK_AnyReg: return true; 2180 } 2181 2182 case MCK_VRN4M2NoV0: 2183 return B == MCK_VRN4M2; 2184 2185 case MCK_Reg33: 2186 switch (B) { 2187 default: return false; 2188 case MCK_Reg32: return true; 2189 case MCK_Reg31: return true; 2190 case MCK_GPRPF64: return true; 2191 } 2192 2193 case MCK_VRN3M2NoV0: 2194 return B == MCK_VRN3M2; 2195 2196 case MCK_Reg32: 2197 switch (B) { 2198 default: return false; 2199 case MCK_Reg31: return true; 2200 case MCK_GPRPF64: return true; 2201 } 2202 2203 case MCK_GPRTC: 2204 switch (B) { 2205 default: return false; 2206 case MCK_GPRJALR: return true; 2207 case MCK_GPRNoX0X2: return true; 2208 case MCK_GPRNoX0: return true; 2209 case MCK_GPR: return true; 2210 case MCK_AnyReg: return true; 2211 } 2212 2213 case MCK_VRN2M2NoV0: 2214 return B == MCK_VRN2M2; 2215 2216 case MCK_Reg31: 2217 return B == MCK_GPRPF64; 2218 2219 case MCK_VRM2NoV0: 2220 return B == MCK_VRM2; 2221 2222 case MCK_VRN8M1NoV0: 2223 return B == MCK_VRN8M1; 2224 2225 case MCK_VRN7M1NoV0: 2226 return B == MCK_VRN7M1; 2227 2228 case MCK_GPRJALR: 2229 switch (B) { 2230 default: return false; 2231 case MCK_GPRNoX0X2: return true; 2232 case MCK_GPRNoX0: return true; 2233 case MCK_GPR: return true; 2234 case MCK_AnyReg: return true; 2235 } 2236 2237 case MCK_VRN6M1NoV0: 2238 return B == MCK_VRN6M1; 2239 2240 case MCK_VRN5M1NoV0: 2241 return B == MCK_VRN5M1; 2242 2243 case MCK_VRN4M1NoV0: 2244 return B == MCK_VRN4M1; 2245 2246 case MCK_VRN3M1NoV0: 2247 return B == MCK_VRN3M1; 2248 2249 case MCK_GPRNoX0X2: 2250 switch (B) { 2251 default: return false; 2252 case MCK_GPRNoX0: return true; 2253 case MCK_GPR: return true; 2254 case MCK_AnyReg: return true; 2255 } 2256 2257 case MCK_VRN2M1NoV0: 2258 return B == MCK_VRN2M1; 2259 2260 case MCK_GPRNoX0: 2261 switch (B) { 2262 default: return false; 2263 case MCK_GPR: return true; 2264 case MCK_AnyReg: return true; 2265 } 2266 2267 case MCK_VRNoV0: 2268 switch (B) { 2269 default: return false; 2270 case MCK_VM: return true; 2271 case MCK_AnyReg: return true; 2272 } 2273 2274 case MCK_FPR64: 2275 return B == MCK_AnyReg; 2276 2277 case MCK_GPR: 2278 return B == MCK_AnyReg; 2279 2280 case MCK_VM: 2281 return B == MCK_AnyReg; 2282 2283 case MCK_RVVMaskRegOpOperand: 2284 return B == OptionalMatchClass; 2285 } 2286} 2287 2288static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) { 2289 RISCVOperand &Operand = (RISCVOperand &)GOp; 2290 if (Kind == InvalidMatchClass) 2291 return MCTargetAsmParser::Match_InvalidOperand; 2292 2293 if (Operand.isToken() && Kind <= MCK_LAST_TOKEN) 2294 return isSubclass(matchTokenString(Operand.getToken()), Kind) ? 2295 MCTargetAsmParser::Match_Success : 2296 MCTargetAsmParser::Match_InvalidOperand; 2297 2298 switch (Kind) { 2299 default: break; 2300 // 'BareSymbol' class 2301 case MCK_BareSymbol: { 2302 DiagnosticPredicate DP(Operand.isBareSymbol()); 2303 if (DP.isMatch()) 2304 return MCTargetAsmParser::Match_Success; 2305 if (DP.isNearMatch()) 2306 return RISCVAsmParser::Match_InvalidBareSymbol; 2307 break; 2308 } 2309 // 'CLUIImm' class 2310 case MCK_CLUIImm: { 2311 DiagnosticPredicate DP(Operand.isCLUIImm()); 2312 if (DP.isMatch()) 2313 return MCTargetAsmParser::Match_Success; 2314 if (DP.isNearMatch()) 2315 return RISCVAsmParser::Match_InvalidCLUIImm; 2316 break; 2317 } 2318 // 'CSRSystemRegister' class 2319 case MCK_CSRSystemRegister: { 2320 DiagnosticPredicate DP(Operand.isCSRSystemRegister()); 2321 if (DP.isMatch()) 2322 return MCTargetAsmParser::Match_Success; 2323 if (DP.isNearMatch()) 2324 return RISCVAsmParser::Match_InvalidCSRSystemRegister; 2325 break; 2326 } 2327 // 'CallSymbol' class 2328 case MCK_CallSymbol: { 2329 DiagnosticPredicate DP(Operand.isCallSymbol()); 2330 if (DP.isMatch()) 2331 return MCTargetAsmParser::Match_Success; 2332 if (DP.isNearMatch()) 2333 return RISCVAsmParser::Match_InvalidCallSymbol; 2334 break; 2335 } 2336 // 'FRMArg' class 2337 case MCK_FRMArg: { 2338 DiagnosticPredicate DP(Operand.isFRMArg()); 2339 if (DP.isMatch()) 2340 return MCTargetAsmParser::Match_Success; 2341 if (DP.isNearMatch()) 2342 return RISCVAsmParser::Match_InvalidFRMArg; 2343 break; 2344 } 2345 // 'FenceArg' class 2346 case MCK_FenceArg: { 2347 DiagnosticPredicate DP(Operand.isFenceArg()); 2348 if (DP.isMatch()) 2349 return MCTargetAsmParser::Match_Success; 2350 if (DP.isNearMatch()) 2351 return RISCVAsmParser::Match_InvalidFenceArg; 2352 break; 2353 } 2354 // 'GPRAsFPR' class 2355 case MCK_GPRAsFPR: { 2356 DiagnosticPredicate DP(Operand.isGPRAsFPR()); 2357 if (DP.isMatch()) 2358 return MCTargetAsmParser::Match_Success; 2359 break; 2360 } 2361 // 'GPRF64AsFPR' class 2362 case MCK_GPRF64AsFPR: { 2363 DiagnosticPredicate DP(Operand.isGPRF64AsFPR()); 2364 if (DP.isMatch()) 2365 return MCTargetAsmParser::Match_Success; 2366 break; 2367 } 2368 // 'GPRPF64AsFPR' class 2369 case MCK_GPRPF64AsFPR: { 2370 DiagnosticPredicate DP(Operand.isGPRPF64AsFPR()); 2371 if (DP.isMatch()) 2372 return MCTargetAsmParser::Match_Success; 2373 break; 2374 } 2375 // 'Imm' class 2376 case MCK_Imm: { 2377 DiagnosticPredicate DP(Operand.isImm()); 2378 if (DP.isMatch()) 2379 return MCTargetAsmParser::Match_Success; 2380 break; 2381 } 2382 // 'ImmZero' class 2383 case MCK_ImmZero: { 2384 DiagnosticPredicate DP(Operand.isImmZero()); 2385 if (DP.isMatch()) 2386 return MCTargetAsmParser::Match_Success; 2387 if (DP.isNearMatch()) 2388 return RISCVAsmParser::Match_InvalidImmZero; 2389 break; 2390 } 2391 // 'InsnDirectiveOpcode' class 2392 case MCK_InsnDirectiveOpcode: { 2393 DiagnosticPredicate DP(Operand.isImm()); 2394 if (DP.isMatch()) 2395 return MCTargetAsmParser::Match_Success; 2396 break; 2397 } 2398 // 'PseudoJumpSymbol' class 2399 case MCK_PseudoJumpSymbol: { 2400 DiagnosticPredicate DP(Operand.isPseudoJumpSymbol()); 2401 if (DP.isMatch()) 2402 return MCTargetAsmParser::Match_Success; 2403 if (DP.isNearMatch()) 2404 return RISCVAsmParser::Match_InvalidPseudoJumpSymbol; 2405 break; 2406 } 2407 // 'RnumArg' class 2408 case MCK_RnumArg: { 2409 DiagnosticPredicate DP(Operand.isRnumArg()); 2410 if (DP.isMatch()) 2411 return MCTargetAsmParser::Match_Success; 2412 if (DP.isNearMatch()) 2413 return RISCVAsmParser::Match_InvalidRnumArg; 2414 break; 2415 } 2416 // 'SImm5Plus1' class 2417 case MCK_SImm5Plus1: { 2418 DiagnosticPredicate DP(Operand.isSImm5Plus1()); 2419 if (DP.isMatch()) 2420 return MCTargetAsmParser::Match_Success; 2421 if (DP.isNearMatch()) 2422 return RISCVAsmParser::Match_InvalidSImm5Plus1; 2423 break; 2424 } 2425 // 'SImm21Lsb0JAL' class 2426 case MCK_SImm21Lsb0JAL: { 2427 DiagnosticPredicate DP(Operand.isSImm21Lsb0JAL()); 2428 if (DP.isMatch()) 2429 return MCTargetAsmParser::Match_Success; 2430 if (DP.isNearMatch()) 2431 return RISCVAsmParser::Match_InvalidSImm21Lsb0JAL; 2432 break; 2433 } 2434 // 'TPRelAddSymbol' class 2435 case MCK_TPRelAddSymbol: { 2436 DiagnosticPredicate DP(Operand.isTPRelAddSymbol()); 2437 if (DP.isMatch()) 2438 return MCTargetAsmParser::Match_Success; 2439 if (DP.isNearMatch()) 2440 return RISCVAsmParser::Match_InvalidTPRelAddSymbol; 2441 break; 2442 } 2443 // 'UImmLog2XLen' class 2444 case MCK_UImmLog2XLen: { 2445 DiagnosticPredicate DP(Operand.isUImmLog2XLen()); 2446 if (DP.isMatch()) 2447 return MCTargetAsmParser::Match_Success; 2448 if (DP.isNearMatch()) 2449 return RISCVAsmParser::Match_InvalidUImmLog2XLen; 2450 break; 2451 } 2452 // 'UImmLog2XLenHalf' class 2453 case MCK_UImmLog2XLenHalf: { 2454 DiagnosticPredicate DP(Operand.isUImmLog2XLenHalf()); 2455 if (DP.isMatch()) 2456 return MCTargetAsmParser::Match_Success; 2457 if (DP.isNearMatch()) 2458 return RISCVAsmParser::Match_InvalidUImmLog2XLenHalf; 2459 break; 2460 } 2461 // 'UImmLog2XLenNonZero' class 2462 case MCK_UImmLog2XLenNonZero: { 2463 DiagnosticPredicate DP(Operand.isUImmLog2XLenNonZero()); 2464 if (DP.isMatch()) 2465 return MCTargetAsmParser::Match_Success; 2466 if (DP.isNearMatch()) 2467 return RISCVAsmParser::Match_InvalidUImmLog2XLenNonZero; 2468 break; 2469 } 2470 // 'RVVMaskRegOpOperand' class 2471 case MCK_RVVMaskRegOpOperand: { 2472 DiagnosticPredicate DP(Operand.isV0Reg()); 2473 if (DP.isMatch()) 2474 return MCTargetAsmParser::Match_Success; 2475 if (DP.isNearMatch()) 2476 return RISCVAsmParser::Match_InvalidVMaskRegister; 2477 break; 2478 } 2479 // 'ZeroOffsetMemOpOperand' class 2480 case MCK_ZeroOffsetMemOpOperand: { 2481 DiagnosticPredicate DP(Operand.isGPR()); 2482 if (DP.isMatch()) 2483 return MCTargetAsmParser::Match_Success; 2484 break; 2485 } 2486 // 'UImm2' class 2487 case MCK_UImm2: { 2488 DiagnosticPredicate DP(Operand.isUImm2()); 2489 if (DP.isMatch()) 2490 return MCTargetAsmParser::Match_Success; 2491 if (DP.isNearMatch()) 2492 return RISCVAsmParser::Match_InvalidUImm2; 2493 break; 2494 } 2495 // 'UImm3' class 2496 case MCK_UImm3: { 2497 DiagnosticPredicate DP(Operand.isUImm3()); 2498 if (DP.isMatch()) 2499 return MCTargetAsmParser::Match_Success; 2500 if (DP.isNearMatch()) 2501 return RISCVAsmParser::Match_InvalidUImm3; 2502 break; 2503 } 2504 // 'UImm5' class 2505 case MCK_UImm5: { 2506 DiagnosticPredicate DP(Operand.isUImm5()); 2507 if (DP.isMatch()) 2508 return MCTargetAsmParser::Match_Success; 2509 if (DP.isNearMatch()) 2510 return RISCVAsmParser::Match_InvalidUImm5; 2511 break; 2512 } 2513 // 'UImm7' class 2514 case MCK_UImm7: { 2515 DiagnosticPredicate DP(Operand.isUImm7()); 2516 if (DP.isMatch()) 2517 return MCTargetAsmParser::Match_Success; 2518 if (DP.isNearMatch()) 2519 return RISCVAsmParser::Match_InvalidUImm7; 2520 break; 2521 } 2522 // 'SImm12' class 2523 case MCK_SImm12: { 2524 DiagnosticPredicate DP(Operand.isSImm12()); 2525 if (DP.isMatch()) 2526 return MCTargetAsmParser::Match_Success; 2527 if (DP.isNearMatch()) 2528 return RISCVAsmParser::Match_InvalidSImm12; 2529 break; 2530 } 2531 // 'SImm13Lsb0' class 2532 case MCK_SImm13Lsb0: { 2533 DiagnosticPredicate DP(Operand.isSImm13Lsb0()); 2534 if (DP.isMatch()) 2535 return MCTargetAsmParser::Match_Success; 2536 if (DP.isNearMatch()) 2537 return RISCVAsmParser::Match_InvalidSImm13Lsb0; 2538 break; 2539 } 2540 // 'UImm20LUI' class 2541 case MCK_UImm20LUI: { 2542 DiagnosticPredicate DP(Operand.isUImm20LUI()); 2543 if (DP.isMatch()) 2544 return MCTargetAsmParser::Match_Success; 2545 if (DP.isNearMatch()) 2546 return RISCVAsmParser::Match_InvalidUImm20LUI; 2547 break; 2548 } 2549 // 'UImm20AUIPC' class 2550 case MCK_UImm20AUIPC: { 2551 DiagnosticPredicate DP(Operand.isUImm20AUIPC()); 2552 if (DP.isMatch()) 2553 return MCTargetAsmParser::Match_Success; 2554 if (DP.isNearMatch()) 2555 return RISCVAsmParser::Match_InvalidUImm20AUIPC; 2556 break; 2557 } 2558 // 'ImmXLenLI' class 2559 case MCK_ImmXLenLI: { 2560 DiagnosticPredicate DP(Operand.isImmXLenLI()); 2561 if (DP.isMatch()) 2562 return MCTargetAsmParser::Match_Success; 2563 if (DP.isNearMatch()) 2564 return RISCVAsmParser::Match_InvalidImmXLenLI; 2565 break; 2566 } 2567 // 'SImm12Lsb00000' class 2568 case MCK_SImm12Lsb00000: { 2569 DiagnosticPredicate DP(Operand.isSImm12Lsb00000()); 2570 if (DP.isMatch()) 2571 return MCTargetAsmParser::Match_Success; 2572 if (DP.isNearMatch()) 2573 return RISCVAsmParser::Match_InvalidSImm12Lsb00000; 2574 break; 2575 } 2576 // 'SImm6' class 2577 case MCK_SImm6: { 2578 DiagnosticPredicate DP(Operand.isSImm6()); 2579 if (DP.isMatch()) 2580 return MCTargetAsmParser::Match_Success; 2581 if (DP.isNearMatch()) 2582 return RISCVAsmParser::Match_InvalidSImm6; 2583 break; 2584 } 2585 // 'SImm6NonZero' class 2586 case MCK_SImm6NonZero: { 2587 DiagnosticPredicate DP(Operand.isSImm6NonZero()); 2588 if (DP.isMatch()) 2589 return MCTargetAsmParser::Match_Success; 2590 if (DP.isNearMatch()) 2591 return RISCVAsmParser::Match_InvalidSImm6NonZero; 2592 break; 2593 } 2594 // 'UImm7Lsb00' class 2595 case MCK_UImm7Lsb00: { 2596 DiagnosticPredicate DP(Operand.isUImm7Lsb00()); 2597 if (DP.isMatch()) 2598 return MCTargetAsmParser::Match_Success; 2599 if (DP.isNearMatch()) 2600 return RISCVAsmParser::Match_InvalidUImm7Lsb00; 2601 break; 2602 } 2603 // 'UImm8Lsb00' class 2604 case MCK_UImm8Lsb00: { 2605 DiagnosticPredicate DP(Operand.isUImm8Lsb00()); 2606 if (DP.isMatch()) 2607 return MCTargetAsmParser::Match_Success; 2608 if (DP.isNearMatch()) 2609 return RISCVAsmParser::Match_InvalidUImm8Lsb00; 2610 break; 2611 } 2612 // 'UImm8Lsb000' class 2613 case MCK_UImm8Lsb000: { 2614 DiagnosticPredicate DP(Operand.isUImm8Lsb000()); 2615 if (DP.isMatch()) 2616 return MCTargetAsmParser::Match_Success; 2617 if (DP.isNearMatch()) 2618 return RISCVAsmParser::Match_InvalidUImm8Lsb000; 2619 break; 2620 } 2621 // 'SImm9Lsb0' class 2622 case MCK_SImm9Lsb0: { 2623 DiagnosticPredicate DP(Operand.isSImm9Lsb0()); 2624 if (DP.isMatch()) 2625 return MCTargetAsmParser::Match_Success; 2626 if (DP.isNearMatch()) 2627 return RISCVAsmParser::Match_InvalidSImm9Lsb0; 2628 break; 2629 } 2630 // 'UImm9Lsb000' class 2631 case MCK_UImm9Lsb000: { 2632 DiagnosticPredicate DP(Operand.isUImm9Lsb000()); 2633 if (DP.isMatch()) 2634 return MCTargetAsmParser::Match_Success; 2635 if (DP.isNearMatch()) 2636 return RISCVAsmParser::Match_InvalidUImm9Lsb000; 2637 break; 2638 } 2639 // 'UImm10Lsb00NonZero' class 2640 case MCK_UImm10Lsb00NonZero: { 2641 DiagnosticPredicate DP(Operand.isUImm10Lsb00NonZero()); 2642 if (DP.isMatch()) 2643 return MCTargetAsmParser::Match_Success; 2644 if (DP.isNearMatch()) 2645 return RISCVAsmParser::Match_InvalidUImm10Lsb00NonZero; 2646 break; 2647 } 2648 // 'SImm10Lsb0000NonZero' class 2649 case MCK_SImm10Lsb0000NonZero: { 2650 DiagnosticPredicate DP(Operand.isSImm10Lsb0000NonZero()); 2651 if (DP.isMatch()) 2652 return MCTargetAsmParser::Match_Success; 2653 if (DP.isNearMatch()) 2654 return RISCVAsmParser::Match_InvalidSImm10Lsb0000NonZero; 2655 break; 2656 } 2657 // 'SImm12Lsb0' class 2658 case MCK_SImm12Lsb0: { 2659 DiagnosticPredicate DP(Operand.isSImm12Lsb0()); 2660 if (DP.isMatch()) 2661 return MCTargetAsmParser::Match_Success; 2662 if (DP.isNearMatch()) 2663 return RISCVAsmParser::Match_InvalidSImm12Lsb0; 2664 break; 2665 } 2666 // 'VTypeI10' class 2667 case MCK_VTypeI10: { 2668 DiagnosticPredicate DP(Operand.isVTypeI10()); 2669 if (DP.isMatch()) 2670 return MCTargetAsmParser::Match_Success; 2671 if (DP.isNearMatch()) 2672 return RISCVAsmParser::Match_InvalidVTypeI; 2673 break; 2674 } 2675 // 'VTypeI11' class 2676 case MCK_VTypeI11: { 2677 DiagnosticPredicate DP(Operand.isVTypeI11()); 2678 if (DP.isMatch()) 2679 return MCTargetAsmParser::Match_Success; 2680 if (DP.isNearMatch()) 2681 return RISCVAsmParser::Match_InvalidVTypeI; 2682 break; 2683 } 2684 // 'SImm5' class 2685 case MCK_SImm5: { 2686 DiagnosticPredicate DP(Operand.isSImm5()); 2687 if (DP.isMatch()) 2688 return MCTargetAsmParser::Match_Success; 2689 if (DP.isNearMatch()) 2690 return RISCVAsmParser::Match_InvalidSImm5; 2691 break; 2692 } 2693 } // end switch (Kind) 2694 2695 if (Operand.isReg()) { 2696 MatchClassKind OpKind; 2697 switch (Operand.getReg()) { 2698 default: OpKind = InvalidMatchClass; break; 2699 case RISCV::X0: OpKind = MCK_GPRX0; break; 2700 case RISCV::X1: OpKind = MCK_GPRNoX0X2; break; 2701 case RISCV::X2: OpKind = MCK_SP; break; 2702 case RISCV::X3: OpKind = MCK_GPRNoX0X2; break; 2703 case RISCV::X4: OpKind = MCK_GPRNoX0X2; break; 2704 case RISCV::X5: OpKind = MCK_GPRNoX0X2; break; 2705 case RISCV::X6: OpKind = MCK_GPRTC; break; 2706 case RISCV::X7: OpKind = MCK_GPRTC; break; 2707 case RISCV::X8: OpKind = MCK_GPRC; break; 2708 case RISCV::X9: OpKind = MCK_GPRC; break; 2709 case RISCV::X10: OpKind = MCK_Reg9; break; 2710 case RISCV::X11: OpKind = MCK_Reg9; break; 2711 case RISCV::X12: OpKind = MCK_Reg9; break; 2712 case RISCV::X13: OpKind = MCK_Reg9; break; 2713 case RISCV::X14: OpKind = MCK_Reg9; break; 2714 case RISCV::X15: OpKind = MCK_Reg9; break; 2715 case RISCV::X16: OpKind = MCK_GPRTC; break; 2716 case RISCV::X17: OpKind = MCK_GPRTC; break; 2717 case RISCV::X18: OpKind = MCK_GPRJALR; break; 2718 case RISCV::X19: OpKind = MCK_GPRJALR; break; 2719 case RISCV::X20: OpKind = MCK_GPRJALR; break; 2720 case RISCV::X21: OpKind = MCK_GPRJALR; break; 2721 case RISCV::X22: OpKind = MCK_GPRJALR; break; 2722 case RISCV::X23: OpKind = MCK_GPRJALR; break; 2723 case RISCV::X24: OpKind = MCK_GPRJALR; break; 2724 case RISCV::X25: OpKind = MCK_GPRJALR; break; 2725 case RISCV::X26: OpKind = MCK_GPRJALR; break; 2726 case RISCV::X27: OpKind = MCK_GPRJALR; break; 2727 case RISCV::X28: OpKind = MCK_GPRTC; break; 2728 case RISCV::X29: OpKind = MCK_GPRTC; break; 2729 case RISCV::X30: OpKind = MCK_GPRTC; break; 2730 case RISCV::X31: OpKind = MCK_GPRTC; break; 2731 case RISCV::F0_H: OpKind = MCK_FPR16; break; 2732 case RISCV::F1_H: OpKind = MCK_FPR16; break; 2733 case RISCV::F2_H: OpKind = MCK_FPR16; break; 2734 case RISCV::F3_H: OpKind = MCK_FPR16; break; 2735 case RISCV::F4_H: OpKind = MCK_FPR16; break; 2736 case RISCV::F5_H: OpKind = MCK_FPR16; break; 2737 case RISCV::F6_H: OpKind = MCK_FPR16; break; 2738 case RISCV::F7_H: OpKind = MCK_FPR16; break; 2739 case RISCV::F8_H: OpKind = MCK_FPR16; break; 2740 case RISCV::F9_H: OpKind = MCK_FPR16; break; 2741 case RISCV::F10_H: OpKind = MCK_FPR16; break; 2742 case RISCV::F11_H: OpKind = MCK_FPR16; break; 2743 case RISCV::F12_H: OpKind = MCK_FPR16; break; 2744 case RISCV::F13_H: OpKind = MCK_FPR16; break; 2745 case RISCV::F14_H: OpKind = MCK_FPR16; break; 2746 case RISCV::F15_H: OpKind = MCK_FPR16; break; 2747 case RISCV::F16_H: OpKind = MCK_FPR16; break; 2748 case RISCV::F17_H: OpKind = MCK_FPR16; break; 2749 case RISCV::F18_H: OpKind = MCK_FPR16; break; 2750 case RISCV::F19_H: OpKind = MCK_FPR16; break; 2751 case RISCV::F20_H: OpKind = MCK_FPR16; break; 2752 case RISCV::F21_H: OpKind = MCK_FPR16; break; 2753 case RISCV::F22_H: OpKind = MCK_FPR16; break; 2754 case RISCV::F23_H: OpKind = MCK_FPR16; break; 2755 case RISCV::F24_H: OpKind = MCK_FPR16; break; 2756 case RISCV::F25_H: OpKind = MCK_FPR16; break; 2757 case RISCV::F26_H: OpKind = MCK_FPR16; break; 2758 case RISCV::F27_H: OpKind = MCK_FPR16; break; 2759 case RISCV::F28_H: OpKind = MCK_FPR16; break; 2760 case RISCV::F29_H: OpKind = MCK_FPR16; break; 2761 case RISCV::F30_H: OpKind = MCK_FPR16; break; 2762 case RISCV::F31_H: OpKind = MCK_FPR16; break; 2763 case RISCV::F0_F: OpKind = MCK_FPR32; break; 2764 case RISCV::F1_F: OpKind = MCK_FPR32; break; 2765 case RISCV::F2_F: OpKind = MCK_FPR32; break; 2766 case RISCV::F3_F: OpKind = MCK_FPR32; break; 2767 case RISCV::F4_F: OpKind = MCK_FPR32; break; 2768 case RISCV::F5_F: OpKind = MCK_FPR32; break; 2769 case RISCV::F6_F: OpKind = MCK_FPR32; break; 2770 case RISCV::F7_F: OpKind = MCK_FPR32; break; 2771 case RISCV::F8_F: OpKind = MCK_FPR32C; break; 2772 case RISCV::F9_F: OpKind = MCK_FPR32C; break; 2773 case RISCV::F10_F: OpKind = MCK_FPR32C; break; 2774 case RISCV::F11_F: OpKind = MCK_FPR32C; break; 2775 case RISCV::F12_F: OpKind = MCK_FPR32C; break; 2776 case RISCV::F13_F: OpKind = MCK_FPR32C; break; 2777 case RISCV::F14_F: OpKind = MCK_FPR32C; break; 2778 case RISCV::F15_F: OpKind = MCK_FPR32C; break; 2779 case RISCV::F16_F: OpKind = MCK_FPR32; break; 2780 case RISCV::F17_F: OpKind = MCK_FPR32; break; 2781 case RISCV::F18_F: OpKind = MCK_FPR32; break; 2782 case RISCV::F19_F: OpKind = MCK_FPR32; break; 2783 case RISCV::F20_F: OpKind = MCK_FPR32; break; 2784 case RISCV::F21_F: OpKind = MCK_FPR32; break; 2785 case RISCV::F22_F: OpKind = MCK_FPR32; break; 2786 case RISCV::F23_F: OpKind = MCK_FPR32; break; 2787 case RISCV::F24_F: OpKind = MCK_FPR32; break; 2788 case RISCV::F25_F: OpKind = MCK_FPR32; break; 2789 case RISCV::F26_F: OpKind = MCK_FPR32; break; 2790 case RISCV::F27_F: OpKind = MCK_FPR32; break; 2791 case RISCV::F28_F: OpKind = MCK_FPR32; break; 2792 case RISCV::F29_F: OpKind = MCK_FPR32; break; 2793 case RISCV::F30_F: OpKind = MCK_FPR32; break; 2794 case RISCV::F31_F: OpKind = MCK_FPR32; break; 2795 case RISCV::F0_D: OpKind = MCK_FPR64; break; 2796 case RISCV::F1_D: OpKind = MCK_FPR64; break; 2797 case RISCV::F2_D: OpKind = MCK_FPR64; break; 2798 case RISCV::F3_D: OpKind = MCK_FPR64; break; 2799 case RISCV::F4_D: OpKind = MCK_FPR64; break; 2800 case RISCV::F5_D: OpKind = MCK_FPR64; break; 2801 case RISCV::F6_D: OpKind = MCK_FPR64; break; 2802 case RISCV::F7_D: OpKind = MCK_FPR64; break; 2803 case RISCV::F8_D: OpKind = MCK_FPR64C; break; 2804 case RISCV::F9_D: OpKind = MCK_FPR64C; break; 2805 case RISCV::F10_D: OpKind = MCK_FPR64C; break; 2806 case RISCV::F11_D: OpKind = MCK_FPR64C; break; 2807 case RISCV::F12_D: OpKind = MCK_FPR64C; break; 2808 case RISCV::F13_D: OpKind = MCK_FPR64C; break; 2809 case RISCV::F14_D: OpKind = MCK_FPR64C; break; 2810 case RISCV::F15_D: OpKind = MCK_FPR64C; break; 2811 case RISCV::F16_D: OpKind = MCK_FPR64; break; 2812 case RISCV::F17_D: OpKind = MCK_FPR64; break; 2813 case RISCV::F18_D: OpKind = MCK_FPR64; break; 2814 case RISCV::F19_D: OpKind = MCK_FPR64; break; 2815 case RISCV::F20_D: OpKind = MCK_FPR64; break; 2816 case RISCV::F21_D: OpKind = MCK_FPR64; break; 2817 case RISCV::F22_D: OpKind = MCK_FPR64; break; 2818 case RISCV::F23_D: OpKind = MCK_FPR64; break; 2819 case RISCV::F24_D: OpKind = MCK_FPR64; break; 2820 case RISCV::F25_D: OpKind = MCK_FPR64; break; 2821 case RISCV::F26_D: OpKind = MCK_FPR64; break; 2822 case RISCV::F27_D: OpKind = MCK_FPR64; break; 2823 case RISCV::F28_D: OpKind = MCK_FPR64; break; 2824 case RISCV::F29_D: OpKind = MCK_FPR64; break; 2825 case RISCV::F30_D: OpKind = MCK_FPR64; break; 2826 case RISCV::F31_D: OpKind = MCK_FPR64; break; 2827 case RISCV::V0: OpKind = MCK_VMV0; break; 2828 case RISCV::V1: OpKind = MCK_VRNoV0; break; 2829 case RISCV::V2: OpKind = MCK_VRNoV0; break; 2830 case RISCV::V3: OpKind = MCK_VRNoV0; break; 2831 case RISCV::V4: OpKind = MCK_VRNoV0; break; 2832 case RISCV::V5: OpKind = MCK_VRNoV0; break; 2833 case RISCV::V6: OpKind = MCK_VRNoV0; break; 2834 case RISCV::V7: OpKind = MCK_VRNoV0; break; 2835 case RISCV::V8: OpKind = MCK_VRNoV0; break; 2836 case RISCV::V9: OpKind = MCK_VRNoV0; break; 2837 case RISCV::V10: OpKind = MCK_VRNoV0; break; 2838 case RISCV::V11: OpKind = MCK_VRNoV0; break; 2839 case RISCV::V12: OpKind = MCK_VRNoV0; break; 2840 case RISCV::V13: OpKind = MCK_VRNoV0; break; 2841 case RISCV::V14: OpKind = MCK_VRNoV0; break; 2842 case RISCV::V15: OpKind = MCK_VRNoV0; break; 2843 case RISCV::V16: OpKind = MCK_VRNoV0; break; 2844 case RISCV::V17: OpKind = MCK_VRNoV0; break; 2845 case RISCV::V18: OpKind = MCK_VRNoV0; break; 2846 case RISCV::V19: OpKind = MCK_VRNoV0; break; 2847 case RISCV::V20: OpKind = MCK_VRNoV0; break; 2848 case RISCV::V21: OpKind = MCK_VRNoV0; break; 2849 case RISCV::V22: OpKind = MCK_VRNoV0; break; 2850 case RISCV::V23: OpKind = MCK_VRNoV0; break; 2851 case RISCV::V24: OpKind = MCK_VRNoV0; break; 2852 case RISCV::V25: OpKind = MCK_VRNoV0; break; 2853 case RISCV::V26: OpKind = MCK_VRNoV0; break; 2854 case RISCV::V27: OpKind = MCK_VRNoV0; break; 2855 case RISCV::V28: OpKind = MCK_VRNoV0; break; 2856 case RISCV::V29: OpKind = MCK_VRNoV0; break; 2857 case RISCV::V30: OpKind = MCK_VRNoV0; break; 2858 case RISCV::V31: OpKind = MCK_VRNoV0; break; 2859 case RISCV::V0M2: OpKind = MCK_Reg18; break; 2860 case RISCV::V2M2: OpKind = MCK_VRM2NoV0; break; 2861 case RISCV::V4M2: OpKind = MCK_VRM2NoV0; break; 2862 case RISCV::V6M2: OpKind = MCK_VRM2NoV0; break; 2863 case RISCV::V8M2: OpKind = MCK_VRM2NoV0; break; 2864 case RISCV::V10M2: OpKind = MCK_VRM2NoV0; break; 2865 case RISCV::V12M2: OpKind = MCK_VRM2NoV0; break; 2866 case RISCV::V14M2: OpKind = MCK_VRM2NoV0; break; 2867 case RISCV::V16M2: OpKind = MCK_VRM2NoV0; break; 2868 case RISCV::V18M2: OpKind = MCK_VRM2NoV0; break; 2869 case RISCV::V20M2: OpKind = MCK_VRM2NoV0; break; 2870 case RISCV::V22M2: OpKind = MCK_VRM2NoV0; break; 2871 case RISCV::V24M2: OpKind = MCK_VRM2NoV0; break; 2872 case RISCV::V26M2: OpKind = MCK_VRM2NoV0; break; 2873 case RISCV::V28M2: OpKind = MCK_VRM2NoV0; break; 2874 case RISCV::V30M2: OpKind = MCK_VRM2NoV0; break; 2875 case RISCV::V0M4: OpKind = MCK_Reg21; break; 2876 case RISCV::V4M4: OpKind = MCK_VRM4NoV0; break; 2877 case RISCV::V8M4: OpKind = MCK_VRM4NoV0; break; 2878 case RISCV::V12M4: OpKind = MCK_VRM4NoV0; break; 2879 case RISCV::V16M4: OpKind = MCK_VRM4NoV0; break; 2880 case RISCV::V20M4: OpKind = MCK_VRM4NoV0; break; 2881 case RISCV::V24M4: OpKind = MCK_VRM4NoV0; break; 2882 case RISCV::V28M4: OpKind = MCK_VRM4NoV0; break; 2883 case RISCV::V0M8: OpKind = MCK_Reg24; break; 2884 case RISCV::V8M8: OpKind = MCK_VRM8NoV0; break; 2885 case RISCV::V16M8: OpKind = MCK_VRM8NoV0; break; 2886 case RISCV::V24M8: OpKind = MCK_VRM8NoV0; break; 2887 case RISCV::VTYPE: OpKind = MCK_VCSR; break; 2888 case RISCV::VL: OpKind = MCK_VCSR; break; 2889 case RISCV::VLENB: OpKind = MCK_VCSR; break; 2890 case RISCV::X0_PD: OpKind = MCK_Reg28; break; 2891 case RISCV::X2_PD: OpKind = MCK_Reg30; break; 2892 case RISCV::X4_PD: OpKind = MCK_Reg32; break; 2893 case RISCV::X6_PD: OpKind = MCK_Reg34; break; 2894 case RISCV::X8_PD: OpKind = MCK_Reg35; break; 2895 case RISCV::X10_PD: OpKind = MCK_Reg36; break; 2896 case RISCV::X12_PD: OpKind = MCK_Reg36; break; 2897 case RISCV::X14_PD: OpKind = MCK_Reg36; break; 2898 case RISCV::X16_PD: OpKind = MCK_Reg34; break; 2899 case RISCV::X18_PD: OpKind = MCK_Reg33; break; 2900 case RISCV::X20_PD: OpKind = MCK_Reg33; break; 2901 case RISCV::X22_PD: OpKind = MCK_Reg33; break; 2902 case RISCV::X24_PD: OpKind = MCK_Reg33; break; 2903 case RISCV::X26_PD: OpKind = MCK_Reg33; break; 2904 case RISCV::X28_PD: OpKind = MCK_Reg34; break; 2905 case RISCV::X30_PD: OpKind = MCK_Reg34; break; 2906 case RISCV::V8_V9: OpKind = MCK_VRN2M1NoV0; break; 2907 case RISCV::V9_V10: OpKind = MCK_VRN2M1NoV0; break; 2908 case RISCV::V10_V11: OpKind = MCK_VRN2M1NoV0; break; 2909 case RISCV::V11_V12: OpKind = MCK_VRN2M1NoV0; break; 2910 case RISCV::V12_V13: OpKind = MCK_VRN2M1NoV0; break; 2911 case RISCV::V13_V14: OpKind = MCK_VRN2M1NoV0; break; 2912 case RISCV::V14_V15: OpKind = MCK_VRN2M1NoV0; break; 2913 case RISCV::V15_V16: OpKind = MCK_VRN2M1NoV0; break; 2914 case RISCV::V16_V17: OpKind = MCK_VRN2M1NoV0; break; 2915 case RISCV::V17_V18: OpKind = MCK_VRN2M1NoV0; break; 2916 case RISCV::V18_V19: OpKind = MCK_VRN2M1NoV0; break; 2917 case RISCV::V19_V20: OpKind = MCK_VRN2M1NoV0; break; 2918 case RISCV::V20_V21: OpKind = MCK_VRN2M1NoV0; break; 2919 case RISCV::V21_V22: OpKind = MCK_VRN2M1NoV0; break; 2920 case RISCV::V22_V23: OpKind = MCK_VRN2M1NoV0; break; 2921 case RISCV::V23_V24: OpKind = MCK_VRN2M1NoV0; break; 2922 case RISCV::V24_V25: OpKind = MCK_VRN2M1NoV0; break; 2923 case RISCV::V25_V26: OpKind = MCK_VRN2M1NoV0; break; 2924 case RISCV::V26_V27: OpKind = MCK_VRN2M1NoV0; break; 2925 case RISCV::V27_V28: OpKind = MCK_VRN2M1NoV0; break; 2926 case RISCV::V28_V29: OpKind = MCK_VRN2M1NoV0; break; 2927 case RISCV::V29_V30: OpKind = MCK_VRN2M1NoV0; break; 2928 case RISCV::V30_V31: OpKind = MCK_VRN2M1NoV0; break; 2929 case RISCV::V1_V2: OpKind = MCK_VRN2M1NoV0; break; 2930 case RISCV::V2_V3: OpKind = MCK_VRN2M1NoV0; break; 2931 case RISCV::V3_V4: OpKind = MCK_VRN2M1NoV0; break; 2932 case RISCV::V4_V5: OpKind = MCK_VRN2M1NoV0; break; 2933 case RISCV::V5_V6: OpKind = MCK_VRN2M1NoV0; break; 2934 case RISCV::V6_V7: OpKind = MCK_VRN2M1NoV0; break; 2935 case RISCV::V7_V8: OpKind = MCK_VRN2M1NoV0; break; 2936 case RISCV::V0_V1: OpKind = MCK_Reg39; break; 2937 case RISCV::V8M2_V10M2: OpKind = MCK_VRN2M2NoV0; break; 2938 case RISCV::V10M2_V12M2: OpKind = MCK_VRN2M2NoV0; break; 2939 case RISCV::V12M2_V14M2: OpKind = MCK_VRN2M2NoV0; break; 2940 case RISCV::V14M2_V16M2: OpKind = MCK_VRN2M2NoV0; break; 2941 case RISCV::V16M2_V18M2: OpKind = MCK_VRN2M2NoV0; break; 2942 case RISCV::V18M2_V20M2: OpKind = MCK_VRN2M2NoV0; break; 2943 case RISCV::V20M2_V22M2: OpKind = MCK_VRN2M2NoV0; break; 2944 case RISCV::V22M2_V24M2: OpKind = MCK_VRN2M2NoV0; break; 2945 case RISCV::V24M2_V26M2: OpKind = MCK_VRN2M2NoV0; break; 2946 case RISCV::V26M2_V28M2: OpKind = MCK_VRN2M2NoV0; break; 2947 case RISCV::V28M2_V30M2: OpKind = MCK_VRN2M2NoV0; break; 2948 case RISCV::V2M2_V4M2: OpKind = MCK_VRN2M2NoV0; break; 2949 case RISCV::V4M2_V6M2: OpKind = MCK_VRN2M2NoV0; break; 2950 case RISCV::V6M2_V8M2: OpKind = MCK_VRN2M2NoV0; break; 2951 case RISCV::V0M2_V2M2: OpKind = MCK_Reg42; break; 2952 case RISCV::V8M4_V12M4: OpKind = MCK_VRN2M4NoV0; break; 2953 case RISCV::V12M4_V16M4: OpKind = MCK_VRN2M4NoV0; break; 2954 case RISCV::V16M4_V20M4: OpKind = MCK_VRN2M4NoV0; break; 2955 case RISCV::V20M4_V24M4: OpKind = MCK_VRN2M4NoV0; break; 2956 case RISCV::V24M4_V28M4: OpKind = MCK_VRN2M4NoV0; break; 2957 case RISCV::V4M4_V8M4: OpKind = MCK_VRN2M4NoV0; break; 2958 case RISCV::V0M4_V4M4: OpKind = MCK_Reg45; break; 2959 case RISCV::V8_V9_V10: OpKind = MCK_VRN3M1NoV0; break; 2960 case RISCV::V9_V10_V11: OpKind = MCK_VRN3M1NoV0; break; 2961 case RISCV::V10_V11_V12: OpKind = MCK_VRN3M1NoV0; break; 2962 case RISCV::V11_V12_V13: OpKind = MCK_VRN3M1NoV0; break; 2963 case RISCV::V12_V13_V14: OpKind = MCK_VRN3M1NoV0; break; 2964 case RISCV::V13_V14_V15: OpKind = MCK_VRN3M1NoV0; break; 2965 case RISCV::V14_V15_V16: OpKind = MCK_VRN3M1NoV0; break; 2966 case RISCV::V15_V16_V17: OpKind = MCK_VRN3M1NoV0; break; 2967 case RISCV::V16_V17_V18: OpKind = MCK_VRN3M1NoV0; break; 2968 case RISCV::V17_V18_V19: OpKind = MCK_VRN3M1NoV0; break; 2969 case RISCV::V18_V19_V20: OpKind = MCK_VRN3M1NoV0; break; 2970 case RISCV::V19_V20_V21: OpKind = MCK_VRN3M1NoV0; break; 2971 case RISCV::V20_V21_V22: OpKind = MCK_VRN3M1NoV0; break; 2972 case RISCV::V21_V22_V23: OpKind = MCK_VRN3M1NoV0; break; 2973 case RISCV::V22_V23_V24: OpKind = MCK_VRN3M1NoV0; break; 2974 case RISCV::V23_V24_V25: OpKind = MCK_VRN3M1NoV0; break; 2975 case RISCV::V24_V25_V26: OpKind = MCK_VRN3M1NoV0; break; 2976 case RISCV::V25_V26_V27: OpKind = MCK_VRN3M1NoV0; break; 2977 case RISCV::V26_V27_V28: OpKind = MCK_VRN3M1NoV0; break; 2978 case RISCV::V27_V28_V29: OpKind = MCK_VRN3M1NoV0; break; 2979 case RISCV::V28_V29_V30: OpKind = MCK_VRN3M1NoV0; break; 2980 case RISCV::V29_V30_V31: OpKind = MCK_VRN3M1NoV0; break; 2981 case RISCV::V1_V2_V3: OpKind = MCK_VRN3M1NoV0; break; 2982 case RISCV::V2_V3_V4: OpKind = MCK_VRN3M1NoV0; break; 2983 case RISCV::V3_V4_V5: OpKind = MCK_VRN3M1NoV0; break; 2984 case RISCV::V4_V5_V6: OpKind = MCK_VRN3M1NoV0; break; 2985 case RISCV::V5_V6_V7: OpKind = MCK_VRN3M1NoV0; break; 2986 case RISCV::V6_V7_V8: OpKind = MCK_VRN3M1NoV0; break; 2987 case RISCV::V7_V8_V9: OpKind = MCK_VRN3M1NoV0; break; 2988 case RISCV::V0_V1_V2: OpKind = MCK_Reg48; break; 2989 case RISCV::V8M2_V10M2_V12M2: OpKind = MCK_VRN3M2NoV0; break; 2990 case RISCV::V10M2_V12M2_V14M2: OpKind = MCK_VRN3M2NoV0; break; 2991 case RISCV::V12M2_V14M2_V16M2: OpKind = MCK_VRN3M2NoV0; break; 2992 case RISCV::V14M2_V16M2_V18M2: OpKind = MCK_VRN3M2NoV0; break; 2993 case RISCV::V16M2_V18M2_V20M2: OpKind = MCK_VRN3M2NoV0; break; 2994 case RISCV::V18M2_V20M2_V22M2: OpKind = MCK_VRN3M2NoV0; break; 2995 case RISCV::V20M2_V22M2_V24M2: OpKind = MCK_VRN3M2NoV0; break; 2996 case RISCV::V22M2_V24M2_V26M2: OpKind = MCK_VRN3M2NoV0; break; 2997 case RISCV::V24M2_V26M2_V28M2: OpKind = MCK_VRN3M2NoV0; break; 2998 case RISCV::V26M2_V28M2_V30M2: OpKind = MCK_VRN3M2NoV0; break; 2999 case RISCV::V2M2_V4M2_V6M2: OpKind = MCK_VRN3M2NoV0; break; 3000 case RISCV::V4M2_V6M2_V8M2: OpKind = MCK_VRN3M2NoV0; break; 3001 case RISCV::V6M2_V8M2_V10M2: OpKind = MCK_VRN3M2NoV0; break; 3002 case RISCV::V0M2_V2M2_V4M2: OpKind = MCK_Reg51; break; 3003 case RISCV::V8_V9_V10_V11: OpKind = MCK_VRN4M1NoV0; break; 3004 case RISCV::V9_V10_V11_V12: OpKind = MCK_VRN4M1NoV0; break; 3005 case RISCV::V10_V11_V12_V13: OpKind = MCK_VRN4M1NoV0; break; 3006 case RISCV::V11_V12_V13_V14: OpKind = MCK_VRN4M1NoV0; break; 3007 case RISCV::V12_V13_V14_V15: OpKind = MCK_VRN4M1NoV0; break; 3008 case RISCV::V13_V14_V15_V16: OpKind = MCK_VRN4M1NoV0; break; 3009 case RISCV::V14_V15_V16_V17: OpKind = MCK_VRN4M1NoV0; break; 3010 case RISCV::V15_V16_V17_V18: OpKind = MCK_VRN4M1NoV0; break; 3011 case RISCV::V16_V17_V18_V19: OpKind = MCK_VRN4M1NoV0; break; 3012 case RISCV::V17_V18_V19_V20: OpKind = MCK_VRN4M1NoV0; break; 3013 case RISCV::V18_V19_V20_V21: OpKind = MCK_VRN4M1NoV0; break; 3014 case RISCV::V19_V20_V21_V22: OpKind = MCK_VRN4M1NoV0; break; 3015 case RISCV::V20_V21_V22_V23: OpKind = MCK_VRN4M1NoV0; break; 3016 case RISCV::V21_V22_V23_V24: OpKind = MCK_VRN4M1NoV0; break; 3017 case RISCV::V22_V23_V24_V25: OpKind = MCK_VRN4M1NoV0; break; 3018 case RISCV::V23_V24_V25_V26: OpKind = MCK_VRN4M1NoV0; break; 3019 case RISCV::V24_V25_V26_V27: OpKind = MCK_VRN4M1NoV0; break; 3020 case RISCV::V25_V26_V27_V28: OpKind = MCK_VRN4M1NoV0; break; 3021 case RISCV::V26_V27_V28_V29: OpKind = MCK_VRN4M1NoV0; break; 3022 case RISCV::V27_V28_V29_V30: OpKind = MCK_VRN4M1NoV0; break; 3023 case RISCV::V28_V29_V30_V31: OpKind = MCK_VRN4M1NoV0; break; 3024 case RISCV::V1_V2_V3_V4: OpKind = MCK_VRN4M1NoV0; break; 3025 case RISCV::V2_V3_V4_V5: OpKind = MCK_VRN4M1NoV0; break; 3026 case RISCV::V3_V4_V5_V6: OpKind = MCK_VRN4M1NoV0; break; 3027 case RISCV::V4_V5_V6_V7: OpKind = MCK_VRN4M1NoV0; break; 3028 case RISCV::V5_V6_V7_V8: OpKind = MCK_VRN4M1NoV0; break; 3029 case RISCV::V6_V7_V8_V9: OpKind = MCK_VRN4M1NoV0; break; 3030 case RISCV::V7_V8_V9_V10: OpKind = MCK_VRN4M1NoV0; break; 3031 case RISCV::V0_V1_V2_V3: OpKind = MCK_Reg54; break; 3032 case RISCV::V8M2_V10M2_V12M2_V14M2: OpKind = MCK_VRN4M2NoV0; break; 3033 case RISCV::V10M2_V12M2_V14M2_V16M2: OpKind = MCK_VRN4M2NoV0; break; 3034 case RISCV::V12M2_V14M2_V16M2_V18M2: OpKind = MCK_VRN4M2NoV0; break; 3035 case RISCV::V14M2_V16M2_V18M2_V20M2: OpKind = MCK_VRN4M2NoV0; break; 3036 case RISCV::V16M2_V18M2_V20M2_V22M2: OpKind = MCK_VRN4M2NoV0; break; 3037 case RISCV::V18M2_V20M2_V22M2_V24M2: OpKind = MCK_VRN4M2NoV0; break; 3038 case RISCV::V20M2_V22M2_V24M2_V26M2: OpKind = MCK_VRN4M2NoV0; break; 3039 case RISCV::V22M2_V24M2_V26M2_V28M2: OpKind = MCK_VRN4M2NoV0; break; 3040 case RISCV::V24M2_V26M2_V28M2_V30M2: OpKind = MCK_VRN4M2NoV0; break; 3041 case RISCV::V2M2_V4M2_V6M2_V8M2: OpKind = MCK_VRN4M2NoV0; break; 3042 case RISCV::V4M2_V6M2_V8M2_V10M2: OpKind = MCK_VRN4M2NoV0; break; 3043 case RISCV::V6M2_V8M2_V10M2_V12M2: OpKind = MCK_VRN4M2NoV0; break; 3044 case RISCV::V0M2_V2M2_V4M2_V6M2: OpKind = MCK_Reg57; break; 3045 case RISCV::V8_V9_V10_V11_V12: OpKind = MCK_VRN5M1NoV0; break; 3046 case RISCV::V9_V10_V11_V12_V13: OpKind = MCK_VRN5M1NoV0; break; 3047 case RISCV::V10_V11_V12_V13_V14: OpKind = MCK_VRN5M1NoV0; break; 3048 case RISCV::V11_V12_V13_V14_V15: OpKind = MCK_VRN5M1NoV0; break; 3049 case RISCV::V12_V13_V14_V15_V16: OpKind = MCK_VRN5M1NoV0; break; 3050 case RISCV::V13_V14_V15_V16_V17: OpKind = MCK_VRN5M1NoV0; break; 3051 case RISCV::V14_V15_V16_V17_V18: OpKind = MCK_VRN5M1NoV0; break; 3052 case RISCV::V15_V16_V17_V18_V19: OpKind = MCK_VRN5M1NoV0; break; 3053 case RISCV::V16_V17_V18_V19_V20: OpKind = MCK_VRN5M1NoV0; break; 3054 case RISCV::V17_V18_V19_V20_V21: OpKind = MCK_VRN5M1NoV0; break; 3055 case RISCV::V18_V19_V20_V21_V22: OpKind = MCK_VRN5M1NoV0; break; 3056 case RISCV::V19_V20_V21_V22_V23: OpKind = MCK_VRN5M1NoV0; break; 3057 case RISCV::V20_V21_V22_V23_V24: OpKind = MCK_VRN5M1NoV0; break; 3058 case RISCV::V21_V22_V23_V24_V25: OpKind = MCK_VRN5M1NoV0; break; 3059 case RISCV::V22_V23_V24_V25_V26: OpKind = MCK_VRN5M1NoV0; break; 3060 case RISCV::V23_V24_V25_V26_V27: OpKind = MCK_VRN5M1NoV0; break; 3061 case RISCV::V24_V25_V26_V27_V28: OpKind = MCK_VRN5M1NoV0; break; 3062 case RISCV::V25_V26_V27_V28_V29: OpKind = MCK_VRN5M1NoV0; break; 3063 case RISCV::V26_V27_V28_V29_V30: OpKind = MCK_VRN5M1NoV0; break; 3064 case RISCV::V27_V28_V29_V30_V31: OpKind = MCK_VRN5M1NoV0; break; 3065 case RISCV::V1_V2_V3_V4_V5: OpKind = MCK_VRN5M1NoV0; break; 3066 case RISCV::V2_V3_V4_V5_V6: OpKind = MCK_VRN5M1NoV0; break; 3067 case RISCV::V3_V4_V5_V6_V7: OpKind = MCK_VRN5M1NoV0; break; 3068 case RISCV::V4_V5_V6_V7_V8: OpKind = MCK_VRN5M1NoV0; break; 3069 case RISCV::V5_V6_V7_V8_V9: OpKind = MCK_VRN5M1NoV0; break; 3070 case RISCV::V6_V7_V8_V9_V10: OpKind = MCK_VRN5M1NoV0; break; 3071 case RISCV::V7_V8_V9_V10_V11: OpKind = MCK_VRN5M1NoV0; break; 3072 case RISCV::V0_V1_V2_V3_V4: OpKind = MCK_Reg60; break; 3073 case RISCV::V8_V9_V10_V11_V12_V13: OpKind = MCK_VRN6M1NoV0; break; 3074 case RISCV::V9_V10_V11_V12_V13_V14: OpKind = MCK_VRN6M1NoV0; break; 3075 case RISCV::V10_V11_V12_V13_V14_V15: OpKind = MCK_VRN6M1NoV0; break; 3076 case RISCV::V11_V12_V13_V14_V15_V16: OpKind = MCK_VRN6M1NoV0; break; 3077 case RISCV::V12_V13_V14_V15_V16_V17: OpKind = MCK_VRN6M1NoV0; break; 3078 case RISCV::V13_V14_V15_V16_V17_V18: OpKind = MCK_VRN6M1NoV0; break; 3079 case RISCV::V14_V15_V16_V17_V18_V19: OpKind = MCK_VRN6M1NoV0; break; 3080 case RISCV::V15_V16_V17_V18_V19_V20: OpKind = MCK_VRN6M1NoV0; break; 3081 case RISCV::V16_V17_V18_V19_V20_V21: OpKind = MCK_VRN6M1NoV0; break; 3082 case RISCV::V17_V18_V19_V20_V21_V22: OpKind = MCK_VRN6M1NoV0; break; 3083 case RISCV::V18_V19_V20_V21_V22_V23: OpKind = MCK_VRN6M1NoV0; break; 3084 case RISCV::V19_V20_V21_V22_V23_V24: OpKind = MCK_VRN6M1NoV0; break; 3085 case RISCV::V20_V21_V22_V23_V24_V25: OpKind = MCK_VRN6M1NoV0; break; 3086 case RISCV::V21_V22_V23_V24_V25_V26: OpKind = MCK_VRN6M1NoV0; break; 3087 case RISCV::V22_V23_V24_V25_V26_V27: OpKind = MCK_VRN6M1NoV0; break; 3088 case RISCV::V23_V24_V25_V26_V27_V28: OpKind = MCK_VRN6M1NoV0; break; 3089 case RISCV::V24_V25_V26_V27_V28_V29: OpKind = MCK_VRN6M1NoV0; break; 3090 case RISCV::V25_V26_V27_V28_V29_V30: OpKind = MCK_VRN6M1NoV0; break; 3091 case RISCV::V26_V27_V28_V29_V30_V31: OpKind = MCK_VRN6M1NoV0; break; 3092 case RISCV::V1_V2_V3_V4_V5_V6: OpKind = MCK_VRN6M1NoV0; break; 3093 case RISCV::V2_V3_V4_V5_V6_V7: OpKind = MCK_VRN6M1NoV0; break; 3094 case RISCV::V3_V4_V5_V6_V7_V8: OpKind = MCK_VRN6M1NoV0; break; 3095 case RISCV::V4_V5_V6_V7_V8_V9: OpKind = MCK_VRN6M1NoV0; break; 3096 case RISCV::V5_V6_V7_V8_V9_V10: OpKind = MCK_VRN6M1NoV0; break; 3097 case RISCV::V6_V7_V8_V9_V10_V11: OpKind = MCK_VRN6M1NoV0; break; 3098 case RISCV::V7_V8_V9_V10_V11_V12: OpKind = MCK_VRN6M1NoV0; break; 3099 case RISCV::V0_V1_V2_V3_V4_V5: OpKind = MCK_Reg63; break; 3100 case RISCV::V8_V9_V10_V11_V12_V13_V14: OpKind = MCK_VRN7M1NoV0; break; 3101 case RISCV::V9_V10_V11_V12_V13_V14_V15: OpKind = MCK_VRN7M1NoV0; break; 3102 case RISCV::V10_V11_V12_V13_V14_V15_V16: OpKind = MCK_VRN7M1NoV0; break; 3103 case RISCV::V11_V12_V13_V14_V15_V16_V17: OpKind = MCK_VRN7M1NoV0; break; 3104 case RISCV::V12_V13_V14_V15_V16_V17_V18: OpKind = MCK_VRN7M1NoV0; break; 3105 case RISCV::V13_V14_V15_V16_V17_V18_V19: OpKind = MCK_VRN7M1NoV0; break; 3106 case RISCV::V14_V15_V16_V17_V18_V19_V20: OpKind = MCK_VRN7M1NoV0; break; 3107 case RISCV::V15_V16_V17_V18_V19_V20_V21: OpKind = MCK_VRN7M1NoV0; break; 3108 case RISCV::V16_V17_V18_V19_V20_V21_V22: OpKind = MCK_VRN7M1NoV0; break; 3109 case RISCV::V17_V18_V19_V20_V21_V22_V23: OpKind = MCK_VRN7M1NoV0; break; 3110 case RISCV::V18_V19_V20_V21_V22_V23_V24: OpKind = MCK_VRN7M1NoV0; break; 3111 case RISCV::V19_V20_V21_V22_V23_V24_V25: OpKind = MCK_VRN7M1NoV0; break; 3112 case RISCV::V20_V21_V22_V23_V24_V25_V26: OpKind = MCK_VRN7M1NoV0; break; 3113 case RISCV::V21_V22_V23_V24_V25_V26_V27: OpKind = MCK_VRN7M1NoV0; break; 3114 case RISCV::V22_V23_V24_V25_V26_V27_V28: OpKind = MCK_VRN7M1NoV0; break; 3115 case RISCV::V23_V24_V25_V26_V27_V28_V29: OpKind = MCK_VRN7M1NoV0; break; 3116 case RISCV::V24_V25_V26_V27_V28_V29_V30: OpKind = MCK_VRN7M1NoV0; break; 3117 case RISCV::V25_V26_V27_V28_V29_V30_V31: OpKind = MCK_VRN7M1NoV0; break; 3118 case RISCV::V1_V2_V3_V4_V5_V6_V7: OpKind = MCK_VRN7M1NoV0; break; 3119 case RISCV::V2_V3_V4_V5_V6_V7_V8: OpKind = MCK_VRN7M1NoV0; break; 3120 case RISCV::V3_V4_V5_V6_V7_V8_V9: OpKind = MCK_VRN7M1NoV0; break; 3121 case RISCV::V4_V5_V6_V7_V8_V9_V10: OpKind = MCK_VRN7M1NoV0; break; 3122 case RISCV::V5_V6_V7_V8_V9_V10_V11: OpKind = MCK_VRN7M1NoV0; break; 3123 case RISCV::V6_V7_V8_V9_V10_V11_V12: OpKind = MCK_VRN7M1NoV0; break; 3124 case RISCV::V7_V8_V9_V10_V11_V12_V13: OpKind = MCK_VRN7M1NoV0; break; 3125 case RISCV::V0_V1_V2_V3_V4_V5_V6: OpKind = MCK_Reg66; break; 3126 case RISCV::V8_V9_V10_V11_V12_V13_V14_V15: OpKind = MCK_VRN8M1NoV0; break; 3127 case RISCV::V9_V10_V11_V12_V13_V14_V15_V16: OpKind = MCK_VRN8M1NoV0; break; 3128 case RISCV::V10_V11_V12_V13_V14_V15_V16_V17: OpKind = MCK_VRN8M1NoV0; break; 3129 case RISCV::V11_V12_V13_V14_V15_V16_V17_V18: OpKind = MCK_VRN8M1NoV0; break; 3130 case RISCV::V12_V13_V14_V15_V16_V17_V18_V19: OpKind = MCK_VRN8M1NoV0; break; 3131 case RISCV::V13_V14_V15_V16_V17_V18_V19_V20: OpKind = MCK_VRN8M1NoV0; break; 3132 case RISCV::V14_V15_V16_V17_V18_V19_V20_V21: OpKind = MCK_VRN8M1NoV0; break; 3133 case RISCV::V15_V16_V17_V18_V19_V20_V21_V22: OpKind = MCK_VRN8M1NoV0; break; 3134 case RISCV::V16_V17_V18_V19_V20_V21_V22_V23: OpKind = MCK_VRN8M1NoV0; break; 3135 case RISCV::V17_V18_V19_V20_V21_V22_V23_V24: OpKind = MCK_VRN8M1NoV0; break; 3136 case RISCV::V18_V19_V20_V21_V22_V23_V24_V25: OpKind = MCK_VRN8M1NoV0; break; 3137 case RISCV::V19_V20_V21_V22_V23_V24_V25_V26: OpKind = MCK_VRN8M1NoV0; break; 3138 case RISCV::V20_V21_V22_V23_V24_V25_V26_V27: OpKind = MCK_VRN8M1NoV0; break; 3139 case RISCV::V21_V22_V23_V24_V25_V26_V27_V28: OpKind = MCK_VRN8M1NoV0; break; 3140 case RISCV::V22_V23_V24_V25_V26_V27_V28_V29: OpKind = MCK_VRN8M1NoV0; break; 3141 case RISCV::V23_V24_V25_V26_V27_V28_V29_V30: OpKind = MCK_VRN8M1NoV0; break; 3142 case RISCV::V24_V25_V26_V27_V28_V29_V30_V31: OpKind = MCK_VRN8M1NoV0; break; 3143 case RISCV::V1_V2_V3_V4_V5_V6_V7_V8: OpKind = MCK_VRN8M1NoV0; break; 3144 case RISCV::V2_V3_V4_V5_V6_V7_V8_V9: OpKind = MCK_VRN8M1NoV0; break; 3145 case RISCV::V3_V4_V5_V6_V7_V8_V9_V10: OpKind = MCK_VRN8M1NoV0; break; 3146 case RISCV::V4_V5_V6_V7_V8_V9_V10_V11: OpKind = MCK_VRN8M1NoV0; break; 3147 case RISCV::V5_V6_V7_V8_V9_V10_V11_V12: OpKind = MCK_VRN8M1NoV0; break; 3148 case RISCV::V6_V7_V8_V9_V10_V11_V12_V13: OpKind = MCK_VRN8M1NoV0; break; 3149 case RISCV::V7_V8_V9_V10_V11_V12_V13_V14: OpKind = MCK_VRN8M1NoV0; break; 3150 case RISCV::V0_V1_V2_V3_V4_V5_V6_V7: OpKind = MCK_Reg69; break; 3151 } 3152 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success : 3153 getDiagKindFromRegisterClass(Kind); 3154 } 3155 3156 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER) 3157 return getDiagKindFromRegisterClass(Kind); 3158 3159 return MCTargetAsmParser::Match_InvalidOperand; 3160} 3161 3162#ifndef NDEBUG 3163const char *getMatchClassName(MatchClassKind Kind) { 3164 switch (Kind) { 3165 case InvalidMatchClass: return "InvalidMatchClass"; 3166 case OptionalMatchClass: return "OptionalMatchClass"; 3167 case MCK__40_: return "MCK__40_"; 3168 case MCK__41_: return "MCK__41_"; 3169 case MCK_Reg69: return "MCK_Reg69"; 3170 case MCK_Reg66: return "MCK_Reg66"; 3171 case MCK_Reg63: return "MCK_Reg63"; 3172 case MCK_Reg60: return "MCK_Reg60"; 3173 case MCK_Reg57: return "MCK_Reg57"; 3174 case MCK_Reg54: return "MCK_Reg54"; 3175 case MCK_Reg51: return "MCK_Reg51"; 3176 case MCK_Reg48: return "MCK_Reg48"; 3177 case MCK_Reg45: return "MCK_Reg45"; 3178 case MCK_Reg42: return "MCK_Reg42"; 3179 case MCK_Reg39: return "MCK_Reg39"; 3180 case MCK_Reg30: return "MCK_Reg30"; 3181 case MCK_Reg28: return "MCK_Reg28"; 3182 case MCK_Reg24: return "MCK_Reg24"; 3183 case MCK_Reg21: return "MCK_Reg21"; 3184 case MCK_Reg18: return "MCK_Reg18"; 3185 case MCK_GPRX0: return "MCK_GPRX0"; 3186 case MCK_SP: return "MCK_SP"; 3187 case MCK_VMV0: return "MCK_VMV0"; 3188 case MCK_Reg36: return "MCK_Reg36"; 3189 case MCK_VCSR: return "MCK_VCSR"; 3190 case MCK_VRM8NoV0: return "MCK_VRM8NoV0"; 3191 case MCK_Reg35: return "MCK_Reg35"; 3192 case MCK_VRM8: return "MCK_VRM8"; 3193 case MCK_Reg9: return "MCK_Reg9"; 3194 case MCK_VRN2M4NoV0: return "MCK_VRN2M4NoV0"; 3195 case MCK_Reg34: return "MCK_Reg34"; 3196 case MCK_VRM4NoV0: return "MCK_VRM4NoV0"; 3197 case MCK_VRN2M4: return "MCK_VRN2M4"; 3198 case MCK_FPR32C: return "MCK_FPR32C"; 3199 case MCK_FPR64C: return "MCK_FPR64C"; 3200 case MCK_GPRC: return "MCK_GPRC"; 3201 case MCK_VRM4: return "MCK_VRM4"; 3202 case MCK_VRN4M2NoV0: return "MCK_VRN4M2NoV0"; 3203 case MCK_Reg33: return "MCK_Reg33"; 3204 case MCK_VRN3M2NoV0: return "MCK_VRN3M2NoV0"; 3205 case MCK_VRN4M2: return "MCK_VRN4M2"; 3206 case MCK_Reg32: return "MCK_Reg32"; 3207 case MCK_GPRTC: return "MCK_GPRTC"; 3208 case MCK_VRN2M2NoV0: return "MCK_VRN2M2NoV0"; 3209 case MCK_VRN3M2: return "MCK_VRN3M2"; 3210 case MCK_Reg31: return "MCK_Reg31"; 3211 case MCK_VRM2NoV0: return "MCK_VRM2NoV0"; 3212 case MCK_VRN2M2: return "MCK_VRN2M2"; 3213 case MCK_GPRPF64: return "MCK_GPRPF64"; 3214 case MCK_VRM2: return "MCK_VRM2"; 3215 case MCK_VRN8M1NoV0: return "MCK_VRN8M1NoV0"; 3216 case MCK_VRN7M1NoV0: return "MCK_VRN7M1NoV0"; 3217 case MCK_VRN8M1: return "MCK_VRN8M1"; 3218 case MCK_GPRJALR: return "MCK_GPRJALR"; 3219 case MCK_VRN6M1NoV0: return "MCK_VRN6M1NoV0"; 3220 case MCK_VRN7M1: return "MCK_VRN7M1"; 3221 case MCK_VRN5M1NoV0: return "MCK_VRN5M1NoV0"; 3222 case MCK_VRN6M1: return "MCK_VRN6M1"; 3223 case MCK_VRN4M1NoV0: return "MCK_VRN4M1NoV0"; 3224 case MCK_VRN5M1: return "MCK_VRN5M1"; 3225 case MCK_VRN3M1NoV0: return "MCK_VRN3M1NoV0"; 3226 case MCK_VRN4M1: return "MCK_VRN4M1"; 3227 case MCK_GPRNoX0X2: return "MCK_GPRNoX0X2"; 3228 case MCK_VRN2M1NoV0: return "MCK_VRN2M1NoV0"; 3229 case MCK_VRN3M1: return "MCK_VRN3M1"; 3230 case MCK_GPRNoX0: return "MCK_GPRNoX0"; 3231 case MCK_VRN2M1: return "MCK_VRN2M1"; 3232 case MCK_VRNoV0: return "MCK_VRNoV0"; 3233 case MCK_FPR16: return "MCK_FPR16"; 3234 case MCK_FPR32: return "MCK_FPR32"; 3235 case MCK_FPR64: return "MCK_FPR64"; 3236 case MCK_GPR: return "MCK_GPR"; 3237 case MCK_VM: return "MCK_VM"; 3238 case MCK_AnyReg: return "MCK_AnyReg"; 3239 case MCK_BareSymbol: return "MCK_BareSymbol"; 3240 case MCK_CLUIImm: return "MCK_CLUIImm"; 3241 case MCK_CSRSystemRegister: return "MCK_CSRSystemRegister"; 3242 case MCK_CallSymbol: return "MCK_CallSymbol"; 3243 case MCK_FRMArg: return "MCK_FRMArg"; 3244 case MCK_FenceArg: return "MCK_FenceArg"; 3245 case MCK_GPRAsFPR: return "MCK_GPRAsFPR"; 3246 case MCK_GPRF64AsFPR: return "MCK_GPRF64AsFPR"; 3247 case MCK_GPRPF64AsFPR: return "MCK_GPRPF64AsFPR"; 3248 case MCK_Imm: return "MCK_Imm"; 3249 case MCK_ImmZero: return "MCK_ImmZero"; 3250 case MCK_InsnDirectiveOpcode: return "MCK_InsnDirectiveOpcode"; 3251 case MCK_PseudoJumpSymbol: return "MCK_PseudoJumpSymbol"; 3252 case MCK_RnumArg: return "MCK_RnumArg"; 3253 case MCK_SImm5Plus1: return "MCK_SImm5Plus1"; 3254 case MCK_SImm21Lsb0JAL: return "MCK_SImm21Lsb0JAL"; 3255 case MCK_TPRelAddSymbol: return "MCK_TPRelAddSymbol"; 3256 case MCK_UImmLog2XLen: return "MCK_UImmLog2XLen"; 3257 case MCK_UImmLog2XLenHalf: return "MCK_UImmLog2XLenHalf"; 3258 case MCK_UImmLog2XLenNonZero: return "MCK_UImmLog2XLenNonZero"; 3259 case MCK_RVVMaskRegOpOperand: return "MCK_RVVMaskRegOpOperand"; 3260 case MCK_ZeroOffsetMemOpOperand: return "MCK_ZeroOffsetMemOpOperand"; 3261 case MCK_UImm2: return "MCK_UImm2"; 3262 case MCK_UImm3: return "MCK_UImm3"; 3263 case MCK_UImm5: return "MCK_UImm5"; 3264 case MCK_UImm7: return "MCK_UImm7"; 3265 case MCK_SImm12: return "MCK_SImm12"; 3266 case MCK_SImm13Lsb0: return "MCK_SImm13Lsb0"; 3267 case MCK_UImm20LUI: return "MCK_UImm20LUI"; 3268 case MCK_UImm20AUIPC: return "MCK_UImm20AUIPC"; 3269 case MCK_ImmXLenLI: return "MCK_ImmXLenLI"; 3270 case MCK_SImm12Lsb00000: return "MCK_SImm12Lsb00000"; 3271 case MCK_SImm6: return "MCK_SImm6"; 3272 case MCK_SImm6NonZero: return "MCK_SImm6NonZero"; 3273 case MCK_UImm7Lsb00: return "MCK_UImm7Lsb00"; 3274 case MCK_UImm8Lsb00: return "MCK_UImm8Lsb00"; 3275 case MCK_UImm8Lsb000: return "MCK_UImm8Lsb000"; 3276 case MCK_SImm9Lsb0: return "MCK_SImm9Lsb0"; 3277 case MCK_UImm9Lsb000: return "MCK_UImm9Lsb000"; 3278 case MCK_UImm10Lsb00NonZero: return "MCK_UImm10Lsb00NonZero"; 3279 case MCK_SImm10Lsb0000NonZero: return "MCK_SImm10Lsb0000NonZero"; 3280 case MCK_SImm12Lsb0: return "MCK_SImm12Lsb0"; 3281 case MCK_VTypeI10: return "MCK_VTypeI10"; 3282 case MCK_VTypeI11: return "MCK_VTypeI11"; 3283 case MCK_SImm5: return "MCK_SImm5"; 3284 case NumMatchClassKinds: return "NumMatchClassKinds"; 3285 } 3286 llvm_unreachable("unhandled MatchClassKind!"); 3287} 3288 3289#endif // NDEBUG 3290FeatureBitset RISCVAsmParser:: 3291ComputeAvailableFeatures(const FeatureBitset &FB) const { 3292 FeatureBitset Features; 3293 if (FB[RISCV::FeatureStdExtM]) 3294 Features.set(Feature_HasStdExtMBit); 3295 if (FB[RISCV::FeatureStdExtM] || FB[RISCV::FeatureStdExtZmmul]) 3296 Features.set(Feature_HasStdExtMOrZmmulBit); 3297 if (FB[RISCV::FeatureStdExtA]) 3298 Features.set(Feature_HasStdExtABit); 3299 if (FB[RISCV::FeatureStdExtF]) 3300 Features.set(Feature_HasStdExtFBit); 3301 if (FB[RISCV::FeatureStdExtD]) 3302 Features.set(Feature_HasStdExtDBit); 3303 if (FB[RISCV::FeatureStdExtH]) 3304 Features.set(Feature_HasStdExtHBit); 3305 if (FB[RISCV::FeatureStdExtZihintpause]) 3306 Features.set(Feature_HasStdExtZihintpauseBit); 3307 if (FB[RISCV::FeatureStdExtZihintntl]) 3308 Features.set(Feature_HasStdExtZihintntlBit); 3309 if (FB[RISCV::FeatureStdExtZfhmin]) 3310 Features.set(Feature_HasStdExtZfhminBit); 3311 if (FB[RISCV::FeatureStdExtZfh]) 3312 Features.set(Feature_HasStdExtZfhBit); 3313 if (FB[RISCV::FeatureStdExtZfh] || FB[RISCV::FeatureStdExtZfhmin]) 3314 Features.set(Feature_HasStdExtZfhOrZfhminBit); 3315 if (FB[RISCV::FeatureStdExtZfinx]) 3316 Features.set(Feature_HasStdExtZfinxBit); 3317 if (FB[RISCV::FeatureStdExtZdinx]) 3318 Features.set(Feature_HasStdExtZdinxBit); 3319 if (FB[RISCV::FeatureStdExtZhinxmin]) 3320 Features.set(Feature_HasStdExtZhinxminBit); 3321 if (FB[RISCV::FeatureStdExtZhinx]) 3322 Features.set(Feature_HasStdExtZhinxBit); 3323 if (FB[RISCV::FeatureStdExtZhinx] || FB[RISCV::FeatureStdExtZhinxmin]) 3324 Features.set(Feature_HasStdExtZhinxOrZhinxminBit); 3325 if (FB[RISCV::FeatureStdExtC]) 3326 Features.set(Feature_HasStdExtCBit); 3327 if (FB[RISCV::FeatureStdExtZba]) 3328 Features.set(Feature_HasStdExtZbaBit); 3329 if (FB[RISCV::FeatureStdExtZbb]) 3330 Features.set(Feature_HasStdExtZbbBit); 3331 if (FB[RISCV::FeatureStdExtZbc]) 3332 Features.set(Feature_HasStdExtZbcBit); 3333 if (FB[RISCV::FeatureStdExtZbs]) 3334 Features.set(Feature_HasStdExtZbsBit); 3335 if (FB[RISCV::FeatureStdExtZbkb]) 3336 Features.set(Feature_HasStdExtZbkbBit); 3337 if (FB[RISCV::FeatureStdExtZbkx]) 3338 Features.set(Feature_HasStdExtZbkxBit); 3339 if (FB[RISCV::FeatureStdExtZbb] || FB[RISCV::FeatureStdExtZbkb]) 3340 Features.set(Feature_HasStdExtZbbOrZbkbBit); 3341 if (FB[RISCV::FeatureStdExtZbkc]) 3342 Features.set(Feature_HasStdExtZbkcBit); 3343 if (FB[RISCV::FeatureStdExtZbc] || FB[RISCV::FeatureStdExtZbkc]) 3344 Features.set(Feature_HasStdExtZbcOrZbkcBit); 3345 if (FB[RISCV::FeatureStdExtZknd]) 3346 Features.set(Feature_HasStdExtZkndBit); 3347 if (FB[RISCV::FeatureStdExtZkne]) 3348 Features.set(Feature_HasStdExtZkneBit); 3349 if (FB[RISCV::FeatureStdExtZknd] || FB[RISCV::FeatureStdExtZkne]) 3350 Features.set(Feature_HasStdExtZkndOrZkneBit); 3351 if (FB[RISCV::FeatureStdExtZknh]) 3352 Features.set(Feature_HasStdExtZknhBit); 3353 if (FB[RISCV::FeatureStdExtZksed]) 3354 Features.set(Feature_HasStdExtZksedBit); 3355 if (FB[RISCV::FeatureStdExtZksh]) 3356 Features.set(Feature_HasStdExtZkshBit); 3357 if (FB[RISCV::FeatureStdExtZkr]) 3358 Features.set(Feature_HasStdExtZkrBit); 3359 if (FB[RISCV::FeatureStdExtC] || FB[RISCV::FeatureExtZca]) 3360 Features.set(Feature_HasStdExtCOrZcaBit); 3361 if (FB[RISCV::FeatureStdExtC] || FB[RISCV::FeatureExtZcd]) 3362 Features.set(Feature_HasStdExtCOrZcdBit); 3363 if (FB[RISCV::FeatureStdExtC] || FB[RISCV::FeatureExtZcf]) 3364 Features.set(Feature_HasStdExtCOrZcfBit); 3365 if (!FB[RISCV::FeatureNoRVCHints]) 3366 Features.set(Feature_HasRVCHintsBit); 3367 if (FB[RISCV::FeatureStdExtZve32x]) 3368 Features.set(Feature_HasVInstructionsBit); 3369 if (FB[RISCV::FeatureStdExtZve64x]) 3370 Features.set(Feature_HasVInstructionsI64Bit); 3371 if (FB[RISCV::FeatureStdExtZve32f]) 3372 Features.set(Feature_HasVInstructionsAnyFBit); 3373 if (FB[RISCV::FeatureStdExtZicbom]) 3374 Features.set(Feature_HasStdExtZicbomBit); 3375 if (FB[RISCV::FeatureStdExtZicboz]) 3376 Features.set(Feature_HasStdExtZicbozBit); 3377 if (FB[RISCV::FeatureStdExtZicbop]) 3378 Features.set(Feature_HasStdExtZicbopBit); 3379 if (FB[RISCV::FeatureStdExtSvinval]) 3380 Features.set(Feature_HasStdExtSvinvalBit); 3381 if (FB[RISCV::FeatureStdExtZtso]) 3382 Features.set(Feature_HasStdExtZtsoBit); 3383 if (FB[RISCV::FeatureStdExtZawrs]) 3384 Features.set(Feature_HasStdExtZawrsBit); 3385 if (FB[RISCV::FeatureVendorXVentanaCondOps]) 3386 Features.set(Feature_HasVendorXVentanaCondOpsBit); 3387 if (FB[RISCV::FeatureVendorXTHeadVdot]) 3388 Features.set(Feature_HasVendorXTHeadVdotBit); 3389 if (FB[RISCV::Feature64Bit]) 3390 Features.set(Feature_IsRV64Bit); 3391 if (!FB[RISCV::Feature64Bit]) 3392 Features.set(Feature_IsRV32Bit); 3393 if (FB[RISCV::FeatureRV32E]) 3394 Features.set(Feature_IsRV32EBit); 3395 return Features; 3396} 3397 3398static bool checkAsmTiedOperandConstraints(const RISCVAsmParser&AsmParser, 3399 unsigned Kind, 3400 const OperandVector &Operands, 3401 uint64_t &ErrorInfo) { 3402 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); 3403 const uint8_t *Converter = ConversionTable[Kind]; 3404 for (const uint8_t *p = Converter; *p; p += 2) { 3405 switch (*p) { 3406 case CVT_Tied: { 3407 unsigned OpIdx = *(p + 1); 3408 assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) - 3409 std::begin(TiedAsmOperandTable)) && 3410 "Tied operand not found"); 3411 unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1]; 3412 unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2]; 3413 if (OpndNum1 != OpndNum2) { 3414 auto &SrcOp1 = Operands[OpndNum1]; 3415 auto &SrcOp2 = Operands[OpndNum2]; 3416 if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) { 3417 ErrorInfo = OpndNum2; 3418 return false; 3419 } 3420 } 3421 break; 3422 } 3423 default: 3424 break; 3425 } 3426 } 3427 return true; 3428} 3429 3430static const char MnemonicTable[] = 3431 "\007.insn_b\007.insn_i\007.insn_j\007.insn_r\010.insn_r4\007.insn_s\010" 3432 ".insn_sb\007.insn_u\010.insn_uj\003add\006add.uw\004addi\005addiw\004ad" 3433 "dw\010aes32dsi\taes32dsmi\010aes32esi\taes32esmi\007aes64ds\010aes64dsm" 3434 "\007aes64es\010aes64esm\007aes64im\taes64ks1i\010aes64ks2\010amoadd.d\013" 3435 "amoadd.d.aq\015amoadd.d.aqrl\013amoadd.d.rl\010amoadd.w\013amoadd.w.aq\015" 3436 "amoadd.w.aqrl\013amoadd.w.rl\010amoand.d\013amoand.d.aq\015amoand.d.aqr" 3437 "l\013amoand.d.rl\010amoand.w\013amoand.w.aq\015amoand.w.aqrl\013amoand." 3438 "w.rl\010amomax.d\013amomax.d.aq\015amomax.d.aqrl\013amomax.d.rl\010amom" 3439 "ax.w\013amomax.w.aq\015amomax.w.aqrl\013amomax.w.rl\tamomaxu.d\014amoma" 3440 "xu.d.aq\016amomaxu.d.aqrl\014amomaxu.d.rl\tamomaxu.w\014amomaxu.w.aq\016" 3441 "amomaxu.w.aqrl\014amomaxu.w.rl\010amomin.d\013amomin.d.aq\015amomin.d.a" 3442 "qrl\013amomin.d.rl\010amomin.w\013amomin.w.aq\015amomin.w.aqrl\013amomi" 3443 "n.w.rl\tamominu.d\014amominu.d.aq\016amominu.d.aqrl\014amominu.d.rl\tam" 3444 "ominu.w\014amominu.w.aq\016amominu.w.aqrl\014amominu.w.rl\007amoor.d\na" 3445 "moor.d.aq\014amoor.d.aqrl\namoor.d.rl\007amoor.w\namoor.w.aq\014amoor.w" 3446 ".aqrl\namoor.w.rl\tamoswap.d\014amoswap.d.aq\016amoswap.d.aqrl\014amosw" 3447 "ap.d.rl\tamoswap.w\014amoswap.w.aq\016amoswap.w.aqrl\014amoswap.w.rl\010" 3448 "amoxor.d\013amoxor.d.aq\015amoxor.d.aqrl\013amoxor.d.rl\010amoxor.w\013" 3449 "amoxor.w.aq\015amoxor.w.aqrl\013amoxor.w.rl\003and\004andi\004andn\005a" 3450 "uipc\004bclr\005bclri\003beq\004beqz\004bext\005bexti\003bge\004bgeu\004" 3451 "bgez\003bgt\004bgtu\004bgtz\004binv\005binvi\003ble\004bleu\004blez\003" 3452 "blt\004bltu\004bltz\003bne\004bnez\005brev8\004bset\005bseti\005c.add\006" 3453 "c.addi\nc.addi16sp\nc.addi4spn\007c.addiw\006c.addw\005c.and\006c.andi\006" 3454 "c.beqz\006c.bnez\010c.ebreak\005c.fld\007c.fldsp\005c.flw\007c.flwsp\005" 3455 "c.fsd\007c.fsdsp\005c.fsw\007c.fswsp\003c.j\005c.jal\006c.jalr\004c.jr\004" 3456 "c.ld\006c.ldsp\004c.li\005c.lui\004c.lw\006c.lwsp\004c.mv\005c.nop\tc.n" 3457 "tl.all\010c.ntl.p1\nc.ntl.pall\010c.ntl.s1\004c.or\004c.sd\006c.sdsp\006" 3458 "c.slli\010c.slli64\006c.srai\010c.srai64\006c.srli\010c.srli64\005c.sub" 3459 "\006c.subw\004c.sw\006c.swsp\007c.unimp\005c.xor\004call\tcbo.clean\tcb" 3460 "o.flush\tcbo.inval\010cbo.zero\005clmul\006clmulh\006clmulr\003clz\004c" 3461 "lzw\004cpop\005cpopw\004csrc\005csrci\004csrr\005csrrc\006csrrci\005csr" 3462 "rs\006csrrsi\005csrrw\006csrrwi\004csrs\005csrsi\004csrw\005csrwi\003ct" 3463 "z\004ctzw\003div\004divu\005divuw\004divw\004dret\006ebreak\005ecall\006" 3464 "fabs.d\006fabs.h\006fabs.s\006fadd.d\006fadd.h\006fadd.s\010fclass.d\010" 3465 "fclass.h\010fclass.s\010fcvt.d.h\010fcvt.d.l\tfcvt.d.lu\010fcvt.d.s\010" 3466 "fcvt.d.w\tfcvt.d.wu\010fcvt.h.d\010fcvt.h.l\tfcvt.h.lu\010fcvt.h.s\010f" 3467 "cvt.h.w\tfcvt.h.wu\010fcvt.l.d\010fcvt.l.h\010fcvt.l.s\tfcvt.lu.d\tfcvt" 3468 ".lu.h\tfcvt.lu.s\010fcvt.s.d\010fcvt.s.h\010fcvt.s.l\tfcvt.s.lu\010fcvt" 3469 ".s.w\tfcvt.s.wu\010fcvt.w.d\010fcvt.w.h\010fcvt.w.s\tfcvt.wu.d\tfcvt.wu" 3470 ".h\tfcvt.wu.s\006fdiv.d\006fdiv.h\006fdiv.s\005fence\007fence.i\tfence." 3471 "tso\005feq.d\005feq.h\005feq.s\005fge.d\005fge.h\005fge.s\005fgt.d\005f" 3472 "gt.h\005fgt.s\003fld\005fle.d\005fle.h\005fle.s\003flh\005flt.d\005flt." 3473 "h\005flt.s\003flw\007fmadd.d\007fmadd.h\007fmadd.s\006fmax.d\006fmax.h\006" 3474 "fmax.s\006fmin.d\006fmin.h\006fmin.s\007fmsub.d\007fmsub.h\007fmsub.s\006" 3475 "fmul.d\006fmul.h\006fmul.s\005fmv.d\007fmv.d.x\005fmv.h\007fmv.h.x\005f" 3476 "mv.s\007fmv.w.x\007fmv.x.d\007fmv.x.h\007fmv.x.w\006fneg.d\006fneg.h\006" 3477 "fneg.s\010fnmadd.d\010fnmadd.h\010fnmadd.s\010fnmsub.d\010fnmsub.h\010f" 3478 "nmsub.s\005frcsr\007frflags\004frrm\004frsr\005fscsr\003fsd\007fsflags\010" 3479 "fsflagsi\007fsgnj.d\007fsgnj.h\007fsgnj.s\010fsgnjn.d\010fsgnjn.h\010fs" 3480 "gnjn.s\010fsgnjx.d\010fsgnjx.h\010fsgnjx.s\003fsh\007fsqrt.d\007fsqrt.h" 3481 "\007fsqrt.s\004fsrm\005fsrmi\004fssr\006fsub.d\006fsub.h\006fsub.s\003f" 3482 "sw\013hfence.gvma\013hfence.vvma\013hinval.gvma\013hinval.vvma\005hlv.b" 3483 "\006hlv.bu\005hlv.d\005hlv.h\006hlv.hu\005hlv.w\006hlv.wu\007hlvx.hu\007" 3484 "hlvx.wu\005hsv.b\005hsv.d\005hsv.h\005hsv.w\001j\003jal\004jalr\002jr\004" 3485 "jump\002la\tla.tls.gd\tla.tls.ie\002lb\003lbu\002ld\002lh\003lhu\002li\003" 3486 "lla\004lr.d\007lr.d.aq\tlr.d.aqrl\007lr.d.rl\004lr.w\007lr.w.aq\tlr.w.a" 3487 "qrl\007lr.w.rl\003lui\002lw\003lwu\003max\004maxu\003min\004minu\004mre" 3488 "t\003mul\004mulh\006mulhsu\005mulhu\004mulw\002mv\003neg\004negw\003nop" 3489 "\003not\007ntl.all\006ntl.p1\010ntl.pall\006ntl.s1\002or\005orc.b\003or" 3490 "i\003orn\004pack\005packh\005packw\005pause\nprefetch.i\nprefetch.r\npr" 3491 "efetch.w\007rdcycle\010rdcycleh\trdinstret\nrdinstreth\006rdtime\007rdt" 3492 "imeh\003rem\004remu\005remuw\004remw\003ret\004rev8\003rol\004rolw\003r" 3493 "or\004rori\005roriw\004rorw\002sb\004sc.d\007sc.d.aq\tsc.d.aqrl\007sc.d" 3494 ".rl\004sc.w\007sc.w.aq\tsc.w.aqrl\007sc.w.rl\002sd\004seqz\006sext.b\006" 3495 "sext.h\006sext.w\017sfence.inval.ir\nsfence.vma\016sfence.w.inval\003sg" 3496 "t\004sgtu\004sgtz\002sh\006sh1add\tsh1add.uw\006sh2add\tsh2add.uw\006sh" 3497 "3add\tsh3add.uw\nsha256sig0\nsha256sig1\nsha256sum0\nsha256sum1\nsha512" 3498 "sig0\013sha512sig0h\013sha512sig0l\nsha512sig1\013sha512sig1h\013sha512" 3499 "sig1l\nsha512sum0\013sha512sum0r\nsha512sum1\013sha512sum1r\nsinval.vma" 3500 "\003sll\004slli\007slli.uw\005slliw\004sllw\003slt\004slti\005sltiu\004" 3501 "sltu\004sltz\005sm3p0\005sm3p1\005sm4ed\005sm4ks\004snez\003sra\004srai" 3502 "\005sraiw\004sraw\004sret\003srl\004srli\005srliw\004srlw\003sub\004sub" 3503 "w\002sw\004tail\013th.vmaqa.vv\013th.vmaqa.vx\015th.vmaqasu.vv\015th.vm" 3504 "aqasu.vx\014th.vmaqau.vv\014th.vmaqau.vx\015th.vmaqaus.vx\005unimp\005u" 3505 "nzip\004uret\010vaadd.vv\010vaadd.vx\tvaaddu.vv\tvaaddu.vx\010vadc.vim\010" 3506 "vadc.vvm\010vadc.vxm\007vadd.vi\007vadd.vv\007vadd.vx\007vand.vi\007van" 3507 "d.vv\007vand.vx\010vasub.vv\010vasub.vx\tvasubu.vv\tvasubu.vx\014vcompr" 3508 "ess.vm\007vcpop.m\007vdiv.vv\007vdiv.vx\010vdivu.vv\010vdivu.vx\007vfab" 3509 "s.v\010vfadd.vf\010vfadd.vv\tvfclass.v\013vfcvt.f.x.v\014vfcvt.f.xu.v\017" 3510 "vfcvt.rtz.x.f.v\020vfcvt.rtz.xu.f.v\013vfcvt.x.f.v\014vfcvt.xu.f.v\010v" 3511 "fdiv.vf\010vfdiv.vv\010vfirst.m\tvfmacc.vf\tvfmacc.vv\tvfmadd.vf\tvfmad" 3512 "d.vv\010vfmax.vf\010vfmax.vv\013vfmerge.vfm\010vfmin.vf\010vfmin.vv\tvf" 3513 "msac.vf\tvfmsac.vv\tvfmsub.vf\tvfmsub.vv\010vfmul.vf\010vfmul.vv\010vfm" 3514 "v.f.s\010vfmv.s.f\010vfmv.v.f\014vfncvt.f.f.w\014vfncvt.f.x.w\015vfncvt" 3515 ".f.xu.w\020vfncvt.rod.f.f.w\020vfncvt.rtz.x.f.w\021vfncvt.rtz.xu.f.w\014" 3516 "vfncvt.x.f.w\015vfncvt.xu.f.w\007vfneg.v\nvfnmacc.vf\nvfnmacc.vv\nvfnma" 3517 "dd.vf\nvfnmadd.vv\nvfnmsac.vf\nvfnmsac.vv\nvfnmsub.vf\nvfnmsub.vv\tvfrd" 3518 "iv.vf\010vfrec7.v\013vfredmax.vs\013vfredmin.vs\014vfredosum.vs\013vfre" 3519 "dsum.vs\014vfredusum.vs\nvfrsqrt7.v\tvfrsub.vf\tvfsgnj.vf\tvfsgnj.vv\nv" 3520 "fsgnjn.vf\nvfsgnjn.vv\nvfsgnjx.vf\nvfsgnjx.vv\017vfslide1down.vf\015vfs" 3521 "lide1up.vf\010vfsqrt.v\010vfsub.vf\010vfsub.vv\tvfwadd.vf\tvfwadd.vv\tv" 3522 "fwadd.wf\tvfwadd.wv\014vfwcvt.f.f.v\014vfwcvt.f.x.v\015vfwcvt.f.xu.v\020" 3523 "vfwcvt.rtz.x.f.v\021vfwcvt.rtz.xu.f.v\014vfwcvt.x.f.v\015vfwcvt.xu.f.v\n" 3524 "vfwmacc.vf\nvfwmacc.vv\nvfwmsac.vf\nvfwmsac.vv\tvfwmul.vf\tvfwmul.vv\013" 3525 "vfwnmacc.vf\013vfwnmacc.vv\013vfwnmsac.vf\013vfwnmsac.vv\015vfwredosum." 3526 "vs\014vfwredsum.vs\015vfwredusum.vs\tvfwsub.vf\tvfwsub.vv\tvfwsub.wf\tv" 3527 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"oxseg8ei32.v\016vloxseg8ei64.v\015vloxseg8ei8.v\010vlse16.v\010vlse32.v" 3540 "\010vlse64.v\007vlse8.v\013vlseg2e16.v\015vlseg2e16ff.v\013vlseg2e32.v\015" 3541 "vlseg2e32ff.v\013vlseg2e64.v\015vlseg2e64ff.v\nvlseg2e8.v\014vlseg2e8ff" 3542 ".v\013vlseg3e16.v\015vlseg3e16ff.v\013vlseg3e32.v\015vlseg3e32ff.v\013v" 3543 "lseg3e64.v\015vlseg3e64ff.v\nvlseg3e8.v\014vlseg3e8ff.v\013vlseg4e16.v\015" 3544 "vlseg4e16ff.v\013vlseg4e32.v\015vlseg4e32ff.v\013vlseg4e64.v\015vlseg4e" 3545 "64ff.v\nvlseg4e8.v\014vlseg4e8ff.v\013vlseg5e16.v\015vlseg5e16ff.v\013v" 3546 "lseg5e32.v\015vlseg5e32ff.v\013vlseg5e64.v\015vlseg5e64ff.v\nvlseg5e8.v" 3547 "\014vlseg5e8ff.v\013vlseg6e16.v\015vlseg6e16ff.v\013vlseg6e32.v\015vlse" 3548 "g6e32ff.v\013vlseg6e64.v\015vlseg6e64ff.v\nvlseg6e8.v\014vlseg6e8ff.v\013" 3549 "vlseg7e16.v\015vlseg7e16ff.v\013vlseg7e32.v\015vlseg7e32ff.v\013vlseg7e" 3550 "64.v\015vlseg7e64ff.v\nvlseg7e8.v\014vlseg7e8ff.v\013vlseg8e16.v\015vls" 3551 "eg8e16ff.v\013vlseg8e32.v\015vlseg8e32ff.v\013vlseg8e64.v\015vlseg8e64f" 3552 "f.v\nvlseg8e8.v\014vlseg8e8ff.v\014vlsseg2e16.v\014vlsseg2e32.v\014vlss" 3553 "eg2e64.v\013vlsseg2e8.v\014vlsseg3e16.v\014vlsseg3e32.v\014vlsseg3e64.v" 3554 "\013vlsseg3e8.v\014vlsseg4e16.v\014vlsseg4e32.v\014vlsseg4e64.v\013vlss" 3555 "eg4e8.v\014vlsseg5e16.v\014vlsseg5e32.v\014vlsseg5e64.v\013vlsseg5e8.v\014" 3556 "vlsseg6e16.v\014vlsseg6e32.v\014vlsseg6e64.v\013vlsseg6e8.v\014vlsseg7e" 3557 "16.v\014vlsseg7e32.v\014vlsseg7e64.v\013vlsseg7e8.v\014vlsseg8e16.v\014" 3558 "vlsseg8e32.v\014vlsseg8e64.v\013vlsseg8e8.v\nvluxei16.v\nvluxei32.v\nvl" 3559 "uxei64.v\tvluxei8.v\016vluxseg2ei16.v\016vluxseg2ei32.v\016vluxseg2ei64" 3560 ".v\015vluxseg2ei8.v\016vluxseg3ei16.v\016vluxseg3ei32.v\016vluxseg3ei64" 3561 ".v\015vluxseg3ei8.v\016vluxseg4ei16.v\016vluxseg4ei32.v\016vluxseg4ei64" 3562 ".v\015vluxseg4ei8.v\016vluxseg5ei16.v\016vluxseg5ei32.v\016vluxseg5ei64" 3563 ".v\015vluxseg5ei8.v\016vluxseg6ei16.v\016vluxseg6ei32.v\016vluxseg6ei64" 3564 ".v\015vluxseg6ei8.v\016vluxseg7ei16.v\016vluxseg7ei32.v\016vluxseg7ei64" 3565 ".v\015vluxseg7ei8.v\016vluxseg8ei16.v\016vluxseg8ei32.v\016vluxseg8ei64" 3566 ".v\015vluxseg8ei8.v\010vmacc.vv\010vmacc.vx\010vmadc.vi\tvmadc.vim\010v" 3567 "madc.vv\tvmadc.vvm\010vmadc.vx\tvmadc.vxm\010vmadd.vv\010vmadd.vx\010vm" 3568 "and.mm\tvmandn.mm\013vmandnot.mm\007vmax.vv\007vmax.vx\010vmaxu.vv\010v" 3569 "maxu.vx\007vmclr.m\nvmerge.vim\nvmerge.vvm\nvmerge.vxm\010vmfeq.vf\010v" 3570 "mfeq.vv\010vmfge.vf\010vmfge.vv\010vmfgt.vf\010vmfgt.vv\010vmfle.vf\010" 3571 "vmfle.vv\010vmflt.vf\010vmflt.vv\010vmfne.vf\010vmfne.vv\007vmin.vv\007" 3572 "vmin.vx\010vminu.vv\010vminu.vx\006vmmv.m\tvmnand.mm\010vmnor.mm\007vmn" 3573 "ot.m\007vmor.mm\010vmorn.mm\nvmornot.mm\010vmsbc.vv\tvmsbc.vvm\010vmsbc" 3574 ".vx\tvmsbc.vxm\007vmsbf.m\010vmseq.vi\010vmseq.vv\010vmseq.vx\007vmset." 3575 "m\010vmsge.vi\010vmsge.vv\010vmsge.vx\tvmsgeu.vi\tvmsgeu.vv\tvmsgeu.vx\010" 3576 "vmsgt.vi\010vmsgt.vv\010vmsgt.vx\tvmsgtu.vi\tvmsgtu.vv\tvmsgtu.vx\007vm" 3577 "sif.m\010vmsle.vi\010vmsle.vv\010vmsle.vx\tvmsleu.vi\tvmsleu.vv\tvmsleu" 3578 ".vx\010vmslt.vi\010vmslt.vv\010vmslt.vx\tvmsltu.vi\tvmsltu.vv\tvmsltu.v" 3579 "x\010vmsne.vi\010vmsne.vv\010vmsne.vx\007vmsof.m\007vmul.vv\007vmul.vx\010" 3580 "vmulh.vv\010vmulh.vx\nvmulhsu.vv\nvmulhsu.vx\tvmulhu.vv\tvmulhu.vx\007v" 3581 "mv.s.x\007vmv.v.i\007vmv.v.v\007vmv.v.x\007vmv.x.s\007vmv1r.v\007vmv2r." 3582 "v\007vmv4r.v\007vmv8r.v\tvmxnor.mm\010vmxor.mm\tvnclip.wi\tvnclip.wv\tv" 3583 "nclip.wx\nvnclipu.wi\nvnclipu.wv\nvnclipu.wx\013vncvt.x.x.w\006vneg.v\t" 3584 "vnmsac.vv\tvnmsac.vx\tvnmsub.vv\tvnmsub.vx\006vnot.v\010vnsra.wi\010vns" 3585 "ra.wv\010vnsra.wx\010vnsrl.wi\010vnsrl.wv\010vnsrl.wx\006vor.vi\006vor." 3586 "vv\006vor.vx\007vpopc.m\nvredand.vs\nvredmax.vs\013vredmaxu.vs\nvredmin" 3587 ".vs\013vredminu.vs\tvredor.vs\nvredsum.vs\nvredxor.vs\007vrem.vv\007vre" 3588 "m.vx\010vremu.vv\010vremu.vx\013vrgather.vi\013vrgather.vv\013vrgather." 3589 "vx\017vrgatherei16.vv\010vrsub.vi\010vrsub.vx\006vs1r.v\006vs2r.v\006vs" 3590 "4r.v\006vs8r.v\010vsadd.vi\010vsadd.vv\010vsadd.vx\tvsaddu.vi\tvsaddu.v" 3591 "v\tvsaddu.vx\010vsbc.vvm\010vsbc.vxm\006vse1.v\007vse16.v\007vse32.v\007" 3592 "vse64.v\006vse8.v\010vsetivli\006vsetvl\007vsetvli\tvsext.vf2\tvsext.vf" 3593 "4\tvsext.vf8\016vslide1down.vx\014vslide1up.vx\015vslidedown.vi\015vsli" 3594 "dedown.vx\013vslideup.vi\013vslideup.vx\007vsll.vi\007vsll.vv\007vsll.v" 3595 "x\005vsm.v\010vsmul.vv\010vsmul.vx\nvsoxei16.v\nvsoxei32.v\nvsoxei64.v\t" 3596 "vsoxei8.v\016vsoxseg2ei16.v\016vsoxseg2ei32.v\016vsoxseg2ei64.v\015vsox" 3597 "seg2ei8.v\016vsoxseg3ei16.v\016vsoxseg3ei32.v\016vsoxseg3ei64.v\015vsox" 3598 "seg3ei8.v\016vsoxseg4ei16.v\016vsoxseg4ei32.v\016vsoxseg4ei64.v\015vsox" 3599 "seg4ei8.v\016vsoxseg5ei16.v\016vsoxseg5ei32.v\016vsoxseg5ei64.v\015vsox" 3600 "seg5ei8.v\016vsoxseg6ei16.v\016vsoxseg6ei32.v\016vsoxseg6ei64.v\015vsox" 3601 "seg6ei8.v\016vsoxseg7ei16.v\016vsoxseg7ei32.v\016vsoxseg7ei64.v\015vsox" 3602 "seg7ei8.v\016vsoxseg8ei16.v\016vsoxseg8ei32.v\016vsoxseg8ei64.v\015vsox" 3603 "seg8ei8.v\007vsra.vi\007vsra.vv\007vsra.vx\007vsrl.vi\007vsrl.vv\007vsr" 3604 "l.vx\010vsse16.v\010vsse32.v\010vsse64.v\007vsse8.v\013vsseg2e16.v\013v" 3605 "sseg2e32.v\013vsseg2e64.v\nvsseg2e8.v\013vsseg3e16.v\013vsseg3e32.v\013" 3606 "vsseg3e64.v\nvsseg3e8.v\013vsseg4e16.v\013vsseg4e32.v\013vsseg4e64.v\nv" 3607 "sseg4e8.v\013vsseg5e16.v\013vsseg5e32.v\013vsseg5e64.v\nvsseg5e8.v\013v" 3608 "sseg6e16.v\013vsseg6e32.v\013vsseg6e64.v\nvsseg6e8.v\013vsseg7e16.v\013" 3609 "vsseg7e32.v\013vsseg7e64.v\nvsseg7e8.v\013vsseg8e16.v\013vsseg8e32.v\013" 3610 "vsseg8e64.v\nvsseg8e8.v\010vssra.vi\010vssra.vv\010vssra.vx\010vssrl.vi" 3611 "\010vssrl.vv\010vssrl.vx\014vssseg2e16.v\014vssseg2e32.v\014vssseg2e64." 3612 "v\013vssseg2e8.v\014vssseg3e16.v\014vssseg3e32.v\014vssseg3e64.v\013vss" 3613 "seg3e8.v\014vssseg4e16.v\014vssseg4e32.v\014vssseg4e64.v\013vssseg4e8.v" 3614 "\014vssseg5e16.v\014vssseg5e32.v\014vssseg5e64.v\013vssseg5e8.v\014vsss" 3615 "eg6e16.v\014vssseg6e32.v\014vssseg6e64.v\013vssseg6e8.v\014vssseg7e16.v" 3616 "\014vssseg7e32.v\014vssseg7e64.v\013vssseg7e8.v\014vssseg8e16.v\014vsss" 3617 "eg8e32.v\014vssseg8e64.v\013vssseg8e8.v\010vssub.vv\010vssub.vx\tvssubu" 3618 ".vv\tvssubu.vx\007vsub.vv\007vsub.vx\nvsuxei16.v\nvsuxei32.v\nvsuxei64." 3619 "v\tvsuxei8.v\016vsuxseg2ei16.v\016vsuxseg2ei32.v\016vsuxseg2ei64.v\015v" 3620 "suxseg2ei8.v\016vsuxseg3ei16.v\016vsuxseg3ei32.v\016vsuxseg3ei64.v\015v" 3621 "suxseg3ei8.v\016vsuxseg4ei16.v\016vsuxseg4ei32.v\016vsuxseg4ei64.v\015v" 3622 "suxseg4ei8.v\016vsuxseg5ei16.v\016vsuxseg5ei32.v\016vsuxseg5ei64.v\015v" 3623 "suxseg5ei8.v\016vsuxseg6ei16.v\016vsuxseg6ei32.v\016vsuxseg6ei64.v\015v" 3624 "suxseg6ei8.v\016vsuxseg7ei16.v\016vsuxseg7ei32.v\016vsuxseg7ei64.v\015v" 3625 "suxseg7ei8.v\016vsuxseg8ei16.v\016vsuxseg8ei32.v\016vsuxseg8ei64.v\015v" 3626 "suxseg8ei8.v\010vt.maskc\tvt.maskcn\010vwadd.vv\010vwadd.vx\010vwadd.wv" 3627 "\010vwadd.wx\tvwaddu.vv\tvwaddu.vx\tvwaddu.wv\tvwaddu.wx\013vwcvt.x.x.v" 3628 "\014vwcvtu.x.x.v\tvwmacc.vv\tvwmacc.vx\013vwmaccsu.vv\013vwmaccsu.vx\nv" 3629 "wmaccu.vv\nvwmaccu.vx\013vwmaccus.vx\010vwmul.vv\010vwmul.vx\nvwmulsu.v" 3630 "v\nvwmulsu.vx\tvwmulu.vv\tvwmulu.vx\013vwredsum.vs\014vwredsumu.vs\010v" 3631 "wsub.vv\010vwsub.vx\010vwsub.wv\010vwsub.wx\tvwsubu.vv\tvwsubu.vx\tvwsu" 3632 "bu.wv\tvwsubu.wx\007vxor.vi\007vxor.vv\007vxor.vx\tvzext.vf2\tvzext.vf4" 3633 "\tvzext.vf8\003wfi\007wrs.nto\007wrs.sto\004xnor\003xor\004xori\006xper" 3634 "m4\006xperm8\006zext.b\006zext.h\006zext.w\003zip"; 3635 3636// Feature bitsets. 3637enum : uint8_t { 3638 AMFBS_None, 3639 AMFBS_HasStdExtA, 3640 AMFBS_HasStdExtCOrZca, 3641 AMFBS_HasStdExtD, 3642 AMFBS_HasStdExtF, 3643 AMFBS_HasStdExtH, 3644 AMFBS_HasStdExtM, 3645 AMFBS_HasStdExtMOrZmmul, 3646 AMFBS_HasStdExtSvinval, 3647 AMFBS_HasStdExtZawrs, 3648 AMFBS_HasStdExtZba, 3649 AMFBS_HasStdExtZbb, 3650 AMFBS_HasStdExtZbbOrZbkb, 3651 AMFBS_HasStdExtZbc, 3652 AMFBS_HasStdExtZbcOrZbkc, 3653 AMFBS_HasStdExtZbkb, 3654 AMFBS_HasStdExtZbkx, 3655 AMFBS_HasStdExtZbs, 3656 AMFBS_HasStdExtZfh, 3657 AMFBS_HasStdExtZfhOrZfhmin, 3658 AMFBS_HasStdExtZfinx, 3659 AMFBS_HasStdExtZhinx, 3660 AMFBS_HasStdExtZhinxOrZhinxmin, 3661 AMFBS_HasStdExtZicbom, 3662 AMFBS_HasStdExtZicbop, 3663 AMFBS_HasStdExtZicboz, 3664 AMFBS_HasStdExtZihintntl, 3665 AMFBS_HasStdExtZihintpause, 3666 AMFBS_HasStdExtZknh, 3667 AMFBS_HasStdExtZksed, 3668 AMFBS_HasStdExtZksh, 3669 AMFBS_HasVInstructions, 3670 AMFBS_HasVInstructionsAnyF, 3671 AMFBS_HasVInstructionsI64, 3672 AMFBS_HasVendorXTHeadVdot, 3673 AMFBS_IsRV32, 3674 AMFBS_IsRV64, 3675 AMFBS_HasStdExtA_IsRV64, 3676 AMFBS_HasStdExtCOrZca_HasRVCHints, 3677 AMFBS_HasStdExtCOrZca_IsRV32, 3678 AMFBS_HasStdExtCOrZca_IsRV64, 3679 AMFBS_HasStdExtCOrZcd_HasStdExtD, 3680 AMFBS_HasStdExtD_IsRV64, 3681 AMFBS_HasStdExtF_IsRV64, 3682 AMFBS_HasStdExtM_IsRV64, 3683 AMFBS_HasStdExtMOrZmmul_IsRV64, 3684 AMFBS_HasStdExtZba_IsRV64, 3685 AMFBS_HasStdExtZbb_IsRV32, 3686 AMFBS_HasStdExtZbb_IsRV64, 3687 AMFBS_HasStdExtZbbOrZbkb_IsRV32, 3688 AMFBS_HasStdExtZbbOrZbkb_IsRV64, 3689 AMFBS_HasStdExtZbkb_IsRV32, 3690 AMFBS_HasStdExtZbkb_IsRV64, 3691 AMFBS_HasStdExtZdinx_IsRV32, 3692 AMFBS_HasStdExtZdinx_IsRV64, 3693 AMFBS_HasStdExtZfh_IsRV64, 3694 AMFBS_HasStdExtZfhOrZfhmin_HasStdExtD, 3695 AMFBS_HasStdExtZfinx_IsRV64, 3696 AMFBS_HasStdExtZhinx_IsRV64, 3697 AMFBS_HasStdExtZhinxOrZhinxmin_HasStdExtZdinx, 3698 AMFBS_HasStdExtZknd_IsRV32, 3699 AMFBS_HasStdExtZknd_IsRV64, 3700 AMFBS_HasStdExtZkndOrZkne_IsRV64, 3701 AMFBS_HasStdExtZkne_IsRV32, 3702 AMFBS_HasStdExtZkne_IsRV64, 3703 AMFBS_HasStdExtZknh_IsRV32, 3704 AMFBS_HasStdExtZknh_IsRV64, 3705 AMFBS_HasVInstructionsI64_IsRV64, 3706 AMFBS_IsRV64_HasStdExtH, 3707 AMFBS_IsRV64_HasVInstructionsI64, 3708 AMFBS_IsRV64_HasVendorXVentanaCondOps, 3709 AMFBS_HasStdExtC_HasRVCHints_HasStdExtZihintntl, 3710 AMFBS_HasStdExtCOrZcf_HasStdExtF_IsRV32, 3711}; 3712 3713static constexpr FeatureBitset FeatureBitsets[] = { 3714 {}, // AMFBS_None 3715 {Feature_HasStdExtABit, }, 3716 {Feature_HasStdExtCOrZcaBit, }, 3717 {Feature_HasStdExtDBit, }, 3718 {Feature_HasStdExtFBit, }, 3719 {Feature_HasStdExtHBit, }, 3720 {Feature_HasStdExtMBit, }, 3721 {Feature_HasStdExtMOrZmmulBit, }, 3722 {Feature_HasStdExtSvinvalBit, }, 3723 {Feature_HasStdExtZawrsBit, }, 3724 {Feature_HasStdExtZbaBit, }, 3725 {Feature_HasStdExtZbbBit, }, 3726 {Feature_HasStdExtZbbOrZbkbBit, }, 3727 {Feature_HasStdExtZbcBit, }, 3728 {Feature_HasStdExtZbcOrZbkcBit, }, 3729 {Feature_HasStdExtZbkbBit, }, 3730 {Feature_HasStdExtZbkxBit, }, 3731 {Feature_HasStdExtZbsBit, }, 3732 {Feature_HasStdExtZfhBit, }, 3733 {Feature_HasStdExtZfhOrZfhminBit, }, 3734 {Feature_HasStdExtZfinxBit, }, 3735 {Feature_HasStdExtZhinxBit, }, 3736 {Feature_HasStdExtZhinxOrZhinxminBit, }, 3737 {Feature_HasStdExtZicbomBit, }, 3738 {Feature_HasStdExtZicbopBit, }, 3739 {Feature_HasStdExtZicbozBit, }, 3740 {Feature_HasStdExtZihintntlBit, }, 3741 {Feature_HasStdExtZihintpauseBit, }, 3742 {Feature_HasStdExtZknhBit, }, 3743 {Feature_HasStdExtZksedBit, }, 3744 {Feature_HasStdExtZkshBit, }, 3745 {Feature_HasVInstructionsBit, }, 3746 {Feature_HasVInstructionsAnyFBit, }, 3747 {Feature_HasVInstructionsI64Bit, }, 3748 {Feature_HasVendorXTHeadVdotBit, }, 3749 {Feature_IsRV32Bit, }, 3750 {Feature_IsRV64Bit, }, 3751 {Feature_HasStdExtABit, Feature_IsRV64Bit, }, 3752 {Feature_HasStdExtCOrZcaBit, Feature_HasRVCHintsBit, }, 3753 {Feature_HasStdExtCOrZcaBit, Feature_IsRV32Bit, }, 3754 {Feature_HasStdExtCOrZcaBit, Feature_IsRV64Bit, }, 3755 {Feature_HasStdExtCOrZcdBit, Feature_HasStdExtDBit, }, 3756 {Feature_HasStdExtDBit, Feature_IsRV64Bit, }, 3757 {Feature_HasStdExtFBit, Feature_IsRV64Bit, }, 3758 {Feature_HasStdExtMBit, Feature_IsRV64Bit, }, 3759 {Feature_HasStdExtMOrZmmulBit, Feature_IsRV64Bit, }, 3760 {Feature_HasStdExtZbaBit, Feature_IsRV64Bit, }, 3761 {Feature_HasStdExtZbbBit, Feature_IsRV32Bit, }, 3762 {Feature_HasStdExtZbbBit, Feature_IsRV64Bit, }, 3763 {Feature_HasStdExtZbbOrZbkbBit, Feature_IsRV32Bit, }, 3764 {Feature_HasStdExtZbbOrZbkbBit, Feature_IsRV64Bit, }, 3765 {Feature_HasStdExtZbkbBit, Feature_IsRV32Bit, }, 3766 {Feature_HasStdExtZbkbBit, Feature_IsRV64Bit, }, 3767 {Feature_HasStdExtZdinxBit, Feature_IsRV32Bit, }, 3768 {Feature_HasStdExtZdinxBit, Feature_IsRV64Bit, }, 3769 {Feature_HasStdExtZfhBit, Feature_IsRV64Bit, }, 3770 {Feature_HasStdExtZfhOrZfhminBit, Feature_HasStdExtDBit, }, 3771 {Feature_HasStdExtZfinxBit, Feature_IsRV64Bit, }, 3772 {Feature_HasStdExtZhinxBit, Feature_IsRV64Bit, }, 3773 {Feature_HasStdExtZhinxOrZhinxminBit, Feature_HasStdExtZdinxBit, }, 3774 {Feature_HasStdExtZkndBit, Feature_IsRV32Bit, }, 3775 {Feature_HasStdExtZkndBit, Feature_IsRV64Bit, }, 3776 {Feature_HasStdExtZkndOrZkneBit, Feature_IsRV64Bit, }, 3777 {Feature_HasStdExtZkneBit, Feature_IsRV32Bit, }, 3778 {Feature_HasStdExtZkneBit, Feature_IsRV64Bit, }, 3779 {Feature_HasStdExtZknhBit, Feature_IsRV32Bit, }, 3780 {Feature_HasStdExtZknhBit, Feature_IsRV64Bit, }, 3781 {Feature_HasVInstructionsI64Bit, Feature_IsRV64Bit, }, 3782 {Feature_IsRV64Bit, Feature_HasStdExtHBit, }, 3783 {Feature_IsRV64Bit, Feature_HasVInstructionsI64Bit, }, 3784 {Feature_IsRV64Bit, Feature_HasVendorXVentanaCondOpsBit, }, 3785 {Feature_HasStdExtCBit, Feature_HasRVCHintsBit, Feature_HasStdExtZihintntlBit, }, 3786 {Feature_HasStdExtCOrZcfBit, Feature_HasStdExtFBit, Feature_IsRV32Bit, }, 3787}; 3788 3789namespace { 3790 struct MatchEntry { 3791 uint16_t Mnemonic; 3792 uint16_t Opcode; 3793 uint8_t ConvertFn; 3794 uint8_t RequiredFeaturesIdx; 3795 uint8_t Classes[7]; 3796 StringRef getMnemonic() const { 3797 return StringRef(MnemonicTable + Mnemonic + 1, 3798 MnemonicTable[Mnemonic]); 3799 } 3800 }; 3801 3802 // Predicate for searching for an opcode. 3803 struct LessOpcode { 3804 bool operator()(const MatchEntry &LHS, StringRef RHS) { 3805 return LHS.getMnemonic() < RHS; 3806 } 3807 bool operator()(StringRef LHS, const MatchEntry &RHS) { 3808 return LHS < RHS.getMnemonic(); 3809 } 3810 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) { 3811 return LHS.getMnemonic() < RHS.getMnemonic(); 3812 } 3813 }; 3814} // end anonymous namespace 3815 3816static const MatchEntry MatchTable0[] = { 3817 { 0 /* .insn_b */, RISCV::InsnB, Convert__InsnDirectiveOpcode1_0__UImm31_1__Reg1_2__Reg1_3__SImm13Lsb01_4, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyReg, MCK_AnyReg, MCK_SImm13Lsb0 }, }, 3818 { 8 /* .insn_i */, RISCV::InsnI, Convert__Reg1_2__InsnDirectiveOpcode1_0__UImm31_1__Reg1_3__SImm121_4, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyReg, MCK_AnyReg, MCK_SImm12 }, }, 3819 { 8 /* .insn_i */, RISCV::InsnI_Mem, Convert__Reg1_2__InsnDirectiveOpcode1_0__UImm31_1__Reg1_5__SImm121_3, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyReg, MCK_SImm12, MCK__40_, MCK_AnyReg, MCK__41_ }, }, 3820 { 16 /* .insn_j */, RISCV::InsnJ, Convert__Reg1_1__InsnDirectiveOpcode1_0__SImm21Lsb0JAL1_2, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_AnyReg, MCK_SImm21Lsb0JAL }, }, 3821 { 24 /* .insn_r */, RISCV::InsnR, Convert__Reg1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm71_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm7, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg }, }, 3822 { 24 /* .insn_r */, RISCV::InsnR4, Convert__Reg1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__Reg1_4__Reg1_5__Reg1_6, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg }, }, 3823 { 32 /* .insn_r4 */, RISCV::InsnR4, Convert__Reg1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__Reg1_4__Reg1_5__Reg1_6, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg }, }, 3824 { 41 /* .insn_s */, RISCV::InsnS, Convert__InsnDirectiveOpcode1_0__UImm31_1__Reg1_2__Reg1_5__SImm121_3, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyReg, MCK_SImm12, MCK__40_, MCK_AnyReg, MCK__41_ }, }, 3825 { 49 /* .insn_sb */, RISCV::InsnB, Convert__InsnDirectiveOpcode1_0__UImm31_1__Reg1_2__Reg1_3__SImm13Lsb01_4, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyReg, MCK_AnyReg, MCK_SImm13Lsb0 }, }, 3826 { 58 /* .insn_u */, RISCV::InsnU, Convert__Reg1_1__InsnDirectiveOpcode1_0__UImm20LUI1_2, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_AnyReg, MCK_UImm20LUI }, }, 3827 { 66 /* .insn_uj */, RISCV::InsnJ, Convert__Reg1_1__InsnDirectiveOpcode1_0__SImm21Lsb0JAL1_2, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_AnyReg, MCK_SImm21Lsb0JAL }, }, 3828 { 75 /* add */, RISCV::ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 3829 { 75 /* add */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 3830 { 75 /* add */, RISCV::PseudoAddTPRel, Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_TPRelAddSymbol }, }, 3831 { 79 /* add.uw */, RISCV::ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 3832 { 86 /* addi */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 3833 { 91 /* addiw */, RISCV::ADDIW, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 3834 { 97 /* addw */, RISCV::ADDW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 3835 { 97 /* addw */, RISCV::ADDIW, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 3836 { 102 /* aes32dsi */, RISCV::AES32DSI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZknd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, }, 3837 { 111 /* aes32dsmi */, RISCV::AES32DSMI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZknd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, }, 3838 { 121 /* aes32esi */, RISCV::AES32ESI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZkne_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, }, 3839 { 130 /* aes32esmi */, RISCV::AES32ESMI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZkne_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, }, 3840 { 140 /* aes64ds */, RISCV::AES64DS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknd_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 3841 { 148 /* aes64dsm */, RISCV::AES64DSM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknd_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 3842 { 157 /* aes64es */, RISCV::AES64ES, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 3843 { 165 /* aes64esm */, RISCV::AES64ESM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 3844 { 174 /* aes64im */, RISCV::AES64IM, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknd_IsRV64, { MCK_GPR, MCK_GPR }, }, 3845 { 182 /* aes64ks1i */, RISCV::AES64KS1I, Convert__Reg1_0__Reg1_1__RnumArg1_2, AMFBS_HasStdExtZkndOrZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_RnumArg }, }, 3846 { 192 /* aes64ks2 */, RISCV::AES64KS2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZkndOrZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 3847 { 201 /* amoadd.d */, RISCV::AMOADD_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3848 { 210 /* amoadd.d.aq */, RISCV::AMOADD_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3849 { 222 /* amoadd.d.aqrl */, RISCV::AMOADD_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3850 { 236 /* amoadd.d.rl */, RISCV::AMOADD_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3851 { 248 /* amoadd.w */, RISCV::AMOADD_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3852 { 257 /* amoadd.w.aq */, RISCV::AMOADD_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3853 { 269 /* amoadd.w.aqrl */, RISCV::AMOADD_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3854 { 283 /* amoadd.w.rl */, RISCV::AMOADD_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3855 { 295 /* amoand.d */, RISCV::AMOAND_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3856 { 304 /* amoand.d.aq */, RISCV::AMOAND_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3857 { 316 /* amoand.d.aqrl */, RISCV::AMOAND_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3858 { 330 /* amoand.d.rl */, RISCV::AMOAND_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3859 { 342 /* amoand.w */, RISCV::AMOAND_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3860 { 351 /* amoand.w.aq */, RISCV::AMOAND_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3861 { 363 /* amoand.w.aqrl */, RISCV::AMOAND_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3862 { 377 /* amoand.w.rl */, RISCV::AMOAND_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3863 { 389 /* amomax.d */, RISCV::AMOMAX_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3864 { 398 /* amomax.d.aq */, RISCV::AMOMAX_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3865 { 410 /* amomax.d.aqrl */, RISCV::AMOMAX_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3866 { 424 /* amomax.d.rl */, RISCV::AMOMAX_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3867 { 436 /* amomax.w */, RISCV::AMOMAX_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3868 { 445 /* amomax.w.aq */, RISCV::AMOMAX_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3869 { 457 /* amomax.w.aqrl */, RISCV::AMOMAX_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3870 { 471 /* amomax.w.rl */, RISCV::AMOMAX_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3871 { 483 /* amomaxu.d */, RISCV::AMOMAXU_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3872 { 493 /* amomaxu.d.aq */, RISCV::AMOMAXU_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3873 { 506 /* amomaxu.d.aqrl */, RISCV::AMOMAXU_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3874 { 521 /* amomaxu.d.rl */, RISCV::AMOMAXU_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3875 { 534 /* amomaxu.w */, RISCV::AMOMAXU_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3876 { 544 /* amomaxu.w.aq */, RISCV::AMOMAXU_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3877 { 557 /* amomaxu.w.aqrl */, RISCV::AMOMAXU_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3878 { 572 /* amomaxu.w.rl */, RISCV::AMOMAXU_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3879 { 585 /* amomin.d */, RISCV::AMOMIN_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3880 { 594 /* amomin.d.aq */, RISCV::AMOMIN_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3881 { 606 /* amomin.d.aqrl */, RISCV::AMOMIN_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3882 { 620 /* amomin.d.rl */, RISCV::AMOMIN_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3883 { 632 /* amomin.w */, RISCV::AMOMIN_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3884 { 641 /* amomin.w.aq */, RISCV::AMOMIN_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3885 { 653 /* amomin.w.aqrl */, RISCV::AMOMIN_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3886 { 667 /* amomin.w.rl */, RISCV::AMOMIN_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3887 { 679 /* amominu.d */, RISCV::AMOMINU_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3888 { 689 /* amominu.d.aq */, RISCV::AMOMINU_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3889 { 702 /* amominu.d.aqrl */, RISCV::AMOMINU_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3890 { 717 /* amominu.d.rl */, RISCV::AMOMINU_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3891 { 730 /* amominu.w */, RISCV::AMOMINU_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3892 { 740 /* amominu.w.aq */, RISCV::AMOMINU_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3893 { 753 /* amominu.w.aqrl */, RISCV::AMOMINU_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3894 { 768 /* amominu.w.rl */, RISCV::AMOMINU_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3895 { 781 /* amoor.d */, RISCV::AMOOR_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3896 { 789 /* amoor.d.aq */, RISCV::AMOOR_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3897 { 800 /* amoor.d.aqrl */, RISCV::AMOOR_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3898 { 813 /* amoor.d.rl */, RISCV::AMOOR_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3899 { 824 /* amoor.w */, RISCV::AMOOR_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3900 { 832 /* amoor.w.aq */, RISCV::AMOOR_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3901 { 843 /* amoor.w.aqrl */, RISCV::AMOOR_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3902 { 856 /* amoor.w.rl */, RISCV::AMOOR_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3903 { 867 /* amoswap.d */, RISCV::AMOSWAP_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3904 { 877 /* amoswap.d.aq */, RISCV::AMOSWAP_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3905 { 890 /* amoswap.d.aqrl */, RISCV::AMOSWAP_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3906 { 905 /* amoswap.d.rl */, RISCV::AMOSWAP_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3907 { 918 /* amoswap.w */, RISCV::AMOSWAP_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3908 { 928 /* amoswap.w.aq */, RISCV::AMOSWAP_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3909 { 941 /* amoswap.w.aqrl */, RISCV::AMOSWAP_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3910 { 956 /* amoswap.w.rl */, RISCV::AMOSWAP_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3911 { 969 /* amoxor.d */, RISCV::AMOXOR_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3912 { 978 /* amoxor.d.aq */, RISCV::AMOXOR_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3913 { 990 /* amoxor.d.aqrl */, RISCV::AMOXOR_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3914 { 1004 /* amoxor.d.rl */, RISCV::AMOXOR_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3915 { 1016 /* amoxor.w */, RISCV::AMOXOR_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3916 { 1025 /* amoxor.w.aq */, RISCV::AMOXOR_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3917 { 1037 /* amoxor.w.aqrl */, RISCV::AMOXOR_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3918 { 1051 /* amoxor.w.rl */, RISCV::AMOXOR_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 3919 { 1063 /* and */, RISCV::AND, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 3920 { 1063 /* and */, RISCV::ANDI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 3921 { 1067 /* andi */, RISCV::ANDI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 3922 { 1072 /* andn */, RISCV::ANDN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 3923 { 1077 /* auipc */, RISCV::AUIPC, Convert__Reg1_0__UImm20AUIPC1_1, AMFBS_None, { MCK_GPR, MCK_UImm20AUIPC }, }, 3924 { 1083 /* bclr */, RISCV::BCLR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 3925 { 1083 /* bclr */, RISCV::BCLRI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 3926 { 1088 /* bclri */, RISCV::BCLRI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 3927 { 1094 /* beq */, RISCV::BEQ, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, }, 3928 { 1098 /* beqz */, RISCV::BEQ, Convert__Reg1_0__regX0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, }, 3929 { 1103 /* bext */, RISCV::BEXT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 3930 { 1103 /* bext */, RISCV::BEXTI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 3931 { 1108 /* bexti */, RISCV::BEXTI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 3932 { 1114 /* bge */, RISCV::BGE, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, }, 3933 { 1118 /* bgeu */, RISCV::BGEU, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, }, 3934 { 1123 /* bgez */, RISCV::BGE, Convert__Reg1_0__regX0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, }, 3935 { 1128 /* bgt */, RISCV::BLT, Convert__Reg1_1__Reg1_0__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, }, 3936 { 1132 /* bgtu */, RISCV::BLTU, Convert__Reg1_1__Reg1_0__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, }, 3937 { 1137 /* bgtz */, RISCV::BLT, Convert__regX0__Reg1_0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, }, 3938 { 1142 /* binv */, RISCV::BINV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 3939 { 1142 /* binv */, RISCV::BINVI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 3940 { 1147 /* binvi */, RISCV::BINVI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 3941 { 1153 /* ble */, RISCV::BGE, Convert__Reg1_1__Reg1_0__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, }, 3942 { 1157 /* bleu */, RISCV::BGEU, Convert__Reg1_1__Reg1_0__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, }, 3943 { 1162 /* blez */, RISCV::BGE, Convert__regX0__Reg1_0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, }, 3944 { 1167 /* blt */, RISCV::BLT, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, }, 3945 { 1171 /* bltu */, RISCV::BLTU, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, }, 3946 { 1176 /* bltz */, RISCV::BLT, Convert__Reg1_0__regX0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, }, 3947 { 1181 /* bne */, RISCV::BNE, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, }, 3948 { 1185 /* bnez */, RISCV::BNE, Convert__Reg1_0__regX0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, }, 3949 { 1190 /* brev8 */, RISCV::BREV8, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbkb, { MCK_GPR, MCK_GPR }, }, 3950 { 1196 /* bset */, RISCV::BSET, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 3951 { 1196 /* bset */, RISCV::BSETI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 3952 { 1201 /* bseti */, RISCV::BSETI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 3953 { 1207 /* c.add */, RISCV::C_ADD_HINT, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtCOrZca_HasRVCHints, { MCK_GPRX0, MCK_GPRNoX0 }, }, 3954 { 1207 /* c.add */, RISCV::C_ADD, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRNoX0, MCK_GPRNoX0 }, }, 3955 { 1213 /* c.addi */, RISCV::C_ADDI_NOP, Convert__Reg1_0__Tie0_1_1__ImmZero1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRX0, MCK_ImmZero }, }, 3956 { 1213 /* c.addi */, RISCV::C_ADDI_HINT_X0, Convert__Reg1_0__Tie0_1_1__SImm6NonZero1_1, AMFBS_HasStdExtCOrZca_HasRVCHints, { MCK_GPRX0, MCK_SImm6NonZero }, }, 3957 { 1213 /* c.addi */, RISCV::C_ADDI_HINT_IMM_ZERO, Convert__Reg1_0__Tie0_1_1__ImmZero1_1, AMFBS_HasStdExtCOrZca_HasRVCHints, { MCK_GPRNoX0, MCK_ImmZero }, }, 3958 { 1213 /* c.addi */, RISCV::C_ADDI, Convert__Reg1_0__Tie0_1_1__SImm6NonZero1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRNoX0, MCK_SImm6NonZero }, }, 3959 { 1220 /* c.addi16sp */, RISCV::C_ADDI16SP, Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1, AMFBS_HasStdExtCOrZca, { MCK_SP, MCK_SImm10Lsb0000NonZero }, }, 3960 { 1231 /* c.addi4spn */, RISCV::C_ADDI4SPN, Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_SP, MCK_UImm10Lsb00NonZero }, }, 3961 { 1242 /* c.addiw */, RISCV::C_ADDIW, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtCOrZca_IsRV64, { MCK_GPRNoX0, MCK_SImm6 }, }, 3962 { 1250 /* c.addw */, RISCV::C_ADDW, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtCOrZca_IsRV64, { MCK_GPRC, MCK_GPRC }, }, 3963 { 1257 /* c.and */, RISCV::C_AND, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_GPRC }, }, 3964 { 1263 /* c.andi */, RISCV::C_ANDI, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_SImm6 }, }, 3965 { 1270 /* c.beqz */, RISCV::C_BEQZ, Convert__Reg1_0__SImm9Lsb01_1, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_SImm9Lsb0 }, }, 3966 { 1277 /* c.bnez */, RISCV::C_BNEZ, Convert__Reg1_0__SImm9Lsb01_1, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_SImm9Lsb0 }, }, 3967 { 1284 /* c.ebreak */, RISCV::C_EBREAK, Convert_NoOperands, AMFBS_HasStdExtCOrZca, { }, }, 3968 { 1293 /* c.fld */, RISCV::C_FLD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64C, MCK__40_, MCK_GPRC, MCK__41_ }, }, 3969 { 1293 /* c.fld */, RISCV::C_FLD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64C, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, }, 3970 { 1299 /* c.fldsp */, RISCV::C_FLDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64C, MCK__40_, MCK_SP, MCK__41_ }, }, 3971 { 1299 /* c.fldsp */, RISCV::C_FLDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, }, 3972 { 1307 /* c.flw */, RISCV::C_FLW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcf_HasStdExtF_IsRV32, { MCK_FPR32C, MCK__40_, MCK_GPRC, MCK__41_ }, }, 3973 { 1307 /* c.flw */, RISCV::C_FLW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtCOrZcf_HasStdExtF_IsRV32, { MCK_FPR32C, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, }, 3974 { 1313 /* c.flwsp */, RISCV::C_FLWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcf_HasStdExtF_IsRV32, { MCK_FPR32C, MCK__40_, MCK_SP, MCK__41_ }, }, 3975 { 1313 /* c.flwsp */, RISCV::C_FLWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtCOrZcf_HasStdExtF_IsRV32, { MCK_FPR32, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, }, 3976 { 1321 /* c.fsd */, RISCV::C_FSD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64C, MCK__40_, MCK_GPRC, MCK__41_ }, }, 3977 { 1321 /* c.fsd */, RISCV::C_FSD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64C, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, }, 3978 { 1327 /* c.fsdsp */, RISCV::C_FSDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64C, MCK__40_, MCK_SP, MCK__41_ }, }, 3979 { 1327 /* c.fsdsp */, RISCV::C_FSDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, }, 3980 { 1335 /* c.fsw */, RISCV::C_FSW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcf_HasStdExtF_IsRV32, { MCK_FPR32C, MCK__40_, MCK_GPRC, MCK__41_ }, }, 3981 { 1335 /* c.fsw */, RISCV::C_FSW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtCOrZcf_HasStdExtF_IsRV32, { MCK_FPR32C, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, }, 3982 { 1341 /* c.fswsp */, RISCV::C_FSWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcf_HasStdExtF_IsRV32, { MCK_FPR32C, MCK__40_, MCK_SP, MCK__41_ }, }, 3983 { 1341 /* c.fswsp */, RISCV::C_FSWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtCOrZcf_HasStdExtF_IsRV32, { MCK_FPR32, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, }, 3984 { 1349 /* c.j */, RISCV::C_J, Convert__SImm12Lsb01_0, AMFBS_HasStdExtCOrZca, { MCK_SImm12Lsb0 }, }, 3985 { 1353 /* c.jal */, RISCV::C_JAL, Convert__SImm12Lsb01_0, AMFBS_HasStdExtCOrZca_IsRV32, { MCK_SImm12Lsb0 }, }, 3986 { 1359 /* c.jalr */, RISCV::C_JALR, Convert__Reg1_0, AMFBS_HasStdExtCOrZca, { MCK_GPRNoX0 }, }, 3987 { 1366 /* c.jr */, RISCV::C_JR, Convert__Reg1_0, AMFBS_HasStdExtCOrZca, { MCK_GPRNoX0 }, }, 3988 { 1371 /* c.ld */, RISCV::C_LD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZca_IsRV64, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, }, 3989 { 1371 /* c.ld */, RISCV::C_LD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtCOrZca_IsRV64, { MCK_GPRC, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, }, 3990 { 1376 /* c.ldsp */, RISCV::C_LDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZca_IsRV64, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, }, 3991 { 1376 /* c.ldsp */, RISCV::C_LDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtCOrZca_IsRV64, { MCK_GPRNoX0, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, }, 3992 { 1383 /* c.li */, RISCV::C_LI_HINT, Convert__Reg1_0__SImm61_1, AMFBS_HasStdExtCOrZca_HasRVCHints, { MCK_GPRX0, MCK_SImm6 }, }, 3993 { 1383 /* c.li */, RISCV::C_LI, Convert__Reg1_0__SImm61_1, AMFBS_HasStdExtCOrZca, { MCK_GPRNoX0, MCK_SImm6 }, }, 3994 { 1388 /* c.lui */, RISCV::C_LUI_HINT, Convert__Reg1_0__CLUIImm1_1, AMFBS_HasStdExtCOrZca_HasRVCHints, { MCK_GPRX0, MCK_CLUIImm }, }, 3995 { 1388 /* c.lui */, RISCV::C_LUI, Convert__Reg1_0__CLUIImm1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRNoX0X2, MCK_CLUIImm }, }, 3996 { 1394 /* c.lw */, RISCV::C_LW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, }, 3997 { 1394 /* c.lw */, RISCV::C_LW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, }, 3998 { 1399 /* c.lwsp */, RISCV::C_LWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, }, 3999 { 1399 /* c.lwsp */, RISCV::C_LWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtCOrZca, { MCK_GPRNoX0, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, }, 4000 { 1406 /* c.mv */, RISCV::C_MV_HINT, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtCOrZca_HasRVCHints, { MCK_GPRX0, MCK_GPRNoX0 }, }, 4001 { 1406 /* c.mv */, RISCV::C_MV, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRNoX0, MCK_GPRNoX0 }, }, 4002 { 1411 /* c.nop */, RISCV::C_NOP, Convert_NoOperands, AMFBS_HasStdExtCOrZca, { }, }, 4003 { 1411 /* c.nop */, RISCV::C_NOP_HINT, Convert__SImm6NonZero1_0, AMFBS_HasStdExtCOrZca_HasRVCHints, { MCK_SImm6NonZero }, }, 4004 { 1417 /* c.ntl.all */, RISCV::C_ADD_HINT, Convert__regX0__Tie0_1_1__regX5, AMFBS_HasStdExtC_HasRVCHints_HasStdExtZihintntl, { }, }, 4005 { 1427 /* c.ntl.p1 */, RISCV::C_ADD_HINT, Convert__regX0__Tie0_1_1__regX2, AMFBS_HasStdExtC_HasRVCHints_HasStdExtZihintntl, { }, }, 4006 { 1436 /* c.ntl.pall */, RISCV::C_ADD_HINT, Convert__regX0__Tie0_1_1__regX3, AMFBS_HasStdExtC_HasRVCHints_HasStdExtZihintntl, { }, }, 4007 { 1447 /* c.ntl.s1 */, RISCV::C_ADD_HINT, Convert__regX0__Tie0_1_1__regX4, AMFBS_HasStdExtC_HasRVCHints_HasStdExtZihintntl, { }, }, 4008 { 1456 /* c.or */, RISCV::C_OR, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_GPRC }, }, 4009 { 1461 /* c.sd */, RISCV::C_SD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZca_IsRV64, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, }, 4010 { 1461 /* c.sd */, RISCV::C_SD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtCOrZca_IsRV64, { MCK_GPRC, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, }, 4011 { 1466 /* c.sdsp */, RISCV::C_SDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZca_IsRV64, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, }, 4012 { 1466 /* c.sdsp */, RISCV::C_SDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtCOrZca_IsRV64, { MCK_GPR, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, }, 4013 { 1473 /* c.slli */, RISCV::C_SLLI_HINT, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasStdExtCOrZca_HasRVCHints, { MCK_GPRX0, MCK_UImmLog2XLenNonZero }, }, 4014 { 1473 /* c.slli */, RISCV::C_SLLI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRNoX0, MCK_UImmLog2XLenNonZero }, }, 4015 { 1480 /* c.slli64 */, RISCV::C_SLLI64_HINT, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtCOrZca_HasRVCHints, { MCK_GPR }, }, 4016 { 1489 /* c.srai */, RISCV::C_SRAI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_UImmLog2XLenNonZero }, }, 4017 { 1496 /* c.srai64 */, RISCV::C_SRAI64_HINT, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtCOrZca_HasRVCHints, { MCK_GPRC }, }, 4018 { 1505 /* c.srli */, RISCV::C_SRLI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_UImmLog2XLenNonZero }, }, 4019 { 1512 /* c.srli64 */, RISCV::C_SRLI64_HINT, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtCOrZca_HasRVCHints, { MCK_GPRC }, }, 4020 { 1521 /* c.sub */, RISCV::C_SUB, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_GPRC }, }, 4021 { 1527 /* c.subw */, RISCV::C_SUBW, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtCOrZca_IsRV64, { MCK_GPRC, MCK_GPRC }, }, 4022 { 1534 /* c.sw */, RISCV::C_SW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, }, 4023 { 1534 /* c.sw */, RISCV::C_SW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, }, 4024 { 1539 /* c.swsp */, RISCV::C_SWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, }, 4025 { 1539 /* c.swsp */, RISCV::C_SWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtCOrZca, { MCK_GPR, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, }, 4026 { 1546 /* c.unimp */, RISCV::C_UNIMP, Convert_NoOperands, AMFBS_HasStdExtCOrZca, { }, }, 4027 { 1554 /* c.xor */, RISCV::C_XOR, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_GPRC }, }, 4028 { 1560 /* call */, RISCV::PseudoCALL, Convert__CallSymbol1_0, AMFBS_None, { MCK_CallSymbol }, }, 4029 { 1560 /* call */, RISCV::PseudoCALLReg, Convert__Reg1_0__CallSymbol1_1, AMFBS_None, { MCK_GPR, MCK_CallSymbol }, }, 4030 { 1565 /* cbo.clean */, RISCV::CBO_CLEAN, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicbom, { MCK_ZeroOffsetMemOpOperand }, }, 4031 { 1575 /* cbo.flush */, RISCV::CBO_FLUSH, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicbom, { MCK_ZeroOffsetMemOpOperand }, }, 4032 { 1585 /* cbo.inval */, RISCV::CBO_INVAL, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicbom, { MCK_ZeroOffsetMemOpOperand }, }, 4033 { 1595 /* cbo.zero */, RISCV::CBO_ZERO, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicboz, { MCK_ZeroOffsetMemOpOperand }, }, 4034 { 1604 /* clmul */, RISCV::CLMUL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbcOrZbkc, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4035 { 1610 /* clmulh */, RISCV::CLMULH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbcOrZbkc, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4036 { 1617 /* clmulr */, RISCV::CLMULR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbc, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4037 { 1624 /* clz */, RISCV::CLZ, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, }, 4038 { 1628 /* clzw */, RISCV::CLZW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, }, 4039 { 1633 /* cpop */, RISCV::CPOP, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, }, 4040 { 1638 /* cpopw */, RISCV::CPOPW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, }, 4041 { 1644 /* csrc */, RISCV::CSRRC, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, }, 4042 { 1644 /* csrc */, RISCV::CSRRCI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, }, 4043 { 1649 /* csrci */, RISCV::CSRRCI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, }, 4044 { 1655 /* csrr */, RISCV::CSRRS, Convert__Reg1_0__CSRSystemRegister1_1__regX0, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister }, }, 4045 { 1660 /* csrrc */, RISCV::CSRRC, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, }, 4046 { 1660 /* csrrc */, RISCV::CSRRCI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, }, 4047 { 1666 /* csrrci */, RISCV::CSRRCI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, }, 4048 { 1673 /* csrrs */, RISCV::CSRRS, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, }, 4049 { 1673 /* csrrs */, RISCV::CSRRSI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, }, 4050 { 1679 /* csrrsi */, RISCV::CSRRSI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, }, 4051 { 1686 /* csrrw */, RISCV::CSRRW, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, }, 4052 { 1686 /* csrrw */, RISCV::CSRRWI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, }, 4053 { 1692 /* csrrwi */, RISCV::CSRRWI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, }, 4054 { 1699 /* csrs */, RISCV::CSRRS, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, }, 4055 { 1699 /* csrs */, RISCV::CSRRSI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, }, 4056 { 1704 /* csrsi */, RISCV::CSRRSI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, }, 4057 { 1710 /* csrw */, RISCV::CSRRW, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, }, 4058 { 1710 /* csrw */, RISCV::CSRRWI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, }, 4059 { 1715 /* csrwi */, RISCV::CSRRWI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, }, 4060 { 1721 /* ctz */, RISCV::CTZ, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, }, 4061 { 1725 /* ctzw */, RISCV::CTZW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, }, 4062 { 1730 /* div */, RISCV::DIV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4063 { 1734 /* divu */, RISCV::DIVU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4064 { 1739 /* divuw */, RISCV::DIVUW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4065 { 1745 /* divw */, RISCV::DIVW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4066 { 1750 /* dret */, RISCV::DRET, Convert__imm_95_0__imm_95_0, AMFBS_None, { }, }, 4067 { 1755 /* ebreak */, RISCV::EBREAK, Convert_NoOperands, AMFBS_None, { }, }, 4068 { 1762 /* ecall */, RISCV::ECALL, Convert_NoOperands, AMFBS_None, { }, }, 4069 { 1768 /* fabs.d */, RISCV::FSGNJX_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, }, 4070 { 1768 /* fabs.d */, RISCV::FSGNJX_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, }, 4071 { 1768 /* fabs.d */, RISCV::FSGNJX_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR }, }, 4072 { 1775 /* fabs.h */, RISCV::FSGNJX_H, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16 }, }, 4073 { 1775 /* fabs.h */, RISCV::FSGNJX_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_1, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4074 { 1782 /* fabs.s */, RISCV::FSGNJX_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, }, 4075 { 1782 /* fabs.s */, RISCV::FSGNJX_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_1, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4076 { 1789 /* fadd.d */, RISCV::FADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 4077 { 1789 /* fadd.d */, RISCV::FADD_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__imm_95_7, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, }, 4078 { 1789 /* fadd.d */, RISCV::FADD_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__imm_95_7, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR }, }, 4079 { 1789 /* fadd.d */, RISCV::FADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, }, 4080 { 1789 /* fadd.d */, RISCV::FADD_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, }, 4081 { 1789 /* fadd.d */, RISCV::FADD_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_FRMArg }, }, 4082 { 1796 /* fadd.h */, RISCV::FADD_H, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, }, 4083 { 1796 /* fadd.h */, RISCV::FADD_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__imm_95_7, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4084 { 1796 /* fadd.h */, RISCV::FADD_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, }, 4085 { 1796 /* fadd.h */, RISCV::FADD_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4086 { 1803 /* fadd.s */, RISCV::FADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 4087 { 1803 /* fadd.s */, RISCV::FADD_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__imm_95_7, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4088 { 1803 /* fadd.s */, RISCV::FADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, }, 4089 { 1803 /* fadd.s */, RISCV::FADD_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4090 { 1810 /* fclass.d */, RISCV::FCLASS_D, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64 }, }, 4091 { 1810 /* fclass.d */, RISCV::FCLASS_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR }, }, 4092 { 1810 /* fclass.d */, RISCV::FCLASS_D_IN32X, Convert__Reg1_0__GPRPF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPF64AsFPR }, }, 4093 { 1819 /* fclass.h */, RISCV::FCLASS_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16 }, }, 4094 { 1819 /* fclass.h */, RISCV::FCLASS_H_INX, Convert__Reg1_0__GPRAsFPR1_1, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR }, }, 4095 { 1828 /* fclass.s */, RISCV::FCLASS_S, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32 }, }, 4096 { 1828 /* fclass.s */, RISCV::FCLASS_S_INX, Convert__Reg1_0__GPRAsFPR1_1, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR }, }, 4097 { 1837 /* fcvt.d.h */, RISCV::FCVT_D_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZfhOrZfhmin_HasStdExtD, { MCK_FPR64, MCK_FPR16 }, }, 4098 { 1837 /* fcvt.d.h */, RISCV::FCVT_D_H_INX, Convert__GPRF64AsFPR1_0__GPRAsFPR1_1, AMFBS_HasStdExtZhinxOrZhinxmin_HasStdExtZdinx, { MCK_GPRF64AsFPR, MCK_GPRAsFPR }, }, 4099 { 1846 /* fcvt.d.l */, RISCV::FCVT_D_L, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR }, }, 4100 { 1846 /* fcvt.d.l */, RISCV::FCVT_D_L_INX, Convert__GPRF64AsFPR1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR }, }, 4101 { 1846 /* fcvt.d.l */, RISCV::FCVT_D_L, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_FRMArg }, }, 4102 { 1846 /* fcvt.d.l */, RISCV::FCVT_D_L_INX, Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR, MCK_FRMArg }, }, 4103 { 1855 /* fcvt.d.lu */, RISCV::FCVT_D_LU, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR }, }, 4104 { 1855 /* fcvt.d.lu */, RISCV::FCVT_D_LU_INX, Convert__GPRF64AsFPR1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR }, }, 4105 { 1855 /* fcvt.d.lu */, RISCV::FCVT_D_LU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_FRMArg }, }, 4106 { 1855 /* fcvt.d.lu */, RISCV::FCVT_D_LU_INX, Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR, MCK_FRMArg }, }, 4107 { 1865 /* fcvt.d.s */, RISCV::FCVT_D_S, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR32 }, }, 4108 { 1865 /* fcvt.d.s */, RISCV::FCVT_D_S_INX, Convert__GPRF64AsFPR1_0__GPRAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRAsFPR }, }, 4109 { 1865 /* fcvt.d.s */, RISCV::FCVT_D_S_IN32X, Convert__GPRPF64AsFPR1_0__GPRAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRAsFPR }, }, 4110 { 1874 /* fcvt.d.w */, RISCV::FCVT_D_W, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_GPR }, }, 4111 { 1874 /* fcvt.d.w */, RISCV::FCVT_D_W_INX, Convert__GPRF64AsFPR1_0__Reg1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR }, }, 4112 { 1874 /* fcvt.d.w */, RISCV::FCVT_D_W_IN32X, Convert__GPRPF64AsFPR1_0__Reg1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPR }, }, 4113 { 1883 /* fcvt.d.wu */, RISCV::FCVT_D_WU, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_GPR }, }, 4114 { 1883 /* fcvt.d.wu */, RISCV::FCVT_D_WU_INX, Convert__GPRF64AsFPR1_0__Reg1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR }, }, 4115 { 1883 /* fcvt.d.wu */, RISCV::FCVT_D_WU_IN32X, Convert__GPRPF64AsFPR1_0__Reg1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPR }, }, 4116 { 1893 /* fcvt.h.d */, RISCV::FCVT_H_D, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtZfhOrZfhmin_HasStdExtD, { MCK_FPR16, MCK_FPR64 }, }, 4117 { 1893 /* fcvt.h.d */, RISCV::FCVT_H_D_INX, Convert__GPRAsFPR1_0__GPRF64AsFPR1_1__imm_95_7, AMFBS_HasStdExtZhinxOrZhinxmin_HasStdExtZdinx, { MCK_GPRAsFPR, MCK_GPRF64AsFPR }, }, 4118 { 1893 /* fcvt.h.d */, RISCV::FCVT_H_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfhOrZfhmin_HasStdExtD, { MCK_FPR16, MCK_FPR64, MCK_FRMArg }, }, 4119 { 1893 /* fcvt.h.d */, RISCV::FCVT_H_D_INX, Convert__GPRAsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZhinxOrZhinxmin_HasStdExtZdinx, { MCK_GPRAsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, }, 4120 { 1902 /* fcvt.h.l */, RISCV::FCVT_H_L, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtZfh_IsRV64, { MCK_FPR16, MCK_GPR }, }, 4121 { 1902 /* fcvt.h.l */, RISCV::FCVT_H_L_INX, Convert__GPRAsFPR1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPRAsFPR, MCK_GPR }, }, 4122 { 1902 /* fcvt.h.l */, RISCV::FCVT_H_L, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, }, 4123 { 1902 /* fcvt.h.l */, RISCV::FCVT_H_L_INX, Convert__GPRAsFPR1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPRAsFPR, MCK_GPR, MCK_FRMArg }, }, 4124 { 1911 /* fcvt.h.lu */, RISCV::FCVT_H_LU, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtZfh_IsRV64, { MCK_FPR16, MCK_GPR }, }, 4125 { 1911 /* fcvt.h.lu */, RISCV::FCVT_H_LU_INX, Convert__GPRAsFPR1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPRAsFPR, MCK_GPR }, }, 4126 { 1911 /* fcvt.h.lu */, RISCV::FCVT_H_LU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, }, 4127 { 1911 /* fcvt.h.lu */, RISCV::FCVT_H_LU_INX, Convert__GPRAsFPR1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPRAsFPR, MCK_GPR, MCK_FRMArg }, }, 4128 { 1921 /* fcvt.h.s */, RISCV::FCVT_H_S, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtZfhOrZfhmin, { MCK_FPR16, MCK_FPR32 }, }, 4129 { 1921 /* fcvt.h.s */, RISCV::FCVT_H_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__imm_95_7, AMFBS_HasStdExtZhinxOrZhinxmin, { MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4130 { 1921 /* fcvt.h.s */, RISCV::FCVT_H_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfhOrZfhmin, { MCK_FPR16, MCK_FPR32, MCK_FRMArg }, }, 4131 { 1921 /* fcvt.h.s */, RISCV::FCVT_H_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZhinxOrZhinxmin, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4132 { 1930 /* fcvt.h.w */, RISCV::FCVT_H_W, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_GPR }, }, 4133 { 1930 /* fcvt.h.w */, RISCV::FCVT_H_W_INX, Convert__GPRAsFPR1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPR }, }, 4134 { 1930 /* fcvt.h.w */, RISCV::FCVT_H_W, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, }, 4135 { 1930 /* fcvt.h.w */, RISCV::FCVT_H_W_INX, Convert__GPRAsFPR1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPR, MCK_FRMArg }, }, 4136 { 1939 /* fcvt.h.wu */, RISCV::FCVT_H_WU, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_GPR }, }, 4137 { 1939 /* fcvt.h.wu */, RISCV::FCVT_H_WU_INX, Convert__GPRAsFPR1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPR }, }, 4138 { 1939 /* fcvt.h.wu */, RISCV::FCVT_H_WU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, }, 4139 { 1939 /* fcvt.h.wu */, RISCV::FCVT_H_WU_INX, Convert__GPRAsFPR1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPR, MCK_FRMArg }, }, 4140 { 1949 /* fcvt.l.d */, RISCV::FCVT_L_D, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64 }, }, 4141 { 1949 /* fcvt.l.d */, RISCV::FCVT_L_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__imm_95_7, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR }, }, 4142 { 1949 /* fcvt.l.d */, RISCV::FCVT_L_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, }, 4143 { 1949 /* fcvt.l.d */, RISCV::FCVT_L_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, }, 4144 { 1958 /* fcvt.l.h */, RISCV::FCVT_L_H, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtZfh_IsRV64, { MCK_GPR, MCK_FPR16 }, }, 4145 { 1958 /* fcvt.l.h */, RISCV::FCVT_L_H_INX, Convert__Reg1_0__GPRAsFPR1_1__imm_95_7, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR }, }, 4146 { 1958 /* fcvt.l.h */, RISCV::FCVT_L_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, }, 4147 { 1958 /* fcvt.l.h */, RISCV::FCVT_L_H_INX, Convert__Reg1_0__GPRAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4148 { 1967 /* fcvt.l.s */, RISCV::FCVT_L_S, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF_IsRV64, { MCK_GPR, MCK_FPR32 }, }, 4149 { 1967 /* fcvt.l.s */, RISCV::FCVT_L_S_INX, Convert__Reg1_0__GPRAsFPR1_1__imm_95_7, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR }, }, 4150 { 1967 /* fcvt.l.s */, RISCV::FCVT_L_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, }, 4151 { 1967 /* fcvt.l.s */, RISCV::FCVT_L_S_INX, Convert__Reg1_0__GPRAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4152 { 1976 /* fcvt.lu.d */, RISCV::FCVT_LU_D, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64 }, }, 4153 { 1976 /* fcvt.lu.d */, RISCV::FCVT_LU_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__imm_95_7, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR }, }, 4154 { 1976 /* fcvt.lu.d */, RISCV::FCVT_LU_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, }, 4155 { 1976 /* fcvt.lu.d */, RISCV::FCVT_LU_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, }, 4156 { 1986 /* fcvt.lu.h */, RISCV::FCVT_LU_H, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtZfh_IsRV64, { MCK_GPR, MCK_FPR16 }, }, 4157 { 1986 /* fcvt.lu.h */, RISCV::FCVT_LU_H_INX, Convert__Reg1_0__GPRAsFPR1_1__imm_95_7, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR }, }, 4158 { 1986 /* fcvt.lu.h */, RISCV::FCVT_LU_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, }, 4159 { 1986 /* fcvt.lu.h */, RISCV::FCVT_LU_H_INX, Convert__Reg1_0__GPRAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4160 { 1996 /* fcvt.lu.s */, RISCV::FCVT_LU_S, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF_IsRV64, { MCK_GPR, MCK_FPR32 }, }, 4161 { 1996 /* fcvt.lu.s */, RISCV::FCVT_LU_S_INX, Convert__Reg1_0__GPRAsFPR1_1__imm_95_7, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR }, }, 4162 { 1996 /* fcvt.lu.s */, RISCV::FCVT_LU_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, }, 4163 { 1996 /* fcvt.lu.s */, RISCV::FCVT_LU_S_INX, Convert__Reg1_0__GPRAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4164 { 2006 /* fcvt.s.d */, RISCV::FCVT_S_D, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR32, MCK_FPR64 }, }, 4165 { 2006 /* fcvt.s.d */, RISCV::FCVT_S_D_INX, Convert__GPRAsFPR1_0__GPRF64AsFPR1_1__imm_95_7, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRAsFPR, MCK_GPRF64AsFPR }, }, 4166 { 2006 /* fcvt.s.d */, RISCV::FCVT_S_D_IN32X, Convert__GPRAsFPR1_0__GPRPF64AsFPR1_1__imm_95_7, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRAsFPR, MCK_GPRPF64AsFPR }, }, 4167 { 2006 /* fcvt.s.d */, RISCV::FCVT_S_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_FPR32, MCK_FPR64, MCK_FRMArg }, }, 4168 { 2006 /* fcvt.s.d */, RISCV::FCVT_S_D_INX, Convert__GPRAsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRAsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, }, 4169 { 2006 /* fcvt.s.d */, RISCV::FCVT_S_D_IN32X, Convert__GPRAsFPR1_0__GPRPF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRAsFPR, MCK_GPRPF64AsFPR, MCK_FRMArg }, }, 4170 { 2015 /* fcvt.s.h */, RISCV::FCVT_S_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZfhOrZfhmin, { MCK_FPR32, MCK_FPR16 }, }, 4171 { 2015 /* fcvt.s.h */, RISCV::FCVT_S_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1, AMFBS_HasStdExtZhinxOrZhinxmin, { MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4172 { 2024 /* fcvt.s.l */, RISCV::FCVT_S_L, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR }, }, 4173 { 2024 /* fcvt.s.l */, RISCV::FCVT_S_L_INX, Convert__GPRAsFPR1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPRAsFPR, MCK_GPR }, }, 4174 { 2024 /* fcvt.s.l */, RISCV::FCVT_S_L, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, }, 4175 { 2024 /* fcvt.s.l */, RISCV::FCVT_S_L_INX, Convert__GPRAsFPR1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPRAsFPR, MCK_GPR, MCK_FRMArg }, }, 4176 { 2033 /* fcvt.s.lu */, RISCV::FCVT_S_LU, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR }, }, 4177 { 2033 /* fcvt.s.lu */, RISCV::FCVT_S_LU_INX, Convert__GPRAsFPR1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPRAsFPR, MCK_GPR }, }, 4178 { 2033 /* fcvt.s.lu */, RISCV::FCVT_S_LU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, }, 4179 { 2033 /* fcvt.s.lu */, RISCV::FCVT_S_LU_INX, Convert__GPRAsFPR1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPRAsFPR, MCK_GPR, MCK_FRMArg }, }, 4180 { 2043 /* fcvt.s.w */, RISCV::FCVT_S_W, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR }, }, 4181 { 2043 /* fcvt.s.w */, RISCV::FCVT_S_W_INX, Convert__GPRAsFPR1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPR }, }, 4182 { 2043 /* fcvt.s.w */, RISCV::FCVT_S_W, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, }, 4183 { 2043 /* fcvt.s.w */, RISCV::FCVT_S_W_INX, Convert__GPRAsFPR1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPR, MCK_FRMArg }, }, 4184 { 2052 /* fcvt.s.wu */, RISCV::FCVT_S_WU, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR }, }, 4185 { 2052 /* fcvt.s.wu */, RISCV::FCVT_S_WU_INX, Convert__GPRAsFPR1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPR }, }, 4186 { 2052 /* fcvt.s.wu */, RISCV::FCVT_S_WU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, }, 4187 { 2052 /* fcvt.s.wu */, RISCV::FCVT_S_WU_INX, Convert__GPRAsFPR1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPR, MCK_FRMArg }, }, 4188 { 2062 /* fcvt.w.d */, RISCV::FCVT_W_D, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64 }, }, 4189 { 2062 /* fcvt.w.d */, RISCV::FCVT_W_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__imm_95_7, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR }, }, 4190 { 2062 /* fcvt.w.d */, RISCV::FCVT_W_D_IN32X, Convert__Reg1_0__GPRPF64AsFPR1_1__imm_95_7, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPF64AsFPR }, }, 4191 { 2062 /* fcvt.w.d */, RISCV::FCVT_W_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, }, 4192 { 2062 /* fcvt.w.d */, RISCV::FCVT_W_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, }, 4193 { 2062 /* fcvt.w.d */, RISCV::FCVT_W_D_IN32X, Convert__Reg1_0__GPRPF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPF64AsFPR, MCK_FRMArg }, }, 4194 { 2071 /* fcvt.w.h */, RISCV::FCVT_W_H, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16 }, }, 4195 { 2071 /* fcvt.w.h */, RISCV::FCVT_W_H_INX, Convert__Reg1_0__GPRAsFPR1_1__imm_95_7, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR }, }, 4196 { 2071 /* fcvt.w.h */, RISCV::FCVT_W_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, }, 4197 { 2071 /* fcvt.w.h */, RISCV::FCVT_W_H_INX, Convert__Reg1_0__GPRAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4198 { 2080 /* fcvt.w.s */, RISCV::FCVT_W_S, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32 }, }, 4199 { 2080 /* fcvt.w.s */, RISCV::FCVT_W_S_INX, Convert__Reg1_0__GPRAsFPR1_1__imm_95_7, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR }, }, 4200 { 2080 /* fcvt.w.s */, RISCV::FCVT_W_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, }, 4201 { 2080 /* fcvt.w.s */, RISCV::FCVT_W_S_INX, Convert__Reg1_0__GPRAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4202 { 2089 /* fcvt.wu.d */, RISCV::FCVT_WU_D, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64 }, }, 4203 { 2089 /* fcvt.wu.d */, RISCV::FCVT_WU_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__imm_95_7, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR }, }, 4204 { 2089 /* fcvt.wu.d */, RISCV::FCVT_WU_D_IN32X, Convert__Reg1_0__GPRPF64AsFPR1_1__imm_95_7, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPF64AsFPR }, }, 4205 { 2089 /* fcvt.wu.d */, RISCV::FCVT_WU_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, }, 4206 { 2089 /* fcvt.wu.d */, RISCV::FCVT_WU_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, }, 4207 { 2089 /* fcvt.wu.d */, RISCV::FCVT_WU_D_IN32X, Convert__Reg1_0__GPRPF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPF64AsFPR, MCK_FRMArg }, }, 4208 { 2099 /* fcvt.wu.h */, RISCV::FCVT_WU_H, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16 }, }, 4209 { 2099 /* fcvt.wu.h */, RISCV::FCVT_WU_H_INX, Convert__Reg1_0__GPRAsFPR1_1__imm_95_7, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR }, }, 4210 { 2099 /* fcvt.wu.h */, RISCV::FCVT_WU_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, }, 4211 { 2099 /* fcvt.wu.h */, RISCV::FCVT_WU_H_INX, Convert__Reg1_0__GPRAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4212 { 2109 /* fcvt.wu.s */, RISCV::FCVT_WU_S, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32 }, }, 4213 { 2109 /* fcvt.wu.s */, RISCV::FCVT_WU_S_INX, Convert__Reg1_0__GPRAsFPR1_1__imm_95_7, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR }, }, 4214 { 2109 /* fcvt.wu.s */, RISCV::FCVT_WU_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, }, 4215 { 2109 /* fcvt.wu.s */, RISCV::FCVT_WU_S_INX, Convert__Reg1_0__GPRAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4216 { 2119 /* fdiv.d */, RISCV::FDIV_D, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 4217 { 2119 /* fdiv.d */, RISCV::FDIV_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__imm_95_7, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, }, 4218 { 2119 /* fdiv.d */, RISCV::FDIV_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__imm_95_7, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR }, }, 4219 { 2119 /* fdiv.d */, RISCV::FDIV_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, }, 4220 { 2119 /* fdiv.d */, RISCV::FDIV_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, }, 4221 { 2119 /* fdiv.d */, RISCV::FDIV_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_FRMArg }, }, 4222 { 2126 /* fdiv.h */, RISCV::FDIV_H, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, }, 4223 { 2126 /* fdiv.h */, RISCV::FDIV_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__imm_95_7, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4224 { 2126 /* fdiv.h */, RISCV::FDIV_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, }, 4225 { 2126 /* fdiv.h */, RISCV::FDIV_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4226 { 2133 /* fdiv.s */, RISCV::FDIV_S, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 4227 { 2133 /* fdiv.s */, RISCV::FDIV_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__imm_95_7, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4228 { 2133 /* fdiv.s */, RISCV::FDIV_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, }, 4229 { 2133 /* fdiv.s */, RISCV::FDIV_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4230 { 2140 /* fence */, RISCV::FENCE, Convert__imm_95_15__imm_95_15, AMFBS_None, { }, }, 4231 { 2140 /* fence */, RISCV::FENCE, Convert__FenceArg1_0__FenceArg1_1, AMFBS_None, { MCK_FenceArg, MCK_FenceArg }, }, 4232 { 2146 /* fence.i */, RISCV::FENCE_I, Convert_NoOperands, AMFBS_None, { }, }, 4233 { 2154 /* fence.tso */, RISCV::FENCE_TSO, Convert_NoOperands, AMFBS_None, { }, }, 4234 { 2164 /* feq.d */, RISCV::FEQ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, }, 4235 { 2164 /* feq.d */, RISCV::FEQ_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, }, 4236 { 2164 /* feq.d */, RISCV::FEQ_D_IN32X, Convert__Reg1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR }, }, 4237 { 2170 /* feq.h */, RISCV::FEQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, }, 4238 { 2170 /* feq.h */, RISCV::FEQ_H_INX, Convert__Reg1_0__GPRAsFPR1_1__GPRAsFPR1_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4239 { 2176 /* feq.s */, RISCV::FEQ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, }, 4240 { 2176 /* feq.s */, RISCV::FEQ_S_INX, Convert__Reg1_0__GPRAsFPR1_1__GPRAsFPR1_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4241 { 2182 /* fge.d */, RISCV::FLE_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, }, 4242 { 2182 /* fge.d */, RISCV::FLE_D_INX, Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, }, 4243 { 2182 /* fge.d */, RISCV::FLE_D_IN32X, Convert__Reg1_0__GPRPF64AsFPR1_2__GPRPF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR }, }, 4244 { 2188 /* fge.h */, RISCV::FLE_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, }, 4245 { 2188 /* fge.h */, RISCV::FLE_H_INX, Convert__Reg1_0__GPRAsFPR1_2__GPRAsFPR1_1, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4246 { 2194 /* fge.s */, RISCV::FLE_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, }, 4247 { 2194 /* fge.s */, RISCV::FLE_S_INX, Convert__Reg1_0__GPRAsFPR1_2__GPRAsFPR1_1, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4248 { 2200 /* fgt.d */, RISCV::FLT_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, }, 4249 { 2200 /* fgt.d */, RISCV::FLT_D_INX, Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, }, 4250 { 2200 /* fgt.d */, RISCV::FLT_D_IN32X, Convert__Reg1_0__GPRPF64AsFPR1_2__GPRPF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR }, }, 4251 { 2206 /* fgt.h */, RISCV::FLT_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, }, 4252 { 2206 /* fgt.h */, RISCV::FLT_H_INX, Convert__Reg1_0__GPRAsFPR1_2__GPRAsFPR1_1, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4253 { 2212 /* fgt.s */, RISCV::FLT_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, }, 4254 { 2212 /* fgt.s */, RISCV::FLT_S_INX, Convert__Reg1_0__GPRAsFPR1_2__GPRAsFPR1_1, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4255 { 2218 /* fld */, RISCV::PseudoFLD, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_BareSymbol, MCK_GPR }, }, 4256 { 2218 /* fld */, RISCV::FLD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtD, { MCK_FPR64, MCK__40_, MCK_GPR, MCK__41_ }, }, 4257 { 2218 /* fld */, RISCV::FLD, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 4258 { 2222 /* fle.d */, RISCV::FLE_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, }, 4259 { 2222 /* fle.d */, RISCV::FLE_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, }, 4260 { 2222 /* fle.d */, RISCV::FLE_D_IN32X, Convert__Reg1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR }, }, 4261 { 2228 /* fle.h */, RISCV::FLE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, }, 4262 { 2228 /* fle.h */, RISCV::FLE_H_INX, Convert__Reg1_0__GPRAsFPR1_1__GPRAsFPR1_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4263 { 2234 /* fle.s */, RISCV::FLE_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, }, 4264 { 2234 /* fle.s */, RISCV::FLE_S_INX, Convert__Reg1_0__GPRAsFPR1_1__GPRAsFPR1_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4265 { 2240 /* flh */, RISCV::PseudoFLH, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtZfhOrZfhmin, { MCK_FPR16, MCK_BareSymbol, MCK_GPR }, }, 4266 { 2240 /* flh */, RISCV::FLH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZfhOrZfhmin, { MCK_FPR16, MCK__40_, MCK_GPR, MCK__41_ }, }, 4267 { 2240 /* flh */, RISCV::FLH, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasStdExtZfhOrZfhmin, { MCK_FPR16, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 4268 { 2244 /* flt.d */, RISCV::FLT_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, }, 4269 { 2244 /* flt.d */, RISCV::FLT_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, }, 4270 { 2244 /* flt.d */, RISCV::FLT_D_IN32X, Convert__Reg1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR }, }, 4271 { 2250 /* flt.h */, RISCV::FLT_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, }, 4272 { 2250 /* flt.h */, RISCV::FLT_H_INX, Convert__Reg1_0__GPRAsFPR1_1__GPRAsFPR1_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4273 { 2256 /* flt.s */, RISCV::FLT_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, }, 4274 { 2256 /* flt.s */, RISCV::FLT_S_INX, Convert__Reg1_0__GPRAsFPR1_1__GPRAsFPR1_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4275 { 2262 /* flw */, RISCV::PseudoFLW, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_BareSymbol, MCK_GPR }, }, 4276 { 2262 /* flw */, RISCV::FLW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtF, { MCK_FPR32, MCK__40_, MCK_GPR, MCK__41_ }, }, 4277 { 2262 /* flw */, RISCV::FLW, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 4278 { 2266 /* fmadd.d */, RISCV::FMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 4279 { 2266 /* fmadd.d */, RISCV::FMADD_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__imm_95_7, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, }, 4280 { 2266 /* fmadd.d */, RISCV::FMADD_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__GPRPF64AsFPR1_3__imm_95_7, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR }, }, 4281 { 2266 /* fmadd.d */, RISCV::FMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, }, 4282 { 2266 /* fmadd.d */, RISCV::FMADD_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, }, 4283 { 2266 /* fmadd.d */, RISCV::FMADD_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__GPRPF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_FRMArg }, }, 4284 { 2274 /* fmadd.h */, RISCV::FMADD_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16 }, }, 4285 { 2274 /* fmadd.h */, RISCV::FMADD_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__imm_95_7, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4286 { 2274 /* fmadd.h */, RISCV::FMADD_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, }, 4287 { 2274 /* fmadd.h */, RISCV::FMADD_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4288 { 2282 /* fmadd.s */, RISCV::FMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 4289 { 2282 /* fmadd.s */, RISCV::FMADD_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__imm_95_7, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4290 { 2282 /* fmadd.s */, RISCV::FMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, }, 4291 { 2282 /* fmadd.s */, RISCV::FMADD_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4292 { 2290 /* fmax.d */, RISCV::FMAX_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 4293 { 2290 /* fmax.d */, RISCV::FMAX_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, }, 4294 { 2290 /* fmax.d */, RISCV::FMAX_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR }, }, 4295 { 2297 /* fmax.h */, RISCV::FMAX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, }, 4296 { 2297 /* fmax.h */, RISCV::FMAX_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4297 { 2304 /* fmax.s */, RISCV::FMAX_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 4298 { 2304 /* fmax.s */, RISCV::FMAX_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4299 { 2311 /* fmin.d */, RISCV::FMIN_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 4300 { 2311 /* fmin.d */, RISCV::FMIN_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, }, 4301 { 2311 /* fmin.d */, RISCV::FMIN_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR }, }, 4302 { 2318 /* fmin.h */, RISCV::FMIN_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, }, 4303 { 2318 /* fmin.h */, RISCV::FMIN_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4304 { 2325 /* fmin.s */, RISCV::FMIN_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 4305 { 2325 /* fmin.s */, RISCV::FMIN_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4306 { 2332 /* fmsub.d */, RISCV::FMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 4307 { 2332 /* fmsub.d */, RISCV::FMSUB_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__imm_95_7, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, }, 4308 { 2332 /* fmsub.d */, RISCV::FMSUB_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__GPRPF64AsFPR1_3__imm_95_7, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR }, }, 4309 { 2332 /* fmsub.d */, RISCV::FMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, }, 4310 { 2332 /* fmsub.d */, RISCV::FMSUB_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, }, 4311 { 2332 /* fmsub.d */, RISCV::FMSUB_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__GPRPF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_FRMArg }, }, 4312 { 2340 /* fmsub.h */, RISCV::FMSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16 }, }, 4313 { 2340 /* fmsub.h */, RISCV::FMSUB_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__imm_95_7, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4314 { 2340 /* fmsub.h */, RISCV::FMSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, }, 4315 { 2340 /* fmsub.h */, RISCV::FMSUB_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4316 { 2348 /* fmsub.s */, RISCV::FMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 4317 { 2348 /* fmsub.s */, RISCV::FMSUB_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__imm_95_7, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4318 { 2348 /* fmsub.s */, RISCV::FMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, }, 4319 { 2348 /* fmsub.s */, RISCV::FMSUB_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4320 { 2356 /* fmul.d */, RISCV::FMUL_D, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 4321 { 2356 /* fmul.d */, RISCV::FMUL_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__imm_95_7, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, }, 4322 { 2356 /* fmul.d */, RISCV::FMUL_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__imm_95_7, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR }, }, 4323 { 2356 /* fmul.d */, RISCV::FMUL_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, }, 4324 { 2356 /* fmul.d */, RISCV::FMUL_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, }, 4325 { 2356 /* fmul.d */, RISCV::FMUL_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_FRMArg }, }, 4326 { 2363 /* fmul.h */, RISCV::FMUL_H, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, }, 4327 { 2363 /* fmul.h */, RISCV::FMUL_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__imm_95_7, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4328 { 2363 /* fmul.h */, RISCV::FMUL_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, }, 4329 { 2363 /* fmul.h */, RISCV::FMUL_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4330 { 2370 /* fmul.s */, RISCV::FMUL_S, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 4331 { 2370 /* fmul.s */, RISCV::FMUL_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__imm_95_7, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4332 { 2370 /* fmul.s */, RISCV::FMUL_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, }, 4333 { 2370 /* fmul.s */, RISCV::FMUL_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4334 { 2377 /* fmv.d */, RISCV::FSGNJ_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, }, 4335 { 2383 /* fmv.d.x */, RISCV::FMV_D_X, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR }, }, 4336 { 2391 /* fmv.h */, RISCV::FSGNJ_H, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16 }, }, 4337 { 2391 /* fmv.h */, RISCV::FSGNJ_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_1, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4338 { 2397 /* fmv.h.x */, RISCV::FMV_H_X, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZfhOrZfhmin, { MCK_FPR16, MCK_GPR }, }, 4339 { 2405 /* fmv.s */, RISCV::FSGNJ_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, }, 4340 { 2411 /* fmv.w.x */, RISCV::FMV_W_X, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR }, }, 4341 { 2419 /* fmv.x.d */, RISCV::FMV_X_D, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64 }, }, 4342 { 2427 /* fmv.x.h */, RISCV::FMV_X_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZfhOrZfhmin, { MCK_GPR, MCK_FPR16 }, }, 4343 { 2435 /* fmv.x.w */, RISCV::FMV_X_W, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32 }, }, 4344 { 2443 /* fneg.d */, RISCV::FSGNJN_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, }, 4345 { 2443 /* fneg.d */, RISCV::FSGNJN_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, }, 4346 { 2443 /* fneg.d */, RISCV::FSGNJN_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR }, }, 4347 { 2450 /* fneg.h */, RISCV::FSGNJN_H, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16 }, }, 4348 { 2450 /* fneg.h */, RISCV::FSGNJN_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_1, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4349 { 2457 /* fneg.s */, RISCV::FSGNJN_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, }, 4350 { 2457 /* fneg.s */, RISCV::FSGNJN_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_1, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4351 { 2464 /* fnmadd.d */, RISCV::FNMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 4352 { 2464 /* fnmadd.d */, RISCV::FNMADD_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__imm_95_7, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, }, 4353 { 2464 /* fnmadd.d */, RISCV::FNMADD_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__GPRPF64AsFPR1_3__imm_95_7, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR }, }, 4354 { 2464 /* fnmadd.d */, RISCV::FNMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, }, 4355 { 2464 /* fnmadd.d */, RISCV::FNMADD_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, }, 4356 { 2464 /* fnmadd.d */, RISCV::FNMADD_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__GPRPF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_FRMArg }, }, 4357 { 2473 /* fnmadd.h */, RISCV::FNMADD_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16 }, }, 4358 { 2473 /* fnmadd.h */, RISCV::FNMADD_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__imm_95_7, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4359 { 2473 /* fnmadd.h */, RISCV::FNMADD_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, }, 4360 { 2473 /* fnmadd.h */, RISCV::FNMADD_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4361 { 2482 /* fnmadd.s */, RISCV::FNMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 4362 { 2482 /* fnmadd.s */, RISCV::FNMADD_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__imm_95_7, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4363 { 2482 /* fnmadd.s */, RISCV::FNMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, }, 4364 { 2482 /* fnmadd.s */, RISCV::FNMADD_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4365 { 2491 /* fnmsub.d */, RISCV::FNMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 4366 { 2491 /* fnmsub.d */, RISCV::FNMSUB_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__imm_95_7, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, }, 4367 { 2491 /* fnmsub.d */, RISCV::FNMSUB_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__GPRPF64AsFPR1_3__imm_95_7, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR }, }, 4368 { 2491 /* fnmsub.d */, RISCV::FNMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, }, 4369 { 2491 /* fnmsub.d */, RISCV::FNMSUB_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, }, 4370 { 2491 /* fnmsub.d */, RISCV::FNMSUB_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__GPRPF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_FRMArg }, }, 4371 { 2500 /* fnmsub.h */, RISCV::FNMSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16 }, }, 4372 { 2500 /* fnmsub.h */, RISCV::FNMSUB_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__imm_95_7, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4373 { 2500 /* fnmsub.h */, RISCV::FNMSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, }, 4374 { 2500 /* fnmsub.h */, RISCV::FNMSUB_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4375 { 2509 /* fnmsub.s */, RISCV::FNMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 4376 { 2509 /* fnmsub.s */, RISCV::FNMSUB_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__imm_95_7, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4377 { 2509 /* fnmsub.s */, RISCV::FNMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, }, 4378 { 2509 /* fnmsub.s */, RISCV::FNMSUB_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4379 { 2518 /* frcsr */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3__regX0, AMFBS_HasStdExtF, { MCK_GPR }, }, 4380 { 2524 /* frflags */, RISCV::CSRRS, Convert__Reg1_0__imm_95_1__regX0, AMFBS_HasStdExtF, { MCK_GPR }, }, 4381 { 2532 /* frrm */, RISCV::CSRRS, Convert__Reg1_0__imm_95_2__regX0, AMFBS_HasStdExtF, { MCK_GPR }, }, 4382 { 2537 /* frsr */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3__regX0, AMFBS_HasStdExtF, { MCK_GPR }, }, 4383 { 2542 /* fscsr */, RISCV::CSRRW, Convert__regX0__imm_95_3__Reg1_0, AMFBS_HasStdExtF, { MCK_GPR }, }, 4384 { 2542 /* fscsr */, RISCV::CSRRW, Convert__Reg1_0__imm_95_3__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_GPR }, }, 4385 { 2548 /* fsd */, RISCV::PseudoFSD, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_BareSymbol, MCK_GPR }, }, 4386 { 2548 /* fsd */, RISCV::FSD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtD, { MCK_FPR64, MCK__40_, MCK_GPR, MCK__41_ }, }, 4387 { 2548 /* fsd */, RISCV::FSD, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 4388 { 2552 /* fsflags */, RISCV::CSRRW, Convert__regX0__imm_95_1__Reg1_0, AMFBS_HasStdExtF, { MCK_GPR }, }, 4389 { 2552 /* fsflags */, RISCV::CSRRW, Convert__Reg1_0__imm_95_1__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_GPR }, }, 4390 { 2560 /* fsflagsi */, RISCV::CSRRWI, Convert__regX0__imm_95_1__UImm51_0, AMFBS_HasStdExtF, { MCK_UImm5 }, }, 4391 { 2560 /* fsflagsi */, RISCV::CSRRWI, Convert__Reg1_0__imm_95_1__UImm51_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_UImm5 }, }, 4392 { 2569 /* fsgnj.d */, RISCV::FSGNJ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 4393 { 2569 /* fsgnj.d */, RISCV::FSGNJ_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, }, 4394 { 2569 /* fsgnj.d */, RISCV::FSGNJ_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR }, }, 4395 { 2577 /* fsgnj.h */, RISCV::FSGNJ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, }, 4396 { 2577 /* fsgnj.h */, RISCV::FSGNJ_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4397 { 2585 /* fsgnj.s */, RISCV::FSGNJ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 4398 { 2585 /* fsgnj.s */, RISCV::FSGNJ_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4399 { 2593 /* fsgnjn.d */, RISCV::FSGNJN_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 4400 { 2593 /* fsgnjn.d */, RISCV::FSGNJN_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, }, 4401 { 2593 /* fsgnjn.d */, RISCV::FSGNJN_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR }, }, 4402 { 2602 /* fsgnjn.h */, RISCV::FSGNJN_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, }, 4403 { 2602 /* fsgnjn.h */, RISCV::FSGNJN_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4404 { 2611 /* fsgnjn.s */, RISCV::FSGNJN_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 4405 { 2611 /* fsgnjn.s */, RISCV::FSGNJN_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4406 { 2620 /* fsgnjx.d */, RISCV::FSGNJX_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 4407 { 2620 /* fsgnjx.d */, RISCV::FSGNJX_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, }, 4408 { 2620 /* fsgnjx.d */, RISCV::FSGNJX_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR }, }, 4409 { 2629 /* fsgnjx.h */, RISCV::FSGNJX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, }, 4410 { 2629 /* fsgnjx.h */, RISCV::FSGNJX_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4411 { 2638 /* fsgnjx.s */, RISCV::FSGNJX_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 4412 { 2638 /* fsgnjx.s */, RISCV::FSGNJX_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4413 { 2647 /* fsh */, RISCV::PseudoFSH, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtZfhOrZfhmin, { MCK_FPR16, MCK_BareSymbol, MCK_GPR }, }, 4414 { 2647 /* fsh */, RISCV::FSH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZfhOrZfhmin, { MCK_FPR16, MCK__40_, MCK_GPR, MCK__41_ }, }, 4415 { 2647 /* fsh */, RISCV::FSH, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasStdExtZfhOrZfhmin, { MCK_FPR16, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 4416 { 2651 /* fsqrt.d */, RISCV::FSQRT_D, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, }, 4417 { 2651 /* fsqrt.d */, RISCV::FSQRT_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__imm_95_7, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, }, 4418 { 2651 /* fsqrt.d */, RISCV::FSQRT_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__imm_95_7, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR }, }, 4419 { 2651 /* fsqrt.d */, RISCV::FSQRT_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FRMArg }, }, 4420 { 2651 /* fsqrt.d */, RISCV::FSQRT_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, }, 4421 { 2651 /* fsqrt.d */, RISCV::FSQRT_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_FRMArg }, }, 4422 { 2659 /* fsqrt.h */, RISCV::FSQRT_H, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16 }, }, 4423 { 2659 /* fsqrt.h */, RISCV::FSQRT_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__imm_95_7, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4424 { 2659 /* fsqrt.h */, RISCV::FSQRT_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FRMArg }, }, 4425 { 2659 /* fsqrt.h */, RISCV::FSQRT_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4426 { 2667 /* fsqrt.s */, RISCV::FSQRT_S, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, }, 4427 { 2667 /* fsqrt.s */, RISCV::FSQRT_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__imm_95_7, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4428 { 2667 /* fsqrt.s */, RISCV::FSQRT_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FRMArg }, }, 4429 { 2667 /* fsqrt.s */, RISCV::FSQRT_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4430 { 2675 /* fsrm */, RISCV::CSRRW, Convert__regX0__imm_95_2__Reg1_0, AMFBS_HasStdExtF, { MCK_GPR }, }, 4431 { 2675 /* fsrm */, RISCV::CSRRW, Convert__Reg1_0__imm_95_2__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_GPR }, }, 4432 { 2680 /* fsrmi */, RISCV::CSRRWI, Convert__regX0__imm_95_2__UImm51_0, AMFBS_HasStdExtF, { MCK_UImm5 }, }, 4433 { 2680 /* fsrmi */, RISCV::CSRRWI, Convert__Reg1_0__imm_95_2__UImm51_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_UImm5 }, }, 4434 { 2686 /* fssr */, RISCV::CSRRW, Convert__regX0__imm_95_3__Reg1_0, AMFBS_HasStdExtF, { MCK_GPR }, }, 4435 { 2686 /* fssr */, RISCV::CSRRW, Convert__Reg1_0__imm_95_3__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_GPR }, }, 4436 { 2691 /* fsub.d */, RISCV::FSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 4437 { 2691 /* fsub.d */, RISCV::FSUB_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__imm_95_7, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, }, 4438 { 2691 /* fsub.d */, RISCV::FSUB_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__imm_95_7, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR }, }, 4439 { 2691 /* fsub.d */, RISCV::FSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, }, 4440 { 2691 /* fsub.d */, RISCV::FSUB_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, }, 4441 { 2691 /* fsub.d */, RISCV::FSUB_D_IN32X, Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_GPRPF64AsFPR, MCK_FRMArg }, }, 4442 { 2698 /* fsub.h */, RISCV::FSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, }, 4443 { 2698 /* fsub.h */, RISCV::FSUB_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__imm_95_7, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4444 { 2698 /* fsub.h */, RISCV::FSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, }, 4445 { 2698 /* fsub.h */, RISCV::FSUB_H_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4446 { 2705 /* fsub.s */, RISCV::FSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 4447 { 2705 /* fsub.s */, RISCV::FSUB_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__imm_95_7, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR }, }, 4448 { 2705 /* fsub.s */, RISCV::FSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, }, 4449 { 2705 /* fsub.s */, RISCV::FSUB_S_INX, Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_GPRAsFPR, MCK_FRMArg }, }, 4450 { 2712 /* fsw */, RISCV::PseudoFSW, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_BareSymbol, MCK_GPR }, }, 4451 { 2712 /* fsw */, RISCV::FSW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtF, { MCK_FPR32, MCK__40_, MCK_GPR, MCK__41_ }, }, 4452 { 2712 /* fsw */, RISCV::FSW, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 4453 { 2716 /* hfence.gvma */, RISCV::HFENCE_GVMA, Convert__regX0__regX0, AMFBS_None, { }, }, 4454 { 2716 /* hfence.gvma */, RISCV::HFENCE_GVMA, Convert__Reg1_0__regX0, AMFBS_None, { MCK_GPR }, }, 4455 { 2716 /* hfence.gvma */, RISCV::HFENCE_GVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_GPR }, }, 4456 { 2728 /* hfence.vvma */, RISCV::HFENCE_VVMA, Convert__regX0__regX0, AMFBS_None, { }, }, 4457 { 2728 /* hfence.vvma */, RISCV::HFENCE_VVMA, Convert__Reg1_0__regX0, AMFBS_None, { MCK_GPR }, }, 4458 { 2728 /* hfence.vvma */, RISCV::HFENCE_VVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_GPR }, }, 4459 { 2740 /* hinval.gvma */, RISCV::HINVAL_GVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtSvinval, { MCK_GPR, MCK_GPR }, }, 4460 { 2752 /* hinval.vvma */, RISCV::HINVAL_VVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtSvinval, { MCK_GPR, MCK_GPR }, }, 4461 { 2764 /* hlv.b */, RISCV::HLV_B, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4462 { 2770 /* hlv.bu */, RISCV::HLV_BU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4463 { 2777 /* hlv.d */, RISCV::HLV_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_IsRV64_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4464 { 2783 /* hlv.h */, RISCV::HLV_H, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4465 { 2789 /* hlv.hu */, RISCV::HLV_HU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4466 { 2796 /* hlv.w */, RISCV::HLV_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4467 { 2802 /* hlv.wu */, RISCV::HLV_WU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_IsRV64_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4468 { 2809 /* hlvx.hu */, RISCV::HLVX_HU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4469 { 2817 /* hlvx.wu */, RISCV::HLVX_WU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4470 { 2825 /* hsv.b */, RISCV::HSV_B, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4471 { 2831 /* hsv.d */, RISCV::HSV_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_IsRV64_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4472 { 2837 /* hsv.h */, RISCV::HSV_H, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4473 { 2843 /* hsv.w */, RISCV::HSV_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4474 { 2849 /* j */, RISCV::JAL, Convert__regX0__SImm21Lsb0JAL1_0, AMFBS_None, { MCK_SImm21Lsb0JAL }, }, 4475 { 2851 /* jal */, RISCV::JAL, Convert__regX1__SImm21Lsb0JAL1_0, AMFBS_None, { MCK_SImm21Lsb0JAL }, }, 4476 { 2851 /* jal */, RISCV::JAL, Convert__Reg1_0__SImm21Lsb0JAL1_1, AMFBS_None, { MCK_GPR, MCK_SImm21Lsb0JAL }, }, 4477 { 2855 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_0__imm_95_0, AMFBS_None, { MCK_GPR }, }, 4478 { 2855 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR, MCK_GPR }, }, 4479 { 2855 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_0__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12 }, }, 4480 { 2855 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 4481 { 2855 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_2__SImm121_0, AMFBS_None, { MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 4482 { 2855 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 4483 { 2860 /* jr */, RISCV::JALR, Convert__regX0__Reg1_0__imm_95_0, AMFBS_None, { MCK_GPR }, }, 4484 { 2860 /* jr */, RISCV::JALR, Convert__regX0__Reg1_0__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12 }, }, 4485 { 2860 /* jr */, RISCV::JALR, Convert__regX0__Reg1_2__SImm121_0, AMFBS_None, { MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 4486 { 2863 /* jump */, RISCV::PseudoJump, Convert__Reg1_1__PseudoJumpSymbol1_0, AMFBS_None, { MCK_PseudoJumpSymbol, MCK_GPR }, }, 4487 { 2868 /* la */, RISCV::PseudoLA, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, }, 4488 { 2871 /* la.tls.gd */, RISCV::PseudoLA_TLS_GD, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, }, 4489 { 2881 /* la.tls.ie */, RISCV::PseudoLA_TLS_IE, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, }, 4490 { 2891 /* lb */, RISCV::PseudoLB, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, }, 4491 { 2891 /* lb */, RISCV::LB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, }, 4492 { 2891 /* lb */, RISCV::LB, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 4493 { 2894 /* lbu */, RISCV::PseudoLBU, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, }, 4494 { 2894 /* lbu */, RISCV::LBU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, }, 4495 { 2894 /* lbu */, RISCV::LBU, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 4496 { 2898 /* ld */, RISCV::PseudoLD, Convert__Reg1_0__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPR, MCK_BareSymbol }, }, 4497 { 2898 /* ld */, RISCV::LD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, }, 4498 { 2898 /* ld */, RISCV::LD, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 4499 { 2901 /* lh */, RISCV::PseudoLH, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, }, 4500 { 2901 /* lh */, RISCV::LH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, }, 4501 { 2901 /* lh */, RISCV::LH, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 4502 { 2904 /* lhu */, RISCV::PseudoLHU, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, }, 4503 { 2904 /* lhu */, RISCV::LHU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, }, 4504 { 2904 /* lhu */, RISCV::LHU, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 4505 { 2908 /* li */, RISCV::ADDI, Convert__Reg1_0__regX0__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12 }, }, 4506 { 2908 /* li */, RISCV::PseudoLI, Convert__Reg1_0__ImmXLenLI1_1, AMFBS_None, { MCK_GPR, MCK_ImmXLenLI }, }, 4507 { 2911 /* lla */, RISCV::PseudoLLA, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, }, 4508 { 2915 /* lr.d */, RISCV::LR_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4509 { 2920 /* lr.d.aq */, RISCV::LR_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4510 { 2928 /* lr.d.aqrl */, RISCV::LR_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4511 { 2938 /* lr.d.rl */, RISCV::LR_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4512 { 2946 /* lr.w */, RISCV::LR_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4513 { 2951 /* lr.w.aq */, RISCV::LR_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4514 { 2959 /* lr.w.aqrl */, RISCV::LR_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4515 { 2969 /* lr.w.rl */, RISCV::LR_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4516 { 2977 /* lui */, RISCV::LUI, Convert__Reg1_0__UImm20LUI1_1, AMFBS_None, { MCK_GPR, MCK_UImm20LUI }, }, 4517 { 2981 /* lw */, RISCV::PseudoLW, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, }, 4518 { 2981 /* lw */, RISCV::LW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, }, 4519 { 2981 /* lw */, RISCV::LW, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 4520 { 2984 /* lwu */, RISCV::PseudoLWU, Convert__Reg1_0__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPR, MCK_BareSymbol }, }, 4521 { 2984 /* lwu */, RISCV::LWU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, }, 4522 { 2984 /* lwu */, RISCV::LWU, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 4523 { 2988 /* max */, RISCV::MAX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4524 { 2992 /* maxu */, RISCV::MAXU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4525 { 2997 /* min */, RISCV::MIN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4526 { 3001 /* minu */, RISCV::MINU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4527 { 3006 /* mret */, RISCV::MRET, Convert__imm_95_0__imm_95_0, AMFBS_None, { }, }, 4528 { 3011 /* mul */, RISCV::MUL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtMOrZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4529 { 3015 /* mulh */, RISCV::MULH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtMOrZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4530 { 3020 /* mulhsu */, RISCV::MULHSU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtMOrZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4531 { 3027 /* mulhu */, RISCV::MULHU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtMOrZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4532 { 3033 /* mulw */, RISCV::MULW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtMOrZmmul_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4533 { 3038 /* mv */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR, MCK_GPR }, }, 4534 { 3041 /* neg */, RISCV::SUB, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, }, 4535 { 3045 /* negw */, RISCV::SUBW, Convert__Reg1_0__regX0__Reg1_1, AMFBS_IsRV64, { MCK_GPR, MCK_GPR }, }, 4536 { 3050 /* nop */, RISCV::ADDI, Convert__regX0__regX0__imm_95_0, AMFBS_None, { }, }, 4537 { 3054 /* not */, RISCV::XORI, Convert__Reg1_0__Reg1_1__imm_95__MINUS_1, AMFBS_None, { MCK_GPR, MCK_GPR }, }, 4538 { 3058 /* ntl.all */, RISCV::ADD, Convert__regX0__regX0__regX5, AMFBS_HasStdExtZihintntl, { }, }, 4539 { 3066 /* ntl.p1 */, RISCV::ADD, Convert__regX0__regX0__regX2, AMFBS_HasStdExtZihintntl, { }, }, 4540 { 3073 /* ntl.pall */, RISCV::ADD, Convert__regX0__regX0__regX3, AMFBS_HasStdExtZihintntl, { }, }, 4541 { 3082 /* ntl.s1 */, RISCV::ADD, Convert__regX0__regX0__regX4, AMFBS_HasStdExtZihintntl, { }, }, 4542 { 3089 /* or */, RISCV::OR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4543 { 3089 /* or */, RISCV::ORI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 4544 { 3092 /* orc.b */, RISCV::ORC_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, }, 4545 { 3098 /* ori */, RISCV::ORI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 4546 { 3102 /* orn */, RISCV::ORN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4547 { 3106 /* pack */, RISCV::PACK, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4548 { 3111 /* packh */, RISCV::PACKH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4549 { 3117 /* packw */, RISCV::PACKW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4550 { 3123 /* pause */, RISCV::FENCE, Convert__imm_95_1__imm_95_0, AMFBS_HasStdExtZihintpause, { }, }, 4551 { 3129 /* prefetch.i */, RISCV::PREFETCH_I, Convert__Reg1_2__SImm12Lsb000001_0, AMFBS_HasStdExtZicbop, { MCK_SImm12Lsb00000, MCK__40_, MCK_GPR, MCK__41_ }, }, 4552 { 3140 /* prefetch.r */, RISCV::PREFETCH_R, Convert__Reg1_2__SImm12Lsb000001_0, AMFBS_HasStdExtZicbop, { MCK_SImm12Lsb00000, MCK__40_, MCK_GPR, MCK__41_ }, }, 4553 { 3151 /* prefetch.w */, RISCV::PREFETCH_W, Convert__Reg1_2__SImm12Lsb000001_0, AMFBS_HasStdExtZicbop, { MCK_SImm12Lsb00000, MCK__40_, MCK_GPR, MCK__41_ }, }, 4554 { 3162 /* rdcycle */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3072__regX0, AMFBS_None, { MCK_GPR }, }, 4555 { 3170 /* rdcycleh */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3200__regX0, AMFBS_IsRV32, { MCK_GPR }, }, 4556 { 3179 /* rdinstret */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3074__regX0, AMFBS_None, { MCK_GPR }, }, 4557 { 3189 /* rdinstreth */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3202__regX0, AMFBS_IsRV32, { MCK_GPR }, }, 4558 { 3200 /* rdtime */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3073__regX0, AMFBS_None, { MCK_GPR }, }, 4559 { 3207 /* rdtimeh */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3201__regX0, AMFBS_IsRV32, { MCK_GPR }, }, 4560 { 3215 /* rem */, RISCV::REM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4561 { 3219 /* remu */, RISCV::REMU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4562 { 3224 /* remuw */, RISCV::REMUW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4563 { 3230 /* remw */, RISCV::REMW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4564 { 3235 /* ret */, RISCV::JALR, Convert__regX0__regX1__imm_95_0, AMFBS_None, { }, }, 4565 { 3239 /* rev8 */, RISCV::REV8_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbbOrZbkb_IsRV32, { MCK_GPR, MCK_GPR }, }, 4566 { 3239 /* rev8 */, RISCV::REV8_RV64, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR }, }, 4567 { 3244 /* rol */, RISCV::ROL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4568 { 3248 /* rolw */, RISCV::ROLW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4569 { 3253 /* ror */, RISCV::ROR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4570 { 3253 /* ror */, RISCV::RORI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 4571 { 3257 /* rori */, RISCV::RORI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 4572 { 3262 /* roriw */, RISCV::RORIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, }, 4573 { 3268 /* rorw */, RISCV::RORW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4574 { 3268 /* rorw */, RISCV::RORIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, }, 4575 { 3273 /* sb */, RISCV::PseudoSB, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, }, 4576 { 3273 /* sb */, RISCV::SB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, }, 4577 { 3273 /* sb */, RISCV::SB, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 4578 { 3276 /* sc.d */, RISCV::SC_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4579 { 3281 /* sc.d.aq */, RISCV::SC_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4580 { 3289 /* sc.d.aqrl */, RISCV::SC_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4581 { 3299 /* sc.d.rl */, RISCV::SC_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4582 { 3307 /* sc.w */, RISCV::SC_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4583 { 3312 /* sc.w.aq */, RISCV::SC_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4584 { 3320 /* sc.w.aqrl */, RISCV::SC_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4585 { 3330 /* sc.w.rl */, RISCV::SC_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, }, 4586 { 3338 /* sd */, RISCV::PseudoSD, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, }, 4587 { 3338 /* sd */, RISCV::SD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, }, 4588 { 3338 /* sd */, RISCV::SD, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 4589 { 3341 /* seqz */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__imm_95_1, AMFBS_None, { MCK_GPR, MCK_GPR }, }, 4590 { 3346 /* sext.b */, RISCV::SEXT_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, }, 4591 { 3346 /* sext.b */, RISCV::PseudoSEXT_B, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, }, 4592 { 3353 /* sext.h */, RISCV::SEXT_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, }, 4593 { 3353 /* sext.h */, RISCV::PseudoSEXT_H, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, }, 4594 { 3360 /* sext.w */, RISCV::ADDIW, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK_GPR }, }, 4595 { 3367 /* sfence.inval.ir */, RISCV::SFENCE_INVAL_IR, Convert__imm_95_0__imm_95_0, AMFBS_HasStdExtSvinval, { }, }, 4596 { 3383 /* sfence.vma */, RISCV::SFENCE_VMA, Convert__regX0__regX0, AMFBS_None, { }, }, 4597 { 3383 /* sfence.vma */, RISCV::SFENCE_VMA, Convert__Reg1_0__regX0, AMFBS_None, { MCK_GPR }, }, 4598 { 3383 /* sfence.vma */, RISCV::SFENCE_VMA, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, }, 4599 { 3394 /* sfence.w.inval */, RISCV::SFENCE_W_INVAL, Convert__imm_95_0__imm_95_0, AMFBS_HasStdExtSvinval, { }, }, 4600 { 3409 /* sgt */, RISCV::SLT, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4601 { 3413 /* sgtu */, RISCV::SLTU, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4602 { 3418 /* sgtz */, RISCV::SLT, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, }, 4603 { 3423 /* sh */, RISCV::PseudoSH, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, }, 4604 { 3423 /* sh */, RISCV::SH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, }, 4605 { 3423 /* sh */, RISCV::SH, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 4606 { 3426 /* sh1add */, RISCV::SH1ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4607 { 3433 /* sh1add.uw */, RISCV::SH1ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4608 { 3443 /* sh2add */, RISCV::SH2ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4609 { 3450 /* sh2add.uw */, RISCV::SH2ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4610 { 3460 /* sh3add */, RISCV::SH3ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4611 { 3467 /* sh3add.uw */, RISCV::SH3ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4612 { 3477 /* sha256sig0 */, RISCV::SHA256SIG0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, }, 4613 { 3488 /* sha256sig1 */, RISCV::SHA256SIG1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, }, 4614 { 3499 /* sha256sum0 */, RISCV::SHA256SUM0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, }, 4615 { 3510 /* sha256sum1 */, RISCV::SHA256SUM1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, }, 4616 { 3521 /* sha512sig0 */, RISCV::SHA512SIG0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, }, 4617 { 3532 /* sha512sig0h */, RISCV::SHA512SIG0H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4618 { 3544 /* sha512sig0l */, RISCV::SHA512SIG0L, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4619 { 3556 /* sha512sig1 */, RISCV::SHA512SIG1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, }, 4620 { 3567 /* sha512sig1h */, RISCV::SHA512SIG1H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4621 { 3579 /* sha512sig1l */, RISCV::SHA512SIG1L, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4622 { 3591 /* sha512sum0 */, RISCV::SHA512SUM0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, }, 4623 { 3602 /* sha512sum0r */, RISCV::SHA512SUM0R, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4624 { 3614 /* sha512sum1 */, RISCV::SHA512SUM1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, }, 4625 { 3625 /* sha512sum1r */, RISCV::SHA512SUM1R, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4626 { 3637 /* sinval.vma */, RISCV::SINVAL_VMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtSvinval, { MCK_GPR, MCK_GPR }, }, 4627 { 3648 /* sll */, RISCV::SLL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4628 { 3648 /* sll */, RISCV::SLLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 4629 { 3652 /* slli */, RISCV::SLLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 4630 { 3657 /* slli.uw */, RISCV::SLLI_UW, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 4631 { 3665 /* slliw */, RISCV::SLLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, }, 4632 { 3671 /* sllw */, RISCV::SLLW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4633 { 3671 /* sllw */, RISCV::SLLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, }, 4634 { 3676 /* slt */, RISCV::SLT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4635 { 3676 /* slt */, RISCV::SLTI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 4636 { 3680 /* slti */, RISCV::SLTI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 4637 { 3685 /* sltiu */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 4638 { 3691 /* sltu */, RISCV::SLTU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4639 { 3691 /* sltu */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 4640 { 3696 /* sltz */, RISCV::SLT, Convert__Reg1_0__Reg1_1__regX0, AMFBS_None, { MCK_GPR, MCK_GPR }, }, 4641 { 3701 /* sm3p0 */, RISCV::SM3P0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZksh, { MCK_GPR, MCK_GPR }, }, 4642 { 3707 /* sm3p1 */, RISCV::SM3P1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZksh, { MCK_GPR, MCK_GPR }, }, 4643 { 3713 /* sm4ed */, RISCV::SM4ED, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZksed, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, }, 4644 { 3719 /* sm4ks */, RISCV::SM4KS, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZksed, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, }, 4645 { 3725 /* snez */, RISCV::SLTU, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, }, 4646 { 3730 /* sra */, RISCV::SRA, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4647 { 3730 /* sra */, RISCV::SRAI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 4648 { 3734 /* srai */, RISCV::SRAI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 4649 { 3739 /* sraiw */, RISCV::SRAIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, }, 4650 { 3745 /* sraw */, RISCV::SRAW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4651 { 3745 /* sraw */, RISCV::SRAIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, }, 4652 { 3750 /* sret */, RISCV::SRET, Convert__imm_95_0__imm_95_0, AMFBS_None, { }, }, 4653 { 3755 /* srl */, RISCV::SRL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4654 { 3755 /* srl */, RISCV::SRLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 4655 { 3759 /* srli */, RISCV::SRLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 4656 { 3764 /* srliw */, RISCV::SRLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, }, 4657 { 3770 /* srlw */, RISCV::SRLW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4658 { 3770 /* srlw */, RISCV::SRLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, }, 4659 { 3775 /* sub */, RISCV::SUB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4660 { 3779 /* subw */, RISCV::SUBW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 4661 { 3784 /* sw */, RISCV::PseudoSW, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, }, 4662 { 3784 /* sw */, RISCV::SW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, }, 4663 { 3784 /* sw */, RISCV::SW, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 4664 { 3787 /* tail */, RISCV::PseudoTAIL, Convert__CallSymbol1_0, AMFBS_None, { MCK_CallSymbol }, }, 4665 { 3792 /* th.vmaqa.vv */, RISCV::THVdotVMAQA_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4666 { 3804 /* th.vmaqa.vx */, RISCV::THVdotVMAQA_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4667 { 3816 /* th.vmaqasu.vv */, RISCV::THVdotVMAQASU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4668 { 3830 /* th.vmaqasu.vx */, RISCV::THVdotVMAQASU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4669 { 3844 /* th.vmaqau.vv */, RISCV::THVdotVMAQAU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4670 { 3857 /* th.vmaqau.vx */, RISCV::THVdotVMAQAU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4671 { 3870 /* th.vmaqaus.vx */, RISCV::THVdotVMAQAUS_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4672 { 3884 /* unimp */, RISCV::UNIMP, Convert_NoOperands, AMFBS_None, { }, }, 4673 { 3890 /* unzip */, RISCV::UNZIP_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbkb_IsRV32, { MCK_GPR, MCK_GPR }, }, 4674 { 3896 /* uret */, RISCV::URET, Convert__imm_95_0__imm_95_0, AMFBS_None, { }, }, 4675 { 3901 /* vaadd.vv */, RISCV::VAADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4676 { 3910 /* vaadd.vx */, RISCV::VAADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4677 { 3919 /* vaaddu.vv */, RISCV::VAADDU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4678 { 3929 /* vaaddu.vx */, RISCV::VAADDU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4679 { 3939 /* vadc.vim */, RISCV::VADC_VIM, Convert__Reg1_0__Reg1_1__SImm51_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_VMV0 }, }, 4680 { 3948 /* vadc.vvm */, RISCV::VADC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_VMV0 }, }, 4681 { 3957 /* vadc.vxm */, RISCV::VADC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_VMV0 }, }, 4682 { 3966 /* vadd.vi */, RISCV::VADD_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, }, 4683 { 3974 /* vadd.vv */, RISCV::VADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4684 { 3982 /* vadd.vx */, RISCV::VADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4685 { 3990 /* vand.vi */, RISCV::VAND_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, }, 4686 { 3998 /* vand.vv */, RISCV::VAND_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4687 { 4006 /* vand.vx */, RISCV::VAND_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4688 { 4014 /* vasub.vv */, RISCV::VASUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4689 { 4023 /* vasub.vx */, RISCV::VASUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4690 { 4032 /* vasubu.vv */, RISCV::VASUBU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4691 { 4042 /* vasubu.vx */, RISCV::VASUBU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4692 { 4052 /* vcompress.vm */, RISCV::VCOMPRESS_VM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, }, 4693 { 4065 /* vcpop.m */, RISCV::VCPOP_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4694 { 4073 /* vdiv.vv */, RISCV::VDIV_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4695 { 4081 /* vdiv.vx */, RISCV::VDIV_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4696 { 4089 /* vdivu.vv */, RISCV::VDIVU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4697 { 4098 /* vdivu.vx */, RISCV::VDIVU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4698 { 4107 /* vfabs.v */, RISCV::VFSGNJX_VV, Convert__Reg1_0__Reg1_1__Reg1_1__reg0, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM }, }, 4699 { 4107 /* vfabs.v */, RISCV::VFSGNJX_VV, Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4700 { 4115 /* vfadd.vf */, RISCV::VFADD_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 4701 { 4124 /* vfadd.vv */, RISCV::VFADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4702 { 4133 /* vfclass.v */, RISCV::VFCLASS_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4703 { 4143 /* vfcvt.f.x.v */, RISCV::VFCVT_F_X_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4704 { 4155 /* vfcvt.f.xu.v */, RISCV::VFCVT_F_XU_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4705 { 4168 /* vfcvt.rtz.x.f.v */, RISCV::VFCVT_RTZ_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4706 { 4184 /* vfcvt.rtz.xu.f.v */, RISCV::VFCVT_RTZ_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4707 { 4201 /* vfcvt.x.f.v */, RISCV::VFCVT_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4708 { 4213 /* vfcvt.xu.f.v */, RISCV::VFCVT_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4709 { 4226 /* vfdiv.vf */, RISCV::VFDIV_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 4710 { 4235 /* vfdiv.vv */, RISCV::VFDIV_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4711 { 4244 /* vfirst.m */, RISCV::VFIRST_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4712 { 4253 /* vfmacc.vf */, RISCV::VFMACC_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4713 { 4263 /* vfmacc.vv */, RISCV::VFMACC_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4714 { 4273 /* vfmadd.vf */, RISCV::VFMADD_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4715 { 4283 /* vfmadd.vv */, RISCV::VFMADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4716 { 4293 /* vfmax.vf */, RISCV::VFMAX_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 4717 { 4302 /* vfmax.vv */, RISCV::VFMAX_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4718 { 4311 /* vfmerge.vfm */, RISCV::VFMERGE_VFM, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_VMV0 }, }, 4719 { 4323 /* vfmin.vf */, RISCV::VFMIN_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 4720 { 4332 /* vfmin.vv */, RISCV::VFMIN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4721 { 4341 /* vfmsac.vf */, RISCV::VFMSAC_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4722 { 4351 /* vfmsac.vv */, RISCV::VFMSAC_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4723 { 4361 /* vfmsub.vf */, RISCV::VFMSUB_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4724 { 4371 /* vfmsub.vv */, RISCV::VFMSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4725 { 4381 /* vfmul.vf */, RISCV::VFMUL_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 4726 { 4390 /* vfmul.vv */, RISCV::VFMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4727 { 4399 /* vfmv.f.s */, RISCV::VFMV_F_S, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructionsAnyF, { MCK_FPR32, MCK_VM }, }, 4728 { 4408 /* vfmv.s.f */, RISCV::VFMV_S_F, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32 }, }, 4729 { 4417 /* vfmv.v.f */, RISCV::VFMV_V_F, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32 }, }, 4730 { 4426 /* vfncvt.f.f.w */, RISCV::VFNCVT_F_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4731 { 4439 /* vfncvt.f.x.w */, RISCV::VFNCVT_F_X_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4732 { 4452 /* vfncvt.f.xu.w */, RISCV::VFNCVT_F_XU_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4733 { 4466 /* vfncvt.rod.f.f.w */, RISCV::VFNCVT_ROD_F_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4734 { 4483 /* vfncvt.rtz.x.f.w */, RISCV::VFNCVT_RTZ_X_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4735 { 4500 /* vfncvt.rtz.xu.f.w */, RISCV::VFNCVT_RTZ_XU_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4736 { 4518 /* vfncvt.x.f.w */, RISCV::VFNCVT_X_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4737 { 4531 /* vfncvt.xu.f.w */, RISCV::VFNCVT_XU_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4738 { 4545 /* vfneg.v */, RISCV::VFSGNJN_VV, Convert__Reg1_0__Reg1_1__Reg1_1__reg0, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM }, }, 4739 { 4545 /* vfneg.v */, RISCV::VFSGNJN_VV, Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4740 { 4553 /* vfnmacc.vf */, RISCV::VFNMACC_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4741 { 4564 /* vfnmacc.vv */, RISCV::VFNMACC_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4742 { 4575 /* vfnmadd.vf */, RISCV::VFNMADD_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4743 { 4586 /* vfnmadd.vv */, RISCV::VFNMADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4744 { 4597 /* vfnmsac.vf */, RISCV::VFNMSAC_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4745 { 4608 /* vfnmsac.vv */, RISCV::VFNMSAC_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4746 { 4619 /* vfnmsub.vf */, RISCV::VFNMSUB_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4747 { 4630 /* vfnmsub.vv */, RISCV::VFNMSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4748 { 4641 /* vfrdiv.vf */, RISCV::VFRDIV_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 4749 { 4651 /* vfrec7.v */, RISCV::VFREC7_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4750 { 4660 /* vfredmax.vs */, RISCV::VFREDMAX_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4751 { 4672 /* vfredmin.vs */, RISCV::VFREDMIN_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4752 { 4684 /* vfredosum.vs */, RISCV::VFREDOSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4753 { 4697 /* vfredsum.vs */, RISCV::VFREDUSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4754 { 4709 /* vfredusum.vs */, RISCV::VFREDUSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4755 { 4722 /* vfrsqrt7.v */, RISCV::VFRSQRT7_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4756 { 4733 /* vfrsub.vf */, RISCV::VFRSUB_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 4757 { 4743 /* vfsgnj.vf */, RISCV::VFSGNJ_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 4758 { 4753 /* vfsgnj.vv */, RISCV::VFSGNJ_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4759 { 4763 /* vfsgnjn.vf */, RISCV::VFSGNJN_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 4760 { 4774 /* vfsgnjn.vv */, RISCV::VFSGNJN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4761 { 4785 /* vfsgnjx.vf */, RISCV::VFSGNJX_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 4762 { 4796 /* vfsgnjx.vv */, RISCV::VFSGNJX_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4763 { 4807 /* vfslide1down.vf */, RISCV::VFSLIDE1DOWN_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 4764 { 4823 /* vfslide1up.vf */, RISCV::VFSLIDE1UP_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 4765 { 4837 /* vfsqrt.v */, RISCV::VFSQRT_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4766 { 4846 /* vfsub.vf */, RISCV::VFSUB_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 4767 { 4855 /* vfsub.vv */, RISCV::VFSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4768 { 4864 /* vfwadd.vf */, RISCV::VFWADD_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 4769 { 4874 /* vfwadd.vv */, RISCV::VFWADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4770 { 4884 /* vfwadd.wf */, RISCV::VFWADD_WF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 4771 { 4894 /* vfwadd.wv */, RISCV::VFWADD_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4772 { 4904 /* vfwcvt.f.f.v */, RISCV::VFWCVT_F_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4773 { 4917 /* vfwcvt.f.x.v */, RISCV::VFWCVT_F_X_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4774 { 4930 /* vfwcvt.f.xu.v */, RISCV::VFWCVT_F_XU_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4775 { 4944 /* vfwcvt.rtz.x.f.v */, RISCV::VFWCVT_RTZ_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4776 { 4961 /* vfwcvt.rtz.xu.f.v */, RISCV::VFWCVT_RTZ_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4777 { 4979 /* vfwcvt.x.f.v */, RISCV::VFWCVT_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4778 { 4992 /* vfwcvt.xu.f.v */, RISCV::VFWCVT_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4779 { 5006 /* vfwmacc.vf */, RISCV::VFWMACC_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4780 { 5017 /* vfwmacc.vv */, RISCV::VFWMACC_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4781 { 5028 /* vfwmsac.vf */, RISCV::VFWMSAC_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4782 { 5039 /* vfwmsac.vv */, RISCV::VFWMSAC_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4783 { 5050 /* vfwmul.vf */, RISCV::VFWMUL_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 4784 { 5060 /* vfwmul.vv */, RISCV::VFWMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4785 { 5070 /* vfwnmacc.vf */, RISCV::VFWNMACC_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4786 { 5082 /* vfwnmacc.vv */, RISCV::VFWNMACC_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4787 { 5094 /* vfwnmsac.vf */, RISCV::VFWNMSAC_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4788 { 5106 /* vfwnmsac.vv */, RISCV::VFWNMSAC_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4789 { 5118 /* vfwredosum.vs */, RISCV::VFWREDOSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4790 { 5132 /* vfwredsum.vs */, RISCV::VFWREDUSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4791 { 5145 /* vfwredusum.vs */, RISCV::VFWREDUSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4792 { 5159 /* vfwsub.vf */, RISCV::VFWSUB_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 4793 { 5169 /* vfwsub.vv */, RISCV::VFWSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4794 { 5179 /* vfwsub.wf */, RISCV::VFWSUB_WF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 4795 { 5189 /* vfwsub.wv */, RISCV::VFWSUB_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4796 { 5199 /* vid.v */, RISCV::VID_V, Convert__Reg1_0__RVVMaskRegOpOperand1_1, AMFBS_HasVInstructions, { MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4797 { 5205 /* viota.m */, RISCV::VIOTA_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4798 { 5213 /* vl1r.v */, RISCV::VL1RE8_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_ }, }, 4799 { 5220 /* vl1re16.v */, RISCV::VL1RE16_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_ }, }, 4800 { 5230 /* vl1re32.v */, RISCV::VL1RE32_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_ }, }, 4801 { 5240 /* vl1re64.v */, RISCV::VL1RE64_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_ }, }, 4802 { 5250 /* vl1re8.v */, RISCV::VL1RE8_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_ }, }, 4803 { 5259 /* vl2r.v */, RISCV::VL2RE8_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VRM2, MCK__40_, MCK_GPR, MCK__41_ }, }, 4804 { 5266 /* vl2re16.v */, RISCV::VL2RE16_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VRM2, MCK__40_, MCK_GPR, MCK__41_ }, }, 4805 { 5276 /* vl2re32.v */, RISCV::VL2RE32_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VRM2, MCK__40_, MCK_GPR, MCK__41_ }, }, 4806 { 5286 /* vl2re64.v */, RISCV::VL2RE64_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructionsI64, { MCK_VRM2, MCK__40_, MCK_GPR, MCK__41_ }, }, 4807 { 5296 /* vl2re8.v */, RISCV::VL2RE8_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VRM2, MCK__40_, MCK_GPR, MCK__41_ }, }, 4808 { 5305 /* vl4r.v */, RISCV::VL4RE8_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VRM4, MCK__40_, MCK_GPR, MCK__41_ }, }, 4809 { 5312 /* vl4re16.v */, RISCV::VL4RE16_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VRM4, MCK__40_, MCK_GPR, MCK__41_ }, }, 4810 { 5322 /* vl4re32.v */, RISCV::VL4RE32_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VRM4, MCK__40_, MCK_GPR, MCK__41_ }, }, 4811 { 5332 /* vl4re64.v */, RISCV::VL4RE64_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructionsI64, { MCK_VRM4, MCK__40_, MCK_GPR, MCK__41_ }, }, 4812 { 5342 /* vl4re8.v */, RISCV::VL4RE8_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VRM4, MCK__40_, MCK_GPR, MCK__41_ }, }, 4813 { 5351 /* vl8r.v */, RISCV::VL8RE8_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VRM8, MCK__40_, MCK_GPR, MCK__41_ }, }, 4814 { 5358 /* vl8re16.v */, RISCV::VL8RE16_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VRM8, MCK__40_, MCK_GPR, MCK__41_ }, }, 4815 { 5368 /* vl8re32.v */, RISCV::VL8RE32_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VRM8, MCK__40_, MCK_GPR, MCK__41_ }, }, 4816 { 5378 /* vl8re64.v */, RISCV::VL8RE64_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructionsI64, { MCK_VRM8, MCK__40_, MCK_GPR, MCK__41_ }, }, 4817 { 5388 /* vl8re8.v */, RISCV::VL8RE8_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VRM8, MCK__40_, MCK_GPR, MCK__41_ }, }, 4818 { 5397 /* vle1.v */, RISCV::VLM_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_ }, }, 4819 { 5404 /* vle16.v */, RISCV::VLE16_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4820 { 5412 /* vle16ff.v */, RISCV::VLE16FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4821 { 5422 /* vle32.v */, RISCV::VLE32_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4822 { 5430 /* vle32ff.v */, RISCV::VLE32FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4823 { 5440 /* vle64.v */, RISCV::VLE64_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4824 { 5448 /* vle64ff.v */, RISCV::VLE64FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4825 { 5458 /* vle8.v */, RISCV::VLE8_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4826 { 5465 /* vle8ff.v */, RISCV::VLE8FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4827 { 5474 /* vlm.v */, RISCV::VLM_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_ }, }, 4828 { 5480 /* vloxei16.v */, RISCV::VLOXEI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4829 { 5491 /* vloxei32.v */, RISCV::VLOXEI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4830 { 5502 /* vloxei64.v */, RISCV::VLOXEI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4831 { 5513 /* vloxei8.v */, RISCV::VLOXEI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4832 { 5523 /* vloxseg2ei16.v */, RISCV::VLOXSEG2EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4833 { 5538 /* vloxseg2ei32.v */, RISCV::VLOXSEG2EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4834 { 5553 /* vloxseg2ei64.v */, RISCV::VLOXSEG2EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4835 { 5568 /* vloxseg2ei8.v */, RISCV::VLOXSEG2EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4836 { 5582 /* vloxseg3ei16.v */, RISCV::VLOXSEG3EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4837 { 5597 /* vloxseg3ei32.v */, RISCV::VLOXSEG3EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4838 { 5612 /* vloxseg3ei64.v */, RISCV::VLOXSEG3EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4839 { 5627 /* vloxseg3ei8.v */, RISCV::VLOXSEG3EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4840 { 5641 /* vloxseg4ei16.v */, RISCV::VLOXSEG4EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4841 { 5656 /* vloxseg4ei32.v */, RISCV::VLOXSEG4EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4842 { 5671 /* vloxseg4ei64.v */, RISCV::VLOXSEG4EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4843 { 5686 /* vloxseg4ei8.v */, RISCV::VLOXSEG4EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4844 { 5700 /* vloxseg5ei16.v */, RISCV::VLOXSEG5EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4845 { 5715 /* vloxseg5ei32.v */, RISCV::VLOXSEG5EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4846 { 5730 /* vloxseg5ei64.v */, RISCV::VLOXSEG5EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4847 { 5745 /* vloxseg5ei8.v */, RISCV::VLOXSEG5EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4848 { 5759 /* vloxseg6ei16.v */, RISCV::VLOXSEG6EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4849 { 5774 /* vloxseg6ei32.v */, RISCV::VLOXSEG6EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4850 { 5789 /* vloxseg6ei64.v */, RISCV::VLOXSEG6EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4851 { 5804 /* vloxseg6ei8.v */, RISCV::VLOXSEG6EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4852 { 5818 /* vloxseg7ei16.v */, RISCV::VLOXSEG7EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4853 { 5833 /* vloxseg7ei32.v */, RISCV::VLOXSEG7EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4854 { 5848 /* vloxseg7ei64.v */, RISCV::VLOXSEG7EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4855 { 5863 /* vloxseg7ei8.v */, RISCV::VLOXSEG7EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4856 { 5877 /* vloxseg8ei16.v */, RISCV::VLOXSEG8EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4857 { 5892 /* vloxseg8ei32.v */, RISCV::VLOXSEG8EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4858 { 5907 /* vloxseg8ei64.v */, RISCV::VLOXSEG8EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4859 { 5922 /* vloxseg8ei8.v */, RISCV::VLOXSEG8EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4860 { 5936 /* vlse16.v */, RISCV::VLSE16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4861 { 5945 /* vlse32.v */, RISCV::VLSE32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4862 { 5954 /* vlse64.v */, RISCV::VLSE64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4863 { 5963 /* vlse8.v */, RISCV::VLSE8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4864 { 5971 /* vlseg2e16.v */, RISCV::VLSEG2E16_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4865 { 5983 /* vlseg2e16ff.v */, RISCV::VLSEG2E16FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4866 { 5997 /* vlseg2e32.v */, RISCV::VLSEG2E32_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4867 { 6009 /* vlseg2e32ff.v */, RISCV::VLSEG2E32FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4868 { 6023 /* vlseg2e64.v */, RISCV::VLSEG2E64_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4869 { 6035 /* vlseg2e64ff.v */, RISCV::VLSEG2E64FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4870 { 6049 /* vlseg2e8.v */, RISCV::VLSEG2E8_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4871 { 6060 /* vlseg2e8ff.v */, RISCV::VLSEG2E8FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4872 { 6073 /* vlseg3e16.v */, RISCV::VLSEG3E16_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4873 { 6085 /* vlseg3e16ff.v */, RISCV::VLSEG3E16FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4874 { 6099 /* vlseg3e32.v */, RISCV::VLSEG3E32_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4875 { 6111 /* vlseg3e32ff.v */, RISCV::VLSEG3E32FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4876 { 6125 /* vlseg3e64.v */, RISCV::VLSEG3E64_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4877 { 6137 /* vlseg3e64ff.v */, RISCV::VLSEG3E64FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4878 { 6151 /* vlseg3e8.v */, RISCV::VLSEG3E8_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4879 { 6162 /* vlseg3e8ff.v */, RISCV::VLSEG3E8FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4880 { 6175 /* vlseg4e16.v */, RISCV::VLSEG4E16_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4881 { 6187 /* vlseg4e16ff.v */, RISCV::VLSEG4E16FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4882 { 6201 /* vlseg4e32.v */, RISCV::VLSEG4E32_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4883 { 6213 /* vlseg4e32ff.v */, RISCV::VLSEG4E32FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4884 { 6227 /* vlseg4e64.v */, RISCV::VLSEG4E64_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4885 { 6239 /* vlseg4e64ff.v */, RISCV::VLSEG4E64FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4886 { 6253 /* vlseg4e8.v */, RISCV::VLSEG4E8_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4887 { 6264 /* vlseg4e8ff.v */, RISCV::VLSEG4E8FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4888 { 6277 /* vlseg5e16.v */, RISCV::VLSEG5E16_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4889 { 6289 /* vlseg5e16ff.v */, RISCV::VLSEG5E16FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4890 { 6303 /* vlseg5e32.v */, RISCV::VLSEG5E32_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4891 { 6315 /* vlseg5e32ff.v */, RISCV::VLSEG5E32FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4892 { 6329 /* vlseg5e64.v */, RISCV::VLSEG5E64_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4893 { 6341 /* vlseg5e64ff.v */, RISCV::VLSEG5E64FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4894 { 6355 /* vlseg5e8.v */, RISCV::VLSEG5E8_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4895 { 6366 /* vlseg5e8ff.v */, RISCV::VLSEG5E8FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4896 { 6379 /* vlseg6e16.v */, RISCV::VLSEG6E16_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4897 { 6391 /* vlseg6e16ff.v */, RISCV::VLSEG6E16FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4898 { 6405 /* vlseg6e32.v */, RISCV::VLSEG6E32_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4899 { 6417 /* vlseg6e32ff.v */, RISCV::VLSEG6E32FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4900 { 6431 /* vlseg6e64.v */, RISCV::VLSEG6E64_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4901 { 6443 /* vlseg6e64ff.v */, RISCV::VLSEG6E64FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4902 { 6457 /* vlseg6e8.v */, RISCV::VLSEG6E8_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4903 { 6468 /* vlseg6e8ff.v */, RISCV::VLSEG6E8FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4904 { 6481 /* vlseg7e16.v */, RISCV::VLSEG7E16_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4905 { 6493 /* vlseg7e16ff.v */, RISCV::VLSEG7E16FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4906 { 6507 /* vlseg7e32.v */, RISCV::VLSEG7E32_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4907 { 6519 /* vlseg7e32ff.v */, RISCV::VLSEG7E32FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4908 { 6533 /* vlseg7e64.v */, RISCV::VLSEG7E64_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4909 { 6545 /* vlseg7e64ff.v */, RISCV::VLSEG7E64FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4910 { 6559 /* vlseg7e8.v */, RISCV::VLSEG7E8_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4911 { 6570 /* vlseg7e8ff.v */, RISCV::VLSEG7E8FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4912 { 6583 /* vlseg8e16.v */, RISCV::VLSEG8E16_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4913 { 6595 /* vlseg8e16ff.v */, RISCV::VLSEG8E16FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4914 { 6609 /* vlseg8e32.v */, RISCV::VLSEG8E32_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4915 { 6621 /* vlseg8e32ff.v */, RISCV::VLSEG8E32FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4916 { 6635 /* vlseg8e64.v */, RISCV::VLSEG8E64_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4917 { 6647 /* vlseg8e64ff.v */, RISCV::VLSEG8E64FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4918 { 6661 /* vlseg8e8.v */, RISCV::VLSEG8E8_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4919 { 6672 /* vlseg8e8ff.v */, RISCV::VLSEG8E8FF_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 4920 { 6685 /* vlsseg2e16.v */, RISCV::VLSSEG2E16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4921 { 6698 /* vlsseg2e32.v */, RISCV::VLSSEG2E32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4922 { 6711 /* vlsseg2e64.v */, RISCV::VLSSEG2E64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4923 { 6724 /* vlsseg2e8.v */, RISCV::VLSSEG2E8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4924 { 6736 /* vlsseg3e16.v */, RISCV::VLSSEG3E16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4925 { 6749 /* vlsseg3e32.v */, RISCV::VLSSEG3E32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4926 { 6762 /* vlsseg3e64.v */, RISCV::VLSSEG3E64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4927 { 6775 /* vlsseg3e8.v */, RISCV::VLSSEG3E8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4928 { 6787 /* vlsseg4e16.v */, RISCV::VLSSEG4E16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4929 { 6800 /* vlsseg4e32.v */, RISCV::VLSSEG4E32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4930 { 6813 /* vlsseg4e64.v */, RISCV::VLSSEG4E64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4931 { 6826 /* vlsseg4e8.v */, RISCV::VLSSEG4E8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4932 { 6838 /* vlsseg5e16.v */, RISCV::VLSSEG5E16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4933 { 6851 /* vlsseg5e32.v */, RISCV::VLSSEG5E32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4934 { 6864 /* vlsseg5e64.v */, RISCV::VLSSEG5E64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4935 { 6877 /* vlsseg5e8.v */, RISCV::VLSSEG5E8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4936 { 6889 /* vlsseg6e16.v */, RISCV::VLSSEG6E16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4937 { 6902 /* vlsseg6e32.v */, RISCV::VLSSEG6E32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4938 { 6915 /* vlsseg6e64.v */, RISCV::VLSSEG6E64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4939 { 6928 /* vlsseg6e8.v */, RISCV::VLSSEG6E8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4940 { 6940 /* vlsseg7e16.v */, RISCV::VLSSEG7E16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4941 { 6953 /* vlsseg7e32.v */, RISCV::VLSSEG7E32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4942 { 6966 /* vlsseg7e64.v */, RISCV::VLSSEG7E64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4943 { 6979 /* vlsseg7e8.v */, RISCV::VLSSEG7E8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4944 { 6991 /* vlsseg8e16.v */, RISCV::VLSSEG8E16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4945 { 7004 /* vlsseg8e32.v */, RISCV::VLSSEG8E32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4946 { 7017 /* vlsseg8e64.v */, RISCV::VLSSEG8E64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4947 { 7030 /* vlsseg8e8.v */, RISCV::VLSSEG8E8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4948 { 7042 /* vluxei16.v */, RISCV::VLUXEI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4949 { 7053 /* vluxei32.v */, RISCV::VLUXEI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4950 { 7064 /* vluxei64.v */, RISCV::VLUXEI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4951 { 7075 /* vluxei8.v */, RISCV::VLUXEI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4952 { 7085 /* vluxseg2ei16.v */, RISCV::VLUXSEG2EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4953 { 7100 /* vluxseg2ei32.v */, RISCV::VLUXSEG2EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4954 { 7115 /* vluxseg2ei64.v */, RISCV::VLUXSEG2EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4955 { 7130 /* vluxseg2ei8.v */, RISCV::VLUXSEG2EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4956 { 7144 /* vluxseg3ei16.v */, RISCV::VLUXSEG3EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4957 { 7159 /* vluxseg3ei32.v */, RISCV::VLUXSEG3EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4958 { 7174 /* vluxseg3ei64.v */, RISCV::VLUXSEG3EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4959 { 7189 /* vluxseg3ei8.v */, RISCV::VLUXSEG3EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4960 { 7203 /* vluxseg4ei16.v */, RISCV::VLUXSEG4EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4961 { 7218 /* vluxseg4ei32.v */, RISCV::VLUXSEG4EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4962 { 7233 /* vluxseg4ei64.v */, RISCV::VLUXSEG4EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4963 { 7248 /* vluxseg4ei8.v */, RISCV::VLUXSEG4EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4964 { 7262 /* vluxseg5ei16.v */, RISCV::VLUXSEG5EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4965 { 7277 /* vluxseg5ei32.v */, RISCV::VLUXSEG5EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4966 { 7292 /* vluxseg5ei64.v */, RISCV::VLUXSEG5EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4967 { 7307 /* vluxseg5ei8.v */, RISCV::VLUXSEG5EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4968 { 7321 /* vluxseg6ei16.v */, RISCV::VLUXSEG6EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4969 { 7336 /* vluxseg6ei32.v */, RISCV::VLUXSEG6EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4970 { 7351 /* vluxseg6ei64.v */, RISCV::VLUXSEG6EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4971 { 7366 /* vluxseg6ei8.v */, RISCV::VLUXSEG6EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4972 { 7380 /* vluxseg7ei16.v */, RISCV::VLUXSEG7EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4973 { 7395 /* vluxseg7ei32.v */, RISCV::VLUXSEG7EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4974 { 7410 /* vluxseg7ei64.v */, RISCV::VLUXSEG7EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4975 { 7425 /* vluxseg7ei8.v */, RISCV::VLUXSEG7EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4976 { 7439 /* vluxseg8ei16.v */, RISCV::VLUXSEG8EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4977 { 7454 /* vluxseg8ei32.v */, RISCV::VLUXSEG8EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4978 { 7469 /* vluxseg8ei64.v */, RISCV::VLUXSEG8EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4979 { 7484 /* vluxseg8ei8.v */, RISCV::VLUXSEG8EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4980 { 7498 /* vmacc.vv */, RISCV::VMACC_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4981 { 7507 /* vmacc.vx */, RISCV::VMACC_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4982 { 7516 /* vmadc.vi */, RISCV::VMADC_VI, Convert__Reg1_0__Reg1_1__SImm51_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5 }, }, 4983 { 7525 /* vmadc.vim */, RISCV::VMADC_VIM, Convert__Reg1_0__Reg1_1__SImm51_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_VMV0 }, }, 4984 { 7535 /* vmadc.vv */, RISCV::VMADC_VV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, }, 4985 { 7544 /* vmadc.vvm */, RISCV::VMADC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_VMV0 }, }, 4986 { 7554 /* vmadc.vx */, RISCV::VMADC_VX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR }, }, 4987 { 7563 /* vmadc.vxm */, RISCV::VMADC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_VMV0 }, }, 4988 { 7573 /* vmadd.vv */, RISCV::VMADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4989 { 7582 /* vmadd.vx */, RISCV::VMADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4990 { 7591 /* vmand.mm */, RISCV::VMAND_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, }, 4991 { 7600 /* vmandn.mm */, RISCV::VMANDN_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, }, 4992 { 7610 /* vmandnot.mm */, RISCV::VMANDN_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, }, 4993 { 7622 /* vmax.vv */, RISCV::VMAX_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4994 { 7630 /* vmax.vx */, RISCV::VMAX_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4995 { 7638 /* vmaxu.vv */, RISCV::VMAXU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 4996 { 7647 /* vmaxu.vx */, RISCV::VMAXU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 4997 { 7656 /* vmclr.m */, RISCV::VMXOR_MM, Convert__Reg1_0__Reg1_0__Reg1_0, AMFBS_HasVInstructions, { MCK_VM }, }, 4998 { 7664 /* vmerge.vim */, RISCV::VMERGE_VIM, Convert__Reg1_0__Reg1_1__SImm51_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_VMV0 }, }, 4999 { 7675 /* vmerge.vvm */, RISCV::VMERGE_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_VMV0 }, }, 5000 { 7686 /* vmerge.vxm */, RISCV::VMERGE_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_VMV0 }, }, 5001 { 7697 /* vmfeq.vf */, RISCV::VMFEQ_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 5002 { 7706 /* vmfeq.vv */, RISCV::VMFEQ_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5003 { 7715 /* vmfge.vf */, RISCV::VMFGE_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 5004 { 7724 /* vmfge.vv */, RISCV::VMFLE_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5005 { 7733 /* vmfgt.vf */, RISCV::VMFGT_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 5006 { 7742 /* vmfgt.vv */, RISCV::VMFLT_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5007 { 7751 /* vmfle.vf */, RISCV::VMFLE_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 5008 { 7760 /* vmfle.vv */, RISCV::VMFLE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5009 { 7769 /* vmflt.vf */, RISCV::VMFLT_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 5010 { 7778 /* vmflt.vv */, RISCV::VMFLT_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5011 { 7787 /* vmfne.vf */, RISCV::VMFNE_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, }, 5012 { 7796 /* vmfne.vv */, RISCV::VMFNE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5013 { 7805 /* vmin.vv */, RISCV::VMIN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5014 { 7813 /* vmin.vx */, RISCV::VMIN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5015 { 7821 /* vminu.vv */, RISCV::VMINU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5016 { 7830 /* vminu.vx */, RISCV::VMINU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5017 { 7839 /* vmmv.m */, RISCV::VMAND_MM, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasVInstructions, { MCK_VM, MCK_VM }, }, 5018 { 7846 /* vmnand.mm */, RISCV::VMNAND_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, }, 5019 { 7856 /* vmnor.mm */, RISCV::VMNOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, }, 5020 { 7865 /* vmnot.m */, RISCV::VMNAND_MM, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasVInstructions, { MCK_VM, MCK_VM }, }, 5021 { 7873 /* vmor.mm */, RISCV::VMOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, }, 5022 { 7881 /* vmorn.mm */, RISCV::VMORN_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, }, 5023 { 7890 /* vmornot.mm */, RISCV::VMORN_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, }, 5024 { 7901 /* vmsbc.vv */, RISCV::VMSBC_VV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, }, 5025 { 7910 /* vmsbc.vvm */, RISCV::VMSBC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_VMV0 }, }, 5026 { 7920 /* vmsbc.vx */, RISCV::VMSBC_VX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR }, }, 5027 { 7929 /* vmsbc.vxm */, RISCV::VMSBC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_VMV0 }, }, 5028 { 7939 /* vmsbf.m */, RISCV::VMSBF_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5029 { 7947 /* vmseq.vi */, RISCV::VMSEQ_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, }, 5030 { 7956 /* vmseq.vv */, RISCV::VMSEQ_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5031 { 7965 /* vmseq.vx */, RISCV::VMSEQ_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5032 { 7974 /* vmset.m */, RISCV::VMXNOR_MM, Convert__Reg1_0__Reg1_0__Reg1_0, AMFBS_HasVInstructions, { MCK_VM }, }, 5033 { 7982 /* vmsge.vi */, RISCV::PseudoVMSGE_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, }, 5034 { 7991 /* vmsge.vv */, RISCV::VMSLE_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5035 { 8000 /* vmsge.vx */, RISCV::PseudoVMSGE_VX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR }, }, 5036 { 8000 /* vmsge.vx */, RISCV::PseudoVMSGE_VX_M, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VRNoV0, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5037 { 8000 /* vmsge.vx */, RISCV::PseudoVMSGE_VX_M_T, Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand, MCK_VRNoV0 }, }, 5038 { 8009 /* vmsgeu.vi */, RISCV::PseudoVMSGEU_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, }, 5039 { 8019 /* vmsgeu.vv */, RISCV::VMSLEU_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5040 { 8029 /* vmsgeu.vx */, RISCV::PseudoVMSGEU_VX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR }, }, 5041 { 8029 /* vmsgeu.vx */, RISCV::PseudoVMSGEU_VX_M, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VRNoV0, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5042 { 8029 /* vmsgeu.vx */, RISCV::PseudoVMSGEU_VX_M_T, Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand, MCK_VRNoV0 }, }, 5043 { 8039 /* vmsgt.vi */, RISCV::VMSGT_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, }, 5044 { 8048 /* vmsgt.vv */, RISCV::VMSLT_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5045 { 8057 /* vmsgt.vx */, RISCV::VMSGT_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5046 { 8066 /* vmsgtu.vi */, RISCV::VMSGTU_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, }, 5047 { 8076 /* vmsgtu.vv */, RISCV::VMSLTU_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5048 { 8086 /* vmsgtu.vx */, RISCV::VMSGTU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5049 { 8096 /* vmsif.m */, RISCV::VMSIF_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5050 { 8104 /* vmsle.vi */, RISCV::VMSLE_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, }, 5051 { 8113 /* vmsle.vv */, RISCV::VMSLE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5052 { 8122 /* vmsle.vx */, RISCV::VMSLE_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5053 { 8131 /* vmsleu.vi */, RISCV::VMSLEU_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, }, 5054 { 8141 /* vmsleu.vv */, RISCV::VMSLEU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5055 { 8151 /* vmsleu.vx */, RISCV::VMSLEU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5056 { 8161 /* vmslt.vi */, RISCV::PseudoVMSLT_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, }, 5057 { 8170 /* vmslt.vv */, RISCV::VMSLT_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5058 { 8179 /* vmslt.vx */, RISCV::VMSLT_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5059 { 8188 /* vmsltu.vi */, RISCV::PseudoVMSLTU_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, }, 5060 { 8198 /* vmsltu.vv */, RISCV::VMSLTU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5061 { 8208 /* vmsltu.vx */, RISCV::VMSLTU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5062 { 8218 /* vmsne.vi */, RISCV::VMSNE_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, }, 5063 { 8227 /* vmsne.vv */, RISCV::VMSNE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5064 { 8236 /* vmsne.vx */, RISCV::VMSNE_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5065 { 8245 /* vmsof.m */, RISCV::VMSOF_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5066 { 8253 /* vmul.vv */, RISCV::VMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5067 { 8261 /* vmul.vx */, RISCV::VMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5068 { 8269 /* vmulh.vv */, RISCV::VMULH_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5069 { 8278 /* vmulh.vx */, RISCV::VMULH_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5070 { 8287 /* vmulhsu.vv */, RISCV::VMULHSU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5071 { 8298 /* vmulhsu.vx */, RISCV::VMULHSU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5072 { 8309 /* vmulhu.vv */, RISCV::VMULHU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5073 { 8319 /* vmulhu.vx */, RISCV::VMULHU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5074 { 8329 /* vmv.s.x */, RISCV::VMV_S_X, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasVInstructions, { MCK_VM, MCK_GPR }, }, 5075 { 8337 /* vmv.v.i */, RISCV::VMV_V_I, Convert__Reg1_0__SImm51_1, AMFBS_HasVInstructions, { MCK_VM, MCK_SImm5 }, }, 5076 { 8345 /* vmv.v.v */, RISCV::VMV_V_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VM, MCK_VM }, }, 5077 { 8353 /* vmv.v.x */, RISCV::VMV_V_X, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VM, MCK_GPR }, }, 5078 { 8361 /* vmv.x.s */, RISCV::VMV_X_S, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_GPR, MCK_VM }, }, 5079 { 8369 /* vmv1r.v */, RISCV::VMV1R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VM, MCK_VM }, }, 5080 { 8377 /* vmv2r.v */, RISCV::VMV2R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_VRM2 }, }, 5081 { 8385 /* vmv4r.v */, RISCV::VMV4R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_VRM4 }, }, 5082 { 8393 /* vmv8r.v */, RISCV::VMV8R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_VRM8 }, }, 5083 { 8401 /* vmxnor.mm */, RISCV::VMXNOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, }, 5084 { 8411 /* vmxor.mm */, RISCV::VMXOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, }, 5085 { 8420 /* vnclip.wi */, RISCV::VNCLIP_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, }, 5086 { 8430 /* vnclip.wv */, RISCV::VNCLIP_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5087 { 8440 /* vnclip.wx */, RISCV::VNCLIP_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5088 { 8450 /* vnclipu.wi */, RISCV::VNCLIPU_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, }, 5089 { 8461 /* vnclipu.wv */, RISCV::VNCLIPU_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5090 { 8472 /* vnclipu.wx */, RISCV::VNCLIPU_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5091 { 8483 /* vncvt.x.x.w */, RISCV::VNSRL_WX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM }, }, 5092 { 8483 /* vncvt.x.x.w */, RISCV::VNSRL_WX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5093 { 8495 /* vneg.v */, RISCV::VRSUB_VX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM }, }, 5094 { 8495 /* vneg.v */, RISCV::VRSUB_VX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5095 { 8502 /* vnmsac.vv */, RISCV::VNMSAC_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5096 { 8512 /* vnmsac.vx */, RISCV::VNMSAC_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5097 { 8522 /* vnmsub.vv */, RISCV::VNMSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5098 { 8532 /* vnmsub.vx */, RISCV::VNMSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5099 { 8542 /* vnot.v */, RISCV::VXOR_VI, Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__reg0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM }, }, 5100 { 8542 /* vnot.v */, RISCV::VXOR_VI, Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5101 { 8549 /* vnsra.wi */, RISCV::VNSRA_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, }, 5102 { 8558 /* vnsra.wv */, RISCV::VNSRA_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5103 { 8567 /* vnsra.wx */, RISCV::VNSRA_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5104 { 8576 /* vnsrl.wi */, RISCV::VNSRL_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, }, 5105 { 8585 /* vnsrl.wv */, RISCV::VNSRL_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5106 { 8594 /* vnsrl.wx */, RISCV::VNSRL_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5107 { 8603 /* vor.vi */, RISCV::VOR_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, }, 5108 { 8610 /* vor.vv */, RISCV::VOR_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5109 { 8617 /* vor.vx */, RISCV::VOR_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5110 { 8624 /* vpopc.m */, RISCV::VCPOP_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5111 { 8632 /* vredand.vs */, RISCV::VREDAND_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5112 { 8643 /* vredmax.vs */, RISCV::VREDMAX_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5113 { 8654 /* vredmaxu.vs */, RISCV::VREDMAXU_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5114 { 8666 /* vredmin.vs */, RISCV::VREDMIN_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5115 { 8677 /* vredminu.vs */, RISCV::VREDMINU_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5116 { 8689 /* vredor.vs */, RISCV::VREDOR_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5117 { 8699 /* vredsum.vs */, RISCV::VREDSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5118 { 8710 /* vredxor.vs */, RISCV::VREDXOR_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5119 { 8721 /* vrem.vv */, RISCV::VREM_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5120 { 8729 /* vrem.vx */, RISCV::VREM_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5121 { 8737 /* vremu.vv */, RISCV::VREMU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5122 { 8746 /* vremu.vx */, RISCV::VREMU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5123 { 8755 /* vrgather.vi */, RISCV::VRGATHER_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, }, 5124 { 8767 /* vrgather.vv */, RISCV::VRGATHER_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5125 { 8779 /* vrgather.vx */, RISCV::VRGATHER_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5126 { 8791 /* vrgatherei16.vv */, RISCV::VRGATHEREI16_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5127 { 8807 /* vrsub.vi */, RISCV::VRSUB_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, }, 5128 { 8816 /* vrsub.vx */, RISCV::VRSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5129 { 8825 /* vs1r.v */, RISCV::VS1R_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_ }, }, 5130 { 8832 /* vs2r.v */, RISCV::VS2R_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VRM2, MCK__40_, MCK_GPR, MCK__41_ }, }, 5131 { 8839 /* vs4r.v */, RISCV::VS4R_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VRM4, MCK__40_, MCK_GPR, MCK__41_ }, }, 5132 { 8846 /* vs8r.v */, RISCV::VS8R_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VRM8, MCK__40_, MCK_GPR, MCK__41_ }, }, 5133 { 8853 /* vsadd.vi */, RISCV::VSADD_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, }, 5134 { 8862 /* vsadd.vv */, RISCV::VSADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5135 { 8871 /* vsadd.vx */, RISCV::VSADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5136 { 8880 /* vsaddu.vi */, RISCV::VSADDU_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, }, 5137 { 8890 /* vsaddu.vv */, RISCV::VSADDU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5138 { 8900 /* vsaddu.vx */, RISCV::VSADDU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5139 { 8910 /* vsbc.vvm */, RISCV::VSBC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_VMV0 }, }, 5140 { 8919 /* vsbc.vxm */, RISCV::VSBC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_VMV0 }, }, 5141 { 8928 /* vse1.v */, RISCV::VSM_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_ }, }, 5142 { 8935 /* vse16.v */, RISCV::VSE16_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5143 { 8943 /* vse32.v */, RISCV::VSE32_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5144 { 8951 /* vse64.v */, RISCV::VSE64_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5145 { 8959 /* vse8.v */, RISCV::VSE8_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5146 { 8966 /* vsetivli */, RISCV::VSETIVLI, Convert__Reg1_0__UImm51_1__VTypeI101_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_UImm5, MCK_VTypeI10 }, }, 5147 { 8975 /* vsetvl */, RISCV::VSETVL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 5148 { 8982 /* vsetvli */, RISCV::VSETVLI, Convert__Reg1_0__Reg1_1__VTypeI111_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_GPR, MCK_VTypeI11 }, }, 5149 { 8990 /* vsext.vf2 */, RISCV::VSEXT_VF2, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5150 { 9000 /* vsext.vf4 */, RISCV::VSEXT_VF4, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5151 { 9010 /* vsext.vf8 */, RISCV::VSEXT_VF8, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5152 { 9020 /* vslide1down.vx */, RISCV::VSLIDE1DOWN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5153 { 9035 /* vslide1up.vx */, RISCV::VSLIDE1UP_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5154 { 9048 /* vslidedown.vi */, RISCV::VSLIDEDOWN_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, }, 5155 { 9062 /* vslidedown.vx */, RISCV::VSLIDEDOWN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5156 { 9076 /* vslideup.vi */, RISCV::VSLIDEUP_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, }, 5157 { 9088 /* vslideup.vx */, RISCV::VSLIDEUP_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5158 { 9100 /* vsll.vi */, RISCV::VSLL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, }, 5159 { 9108 /* vsll.vv */, RISCV::VSLL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5160 { 9116 /* vsll.vx */, RISCV::VSLL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5161 { 9124 /* vsm.v */, RISCV::VSM_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_ }, }, 5162 { 9130 /* vsmul.vv */, RISCV::VSMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5163 { 9139 /* vsmul.vx */, RISCV::VSMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5164 { 9148 /* vsoxei16.v */, RISCV::VSOXEI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5165 { 9159 /* vsoxei32.v */, RISCV::VSOXEI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5166 { 9170 /* vsoxei64.v */, RISCV::VSOXEI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5167 { 9181 /* vsoxei8.v */, RISCV::VSOXEI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5168 { 9191 /* vsoxseg2ei16.v */, RISCV::VSOXSEG2EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5169 { 9206 /* vsoxseg2ei32.v */, RISCV::VSOXSEG2EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5170 { 9221 /* vsoxseg2ei64.v */, RISCV::VSOXSEG2EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5171 { 9236 /* vsoxseg2ei8.v */, RISCV::VSOXSEG2EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5172 { 9250 /* vsoxseg3ei16.v */, RISCV::VSOXSEG3EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5173 { 9265 /* vsoxseg3ei32.v */, RISCV::VSOXSEG3EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5174 { 9280 /* vsoxseg3ei64.v */, RISCV::VSOXSEG3EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5175 { 9295 /* vsoxseg3ei8.v */, RISCV::VSOXSEG3EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5176 { 9309 /* vsoxseg4ei16.v */, RISCV::VSOXSEG4EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5177 { 9324 /* vsoxseg4ei32.v */, RISCV::VSOXSEG4EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5178 { 9339 /* vsoxseg4ei64.v */, RISCV::VSOXSEG4EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5179 { 9354 /* vsoxseg4ei8.v */, RISCV::VSOXSEG4EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5180 { 9368 /* vsoxseg5ei16.v */, RISCV::VSOXSEG5EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5181 { 9383 /* vsoxseg5ei32.v */, RISCV::VSOXSEG5EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5182 { 9398 /* vsoxseg5ei64.v */, RISCV::VSOXSEG5EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5183 { 9413 /* vsoxseg5ei8.v */, RISCV::VSOXSEG5EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5184 { 9427 /* vsoxseg6ei16.v */, RISCV::VSOXSEG6EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5185 { 9442 /* vsoxseg6ei32.v */, RISCV::VSOXSEG6EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5186 { 9457 /* vsoxseg6ei64.v */, RISCV::VSOXSEG6EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5187 { 9472 /* vsoxseg6ei8.v */, RISCV::VSOXSEG6EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5188 { 9486 /* vsoxseg7ei16.v */, RISCV::VSOXSEG7EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5189 { 9501 /* vsoxseg7ei32.v */, RISCV::VSOXSEG7EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5190 { 9516 /* vsoxseg7ei64.v */, RISCV::VSOXSEG7EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5191 { 9531 /* vsoxseg7ei8.v */, RISCV::VSOXSEG7EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5192 { 9545 /* vsoxseg8ei16.v */, RISCV::VSOXSEG8EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5193 { 9560 /* vsoxseg8ei32.v */, RISCV::VSOXSEG8EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5194 { 9575 /* vsoxseg8ei64.v */, RISCV::VSOXSEG8EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5195 { 9590 /* vsoxseg8ei8.v */, RISCV::VSOXSEG8EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5196 { 9604 /* vsra.vi */, RISCV::VSRA_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, }, 5197 { 9612 /* vsra.vv */, RISCV::VSRA_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5198 { 9620 /* vsra.vx */, RISCV::VSRA_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5199 { 9628 /* vsrl.vi */, RISCV::VSRL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, }, 5200 { 9636 /* vsrl.vv */, RISCV::VSRL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5201 { 9644 /* vsrl.vx */, RISCV::VSRL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5202 { 9652 /* vsse16.v */, RISCV::VSSE16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5203 { 9661 /* vsse32.v */, RISCV::VSSE32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5204 { 9670 /* vsse64.v */, RISCV::VSSE64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5205 { 9679 /* vsse8.v */, RISCV::VSSE8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5206 { 9687 /* vsseg2e16.v */, RISCV::VSSEG2E16_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5207 { 9699 /* vsseg2e32.v */, RISCV::VSSEG2E32_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5208 { 9711 /* vsseg2e64.v */, RISCV::VSSEG2E64_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5209 { 9723 /* vsseg2e8.v */, RISCV::VSSEG2E8_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5210 { 9734 /* vsseg3e16.v */, RISCV::VSSEG3E16_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5211 { 9746 /* vsseg3e32.v */, RISCV::VSSEG3E32_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5212 { 9758 /* vsseg3e64.v */, RISCV::VSSEG3E64_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5213 { 9770 /* vsseg3e8.v */, RISCV::VSSEG3E8_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5214 { 9781 /* vsseg4e16.v */, RISCV::VSSEG4E16_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5215 { 9793 /* vsseg4e32.v */, RISCV::VSSEG4E32_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5216 { 9805 /* vsseg4e64.v */, RISCV::VSSEG4E64_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5217 { 9817 /* vsseg4e8.v */, RISCV::VSSEG4E8_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5218 { 9828 /* vsseg5e16.v */, RISCV::VSSEG5E16_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5219 { 9840 /* vsseg5e32.v */, RISCV::VSSEG5E32_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5220 { 9852 /* vsseg5e64.v */, RISCV::VSSEG5E64_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5221 { 9864 /* vsseg5e8.v */, RISCV::VSSEG5E8_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5222 { 9875 /* vsseg6e16.v */, RISCV::VSSEG6E16_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5223 { 9887 /* vsseg6e32.v */, RISCV::VSSEG6E32_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5224 { 9899 /* vsseg6e64.v */, RISCV::VSSEG6E64_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5225 { 9911 /* vsseg6e8.v */, RISCV::VSSEG6E8_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5226 { 9922 /* vsseg7e16.v */, RISCV::VSSEG7E16_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5227 { 9934 /* vsseg7e32.v */, RISCV::VSSEG7E32_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5228 { 9946 /* vsseg7e64.v */, RISCV::VSSEG7E64_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5229 { 9958 /* vsseg7e8.v */, RISCV::VSSEG7E8_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5230 { 9969 /* vsseg8e16.v */, RISCV::VSSEG8E16_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5231 { 9981 /* vsseg8e32.v */, RISCV::VSSEG8E32_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5232 { 9993 /* vsseg8e64.v */, RISCV::VSSEG8E64_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5233 { 10005 /* vsseg8e8.v */, RISCV::VSSEG8E8_V, Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_RVVMaskRegOpOperand }, }, 5234 { 10016 /* vssra.vi */, RISCV::VSSRA_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, }, 5235 { 10025 /* vssra.vv */, RISCV::VSSRA_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5236 { 10034 /* vssra.vx */, RISCV::VSSRA_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5237 { 10043 /* vssrl.vi */, RISCV::VSSRL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, }, 5238 { 10052 /* vssrl.vv */, RISCV::VSSRL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5239 { 10061 /* vssrl.vx */, RISCV::VSSRL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5240 { 10070 /* vssseg2e16.v */, RISCV::VSSSEG2E16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5241 { 10083 /* vssseg2e32.v */, RISCV::VSSSEG2E32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5242 { 10096 /* vssseg2e64.v */, RISCV::VSSSEG2E64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5243 { 10109 /* vssseg2e8.v */, RISCV::VSSSEG2E8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5244 { 10121 /* vssseg3e16.v */, RISCV::VSSSEG3E16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5245 { 10134 /* vssseg3e32.v */, RISCV::VSSSEG3E32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5246 { 10147 /* vssseg3e64.v */, RISCV::VSSSEG3E64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5247 { 10160 /* vssseg3e8.v */, RISCV::VSSSEG3E8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5248 { 10172 /* vssseg4e16.v */, RISCV::VSSSEG4E16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5249 { 10185 /* vssseg4e32.v */, RISCV::VSSSEG4E32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5250 { 10198 /* vssseg4e64.v */, RISCV::VSSSEG4E64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5251 { 10211 /* vssseg4e8.v */, RISCV::VSSSEG4E8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5252 { 10223 /* vssseg5e16.v */, RISCV::VSSSEG5E16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5253 { 10236 /* vssseg5e32.v */, RISCV::VSSSEG5E32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5254 { 10249 /* vssseg5e64.v */, RISCV::VSSSEG5E64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5255 { 10262 /* vssseg5e8.v */, RISCV::VSSSEG5E8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5256 { 10274 /* vssseg6e16.v */, RISCV::VSSSEG6E16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5257 { 10287 /* vssseg6e32.v */, RISCV::VSSSEG6E32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5258 { 10300 /* vssseg6e64.v */, RISCV::VSSSEG6E64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5259 { 10313 /* vssseg6e8.v */, RISCV::VSSSEG6E8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5260 { 10325 /* vssseg7e16.v */, RISCV::VSSSEG7E16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5261 { 10338 /* vssseg7e32.v */, RISCV::VSSSEG7E32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5262 { 10351 /* vssseg7e64.v */, RISCV::VSSSEG7E64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5263 { 10364 /* vssseg7e8.v */, RISCV::VSSSEG7E8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5264 { 10376 /* vssseg8e16.v */, RISCV::VSSSEG8E16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5265 { 10389 /* vssseg8e32.v */, RISCV::VSSSEG8E32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5266 { 10402 /* vssseg8e64.v */, RISCV::VSSSEG8E64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5267 { 10415 /* vssseg8e8.v */, RISCV::VSSSEG8E8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5268 { 10427 /* vssub.vv */, RISCV::VSSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5269 { 10436 /* vssub.vx */, RISCV::VSSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5270 { 10445 /* vssubu.vv */, RISCV::VSSUBU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5271 { 10455 /* vssubu.vx */, RISCV::VSSUBU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5272 { 10465 /* vsub.vv */, RISCV::VSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5273 { 10473 /* vsub.vx */, RISCV::VSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5274 { 10481 /* vsuxei16.v */, RISCV::VSUXEI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5275 { 10492 /* vsuxei32.v */, RISCV::VSUXEI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5276 { 10503 /* vsuxei64.v */, RISCV::VSUXEI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5277 { 10514 /* vsuxei8.v */, RISCV::VSUXEI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5278 { 10524 /* vsuxseg2ei16.v */, RISCV::VSUXSEG2EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5279 { 10539 /* vsuxseg2ei32.v */, RISCV::VSUXSEG2EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5280 { 10554 /* vsuxseg2ei64.v */, RISCV::VSUXSEG2EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5281 { 10569 /* vsuxseg2ei8.v */, RISCV::VSUXSEG2EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5282 { 10583 /* vsuxseg3ei16.v */, RISCV::VSUXSEG3EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5283 { 10598 /* vsuxseg3ei32.v */, RISCV::VSUXSEG3EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5284 { 10613 /* vsuxseg3ei64.v */, RISCV::VSUXSEG3EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5285 { 10628 /* vsuxseg3ei8.v */, RISCV::VSUXSEG3EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5286 { 10642 /* vsuxseg4ei16.v */, RISCV::VSUXSEG4EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5287 { 10657 /* vsuxseg4ei32.v */, RISCV::VSUXSEG4EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5288 { 10672 /* vsuxseg4ei64.v */, RISCV::VSUXSEG4EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5289 { 10687 /* vsuxseg4ei8.v */, RISCV::VSUXSEG4EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5290 { 10701 /* vsuxseg5ei16.v */, RISCV::VSUXSEG5EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5291 { 10716 /* vsuxseg5ei32.v */, RISCV::VSUXSEG5EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5292 { 10731 /* vsuxseg5ei64.v */, RISCV::VSUXSEG5EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5293 { 10746 /* vsuxseg5ei8.v */, RISCV::VSUXSEG5EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5294 { 10760 /* vsuxseg6ei16.v */, RISCV::VSUXSEG6EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5295 { 10775 /* vsuxseg6ei32.v */, RISCV::VSUXSEG6EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5296 { 10790 /* vsuxseg6ei64.v */, RISCV::VSUXSEG6EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5297 { 10805 /* vsuxseg6ei8.v */, RISCV::VSUXSEG6EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5298 { 10819 /* vsuxseg7ei16.v */, RISCV::VSUXSEG7EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5299 { 10834 /* vsuxseg7ei32.v */, RISCV::VSUXSEG7EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5300 { 10849 /* vsuxseg7ei64.v */, RISCV::VSUXSEG7EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5301 { 10864 /* vsuxseg7ei8.v */, RISCV::VSUXSEG7EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5302 { 10878 /* vsuxseg8ei16.v */, RISCV::VSUXSEG8EI16_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5303 { 10893 /* vsuxseg8ei32.v */, RISCV::VSUXSEG8EI32_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5304 { 10908 /* vsuxseg8ei64.v */, RISCV::VSUXSEG8EI64_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5305 { 10923 /* vsuxseg8ei8.v */, RISCV::VSUXSEG8EI8_V, Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5306 { 10937 /* vt.maskc */, RISCV::VT_MASKC, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64_HasVendorXVentanaCondOps, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 5307 { 10946 /* vt.maskcn */, RISCV::VT_MASKCN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64_HasVendorXVentanaCondOps, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 5308 { 10956 /* vwadd.vv */, RISCV::VWADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5309 { 10965 /* vwadd.vx */, RISCV::VWADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5310 { 10974 /* vwadd.wv */, RISCV::VWADD_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5311 { 10983 /* vwadd.wx */, RISCV::VWADD_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5312 { 10992 /* vwaddu.vv */, RISCV::VWADDU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5313 { 11002 /* vwaddu.vx */, RISCV::VWADDU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5314 { 11012 /* vwaddu.wv */, RISCV::VWADDU_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5315 { 11022 /* vwaddu.wx */, RISCV::VWADDU_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5316 { 11032 /* vwcvt.x.x.v */, RISCV::VWADD_VX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM }, }, 5317 { 11032 /* vwcvt.x.x.v */, RISCV::VWADD_VX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5318 { 11044 /* vwcvtu.x.x.v */, RISCV::VWADDU_VX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM }, }, 5319 { 11044 /* vwcvtu.x.x.v */, RISCV::VWADDU_VX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5320 { 11057 /* vwmacc.vv */, RISCV::VWMACC_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5321 { 11067 /* vwmacc.vx */, RISCV::VWMACC_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5322 { 11077 /* vwmaccsu.vv */, RISCV::VWMACCSU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5323 { 11089 /* vwmaccsu.vx */, RISCV::VWMACCSU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5324 { 11101 /* vwmaccu.vv */, RISCV::VWMACCU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5325 { 11112 /* vwmaccu.vx */, RISCV::VWMACCU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5326 { 11123 /* vwmaccus.vx */, RISCV::VWMACCUS_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5327 { 11135 /* vwmul.vv */, RISCV::VWMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5328 { 11144 /* vwmul.vx */, RISCV::VWMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5329 { 11153 /* vwmulsu.vv */, RISCV::VWMULSU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5330 { 11164 /* vwmulsu.vx */, RISCV::VWMULSU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5331 { 11175 /* vwmulu.vv */, RISCV::VWMULU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5332 { 11185 /* vwmulu.vx */, RISCV::VWMULU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5333 { 11195 /* vwredsum.vs */, RISCV::VWREDSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5334 { 11207 /* vwredsumu.vs */, RISCV::VWREDSUMU_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5335 { 11220 /* vwsub.vv */, RISCV::VWSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5336 { 11229 /* vwsub.vx */, RISCV::VWSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5337 { 11238 /* vwsub.wv */, RISCV::VWSUB_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5338 { 11247 /* vwsub.wx */, RISCV::VWSUB_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5339 { 11256 /* vwsubu.vv */, RISCV::VWSUBU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5340 { 11266 /* vwsubu.vx */, RISCV::VWSUBU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5341 { 11276 /* vwsubu.wv */, RISCV::VWSUBU_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5342 { 11286 /* vwsubu.wx */, RISCV::VWSUBU_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5343 { 11296 /* vxor.vi */, RISCV::VXOR_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, }, 5344 { 11304 /* vxor.vv */, RISCV::VXOR_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5345 { 11312 /* vxor.vx */, RISCV::VXOR_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, }, 5346 { 11320 /* vzext.vf2 */, RISCV::VZEXT_VF2, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5347 { 11330 /* vzext.vf4 */, RISCV::VZEXT_VF4, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5348 { 11340 /* vzext.vf8 */, RISCV::VZEXT_VF8, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, }, 5349 { 11350 /* wfi */, RISCV::WFI, Convert__imm_95_0__imm_95_0, AMFBS_None, { }, }, 5350 { 11354 /* wrs.nto */, RISCV::WRS_NTO, Convert_NoOperands, AMFBS_HasStdExtZawrs, { }, }, 5351 { 11362 /* wrs.sto */, RISCV::WRS_STO, Convert_NoOperands, AMFBS_HasStdExtZawrs, { }, }, 5352 { 11370 /* xnor */, RISCV::XNOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 5353 { 11375 /* xor */, RISCV::XOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 5354 { 11375 /* xor */, RISCV::XORI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 5355 { 11379 /* xori */, RISCV::XORI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 5356 { 11384 /* xperm4 */, RISCV::XPERM4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkx, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 5357 { 11391 /* xperm8 */, RISCV::XPERM8, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkx, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 5358 { 11398 /* zext.b */, RISCV::ANDI, Convert__Reg1_0__Reg1_1__imm_95_255, AMFBS_None, { MCK_GPR, MCK_GPR }, }, 5359 { 11405 /* zext.h */, RISCV::ZEXT_H_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV32, { MCK_GPR, MCK_GPR }, }, 5360 { 11405 /* zext.h */, RISCV::ZEXT_H_RV64, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, }, 5361 { 11405 /* zext.h */, RISCV::PseudoZEXT_H, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, }, 5362 { 11412 /* zext.w */, RISCV::ADD_UW, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR }, }, 5363 { 11412 /* zext.w */, RISCV::PseudoZEXT_W, Convert__Reg1_0__Reg1_1, AMFBS_IsRV64, { MCK_GPR, MCK_GPR }, }, 5364 { 11419 /* zip */, RISCV::ZIP_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbkb_IsRV32, { MCK_GPR, MCK_GPR }, }, 5365}; 5366 5367#include "llvm/Support/Debug.h" 5368#include "llvm/Support/Format.h" 5369 5370unsigned RISCVAsmParser:: 5371MatchInstructionImpl(const OperandVector &Operands, 5372 MCInst &Inst, 5373 uint64_t &ErrorInfo, 5374 FeatureBitset &MissingFeatures, 5375 bool matchingInlineAsm, unsigned VariantID) { 5376 // Eliminate obvious mismatches. 5377 if (Operands.size() > 8) { 5378 ErrorInfo = 8; 5379 return Match_InvalidOperand; 5380 } 5381 5382 // Get the current feature set. 5383 const FeatureBitset &AvailableFeatures = getAvailableFeatures(); 5384 5385 // Get the instruction mnemonic, which is the first token. 5386 StringRef Mnemonic = ((RISCVOperand &)*Operands[0]).getToken(); 5387 5388 // Process all MnemonicAliases to remap the mnemonic. 5389 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID); 5390 5391 // Some state to try to produce better error messages. 5392 bool HadMatchOtherThanFeatures = false; 5393 bool HadMatchOtherThanPredicate = false; 5394 unsigned RetCode = Match_InvalidOperand; 5395 MissingFeatures.set(); 5396 // Set ErrorInfo to the operand that mismatches if it is 5397 // wrong for all instances of the instruction. 5398 ErrorInfo = ~0ULL; 5399 SmallBitVector OptionalOperandsMask(7); 5400 // Find the appropriate table for this asm variant. 5401 const MatchEntry *Start, *End; 5402 switch (VariantID) { 5403 default: llvm_unreachable("invalid variant!"); 5404 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; 5405 } 5406 // Search the table. 5407 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode()); 5408 5409 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " << 5410 std::distance(MnemonicRange.first, MnemonicRange.second) << 5411 " encodings with mnemonic '" << Mnemonic << "'\n"); 5412 5413 // Return a more specific error code if no mnemonics match. 5414 if (MnemonicRange.first == MnemonicRange.second) 5415 return Match_MnemonicFail; 5416 5417 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second; 5418 it != ie; ++it) { 5419 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx]; 5420 bool HasRequiredFeatures = 5421 (AvailableFeatures & RequiredFeatures) == RequiredFeatures; 5422 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode " 5423 << MII.getName(it->Opcode) << "\n"); 5424 // equal_range guarantees that instruction mnemonic matches. 5425 assert(Mnemonic == it->getMnemonic()); 5426 bool OperandsValid = true; 5427 OptionalOperandsMask.reset(0, 7); 5428 for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 7; ++FormalIdx) { 5429 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]); 5430 DEBUG_WITH_TYPE("asm-matcher", 5431 dbgs() << " Matching formal operand class " << getMatchClassName(Formal) 5432 << " against actual operand at index " << ActualIdx); 5433 if (ActualIdx < Operands.size()) 5434 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " ("; 5435 Operands[ActualIdx]->print(dbgs()); dbgs() << "): "); 5436 else 5437 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": "); 5438 if (ActualIdx >= Operands.size()) { 5439 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n"); 5440 if (Formal == InvalidMatchClass) { 5441 OptionalOperandsMask.set(FormalIdx, 7); 5442 break; 5443 } 5444 if (isSubclass(Formal, OptionalMatchClass)) { 5445 OptionalOperandsMask.set(FormalIdx); 5446 continue; 5447 } 5448 OperandsValid = false; 5449 ErrorInfo = ActualIdx; 5450 break; 5451 } 5452 MCParsedAsmOperand &Actual = *Operands[ActualIdx]; 5453 unsigned Diag = validateOperandClass(Actual, Formal); 5454 if (Diag == Match_Success) { 5455 DEBUG_WITH_TYPE("asm-matcher", 5456 dbgs() << "match success using generic matcher\n"); 5457 ++ActualIdx; 5458 continue; 5459 } 5460 // If the generic handler indicates an invalid operand 5461 // failure, check for a special case. 5462 if (Diag != Match_Success) { 5463 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal); 5464 if (TargetDiag == Match_Success) { 5465 DEBUG_WITH_TYPE("asm-matcher", 5466 dbgs() << "match success using target matcher\n"); 5467 ++ActualIdx; 5468 continue; 5469 } 5470 // If the target matcher returned a specific error code use 5471 // that, else use the one from the generic matcher. 5472 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures) 5473 Diag = TargetDiag; 5474 } 5475 // If current formal operand wasn't matched and it is optional 5476 // then try to match next formal operand 5477 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) { 5478 OptionalOperandsMask.set(FormalIdx); 5479 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n"); 5480 continue; 5481 } 5482 // If this operand is broken for all of the instances of this 5483 // mnemonic, keep track of it so we can report loc info. 5484 // If we already had a match that only failed due to a 5485 // target predicate, that diagnostic is preferred. 5486 if (!HadMatchOtherThanPredicate && 5487 (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) { 5488 if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand)) 5489 RetCode = Diag; 5490 ErrorInfo = ActualIdx; 5491 } 5492 // Otherwise, just reject this instance of the mnemonic. 5493 OperandsValid = false; 5494 break; 5495 } 5496 5497 if (!OperandsValid) { 5498 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple " 5499 "operand mismatches, ignoring " 5500 "this opcode\n"); 5501 continue; 5502 } 5503 if (!HasRequiredFeatures) { 5504 HadMatchOtherThanFeatures = true; 5505 FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures; 5506 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:"; 5507 for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I) 5508 if (NewMissingFeatures[I]) 5509 dbgs() << ' ' << I; 5510 dbgs() << "\n"); 5511 if (NewMissingFeatures.count() <= 5512 MissingFeatures.count()) 5513 MissingFeatures = NewMissingFeatures; 5514 continue; 5515 } 5516 5517 Inst.clear(); 5518 5519 Inst.setOpcode(it->Opcode); 5520 // We have a potential match but have not rendered the operands. 5521 // Check the target predicate to handle any context sensitive 5522 // constraints. 5523 // For example, Ties that are referenced multiple times must be 5524 // checked here to ensure the input is the same for each match 5525 // constraints. If we leave it any later the ties will have been 5526 // canonicalized 5527 unsigned MatchResult; 5528 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) { 5529 Inst.clear(); 5530 DEBUG_WITH_TYPE( 5531 "asm-matcher", 5532 dbgs() << "Early target match predicate failed with diag code " 5533 << MatchResult << "\n"); 5534 RetCode = MatchResult; 5535 HadMatchOtherThanPredicate = true; 5536 continue; 5537 } 5538 5539 if (matchingInlineAsm) { 5540 convertToMapAndConstraints(it->ConvertFn, Operands); 5541 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo)) 5542 return Match_InvalidTiedOperand; 5543 5544 return Match_Success; 5545 } 5546 5547 // We have selected a definite instruction, convert the parsed 5548 // operands into the appropriate MCInst. 5549 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands, 5550 OptionalOperandsMask); 5551 5552 // We have a potential match. Check the target predicate to 5553 // handle any context sensitive constraints. 5554 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) { 5555 DEBUG_WITH_TYPE("asm-matcher", 5556 dbgs() << "Target match predicate failed with diag code " 5557 << MatchResult << "\n"); 5558 Inst.clear(); 5559 RetCode = MatchResult; 5560 HadMatchOtherThanPredicate = true; 5561 continue; 5562 } 5563 5564 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo)) 5565 return Match_InvalidTiedOperand; 5566 5567 DEBUG_WITH_TYPE( 5568 "asm-matcher", 5569 dbgs() << "Opcode result: complete match, selecting this opcode\n"); 5570 return Match_Success; 5571 } 5572 5573 // Okay, we had no match. Try to return a useful error code. 5574 if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures) 5575 return RetCode; 5576 5577 ErrorInfo = 0; 5578 return Match_MissingFeature; 5579} 5580 5581namespace { 5582 struct OperandMatchEntry { 5583 uint16_t Mnemonic; 5584 uint8_t OperandMask; 5585 uint8_t Class; 5586 uint8_t RequiredFeaturesIdx; 5587 5588 StringRef getMnemonic() const { 5589 return StringRef(MnemonicTable + Mnemonic + 1, 5590 MnemonicTable[Mnemonic]); 5591 } 5592 }; 5593 5594 // Predicate for searching for an opcode. 5595 struct LessOpcodeOperand { 5596 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) { 5597 return LHS.getMnemonic() < RHS; 5598 } 5599 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) { 5600 return LHS < RHS.getMnemonic(); 5601 } 5602 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) { 5603 return LHS.getMnemonic() < RHS.getMnemonic(); 5604 } 5605 }; 5606} // end anonymous namespace 5607 5608static const OperandMatchEntry OperandMatchTable[959] = { 5609 /* Operand List Mnemonic, Mask, Operand Class, Features */ 5610 { 0 /* .insn_b */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None }, 5611 { 8 /* .insn_i */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None }, 5612 { 8 /* .insn_i */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None }, 5613 { 16 /* .insn_j */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None }, 5614 { 16 /* .insn_j */, 4 /* 2 */, MCK_SImm21Lsb0JAL, AMFBS_None }, 5615 { 24 /* .insn_r */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None }, 5616 { 24 /* .insn_r */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None }, 5617 { 32 /* .insn_r4 */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None }, 5618 { 41 /* .insn_s */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None }, 5619 { 49 /* .insn_sb */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None }, 5620 { 58 /* .insn_u */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None }, 5621 { 66 /* .insn_uj */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None }, 5622 { 66 /* .insn_uj */, 4 /* 2 */, MCK_SImm21Lsb0JAL, AMFBS_None }, 5623 { 75 /* add */, 8 /* 3 */, MCK_TPRelAddSymbol, AMFBS_None }, 5624 { 201 /* amoadd.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5625 { 210 /* amoadd.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5626 { 222 /* amoadd.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5627 { 236 /* amoadd.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5628 { 248 /* amoadd.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5629 { 257 /* amoadd.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5630 { 269 /* amoadd.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5631 { 283 /* amoadd.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5632 { 295 /* amoand.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5633 { 304 /* amoand.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5634 { 316 /* amoand.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5635 { 330 /* amoand.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5636 { 342 /* amoand.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5637 { 351 /* amoand.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5638 { 363 /* amoand.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5639 { 377 /* amoand.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5640 { 389 /* amomax.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5641 { 398 /* amomax.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5642 { 410 /* amomax.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5643 { 424 /* amomax.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5644 { 436 /* amomax.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5645 { 445 /* amomax.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5646 { 457 /* amomax.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5647 { 471 /* amomax.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5648 { 483 /* amomaxu.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5649 { 493 /* amomaxu.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5650 { 506 /* amomaxu.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5651 { 521 /* amomaxu.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5652 { 534 /* amomaxu.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5653 { 544 /* amomaxu.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5654 { 557 /* amomaxu.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5655 { 572 /* amomaxu.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5656 { 585 /* amomin.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5657 { 594 /* amomin.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5658 { 606 /* amomin.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5659 { 620 /* amomin.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5660 { 632 /* amomin.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5661 { 641 /* amomin.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5662 { 653 /* amomin.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5663 { 667 /* amomin.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5664 { 679 /* amominu.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5665 { 689 /* amominu.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5666 { 702 /* amominu.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5667 { 717 /* amominu.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5668 { 730 /* amominu.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5669 { 740 /* amominu.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5670 { 753 /* amominu.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5671 { 768 /* amominu.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5672 { 781 /* amoor.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5673 { 789 /* amoor.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5674 { 800 /* amoor.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5675 { 813 /* amoor.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5676 { 824 /* amoor.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5677 { 832 /* amoor.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5678 { 843 /* amoor.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5679 { 856 /* amoor.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5680 { 867 /* amoswap.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5681 { 877 /* amoswap.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5682 { 890 /* amoswap.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5683 { 905 /* amoswap.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5684 { 918 /* amoswap.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5685 { 928 /* amoswap.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5686 { 941 /* amoswap.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5687 { 956 /* amoswap.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5688 { 969 /* amoxor.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5689 { 978 /* amoxor.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5690 { 990 /* amoxor.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5691 { 1004 /* amoxor.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5692 { 1016 /* amoxor.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5693 { 1025 /* amoxor.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5694 { 1037 /* amoxor.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5695 { 1051 /* amoxor.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5696 { 1560 /* call */, 1 /* 0 */, MCK_CallSymbol, AMFBS_None }, 5697 { 1560 /* call */, 2 /* 1 */, MCK_CallSymbol, AMFBS_None }, 5698 { 1565 /* cbo.clean */, 1 /* 0 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicbom }, 5699 { 1575 /* cbo.flush */, 1 /* 0 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicbom }, 5700 { 1585 /* cbo.inval */, 1 /* 0 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicbom }, 5701 { 1595 /* cbo.zero */, 1 /* 0 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicboz }, 5702 { 1644 /* csrc */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None }, 5703 { 1644 /* csrc */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None }, 5704 { 1649 /* csrci */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None }, 5705 { 1655 /* csrr */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None }, 5706 { 1660 /* csrrc */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None }, 5707 { 1660 /* csrrc */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None }, 5708 { 1666 /* csrrci */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None }, 5709 { 1673 /* csrrs */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None }, 5710 { 1673 /* csrrs */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None }, 5711 { 1679 /* csrrsi */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None }, 5712 { 1686 /* csrrw */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None }, 5713 { 1686 /* csrrw */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None }, 5714 { 1692 /* csrrwi */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None }, 5715 { 1699 /* csrs */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None }, 5716 { 1699 /* csrs */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None }, 5717 { 1704 /* csrsi */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None }, 5718 { 1710 /* csrw */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None }, 5719 { 1710 /* csrw */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None }, 5720 { 1715 /* csrwi */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None }, 5721 { 1768 /* fabs.d */, 3 /* 0, 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5722 { 1768 /* fabs.d */, 3 /* 0, 1 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5723 { 1775 /* fabs.h */, 3 /* 0, 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5724 { 1782 /* fabs.s */, 3 /* 0, 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5725 { 1789 /* fadd.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5726 { 1789 /* fadd.d */, 7 /* 0, 1, 2 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5727 { 1789 /* fadd.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5728 { 1789 /* fadd.d */, 7 /* 0, 1, 2 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5729 { 1796 /* fadd.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5730 { 1796 /* fadd.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5731 { 1803 /* fadd.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5732 { 1803 /* fadd.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5733 { 1810 /* fclass.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5734 { 1810 /* fclass.d */, 2 /* 1 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5735 { 1819 /* fclass.h */, 2 /* 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5736 { 1828 /* fclass.s */, 2 /* 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5737 { 1837 /* fcvt.d.h */, 2 /* 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinxOrZhinxmin_HasStdExtZdinx }, 5738 { 1837 /* fcvt.d.h */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZhinxOrZhinxmin_HasStdExtZdinx }, 5739 { 1846 /* fcvt.d.l */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5740 { 1846 /* fcvt.d.l */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5741 { 1855 /* fcvt.d.lu */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5742 { 1855 /* fcvt.d.lu */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5743 { 1865 /* fcvt.d.s */, 2 /* 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5744 { 1865 /* fcvt.d.s */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5745 { 1865 /* fcvt.d.s */, 2 /* 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5746 { 1865 /* fcvt.d.s */, 1 /* 0 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5747 { 1874 /* fcvt.d.w */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5748 { 1874 /* fcvt.d.w */, 1 /* 0 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5749 { 1883 /* fcvt.d.wu */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5750 { 1883 /* fcvt.d.wu */, 1 /* 0 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5751 { 1893 /* fcvt.h.d */, 1 /* 0 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinxOrZhinxmin_HasStdExtZdinx }, 5752 { 1893 /* fcvt.h.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZhinxOrZhinxmin_HasStdExtZdinx }, 5753 { 1893 /* fcvt.h.d */, 1 /* 0 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinxOrZhinxmin_HasStdExtZdinx }, 5754 { 1893 /* fcvt.h.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZhinxOrZhinxmin_HasStdExtZdinx }, 5755 { 1902 /* fcvt.h.l */, 1 /* 0 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx_IsRV64 }, 5756 { 1902 /* fcvt.h.l */, 1 /* 0 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx_IsRV64 }, 5757 { 1911 /* fcvt.h.lu */, 1 /* 0 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx_IsRV64 }, 5758 { 1911 /* fcvt.h.lu */, 1 /* 0 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx_IsRV64 }, 5759 { 1921 /* fcvt.h.s */, 3 /* 0, 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinxOrZhinxmin }, 5760 { 1921 /* fcvt.h.s */, 3 /* 0, 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinxOrZhinxmin }, 5761 { 1930 /* fcvt.h.w */, 1 /* 0 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5762 { 1930 /* fcvt.h.w */, 1 /* 0 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5763 { 1939 /* fcvt.h.wu */, 1 /* 0 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5764 { 1939 /* fcvt.h.wu */, 1 /* 0 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5765 { 1949 /* fcvt.l.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5766 { 1949 /* fcvt.l.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5767 { 1958 /* fcvt.l.h */, 2 /* 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx_IsRV64 }, 5768 { 1958 /* fcvt.l.h */, 2 /* 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx_IsRV64 }, 5769 { 1967 /* fcvt.l.s */, 2 /* 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx_IsRV64 }, 5770 { 1967 /* fcvt.l.s */, 2 /* 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx_IsRV64 }, 5771 { 1976 /* fcvt.lu.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5772 { 1976 /* fcvt.lu.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5773 { 1986 /* fcvt.lu.h */, 2 /* 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx_IsRV64 }, 5774 { 1986 /* fcvt.lu.h */, 2 /* 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx_IsRV64 }, 5775 { 1996 /* fcvt.lu.s */, 2 /* 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx_IsRV64 }, 5776 { 1996 /* fcvt.lu.s */, 2 /* 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx_IsRV64 }, 5777 { 2006 /* fcvt.s.d */, 1 /* 0 */, MCK_GPRAsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5778 { 2006 /* fcvt.s.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5779 { 2006 /* fcvt.s.d */, 1 /* 0 */, MCK_GPRAsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5780 { 2006 /* fcvt.s.d */, 2 /* 1 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5781 { 2006 /* fcvt.s.d */, 1 /* 0 */, MCK_GPRAsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5782 { 2006 /* fcvt.s.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5783 { 2006 /* fcvt.s.d */, 1 /* 0 */, MCK_GPRAsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5784 { 2006 /* fcvt.s.d */, 2 /* 1 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5785 { 2015 /* fcvt.s.h */, 3 /* 0, 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinxOrZhinxmin }, 5786 { 2024 /* fcvt.s.l */, 1 /* 0 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx_IsRV64 }, 5787 { 2024 /* fcvt.s.l */, 1 /* 0 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx_IsRV64 }, 5788 { 2033 /* fcvt.s.lu */, 1 /* 0 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx_IsRV64 }, 5789 { 2033 /* fcvt.s.lu */, 1 /* 0 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx_IsRV64 }, 5790 { 2043 /* fcvt.s.w */, 1 /* 0 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5791 { 2043 /* fcvt.s.w */, 1 /* 0 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5792 { 2052 /* fcvt.s.wu */, 1 /* 0 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5793 { 2052 /* fcvt.s.wu */, 1 /* 0 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5794 { 2062 /* fcvt.w.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5795 { 2062 /* fcvt.w.d */, 2 /* 1 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5796 { 2062 /* fcvt.w.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5797 { 2062 /* fcvt.w.d */, 2 /* 1 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5798 { 2071 /* fcvt.w.h */, 2 /* 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5799 { 2071 /* fcvt.w.h */, 2 /* 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5800 { 2080 /* fcvt.w.s */, 2 /* 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5801 { 2080 /* fcvt.w.s */, 2 /* 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5802 { 2089 /* fcvt.wu.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5803 { 2089 /* fcvt.wu.d */, 2 /* 1 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5804 { 2089 /* fcvt.wu.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5805 { 2089 /* fcvt.wu.d */, 2 /* 1 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5806 { 2099 /* fcvt.wu.h */, 2 /* 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5807 { 2099 /* fcvt.wu.h */, 2 /* 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5808 { 2109 /* fcvt.wu.s */, 2 /* 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5809 { 2109 /* fcvt.wu.s */, 2 /* 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5810 { 2119 /* fdiv.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5811 { 2119 /* fdiv.d */, 7 /* 0, 1, 2 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5812 { 2119 /* fdiv.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5813 { 2119 /* fdiv.d */, 7 /* 0, 1, 2 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5814 { 2126 /* fdiv.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5815 { 2126 /* fdiv.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5816 { 2133 /* fdiv.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5817 { 2133 /* fdiv.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5818 { 2164 /* feq.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5819 { 2164 /* feq.d */, 6 /* 1, 2 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5820 { 2170 /* feq.h */, 6 /* 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5821 { 2176 /* feq.s */, 6 /* 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5822 { 2182 /* fge.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5823 { 2182 /* fge.d */, 6 /* 1, 2 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5824 { 2188 /* fge.h */, 6 /* 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5825 { 2194 /* fge.s */, 6 /* 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5826 { 2200 /* fgt.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5827 { 2200 /* fgt.d */, 6 /* 1, 2 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5828 { 2206 /* fgt.h */, 6 /* 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5829 { 2212 /* fgt.s */, 6 /* 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5830 { 2218 /* fld */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtD }, 5831 { 2222 /* fle.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5832 { 2222 /* fle.d */, 6 /* 1, 2 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5833 { 2228 /* fle.h */, 6 /* 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5834 { 2234 /* fle.s */, 6 /* 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5835 { 2240 /* flh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtZfhOrZfhmin }, 5836 { 2244 /* flt.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5837 { 2244 /* flt.d */, 6 /* 1, 2 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5838 { 2250 /* flt.h */, 6 /* 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5839 { 2256 /* flt.s */, 6 /* 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5840 { 2262 /* flw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtF }, 5841 { 2266 /* fmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5842 { 2266 /* fmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5843 { 2266 /* fmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5844 { 2266 /* fmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5845 { 2274 /* fmadd.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5846 { 2274 /* fmadd.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5847 { 2282 /* fmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5848 { 2282 /* fmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5849 { 2290 /* fmax.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5850 { 2290 /* fmax.d */, 7 /* 0, 1, 2 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5851 { 2297 /* fmax.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5852 { 2304 /* fmax.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5853 { 2311 /* fmin.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5854 { 2311 /* fmin.d */, 7 /* 0, 1, 2 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5855 { 2318 /* fmin.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5856 { 2325 /* fmin.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5857 { 2332 /* fmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5858 { 2332 /* fmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5859 { 2332 /* fmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5860 { 2332 /* fmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5861 { 2340 /* fmsub.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5862 { 2340 /* fmsub.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5863 { 2348 /* fmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5864 { 2348 /* fmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5865 { 2356 /* fmul.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5866 { 2356 /* fmul.d */, 7 /* 0, 1, 2 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5867 { 2356 /* fmul.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5868 { 2356 /* fmul.d */, 7 /* 0, 1, 2 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5869 { 2363 /* fmul.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5870 { 2363 /* fmul.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5871 { 2370 /* fmul.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5872 { 2370 /* fmul.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5873 { 2391 /* fmv.h */, 3 /* 0, 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5874 { 2443 /* fneg.d */, 3 /* 0, 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5875 { 2443 /* fneg.d */, 3 /* 0, 1 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5876 { 2450 /* fneg.h */, 3 /* 0, 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5877 { 2457 /* fneg.s */, 3 /* 0, 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5878 { 2464 /* fnmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5879 { 2464 /* fnmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5880 { 2464 /* fnmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5881 { 2464 /* fnmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5882 { 2473 /* fnmadd.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5883 { 2473 /* fnmadd.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5884 { 2482 /* fnmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5885 { 2482 /* fnmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5886 { 2491 /* fnmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5887 { 2491 /* fnmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5888 { 2491 /* fnmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5889 { 2491 /* fnmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5890 { 2500 /* fnmsub.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5891 { 2500 /* fnmsub.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5892 { 2509 /* fnmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5893 { 2509 /* fnmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5894 { 2548 /* fsd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtD }, 5895 { 2569 /* fsgnj.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5896 { 2569 /* fsgnj.d */, 7 /* 0, 1, 2 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5897 { 2577 /* fsgnj.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5898 { 2585 /* fsgnj.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5899 { 2593 /* fsgnjn.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5900 { 2593 /* fsgnjn.d */, 7 /* 0, 1, 2 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5901 { 2602 /* fsgnjn.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5902 { 2611 /* fsgnjn.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5903 { 2620 /* fsgnjx.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5904 { 2620 /* fsgnjx.d */, 7 /* 0, 1, 2 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5905 { 2629 /* fsgnjx.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5906 { 2638 /* fsgnjx.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5907 { 2647 /* fsh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtZfhOrZfhmin }, 5908 { 2651 /* fsqrt.d */, 3 /* 0, 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5909 { 2651 /* fsqrt.d */, 3 /* 0, 1 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5910 { 2651 /* fsqrt.d */, 3 /* 0, 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5911 { 2651 /* fsqrt.d */, 3 /* 0, 1 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5912 { 2659 /* fsqrt.h */, 3 /* 0, 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5913 { 2659 /* fsqrt.h */, 3 /* 0, 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5914 { 2667 /* fsqrt.s */, 3 /* 0, 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5915 { 2667 /* fsqrt.s */, 3 /* 0, 1 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5916 { 2691 /* fsub.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5917 { 2691 /* fsub.d */, 7 /* 0, 1, 2 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5918 { 2691 /* fsub.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 }, 5919 { 2691 /* fsub.d */, 7 /* 0, 1, 2 */, MCK_GPRPF64AsFPR, AMFBS_HasStdExtZdinx_IsRV32 }, 5920 { 2698 /* fsub.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5921 { 2698 /* fsub.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZhinx }, 5922 { 2705 /* fsub.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5923 { 2705 /* fsub.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR, AMFBS_HasStdExtZfinx }, 5924 { 2712 /* fsw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtF }, 5925 { 2764 /* hlv.b */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH }, 5926 { 2770 /* hlv.bu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH }, 5927 { 2777 /* hlv.d */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasStdExtH }, 5928 { 2783 /* hlv.h */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH }, 5929 { 2789 /* hlv.hu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH }, 5930 { 2796 /* hlv.w */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH }, 5931 { 2802 /* hlv.wu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasStdExtH }, 5932 { 2809 /* hlvx.hu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH }, 5933 { 2817 /* hlvx.wu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH }, 5934 { 2825 /* hsv.b */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH }, 5935 { 2831 /* hsv.d */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasStdExtH }, 5936 { 2837 /* hsv.h */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH }, 5937 { 2843 /* hsv.w */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH }, 5938 { 2849 /* j */, 1 /* 0 */, MCK_SImm21Lsb0JAL, AMFBS_None }, 5939 { 2851 /* jal */, 1 /* 0 */, MCK_SImm21Lsb0JAL, AMFBS_None }, 5940 { 2851 /* jal */, 2 /* 1 */, MCK_SImm21Lsb0JAL, AMFBS_None }, 5941 { 2863 /* jump */, 1 /* 0 */, MCK_PseudoJumpSymbol, AMFBS_None }, 5942 { 2868 /* la */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 5943 { 2871 /* la.tls.gd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 5944 { 2881 /* la.tls.ie */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 5945 { 2891 /* lb */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 5946 { 2894 /* lbu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 5947 { 2898 /* ld */, 2 /* 1 */, MCK_BareSymbol, AMFBS_IsRV64 }, 5948 { 2901 /* lh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 5949 { 2904 /* lhu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 5950 { 2911 /* lla */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 5951 { 2915 /* lr.d */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5952 { 2920 /* lr.d.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5953 { 2928 /* lr.d.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5954 { 2938 /* lr.d.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5955 { 2946 /* lr.w */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5956 { 2951 /* lr.w.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5957 { 2959 /* lr.w.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5958 { 2969 /* lr.w.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5959 { 2981 /* lw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 5960 { 2984 /* lwu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_IsRV64 }, 5961 { 3273 /* sb */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 5962 { 3276 /* sc.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5963 { 3281 /* sc.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5964 { 3289 /* sc.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5965 { 3299 /* sc.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 5966 { 3307 /* sc.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5967 { 3312 /* sc.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5968 { 3320 /* sc.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5969 { 3330 /* sc.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtA }, 5970 { 3338 /* sd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_IsRV64 }, 5971 { 3423 /* sh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 5972 { 3784 /* sw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 5973 { 3787 /* tail */, 1 /* 0 */, MCK_CallSymbol, AMFBS_None }, 5974 { 3792 /* th.vmaqa.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot }, 5975 { 3804 /* th.vmaqa.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot }, 5976 { 3816 /* th.vmaqasu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot }, 5977 { 3830 /* th.vmaqasu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot }, 5978 { 3844 /* th.vmaqau.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot }, 5979 { 3857 /* th.vmaqau.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot }, 5980 { 3870 /* th.vmaqaus.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot }, 5981 { 3901 /* vaadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 5982 { 3910 /* vaadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 5983 { 3919 /* vaaddu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 5984 { 3929 /* vaaddu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 5985 { 3966 /* vadd.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 5986 { 3974 /* vadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 5987 { 3982 /* vadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 5988 { 3990 /* vand.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 5989 { 3998 /* vand.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 5990 { 4006 /* vand.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 5991 { 4014 /* vasub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 5992 { 4023 /* vasub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 5993 { 4032 /* vasubu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 5994 { 4042 /* vasubu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 5995 { 4065 /* vcpop.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 5996 { 4073 /* vdiv.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 5997 { 4081 /* vdiv.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 5998 { 4089 /* vdivu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 5999 { 4098 /* vdivu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6000 { 4107 /* vfabs.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6001 { 4115 /* vfadd.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6002 { 4124 /* vfadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6003 { 4133 /* vfclass.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6004 { 4143 /* vfcvt.f.x.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6005 { 4155 /* vfcvt.f.xu.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6006 { 4168 /* vfcvt.rtz.x.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6007 { 4184 /* vfcvt.rtz.xu.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6008 { 4201 /* vfcvt.x.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6009 { 4213 /* vfcvt.xu.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6010 { 4226 /* vfdiv.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6011 { 4235 /* vfdiv.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6012 { 4244 /* vfirst.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6013 { 4253 /* vfmacc.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6014 { 4263 /* vfmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6015 { 4273 /* vfmadd.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6016 { 4283 /* vfmadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6017 { 4293 /* vfmax.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6018 { 4302 /* vfmax.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6019 { 4323 /* vfmin.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6020 { 4332 /* vfmin.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6021 { 4341 /* vfmsac.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6022 { 4351 /* vfmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6023 { 4361 /* vfmsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6024 { 4371 /* vfmsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6025 { 4381 /* vfmul.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6026 { 4390 /* vfmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6027 { 4426 /* vfncvt.f.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6028 { 4439 /* vfncvt.f.x.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6029 { 4452 /* vfncvt.f.xu.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6030 { 4466 /* vfncvt.rod.f.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6031 { 4483 /* vfncvt.rtz.x.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6032 { 4500 /* vfncvt.rtz.xu.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6033 { 4518 /* vfncvt.x.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6034 { 4531 /* vfncvt.xu.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6035 { 4545 /* vfneg.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6036 { 4553 /* vfnmacc.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6037 { 4564 /* vfnmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6038 { 4575 /* vfnmadd.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6039 { 4586 /* vfnmadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6040 { 4597 /* vfnmsac.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6041 { 4608 /* vfnmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6042 { 4619 /* vfnmsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6043 { 4630 /* vfnmsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6044 { 4641 /* vfrdiv.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6045 { 4651 /* vfrec7.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6046 { 4660 /* vfredmax.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6047 { 4672 /* vfredmin.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6048 { 4684 /* vfredosum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6049 { 4697 /* vfredsum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6050 { 4709 /* vfredusum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6051 { 4722 /* vfrsqrt7.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6052 { 4733 /* vfrsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6053 { 4743 /* vfsgnj.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6054 { 4753 /* vfsgnj.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6055 { 4763 /* vfsgnjn.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6056 { 4774 /* vfsgnjn.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6057 { 4785 /* vfsgnjx.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6058 { 4796 /* vfsgnjx.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6059 { 4807 /* vfslide1down.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6060 { 4823 /* vfslide1up.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6061 { 4837 /* vfsqrt.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6062 { 4846 /* vfsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6063 { 4855 /* vfsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6064 { 4864 /* vfwadd.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6065 { 4874 /* vfwadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6066 { 4884 /* vfwadd.wf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6067 { 4894 /* vfwadd.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6068 { 4904 /* vfwcvt.f.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6069 { 4917 /* vfwcvt.f.x.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6070 { 4930 /* vfwcvt.f.xu.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6071 { 4944 /* vfwcvt.rtz.x.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6072 { 4961 /* vfwcvt.rtz.xu.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6073 { 4979 /* vfwcvt.x.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6074 { 4992 /* vfwcvt.xu.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6075 { 5006 /* vfwmacc.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6076 { 5017 /* vfwmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6077 { 5028 /* vfwmsac.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6078 { 5039 /* vfwmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6079 { 5050 /* vfwmul.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6080 { 5060 /* vfwmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6081 { 5070 /* vfwnmacc.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6082 { 5082 /* vfwnmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6083 { 5094 /* vfwnmsac.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6084 { 5106 /* vfwnmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6085 { 5118 /* vfwredosum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6086 { 5132 /* vfwredsum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6087 { 5145 /* vfwredusum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6088 { 5159 /* vfwsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6089 { 5169 /* vfwsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6090 { 5179 /* vfwsub.wf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6091 { 5189 /* vfwsub.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6092 { 5199 /* vid.v */, 2 /* 1 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6093 { 5205 /* viota.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6094 { 5404 /* vle16.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6095 { 5412 /* vle16ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6096 { 5422 /* vle32.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6097 { 5430 /* vle32ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6098 { 5440 /* vle64.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6099 { 5448 /* vle64ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6100 { 5458 /* vle8.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6101 { 5465 /* vle8ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6102 { 5480 /* vloxei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6103 { 5491 /* vloxei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6104 { 5502 /* vloxei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_IsRV64_HasVInstructionsI64 }, 6105 { 5513 /* vloxei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6106 { 5523 /* vloxseg2ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6107 { 5538 /* vloxseg2ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6108 { 5553 /* vloxseg2ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6109 { 5568 /* vloxseg2ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6110 { 5582 /* vloxseg3ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6111 { 5597 /* vloxseg3ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6112 { 5612 /* vloxseg3ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6113 { 5627 /* vloxseg3ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6114 { 5641 /* vloxseg4ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6115 { 5656 /* vloxseg4ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6116 { 5671 /* vloxseg4ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6117 { 5686 /* vloxseg4ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6118 { 5700 /* vloxseg5ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6119 { 5715 /* vloxseg5ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6120 { 5730 /* vloxseg5ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6121 { 5745 /* vloxseg5ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6122 { 5759 /* vloxseg6ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6123 { 5774 /* vloxseg6ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6124 { 5789 /* vloxseg6ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6125 { 5804 /* vloxseg6ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6126 { 5818 /* vloxseg7ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6127 { 5833 /* vloxseg7ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6128 { 5848 /* vloxseg7ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6129 { 5863 /* vloxseg7ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6130 { 5877 /* vloxseg8ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6131 { 5892 /* vloxseg8ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6132 { 5907 /* vloxseg8ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6133 { 5922 /* vloxseg8ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6134 { 5936 /* vlse16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6135 { 5945 /* vlse32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6136 { 5954 /* vlse64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6137 { 5963 /* vlse8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6138 { 5971 /* vlseg2e16.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6139 { 5983 /* vlseg2e16ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6140 { 5997 /* vlseg2e32.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6141 { 6009 /* vlseg2e32ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6142 { 6023 /* vlseg2e64.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6143 { 6035 /* vlseg2e64ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6144 { 6049 /* vlseg2e8.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6145 { 6060 /* vlseg2e8ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6146 { 6073 /* vlseg3e16.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6147 { 6085 /* vlseg3e16ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6148 { 6099 /* vlseg3e32.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6149 { 6111 /* vlseg3e32ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6150 { 6125 /* vlseg3e64.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6151 { 6137 /* vlseg3e64ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6152 { 6151 /* vlseg3e8.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6153 { 6162 /* vlseg3e8ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6154 { 6175 /* vlseg4e16.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6155 { 6187 /* vlseg4e16ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6156 { 6201 /* vlseg4e32.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6157 { 6213 /* vlseg4e32ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6158 { 6227 /* vlseg4e64.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6159 { 6239 /* vlseg4e64ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6160 { 6253 /* vlseg4e8.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6161 { 6264 /* vlseg4e8ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6162 { 6277 /* vlseg5e16.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6163 { 6289 /* vlseg5e16ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6164 { 6303 /* vlseg5e32.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6165 { 6315 /* vlseg5e32ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6166 { 6329 /* vlseg5e64.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6167 { 6341 /* vlseg5e64ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6168 { 6355 /* vlseg5e8.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6169 { 6366 /* vlseg5e8ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6170 { 6379 /* vlseg6e16.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6171 { 6391 /* vlseg6e16ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6172 { 6405 /* vlseg6e32.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6173 { 6417 /* vlseg6e32ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6174 { 6431 /* vlseg6e64.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6175 { 6443 /* vlseg6e64ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6176 { 6457 /* vlseg6e8.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6177 { 6468 /* vlseg6e8ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6178 { 6481 /* vlseg7e16.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6179 { 6493 /* vlseg7e16ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6180 { 6507 /* vlseg7e32.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6181 { 6519 /* vlseg7e32ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6182 { 6533 /* vlseg7e64.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6183 { 6545 /* vlseg7e64ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6184 { 6559 /* vlseg7e8.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6185 { 6570 /* vlseg7e8ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6186 { 6583 /* vlseg8e16.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6187 { 6595 /* vlseg8e16ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6188 { 6609 /* vlseg8e32.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6189 { 6621 /* vlseg8e32ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6190 { 6635 /* vlseg8e64.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6191 { 6647 /* vlseg8e64ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6192 { 6661 /* vlseg8e8.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6193 { 6672 /* vlseg8e8ff.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6194 { 6685 /* vlsseg2e16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6195 { 6698 /* vlsseg2e32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6196 { 6711 /* vlsseg2e64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6197 { 6724 /* vlsseg2e8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6198 { 6736 /* vlsseg3e16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6199 { 6749 /* vlsseg3e32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6200 { 6762 /* vlsseg3e64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6201 { 6775 /* vlsseg3e8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6202 { 6787 /* vlsseg4e16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6203 { 6800 /* vlsseg4e32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6204 { 6813 /* vlsseg4e64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6205 { 6826 /* vlsseg4e8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6206 { 6838 /* vlsseg5e16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6207 { 6851 /* vlsseg5e32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6208 { 6864 /* vlsseg5e64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6209 { 6877 /* vlsseg5e8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6210 { 6889 /* vlsseg6e16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6211 { 6902 /* vlsseg6e32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6212 { 6915 /* vlsseg6e64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6213 { 6928 /* vlsseg6e8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6214 { 6940 /* vlsseg7e16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6215 { 6953 /* vlsseg7e32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6216 { 6966 /* vlsseg7e64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6217 { 6979 /* vlsseg7e8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6218 { 6991 /* vlsseg8e16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6219 { 7004 /* vlsseg8e32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6220 { 7017 /* vlsseg8e64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6221 { 7030 /* vlsseg8e8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6222 { 7042 /* vluxei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6223 { 7053 /* vluxei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6224 { 7064 /* vluxei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_IsRV64_HasVInstructionsI64 }, 6225 { 7075 /* vluxei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6226 { 7085 /* vluxseg2ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6227 { 7100 /* vluxseg2ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6228 { 7115 /* vluxseg2ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6229 { 7130 /* vluxseg2ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6230 { 7144 /* vluxseg3ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6231 { 7159 /* vluxseg3ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6232 { 7174 /* vluxseg3ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6233 { 7189 /* vluxseg3ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6234 { 7203 /* vluxseg4ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6235 { 7218 /* vluxseg4ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6236 { 7233 /* vluxseg4ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6237 { 7248 /* vluxseg4ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6238 { 7262 /* vluxseg5ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6239 { 7277 /* vluxseg5ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6240 { 7292 /* vluxseg5ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6241 { 7307 /* vluxseg5ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6242 { 7321 /* vluxseg6ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6243 { 7336 /* vluxseg6ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6244 { 7351 /* vluxseg6ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6245 { 7366 /* vluxseg6ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6246 { 7380 /* vluxseg7ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6247 { 7395 /* vluxseg7ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6248 { 7410 /* vluxseg7ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6249 { 7425 /* vluxseg7ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6250 { 7439 /* vluxseg8ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6251 { 7454 /* vluxseg8ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6252 { 7469 /* vluxseg8ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6253 { 7484 /* vluxseg8ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6254 { 7498 /* vmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6255 { 7507 /* vmacc.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6256 { 7573 /* vmadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6257 { 7582 /* vmadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6258 { 7622 /* vmax.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6259 { 7630 /* vmax.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6260 { 7638 /* vmaxu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6261 { 7647 /* vmaxu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6262 { 7697 /* vmfeq.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6263 { 7706 /* vmfeq.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6264 { 7715 /* vmfge.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6265 { 7724 /* vmfge.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6266 { 7733 /* vmfgt.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6267 { 7742 /* vmfgt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6268 { 7751 /* vmfle.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6269 { 7760 /* vmfle.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6270 { 7769 /* vmflt.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6271 { 7778 /* vmflt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6272 { 7787 /* vmfne.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6273 { 7796 /* vmfne.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF }, 6274 { 7805 /* vmin.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6275 { 7813 /* vmin.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6276 { 7821 /* vminu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6277 { 7830 /* vminu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6278 { 7939 /* vmsbf.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6279 { 7947 /* vmseq.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6280 { 7956 /* vmseq.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6281 { 7965 /* vmseq.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6282 { 7982 /* vmsge.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6283 { 7991 /* vmsge.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6284 { 8000 /* vmsge.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6285 { 8000 /* vmsge.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6286 { 8009 /* vmsgeu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6287 { 8019 /* vmsgeu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6288 { 8029 /* vmsgeu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6289 { 8029 /* vmsgeu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6290 { 8039 /* vmsgt.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6291 { 8048 /* vmsgt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6292 { 8057 /* vmsgt.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6293 { 8066 /* vmsgtu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6294 { 8076 /* vmsgtu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6295 { 8086 /* vmsgtu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6296 { 8096 /* vmsif.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6297 { 8104 /* vmsle.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6298 { 8113 /* vmsle.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6299 { 8122 /* vmsle.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6300 { 8131 /* vmsleu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6301 { 8141 /* vmsleu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6302 { 8151 /* vmsleu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6303 { 8161 /* vmslt.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6304 { 8170 /* vmslt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6305 { 8179 /* vmslt.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6306 { 8188 /* vmsltu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6307 { 8198 /* vmsltu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6308 { 8208 /* vmsltu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6309 { 8218 /* vmsne.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6310 { 8227 /* vmsne.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6311 { 8236 /* vmsne.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6312 { 8245 /* vmsof.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6313 { 8253 /* vmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6314 { 8261 /* vmul.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6315 { 8269 /* vmulh.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6316 { 8278 /* vmulh.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6317 { 8287 /* vmulhsu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6318 { 8298 /* vmulhsu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6319 { 8309 /* vmulhu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6320 { 8319 /* vmulhu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6321 { 8420 /* vnclip.wi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6322 { 8430 /* vnclip.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6323 { 8440 /* vnclip.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6324 { 8450 /* vnclipu.wi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6325 { 8461 /* vnclipu.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6326 { 8472 /* vnclipu.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6327 { 8483 /* vncvt.x.x.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6328 { 8495 /* vneg.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6329 { 8502 /* vnmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6330 { 8512 /* vnmsac.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6331 { 8522 /* vnmsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6332 { 8532 /* vnmsub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6333 { 8542 /* vnot.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6334 { 8549 /* vnsra.wi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6335 { 8558 /* vnsra.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6336 { 8567 /* vnsra.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6337 { 8576 /* vnsrl.wi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6338 { 8585 /* vnsrl.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6339 { 8594 /* vnsrl.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6340 { 8603 /* vor.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6341 { 8610 /* vor.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6342 { 8617 /* vor.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6343 { 8624 /* vpopc.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6344 { 8632 /* vredand.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6345 { 8643 /* vredmax.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6346 { 8654 /* vredmaxu.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6347 { 8666 /* vredmin.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6348 { 8677 /* vredminu.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6349 { 8689 /* vredor.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6350 { 8699 /* vredsum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6351 { 8710 /* vredxor.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6352 { 8721 /* vrem.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6353 { 8729 /* vrem.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6354 { 8737 /* vremu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6355 { 8746 /* vremu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6356 { 8755 /* vrgather.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6357 { 8767 /* vrgather.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6358 { 8779 /* vrgather.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6359 { 8791 /* vrgatherei16.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6360 { 8807 /* vrsub.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6361 { 8816 /* vrsub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6362 { 8853 /* vsadd.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6363 { 8862 /* vsadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6364 { 8871 /* vsadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6365 { 8880 /* vsaddu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6366 { 8890 /* vsaddu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6367 { 8900 /* vsaddu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6368 { 8935 /* vse16.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6369 { 8943 /* vse32.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6370 { 8951 /* vse64.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6371 { 8959 /* vse8.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6372 { 8966 /* vsetivli */, 4 /* 2 */, MCK_VTypeI10, AMFBS_HasVInstructions }, 6373 { 8982 /* vsetvli */, 4 /* 2 */, MCK_VTypeI11, AMFBS_HasVInstructions }, 6374 { 8990 /* vsext.vf2 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6375 { 9000 /* vsext.vf4 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6376 { 9010 /* vsext.vf8 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6377 { 9020 /* vslide1down.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6378 { 9035 /* vslide1up.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6379 { 9048 /* vslidedown.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6380 { 9062 /* vslidedown.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6381 { 9076 /* vslideup.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6382 { 9088 /* vslideup.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6383 { 9100 /* vsll.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6384 { 9108 /* vsll.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6385 { 9116 /* vsll.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6386 { 9130 /* vsmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6387 { 9139 /* vsmul.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6388 { 9148 /* vsoxei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6389 { 9159 /* vsoxei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6390 { 9170 /* vsoxei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_IsRV64_HasVInstructionsI64 }, 6391 { 9181 /* vsoxei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6392 { 9191 /* vsoxseg2ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6393 { 9206 /* vsoxseg2ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6394 { 9221 /* vsoxseg2ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6395 { 9236 /* vsoxseg2ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6396 { 9250 /* vsoxseg3ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6397 { 9265 /* vsoxseg3ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6398 { 9280 /* vsoxseg3ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6399 { 9295 /* vsoxseg3ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6400 { 9309 /* vsoxseg4ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6401 { 9324 /* vsoxseg4ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6402 { 9339 /* vsoxseg4ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6403 { 9354 /* vsoxseg4ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6404 { 9368 /* vsoxseg5ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6405 { 9383 /* vsoxseg5ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6406 { 9398 /* vsoxseg5ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6407 { 9413 /* vsoxseg5ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6408 { 9427 /* vsoxseg6ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6409 { 9442 /* vsoxseg6ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6410 { 9457 /* vsoxseg6ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6411 { 9472 /* vsoxseg6ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6412 { 9486 /* vsoxseg7ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6413 { 9501 /* vsoxseg7ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6414 { 9516 /* vsoxseg7ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6415 { 9531 /* vsoxseg7ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6416 { 9545 /* vsoxseg8ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6417 { 9560 /* vsoxseg8ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6418 { 9575 /* vsoxseg8ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6419 { 9590 /* vsoxseg8ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6420 { 9604 /* vsra.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6421 { 9612 /* vsra.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6422 { 9620 /* vsra.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6423 { 9628 /* vsrl.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6424 { 9636 /* vsrl.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6425 { 9644 /* vsrl.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6426 { 9652 /* vsse16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6427 { 9661 /* vsse32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6428 { 9670 /* vsse64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6429 { 9679 /* vsse8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6430 { 9687 /* vsseg2e16.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6431 { 9699 /* vsseg2e32.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6432 { 9711 /* vsseg2e64.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6433 { 9723 /* vsseg2e8.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6434 { 9734 /* vsseg3e16.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6435 { 9746 /* vsseg3e32.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6436 { 9758 /* vsseg3e64.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6437 { 9770 /* vsseg3e8.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6438 { 9781 /* vsseg4e16.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6439 { 9793 /* vsseg4e32.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6440 { 9805 /* vsseg4e64.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6441 { 9817 /* vsseg4e8.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6442 { 9828 /* vsseg5e16.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6443 { 9840 /* vsseg5e32.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6444 { 9852 /* vsseg5e64.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6445 { 9864 /* vsseg5e8.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6446 { 9875 /* vsseg6e16.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6447 { 9887 /* vsseg6e32.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6448 { 9899 /* vsseg6e64.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6449 { 9911 /* vsseg6e8.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6450 { 9922 /* vsseg7e16.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6451 { 9934 /* vsseg7e32.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6452 { 9946 /* vsseg7e64.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6453 { 9958 /* vsseg7e8.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6454 { 9969 /* vsseg8e16.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6455 { 9981 /* vsseg8e32.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6456 { 9993 /* vsseg8e64.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6457 { 10005 /* vsseg8e8.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6458 { 10016 /* vssra.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6459 { 10025 /* vssra.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6460 { 10034 /* vssra.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6461 { 10043 /* vssrl.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6462 { 10052 /* vssrl.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6463 { 10061 /* vssrl.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6464 { 10070 /* vssseg2e16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6465 { 10083 /* vssseg2e32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6466 { 10096 /* vssseg2e64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6467 { 10109 /* vssseg2e8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6468 { 10121 /* vssseg3e16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6469 { 10134 /* vssseg3e32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6470 { 10147 /* vssseg3e64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6471 { 10160 /* vssseg3e8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6472 { 10172 /* vssseg4e16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6473 { 10185 /* vssseg4e32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6474 { 10198 /* vssseg4e64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6475 { 10211 /* vssseg4e8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6476 { 10223 /* vssseg5e16.v */, 32 /* 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AMFBS_HasVInstructionsI64 }, 6487 { 10364 /* vssseg7e8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6488 { 10376 /* vssseg8e16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6489 { 10389 /* vssseg8e32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6490 { 10402 /* vssseg8e64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 }, 6491 { 10415 /* vssseg8e8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6492 { 10427 /* vssub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6493 { 10436 /* vssub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6494 { 10445 /* vssubu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6495 { 10455 /* vssubu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6496 { 10465 /* vsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6497 { 10473 /* vsub.vx */, 8 /* 3 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MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6508 { 10613 /* vsuxseg3ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6509 { 10628 /* vsuxseg3ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6510 { 10642 /* vsuxseg4ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6511 { 10657 /* vsuxseg4ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6512 { 10672 /* vsuxseg4ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6513 { 10687 /* vsuxseg4ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6514 { 10701 /* vsuxseg5ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6515 { 10716 /* vsuxseg5ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6516 { 10731 /* vsuxseg5ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6517 { 10746 /* vsuxseg5ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6518 { 10760 /* vsuxseg6ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6519 { 10775 /* vsuxseg6ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6520 { 10790 /* vsuxseg6ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6521 { 10805 /* vsuxseg6ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6522 { 10819 /* vsuxseg7ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6523 { 10834 /* vsuxseg7ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6524 { 10849 /* vsuxseg7ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6525 { 10864 /* vsuxseg7ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6526 { 10878 /* vsuxseg8ei16.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6527 { 10893 /* vsuxseg8ei32.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6528 { 10908 /* vsuxseg8ei64.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 }, 6529 { 10923 /* vsuxseg8ei8.v */, 32 /* 5 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6530 { 10956 /* vwadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6531 { 10965 /* vwadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6532 { 10974 /* vwadd.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6533 { 10983 /* vwadd.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6534 { 10992 /* vwaddu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6535 { 11002 /* vwaddu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6536 { 11012 /* vwaddu.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6537 { 11022 /* vwaddu.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6538 { 11032 /* vwcvt.x.x.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6539 { 11044 /* vwcvtu.x.x.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6540 { 11057 /* vwmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6541 { 11067 /* vwmacc.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6542 { 11077 /* vwmaccsu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6543 { 11089 /* vwmaccsu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6544 { 11101 /* vwmaccu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6545 { 11112 /* vwmaccu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6546 { 11123 /* vwmaccus.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6547 { 11135 /* vwmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6548 { 11144 /* vwmul.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6549 { 11153 /* vwmulsu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6550 { 11164 /* vwmulsu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6551 { 11175 /* vwmulu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6552 { 11185 /* vwmulu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6553 { 11195 /* vwredsum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6554 { 11207 /* vwredsumu.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6555 { 11220 /* vwsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6556 { 11229 /* vwsub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6557 { 11238 /* vwsub.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6558 { 11247 /* vwsub.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6559 { 11256 /* vwsubu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6560 { 11266 /* vwsubu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6561 { 11276 /* vwsubu.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6562 { 11286 /* vwsubu.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6563 { 11296 /* vxor.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6564 { 11304 /* vxor.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6565 { 11312 /* vxor.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6566 { 11320 /* vzext.vf2 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6567 { 11330 /* vzext.vf4 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6568 { 11340 /* vzext.vf8 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions }, 6569}; 6570 6571OperandMatchResultTy RISCVAsmParser:: 6572tryCustomParseOperand(OperandVector &Operands, 6573 unsigned MCK) { 6574 6575 switch(MCK) { 6576 case MCK_BareSymbol: 6577 return parseBareSymbol(Operands); 6578 case MCK_CSRSystemRegister: 6579 return parseCSRSystemRegister(Operands); 6580 case MCK_CallSymbol: 6581 return parseCallSymbol(Operands); 6582 case MCK_GPRAsFPR: 6583 return parseGPRAsFPR(Operands); 6584 case MCK_GPRF64AsFPR: 6585 return parseGPRAsFPR(Operands); 6586 case MCK_GPRPF64AsFPR: 6587 return parseGPRAsFPR(Operands); 6588 case MCK_InsnDirectiveOpcode: 6589 return parseInsnDirectiveOpcode(Operands); 6590 case MCK_PseudoJumpSymbol: 6591 return parsePseudoJumpSymbol(Operands); 6592 case MCK_SImm21Lsb0JAL: 6593 return parseJALOffset(Operands); 6594 case MCK_TPRelAddSymbol: 6595 return parseOperandWithModifier(Operands); 6596 case MCK_RVVMaskRegOpOperand: 6597 return parseMaskReg(Operands); 6598 case MCK_ZeroOffsetMemOpOperand: 6599 return parseZeroOffsetMemOp(Operands); 6600 case MCK_VTypeI10: 6601 return parseVTypeI(Operands); 6602 case MCK_VTypeI11: 6603 return parseVTypeI(Operands); 6604 default: 6605 return MatchOperand_NoMatch; 6606 } 6607 return MatchOperand_NoMatch; 6608} 6609 6610OperandMatchResultTy RISCVAsmParser:: 6611MatchOperandParserImpl(OperandVector &Operands, 6612 StringRef Mnemonic, 6613 bool ParseForAllFeatures) { 6614 // Get the current feature set. 6615 const FeatureBitset &AvailableFeatures = getAvailableFeatures(); 6616 6617 // Get the next operand index. 6618 unsigned NextOpNum = Operands.size() - 1; 6619 // Search the table. 6620 auto MnemonicRange = 6621 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable), 6622 Mnemonic, LessOpcodeOperand()); 6623 6624 if (MnemonicRange.first == MnemonicRange.second) 6625 return MatchOperand_NoMatch; 6626 6627 for (const OperandMatchEntry *it = MnemonicRange.first, 6628 *ie = MnemonicRange.second; it != ie; ++it) { 6629 // equal_range guarantees that instruction mnemonic matches. 6630 assert(Mnemonic == it->getMnemonic()); 6631 6632 // check if the available features match 6633 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx]; 6634 if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures) 6635 continue; 6636 6637 // check if the operand in question has a custom parser. 6638 if (!(it->OperandMask & (1 << NextOpNum))) 6639 continue; 6640 6641 // call custom parse method to handle the operand 6642 OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class); 6643 if (Result != MatchOperand_NoMatch) 6644 return Result; 6645 } 6646 6647 // Okay, we had no match. 6648 return MatchOperand_NoMatch; 6649} 6650 6651#endif // GET_MATCHER_IMPLEMENTATION 6652 6653 6654#ifdef GET_MNEMONIC_SPELL_CHECKER 6655#undef GET_MNEMONIC_SPELL_CHECKER 6656 6657static std::string RISCVMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) { 6658 const unsigned MaxEditDist = 2; 6659 std::vector<StringRef> Candidates; 6660 StringRef Prev = ""; 6661 6662 // Find the appropriate table for this asm variant. 6663 const MatchEntry *Start, *End; 6664 switch (VariantID) { 6665 default: llvm_unreachable("invalid variant!"); 6666 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; 6667 } 6668 6669 for (auto I = Start; I < End; I++) { 6670 // Ignore unsupported instructions. 6671 const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx]; 6672 if ((FBS & RequiredFeatures) != RequiredFeatures) 6673 continue; 6674 6675 StringRef T = I->getMnemonic(); 6676 // Avoid recomputing the edit distance for the same string. 6677 if (T.equals(Prev)) 6678 continue; 6679 6680 Prev = T; 6681 unsigned Dist = S.edit_distance(T, false, MaxEditDist); 6682 if (Dist <= MaxEditDist) 6683 Candidates.push_back(T); 6684 } 6685 6686 if (Candidates.empty()) 6687 return ""; 6688 6689 std::string Res = ", did you mean: "; 6690 unsigned i = 0; 6691 for (; i < Candidates.size() - 1; i++) 6692 Res += Candidates[i].str() + ", "; 6693 return Res + Candidates[i].str() + "?"; 6694} 6695 6696#endif // GET_MNEMONIC_SPELL_CHECKER 6697 6698 6699#ifdef GET_MNEMONIC_CHECKER 6700#undef GET_MNEMONIC_CHECKER 6701 6702static bool RISCVCheckMnemonic(StringRef Mnemonic, 6703 const FeatureBitset &AvailableFeatures, 6704 unsigned VariantID) { 6705 // Process all MnemonicAliases to remap the mnemonic. 6706 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID); 6707 6708 // Find the appropriate table for this asm variant. 6709 const MatchEntry *Start, *End; 6710 switch (VariantID) { 6711 default: llvm_unreachable("invalid variant!"); 6712 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; 6713 } 6714 6715 // Search the table. 6716 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode()); 6717 6718 if (MnemonicRange.first == MnemonicRange.second) 6719 return false; 6720 6721 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second; 6722 it != ie; ++it) { 6723 const FeatureBitset &RequiredFeatures = 6724 FeatureBitsets[it->RequiredFeaturesIdx]; 6725 if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures) 6726 return true; 6727 } 6728 return false; 6729} 6730 6731#endif // GET_MNEMONIC_CHECKER 6732 6733