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1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|* Target Register Enum Values                                                *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass X86MCRegisterClasses[];
17
18namespace X86 {
19enum {
20  NoRegister,
21  AH = 1,
22  AL = 2,
23  AX = 3,
24  BH = 4,
25  BL = 5,
26  BP = 6,
27  BPH = 7,
28  BPL = 8,
29  BX = 9,
30  CH = 10,
31  CL = 11,
32  CS = 12,
33  CX = 13,
34  DF = 14,
35  DH = 15,
36  DI = 16,
37  DIH = 17,
38  DIL = 18,
39  DL = 19,
40  DS = 20,
41  DX = 21,
42  EAX = 22,
43  EBP = 23,
44  EBX = 24,
45  ECX = 25,
46  EDI = 26,
47  EDX = 27,
48  EFLAGS = 28,
49  EIP = 29,
50  EIZ = 30,
51  ES = 31,
52  ESI = 32,
53  ESP = 33,
54  FPCW = 34,
55  FPSW = 35,
56  FS = 36,
57  FS_BASE = 37,
58  GS = 38,
59  GS_BASE = 39,
60  HAX = 40,
61  HBP = 41,
62  HBX = 42,
63  HCX = 43,
64  HDI = 44,
65  HDX = 45,
66  HIP = 46,
67  HSI = 47,
68  HSP = 48,
69  IP = 49,
70  MXCSR = 50,
71  RAX = 51,
72  RBP = 52,
73  RBX = 53,
74  RCX = 54,
75  RDI = 55,
76  RDX = 56,
77  RFLAGS = 57,
78  RIP = 58,
79  RIZ = 59,
80  RSI = 60,
81  RSP = 61,
82  SI = 62,
83  SIH = 63,
84  SIL = 64,
85  SP = 65,
86  SPH = 66,
87  SPL = 67,
88  SS = 68,
89  SSP = 69,
90  TMMCFG = 70,
91  _EFLAGS = 71,
92  CR0 = 72,
93  CR1 = 73,
94  CR2 = 74,
95  CR3 = 75,
96  CR4 = 76,
97  CR5 = 77,
98  CR6 = 78,
99  CR7 = 79,
100  CR8 = 80,
101  CR9 = 81,
102  CR10 = 82,
103  CR11 = 83,
104  CR12 = 84,
105  CR13 = 85,
106  CR14 = 86,
107  CR15 = 87,
108  DR0 = 88,
109  DR1 = 89,
110  DR2 = 90,
111  DR3 = 91,
112  DR4 = 92,
113  DR5 = 93,
114  DR6 = 94,
115  DR7 = 95,
116  DR8 = 96,
117  DR9 = 97,
118  DR10 = 98,
119  DR11 = 99,
120  DR12 = 100,
121  DR13 = 101,
122  DR14 = 102,
123  DR15 = 103,
124  FP0 = 104,
125  FP1 = 105,
126  FP2 = 106,
127  FP3 = 107,
128  FP4 = 108,
129  FP5 = 109,
130  FP6 = 110,
131  FP7 = 111,
132  K0 = 112,
133  K1 = 113,
134  K2 = 114,
135  K3 = 115,
136  K4 = 116,
137  K5 = 117,
138  K6 = 118,
139  K7 = 119,
140  MM0 = 120,
141  MM1 = 121,
142  MM2 = 122,
143  MM3 = 123,
144  MM4 = 124,
145  MM5 = 125,
146  MM6 = 126,
147  MM7 = 127,
148  R8 = 128,
149  R9 = 129,
150  R10 = 130,
151  R11 = 131,
152  R12 = 132,
153  R13 = 133,
154  R14 = 134,
155  R15 = 135,
156  ST0 = 136,
157  ST1 = 137,
158  ST2 = 138,
159  ST3 = 139,
160  ST4 = 140,
161  ST5 = 141,
162  ST6 = 142,
163  ST7 = 143,
164  TMM0 = 144,
165  TMM1 = 145,
166  TMM2 = 146,
167  TMM3 = 147,
168  TMM4 = 148,
169  TMM5 = 149,
170  TMM6 = 150,
171  TMM7 = 151,
172  XMM0 = 152,
173  XMM1 = 153,
174  XMM2 = 154,
175  XMM3 = 155,
176  XMM4 = 156,
177  XMM5 = 157,
178  XMM6 = 158,
179  XMM7 = 159,
180  XMM8 = 160,
181  XMM9 = 161,
182  XMM10 = 162,
183  XMM11 = 163,
184  XMM12 = 164,
185  XMM13 = 165,
186  XMM14 = 166,
187  XMM15 = 167,
188  XMM16 = 168,
189  XMM17 = 169,
190  XMM18 = 170,
191  XMM19 = 171,
192  XMM20 = 172,
193  XMM21 = 173,
194  XMM22 = 174,
195  XMM23 = 175,
196  XMM24 = 176,
197  XMM25 = 177,
198  XMM26 = 178,
199  XMM27 = 179,
200  XMM28 = 180,
201  XMM29 = 181,
202  XMM30 = 182,
203  XMM31 = 183,
204  YMM0 = 184,
205  YMM1 = 185,
206  YMM2 = 186,
207  YMM3 = 187,
208  YMM4 = 188,
209  YMM5 = 189,
210  YMM6 = 190,
211  YMM7 = 191,
212  YMM8 = 192,
213  YMM9 = 193,
214  YMM10 = 194,
215  YMM11 = 195,
216  YMM12 = 196,
217  YMM13 = 197,
218  YMM14 = 198,
219  YMM15 = 199,
220  YMM16 = 200,
221  YMM17 = 201,
222  YMM18 = 202,
223  YMM19 = 203,
224  YMM20 = 204,
225  YMM21 = 205,
226  YMM22 = 206,
227  YMM23 = 207,
228  YMM24 = 208,
229  YMM25 = 209,
230  YMM26 = 210,
231  YMM27 = 211,
232  YMM28 = 212,
233  YMM29 = 213,
234  YMM30 = 214,
235  YMM31 = 215,
236  ZMM0 = 216,
237  ZMM1 = 217,
238  ZMM2 = 218,
239  ZMM3 = 219,
240  ZMM4 = 220,
241  ZMM5 = 221,
242  ZMM6 = 222,
243  ZMM7 = 223,
244  ZMM8 = 224,
245  ZMM9 = 225,
246  ZMM10 = 226,
247  ZMM11 = 227,
248  ZMM12 = 228,
249  ZMM13 = 229,
250  ZMM14 = 230,
251  ZMM15 = 231,
252  ZMM16 = 232,
253  ZMM17 = 233,
254  ZMM18 = 234,
255  ZMM19 = 235,
256  ZMM20 = 236,
257  ZMM21 = 237,
258  ZMM22 = 238,
259  ZMM23 = 239,
260  ZMM24 = 240,
261  ZMM25 = 241,
262  ZMM26 = 242,
263  ZMM27 = 243,
264  ZMM28 = 244,
265  ZMM29 = 245,
266  ZMM30 = 246,
267  ZMM31 = 247,
268  R8B = 248,
269  R9B = 249,
270  R10B = 250,
271  R11B = 251,
272  R12B = 252,
273  R13B = 253,
274  R14B = 254,
275  R15B = 255,
276  R8BH = 256,
277  R9BH = 257,
278  R10BH = 258,
279  R11BH = 259,
280  R12BH = 260,
281  R13BH = 261,
282  R14BH = 262,
283  R15BH = 263,
284  R8D = 264,
285  R9D = 265,
286  R10D = 266,
287  R11D = 267,
288  R12D = 268,
289  R13D = 269,
290  R14D = 270,
291  R15D = 271,
292  R8W = 272,
293  R9W = 273,
294  R10W = 274,
295  R11W = 275,
296  R12W = 276,
297  R13W = 277,
298  R14W = 278,
299  R15W = 279,
300  R8WH = 280,
301  R9WH = 281,
302  R10WH = 282,
303  R11WH = 283,
304  R12WH = 284,
305  R13WH = 285,
306  R14WH = 286,
307  R15WH = 287,
308  K0_K1 = 288,
309  K2_K3 = 289,
310  K4_K5 = 290,
311  K6_K7 = 291,
312  NUM_TARGET_REGS // 292
313};
314} // end namespace X86
315
316// Register classes
317
318namespace X86 {
319enum {
320  GR8RegClassID = 0,
321  GRH8RegClassID = 1,
322  GR8_NOREXRegClassID = 2,
323  GR8_ABCD_HRegClassID = 3,
324  GR8_ABCD_LRegClassID = 4,
325  GRH16RegClassID = 5,
326  GR16RegClassID = 6,
327  GR16_NOREXRegClassID = 7,
328  VK1RegClassID = 8,
329  VK16RegClassID = 9,
330  VK2RegClassID = 10,
331  VK4RegClassID = 11,
332  VK8RegClassID = 12,
333  VK16WMRegClassID = 13,
334  VK1WMRegClassID = 14,
335  VK2WMRegClassID = 15,
336  VK4WMRegClassID = 16,
337  VK8WMRegClassID = 17,
338  SEGMENT_REGRegClassID = 18,
339  GR16_ABCDRegClassID = 19,
340  FPCCRRegClassID = 20,
341  FR16XRegClassID = 21,
342  FR16RegClassID = 22,
343  VK16PAIRRegClassID = 23,
344  VK1PAIRRegClassID = 24,
345  VK2PAIRRegClassID = 25,
346  VK4PAIRRegClassID = 26,
347  VK8PAIRRegClassID = 27,
348  VK16PAIR_with_sub_mask_0_in_VK16WMRegClassID = 28,
349  FR32XRegClassID = 29,
350  LOW32_ADDR_ACCESS_RBPRegClassID = 30,
351  LOW32_ADDR_ACCESSRegClassID = 31,
352  LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID = 32,
353  DEBUG_REGRegClassID = 33,
354  FR32RegClassID = 34,
355  GR32RegClassID = 35,
356  GR32_NOSPRegClassID = 36,
357  LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID = 37,
358  GR32_NOREXRegClassID = 38,
359  VK32RegClassID = 39,
360  GR32_NOREX_NOSPRegClassID = 40,
361  RFP32RegClassID = 41,
362  VK32WMRegClassID = 42,
363  GR32_ABCDRegClassID = 43,
364  GR32_TCRegClassID = 44,
365  GR32_ABCD_and_GR32_TCRegClassID = 45,
366  GR32_ADRegClassID = 46,
367  GR32_BPSPRegClassID = 47,
368  GR32_BSIRegClassID = 48,
369  GR32_CBRegClassID = 49,
370  GR32_DCRegClassID = 50,
371  GR32_DIBPRegClassID = 51,
372  GR32_SIDIRegClassID = 52,
373  LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID = 53,
374  CCRRegClassID = 54,
375  DFCCRRegClassID = 55,
376  GR32_ABCD_and_GR32_BSIRegClassID = 56,
377  GR32_AD_and_GR32_DCRegClassID = 57,
378  GR32_BPSP_and_GR32_DIBPRegClassID = 58,
379  GR32_BPSP_and_GR32_TCRegClassID = 59,
380  GR32_BSI_and_GR32_SIDIRegClassID = 60,
381  GR32_CB_and_GR32_DCRegClassID = 61,
382  GR32_DIBP_and_GR32_SIDIRegClassID = 62,
383  LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID = 63,
384  LOW32_ADDR_ACCESS_with_sub_32bitRegClassID = 64,
385  RFP64RegClassID = 65,
386  FR64XRegClassID = 66,
387  GR64RegClassID = 67,
388  CONTROL_REGRegClassID = 68,
389  FR64RegClassID = 69,
390  GR64_with_sub_8bitRegClassID = 70,
391  GR64_NOSPRegClassID = 71,
392  GR64PLTSafeRegClassID = 72,
393  GR64_TCRegClassID = 73,
394  GR64_NOREXRegClassID = 74,
395  GR64_TCW64RegClassID = 75,
396  GR64_TC_with_sub_8bitRegClassID = 76,
397  GR64_NOSP_and_GR64_TCRegClassID = 77,
398  GR64_TCW64_with_sub_8bitRegClassID = 78,
399  GR64_TC_and_GR64_TCW64RegClassID = 79,
400  GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 80,
401  VK64RegClassID = 81,
402  VR64RegClassID = 82,
403  GR64PLTSafe_and_GR64_TCRegClassID = 83,
404  GR64_NOREX_NOSPRegClassID = 84,
405  GR64_NOREX_and_GR64_TCRegClassID = 85,
406  GR64_NOSP_and_GR64_TCW64RegClassID = 86,
407  GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID = 87,
408  VK64WMRegClassID = 88,
409  GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID = 89,
410  GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 90,
411  GR64PLTSafe_and_GR64_TCW64RegClassID = 91,
412  GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID = 92,
413  GR64_NOREX_and_GR64_TCW64RegClassID = 93,
414  GR64_ABCDRegClassID = 94,
415  GR64_with_sub_32bit_in_GR32_TCRegClassID = 95,
416  GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID = 96,
417  GR64_ADRegClassID = 97,
418  GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID = 98,
419  GR64_with_sub_32bit_in_GR32_BPSPRegClassID = 99,
420  GR64_with_sub_32bit_in_GR32_BSIRegClassID = 100,
421  GR64_with_sub_32bit_in_GR32_CBRegClassID = 101,
422  GR64_with_sub_32bit_in_GR32_DCRegClassID = 102,
423  GR64_with_sub_32bit_in_GR32_DIBPRegClassID = 103,
424  GR64_with_sub_32bit_in_GR32_SIDIRegClassID = 104,
425  GR64_and_LOW32_ADDR_ACCESSRegClassID = 105,
426  GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID = 106,
427  GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID = 107,
428  GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID = 108,
429  GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID = 109,
430  GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID = 110,
431  GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID = 111,
432  GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID = 112,
433  RSTRegClassID = 113,
434  RFP80RegClassID = 114,
435  RFP80_7RegClassID = 115,
436  VR128XRegClassID = 116,
437  VR128RegClassID = 117,
438  VR256XRegClassID = 118,
439  VR256RegClassID = 119,
440  VR512RegClassID = 120,
441  VR512_0_15RegClassID = 121,
442  TILERegClassID = 122,
443
444};
445} // end namespace X86
446
447
448// Subregister indices
449
450namespace X86 {
451enum : uint16_t {
452  NoSubRegister,
453  sub_8bit,	// 1
454  sub_8bit_hi,	// 2
455  sub_8bit_hi_phony,	// 3
456  sub_16bit,	// 4
457  sub_16bit_hi,	// 5
458  sub_32bit,	// 6
459  sub_mask_0,	// 7
460  sub_mask_1,	// 8
461  sub_xmm,	// 9
462  sub_ymm,	// 10
463  NUM_TARGET_SUBREGS
464};
465} // end namespace X86
466
467// Register pressure sets enum.
468namespace X86 {
469enum RegisterPressureSets {
470  SEGMENT_REG = 0,
471  GR32_BPSP = 1,
472  LOW32_ADDR_ACCESS_with_sub_32bit = 2,
473  GR32_BSI = 3,
474  GR32_SIDI = 4,
475  GR32_DIBP_with_GR32_SIDI = 5,
476  GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit = 6,
477  RFP32 = 7,
478  GR8_ABCD_H_with_GR32_BSI = 8,
479  GR8_ABCD_L_with_GR32_BSI = 9,
480  VK1 = 10,
481  VR64 = 11,
482  TILE = 12,
483  GR8_NOREX = 13,
484  GR32_TC = 14,
485  GR32_BPSP_with_GR32_TC = 15,
486  FR16 = 16,
487  DEBUG_REG = 17,
488  CONTROL_REG = 18,
489  GR64_NOREX = 19,
490  GR64_TCW64 = 20,
491  GR32_BPSP_with_GR64_TCW64 = 21,
492  GR8 = 22,
493  GR8_with_GR32_DIBP = 23,
494  GR8_with_GR32_BSI = 24,
495  GR64_TC_with_GR64_TCW64 = 25,
496  GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit = 26,
497  GR8_with_GR64_NOREX = 27,
498  GR64_TC = 28,
499  GR8_with_GR64_TCW64 = 29,
500  GR8_with_GR64_TC = 30,
501  GR8_with_GR64PLTSafe = 31,
502  FR16X = 32,
503  GR16 = 33,
504};
505} // end namespace X86
506
507} // end namespace llvm
508
509#endif // GET_REGINFO_ENUM
510
511/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
512|*                                                                            *|
513|* MC Register Information                                                    *|
514|*                                                                            *|
515|* Automatically generated file, do not edit!                                 *|
516|*                                                                            *|
517\*===----------------------------------------------------------------------===*/
518
519
520#ifdef GET_REGINFO_MC_DESC
521#undef GET_REGINFO_MC_DESC
522
523namespace llvm {
524
525extern const MCPhysReg X86RegDiffLists[] = {
526  /* 0 */ 0, 1, 0,
527  /* 3 */ 64845, 1, 1, 0,
528  /* 7 */ 65253, 1, 1, 0,
529  /* 11 */ 65382, 1, 1, 0,
530  /* 15 */ 65466, 1, 1, 0,
531  /* 19 */ 2, 1, 0,
532  /* 22 */ 4, 1, 0,
533  /* 25 */ 6, 1, 0,
534  /* 28 */ 11, 1, 0,
535  /* 31 */ 22, 1, 0,
536  /* 34 */ 26, 1, 0,
537  /* 37 */ 29, 1, 0,
538  /* 40 */ 64821, 1, 0,
539  /* 43 */ 65045, 1, 0,
540  /* 46 */ 65360, 1, 0,
541  /* 49 */ 65361, 1, 0,
542  /* 52 */ 65362, 1, 0,
543  /* 55 */ 65363, 1, 0,
544  /* 58 */ 10, 3, 0,
545  /* 61 */ 4, 0,
546  /* 63 */ 5, 0,
547  /* 65 */ 65272, 1, 7, 0,
548  /* 69 */ 65417, 1, 7, 0,
549  /* 73 */ 10, 3, 7, 0,
550  /* 77 */ 65512, 8, 0,
551  /* 80 */ 65326, 1, 11, 0,
552  /* 84 */ 65332, 1, 11, 0,
553  /* 88 */ 65442, 1, 11, 0,
554  /* 92 */ 65448, 1, 11, 0,
555  /* 96 */ 12, 0,
556  /* 98 */ 65326, 1, 14, 0,
557  /* 102 */ 65332, 1, 14, 0,
558  /* 106 */ 65442, 1, 14, 0,
559  /* 110 */ 65448, 1, 14, 0,
560  /* 114 */ 21, 0,
561  /* 116 */ 22, 0,
562  /* 118 */ 136, 8, 65512, 8, 24, 0,
563  /* 124 */ 26, 0,
564  /* 126 */ 65507, 65526, 2, 65535, 27, 0,
565  /* 132 */ 65534, 65504, 28, 0,
566  /* 136 */ 65535, 65504, 28, 0,
567  /* 140 */ 65534, 65506, 28, 0,
568  /* 144 */ 65535, 65506, 28, 0,
569  /* 148 */ 65521, 28, 0,
570  /* 151 */ 2, 6, 29, 0,
571  /* 155 */ 6, 6, 29, 0,
572  /* 159 */ 65534, 10, 29, 0,
573  /* 163 */ 65535, 10, 29, 0,
574  /* 167 */ 2, 12, 29, 0,
575  /* 171 */ 3, 12, 29, 0,
576  /* 175 */ 4, 15, 29, 0,
577  /* 179 */ 5, 15, 29, 0,
578  /* 183 */ 65534, 17, 29, 0,
579  /* 187 */ 65535, 17, 29, 0,
580  /* 191 */ 1, 19, 29, 0,
581  /* 195 */ 2, 19, 29, 0,
582  /* 199 */ 65516, 29, 0,
583  /* 202 */ 65518, 29, 0,
584  /* 205 */ 65519, 29, 0,
585  /* 208 */ 65507, 65530, 65534, 65532, 30, 0,
586  /* 214 */ 32, 32, 0,
587  /* 217 */ 65507, 65524, 65534, 65535, 33, 0,
588  /* 223 */ 65507, 65519, 2, 65535, 34, 0,
589  /* 229 */ 65507, 65521, 65532, 65535, 38, 0,
590  /* 235 */ 65507, 65517, 65535, 65535, 39, 0,
591  /* 241 */ 40, 0,
592  /* 243 */ 172, 0,
593  /* 245 */ 173, 0,
594  /* 247 */ 174, 0,
595  /* 249 */ 175, 0,
596  /* 251 */ 176, 0,
597  /* 253 */ 64761, 0,
598  /* 255 */ 64799, 0,
599  /* 257 */ 64870, 0,
600  /* 259 */ 64893, 0,
601  /* 261 */ 65520, 65400, 0,
602  /* 264 */ 16, 65528, 65400, 0,
603  /* 268 */ 24, 65528, 65400, 0,
604  /* 272 */ 65421, 0,
605  /* 274 */ 65423, 0,
606  /* 276 */ 65461, 0,
607  /* 278 */ 65493, 0,
608  /* 280 */ 65504, 65504, 0,
609  /* 283 */ 65509, 0,
610  /* 285 */ 65511, 0,
611  /* 287 */ 65508, 32, 2, 65535, 65518, 0,
612  /* 293 */ 65508, 30, 2, 65535, 65520, 0,
613  /* 299 */ 65525, 0,
614  /* 301 */ 65530, 0,
615  /* 303 */ 65531, 0,
616  /* 305 */ 65534, 65532, 0,
617  /* 308 */ 65507, 20, 65533, 0,
618  /* 312 */ 65534, 0,
619  /* 314 */ 2, 65535, 0,
620  /* 317 */ 65532, 65535, 0,
621  /* 320 */ 65534, 65535, 0,
622  /* 323 */ 65535, 65535, 0,
623};
624
625extern const LaneBitmask X86LaneMaskLists[] = {
626  /* 0 */ LaneBitmask(0x0000000000000000), LaneBitmask::getAll(),
627  /* 2 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
628  /* 5 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004), LaneBitmask::getAll(),
629  /* 8 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(),
630  /* 12 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(),
631  /* 16 */ LaneBitmask(0x0000000000000007), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(),
632  /* 19 */ LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask::getAll(),
633  /* 22 */ LaneBitmask(0x0000000000000040), LaneBitmask::getAll(),
634};
635
636extern const uint16_t X86SubRegIdxLists[] = {
637  /* 0 */ 1, 2, 0,
638  /* 3 */ 1, 3, 0,
639  /* 6 */ 6, 4, 1, 2, 5, 0,
640  /* 12 */ 6, 4, 1, 3, 5, 0,
641  /* 18 */ 6, 4, 5, 0,
642  /* 22 */ 7, 8, 0,
643  /* 25 */ 10, 9, 0,
644};
645
646extern const MCRegisterInfo::SubRegCoveredBits X86SubRegIdxRanges[] = {
647  { 65535, 65535 },
648  { 0, 8 },	// sub_8bit
649  { 8, 8 },	// sub_8bit_hi
650  { 8, 8 },	// sub_8bit_hi_phony
651  { 0, 16 },	// sub_16bit
652  { 16, 16 },	// sub_16bit_hi
653  { 0, 32 },	// sub_32bit
654  { 0, 65535 },	// sub_mask_0
655  { 65535, 65535 },	// sub_mask_1
656  { 0, 128 },	// sub_xmm
657  { 0, 256 },	// sub_ymm
658};
659
660extern const char X86RegStrings[] = {
661  /* 0 */ 'X', 'M', 'M', '1', '0', 0,
662  /* 6 */ 'Y', 'M', 'M', '1', '0', 0,
663  /* 12 */ 'Z', 'M', 'M', '1', '0', 0,
664  /* 18 */ 'C', 'R', '1', '0', 0,
665  /* 23 */ 'D', 'R', '1', '0', 0,
666  /* 28 */ 'X', 'M', 'M', '2', '0', 0,
667  /* 34 */ 'Y', 'M', 'M', '2', '0', 0,
668  /* 40 */ 'Z', 'M', 'M', '2', '0', 0,
669  /* 46 */ 'X', 'M', 'M', '3', '0', 0,
670  /* 52 */ 'Y', 'M', 'M', '3', '0', 0,
671  /* 58 */ 'Z', 'M', 'M', '3', '0', 0,
672  /* 64 */ 'K', '0', 0,
673  /* 67 */ 'T', 'M', 'M', '0', 0,
674  /* 72 */ 'X', 'M', 'M', '0', 0,
675  /* 77 */ 'Y', 'M', 'M', '0', 0,
676  /* 82 */ 'Z', 'M', 'M', '0', 0,
677  /* 87 */ 'F', 'P', '0', 0,
678  /* 91 */ 'C', 'R', '0', 0,
679  /* 95 */ 'D', 'R', '0', 0,
680  /* 99 */ 'S', 'T', '0', 0,
681  /* 103 */ 'X', 'M', 'M', '1', '1', 0,
682  /* 109 */ 'Y', 'M', 'M', '1', '1', 0,
683  /* 115 */ 'Z', 'M', 'M', '1', '1', 0,
684  /* 121 */ 'C', 'R', '1', '1', 0,
685  /* 126 */ 'D', 'R', '1', '1', 0,
686  /* 131 */ 'X', 'M', 'M', '2', '1', 0,
687  /* 137 */ 'Y', 'M', 'M', '2', '1', 0,
688  /* 143 */ 'Z', 'M', 'M', '2', '1', 0,
689  /* 149 */ 'X', 'M', 'M', '3', '1', 0,
690  /* 155 */ 'Y', 'M', 'M', '3', '1', 0,
691  /* 161 */ 'Z', 'M', 'M', '3', '1', 0,
692  /* 167 */ 'K', '0', '_', 'K', '1', 0,
693  /* 173 */ 'T', 'M', 'M', '1', 0,
694  /* 178 */ 'X', 'M', 'M', '1', 0,
695  /* 183 */ 'Y', 'M', 'M', '1', 0,
696  /* 188 */ 'Z', 'M', 'M', '1', 0,
697  /* 193 */ 'F', 'P', '1', 0,
698  /* 197 */ 'C', 'R', '1', 0,
699  /* 201 */ 'D', 'R', '1', 0,
700  /* 205 */ 'S', 'T', '1', 0,
701  /* 209 */ 'X', 'M', 'M', '1', '2', 0,
702  /* 215 */ 'Y', 'M', 'M', '1', '2', 0,
703  /* 221 */ 'Z', 'M', 'M', '1', '2', 0,
704  /* 227 */ 'C', 'R', '1', '2', 0,
705  /* 232 */ 'D', 'R', '1', '2', 0,
706  /* 237 */ 'X', 'M', 'M', '2', '2', 0,
707  /* 243 */ 'Y', 'M', 'M', '2', '2', 0,
708  /* 249 */ 'Z', 'M', 'M', '2', '2', 0,
709  /* 255 */ 'K', '2', 0,
710  /* 258 */ 'T', 'M', 'M', '2', 0,
711  /* 263 */ 'X', 'M', 'M', '2', 0,
712  /* 268 */ 'Y', 'M', 'M', '2', 0,
713  /* 273 */ 'Z', 'M', 'M', '2', 0,
714  /* 278 */ 'F', 'P', '2', 0,
715  /* 282 */ 'C', 'R', '2', 0,
716  /* 286 */ 'D', 'R', '2', 0,
717  /* 290 */ 'S', 'T', '2', 0,
718  /* 294 */ 'X', 'M', 'M', '1', '3', 0,
719  /* 300 */ 'Y', 'M', 'M', '1', '3', 0,
720  /* 306 */ 'Z', 'M', 'M', '1', '3', 0,
721  /* 312 */ 'C', 'R', '1', '3', 0,
722  /* 317 */ 'D', 'R', '1', '3', 0,
723  /* 322 */ 'X', 'M', 'M', '2', '3', 0,
724  /* 328 */ 'Y', 'M', 'M', '2', '3', 0,
725  /* 334 */ 'Z', 'M', 'M', '2', '3', 0,
726  /* 340 */ 'K', '2', '_', 'K', '3', 0,
727  /* 346 */ 'T', 'M', 'M', '3', 0,
728  /* 351 */ 'X', 'M', 'M', '3', 0,
729  /* 356 */ 'Y', 'M', 'M', '3', 0,
730  /* 361 */ 'Z', 'M', 'M', '3', 0,
731  /* 366 */ 'F', 'P', '3', 0,
732  /* 370 */ 'C', 'R', '3', 0,
733  /* 374 */ 'D', 'R', '3', 0,
734  /* 378 */ 'S', 'T', '3', 0,
735  /* 382 */ 'X', 'M', 'M', '1', '4', 0,
736  /* 388 */ 'Y', 'M', 'M', '1', '4', 0,
737  /* 394 */ 'Z', 'M', 'M', '1', '4', 0,
738  /* 400 */ 'C', 'R', '1', '4', 0,
739  /* 405 */ 'D', 'R', '1', '4', 0,
740  /* 410 */ 'X', 'M', 'M', '2', '4', 0,
741  /* 416 */ 'Y', 'M', 'M', '2', '4', 0,
742  /* 422 */ 'Z', 'M', 'M', '2', '4', 0,
743  /* 428 */ 'K', '4', 0,
744  /* 431 */ 'T', 'M', 'M', '4', 0,
745  /* 436 */ 'X', 'M', 'M', '4', 0,
746  /* 441 */ 'Y', 'M', 'M', '4', 0,
747  /* 446 */ 'Z', 'M', 'M', '4', 0,
748  /* 451 */ 'F', 'P', '4', 0,
749  /* 455 */ 'C', 'R', '4', 0,
750  /* 459 */ 'D', 'R', '4', 0,
751  /* 463 */ 'S', 'T', '4', 0,
752  /* 467 */ 'X', 'M', 'M', '1', '5', 0,
753  /* 473 */ 'Y', 'M', 'M', '1', '5', 0,
754  /* 479 */ 'Z', 'M', 'M', '1', '5', 0,
755  /* 485 */ 'C', 'R', '1', '5', 0,
756  /* 490 */ 'D', 'R', '1', '5', 0,
757  /* 495 */ 'X', 'M', 'M', '2', '5', 0,
758  /* 501 */ 'Y', 'M', 'M', '2', '5', 0,
759  /* 507 */ 'Z', 'M', 'M', '2', '5', 0,
760  /* 513 */ 'K', '4', '_', 'K', '5', 0,
761  /* 519 */ 'T', 'M', 'M', '5', 0,
762  /* 524 */ 'X', 'M', 'M', '5', 0,
763  /* 529 */ 'Y', 'M', 'M', '5', 0,
764  /* 534 */ 'Z', 'M', 'M', '5', 0,
765  /* 539 */ 'F', 'P', '5', 0,
766  /* 543 */ 'C', 'R', '5', 0,
767  /* 547 */ 'D', 'R', '5', 0,
768  /* 551 */ 'S', 'T', '5', 0,
769  /* 555 */ 'X', 'M', 'M', '1', '6', 0,
770  /* 561 */ 'Y', 'M', 'M', '1', '6', 0,
771  /* 567 */ 'Z', 'M', 'M', '1', '6', 0,
772  /* 573 */ 'X', 'M', 'M', '2', '6', 0,
773  /* 579 */ 'Y', 'M', 'M', '2', '6', 0,
774  /* 585 */ 'Z', 'M', 'M', '2', '6', 0,
775  /* 591 */ 'K', '6', 0,
776  /* 594 */ 'T', 'M', 'M', '6', 0,
777  /* 599 */ 'X', 'M', 'M', '6', 0,
778  /* 604 */ 'Y', 'M', 'M', '6', 0,
779  /* 609 */ 'Z', 'M', 'M', '6', 0,
780  /* 614 */ 'F', 'P', '6', 0,
781  /* 618 */ 'C', 'R', '6', 0,
782  /* 622 */ 'D', 'R', '6', 0,
783  /* 626 */ 'S', 'T', '6', 0,
784  /* 630 */ 'X', 'M', 'M', '1', '7', 0,
785  /* 636 */ 'Y', 'M', 'M', '1', '7', 0,
786  /* 642 */ 'Z', 'M', 'M', '1', '7', 0,
787  /* 648 */ 'X', 'M', 'M', '2', '7', 0,
788  /* 654 */ 'Y', 'M', 'M', '2', '7', 0,
789  /* 660 */ 'Z', 'M', 'M', '2', '7', 0,
790  /* 666 */ 'K', '6', '_', 'K', '7', 0,
791  /* 672 */ 'T', 'M', 'M', '7', 0,
792  /* 677 */ 'X', 'M', 'M', '7', 0,
793  /* 682 */ 'Y', 'M', 'M', '7', 0,
794  /* 687 */ 'Z', 'M', 'M', '7', 0,
795  /* 692 */ 'F', 'P', '7', 0,
796  /* 696 */ 'C', 'R', '7', 0,
797  /* 700 */ 'D', 'R', '7', 0,
798  /* 704 */ 'S', 'T', '7', 0,
799  /* 708 */ 'X', 'M', 'M', '1', '8', 0,
800  /* 714 */ 'Y', 'M', 'M', '1', '8', 0,
801  /* 720 */ 'Z', 'M', 'M', '1', '8', 0,
802  /* 726 */ 'X', 'M', 'M', '2', '8', 0,
803  /* 732 */ 'Y', 'M', 'M', '2', '8', 0,
804  /* 738 */ 'Z', 'M', 'M', '2', '8', 0,
805  /* 744 */ 'X', 'M', 'M', '8', 0,
806  /* 749 */ 'Y', 'M', 'M', '8', 0,
807  /* 754 */ 'Z', 'M', 'M', '8', 0,
808  /* 759 */ 'C', 'R', '8', 0,
809  /* 763 */ 'D', 'R', '8', 0,
810  /* 767 */ 'X', 'M', 'M', '1', '9', 0,
811  /* 773 */ 'Y', 'M', 'M', '1', '9', 0,
812  /* 779 */ 'Z', 'M', 'M', '1', '9', 0,
813  /* 785 */ 'X', 'M', 'M', '2', '9', 0,
814  /* 791 */ 'Y', 'M', 'M', '2', '9', 0,
815  /* 797 */ 'Z', 'M', 'M', '2', '9', 0,
816  /* 803 */ 'X', 'M', 'M', '9', 0,
817  /* 808 */ 'Y', 'M', 'M', '9', 0,
818  /* 813 */ 'Z', 'M', 'M', '9', 0,
819  /* 818 */ 'C', 'R', '9', 0,
820  /* 822 */ 'D', 'R', '9', 0,
821  /* 826 */ 'R', '1', '0', 'B', 0,
822  /* 831 */ 'R', '1', '1', 'B', 0,
823  /* 836 */ 'R', '1', '2', 'B', 0,
824  /* 841 */ 'R', '1', '3', 'B', 0,
825  /* 846 */ 'R', '1', '4', 'B', 0,
826  /* 851 */ 'R', '1', '5', 'B', 0,
827  /* 856 */ 'R', '8', 'B', 0,
828  /* 860 */ 'R', '9', 'B', 0,
829  /* 864 */ 'R', '1', '0', 'D', 0,
830  /* 869 */ 'R', '1', '1', 'D', 0,
831  /* 874 */ 'R', '1', '2', 'D', 0,
832  /* 879 */ 'R', '1', '3', 'D', 0,
833  /* 884 */ 'R', '1', '4', 'D', 0,
834  /* 889 */ 'R', '1', '5', 'D', 0,
835  /* 894 */ 'R', '8', 'D', 0,
836  /* 898 */ 'R', '9', 'D', 0,
837  /* 902 */ 'F', 'S', '_', 'B', 'A', 'S', 'E', 0,
838  /* 910 */ 'G', 'S', '_', 'B', 'A', 'S', 'E', 0,
839  /* 918 */ 'D', 'F', 0,
840  /* 921 */ 'T', 'M', 'M', 'C', 'F', 'G', 0,
841  /* 928 */ 'A', 'H', 0,
842  /* 931 */ 'R', '1', '0', 'B', 'H', 0,
843  /* 937 */ 'R', '1', '1', 'B', 'H', 0,
844  /* 943 */ 'R', '1', '2', 'B', 'H', 0,
845  /* 949 */ 'R', '1', '3', 'B', 'H', 0,
846  /* 955 */ 'R', '1', '4', 'B', 'H', 0,
847  /* 961 */ 'R', '1', '5', 'B', 'H', 0,
848  /* 967 */ 'R', '8', 'B', 'H', 0,
849  /* 972 */ 'R', '9', 'B', 'H', 0,
850  /* 977 */ 'C', 'H', 0,
851  /* 980 */ 'D', 'H', 0,
852  /* 983 */ 'D', 'I', 'H', 0,
853  /* 987 */ 'S', 'I', 'H', 0,
854  /* 991 */ 'B', 'P', 'H', 0,
855  /* 995 */ 'S', 'P', 'H', 0,
856  /* 999 */ 'R', '1', '0', 'W', 'H', 0,
857  /* 1005 */ 'R', '1', '1', 'W', 'H', 0,
858  /* 1011 */ 'R', '1', '2', 'W', 'H', 0,
859  /* 1017 */ 'R', '1', '3', 'W', 'H', 0,
860  /* 1023 */ 'R', '1', '4', 'W', 'H', 0,
861  /* 1029 */ 'R', '1', '5', 'W', 'H', 0,
862  /* 1035 */ 'R', '8', 'W', 'H', 0,
863  /* 1040 */ 'R', '9', 'W', 'H', 0,
864  /* 1045 */ 'E', 'D', 'I', 0,
865  /* 1049 */ 'H', 'D', 'I', 0,
866  /* 1053 */ 'R', 'D', 'I', 0,
867  /* 1057 */ 'E', 'S', 'I', 0,
868  /* 1061 */ 'H', 'S', 'I', 0,
869  /* 1065 */ 'R', 'S', 'I', 0,
870  /* 1069 */ 'A', 'L', 0,
871  /* 1072 */ 'B', 'L', 0,
872  /* 1075 */ 'C', 'L', 0,
873  /* 1078 */ 'D', 'L', 0,
874  /* 1081 */ 'D', 'I', 'L', 0,
875  /* 1085 */ 'S', 'I', 'L', 0,
876  /* 1089 */ 'B', 'P', 'L', 0,
877  /* 1093 */ 'S', 'P', 'L', 0,
878  /* 1097 */ 'E', 'B', 'P', 0,
879  /* 1101 */ 'H', 'B', 'P', 0,
880  /* 1105 */ 'R', 'B', 'P', 0,
881  /* 1109 */ 'E', 'I', 'P', 0,
882  /* 1113 */ 'H', 'I', 'P', 0,
883  /* 1117 */ 'R', 'I', 'P', 0,
884  /* 1121 */ 'E', 'S', 'P', 0,
885  /* 1125 */ 'H', 'S', 'P', 0,
886  /* 1129 */ 'R', 'S', 'P', 0,
887  /* 1133 */ 'S', 'S', 'P', 0,
888  /* 1137 */ 'M', 'X', 'C', 'S', 'R', 0,
889  /* 1143 */ 'C', 'S', 0,
890  /* 1146 */ 'D', 'S', 0,
891  /* 1149 */ 'E', 'S', 0,
892  /* 1152 */ 'F', 'S', 0,
893  /* 1155 */ '_', 'E', 'F', 'L', 'A', 'G', 'S', 0,
894  /* 1163 */ 'R', 'F', 'L', 'A', 'G', 'S', 0,
895  /* 1170 */ 'S', 'S', 0,
896  /* 1173 */ 'R', '1', '0', 'W', 0,
897  /* 1178 */ 'R', '1', '1', 'W', 0,
898  /* 1183 */ 'R', '1', '2', 'W', 0,
899  /* 1188 */ 'R', '1', '3', 'W', 0,
900  /* 1193 */ 'R', '1', '4', 'W', 0,
901  /* 1198 */ 'R', '1', '5', 'W', 0,
902  /* 1203 */ 'R', '8', 'W', 0,
903  /* 1207 */ 'R', '9', 'W', 0,
904  /* 1211 */ 'F', 'P', 'C', 'W', 0,
905  /* 1216 */ 'F', 'P', 'S', 'W', 0,
906  /* 1221 */ 'E', 'A', 'X', 0,
907  /* 1225 */ 'H', 'A', 'X', 0,
908  /* 1229 */ 'R', 'A', 'X', 0,
909  /* 1233 */ 'E', 'B', 'X', 0,
910  /* 1237 */ 'H', 'B', 'X', 0,
911  /* 1241 */ 'R', 'B', 'X', 0,
912  /* 1245 */ 'E', 'C', 'X', 0,
913  /* 1249 */ 'H', 'C', 'X', 0,
914  /* 1253 */ 'R', 'C', 'X', 0,
915  /* 1257 */ 'E', 'D', 'X', 0,
916  /* 1261 */ 'H', 'D', 'X', 0,
917  /* 1265 */ 'R', 'D', 'X', 0,
918  /* 1269 */ 'E', 'I', 'Z', 0,
919  /* 1273 */ 'R', 'I', 'Z', 0,
920  0
921};
922
923extern const MCRegisterDesc X86RegDesc[] = { // Descriptors
924  { 5, 0, 0, 0, 0, 0 },
925  { 928, 2, 195, 2, 5041, 0 },
926  { 1069, 2, 191, 2, 5041, 0 },
927  { 1222, 323, 192, 0, 0, 2 },
928  { 934, 2, 179, 2, 4993, 0 },
929  { 1072, 2, 175, 2, 4993, 0 },
930  { 1098, 314, 184, 3, 352, 5 },
931  { 991, 2, 187, 2, 1008, 0 },
932  { 1089, 2, 183, 2, 976, 0 },
933  { 1234, 317, 176, 0, 304, 2 },
934  { 977, 2, 171, 2, 4897, 0 },
935  { 1075, 2, 167, 2, 4897, 0 },
936  { 1143, 2, 2, 2, 4897, 0 },
937  { 1246, 320, 168, 0, 400, 2 },
938  { 918, 2, 2, 2, 4849, 0 },
939  { 980, 2, 155, 2, 4849, 0 },
940  { 1046, 314, 160, 3, 448, 5 },
941  { 983, 2, 163, 2, 1536, 0 },
942  { 1081, 2, 159, 2, 4562, 0 },
943  { 1078, 2, 151, 2, 4817, 0 },
944  { 1146, 2, 2, 2, 4817, 0 },
945  { 1258, 305, 152, 0, 928, 2 },
946  { 1221, 236, 153, 7, 1764, 8 },
947  { 1097, 224, 153, 13, 1476, 12 },
948  { 1233, 230, 153, 7, 1700, 8 },
949  { 1245, 218, 153, 7, 1412, 8 },
950  { 1045, 127, 153, 13, 1109, 12 },
951  { 1257, 209, 153, 7, 1168, 8 },
952  { 1156, 2, 2, 2, 1824, 0 },
953  { 1109, 309, 153, 19, 496, 16 },
954  { 1269, 2, 2, 2, 4817, 0 },
955  { 1149, 2, 2, 2, 4817, 0 },
956  { 1057, 294, 134, 13, 243, 12 },
957  { 1121, 288, 134, 13, 243, 12 },
958  { 1211, 2, 2, 2, 4993, 0 },
959  { 1216, 2, 2, 2, 4993, 0 },
960  { 1152, 2, 2, 2, 4993, 0 },
961  { 902, 2, 2, 2, 4993, 0 },
962  { 1160, 2, 2, 2, 4993, 0 },
963  { 910, 2, 2, 2, 4993, 0 },
964  { 1225, 2, 202, 2, 4561, 0 },
965  { 1101, 2, 202, 2, 4561, 0 },
966  { 1237, 2, 202, 2, 4561, 0 },
967  { 1249, 2, 202, 2, 4561, 0 },
968  { 1049, 2, 202, 2, 4561, 0 },
969  { 1261, 2, 202, 2, 4561, 0 },
970  { 1113, 2, 205, 2, 4355, 0 },
971  { 1061, 2, 148, 2, 4387, 0 },
972  { 1125, 2, 148, 2, 4387, 0 },
973  { 1110, 2, 199, 2, 1856, 0 },
974  { 1137, 2, 2, 2, 3728, 0 },
975  { 1229, 235, 2, 6, 1636, 8 },
976  { 1105, 223, 2, 12, 1348, 12 },
977  { 1241, 229, 2, 6, 1572, 8 },
978  { 1253, 217, 2, 6, 1284, 8 },
979  { 1053, 126, 2, 12, 1045, 12 },
980  { 1265, 208, 2, 6, 1168, 8 },
981  { 1163, 2, 2, 2, 3824, 0 },
982  { 1117, 308, 2, 18, 496, 16 },
983  { 1273, 2, 2, 2, 3856, 0 },
984  { 1065, 293, 2, 12, 179, 12 },
985  { 1129, 287, 2, 12, 179, 12 },
986  { 1058, 314, 141, 3, 544, 5 },
987  { 987, 2, 144, 2, 2080, 0 },
988  { 1085, 2, 140, 2, 1984, 0 },
989  { 1122, 314, 133, 3, 592, 5 },
990  { 995, 2, 136, 2, 3392, 0 },
991  { 1093, 2, 132, 2, 4060, 0 },
992  { 1170, 2, 2, 2, 4529, 0 },
993  { 1133, 2, 2, 2, 4529, 0 },
994  { 921, 2, 2, 2, 4529, 0 },
995  { 1155, 2, 2, 2, 4529, 0 },
996  { 91, 2, 2, 2, 4529, 0 },
997  { 197, 2, 2, 2, 4529, 0 },
998  { 282, 2, 2, 2, 4529, 0 },
999  { 370, 2, 2, 2, 4529, 0 },
1000  { 455, 2, 2, 2, 4529, 0 },
1001  { 543, 2, 2, 2, 4529, 0 },
1002  { 618, 2, 2, 2, 4529, 0 },
1003  { 696, 2, 2, 2, 4529, 0 },
1004  { 759, 2, 2, 2, 4529, 0 },
1005  { 818, 2, 2, 2, 4529, 0 },
1006  { 18, 2, 2, 2, 4529, 0 },
1007  { 121, 2, 2, 2, 4529, 0 },
1008  { 227, 2, 2, 2, 4529, 0 },
1009  { 312, 2, 2, 2, 4529, 0 },
1010  { 400, 2, 2, 2, 4529, 0 },
1011  { 485, 2, 2, 2, 4529, 0 },
1012  { 95, 2, 2, 2, 4529, 0 },
1013  { 201, 2, 2, 2, 4529, 0 },
1014  { 286, 2, 2, 2, 4529, 0 },
1015  { 374, 2, 2, 2, 4529, 0 },
1016  { 459, 2, 2, 2, 4529, 0 },
1017  { 547, 2, 2, 2, 4529, 0 },
1018  { 622, 2, 2, 2, 4529, 0 },
1019  { 700, 2, 2, 2, 4529, 0 },
1020  { 763, 2, 2, 2, 4529, 0 },
1021  { 822, 2, 2, 2, 4529, 0 },
1022  { 23, 2, 2, 2, 4529, 0 },
1023  { 126, 2, 2, 2, 4529, 0 },
1024  { 232, 2, 2, 2, 4529, 0 },
1025  { 317, 2, 2, 2, 4529, 0 },
1026  { 405, 2, 2, 2, 4529, 0 },
1027  { 490, 2, 2, 2, 4529, 0 },
1028  { 87, 2, 2, 2, 4529, 0 },
1029  { 193, 2, 2, 2, 4529, 0 },
1030  { 278, 2, 2, 2, 4529, 0 },
1031  { 366, 2, 2, 2, 4529, 0 },
1032  { 451, 2, 2, 2, 4529, 0 },
1033  { 539, 2, 2, 2, 4529, 0 },
1034  { 614, 2, 2, 2, 4529, 0 },
1035  { 692, 2, 2, 2, 4529, 0 },
1036  { 64, 2, 251, 2, 4529, 0 },
1037  { 170, 2, 249, 2, 4529, 0 },
1038  { 255, 2, 249, 2, 4529, 0 },
1039  { 343, 2, 247, 2, 4529, 0 },
1040  { 428, 2, 247, 2, 4529, 0 },
1041  { 516, 2, 245, 2, 4529, 0 },
1042  { 591, 2, 245, 2, 4529, 0 },
1043  { 669, 2, 243, 2, 4529, 0 },
1044  { 68, 2, 2, 2, 4529, 0 },
1045  { 174, 2, 2, 2, 4529, 0 },
1046  { 259, 2, 2, 2, 4529, 0 },
1047  { 347, 2, 2, 2, 4529, 0 },
1048  { 432, 2, 2, 2, 4529, 0 },
1049  { 520, 2, 2, 2, 4529, 0 },
1050  { 595, 2, 2, 2, 4529, 0 },
1051  { 673, 2, 2, 2, 4529, 0 },
1052  { 760, 118, 2, 12, 115, 12 },
1053  { 819, 118, 2, 12, 115, 12 },
1054  { 19, 118, 2, 12, 115, 12 },
1055  { 122, 118, 2, 12, 115, 12 },
1056  { 228, 118, 2, 12, 115, 12 },
1057  { 313, 118, 2, 12, 115, 12 },
1058  { 401, 118, 2, 12, 115, 12 },
1059  { 486, 118, 2, 12, 115, 12 },
1060  { 99, 2, 2, 2, 4785, 0 },
1061  { 205, 2, 2, 2, 4785, 0 },
1062  { 290, 2, 2, 2, 4785, 0 },
1063  { 378, 2, 2, 2, 4785, 0 },
1064  { 463, 2, 2, 2, 4785, 0 },
1065  { 551, 2, 2, 2, 4785, 0 },
1066  { 626, 2, 2, 2, 4785, 0 },
1067  { 704, 2, 2, 2, 4785, 0 },
1068  { 67, 2, 2, 2, 4785, 0 },
1069  { 173, 2, 2, 2, 4785, 0 },
1070  { 258, 2, 2, 2, 4785, 0 },
1071  { 346, 2, 2, 2, 4785, 0 },
1072  { 431, 2, 2, 2, 4785, 0 },
1073  { 519, 2, 2, 2, 4785, 0 },
1074  { 594, 2, 2, 2, 4785, 0 },
1075  { 672, 2, 2, 2, 4785, 0 },
1076  { 72, 2, 214, 2, 4785, 0 },
1077  { 178, 2, 214, 2, 4785, 0 },
1078  { 263, 2, 214, 2, 4785, 0 },
1079  { 351, 2, 214, 2, 4785, 0 },
1080  { 436, 2, 214, 2, 4785, 0 },
1081  { 524, 2, 214, 2, 4785, 0 },
1082  { 599, 2, 214, 2, 4785, 0 },
1083  { 677, 2, 214, 2, 4785, 0 },
1084  { 744, 2, 214, 2, 4785, 0 },
1085  { 803, 2, 214, 2, 4785, 0 },
1086  { 0, 2, 214, 2, 4785, 0 },
1087  { 103, 2, 214, 2, 4785, 0 },
1088  { 209, 2, 214, 2, 4785, 0 },
1089  { 294, 2, 214, 2, 4785, 0 },
1090  { 382, 2, 214, 2, 4785, 0 },
1091  { 467, 2, 214, 2, 4785, 0 },
1092  { 555, 2, 214, 2, 4785, 0 },
1093  { 630, 2, 214, 2, 4785, 0 },
1094  { 708, 2, 214, 2, 4785, 0 },
1095  { 767, 2, 214, 2, 4785, 0 },
1096  { 28, 2, 214, 2, 4785, 0 },
1097  { 131, 2, 214, 2, 4785, 0 },
1098  { 237, 2, 214, 2, 4785, 0 },
1099  { 322, 2, 214, 2, 4785, 0 },
1100  { 410, 2, 214, 2, 4785, 0 },
1101  { 495, 2, 214, 2, 4785, 0 },
1102  { 573, 2, 214, 2, 4785, 0 },
1103  { 648, 2, 214, 2, 4785, 0 },
1104  { 726, 2, 214, 2, 4785, 0 },
1105  { 785, 2, 214, 2, 4785, 0 },
1106  { 46, 2, 214, 2, 4785, 0 },
1107  { 149, 2, 214, 2, 4785, 0 },
1108  { 77, 281, 215, 26, 4449, 22 },
1109  { 183, 281, 215, 26, 4449, 22 },
1110  { 268, 281, 215, 26, 4449, 22 },
1111  { 356, 281, 215, 26, 4449, 22 },
1112  { 441, 281, 215, 26, 4449, 22 },
1113  { 529, 281, 215, 26, 4449, 22 },
1114  { 604, 281, 215, 26, 4449, 22 },
1115  { 682, 281, 215, 26, 4449, 22 },
1116  { 749, 281, 215, 26, 4449, 22 },
1117  { 808, 281, 215, 26, 4449, 22 },
1118  { 6, 281, 215, 26, 4449, 22 },
1119  { 109, 281, 215, 26, 4449, 22 },
1120  { 215, 281, 215, 26, 4449, 22 },
1121  { 300, 281, 215, 26, 4449, 22 },
1122  { 388, 281, 215, 26, 4449, 22 },
1123  { 473, 281, 215, 26, 4449, 22 },
1124  { 561, 281, 215, 26, 4449, 22 },
1125  { 636, 281, 215, 26, 4449, 22 },
1126  { 714, 281, 215, 26, 4449, 22 },
1127  { 773, 281, 215, 26, 4449, 22 },
1128  { 34, 281, 215, 26, 4449, 22 },
1129  { 137, 281, 215, 26, 4449, 22 },
1130  { 243, 281, 215, 26, 4449, 22 },
1131  { 328, 281, 215, 26, 4449, 22 },
1132  { 416, 281, 215, 26, 4449, 22 },
1133  { 501, 281, 215, 26, 4449, 22 },
1134  { 579, 281, 215, 26, 4449, 22 },
1135  { 654, 281, 215, 26, 4449, 22 },
1136  { 732, 281, 215, 26, 4449, 22 },
1137  { 791, 281, 215, 26, 4449, 22 },
1138  { 52, 281, 215, 26, 4449, 22 },
1139  { 155, 281, 215, 26, 4449, 22 },
1140  { 82, 280, 2, 25, 4417, 22 },
1141  { 188, 280, 2, 25, 4417, 22 },
1142  { 273, 280, 2, 25, 4417, 22 },
1143  { 361, 280, 2, 25, 4417, 22 },
1144  { 446, 280, 2, 25, 4417, 22 },
1145  { 534, 280, 2, 25, 4417, 22 },
1146  { 609, 280, 2, 25, 4417, 22 },
1147  { 687, 280, 2, 25, 4417, 22 },
1148  { 754, 280, 2, 25, 4417, 22 },
1149  { 813, 280, 2, 25, 4417, 22 },
1150  { 12, 280, 2, 25, 4417, 22 },
1151  { 115, 280, 2, 25, 4417, 22 },
1152  { 221, 280, 2, 25, 4417, 22 },
1153  { 306, 280, 2, 25, 4417, 22 },
1154  { 394, 280, 2, 25, 4417, 22 },
1155  { 479, 280, 2, 25, 4417, 22 },
1156  { 567, 280, 2, 25, 4417, 22 },
1157  { 642, 280, 2, 25, 4417, 22 },
1158  { 720, 280, 2, 25, 4417, 22 },
1159  { 779, 280, 2, 25, 4417, 22 },
1160  { 40, 280, 2, 25, 4417, 22 },
1161  { 143, 280, 2, 25, 4417, 22 },
1162  { 249, 280, 2, 25, 4417, 22 },
1163  { 334, 280, 2, 25, 4417, 22 },
1164  { 422, 280, 2, 25, 4417, 22 },
1165  { 507, 280, 2, 25, 4417, 22 },
1166  { 585, 280, 2, 25, 4417, 22 },
1167  { 660, 280, 2, 25, 4417, 22 },
1168  { 738, 280, 2, 25, 4417, 22 },
1169  { 797, 280, 2, 25, 4417, 22 },
1170  { 58, 280, 2, 25, 4417, 22 },
1171  { 161, 280, 2, 25, 4417, 22 },
1172  { 856, 2, 268, 2, 4147, 0 },
1173  { 860, 2, 268, 2, 4147, 0 },
1174  { 826, 2, 268, 2, 4147, 0 },
1175  { 831, 2, 268, 2, 4147, 0 },
1176  { 836, 2, 268, 2, 4147, 0 },
1177  { 841, 2, 268, 2, 4147, 0 },
1178  { 846, 2, 268, 2, 4147, 0 },
1179  { 851, 2, 268, 2, 4147, 0 },
1180  { 967, 2, 264, 2, 4115, 0 },
1181  { 972, 2, 264, 2, 4115, 0 },
1182  { 931, 2, 264, 2, 4115, 0 },
1183  { 937, 2, 264, 2, 4115, 0 },
1184  { 943, 2, 264, 2, 4115, 0 },
1185  { 949, 2, 264, 2, 4115, 0 },
1186  { 955, 2, 264, 2, 4115, 0 },
1187  { 961, 2, 264, 2, 4115, 0 },
1188  { 894, 119, 262, 13, 51, 12 },
1189  { 898, 119, 262, 13, 51, 12 },
1190  { 864, 119, 262, 13, 51, 12 },
1191  { 869, 119, 262, 13, 51, 12 },
1192  { 874, 119, 262, 13, 51, 12 },
1193  { 879, 119, 262, 13, 51, 12 },
1194  { 884, 119, 262, 13, 51, 12 },
1195  { 889, 119, 262, 13, 51, 12 },
1196  { 1203, 77, 265, 3, 643, 5 },
1197  { 1207, 77, 265, 3, 643, 5 },
1198  { 1173, 77, 265, 3, 643, 5 },
1199  { 1178, 77, 265, 3, 643, 5 },
1200  { 1183, 77, 265, 3, 643, 5 },
1201  { 1188, 77, 265, 3, 643, 5 },
1202  { 1193, 77, 265, 3, 643, 5 },
1203  { 1198, 77, 265, 3, 643, 5 },
1204  { 1035, 2, 261, 2, 4083, 0 },
1205  { 1040, 2, 261, 2, 4083, 0 },
1206  { 999, 2, 261, 2, 4083, 0 },
1207  { 1005, 2, 261, 2, 4083, 0 },
1208  { 1011, 2, 261, 2, 4083, 0 },
1209  { 1017, 2, 261, 2, 4083, 0 },
1210  { 1023, 2, 261, 2, 4083, 0 },
1211  { 1029, 2, 261, 2, 4083, 0 },
1212  { 167, 46, 2, 22, 690, 19 },
1213  { 340, 49, 2, 22, 690, 19 },
1214  { 513, 52, 2, 22, 690, 19 },
1215  { 666, 55, 2, 22, 690, 19 },
1216};
1217
1218extern const MCPhysReg X86RegUnitRoots[][2] = {
1219  { X86::AH },
1220  { X86::AL },
1221  { X86::BH },
1222  { X86::BL },
1223  { X86::BPL },
1224  { X86::BPH },
1225  { X86::CH },
1226  { X86::CL },
1227  { X86::CS },
1228  { X86::DF },
1229  { X86::DH },
1230  { X86::DIL },
1231  { X86::DIH },
1232  { X86::DL },
1233  { X86::DS },
1234  { X86::HAX },
1235  { X86::HBP },
1236  { X86::HBX },
1237  { X86::HCX },
1238  { X86::HDI },
1239  { X86::HDX },
1240  { X86::EFLAGS },
1241  { X86::IP },
1242  { X86::HIP },
1243  { X86::EIZ },
1244  { X86::ES },
1245  { X86::SIL },
1246  { X86::SIH },
1247  { X86::HSI },
1248  { X86::SPL },
1249  { X86::SPH },
1250  { X86::HSP },
1251  { X86::FPCW },
1252  { X86::FPSW },
1253  { X86::FS },
1254  { X86::FS_BASE },
1255  { X86::GS },
1256  { X86::GS_BASE },
1257  { X86::MXCSR },
1258  { X86::RFLAGS },
1259  { X86::RIZ },
1260  { X86::SS },
1261  { X86::SSP },
1262  { X86::TMMCFG },
1263  { X86::_EFLAGS },
1264  { X86::CR0 },
1265  { X86::CR1 },
1266  { X86::CR2 },
1267  { X86::CR3 },
1268  { X86::CR4 },
1269  { X86::CR5 },
1270  { X86::CR6 },
1271  { X86::CR7 },
1272  { X86::CR8 },
1273  { X86::CR9 },
1274  { X86::CR10 },
1275  { X86::CR11 },
1276  { X86::CR12 },
1277  { X86::CR13 },
1278  { X86::CR14 },
1279  { X86::CR15 },
1280  { X86::DR0 },
1281  { X86::DR1 },
1282  { X86::DR2 },
1283  { X86::DR3 },
1284  { X86::DR4 },
1285  { X86::DR5 },
1286  { X86::DR6 },
1287  { X86::DR7 },
1288  { X86::DR8 },
1289  { X86::DR9 },
1290  { X86::DR10 },
1291  { X86::DR11 },
1292  { X86::DR12 },
1293  { X86::DR13 },
1294  { X86::DR14 },
1295  { X86::DR15 },
1296  { X86::FP0 },
1297  { X86::FP1 },
1298  { X86::FP2 },
1299  { X86::FP3 },
1300  { X86::FP4 },
1301  { X86::FP5 },
1302  { X86::FP6 },
1303  { X86::FP7 },
1304  { X86::K0 },
1305  { X86::K1 },
1306  { X86::K2 },
1307  { X86::K3 },
1308  { X86::K4 },
1309  { X86::K5 },
1310  { X86::K6 },
1311  { X86::K7 },
1312  { X86::MM0 },
1313  { X86::MM1 },
1314  { X86::MM2 },
1315  { X86::MM3 },
1316  { X86::MM4 },
1317  { X86::MM5 },
1318  { X86::MM6 },
1319  { X86::MM7 },
1320  { X86::R8B },
1321  { X86::R8BH },
1322  { X86::R8WH },
1323  { X86::R9B },
1324  { X86::R9BH },
1325  { X86::R9WH },
1326  { X86::R10B },
1327  { X86::R10BH },
1328  { X86::R10WH },
1329  { X86::R11B },
1330  { X86::R11BH },
1331  { X86::R11WH },
1332  { X86::R12B },
1333  { X86::R12BH },
1334  { X86::R12WH },
1335  { X86::R13B },
1336  { X86::R13BH },
1337  { X86::R13WH },
1338  { X86::R14B },
1339  { X86::R14BH },
1340  { X86::R14WH },
1341  { X86::R15B },
1342  { X86::R15BH },
1343  { X86::R15WH },
1344  { X86::ST0 },
1345  { X86::ST1 },
1346  { X86::ST2 },
1347  { X86::ST3 },
1348  { X86::ST4 },
1349  { X86::ST5 },
1350  { X86::ST6 },
1351  { X86::ST7 },
1352  { X86::TMM0 },
1353  { X86::TMM1 },
1354  { X86::TMM2 },
1355  { X86::TMM3 },
1356  { X86::TMM4 },
1357  { X86::TMM5 },
1358  { X86::TMM6 },
1359  { X86::TMM7 },
1360  { X86::XMM0 },
1361  { X86::XMM1 },
1362  { X86::XMM2 },
1363  { X86::XMM3 },
1364  { X86::XMM4 },
1365  { X86::XMM5 },
1366  { X86::XMM6 },
1367  { X86::XMM7 },
1368  { X86::XMM8 },
1369  { X86::XMM9 },
1370  { X86::XMM10 },
1371  { X86::XMM11 },
1372  { X86::XMM12 },
1373  { X86::XMM13 },
1374  { X86::XMM14 },
1375  { X86::XMM15 },
1376  { X86::XMM16 },
1377  { X86::XMM17 },
1378  { X86::XMM18 },
1379  { X86::XMM19 },
1380  { X86::XMM20 },
1381  { X86::XMM21 },
1382  { X86::XMM22 },
1383  { X86::XMM23 },
1384  { X86::XMM24 },
1385  { X86::XMM25 },
1386  { X86::XMM26 },
1387  { X86::XMM27 },
1388  { X86::XMM28 },
1389  { X86::XMM29 },
1390  { X86::XMM30 },
1391  { X86::XMM31 },
1392};
1393
1394namespace {     // Register classes...
1395  // GR8 Register Class...
1396  const MCPhysReg GR8[] = {
1397    X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B,
1398  };
1399
1400  // GR8 Bit set.
1401  const uint8_t GR8Bits[] = {
1402    0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1403  };
1404
1405  // GRH8 Register Class...
1406  const MCPhysReg GRH8[] = {
1407    X86::SIH, X86::DIH, X86::BPH, X86::SPH, X86::R8BH, X86::R9BH, X86::R10BH, X86::R11BH, X86::R12BH, X86::R13BH, X86::R14BH, X86::R15BH,
1408  };
1409
1410  // GRH8 Bit set.
1411  const uint8_t GRH8Bits[] = {
1412    0x80, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x80, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1413  };
1414
1415  // GR8_NOREX Register Class...
1416  const MCPhysReg GR8_NOREX[] = {
1417    X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH,
1418  };
1419
1420  // GR8_NOREX Bit set.
1421  const uint8_t GR8_NOREXBits[] = {
1422    0x36, 0x8c, 0x08,
1423  };
1424
1425  // GR8_ABCD_H Register Class...
1426  const MCPhysReg GR8_ABCD_H[] = {
1427    X86::AH, X86::CH, X86::DH, X86::BH,
1428  };
1429
1430  // GR8_ABCD_H Bit set.
1431  const uint8_t GR8_ABCD_HBits[] = {
1432    0x12, 0x84,
1433  };
1434
1435  // GR8_ABCD_L Register Class...
1436  const MCPhysReg GR8_ABCD_L[] = {
1437    X86::AL, X86::CL, X86::DL, X86::BL,
1438  };
1439
1440  // GR8_ABCD_L Bit set.
1441  const uint8_t GR8_ABCD_LBits[] = {
1442    0x24, 0x08, 0x08,
1443  };
1444
1445  // GRH16 Register Class...
1446  const MCPhysReg GRH16[] = {
1447    X86::HAX, X86::HCX, X86::HDX, X86::HSI, X86::HDI, X86::HBX, X86::HBP, X86::HSP, X86::HIP, X86::R8WH, X86::R9WH, X86::R10WH, X86::R11WH, X86::R12WH, X86::R13WH, X86::R14WH, X86::R15WH,
1448  };
1449
1450  // GRH16 Bit set.
1451  const uint8_t GRH16Bits[] = {
1452    0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1453  };
1454
1455  // GR16 Register Class...
1456  const MCPhysReg GR16[] = {
1457    X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R14W, X86::R15W, X86::R12W, X86::R13W,
1458  };
1459
1460  // GR16 Bit set.
1461  const uint8_t GR16Bits[] = {
1462    0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1463  };
1464
1465  // GR16_NOREX Register Class...
1466  const MCPhysReg GR16_NOREX[] = {
1467    X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP,
1468  };
1469
1470  // GR16_NOREX Bit set.
1471  const uint8_t GR16_NOREXBits[] = {
1472    0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02,
1473  };
1474
1475  // VK1 Register Class...
1476  const MCPhysReg VK1[] = {
1477    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1478  };
1479
1480  // VK1 Bit set.
1481  const uint8_t VK1Bits[] = {
1482    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1483  };
1484
1485  // VK16 Register Class...
1486  const MCPhysReg VK16[] = {
1487    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1488  };
1489
1490  // VK16 Bit set.
1491  const uint8_t VK16Bits[] = {
1492    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1493  };
1494
1495  // VK2 Register Class...
1496  const MCPhysReg VK2[] = {
1497    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1498  };
1499
1500  // VK2 Bit set.
1501  const uint8_t VK2Bits[] = {
1502    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1503  };
1504
1505  // VK4 Register Class...
1506  const MCPhysReg VK4[] = {
1507    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1508  };
1509
1510  // VK4 Bit set.
1511  const uint8_t VK4Bits[] = {
1512    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1513  };
1514
1515  // VK8 Register Class...
1516  const MCPhysReg VK8[] = {
1517    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1518  };
1519
1520  // VK8 Bit set.
1521  const uint8_t VK8Bits[] = {
1522    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1523  };
1524
1525  // VK16WM Register Class...
1526  const MCPhysReg VK16WM[] = {
1527    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1528  };
1529
1530  // VK16WM Bit set.
1531  const uint8_t VK16WMBits[] = {
1532    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
1533  };
1534
1535  // VK1WM Register Class...
1536  const MCPhysReg VK1WM[] = {
1537    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1538  };
1539
1540  // VK1WM Bit set.
1541  const uint8_t VK1WMBits[] = {
1542    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
1543  };
1544
1545  // VK2WM Register Class...
1546  const MCPhysReg VK2WM[] = {
1547    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1548  };
1549
1550  // VK2WM Bit set.
1551  const uint8_t VK2WMBits[] = {
1552    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
1553  };
1554
1555  // VK4WM Register Class...
1556  const MCPhysReg VK4WM[] = {
1557    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1558  };
1559
1560  // VK4WM Bit set.
1561  const uint8_t VK4WMBits[] = {
1562    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
1563  };
1564
1565  // VK8WM Register Class...
1566  const MCPhysReg VK8WM[] = {
1567    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1568  };
1569
1570  // VK8WM Bit set.
1571  const uint8_t VK8WMBits[] = {
1572    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
1573  };
1574
1575  // SEGMENT_REG Register Class...
1576  const MCPhysReg SEGMENT_REG[] = {
1577    X86::CS, X86::DS, X86::SS, X86::ES, X86::FS, X86::GS,
1578  };
1579
1580  // SEGMENT_REG Bit set.
1581  const uint8_t SEGMENT_REGBits[] = {
1582    0x00, 0x10, 0x10, 0x80, 0x50, 0x00, 0x00, 0x00, 0x10,
1583  };
1584
1585  // GR16_ABCD Register Class...
1586  const MCPhysReg GR16_ABCD[] = {
1587    X86::AX, X86::CX, X86::DX, X86::BX,
1588  };
1589
1590  // GR16_ABCD Bit set.
1591  const uint8_t GR16_ABCDBits[] = {
1592    0x08, 0x22, 0x20,
1593  };
1594
1595  // FPCCR Register Class...
1596  const MCPhysReg FPCCR[] = {
1597    X86::FPSW,
1598  };
1599
1600  // FPCCR Bit set.
1601  const uint8_t FPCCRBits[] = {
1602    0x00, 0x00, 0x00, 0x00, 0x08,
1603  };
1604
1605  // FR16X Register Class...
1606  const MCPhysReg FR16X[] = {
1607    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
1608  };
1609
1610  // FR16X Bit set.
1611  const uint8_t FR16XBits[] = {
1612    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
1613  };
1614
1615  // FR16 Register Class...
1616  const MCPhysReg FR16[] = {
1617    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
1618  };
1619
1620  // FR16 Bit set.
1621  const uint8_t FR16Bits[] = {
1622    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
1623  };
1624
1625  // VK16PAIR Register Class...
1626  const MCPhysReg VK16PAIR[] = {
1627    X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1628  };
1629
1630  // VK16PAIR Bit set.
1631  const uint8_t VK16PAIRBits[] = {
1632    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
1633  };
1634
1635  // VK1PAIR Register Class...
1636  const MCPhysReg VK1PAIR[] = {
1637    X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1638  };
1639
1640  // VK1PAIR Bit set.
1641  const uint8_t VK1PAIRBits[] = {
1642    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
1643  };
1644
1645  // VK2PAIR Register Class...
1646  const MCPhysReg VK2PAIR[] = {
1647    X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1648  };
1649
1650  // VK2PAIR Bit set.
1651  const uint8_t VK2PAIRBits[] = {
1652    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
1653  };
1654
1655  // VK4PAIR Register Class...
1656  const MCPhysReg VK4PAIR[] = {
1657    X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1658  };
1659
1660  // VK4PAIR Bit set.
1661  const uint8_t VK4PAIRBits[] = {
1662    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
1663  };
1664
1665  // VK8PAIR Register Class...
1666  const MCPhysReg VK8PAIR[] = {
1667    X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1668  };
1669
1670  // VK8PAIR Bit set.
1671  const uint8_t VK8PAIRBits[] = {
1672    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
1673  };
1674
1675  // VK16PAIR_with_sub_mask_0_in_VK16WM Register Class...
1676  const MCPhysReg VK16PAIR_with_sub_mask_0_in_VK16WM[] = {
1677    X86::K2_K3, X86::K4_K5, X86::K6_K7,
1678  };
1679
1680  // VK16PAIR_with_sub_mask_0_in_VK16WM Bit set.
1681  const uint8_t VK16PAIR_with_sub_mask_0_in_VK16WMBits[] = {
1682    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e,
1683  };
1684
1685  // FR32X Register Class...
1686  const MCPhysReg FR32X[] = {
1687    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
1688  };
1689
1690  // FR32X Bit set.
1691  const uint8_t FR32XBits[] = {
1692    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
1693  };
1694
1695  // LOW32_ADDR_ACCESS_RBP Register Class...
1696  const MCPhysReg LOW32_ADDR_ACCESS_RBP[] = {
1697    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP, X86::RBP,
1698  };
1699
1700  // LOW32_ADDR_ACCESS_RBP Bit set.
1701  const uint8_t LOW32_ADDR_ACCESS_RBPBits[] = {
1702    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1703  };
1704
1705  // LOW32_ADDR_ACCESS Register Class...
1706  const MCPhysReg LOW32_ADDR_ACCESS[] = {
1707    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP,
1708  };
1709
1710  // LOW32_ADDR_ACCESS Bit set.
1711  const uint8_t LOW32_ADDR_ACCESSBits[] = {
1712    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1713  };
1714
1715  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Register Class...
1716  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit[] = {
1717    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RBP,
1718  };
1719
1720  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Bit set.
1721  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits[] = {
1722    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1723  };
1724
1725  // DEBUG_REG Register Class...
1726  const MCPhysReg DEBUG_REG[] = {
1727    X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7, X86::DR8, X86::DR9, X86::DR10, X86::DR11, X86::DR12, X86::DR13, X86::DR14, X86::DR15,
1728  };
1729
1730  // DEBUG_REG Bit set.
1731  const uint8_t DEBUG_REGBits[] = {
1732    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
1733  };
1734
1735  // FR32 Register Class...
1736  const MCPhysReg FR32[] = {
1737    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
1738  };
1739
1740  // FR32 Bit set.
1741  const uint8_t FR32Bits[] = {
1742    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
1743  };
1744
1745  // GR32 Register Class...
1746  const MCPhysReg GR32[] = {
1747    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
1748  };
1749
1750  // GR32 Bit set.
1751  const uint8_t GR32Bits[] = {
1752    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1753  };
1754
1755  // GR32_NOSP Register Class...
1756  const MCPhysReg GR32_NOSP[] = {
1757    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
1758  };
1759
1760  // GR32_NOSP Bit set.
1761  const uint8_t GR32_NOSPBits[] = {
1762    0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1763  };
1764
1765  // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Register Class...
1766  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX[] = {
1767    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::RBP,
1768  };
1769
1770  // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Bit set.
1771  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits[] = {
1772    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10,
1773  };
1774
1775  // GR32_NOREX Register Class...
1776  const MCPhysReg GR32_NOREX[] = {
1777    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP,
1778  };
1779
1780  // GR32_NOREX Bit set.
1781  const uint8_t GR32_NOREXBits[] = {
1782    0x00, 0x00, 0xc0, 0x0f, 0x03,
1783  };
1784
1785  // VK32 Register Class...
1786  const MCPhysReg VK32[] = {
1787    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1788  };
1789
1790  // VK32 Bit set.
1791  const uint8_t VK32Bits[] = {
1792    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1793  };
1794
1795  // GR32_NOREX_NOSP Register Class...
1796  const MCPhysReg GR32_NOREX_NOSP[] = {
1797    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP,
1798  };
1799
1800  // GR32_NOREX_NOSP Bit set.
1801  const uint8_t GR32_NOREX_NOSPBits[] = {
1802    0x00, 0x00, 0xc0, 0x0f, 0x01,
1803  };
1804
1805  // RFP32 Register Class...
1806  const MCPhysReg RFP32[] = {
1807    X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
1808  };
1809
1810  // RFP32 Bit set.
1811  const uint8_t RFP32Bits[] = {
1812    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1813  };
1814
1815  // VK32WM Register Class...
1816  const MCPhysReg VK32WM[] = {
1817    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1818  };
1819
1820  // VK32WM Bit set.
1821  const uint8_t VK32WMBits[] = {
1822    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
1823  };
1824
1825  // GR32_ABCD Register Class...
1826  const MCPhysReg GR32_ABCD[] = {
1827    X86::EAX, X86::ECX, X86::EDX, X86::EBX,
1828  };
1829
1830  // GR32_ABCD Bit set.
1831  const uint8_t GR32_ABCDBits[] = {
1832    0x00, 0x00, 0x40, 0x0b,
1833  };
1834
1835  // GR32_TC Register Class...
1836  const MCPhysReg GR32_TC[] = {
1837    X86::EAX, X86::ECX, X86::EDX, X86::ESP,
1838  };
1839
1840  // GR32_TC Bit set.
1841  const uint8_t GR32_TCBits[] = {
1842    0x00, 0x00, 0x40, 0x0a, 0x02,
1843  };
1844
1845  // GR32_ABCD_and_GR32_TC Register Class...
1846  const MCPhysReg GR32_ABCD_and_GR32_TC[] = {
1847    X86::EAX, X86::ECX, X86::EDX,
1848  };
1849
1850  // GR32_ABCD_and_GR32_TC Bit set.
1851  const uint8_t GR32_ABCD_and_GR32_TCBits[] = {
1852    0x00, 0x00, 0x40, 0x0a,
1853  };
1854
1855  // GR32_AD Register Class...
1856  const MCPhysReg GR32_AD[] = {
1857    X86::EAX, X86::EDX,
1858  };
1859
1860  // GR32_AD Bit set.
1861  const uint8_t GR32_ADBits[] = {
1862    0x00, 0x00, 0x40, 0x08,
1863  };
1864
1865  // GR32_BPSP Register Class...
1866  const MCPhysReg GR32_BPSP[] = {
1867    X86::EBP, X86::ESP,
1868  };
1869
1870  // GR32_BPSP Bit set.
1871  const uint8_t GR32_BPSPBits[] = {
1872    0x00, 0x00, 0x80, 0x00, 0x02,
1873  };
1874
1875  // GR32_BSI Register Class...
1876  const MCPhysReg GR32_BSI[] = {
1877    X86::EBX, X86::ESI,
1878  };
1879
1880  // GR32_BSI Bit set.
1881  const uint8_t GR32_BSIBits[] = {
1882    0x00, 0x00, 0x00, 0x01, 0x01,
1883  };
1884
1885  // GR32_CB Register Class...
1886  const MCPhysReg GR32_CB[] = {
1887    X86::ECX, X86::EBX,
1888  };
1889
1890  // GR32_CB Bit set.
1891  const uint8_t GR32_CBBits[] = {
1892    0x00, 0x00, 0x00, 0x03,
1893  };
1894
1895  // GR32_DC Register Class...
1896  const MCPhysReg GR32_DC[] = {
1897    X86::EDX, X86::ECX,
1898  };
1899
1900  // GR32_DC Bit set.
1901  const uint8_t GR32_DCBits[] = {
1902    0x00, 0x00, 0x00, 0x0a,
1903  };
1904
1905  // GR32_DIBP Register Class...
1906  const MCPhysReg GR32_DIBP[] = {
1907    X86::EDI, X86::EBP,
1908  };
1909
1910  // GR32_DIBP Bit set.
1911  const uint8_t GR32_DIBPBits[] = {
1912    0x00, 0x00, 0x80, 0x04,
1913  };
1914
1915  // GR32_SIDI Register Class...
1916  const MCPhysReg GR32_SIDI[] = {
1917    X86::ESI, X86::EDI,
1918  };
1919
1920  // GR32_SIDI Bit set.
1921  const uint8_t GR32_SIDIBits[] = {
1922    0x00, 0x00, 0x00, 0x04, 0x01,
1923  };
1924
1925  // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Register Class...
1926  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_32bit[] = {
1927    X86::RIP, X86::RBP,
1928  };
1929
1930  // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Bit set.
1931  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits[] = {
1932    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x04,
1933  };
1934
1935  // CCR Register Class...
1936  const MCPhysReg CCR[] = {
1937    X86::EFLAGS,
1938  };
1939
1940  // CCR Bit set.
1941  const uint8_t CCRBits[] = {
1942    0x00, 0x00, 0x00, 0x10,
1943  };
1944
1945  // DFCCR Register Class...
1946  const MCPhysReg DFCCR[] = {
1947    X86::DF,
1948  };
1949
1950  // DFCCR Bit set.
1951  const uint8_t DFCCRBits[] = {
1952    0x00, 0x40,
1953  };
1954
1955  // GR32_ABCD_and_GR32_BSI Register Class...
1956  const MCPhysReg GR32_ABCD_and_GR32_BSI[] = {
1957    X86::EBX,
1958  };
1959
1960  // GR32_ABCD_and_GR32_BSI Bit set.
1961  const uint8_t GR32_ABCD_and_GR32_BSIBits[] = {
1962    0x00, 0x00, 0x00, 0x01,
1963  };
1964
1965  // GR32_AD_and_GR32_DC Register Class...
1966  const MCPhysReg GR32_AD_and_GR32_DC[] = {
1967    X86::EDX,
1968  };
1969
1970  // GR32_AD_and_GR32_DC Bit set.
1971  const uint8_t GR32_AD_and_GR32_DCBits[] = {
1972    0x00, 0x00, 0x00, 0x08,
1973  };
1974
1975  // GR32_BPSP_and_GR32_DIBP Register Class...
1976  const MCPhysReg GR32_BPSP_and_GR32_DIBP[] = {
1977    X86::EBP,
1978  };
1979
1980  // GR32_BPSP_and_GR32_DIBP Bit set.
1981  const uint8_t GR32_BPSP_and_GR32_DIBPBits[] = {
1982    0x00, 0x00, 0x80,
1983  };
1984
1985  // GR32_BPSP_and_GR32_TC Register Class...
1986  const MCPhysReg GR32_BPSP_and_GR32_TC[] = {
1987    X86::ESP,
1988  };
1989
1990  // GR32_BPSP_and_GR32_TC Bit set.
1991  const uint8_t GR32_BPSP_and_GR32_TCBits[] = {
1992    0x00, 0x00, 0x00, 0x00, 0x02,
1993  };
1994
1995  // GR32_BSI_and_GR32_SIDI Register Class...
1996  const MCPhysReg GR32_BSI_and_GR32_SIDI[] = {
1997    X86::ESI,
1998  };
1999
2000  // GR32_BSI_and_GR32_SIDI Bit set.
2001  const uint8_t GR32_BSI_and_GR32_SIDIBits[] = {
2002    0x00, 0x00, 0x00, 0x00, 0x01,
2003  };
2004
2005  // GR32_CB_and_GR32_DC Register Class...
2006  const MCPhysReg GR32_CB_and_GR32_DC[] = {
2007    X86::ECX,
2008  };
2009
2010  // GR32_CB_and_GR32_DC Bit set.
2011  const uint8_t GR32_CB_and_GR32_DCBits[] = {
2012    0x00, 0x00, 0x00, 0x02,
2013  };
2014
2015  // GR32_DIBP_and_GR32_SIDI Register Class...
2016  const MCPhysReg GR32_DIBP_and_GR32_SIDI[] = {
2017    X86::EDI,
2018  };
2019
2020  // GR32_DIBP_and_GR32_SIDI Bit set.
2021  const uint8_t GR32_DIBP_and_GR32_SIDIBits[] = {
2022    0x00, 0x00, 0x00, 0x04,
2023  };
2024
2025  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Register Class...
2026  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit[] = {
2027    X86::RBP,
2028  };
2029
2030  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Bit set.
2031  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits[] = {
2032    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2033  };
2034
2035  // LOW32_ADDR_ACCESS_with_sub_32bit Register Class...
2036  const MCPhysReg LOW32_ADDR_ACCESS_with_sub_32bit[] = {
2037    X86::RIP,
2038  };
2039
2040  // LOW32_ADDR_ACCESS_with_sub_32bit Bit set.
2041  const uint8_t LOW32_ADDR_ACCESS_with_sub_32bitBits[] = {
2042    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2043  };
2044
2045  // RFP64 Register Class...
2046  const MCPhysReg RFP64[] = {
2047    X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
2048  };
2049
2050  // RFP64 Bit set.
2051  const uint8_t RFP64Bits[] = {
2052    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
2053  };
2054
2055  // FR64X Register Class...
2056  const MCPhysReg FR64X[] = {
2057    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
2058  };
2059
2060  // FR64X Bit set.
2061  const uint8_t FR64XBits[] = {
2062    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
2063  };
2064
2065  // GR64 Register Class...
2066  const MCPhysReg GR64[] = {
2067    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP,
2068  };
2069
2070  // GR64 Bit set.
2071  const uint8_t GR64Bits[] = {
2072    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
2073  };
2074
2075  // CONTROL_REG Register Class...
2076  const MCPhysReg CONTROL_REG[] = {
2077    X86::CR0, X86::CR1, X86::CR2, X86::CR3, X86::CR4, X86::CR5, X86::CR6, X86::CR7, X86::CR8, X86::CR9, X86::CR10, X86::CR11, X86::CR12, X86::CR13, X86::CR14, X86::CR15,
2078  };
2079
2080  // CONTROL_REG Bit set.
2081  const uint8_t CONTROL_REGBits[] = {
2082    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
2083  };
2084
2085  // FR64 Register Class...
2086  const MCPhysReg FR64[] = {
2087    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
2088  };
2089
2090  // FR64 Bit set.
2091  const uint8_t FR64Bits[] = {
2092    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
2093  };
2094
2095  // GR64_with_sub_8bit Register Class...
2096  const MCPhysReg GR64_with_sub_8bit[] = {
2097    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP,
2098  };
2099
2100  // GR64_with_sub_8bit Bit set.
2101  const uint8_t GR64_with_sub_8bitBits[] = {
2102    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
2103  };
2104
2105  // GR64_NOSP Register Class...
2106  const MCPhysReg GR64_NOSP[] = {
2107    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
2108  };
2109
2110  // GR64_NOSP Bit set.
2111  const uint8_t GR64_NOSPBits[] = {
2112    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
2113  };
2114
2115  // GR64PLTSafe Register Class...
2116  const MCPhysReg GR64PLTSafe[] = {
2117    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
2118  };
2119
2120  // GR64PLTSafe Bit set.
2121  const uint8_t GR64PLTSafeBits[] = {
2122    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3,
2123  };
2124
2125  // GR64_TC Register Class...
2126  const MCPhysReg GR64_TC[] = {
2127    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
2128  };
2129
2130  // GR64_TC Bit set.
2131  const uint8_t GR64_TCBits[] = {
2132    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b,
2133  };
2134
2135  // GR64_NOREX Register Class...
2136  const MCPhysReg GR64_NOREX[] = {
2137    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP,
2138  };
2139
2140  // GR64_NOREX Bit set.
2141  const uint8_t GR64_NOREXBits[] = {
2142    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35,
2143  };
2144
2145  // GR64_TCW64 Register Class...
2146  const MCPhysReg GR64_TCW64[] = {
2147    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RIP, X86::RSP,
2148  };
2149
2150  // GR64_TCW64 Bit set.
2151  const uint8_t GR64_TCW64Bits[] = {
2152    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
2153  };
2154
2155  // GR64_TC_with_sub_8bit Register Class...
2156  const MCPhysReg GR64_TC_with_sub_8bit[] = {
2157    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RSP,
2158  };
2159
2160  // GR64_TC_with_sub_8bit Bit set.
2161  const uint8_t GR64_TC_with_sub_8bitBits[] = {
2162    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b,
2163  };
2164
2165  // GR64_NOSP_and_GR64_TC Register Class...
2166  const MCPhysReg GR64_NOSP_and_GR64_TC[] = {
2167    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11,
2168  };
2169
2170  // GR64_NOSP_and_GR64_TC Bit set.
2171  const uint8_t GR64_NOSP_and_GR64_TCBits[] = {
2172    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b,
2173  };
2174
2175  // GR64_TCW64_with_sub_8bit Register Class...
2176  const MCPhysReg GR64_TCW64_with_sub_8bit[] = {
2177    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RSP,
2178  };
2179
2180  // GR64_TCW64_with_sub_8bit Bit set.
2181  const uint8_t GR64_TCW64_with_sub_8bitBits[] = {
2182    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
2183  };
2184
2185  // GR64_TC_and_GR64_TCW64 Register Class...
2186  const MCPhysReg GR64_TC_and_GR64_TCW64[] = {
2187    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
2188  };
2189
2190  // GR64_TC_and_GR64_TCW64 Bit set.
2191  const uint8_t GR64_TC_and_GR64_TCW64Bits[] = {
2192    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b,
2193  };
2194
2195  // GR64_with_sub_16bit_in_GR16_NOREX Register Class...
2196  const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX[] = {
2197    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP,
2198  };
2199
2200  // GR64_with_sub_16bit_in_GR16_NOREX Bit set.
2201  const uint8_t GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
2202    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31,
2203  };
2204
2205  // VK64 Register Class...
2206  const MCPhysReg VK64[] = {
2207    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
2208  };
2209
2210  // VK64 Bit set.
2211  const uint8_t VK64Bits[] = {
2212    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
2213  };
2214
2215  // VR64 Register Class...
2216  const MCPhysReg VR64[] = {
2217    X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
2218  };
2219
2220  // VR64 Bit set.
2221  const uint8_t VR64Bits[] = {
2222    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
2223  };
2224
2225  // GR64PLTSafe_and_GR64_TC Register Class...
2226  const MCPhysReg GR64PLTSafe_and_GR64_TC[] = {
2227    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9,
2228  };
2229
2230  // GR64PLTSafe_and_GR64_TC Bit set.
2231  const uint8_t GR64PLTSafe_and_GR64_TCBits[] = {
2232    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
2233  };
2234
2235  // GR64_NOREX_NOSP Register Class...
2236  const MCPhysReg GR64_NOREX_NOSP[] = {
2237    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP,
2238  };
2239
2240  // GR64_NOREX_NOSP Bit set.
2241  const uint8_t GR64_NOREX_NOSPBits[] = {
2242    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11,
2243  };
2244
2245  // GR64_NOREX_and_GR64_TC Register Class...
2246  const MCPhysReg GR64_NOREX_and_GR64_TC[] = {
2247    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP, X86::RIP,
2248  };
2249
2250  // GR64_NOREX_and_GR64_TC Bit set.
2251  const uint8_t GR64_NOREX_and_GR64_TCBits[] = {
2252    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x35,
2253  };
2254
2255  // GR64_NOSP_and_GR64_TCW64 Register Class...
2256  const MCPhysReg GR64_NOSP_and_GR64_TCW64[] = {
2257    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11,
2258  };
2259
2260  // GR64_NOSP_and_GR64_TCW64 Bit set.
2261  const uint8_t GR64_NOSP_and_GR64_TCW64Bits[] = {
2262    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
2263  };
2264
2265  // GR64_TCW64_and_GR64_TC_with_sub_8bit Register Class...
2266  const MCPhysReg GR64_TCW64_and_GR64_TC_with_sub_8bit[] = {
2267    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RSP,
2268  };
2269
2270  // GR64_TCW64_and_GR64_TC_with_sub_8bit Bit set.
2271  const uint8_t GR64_TCW64_and_GR64_TC_with_sub_8bitBits[] = {
2272    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b,
2273  };
2274
2275  // VK64WM Register Class...
2276  const MCPhysReg VK64WM[] = {
2277    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
2278  };
2279
2280  // VK64WM Bit set.
2281  const uint8_t VK64WMBits[] = {
2282    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
2283  };
2284
2285  // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 Register Class...
2286  const MCPhysReg GR64_TC_and_GR64_NOSP_and_GR64_TCW64[] = {
2287    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11,
2288  };
2289
2290  // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 Bit set.
2291  const uint8_t GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits[] = {
2292    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b,
2293  };
2294
2295  // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX Register Class...
2296  const MCPhysReg GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX[] = {
2297    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP,
2298  };
2299
2300  // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX Bit set.
2301  const uint8_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
2302    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x31,
2303  };
2304
2305  // GR64PLTSafe_and_GR64_TCW64 Register Class...
2306  const MCPhysReg GR64PLTSafe_and_GR64_TCW64[] = {
2307    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9,
2308  };
2309
2310  // GR64PLTSafe_and_GR64_TCW64 Bit set.
2311  const uint8_t GR64PLTSafe_and_GR64_TCW64Bits[] = {
2312    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
2313  };
2314
2315  // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC Register Class...
2316  const MCPhysReg GR64_NOREX_and_GR64PLTSafe_and_GR64_TC[] = {
2317    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI,
2318  };
2319
2320  // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC Bit set.
2321  const uint8_t GR64_NOREX_and_GR64PLTSafe_and_GR64_TCBits[] = {
2322    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11,
2323  };
2324
2325  // GR64_NOREX_and_GR64_TCW64 Register Class...
2326  const MCPhysReg GR64_NOREX_and_GR64_TCW64[] = {
2327    X86::RAX, X86::RCX, X86::RDX, X86::RSP, X86::RIP,
2328  };
2329
2330  // GR64_NOREX_and_GR64_TCW64 Bit set.
2331  const uint8_t GR64_NOREX_and_GR64_TCW64Bits[] = {
2332    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25,
2333  };
2334
2335  // GR64_ABCD Register Class...
2336  const MCPhysReg GR64_ABCD[] = {
2337    X86::RAX, X86::RCX, X86::RDX, X86::RBX,
2338  };
2339
2340  // GR64_ABCD Bit set.
2341  const uint8_t GR64_ABCDBits[] = {
2342    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0x01,
2343  };
2344
2345  // GR64_with_sub_32bit_in_GR32_TC Register Class...
2346  const MCPhysReg GR64_with_sub_32bit_in_GR32_TC[] = {
2347    X86::RAX, X86::RCX, X86::RDX, X86::RSP,
2348  };
2349
2350  // GR64_with_sub_32bit_in_GR32_TC Bit set.
2351  const uint8_t GR64_with_sub_32bit_in_GR32_TCBits[] = {
2352    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21,
2353  };
2354
2355  // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC Register Class...
2356  const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC[] = {
2357    X86::RAX, X86::RCX, X86::RDX,
2358  };
2359
2360  // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC Bit set.
2361  const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits[] = {
2362    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01,
2363  };
2364
2365  // GR64_AD Register Class...
2366  const MCPhysReg GR64_AD[] = {
2367    X86::RAX, X86::RDX,
2368  };
2369
2370  // GR64_AD Bit set.
2371  const uint8_t GR64_ADBits[] = {
2372    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01,
2373  };
2374
2375  // GR64_and_LOW32_ADDR_ACCESS_RBP Register Class...
2376  const MCPhysReg GR64_and_LOW32_ADDR_ACCESS_RBP[] = {
2377    X86::RBP, X86::RIP,
2378  };
2379
2380  // GR64_and_LOW32_ADDR_ACCESS_RBP Bit set.
2381  const uint8_t GR64_and_LOW32_ADDR_ACCESS_RBPBits[] = {
2382    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x04,
2383  };
2384
2385  // GR64_with_sub_32bit_in_GR32_BPSP Register Class...
2386  const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP[] = {
2387    X86::RBP, X86::RSP,
2388  };
2389
2390  // GR64_with_sub_32bit_in_GR32_BPSP Bit set.
2391  const uint8_t GR64_with_sub_32bit_in_GR32_BPSPBits[] = {
2392    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x20,
2393  };
2394
2395  // GR64_with_sub_32bit_in_GR32_BSI Register Class...
2396  const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI[] = {
2397    X86::RSI, X86::RBX,
2398  };
2399
2400  // GR64_with_sub_32bit_in_GR32_BSI Bit set.
2401  const uint8_t GR64_with_sub_32bit_in_GR32_BSIBits[] = {
2402    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x10,
2403  };
2404
2405  // GR64_with_sub_32bit_in_GR32_CB Register Class...
2406  const MCPhysReg GR64_with_sub_32bit_in_GR32_CB[] = {
2407    X86::RCX, X86::RBX,
2408  };
2409
2410  // GR64_with_sub_32bit_in_GR32_CB Bit set.
2411  const uint8_t GR64_with_sub_32bit_in_GR32_CBBits[] = {
2412    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
2413  };
2414
2415  // GR64_with_sub_32bit_in_GR32_DC Register Class...
2416  const MCPhysReg GR64_with_sub_32bit_in_GR32_DC[] = {
2417    X86::RCX, X86::RDX,
2418  };
2419
2420  // GR64_with_sub_32bit_in_GR32_DC Bit set.
2421  const uint8_t GR64_with_sub_32bit_in_GR32_DCBits[] = {
2422    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x01,
2423  };
2424
2425  // GR64_with_sub_32bit_in_GR32_DIBP Register Class...
2426  const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP[] = {
2427    X86::RDI, X86::RBP,
2428  };
2429
2430  // GR64_with_sub_32bit_in_GR32_DIBP Bit set.
2431  const uint8_t GR64_with_sub_32bit_in_GR32_DIBPBits[] = {
2432    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90,
2433  };
2434
2435  // GR64_with_sub_32bit_in_GR32_SIDI Register Class...
2436  const MCPhysReg GR64_with_sub_32bit_in_GR32_SIDI[] = {
2437    X86::RSI, X86::RDI,
2438  };
2439
2440  // GR64_with_sub_32bit_in_GR32_SIDI Bit set.
2441  const uint8_t GR64_with_sub_32bit_in_GR32_SIDIBits[] = {
2442    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x10,
2443  };
2444
2445  // GR64_and_LOW32_ADDR_ACCESS Register Class...
2446  const MCPhysReg GR64_and_LOW32_ADDR_ACCESS[] = {
2447    X86::RIP,
2448  };
2449
2450  // GR64_and_LOW32_ADDR_ACCESS Bit set.
2451  const uint8_t GR64_and_LOW32_ADDR_ACCESSBits[] = {
2452    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2453  };
2454
2455  // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Register Class...
2456  const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI[] = {
2457    X86::RBX,
2458  };
2459
2460  // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Bit set.
2461  const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits[] = {
2462    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2463  };
2464
2465  // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC Register Class...
2466  const MCPhysReg GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC[] = {
2467    X86::RDX,
2468  };
2469
2470  // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC Bit set.
2471  const uint8_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCBits[] = {
2472    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
2473  };
2474
2475  // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Register Class...
2476  const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP[] = {
2477    X86::RBP,
2478  };
2479
2480  // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Bit set.
2481  const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits[] = {
2482    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2483  };
2484
2485  // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC Register Class...
2486  const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC[] = {
2487    X86::RSP,
2488  };
2489
2490  // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC Bit set.
2491  const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits[] = {
2492    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2493  };
2494
2495  // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Register Class...
2496  const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI[] = {
2497    X86::RSI,
2498  };
2499
2500  // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Bit set.
2501  const uint8_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits[] = {
2502    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2503  };
2504
2505  // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC Register Class...
2506  const MCPhysReg GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC[] = {
2507    X86::RCX,
2508  };
2509
2510  // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC Bit set.
2511  const uint8_t GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCBits[] = {
2512    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
2513  };
2514
2515  // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Register Class...
2516  const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI[] = {
2517    X86::RDI,
2518  };
2519
2520  // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Bit set.
2521  const uint8_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits[] = {
2522    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
2523  };
2524
2525  // RST Register Class...
2526  const MCPhysReg RST[] = {
2527    X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7,
2528  };
2529
2530  // RST Bit set.
2531  const uint8_t RSTBits[] = {
2532    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
2533  };
2534
2535  // RFP80 Register Class...
2536  const MCPhysReg RFP80[] = {
2537    X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
2538  };
2539
2540  // RFP80 Bit set.
2541  const uint8_t RFP80Bits[] = {
2542    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
2543  };
2544
2545  // RFP80_7 Register Class...
2546  const MCPhysReg RFP80_7[] = {
2547    X86::FP7,
2548  };
2549
2550  // RFP80_7 Bit set.
2551  const uint8_t RFP80_7Bits[] = {
2552    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
2553  };
2554
2555  // VR128X Register Class...
2556  const MCPhysReg VR128X[] = {
2557    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
2558  };
2559
2560  // VR128X Bit set.
2561  const uint8_t VR128XBits[] = {
2562    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
2563  };
2564
2565  // VR128 Register Class...
2566  const MCPhysReg VR128[] = {
2567    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
2568  };
2569
2570  // VR128 Bit set.
2571  const uint8_t VR128Bits[] = {
2572    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
2573  };
2574
2575  // VR256X Register Class...
2576  const MCPhysReg VR256X[] = {
2577    X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM16, X86::YMM17, X86::YMM18, X86::YMM19, X86::YMM20, X86::YMM21, X86::YMM22, X86::YMM23, X86::YMM24, X86::YMM25, X86::YMM26, X86::YMM27, X86::YMM28, X86::YMM29, X86::YMM30, X86::YMM31,
2578  };
2579
2580  // VR256X Bit set.
2581  const uint8_t VR256XBits[] = {
2582    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
2583  };
2584
2585  // VR256 Register Class...
2586  const MCPhysReg VR256[] = {
2587    X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15,
2588  };
2589
2590  // VR256 Bit set.
2591  const uint8_t VR256Bits[] = {
2592    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
2593  };
2594
2595  // VR512 Register Class...
2596  const MCPhysReg VR512[] = {
2597    X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31,
2598  };
2599
2600  // VR512 Bit set.
2601  const uint8_t VR512Bits[] = {
2602    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
2603  };
2604
2605  // VR512_0_15 Register Class...
2606  const MCPhysReg VR512_0_15[] = {
2607    X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15,
2608  };
2609
2610  // VR512_0_15 Bit set.
2611  const uint8_t VR512_0_15Bits[] = {
2612    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
2613  };
2614
2615  // TILE Register Class...
2616  const MCPhysReg TILE[] = {
2617    X86::TMM0, X86::TMM1, X86::TMM2, X86::TMM3, X86::TMM4, X86::TMM5, X86::TMM6, X86::TMM7,
2618  };
2619
2620  // TILE Bit set.
2621  const uint8_t TILEBits[] = {
2622    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
2623  };
2624
2625} // end anonymous namespace
2626
2627extern const char X86RegClassStrings[] = {
2628  /* 0 */ 'R', 'F', 'P', '8', '0', 0,
2629  /* 6 */ 'V', 'K', '1', 0,
2630  /* 10 */ 'V', 'R', '5', '1', '2', 0,
2631  /* 16 */ 'V', 'K', '3', '2', 0,
2632  /* 21 */ 'R', 'F', 'P', '3', '2', 0,
2633  /* 27 */ 'F', 'R', '3', '2', 0,
2634  /* 32 */ 'G', 'R', '3', '2', 0,
2635  /* 37 */ 'V', 'K', '2', 0,
2636  /* 41 */ 'V', 'K', '6', '4', 0,
2637  /* 46 */ 'R', 'F', 'P', '6', '4', 0,
2638  /* 52 */ 'F', 'R', '6', '4', 0,
2639  /* 57 */ 'G', 'R', '6', '4', 0,
2640  /* 62 */ 'V', 'R', '6', '4', 0,
2641  /* 67 */ 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
2642  /* 90 */ 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
2643  /* 127 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
2644  /* 153 */ 'G', 'R', '6', '4', 'P', 'L', 'T', 'S', 'a', 'f', 'e', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
2645  /* 180 */ 'V', 'K', '4', 0,
2646  /* 184 */ 'V', 'R', '5', '1', '2', '_', '0', '_', '1', '5', 0,
2647  /* 195 */ 'G', 'R', 'H', '1', '6', 0,
2648  /* 201 */ 'V', 'K', '1', '6', 0,
2649  /* 206 */ 'F', 'R', '1', '6', 0,
2650  /* 211 */ 'G', 'R', '1', '6', 0,
2651  /* 216 */ 'V', 'R', '2', '5', '6', 0,
2652  /* 222 */ 'R', 'F', 'P', '8', '0', '_', '7', 0,
2653  /* 230 */ 'V', 'R', '1', '2', '8', 0,
2654  /* 236 */ 'G', 'R', 'H', '8', 0,
2655  /* 241 */ 'V', 'K', '8', 0,
2656  /* 245 */ 'G', 'R', '8', 0,
2657  /* 249 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'C', 'B', 0,
2658  /* 280 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'C', 'B', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'D', 'C', 0,
2659  /* 323 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'A', 'D', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'D', 'C', 0,
2660  /* 366 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'D', 'C', 0,
2661  /* 397 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'A', 'B', 'C', 'D', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'T', 'C', 0,
2662  /* 442 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'P', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'T', 'C', 0,
2663  /* 487 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'T', 'C', 0,
2664  /* 518 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0,
2665  /* 540 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0,
2666  /* 563 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', 'P', 'L', 'T', 'S', 'a', 'f', 'e', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0,
2667  /* 602 */ 'G', 'R', '3', '2', '_', 'A', 'D', 0,
2668  /* 610 */ 'G', 'R', '6', '4', '_', 'A', 'D', 0,
2669  /* 618 */ 'G', 'R', '3', '2', '_', 'A', 'B', 'C', 'D', 0,
2670  /* 628 */ 'G', 'R', '6', '4', '_', 'A', 'B', 'C', 'D', 0,
2671  /* 638 */ 'G', 'R', '1', '6', '_', 'A', 'B', 'C', 'D', 0,
2672  /* 648 */ 'T', 'I', 'L', 'E', 0,
2673  /* 653 */ 'D', 'E', 'B', 'U', 'G', '_', 'R', 'E', 'G', 0,
2674  /* 663 */ 'C', 'O', 'N', 'T', 'R', 'O', 'L', '_', 'R', 'E', 'G', 0,
2675  /* 675 */ 'S', 'E', 'G', 'M', 'E', 'N', 'T', '_', 'R', 'E', 'G', 0,
2676  /* 687 */ 'G', 'R', '8', '_', 'A', 'B', 'C', 'D', '_', 'H', 0,
2677  /* 698 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'S', 'I', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'S', 'I', 'D', 'I', 0,
2678  /* 744 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'D', 'I', 'B', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'S', 'I', 'D', 'I', 0,
2679  /* 791 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'S', 'I', 'D', 'I', 0,
2680  /* 824 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'A', 'B', 'C', 'D', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'B', 'S', 'I', 0,
2681  /* 870 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'S', 'I', 0,
2682  /* 902 */ 'G', 'R', '8', '_', 'A', 'B', 'C', 'D', '_', 'L', 0,
2683  /* 913 */ 'V', 'K', '1', 'W', 'M', 0,
2684  /* 919 */ 'V', 'K', '3', '2', 'W', 'M', 0,
2685  /* 926 */ 'V', 'K', '2', 'W', 'M', 0,
2686  /* 932 */ 'V', 'K', '6', '4', 'W', 'M', 0,
2687  /* 939 */ 'V', 'K', '4', 'W', 'M', 0,
2688  /* 945 */ 'V', 'K', '1', '6', 'P', 'A', 'I', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'm', 'a', 's', 'k', '_', '0', '_', 'i', 'n', '_', 'V', 'K', '1', '6', 'W', 'M', 0,
2689  /* 980 */ 'V', 'K', '8', 'W', 'M', 0,
2690  /* 986 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'P', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'D', 'I', 'B', 'P', 0,
2691  /* 1033 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'D', 'I', 'B', 'P', 0,
2692  /* 1066 */ 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', 0,
2693  /* 1097 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'S', 'P', 0,
2694  /* 1107 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', 0,
2695  /* 1117 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', 0,
2696  /* 1133 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', 0,
2697  /* 1149 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'P', 'S', 'P', 0,
2698  /* 1182 */ 'D', 'F', 'C', 'C', 'R', 0,
2699  /* 1188 */ 'F', 'P', 'C', 'C', 'R', 0,
2700  /* 1194 */ 'V', 'K', '1', 'P', 'A', 'I', 'R', 0,
2701  /* 1202 */ 'V', 'K', '2', 'P', 'A', 'I', 'R', 0,
2702  /* 1210 */ 'V', 'K', '4', 'P', 'A', 'I', 'R', 0,
2703  /* 1218 */ 'V', 'K', '1', '6', 'P', 'A', 'I', 'R', 0,
2704  /* 1227 */ 'V', 'K', '8', 'P', 'A', 'I', 'R', 0,
2705  /* 1235 */ 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', 0,
2706  /* 1262 */ 'R', 'S', 'T', 0,
2707  /* 1266 */ 'F', 'R', '3', '2', 'X', 0,
2708  /* 1272 */ 'F', 'R', '6', '4', 'X', 0,
2709  /* 1278 */ 'F', 'R', '1', '6', 'X', 0,
2710  /* 1284 */ 'V', 'R', '2', '5', '6', 'X', 0,
2711  /* 1291 */ 'V', 'R', '1', '2', '8', 'X', 0,
2712  /* 1298 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'R', 'E', 'X', 0,
2713  /* 1309 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', 0,
2714  /* 1320 */ 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '1', '6', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '1', '6', '_', 'N', 'O', 'R', 'E', 'X', 0,
2715  /* 1366 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '1', '6', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '1', '6', '_', 'N', 'O', 'R', 'E', 'X', 0,
2716  /* 1417 */ 'G', 'R', '8', '_', 'N', 'O', 'R', 'E', 'X', 0,
2717  /* 1427 */ 'G', 'R', '6', '4', 'P', 'L', 'T', 'S', 'a', 'f', 'e', 0,
2718  /* 1439 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0,
2719  /* 1476 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0,
2720  /* 1509 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0,
2721  /* 1560 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
2722  /* 1579 */ 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
2723  /* 1604 */ 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
2724  /* 1641 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
2725  0
2726};
2727
2728extern const MCRegisterClass X86MCRegisterClasses[] = {
2729  { GR8, GR8Bits, 245, 20, sizeof(GR8Bits), X86::GR8RegClassID, 8, 1, true },
2730  { GRH8, GRH8Bits, 236, 12, sizeof(GRH8Bits), X86::GRH8RegClassID, 8, 1, false },
2731  { GR8_NOREX, GR8_NOREXBits, 1417, 8, sizeof(GR8_NOREXBits), X86::GR8_NOREXRegClassID, 8, 1, true },
2732  { GR8_ABCD_H, GR8_ABCD_HBits, 687, 4, sizeof(GR8_ABCD_HBits), X86::GR8_ABCD_HRegClassID, 8, 1, true },
2733  { GR8_ABCD_L, GR8_ABCD_LBits, 902, 4, sizeof(GR8_ABCD_LBits), X86::GR8_ABCD_LRegClassID, 8, 1, true },
2734  { GRH16, GRH16Bits, 195, 17, sizeof(GRH16Bits), X86::GRH16RegClassID, 16, 1, false },
2735  { GR16, GR16Bits, 211, 16, sizeof(GR16Bits), X86::GR16RegClassID, 16, 1, true },
2736  { GR16_NOREX, GR16_NOREXBits, 1355, 8, sizeof(GR16_NOREXBits), X86::GR16_NOREXRegClassID, 16, 1, true },
2737  { VK1, VK1Bits, 6, 8, sizeof(VK1Bits), X86::VK1RegClassID, 16, 1, true },
2738  { VK16, VK16Bits, 201, 8, sizeof(VK16Bits), X86::VK16RegClassID, 16, 1, true },
2739  { VK2, VK2Bits, 37, 8, sizeof(VK2Bits), X86::VK2RegClassID, 16, 1, true },
2740  { VK4, VK4Bits, 180, 8, sizeof(VK4Bits), X86::VK4RegClassID, 16, 1, true },
2741  { VK8, VK8Bits, 241, 8, sizeof(VK8Bits), X86::VK8RegClassID, 16, 1, true },
2742  { VK16WM, VK16WMBits, 973, 7, sizeof(VK16WMBits), X86::VK16WMRegClassID, 16, 1, true },
2743  { VK1WM, VK1WMBits, 913, 7, sizeof(VK1WMBits), X86::VK1WMRegClassID, 16, 1, true },
2744  { VK2WM, VK2WMBits, 926, 7, sizeof(VK2WMBits), X86::VK2WMRegClassID, 16, 1, true },
2745  { VK4WM, VK4WMBits, 939, 7, sizeof(VK4WMBits), X86::VK4WMRegClassID, 16, 1, true },
2746  { VK8WM, VK8WMBits, 980, 7, sizeof(VK8WMBits), X86::VK8WMRegClassID, 16, 1, true },
2747  { SEGMENT_REG, SEGMENT_REGBits, 675, 6, sizeof(SEGMENT_REGBits), X86::SEGMENT_REGRegClassID, 16, 1, true },
2748  { GR16_ABCD, GR16_ABCDBits, 638, 4, sizeof(GR16_ABCDBits), X86::GR16_ABCDRegClassID, 16, 1, true },
2749  { FPCCR, FPCCRBits, 1188, 1, sizeof(FPCCRBits), X86::FPCCRRegClassID, 16, -1, false },
2750  { FR16X, FR16XBits, 1278, 32, sizeof(FR16XBits), X86::FR16XRegClassID, 32, 1, true },
2751  { FR16, FR16Bits, 206, 16, sizeof(FR16Bits), X86::FR16RegClassID, 32, 1, true },
2752  { VK16PAIR, VK16PAIRBits, 1218, 4, sizeof(VK16PAIRBits), X86::VK16PAIRRegClassID, 32, 1, true },
2753  { VK1PAIR, VK1PAIRBits, 1194, 4, sizeof(VK1PAIRBits), X86::VK1PAIRRegClassID, 32, 1, true },
2754  { VK2PAIR, VK2PAIRBits, 1202, 4, sizeof(VK2PAIRBits), X86::VK2PAIRRegClassID, 32, 1, true },
2755  { VK4PAIR, VK4PAIRBits, 1210, 4, sizeof(VK4PAIRBits), X86::VK4PAIRRegClassID, 32, 1, true },
2756  { VK8PAIR, VK8PAIRBits, 1227, 4, sizeof(VK8PAIRBits), X86::VK8PAIRRegClassID, 32, 1, true },
2757  { VK16PAIR_with_sub_mask_0_in_VK16WM, VK16PAIR_with_sub_mask_0_in_VK16WMBits, 945, 3, sizeof(VK16PAIR_with_sub_mask_0_in_VK16WMBits), X86::VK16PAIR_with_sub_mask_0_in_VK16WMRegClassID, 32, 1, true },
2758  { FR32X, FR32XBits, 1266, 32, sizeof(FR32XBits), X86::FR32XRegClassID, 32, 1, true },
2759  { LOW32_ADDR_ACCESS_RBP, LOW32_ADDR_ACCESS_RBPBits, 1075, 18, sizeof(LOW32_ADDR_ACCESS_RBPBits), X86::LOW32_ADDR_ACCESS_RBPRegClassID, 32, 1, true },
2760  { LOW32_ADDR_ACCESS, LOW32_ADDR_ACCESSBits, 1244, 17, sizeof(LOW32_ADDR_ACCESSBits), X86::LOW32_ADDR_ACCESSRegClassID, 32, 1, true },
2761  { LOW32_ADDR_ACCESS_RBP_with_sub_8bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits, 1641, 17, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 32, 1, true },
2762  { DEBUG_REG, DEBUG_REGBits, 653, 16, sizeof(DEBUG_REGBits), X86::DEBUG_REGRegClassID, 32, 1, true },
2763  { FR32, FR32Bits, 27, 16, sizeof(FR32Bits), X86::FR32RegClassID, 32, 1, true },
2764  { GR32, GR32Bits, 32, 16, sizeof(GR32Bits), X86::GR32RegClassID, 32, 1, true },
2765  { GR32_NOSP, GR32_NOSPBits, 1097, 15, sizeof(GR32_NOSPBits), X86::GR32_NOSPRegClassID, 32, 1, true },
2766  { LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX, LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits, 1366, 9, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, 32, 1, true },
2767  { GR32_NOREX, GR32_NOREXBits, 1298, 8, sizeof(GR32_NOREXBits), X86::GR32_NOREXRegClassID, 32, 1, true },
2768  { VK32, VK32Bits, 16, 8, sizeof(VK32Bits), X86::VK32RegClassID, 32, 1, true },
2769  { GR32_NOREX_NOSP, GR32_NOREX_NOSPBits, 1117, 7, sizeof(GR32_NOREX_NOSPBits), X86::GR32_NOREX_NOSPRegClassID, 32, 1, true },
2770  { RFP32, RFP32Bits, 21, 7, sizeof(RFP32Bits), X86::RFP32RegClassID, 32, 1, true },
2771  { VK32WM, VK32WMBits, 919, 7, sizeof(VK32WMBits), X86::VK32WMRegClassID, 32, 1, true },
2772  { GR32_ABCD, GR32_ABCDBits, 618, 4, sizeof(GR32_ABCDBits), X86::GR32_ABCDRegClassID, 32, 1, true },
2773  { GR32_TC, GR32_TCBits, 434, 4, sizeof(GR32_TCBits), X86::GR32_TCRegClassID, 32, 1, true },
2774  { GR32_ABCD_and_GR32_TC, GR32_ABCD_and_GR32_TCBits, 420, 3, sizeof(GR32_ABCD_and_GR32_TCBits), X86::GR32_ABCD_and_GR32_TCRegClassID, 32, 1, true },
2775  { GR32_AD, GR32_ADBits, 602, 2, sizeof(GR32_ADBits), X86::GR32_ADRegClassID, 32, 1, true },
2776  { GR32_BPSP, GR32_BPSPBits, 1172, 2, sizeof(GR32_BPSPBits), X86::GR32_BPSPRegClassID, 32, 1, true },
2777  { GR32_BSI, GR32_BSIBits, 861, 2, sizeof(GR32_BSIBits), X86::GR32_BSIRegClassID, 32, 1, true },
2778  { GR32_CB, GR32_CBBits, 272, 2, sizeof(GR32_CBBits), X86::GR32_CBRegClassID, 32, 1, true },
2779  { GR32_DC, GR32_DCBits, 315, 2, sizeof(GR32_DCBits), X86::GR32_DCRegClassID, 32, 1, true },
2780  { GR32_DIBP, GR32_DIBPBits, 1023, 2, sizeof(GR32_DIBPBits), X86::GR32_DIBPRegClassID, 32, 1, true },
2781  { GR32_SIDI, GR32_SIDIBits, 734, 2, sizeof(GR32_SIDIBits), X86::GR32_SIDIRegClassID, 32, 1, true },
2782  { LOW32_ADDR_ACCESS_RBP_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits, 1439, 2, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID, 32, 1, true },
2783  { CCR, CCRBits, 1184, 1, sizeof(CCRBits), X86::CCRRegClassID, 32, -1, false },
2784  { DFCCR, DFCCRBits, 1182, 1, sizeof(DFCCRBits), X86::DFCCRRegClassID, 32, -1, false },
2785  { GR32_ABCD_and_GR32_BSI, GR32_ABCD_and_GR32_BSIBits, 847, 1, sizeof(GR32_ABCD_and_GR32_BSIBits), X86::GR32_ABCD_and_GR32_BSIRegClassID, 32, 1, true },
2786  { GR32_AD_and_GR32_DC, GR32_AD_and_GR32_DCBits, 346, 1, sizeof(GR32_AD_and_GR32_DCBits), X86::GR32_AD_and_GR32_DCRegClassID, 32, 1, true },
2787  { GR32_BPSP_and_GR32_DIBP, GR32_BPSP_and_GR32_DIBPBits, 1009, 1, sizeof(GR32_BPSP_and_GR32_DIBPBits), X86::GR32_BPSP_and_GR32_DIBPRegClassID, 32, 1, true },
2788  { GR32_BPSP_and_GR32_TC, GR32_BPSP_and_GR32_TCBits, 465, 1, sizeof(GR32_BPSP_and_GR32_TCBits), X86::GR32_BPSP_and_GR32_TCRegClassID, 32, 1, true },
2789  { GR32_BSI_and_GR32_SIDI, GR32_BSI_and_GR32_SIDIBits, 721, 1, sizeof(GR32_BSI_and_GR32_SIDIBits), X86::GR32_BSI_and_GR32_SIDIRegClassID, 32, 1, true },
2790  { GR32_CB_and_GR32_DC, GR32_CB_and_GR32_DCBits, 303, 1, sizeof(GR32_CB_and_GR32_DCBits), X86::GR32_CB_and_GR32_DCRegClassID, 32, 1, true },
2791  { GR32_DIBP_and_GR32_SIDI, GR32_DIBP_and_GR32_SIDIBits, 767, 1, sizeof(GR32_DIBP_and_GR32_SIDIBits), X86::GR32_DIBP_and_GR32_SIDIRegClassID, 32, 1, true },
2792  { LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits, 1509, 1, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID, 32, 1, true },
2793  { LOW32_ADDR_ACCESS_with_sub_32bit, LOW32_ADDR_ACCESS_with_sub_32bitBits, 1476, 1, sizeof(LOW32_ADDR_ACCESS_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClassID, 32, 1, true },
2794  { RFP64, RFP64Bits, 46, 7, sizeof(RFP64Bits), X86::RFP64RegClassID, 64, 1, true },
2795  { FR64X, FR64XBits, 1272, 32, sizeof(FR64XBits), X86::FR64XRegClassID, 64, 1, true },
2796  { GR64, GR64Bits, 57, 17, sizeof(GR64Bits), X86::GR64RegClassID, 64, 1, true },
2797  { CONTROL_REG, CONTROL_REGBits, 663, 16, sizeof(CONTROL_REGBits), X86::CONTROL_REGRegClassID, 64, 1, true },
2798  { FR64, FR64Bits, 52, 16, sizeof(FR64Bits), X86::FR64RegClassID, 64, 1, true },
2799  { GR64_with_sub_8bit, GR64_with_sub_8bitBits, 1560, 16, sizeof(GR64_with_sub_8bitBits), X86::GR64_with_sub_8bitRegClassID, 64, 1, true },
2800  { GR64_NOSP, GR64_NOSPBits, 1107, 15, sizeof(GR64_NOSPBits), X86::GR64_NOSPRegClassID, 64, 1, true },
2801  { GR64PLTSafe, GR64PLTSafeBits, 1427, 13, sizeof(GR64PLTSafeBits), X86::GR64PLTSafeRegClassID, 64, 1, true },
2802  { GR64_TC, GR64_TCBits, 532, 10, sizeof(GR64_TCBits), X86::GR64_TCRegClassID, 64, 1, true },
2803  { GR64_NOREX, GR64_NOREXBits, 1309, 9, sizeof(GR64_NOREXBits), X86::GR64_NOREXRegClassID, 64, 1, true },
2804  { GR64_TCW64, GR64_TCW64Bits, 79, 9, sizeof(GR64_TCW64Bits), X86::GR64_TCW64RegClassID, 64, 1, true },
2805  { GR64_TC_with_sub_8bit, GR64_TC_with_sub_8bitBits, 1619, 9, sizeof(GR64_TC_with_sub_8bitBits), X86::GR64_TC_with_sub_8bitRegClassID, 64, 1, true },
2806  { GR64_NOSP_and_GR64_TC, GR64_NOSP_and_GR64_TCBits, 518, 8, sizeof(GR64_NOSP_and_GR64_TCBits), X86::GR64_NOSP_and_GR64_TCRegClassID, 64, 1, true },
2807  { GR64_TCW64_with_sub_8bit, GR64_TCW64_with_sub_8bitBits, 1579, 8, sizeof(GR64_TCW64_with_sub_8bitBits), X86::GR64_TCW64_with_sub_8bitRegClassID, 64, 1, true },
2808  { GR64_TC_and_GR64_TCW64, GR64_TC_and_GR64_TCW64Bits, 67, 8, sizeof(GR64_TC_and_GR64_TCW64Bits), X86::GR64_TC_and_GR64_TCW64RegClassID, 64, 1, true },
2809  { GR64_with_sub_16bit_in_GR16_NOREX, GR64_with_sub_16bit_in_GR16_NOREXBits, 1332, 8, sizeof(GR64_with_sub_16bit_in_GR16_NOREXBits), X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, 64, 1, true },
2810  { VK64, VK64Bits, 41, 8, sizeof(VK64Bits), X86::VK64RegClassID, 64, 1, true },
2811  { VR64, VR64Bits, 62, 8, sizeof(VR64Bits), X86::VR64RegClassID, 64, 1, true },
2812  { GR64PLTSafe_and_GR64_TC, GR64PLTSafe_and_GR64_TCBits, 578, 7, sizeof(GR64PLTSafe_and_GR64_TCBits), X86::GR64PLTSafe_and_GR64_TCRegClassID, 64, 1, true },
2813  { GR64_NOREX_NOSP, GR64_NOREX_NOSPBits, 1133, 7, sizeof(GR64_NOREX_NOSPBits), X86::GR64_NOREX_NOSPRegClassID, 64, 1, true },
2814  { GR64_NOREX_and_GR64_TC, GR64_NOREX_and_GR64_TCBits, 540, 7, sizeof(GR64_NOREX_and_GR64_TCBits), X86::GR64_NOREX_and_GR64_TCRegClassID, 64, 1, true },
2815  { GR64_NOSP_and_GR64_TCW64, GR64_NOSP_and_GR64_TCW64Bits, 102, 7, sizeof(GR64_NOSP_and_GR64_TCW64Bits), X86::GR64_NOSP_and_GR64_TCW64RegClassID, 64, 1, true },
2816  { GR64_TCW64_and_GR64_TC_with_sub_8bit, GR64_TCW64_and_GR64_TC_with_sub_8bitBits, 1604, 7, sizeof(GR64_TCW64_and_GR64_TC_with_sub_8bitBits), X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, 64, 1, true },
2817  { VK64WM, VK64WMBits, 932, 7, sizeof(VK64WMBits), X86::VK64WMRegClassID, 64, 1, true },
2818  { GR64_TC_and_GR64_NOSP_and_GR64_TCW64, GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits, 90, 6, sizeof(GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits), X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID, 64, 1, true },
2819  { GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX, GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits, 1320, 6, sizeof(GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits), X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, 64, 1, true },
2820  { GR64PLTSafe_and_GR64_TCW64, GR64PLTSafe_and_GR64_TCW64Bits, 153, 5, sizeof(GR64PLTSafe_and_GR64_TCW64Bits), X86::GR64PLTSafe_and_GR64_TCW64RegClassID, 64, 1, true },
2821  { GR64_NOREX_and_GR64PLTSafe_and_GR64_TC, GR64_NOREX_and_GR64PLTSafe_and_GR64_TCBits, 563, 5, sizeof(GR64_NOREX_and_GR64PLTSafe_and_GR64_TCBits), X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, 64, 1, true },
2822  { GR64_NOREX_and_GR64_TCW64, GR64_NOREX_and_GR64_TCW64Bits, 127, 5, sizeof(GR64_NOREX_and_GR64_TCW64Bits), X86::GR64_NOREX_and_GR64_TCW64RegClassID, 64, 1, true },
2823  { GR64_ABCD, GR64_ABCDBits, 628, 4, sizeof(GR64_ABCDBits), X86::GR64_ABCDRegClassID, 64, 1, true },
2824  { GR64_with_sub_32bit_in_GR32_TC, GR64_with_sub_32bit_in_GR32_TCBits, 487, 4, sizeof(GR64_with_sub_32bit_in_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, 64, 1, true },
2825  { GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC, GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits, 397, 3, sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID, 64, 1, true },
2826  { GR64_AD, GR64_ADBits, 610, 2, sizeof(GR64_ADBits), X86::GR64_ADRegClassID, 64, 1, true },
2827  { GR64_and_LOW32_ADDR_ACCESS_RBP, GR64_and_LOW32_ADDR_ACCESS_RBPBits, 1066, 2, sizeof(GR64_and_LOW32_ADDR_ACCESS_RBPBits), X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID, 64, 1, true },
2828  { GR64_with_sub_32bit_in_GR32_BPSP, GR64_with_sub_32bit_in_GR32_BPSPBits, 1149, 2, sizeof(GR64_with_sub_32bit_in_GR32_BPSPBits), X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID, 64, 1, true },
2829  { GR64_with_sub_32bit_in_GR32_BSI, GR64_with_sub_32bit_in_GR32_BSIBits, 870, 2, sizeof(GR64_with_sub_32bit_in_GR32_BSIBits), X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID, 64, 1, true },
2830  { GR64_with_sub_32bit_in_GR32_CB, GR64_with_sub_32bit_in_GR32_CBBits, 249, 2, sizeof(GR64_with_sub_32bit_in_GR32_CBBits), X86::GR64_with_sub_32bit_in_GR32_CBRegClassID, 64, 1, true },
2831  { GR64_with_sub_32bit_in_GR32_DC, GR64_with_sub_32bit_in_GR32_DCBits, 366, 2, sizeof(GR64_with_sub_32bit_in_GR32_DCBits), X86::GR64_with_sub_32bit_in_GR32_DCRegClassID, 64, 1, true },
2832  { GR64_with_sub_32bit_in_GR32_DIBP, GR64_with_sub_32bit_in_GR32_DIBPBits, 1033, 2, sizeof(GR64_with_sub_32bit_in_GR32_DIBPBits), X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID, 64, 1, true },
2833  { GR64_with_sub_32bit_in_GR32_SIDI, GR64_with_sub_32bit_in_GR32_SIDIBits, 791, 2, sizeof(GR64_with_sub_32bit_in_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID, 64, 1, true },
2834  { GR64_and_LOW32_ADDR_ACCESS, GR64_and_LOW32_ADDR_ACCESSBits, 1235, 1, sizeof(GR64_and_LOW32_ADDR_ACCESSBits), X86::GR64_and_LOW32_ADDR_ACCESSRegClassID, 64, 1, true },
2835  { GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI, GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits, 824, 1, sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits), X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID, 64, 1, true },
2836  { GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC, GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCBits, 323, 1, sizeof(GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCBits), X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID, 64, 1, true },
2837  { GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP, GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits, 986, 1, sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits), X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID, 64, 1, true },
2838  { GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC, GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits, 442, 1, sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID, 64, 1, true },
2839  { GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI, GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits, 698, 1, sizeof(GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID, 64, 1, true },
2840  { GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC, GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCBits, 280, 1, sizeof(GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCBits), X86::GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID, 64, 1, true },
2841  { GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI, GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits, 744, 1, sizeof(GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID, 64, 1, true },
2842  { RST, RSTBits, 1262, 8, sizeof(RSTBits), X86::RSTRegClassID, 80, 1, false },
2843  { RFP80, RFP80Bits, 0, 7, sizeof(RFP80Bits), X86::RFP80RegClassID, 80, 1, true },
2844  { RFP80_7, RFP80_7Bits, 222, 1, sizeof(RFP80_7Bits), X86::RFP80_7RegClassID, 80, 1, false },
2845  { VR128X, VR128XBits, 1291, 32, sizeof(VR128XBits), X86::VR128XRegClassID, 128, 1, true },
2846  { VR128, VR128Bits, 230, 16, sizeof(VR128Bits), X86::VR128RegClassID, 128, 1, true },
2847  { VR256X, VR256XBits, 1284, 32, sizeof(VR256XBits), X86::VR256XRegClassID, 256, 1, true },
2848  { VR256, VR256Bits, 216, 16, sizeof(VR256Bits), X86::VR256RegClassID, 256, 1, true },
2849  { VR512, VR512Bits, 10, 32, sizeof(VR512Bits), X86::VR512RegClassID, 512, 1, true },
2850  { VR512_0_15, VR512_0_15Bits, 184, 16, sizeof(VR512_0_15Bits), X86::VR512_0_15RegClassID, 512, 1, true },
2851  { TILE, TILEBits, 648, 8, sizeof(TILEBits), X86::TILERegClassID, 8192, -1, true },
2852};
2853
2854// X86 Dwarf<->LLVM register mappings.
2855extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[] = {
2856  { 0U, X86::RAX },
2857  { 1U, X86::RDX },
2858  { 2U, X86::RCX },
2859  { 3U, X86::RBX },
2860  { 4U, X86::RSI },
2861  { 5U, X86::RDI },
2862  { 6U, X86::RBP },
2863  { 7U, X86::RSP },
2864  { 8U, X86::R8 },
2865  { 9U, X86::R9 },
2866  { 10U, X86::R10 },
2867  { 11U, X86::R11 },
2868  { 12U, X86::R12 },
2869  { 13U, X86::R13 },
2870  { 14U, X86::R14 },
2871  { 15U, X86::R15 },
2872  { 16U, X86::RIP },
2873  { 17U, X86::XMM0 },
2874  { 18U, X86::XMM1 },
2875  { 19U, X86::XMM2 },
2876  { 20U, X86::XMM3 },
2877  { 21U, X86::XMM4 },
2878  { 22U, X86::XMM5 },
2879  { 23U, X86::XMM6 },
2880  { 24U, X86::XMM7 },
2881  { 25U, X86::XMM8 },
2882  { 26U, X86::XMM9 },
2883  { 27U, X86::XMM10 },
2884  { 28U, X86::XMM11 },
2885  { 29U, X86::XMM12 },
2886  { 30U, X86::XMM13 },
2887  { 31U, X86::XMM14 },
2888  { 32U, X86::XMM15 },
2889  { 33U, X86::ST0 },
2890  { 34U, X86::ST1 },
2891  { 35U, X86::ST2 },
2892  { 36U, X86::ST3 },
2893  { 37U, X86::ST4 },
2894  { 38U, X86::ST5 },
2895  { 39U, X86::ST6 },
2896  { 40U, X86::ST7 },
2897  { 41U, X86::MM0 },
2898  { 42U, X86::MM1 },
2899  { 43U, X86::MM2 },
2900  { 44U, X86::MM3 },
2901  { 45U, X86::MM4 },
2902  { 46U, X86::MM5 },
2903  { 47U, X86::MM6 },
2904  { 48U, X86::MM7 },
2905  { 49U, X86::RFLAGS },
2906  { 58U, X86::FS_BASE },
2907  { 59U, X86::GS_BASE },
2908  { 67U, X86::XMM16 },
2909  { 68U, X86::XMM17 },
2910  { 69U, X86::XMM18 },
2911  { 70U, X86::XMM19 },
2912  { 71U, X86::XMM20 },
2913  { 72U, X86::XMM21 },
2914  { 73U, X86::XMM22 },
2915  { 74U, X86::XMM23 },
2916  { 75U, X86::XMM24 },
2917  { 76U, X86::XMM25 },
2918  { 77U, X86::XMM26 },
2919  { 78U, X86::XMM27 },
2920  { 79U, X86::XMM28 },
2921  { 80U, X86::XMM29 },
2922  { 81U, X86::XMM30 },
2923  { 82U, X86::XMM31 },
2924  { 118U, X86::K0 },
2925  { 119U, X86::K1 },
2926  { 120U, X86::K2 },
2927  { 121U, X86::K3 },
2928  { 122U, X86::K4 },
2929  { 123U, X86::K5 },
2930  { 124U, X86::K6 },
2931  { 125U, X86::K7 },
2932};
2933extern const unsigned X86DwarfFlavour0Dwarf2LSize = std::size(X86DwarfFlavour0Dwarf2L);
2934
2935extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[] = {
2936  { 0U, X86::EAX },
2937  { 1U, X86::ECX },
2938  { 2U, X86::EDX },
2939  { 3U, X86::EBX },
2940  { 4U, X86::EBP },
2941  { 5U, X86::ESP },
2942  { 6U, X86::ESI },
2943  { 7U, X86::EDI },
2944  { 8U, X86::EIP },
2945  { 9U, X86::EFLAGS },
2946  { 12U, X86::ST0 },
2947  { 13U, X86::ST1 },
2948  { 14U, X86::ST2 },
2949  { 15U, X86::ST3 },
2950  { 16U, X86::ST4 },
2951  { 17U, X86::ST5 },
2952  { 18U, X86::ST6 },
2953  { 19U, X86::ST7 },
2954  { 21U, X86::XMM0 },
2955  { 22U, X86::XMM1 },
2956  { 23U, X86::XMM2 },
2957  { 24U, X86::XMM3 },
2958  { 25U, X86::XMM4 },
2959  { 26U, X86::XMM5 },
2960  { 27U, X86::XMM6 },
2961  { 28U, X86::XMM7 },
2962  { 29U, X86::MM0 },
2963  { 30U, X86::MM1 },
2964  { 31U, X86::MM2 },
2965  { 32U, X86::MM3 },
2966  { 33U, X86::MM4 },
2967  { 34U, X86::MM5 },
2968  { 35U, X86::MM6 },
2969  { 36U, X86::MM7 },
2970  { 93U, X86::K0 },
2971  { 94U, X86::K1 },
2972  { 95U, X86::K2 },
2973  { 96U, X86::K3 },
2974  { 97U, X86::K4 },
2975  { 98U, X86::K5 },
2976  { 99U, X86::K6 },
2977  { 100U, X86::K7 },
2978};
2979extern const unsigned X86DwarfFlavour1Dwarf2LSize = std::size(X86DwarfFlavour1Dwarf2L);
2980
2981extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[] = {
2982  { 0U, X86::EAX },
2983  { 1U, X86::ECX },
2984  { 2U, X86::EDX },
2985  { 3U, X86::EBX },
2986  { 4U, X86::ESP },
2987  { 5U, X86::EBP },
2988  { 6U, X86::ESI },
2989  { 7U, X86::EDI },
2990  { 8U, X86::EIP },
2991  { 9U, X86::EFLAGS },
2992  { 11U, X86::ST0 },
2993  { 12U, X86::ST1 },
2994  { 13U, X86::ST2 },
2995  { 14U, X86::ST3 },
2996  { 15U, X86::ST4 },
2997  { 16U, X86::ST5 },
2998  { 17U, X86::ST6 },
2999  { 18U, X86::ST7 },
3000  { 21U, X86::XMM0 },
3001  { 22U, X86::XMM1 },
3002  { 23U, X86::XMM2 },
3003  { 24U, X86::XMM3 },
3004  { 25U, X86::XMM4 },
3005  { 26U, X86::XMM5 },
3006  { 27U, X86::XMM6 },
3007  { 28U, X86::XMM7 },
3008  { 29U, X86::MM0 },
3009  { 30U, X86::MM1 },
3010  { 31U, X86::MM2 },
3011  { 32U, X86::MM3 },
3012  { 33U, X86::MM4 },
3013  { 34U, X86::MM5 },
3014  { 35U, X86::MM6 },
3015  { 36U, X86::MM7 },
3016  { 93U, X86::K0 },
3017  { 94U, X86::K1 },
3018  { 95U, X86::K2 },
3019  { 96U, X86::K3 },
3020  { 97U, X86::K4 },
3021  { 98U, X86::K5 },
3022  { 99U, X86::K6 },
3023  { 100U, X86::K7 },
3024};
3025extern const unsigned X86DwarfFlavour2Dwarf2LSize = std::size(X86DwarfFlavour2Dwarf2L);
3026
3027extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[] = {
3028  { 0U, X86::RAX },
3029  { 1U, X86::RDX },
3030  { 2U, X86::RCX },
3031  { 3U, X86::RBX },
3032  { 4U, X86::RSI },
3033  { 5U, X86::RDI },
3034  { 6U, X86::RBP },
3035  { 7U, X86::RSP },
3036  { 8U, X86::R8 },
3037  { 9U, X86::R9 },
3038  { 10U, X86::R10 },
3039  { 11U, X86::R11 },
3040  { 12U, X86::R12 },
3041  { 13U, X86::R13 },
3042  { 14U, X86::R14 },
3043  { 15U, X86::R15 },
3044  { 16U, X86::RIP },
3045  { 17U, X86::XMM0 },
3046  { 18U, X86::XMM1 },
3047  { 19U, X86::XMM2 },
3048  { 20U, X86::XMM3 },
3049  { 21U, X86::XMM4 },
3050  { 22U, X86::XMM5 },
3051  { 23U, X86::XMM6 },
3052  { 24U, X86::XMM7 },
3053  { 25U, X86::XMM8 },
3054  { 26U, X86::XMM9 },
3055  { 27U, X86::XMM10 },
3056  { 28U, X86::XMM11 },
3057  { 29U, X86::XMM12 },
3058  { 30U, X86::XMM13 },
3059  { 31U, X86::XMM14 },
3060  { 32U, X86::XMM15 },
3061  { 33U, X86::ST0 },
3062  { 34U, X86::ST1 },
3063  { 35U, X86::ST2 },
3064  { 36U, X86::ST3 },
3065  { 37U, X86::ST4 },
3066  { 38U, X86::ST5 },
3067  { 39U, X86::ST6 },
3068  { 40U, X86::ST7 },
3069  { 41U, X86::MM0 },
3070  { 42U, X86::MM1 },
3071  { 43U, X86::MM2 },
3072  { 44U, X86::MM3 },
3073  { 45U, X86::MM4 },
3074  { 46U, X86::MM5 },
3075  { 47U, X86::MM6 },
3076  { 48U, X86::MM7 },
3077  { 49U, X86::RFLAGS },
3078  { 58U, X86::FS_BASE },
3079  { 59U, X86::GS_BASE },
3080  { 67U, X86::XMM16 },
3081  { 68U, X86::XMM17 },
3082  { 69U, X86::XMM18 },
3083  { 70U, X86::XMM19 },
3084  { 71U, X86::XMM20 },
3085  { 72U, X86::XMM21 },
3086  { 73U, X86::XMM22 },
3087  { 74U, X86::XMM23 },
3088  { 75U, X86::XMM24 },
3089  { 76U, X86::XMM25 },
3090  { 77U, X86::XMM26 },
3091  { 78U, X86::XMM27 },
3092  { 79U, X86::XMM28 },
3093  { 80U, X86::XMM29 },
3094  { 81U, X86::XMM30 },
3095  { 82U, X86::XMM31 },
3096  { 118U, X86::K0 },
3097  { 119U, X86::K1 },
3098  { 120U, X86::K2 },
3099  { 121U, X86::K3 },
3100  { 122U, X86::K4 },
3101  { 123U, X86::K5 },
3102  { 124U, X86::K6 },
3103  { 125U, X86::K7 },
3104};
3105extern const unsigned X86EHFlavour0Dwarf2LSize = std::size(X86EHFlavour0Dwarf2L);
3106
3107extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[] = {
3108  { 0U, X86::EAX },
3109  { 1U, X86::ECX },
3110  { 2U, X86::EDX },
3111  { 3U, X86::EBX },
3112  { 4U, X86::EBP },
3113  { 5U, X86::ESP },
3114  { 6U, X86::ESI },
3115  { 7U, X86::EDI },
3116  { 8U, X86::EIP },
3117  { 9U, X86::EFLAGS },
3118  { 12U, X86::ST0 },
3119  { 13U, X86::ST1 },
3120  { 14U, X86::ST2 },
3121  { 15U, X86::ST3 },
3122  { 16U, X86::ST4 },
3123  { 17U, X86::ST5 },
3124  { 18U, X86::ST6 },
3125  { 19U, X86::ST7 },
3126  { 21U, X86::XMM0 },
3127  { 22U, X86::XMM1 },
3128  { 23U, X86::XMM2 },
3129  { 24U, X86::XMM3 },
3130  { 25U, X86::XMM4 },
3131  { 26U, X86::XMM5 },
3132  { 27U, X86::XMM6 },
3133  { 28U, X86::XMM7 },
3134  { 29U, X86::MM0 },
3135  { 30U, X86::MM1 },
3136  { 31U, X86::MM2 },
3137  { 32U, X86::MM3 },
3138  { 33U, X86::MM4 },
3139  { 34U, X86::MM5 },
3140  { 35U, X86::MM6 },
3141  { 36U, X86::MM7 },
3142  { 93U, X86::K0 },
3143  { 94U, X86::K1 },
3144  { 95U, X86::K2 },
3145  { 96U, X86::K3 },
3146  { 97U, X86::K4 },
3147  { 98U, X86::K5 },
3148  { 99U, X86::K6 },
3149  { 100U, X86::K7 },
3150};
3151extern const unsigned X86EHFlavour1Dwarf2LSize = std::size(X86EHFlavour1Dwarf2L);
3152
3153extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[] = {
3154  { 0U, X86::EAX },
3155  { 1U, X86::ECX },
3156  { 2U, X86::EDX },
3157  { 3U, X86::EBX },
3158  { 4U, X86::ESP },
3159  { 5U, X86::EBP },
3160  { 6U, X86::ESI },
3161  { 7U, X86::EDI },
3162  { 8U, X86::EIP },
3163  { 9U, X86::EFLAGS },
3164  { 11U, X86::ST0 },
3165  { 12U, X86::ST1 },
3166  { 13U, X86::ST2 },
3167  { 14U, X86::ST3 },
3168  { 15U, X86::ST4 },
3169  { 16U, X86::ST5 },
3170  { 17U, X86::ST6 },
3171  { 18U, X86::ST7 },
3172  { 21U, X86::XMM0 },
3173  { 22U, X86::XMM1 },
3174  { 23U, X86::XMM2 },
3175  { 24U, X86::XMM3 },
3176  { 25U, X86::XMM4 },
3177  { 26U, X86::XMM5 },
3178  { 27U, X86::XMM6 },
3179  { 28U, X86::XMM7 },
3180  { 29U, X86::MM0 },
3181  { 30U, X86::MM1 },
3182  { 31U, X86::MM2 },
3183  { 32U, X86::MM3 },
3184  { 33U, X86::MM4 },
3185  { 34U, X86::MM5 },
3186  { 35U, X86::MM6 },
3187  { 36U, X86::MM7 },
3188  { 93U, X86::K0 },
3189  { 94U, X86::K1 },
3190  { 95U, X86::K2 },
3191  { 96U, X86::K3 },
3192  { 97U, X86::K4 },
3193  { 98U, X86::K5 },
3194  { 99U, X86::K6 },
3195  { 100U, X86::K7 },
3196};
3197extern const unsigned X86EHFlavour2Dwarf2LSize = std::size(X86EHFlavour2Dwarf2L);
3198
3199extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[] = {
3200  { X86::EAX, -2U },
3201  { X86::EBP, -2U },
3202  { X86::EBX, -2U },
3203  { X86::ECX, -2U },
3204  { X86::EDI, -2U },
3205  { X86::EDX, -2U },
3206  { X86::EFLAGS, 49U },
3207  { X86::EIP, -2U },
3208  { X86::ESI, -2U },
3209  { X86::ESP, -2U },
3210  { X86::FS_BASE, 58U },
3211  { X86::GS_BASE, 59U },
3212  { X86::RAX, 0U },
3213  { X86::RBP, 6U },
3214  { X86::RBX, 3U },
3215  { X86::RCX, 2U },
3216  { X86::RDI, 5U },
3217  { X86::RDX, 1U },
3218  { X86::RFLAGS, 49U },
3219  { X86::RIP, 16U },
3220  { X86::RSI, 4U },
3221  { X86::RSP, 7U },
3222  { X86::_EFLAGS, 49U },
3223  { X86::K0, 118U },
3224  { X86::K1, 119U },
3225  { X86::K2, 120U },
3226  { X86::K3, 121U },
3227  { X86::K4, 122U },
3228  { X86::K5, 123U },
3229  { X86::K6, 124U },
3230  { X86::K7, 125U },
3231  { X86::MM0, 41U },
3232  { X86::MM1, 42U },
3233  { X86::MM2, 43U },
3234  { X86::MM3, 44U },
3235  { X86::MM4, 45U },
3236  { X86::MM5, 46U },
3237  { X86::MM6, 47U },
3238  { X86::MM7, 48U },
3239  { X86::R8, 8U },
3240  { X86::R9, 9U },
3241  { X86::R10, 10U },
3242  { X86::R11, 11U },
3243  { X86::R12, 12U },
3244  { X86::R13, 13U },
3245  { X86::R14, 14U },
3246  { X86::R15, 15U },
3247  { X86::ST0, 33U },
3248  { X86::ST1, 34U },
3249  { X86::ST2, 35U },
3250  { X86::ST3, 36U },
3251  { X86::ST4, 37U },
3252  { X86::ST5, 38U },
3253  { X86::ST6, 39U },
3254  { X86::ST7, 40U },
3255  { X86::XMM0, 17U },
3256  { X86::XMM1, 18U },
3257  { X86::XMM2, 19U },
3258  { X86::XMM3, 20U },
3259  { X86::XMM4, 21U },
3260  { X86::XMM5, 22U },
3261  { X86::XMM6, 23U },
3262  { X86::XMM7, 24U },
3263  { X86::XMM8, 25U },
3264  { X86::XMM9, 26U },
3265  { X86::XMM10, 27U },
3266  { X86::XMM11, 28U },
3267  { X86::XMM12, 29U },
3268  { X86::XMM13, 30U },
3269  { X86::XMM14, 31U },
3270  { X86::XMM15, 32U },
3271  { X86::XMM16, 67U },
3272  { X86::XMM17, 68U },
3273  { X86::XMM18, 69U },
3274  { X86::XMM19, 70U },
3275  { X86::XMM20, 71U },
3276  { X86::XMM21, 72U },
3277  { X86::XMM22, 73U },
3278  { X86::XMM23, 74U },
3279  { X86::XMM24, 75U },
3280  { X86::XMM25, 76U },
3281  { X86::XMM26, 77U },
3282  { X86::XMM27, 78U },
3283  { X86::XMM28, 79U },
3284  { X86::XMM29, 80U },
3285  { X86::XMM30, 81U },
3286  { X86::XMM31, 82U },
3287  { X86::YMM0, 17U },
3288  { X86::YMM1, 18U },
3289  { X86::YMM2, 19U },
3290  { X86::YMM3, 20U },
3291  { X86::YMM4, 21U },
3292  { X86::YMM5, 22U },
3293  { X86::YMM6, 23U },
3294  { X86::YMM7, 24U },
3295  { X86::YMM8, 25U },
3296  { X86::YMM9, 26U },
3297  { X86::YMM10, 27U },
3298  { X86::YMM11, 28U },
3299  { X86::YMM12, 29U },
3300  { X86::YMM13, 30U },
3301  { X86::YMM14, 31U },
3302  { X86::YMM15, 32U },
3303  { X86::YMM16, 67U },
3304  { X86::YMM17, 68U },
3305  { X86::YMM18, 69U },
3306  { X86::YMM19, 70U },
3307  { X86::YMM20, 71U },
3308  { X86::YMM21, 72U },
3309  { X86::YMM22, 73U },
3310  { X86::YMM23, 74U },
3311  { X86::YMM24, 75U },
3312  { X86::YMM25, 76U },
3313  { X86::YMM26, 77U },
3314  { X86::YMM27, 78U },
3315  { X86::YMM28, 79U },
3316  { X86::YMM29, 80U },
3317  { X86::YMM30, 81U },
3318  { X86::YMM31, 82U },
3319  { X86::ZMM0, 17U },
3320  { X86::ZMM1, 18U },
3321  { X86::ZMM2, 19U },
3322  { X86::ZMM3, 20U },
3323  { X86::ZMM4, 21U },
3324  { X86::ZMM5, 22U },
3325  { X86::ZMM6, 23U },
3326  { X86::ZMM7, 24U },
3327  { X86::ZMM8, 25U },
3328  { X86::ZMM9, 26U },
3329  { X86::ZMM10, 27U },
3330  { X86::ZMM11, 28U },
3331  { X86::ZMM12, 29U },
3332  { X86::ZMM13, 30U },
3333  { X86::ZMM14, 31U },
3334  { X86::ZMM15, 32U },
3335  { X86::ZMM16, 67U },
3336  { X86::ZMM17, 68U },
3337  { X86::ZMM18, 69U },
3338  { X86::ZMM19, 70U },
3339  { X86::ZMM20, 71U },
3340  { X86::ZMM21, 72U },
3341  { X86::ZMM22, 73U },
3342  { X86::ZMM23, 74U },
3343  { X86::ZMM24, 75U },
3344  { X86::ZMM25, 76U },
3345  { X86::ZMM26, 77U },
3346  { X86::ZMM27, 78U },
3347  { X86::ZMM28, 79U },
3348  { X86::ZMM29, 80U },
3349  { X86::ZMM30, 81U },
3350  { X86::ZMM31, 82U },
3351};
3352extern const unsigned X86DwarfFlavour0L2DwarfSize = std::size(X86DwarfFlavour0L2Dwarf);
3353
3354extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[] = {
3355  { X86::EAX, 0U },
3356  { X86::EBP, 4U },
3357  { X86::EBX, 3U },
3358  { X86::ECX, 1U },
3359  { X86::EDI, 7U },
3360  { X86::EDX, 2U },
3361  { X86::EFLAGS, 9U },
3362  { X86::EIP, 8U },
3363  { X86::ESI, 6U },
3364  { X86::ESP, 5U },
3365  { X86::FS_BASE, -2U },
3366  { X86::GS_BASE, -2U },
3367  { X86::RAX, -2U },
3368  { X86::RBP, -2U },
3369  { X86::RBX, -2U },
3370  { X86::RCX, -2U },
3371  { X86::RDI, -2U },
3372  { X86::RDX, -2U },
3373  { X86::RFLAGS, -2U },
3374  { X86::RIP, -2U },
3375  { X86::RSI, -2U },
3376  { X86::RSP, -2U },
3377  { X86::_EFLAGS, 9U },
3378  { X86::K0, 93U },
3379  { X86::K1, 94U },
3380  { X86::K2, 95U },
3381  { X86::K3, 96U },
3382  { X86::K4, 97U },
3383  { X86::K5, 98U },
3384  { X86::K6, 99U },
3385  { X86::K7, 100U },
3386  { X86::MM0, 29U },
3387  { X86::MM1, 30U },
3388  { X86::MM2, 31U },
3389  { X86::MM3, 32U },
3390  { X86::MM4, 33U },
3391  { X86::MM5, 34U },
3392  { X86::MM6, 35U },
3393  { X86::MM7, 36U },
3394  { X86::R8, -2U },
3395  { X86::R9, -2U },
3396  { X86::R10, -2U },
3397  { X86::R11, -2U },
3398  { X86::R12, -2U },
3399  { X86::R13, -2U },
3400  { X86::R14, -2U },
3401  { X86::R15, -2U },
3402  { X86::ST0, 12U },
3403  { X86::ST1, 13U },
3404  { X86::ST2, 14U },
3405  { X86::ST3, 15U },
3406  { X86::ST4, 16U },
3407  { X86::ST5, 17U },
3408  { X86::ST6, 18U },
3409  { X86::ST7, 19U },
3410  { X86::XMM0, 21U },
3411  { X86::XMM1, 22U },
3412  { X86::XMM2, 23U },
3413  { X86::XMM3, 24U },
3414  { X86::XMM4, 25U },
3415  { X86::XMM5, 26U },
3416  { X86::XMM6, 27U },
3417  { X86::XMM7, 28U },
3418  { X86::XMM8, -2U },
3419  { X86::XMM9, -2U },
3420  { X86::XMM10, -2U },
3421  { X86::XMM11, -2U },
3422  { X86::XMM12, -2U },
3423  { X86::XMM13, -2U },
3424  { X86::XMM14, -2U },
3425  { X86::XMM15, -2U },
3426  { X86::XMM16, -2U },
3427  { X86::XMM17, -2U },
3428  { X86::XMM18, -2U },
3429  { X86::XMM19, -2U },
3430  { X86::XMM20, -2U },
3431  { X86::XMM21, -2U },
3432  { X86::XMM22, -2U },
3433  { X86::XMM23, -2U },
3434  { X86::XMM24, -2U },
3435  { X86::XMM25, -2U },
3436  { X86::XMM26, -2U },
3437  { X86::XMM27, -2U },
3438  { X86::XMM28, -2U },
3439  { X86::XMM29, -2U },
3440  { X86::XMM30, -2U },
3441  { X86::XMM31, -2U },
3442  { X86::YMM0, 21U },
3443  { X86::YMM1, 22U },
3444  { X86::YMM2, 23U },
3445  { X86::YMM3, 24U },
3446  { X86::YMM4, 25U },
3447  { X86::YMM5, 26U },
3448  { X86::YMM6, 27U },
3449  { X86::YMM7, 28U },
3450  { X86::YMM8, -2U },
3451  { X86::YMM9, -2U },
3452  { X86::YMM10, -2U },
3453  { X86::YMM11, -2U },
3454  { X86::YMM12, -2U },
3455  { X86::YMM13, -2U },
3456  { X86::YMM14, -2U },
3457  { X86::YMM15, -2U },
3458  { X86::YMM16, -2U },
3459  { X86::YMM17, -2U },
3460  { X86::YMM18, -2U },
3461  { X86::YMM19, -2U },
3462  { X86::YMM20, -2U },
3463  { X86::YMM21, -2U },
3464  { X86::YMM22, -2U },
3465  { X86::YMM23, -2U },
3466  { X86::YMM24, -2U },
3467  { X86::YMM25, -2U },
3468  { X86::YMM26, -2U },
3469  { X86::YMM27, -2U },
3470  { X86::YMM28, -2U },
3471  { X86::YMM29, -2U },
3472  { X86::YMM30, -2U },
3473  { X86::YMM31, -2U },
3474  { X86::ZMM0, 21U },
3475  { X86::ZMM1, 22U },
3476  { X86::ZMM2, 23U },
3477  { X86::ZMM3, 24U },
3478  { X86::ZMM4, 25U },
3479  { X86::ZMM5, 26U },
3480  { X86::ZMM6, 27U },
3481  { X86::ZMM7, 28U },
3482  { X86::ZMM8, -2U },
3483  { X86::ZMM9, -2U },
3484  { X86::ZMM10, -2U },
3485  { X86::ZMM11, -2U },
3486  { X86::ZMM12, -2U },
3487  { X86::ZMM13, -2U },
3488  { X86::ZMM14, -2U },
3489  { X86::ZMM15, -2U },
3490  { X86::ZMM16, -2U },
3491  { X86::ZMM17, -2U },
3492  { X86::ZMM18, -2U },
3493  { X86::ZMM19, -2U },
3494  { X86::ZMM20, -2U },
3495  { X86::ZMM21, -2U },
3496  { X86::ZMM22, -2U },
3497  { X86::ZMM23, -2U },
3498  { X86::ZMM24, -2U },
3499  { X86::ZMM25, -2U },
3500  { X86::ZMM26, -2U },
3501  { X86::ZMM27, -2U },
3502  { X86::ZMM28, -2U },
3503  { X86::ZMM29, -2U },
3504  { X86::ZMM30, -2U },
3505  { X86::ZMM31, -2U },
3506};
3507extern const unsigned X86DwarfFlavour1L2DwarfSize = std::size(X86DwarfFlavour1L2Dwarf);
3508
3509extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[] = {
3510  { X86::EAX, 0U },
3511  { X86::EBP, 5U },
3512  { X86::EBX, 3U },
3513  { X86::ECX, 1U },
3514  { X86::EDI, 7U },
3515  { X86::EDX, 2U },
3516  { X86::EFLAGS, 9U },
3517  { X86::EIP, 8U },
3518  { X86::ESI, 6U },
3519  { X86::ESP, 4U },
3520  { X86::FS_BASE, -2U },
3521  { X86::GS_BASE, -2U },
3522  { X86::RAX, -2U },
3523  { X86::RBP, -2U },
3524  { X86::RBX, -2U },
3525  { X86::RCX, -2U },
3526  { X86::RDI, -2U },
3527  { X86::RDX, -2U },
3528  { X86::RFLAGS, -2U },
3529  { X86::RIP, -2U },
3530  { X86::RSI, -2U },
3531  { X86::RSP, -2U },
3532  { X86::_EFLAGS, 9U },
3533  { X86::K0, 93U },
3534  { X86::K1, 94U },
3535  { X86::K2, 95U },
3536  { X86::K3, 96U },
3537  { X86::K4, 97U },
3538  { X86::K5, 98U },
3539  { X86::K6, 99U },
3540  { X86::K7, 100U },
3541  { X86::MM0, 29U },
3542  { X86::MM1, 30U },
3543  { X86::MM2, 31U },
3544  { X86::MM3, 32U },
3545  { X86::MM4, 33U },
3546  { X86::MM5, 34U },
3547  { X86::MM6, 35U },
3548  { X86::MM7, 36U },
3549  { X86::R8, -2U },
3550  { X86::R9, -2U },
3551  { X86::R10, -2U },
3552  { X86::R11, -2U },
3553  { X86::R12, -2U },
3554  { X86::R13, -2U },
3555  { X86::R14, -2U },
3556  { X86::R15, -2U },
3557  { X86::ST0, 11U },
3558  { X86::ST1, 12U },
3559  { X86::ST2, 13U },
3560  { X86::ST3, 14U },
3561  { X86::ST4, 15U },
3562  { X86::ST5, 16U },
3563  { X86::ST6, 17U },
3564  { X86::ST7, 18U },
3565  { X86::XMM0, 21U },
3566  { X86::XMM1, 22U },
3567  { X86::XMM2, 23U },
3568  { X86::XMM3, 24U },
3569  { X86::XMM4, 25U },
3570  { X86::XMM5, 26U },
3571  { X86::XMM6, 27U },
3572  { X86::XMM7, 28U },
3573  { X86::XMM8, -2U },
3574  { X86::XMM9, -2U },
3575  { X86::XMM10, -2U },
3576  { X86::XMM11, -2U },
3577  { X86::XMM12, -2U },
3578  { X86::XMM13, -2U },
3579  { X86::XMM14, -2U },
3580  { X86::XMM15, -2U },
3581  { X86::XMM16, -2U },
3582  { X86::XMM17, -2U },
3583  { X86::XMM18, -2U },
3584  { X86::XMM19, -2U },
3585  { X86::XMM20, -2U },
3586  { X86::XMM21, -2U },
3587  { X86::XMM22, -2U },
3588  { X86::XMM23, -2U },
3589  { X86::XMM24, -2U },
3590  { X86::XMM25, -2U },
3591  { X86::XMM26, -2U },
3592  { X86::XMM27, -2U },
3593  { X86::XMM28, -2U },
3594  { X86::XMM29, -2U },
3595  { X86::XMM30, -2U },
3596  { X86::XMM31, -2U },
3597  { X86::YMM0, 21U },
3598  { X86::YMM1, 22U },
3599  { X86::YMM2, 23U },
3600  { X86::YMM3, 24U },
3601  { X86::YMM4, 25U },
3602  { X86::YMM5, 26U },
3603  { X86::YMM6, 27U },
3604  { X86::YMM7, 28U },
3605  { X86::YMM8, -2U },
3606  { X86::YMM9, -2U },
3607  { X86::YMM10, -2U },
3608  { X86::YMM11, -2U },
3609  { X86::YMM12, -2U },
3610  { X86::YMM13, -2U },
3611  { X86::YMM14, -2U },
3612  { X86::YMM15, -2U },
3613  { X86::YMM16, -2U },
3614  { X86::YMM17, -2U },
3615  { X86::YMM18, -2U },
3616  { X86::YMM19, -2U },
3617  { X86::YMM20, -2U },
3618  { X86::YMM21, -2U },
3619  { X86::YMM22, -2U },
3620  { X86::YMM23, -2U },
3621  { X86::YMM24, -2U },
3622  { X86::YMM25, -2U },
3623  { X86::YMM26, -2U },
3624  { X86::YMM27, -2U },
3625  { X86::YMM28, -2U },
3626  { X86::YMM29, -2U },
3627  { X86::YMM30, -2U },
3628  { X86::YMM31, -2U },
3629  { X86::ZMM0, 21U },
3630  { X86::ZMM1, 22U },
3631  { X86::ZMM2, 23U },
3632  { X86::ZMM3, 24U },
3633  { X86::ZMM4, 25U },
3634  { X86::ZMM5, 26U },
3635  { X86::ZMM6, 27U },
3636  { X86::ZMM7, 28U },
3637  { X86::ZMM8, -2U },
3638  { X86::ZMM9, -2U },
3639  { X86::ZMM10, -2U },
3640  { X86::ZMM11, -2U },
3641  { X86::ZMM12, -2U },
3642  { X86::ZMM13, -2U },
3643  { X86::ZMM14, -2U },
3644  { X86::ZMM15, -2U },
3645  { X86::ZMM16, -2U },
3646  { X86::ZMM17, -2U },
3647  { X86::ZMM18, -2U },
3648  { X86::ZMM19, -2U },
3649  { X86::ZMM20, -2U },
3650  { X86::ZMM21, -2U },
3651  { X86::ZMM22, -2U },
3652  { X86::ZMM23, -2U },
3653  { X86::ZMM24, -2U },
3654  { X86::ZMM25, -2U },
3655  { X86::ZMM26, -2U },
3656  { X86::ZMM27, -2U },
3657  { X86::ZMM28, -2U },
3658  { X86::ZMM29, -2U },
3659  { X86::ZMM30, -2U },
3660  { X86::ZMM31, -2U },
3661};
3662extern const unsigned X86DwarfFlavour2L2DwarfSize = std::size(X86DwarfFlavour2L2Dwarf);
3663
3664extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[] = {
3665  { X86::EAX, -2U },
3666  { X86::EBP, -2U },
3667  { X86::EBX, -2U },
3668  { X86::ECX, -2U },
3669  { X86::EDI, -2U },
3670  { X86::EDX, -2U },
3671  { X86::EFLAGS, 49U },
3672  { X86::EIP, -2U },
3673  { X86::ESI, -2U },
3674  { X86::ESP, -2U },
3675  { X86::FS_BASE, 58U },
3676  { X86::GS_BASE, 59U },
3677  { X86::RAX, 0U },
3678  { X86::RBP, 6U },
3679  { X86::RBX, 3U },
3680  { X86::RCX, 2U },
3681  { X86::RDI, 5U },
3682  { X86::RDX, 1U },
3683  { X86::RFLAGS, 49U },
3684  { X86::RIP, 16U },
3685  { X86::RSI, 4U },
3686  { X86::RSP, 7U },
3687  { X86::_EFLAGS, 49U },
3688  { X86::K0, 118U },
3689  { X86::K1, 119U },
3690  { X86::K2, 120U },
3691  { X86::K3, 121U },
3692  { X86::K4, 122U },
3693  { X86::K5, 123U },
3694  { X86::K6, 124U },
3695  { X86::K7, 125U },
3696  { X86::MM0, 41U },
3697  { X86::MM1, 42U },
3698  { X86::MM2, 43U },
3699  { X86::MM3, 44U },
3700  { X86::MM4, 45U },
3701  { X86::MM5, 46U },
3702  { X86::MM6, 47U },
3703  { X86::MM7, 48U },
3704  { X86::R8, 8U },
3705  { X86::R9, 9U },
3706  { X86::R10, 10U },
3707  { X86::R11, 11U },
3708  { X86::R12, 12U },
3709  { X86::R13, 13U },
3710  { X86::R14, 14U },
3711  { X86::R15, 15U },
3712  { X86::ST0, 33U },
3713  { X86::ST1, 34U },
3714  { X86::ST2, 35U },
3715  { X86::ST3, 36U },
3716  { X86::ST4, 37U },
3717  { X86::ST5, 38U },
3718  { X86::ST6, 39U },
3719  { X86::ST7, 40U },
3720  { X86::XMM0, 17U },
3721  { X86::XMM1, 18U },
3722  { X86::XMM2, 19U },
3723  { X86::XMM3, 20U },
3724  { X86::XMM4, 21U },
3725  { X86::XMM5, 22U },
3726  { X86::XMM6, 23U },
3727  { X86::XMM7, 24U },
3728  { X86::XMM8, 25U },
3729  { X86::XMM9, 26U },
3730  { X86::XMM10, 27U },
3731  { X86::XMM11, 28U },
3732  { X86::XMM12, 29U },
3733  { X86::XMM13, 30U },
3734  { X86::XMM14, 31U },
3735  { X86::XMM15, 32U },
3736  { X86::XMM16, 67U },
3737  { X86::XMM17, 68U },
3738  { X86::XMM18, 69U },
3739  { X86::XMM19, 70U },
3740  { X86::XMM20, 71U },
3741  { X86::XMM21, 72U },
3742  { X86::XMM22, 73U },
3743  { X86::XMM23, 74U },
3744  { X86::XMM24, 75U },
3745  { X86::XMM25, 76U },
3746  { X86::XMM26, 77U },
3747  { X86::XMM27, 78U },
3748  { X86::XMM28, 79U },
3749  { X86::XMM29, 80U },
3750  { X86::XMM30, 81U },
3751  { X86::XMM31, 82U },
3752  { X86::YMM0, 17U },
3753  { X86::YMM1, 18U },
3754  { X86::YMM2, 19U },
3755  { X86::YMM3, 20U },
3756  { X86::YMM4, 21U },
3757  { X86::YMM5, 22U },
3758  { X86::YMM6, 23U },
3759  { X86::YMM7, 24U },
3760  { X86::YMM8, 25U },
3761  { X86::YMM9, 26U },
3762  { X86::YMM10, 27U },
3763  { X86::YMM11, 28U },
3764  { X86::YMM12, 29U },
3765  { X86::YMM13, 30U },
3766  { X86::YMM14, 31U },
3767  { X86::YMM15, 32U },
3768  { X86::YMM16, 67U },
3769  { X86::YMM17, 68U },
3770  { X86::YMM18, 69U },
3771  { X86::YMM19, 70U },
3772  { X86::YMM20, 71U },
3773  { X86::YMM21, 72U },
3774  { X86::YMM22, 73U },
3775  { X86::YMM23, 74U },
3776  { X86::YMM24, 75U },
3777  { X86::YMM25, 76U },
3778  { X86::YMM26, 77U },
3779  { X86::YMM27, 78U },
3780  { X86::YMM28, 79U },
3781  { X86::YMM29, 80U },
3782  { X86::YMM30, 81U },
3783  { X86::YMM31, 82U },
3784  { X86::ZMM0, 17U },
3785  { X86::ZMM1, 18U },
3786  { X86::ZMM2, 19U },
3787  { X86::ZMM3, 20U },
3788  { X86::ZMM4, 21U },
3789  { X86::ZMM5, 22U },
3790  { X86::ZMM6, 23U },
3791  { X86::ZMM7, 24U },
3792  { X86::ZMM8, 25U },
3793  { X86::ZMM9, 26U },
3794  { X86::ZMM10, 27U },
3795  { X86::ZMM11, 28U },
3796  { X86::ZMM12, 29U },
3797  { X86::ZMM13, 30U },
3798  { X86::ZMM14, 31U },
3799  { X86::ZMM15, 32U },
3800  { X86::ZMM16, 67U },
3801  { X86::ZMM17, 68U },
3802  { X86::ZMM18, 69U },
3803  { X86::ZMM19, 70U },
3804  { X86::ZMM20, 71U },
3805  { X86::ZMM21, 72U },
3806  { X86::ZMM22, 73U },
3807  { X86::ZMM23, 74U },
3808  { X86::ZMM24, 75U },
3809  { X86::ZMM25, 76U },
3810  { X86::ZMM26, 77U },
3811  { X86::ZMM27, 78U },
3812  { X86::ZMM28, 79U },
3813  { X86::ZMM29, 80U },
3814  { X86::ZMM30, 81U },
3815  { X86::ZMM31, 82U },
3816};
3817extern const unsigned X86EHFlavour0L2DwarfSize = std::size(X86EHFlavour0L2Dwarf);
3818
3819extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[] = {
3820  { X86::EAX, 0U },
3821  { X86::EBP, 4U },
3822  { X86::EBX, 3U },
3823  { X86::ECX, 1U },
3824  { X86::EDI, 7U },
3825  { X86::EDX, 2U },
3826  { X86::EFLAGS, 9U },
3827  { X86::EIP, 8U },
3828  { X86::ESI, 6U },
3829  { X86::ESP, 5U },
3830  { X86::FS_BASE, -2U },
3831  { X86::GS_BASE, -2U },
3832  { X86::RAX, -2U },
3833  { X86::RBP, -2U },
3834  { X86::RBX, -2U },
3835  { X86::RCX, -2U },
3836  { X86::RDI, -2U },
3837  { X86::RDX, -2U },
3838  { X86::RFLAGS, -2U },
3839  { X86::RIP, -2U },
3840  { X86::RSI, -2U },
3841  { X86::RSP, -2U },
3842  { X86::_EFLAGS, 9U },
3843  { X86::K0, 93U },
3844  { X86::K1, 94U },
3845  { X86::K2, 95U },
3846  { X86::K3, 96U },
3847  { X86::K4, 97U },
3848  { X86::K5, 98U },
3849  { X86::K6, 99U },
3850  { X86::K7, 100U },
3851  { X86::MM0, 29U },
3852  { X86::MM1, 30U },
3853  { X86::MM2, 31U },
3854  { X86::MM3, 32U },
3855  { X86::MM4, 33U },
3856  { X86::MM5, 34U },
3857  { X86::MM6, 35U },
3858  { X86::MM7, 36U },
3859  { X86::R8, -2U },
3860  { X86::R9, -2U },
3861  { X86::R10, -2U },
3862  { X86::R11, -2U },
3863  { X86::R12, -2U },
3864  { X86::R13, -2U },
3865  { X86::R14, -2U },
3866  { X86::R15, -2U },
3867  { X86::ST0, 12U },
3868  { X86::ST1, 13U },
3869  { X86::ST2, 14U },
3870  { X86::ST3, 15U },
3871  { X86::ST4, 16U },
3872  { X86::ST5, 17U },
3873  { X86::ST6, 18U },
3874  { X86::ST7, 19U },
3875  { X86::XMM0, 21U },
3876  { X86::XMM1, 22U },
3877  { X86::XMM2, 23U },
3878  { X86::XMM3, 24U },
3879  { X86::XMM4, 25U },
3880  { X86::XMM5, 26U },
3881  { X86::XMM6, 27U },
3882  { X86::XMM7, 28U },
3883  { X86::XMM8, -2U },
3884  { X86::XMM9, -2U },
3885  { X86::XMM10, -2U },
3886  { X86::XMM11, -2U },
3887  { X86::XMM12, -2U },
3888  { X86::XMM13, -2U },
3889  { X86::XMM14, -2U },
3890  { X86::XMM15, -2U },
3891  { X86::XMM16, -2U },
3892  { X86::XMM17, -2U },
3893  { X86::XMM18, -2U },
3894  { X86::XMM19, -2U },
3895  { X86::XMM20, -2U },
3896  { X86::XMM21, -2U },
3897  { X86::XMM22, -2U },
3898  { X86::XMM23, -2U },
3899  { X86::XMM24, -2U },
3900  { X86::XMM25, -2U },
3901  { X86::XMM26, -2U },
3902  { X86::XMM27, -2U },
3903  { X86::XMM28, -2U },
3904  { X86::XMM29, -2U },
3905  { X86::XMM30, -2U },
3906  { X86::XMM31, -2U },
3907  { X86::YMM0, 21U },
3908  { X86::YMM1, 22U },
3909  { X86::YMM2, 23U },
3910  { X86::YMM3, 24U },
3911  { X86::YMM4, 25U },
3912  { X86::YMM5, 26U },
3913  { X86::YMM6, 27U },
3914  { X86::YMM7, 28U },
3915  { X86::YMM8, -2U },
3916  { X86::YMM9, -2U },
3917  { X86::YMM10, -2U },
3918  { X86::YMM11, -2U },
3919  { X86::YMM12, -2U },
3920  { X86::YMM13, -2U },
3921  { X86::YMM14, -2U },
3922  { X86::YMM15, -2U },
3923  { X86::YMM16, -2U },
3924  { X86::YMM17, -2U },
3925  { X86::YMM18, -2U },
3926  { X86::YMM19, -2U },
3927  { X86::YMM20, -2U },
3928  { X86::YMM21, -2U },
3929  { X86::YMM22, -2U },
3930  { X86::YMM23, -2U },
3931  { X86::YMM24, -2U },
3932  { X86::YMM25, -2U },
3933  { X86::YMM26, -2U },
3934  { X86::YMM27, -2U },
3935  { X86::YMM28, -2U },
3936  { X86::YMM29, -2U },
3937  { X86::YMM30, -2U },
3938  { X86::YMM31, -2U },
3939  { X86::ZMM0, 21U },
3940  { X86::ZMM1, 22U },
3941  { X86::ZMM2, 23U },
3942  { X86::ZMM3, 24U },
3943  { X86::ZMM4, 25U },
3944  { X86::ZMM5, 26U },
3945  { X86::ZMM6, 27U },
3946  { X86::ZMM7, 28U },
3947  { X86::ZMM8, -2U },
3948  { X86::ZMM9, -2U },
3949  { X86::ZMM10, -2U },
3950  { X86::ZMM11, -2U },
3951  { X86::ZMM12, -2U },
3952  { X86::ZMM13, -2U },
3953  { X86::ZMM14, -2U },
3954  { X86::ZMM15, -2U },
3955  { X86::ZMM16, -2U },
3956  { X86::ZMM17, -2U },
3957  { X86::ZMM18, -2U },
3958  { X86::ZMM19, -2U },
3959  { X86::ZMM20, -2U },
3960  { X86::ZMM21, -2U },
3961  { X86::ZMM22, -2U },
3962  { X86::ZMM23, -2U },
3963  { X86::ZMM24, -2U },
3964  { X86::ZMM25, -2U },
3965  { X86::ZMM26, -2U },
3966  { X86::ZMM27, -2U },
3967  { X86::ZMM28, -2U },
3968  { X86::ZMM29, -2U },
3969  { X86::ZMM30, -2U },
3970  { X86::ZMM31, -2U },
3971};
3972extern const unsigned X86EHFlavour1L2DwarfSize = std::size(X86EHFlavour1L2Dwarf);
3973
3974extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[] = {
3975  { X86::EAX, 0U },
3976  { X86::EBP, 5U },
3977  { X86::EBX, 3U },
3978  { X86::ECX, 1U },
3979  { X86::EDI, 7U },
3980  { X86::EDX, 2U },
3981  { X86::EFLAGS, 9U },
3982  { X86::EIP, 8U },
3983  { X86::ESI, 6U },
3984  { X86::ESP, 4U },
3985  { X86::FS_BASE, -2U },
3986  { X86::GS_BASE, -2U },
3987  { X86::RAX, -2U },
3988  { X86::RBP, -2U },
3989  { X86::RBX, -2U },
3990  { X86::RCX, -2U },
3991  { X86::RDI, -2U },
3992  { X86::RDX, -2U },
3993  { X86::RFLAGS, -2U },
3994  { X86::RIP, -2U },
3995  { X86::RSI, -2U },
3996  { X86::RSP, -2U },
3997  { X86::_EFLAGS, 9U },
3998  { X86::K0, 93U },
3999  { X86::K1, 94U },
4000  { X86::K2, 95U },
4001  { X86::K3, 96U },
4002  { X86::K4, 97U },
4003  { X86::K5, 98U },
4004  { X86::K6, 99U },
4005  { X86::K7, 100U },
4006  { X86::MM0, 29U },
4007  { X86::MM1, 30U },
4008  { X86::MM2, 31U },
4009  { X86::MM3, 32U },
4010  { X86::MM4, 33U },
4011  { X86::MM5, 34U },
4012  { X86::MM6, 35U },
4013  { X86::MM7, 36U },
4014  { X86::R8, -2U },
4015  { X86::R9, -2U },
4016  { X86::R10, -2U },
4017  { X86::R11, -2U },
4018  { X86::R12, -2U },
4019  { X86::R13, -2U },
4020  { X86::R14, -2U },
4021  { X86::R15, -2U },
4022  { X86::ST0, 11U },
4023  { X86::ST1, 12U },
4024  { X86::ST2, 13U },
4025  { X86::ST3, 14U },
4026  { X86::ST4, 15U },
4027  { X86::ST5, 16U },
4028  { X86::ST6, 17U },
4029  { X86::ST7, 18U },
4030  { X86::XMM0, 21U },
4031  { X86::XMM1, 22U },
4032  { X86::XMM2, 23U },
4033  { X86::XMM3, 24U },
4034  { X86::XMM4, 25U },
4035  { X86::XMM5, 26U },
4036  { X86::XMM6, 27U },
4037  { X86::XMM7, 28U },
4038  { X86::XMM8, -2U },
4039  { X86::XMM9, -2U },
4040  { X86::XMM10, -2U },
4041  { X86::XMM11, -2U },
4042  { X86::XMM12, -2U },
4043  { X86::XMM13, -2U },
4044  { X86::XMM14, -2U },
4045  { X86::XMM15, -2U },
4046  { X86::XMM16, -2U },
4047  { X86::XMM17, -2U },
4048  { X86::XMM18, -2U },
4049  { X86::XMM19, -2U },
4050  { X86::XMM20, -2U },
4051  { X86::XMM21, -2U },
4052  { X86::XMM22, -2U },
4053  { X86::XMM23, -2U },
4054  { X86::XMM24, -2U },
4055  { X86::XMM25, -2U },
4056  { X86::XMM26, -2U },
4057  { X86::XMM27, -2U },
4058  { X86::XMM28, -2U },
4059  { X86::XMM29, -2U },
4060  { X86::XMM30, -2U },
4061  { X86::XMM31, -2U },
4062  { X86::YMM0, 21U },
4063  { X86::YMM1, 22U },
4064  { X86::YMM2, 23U },
4065  { X86::YMM3, 24U },
4066  { X86::YMM4, 25U },
4067  { X86::YMM5, 26U },
4068  { X86::YMM6, 27U },
4069  { X86::YMM7, 28U },
4070  { X86::YMM8, -2U },
4071  { X86::YMM9, -2U },
4072  { X86::YMM10, -2U },
4073  { X86::YMM11, -2U },
4074  { X86::YMM12, -2U },
4075  { X86::YMM13, -2U },
4076  { X86::YMM14, -2U },
4077  { X86::YMM15, -2U },
4078  { X86::YMM16, -2U },
4079  { X86::YMM17, -2U },
4080  { X86::YMM18, -2U },
4081  { X86::YMM19, -2U },
4082  { X86::YMM20, -2U },
4083  { X86::YMM21, -2U },
4084  { X86::YMM22, -2U },
4085  { X86::YMM23, -2U },
4086  { X86::YMM24, -2U },
4087  { X86::YMM25, -2U },
4088  { X86::YMM26, -2U },
4089  { X86::YMM27, -2U },
4090  { X86::YMM28, -2U },
4091  { X86::YMM29, -2U },
4092  { X86::YMM30, -2U },
4093  { X86::YMM31, -2U },
4094  { X86::ZMM0, 21U },
4095  { X86::ZMM1, 22U },
4096  { X86::ZMM2, 23U },
4097  { X86::ZMM3, 24U },
4098  { X86::ZMM4, 25U },
4099  { X86::ZMM5, 26U },
4100  { X86::ZMM6, 27U },
4101  { X86::ZMM7, 28U },
4102  { X86::ZMM8, -2U },
4103  { X86::ZMM9, -2U },
4104  { X86::ZMM10, -2U },
4105  { X86::ZMM11, -2U },
4106  { X86::ZMM12, -2U },
4107  { X86::ZMM13, -2U },
4108  { X86::ZMM14, -2U },
4109  { X86::ZMM15, -2U },
4110  { X86::ZMM16, -2U },
4111  { X86::ZMM17, -2U },
4112  { X86::ZMM18, -2U },
4113  { X86::ZMM19, -2U },
4114  { X86::ZMM20, -2U },
4115  { X86::ZMM21, -2U },
4116  { X86::ZMM22, -2U },
4117  { X86::ZMM23, -2U },
4118  { X86::ZMM24, -2U },
4119  { X86::ZMM25, -2U },
4120  { X86::ZMM26, -2U },
4121  { X86::ZMM27, -2U },
4122  { X86::ZMM28, -2U },
4123  { X86::ZMM29, -2U },
4124  { X86::ZMM30, -2U },
4125  { X86::ZMM31, -2U },
4126};
4127extern const unsigned X86EHFlavour2L2DwarfSize = std::size(X86EHFlavour2L2Dwarf);
4128
4129extern const uint16_t X86RegEncodingTable[] = {
4130  0,
4131  4,
4132  0,
4133  0,
4134  7,
4135  3,
4136  5,
4137  65535,
4138  5,
4139  3,
4140  5,
4141  1,
4142  1,
4143  1,
4144  0,
4145  6,
4146  7,
4147  65535,
4148  7,
4149  2,
4150  3,
4151  2,
4152  0,
4153  5,
4154  3,
4155  1,
4156  7,
4157  2,
4158  0,
4159  0,
4160  4,
4161  0,
4162  6,
4163  4,
4164  0,
4165  0,
4166  4,
4167  0,
4168  5,
4169  0,
4170  65535,
4171  65535,
4172  65535,
4173  65535,
4174  65535,
4175  65535,
4176  65535,
4177  65535,
4178  65535,
4179  0,
4180  0,
4181  0,
4182  5,
4183  3,
4184  1,
4185  7,
4186  2,
4187  0,
4188  0,
4189  4,
4190  6,
4191  4,
4192  6,
4193  65535,
4194  6,
4195  4,
4196  65535,
4197  4,
4198  2,
4199  0,
4200  0,
4201  0,
4202  0,
4203  1,
4204  2,
4205  3,
4206  4,
4207  5,
4208  6,
4209  7,
4210  8,
4211  9,
4212  10,
4213  11,
4214  12,
4215  13,
4216  14,
4217  15,
4218  0,
4219  1,
4220  2,
4221  3,
4222  4,
4223  5,
4224  6,
4225  7,
4226  8,
4227  9,
4228  10,
4229  11,
4230  12,
4231  13,
4232  14,
4233  15,
4234  0,
4235  0,
4236  0,
4237  0,
4238  0,
4239  0,
4240  0,
4241  0,
4242  0,
4243  1,
4244  2,
4245  3,
4246  4,
4247  5,
4248  6,
4249  7,
4250  0,
4251  1,
4252  2,
4253  3,
4254  4,
4255  5,
4256  6,
4257  7,
4258  8,
4259  9,
4260  10,
4261  11,
4262  12,
4263  13,
4264  14,
4265  15,
4266  0,
4267  1,
4268  2,
4269  3,
4270  4,
4271  5,
4272  6,
4273  7,
4274  0,
4275  1,
4276  2,
4277  3,
4278  4,
4279  5,
4280  6,
4281  7,
4282  0,
4283  1,
4284  2,
4285  3,
4286  4,
4287  5,
4288  6,
4289  7,
4290  8,
4291  9,
4292  10,
4293  11,
4294  12,
4295  13,
4296  14,
4297  15,
4298  16,
4299  17,
4300  18,
4301  19,
4302  20,
4303  21,
4304  22,
4305  23,
4306  24,
4307  25,
4308  26,
4309  27,
4310  28,
4311  29,
4312  30,
4313  31,
4314  0,
4315  1,
4316  2,
4317  3,
4318  4,
4319  5,
4320  6,
4321  7,
4322  8,
4323  9,
4324  10,
4325  11,
4326  12,
4327  13,
4328  14,
4329  15,
4330  16,
4331  17,
4332  18,
4333  19,
4334  20,
4335  21,
4336  22,
4337  23,
4338  24,
4339  25,
4340  26,
4341  27,
4342  28,
4343  29,
4344  30,
4345  31,
4346  0,
4347  1,
4348  2,
4349  3,
4350  4,
4351  5,
4352  6,
4353  7,
4354  8,
4355  9,
4356  10,
4357  11,
4358  12,
4359  13,
4360  14,
4361  15,
4362  16,
4363  17,
4364  18,
4365  19,
4366  20,
4367  21,
4368  22,
4369  23,
4370  24,
4371  25,
4372  26,
4373  27,
4374  28,
4375  29,
4376  30,
4377  31,
4378  8,
4379  9,
4380  10,
4381  11,
4382  12,
4383  13,
4384  14,
4385  15,
4386  65535,
4387  65535,
4388  65535,
4389  65535,
4390  65535,
4391  65535,
4392  65535,
4393  65535,
4394  8,
4395  9,
4396  10,
4397  11,
4398  12,
4399  13,
4400  14,
4401  15,
4402  8,
4403  9,
4404  10,
4405  11,
4406  12,
4407  13,
4408  14,
4409  15,
4410  65535,
4411  65535,
4412  65535,
4413  65535,
4414  65535,
4415  65535,
4416  65535,
4417  65535,
4418  0,
4419  2,
4420  4,
4421  6,
4422};
4423static inline void InitX86MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
4424  RI->InitMCRegisterInfo(X86RegDesc, 292, RA, PC, X86MCRegisterClasses, 123, X86RegUnitRoots, 173, X86RegDiffLists, X86LaneMaskLists, X86RegStrings, X86RegClassStrings, X86SubRegIdxLists, 11,
4425X86SubRegIdxRanges, X86RegEncodingTable);
4426
4427  switch (DwarfFlavour) {
4428  default:
4429    llvm_unreachable("Unknown DWARF flavour");
4430  case 0:
4431    RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour0Dwarf2L, X86DwarfFlavour0Dwarf2LSize, false);
4432    break;
4433  case 1:
4434    RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour1Dwarf2L, X86DwarfFlavour1Dwarf2LSize, false);
4435    break;
4436  case 2:
4437    RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour2Dwarf2L, X86DwarfFlavour2Dwarf2LSize, false);
4438    break;
4439  }
4440  switch (EHFlavour) {
4441  default:
4442    llvm_unreachable("Unknown DWARF flavour");
4443  case 0:
4444    RI->mapDwarfRegsToLLVMRegs(X86EHFlavour0Dwarf2L, X86EHFlavour0Dwarf2LSize, true);
4445    break;
4446  case 1:
4447    RI->mapDwarfRegsToLLVMRegs(X86EHFlavour1Dwarf2L, X86EHFlavour1Dwarf2LSize, true);
4448    break;
4449  case 2:
4450    RI->mapDwarfRegsToLLVMRegs(X86EHFlavour2Dwarf2L, X86EHFlavour2Dwarf2LSize, true);
4451    break;
4452  }
4453  switch (DwarfFlavour) {
4454  default:
4455    llvm_unreachable("Unknown DWARF flavour");
4456  case 0:
4457    RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour0L2Dwarf, X86DwarfFlavour0L2DwarfSize, false);
4458    break;
4459  case 1:
4460    RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour1L2Dwarf, X86DwarfFlavour1L2DwarfSize, false);
4461    break;
4462  case 2:
4463    RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour2L2Dwarf, X86DwarfFlavour2L2DwarfSize, false);
4464    break;
4465  }
4466  switch (EHFlavour) {
4467  default:
4468    llvm_unreachable("Unknown DWARF flavour");
4469  case 0:
4470    RI->mapLLVMRegsToDwarfRegs(X86EHFlavour0L2Dwarf, X86EHFlavour0L2DwarfSize, true);
4471    break;
4472  case 1:
4473    RI->mapLLVMRegsToDwarfRegs(X86EHFlavour1L2Dwarf, X86EHFlavour1L2DwarfSize, true);
4474    break;
4475  case 2:
4476    RI->mapLLVMRegsToDwarfRegs(X86EHFlavour2L2Dwarf, X86EHFlavour2L2DwarfSize, true);
4477    break;
4478  }
4479}
4480
4481} // end namespace llvm
4482
4483#endif // GET_REGINFO_MC_DESC
4484
4485/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
4486|*                                                                            *|
4487|* Register Information Header Fragment                                       *|
4488|*                                                                            *|
4489|* Automatically generated file, do not edit!                                 *|
4490|*                                                                            *|
4491\*===----------------------------------------------------------------------===*/
4492
4493
4494#ifdef GET_REGINFO_HEADER
4495#undef GET_REGINFO_HEADER
4496
4497#include "llvm/CodeGen/TargetRegisterInfo.h"
4498
4499namespace llvm {
4500
4501class X86FrameLowering;
4502
4503struct X86GenRegisterInfo : public TargetRegisterInfo {
4504  explicit X86GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
4505      unsigned PC = 0, unsigned HwMode = 0);
4506  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
4507  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
4508  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
4509  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
4510  const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
4511  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
4512  unsigned getRegUnitWeight(unsigned RegUnit) const override;
4513  unsigned getNumRegPressureSets() const override;
4514  const char *getRegPressureSetName(unsigned Idx) const override;
4515  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
4516  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
4517  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
4518  ArrayRef<const char *> getRegMaskNames() const override;
4519  ArrayRef<const uint32_t *> getRegMasks() const override;
4520  bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
4521  bool isFixedRegister(const MachineFunction &, MCRegister) const override;
4522  bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
4523  bool isConstantPhysReg(MCRegister PhysReg) const override final;
4524  /// Devirtualized TargetFrameLowering.
4525  static const X86FrameLowering *getFrameLowering(
4526      const MachineFunction &MF);
4527};
4528
4529namespace X86 { // Register classes
4530  extern const TargetRegisterClass GR8RegClass;
4531  extern const TargetRegisterClass GRH8RegClass;
4532  extern const TargetRegisterClass GR8_NOREXRegClass;
4533  extern const TargetRegisterClass GR8_ABCD_HRegClass;
4534  extern const TargetRegisterClass GR8_ABCD_LRegClass;
4535  extern const TargetRegisterClass GRH16RegClass;
4536  extern const TargetRegisterClass GR16RegClass;
4537  extern const TargetRegisterClass GR16_NOREXRegClass;
4538  extern const TargetRegisterClass VK1RegClass;
4539  extern const TargetRegisterClass VK16RegClass;
4540  extern const TargetRegisterClass VK2RegClass;
4541  extern const TargetRegisterClass VK4RegClass;
4542  extern const TargetRegisterClass VK8RegClass;
4543  extern const TargetRegisterClass VK16WMRegClass;
4544  extern const TargetRegisterClass VK1WMRegClass;
4545  extern const TargetRegisterClass VK2WMRegClass;
4546  extern const TargetRegisterClass VK4WMRegClass;
4547  extern const TargetRegisterClass VK8WMRegClass;
4548  extern const TargetRegisterClass SEGMENT_REGRegClass;
4549  extern const TargetRegisterClass GR16_ABCDRegClass;
4550  extern const TargetRegisterClass FPCCRRegClass;
4551  extern const TargetRegisterClass FR16XRegClass;
4552  extern const TargetRegisterClass FR16RegClass;
4553  extern const TargetRegisterClass VK16PAIRRegClass;
4554  extern const TargetRegisterClass VK1PAIRRegClass;
4555  extern const TargetRegisterClass VK2PAIRRegClass;
4556  extern const TargetRegisterClass VK4PAIRRegClass;
4557  extern const TargetRegisterClass VK8PAIRRegClass;
4558  extern const TargetRegisterClass VK16PAIR_with_sub_mask_0_in_VK16WMRegClass;
4559  extern const TargetRegisterClass FR32XRegClass;
4560  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass;
4561  extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass;
4562  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass;
4563  extern const TargetRegisterClass DEBUG_REGRegClass;
4564  extern const TargetRegisterClass FR32RegClass;
4565  extern const TargetRegisterClass GR32RegClass;
4566  extern const TargetRegisterClass GR32_NOSPRegClass;
4567  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass;
4568  extern const TargetRegisterClass GR32_NOREXRegClass;
4569  extern const TargetRegisterClass VK32RegClass;
4570  extern const TargetRegisterClass GR32_NOREX_NOSPRegClass;
4571  extern const TargetRegisterClass RFP32RegClass;
4572  extern const TargetRegisterClass VK32WMRegClass;
4573  extern const TargetRegisterClass GR32_ABCDRegClass;
4574  extern const TargetRegisterClass GR32_TCRegClass;
4575  extern const TargetRegisterClass GR32_ABCD_and_GR32_TCRegClass;
4576  extern const TargetRegisterClass GR32_ADRegClass;
4577  extern const TargetRegisterClass GR32_BPSPRegClass;
4578  extern const TargetRegisterClass GR32_BSIRegClass;
4579  extern const TargetRegisterClass GR32_CBRegClass;
4580  extern const TargetRegisterClass GR32_DCRegClass;
4581  extern const TargetRegisterClass GR32_DIBPRegClass;
4582  extern const TargetRegisterClass GR32_SIDIRegClass;
4583  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass;
4584  extern const TargetRegisterClass CCRRegClass;
4585  extern const TargetRegisterClass DFCCRRegClass;
4586  extern const TargetRegisterClass GR32_ABCD_and_GR32_BSIRegClass;
4587  extern const TargetRegisterClass GR32_AD_and_GR32_DCRegClass;
4588  extern const TargetRegisterClass GR32_BPSP_and_GR32_DIBPRegClass;
4589  extern const TargetRegisterClass GR32_BPSP_and_GR32_TCRegClass;
4590  extern const TargetRegisterClass GR32_BSI_and_GR32_SIDIRegClass;
4591  extern const TargetRegisterClass GR32_CB_and_GR32_DCRegClass;
4592  extern const TargetRegisterClass GR32_DIBP_and_GR32_SIDIRegClass;
4593  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass;
4594  extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass;
4595  extern const TargetRegisterClass RFP64RegClass;
4596  extern const TargetRegisterClass FR64XRegClass;
4597  extern const TargetRegisterClass GR64RegClass;
4598  extern const TargetRegisterClass CONTROL_REGRegClass;
4599  extern const TargetRegisterClass FR64RegClass;
4600  extern const TargetRegisterClass GR64_with_sub_8bitRegClass;
4601  extern const TargetRegisterClass GR64_NOSPRegClass;
4602  extern const TargetRegisterClass GR64PLTSafeRegClass;
4603  extern const TargetRegisterClass GR64_TCRegClass;
4604  extern const TargetRegisterClass GR64_NOREXRegClass;
4605  extern const TargetRegisterClass GR64_TCW64RegClass;
4606  extern const TargetRegisterClass GR64_TC_with_sub_8bitRegClass;
4607  extern const TargetRegisterClass GR64_NOSP_and_GR64_TCRegClass;
4608  extern const TargetRegisterClass GR64_TCW64_with_sub_8bitRegClass;
4609  extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass;
4610  extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass;
4611  extern const TargetRegisterClass VK64RegClass;
4612  extern const TargetRegisterClass VR64RegClass;
4613  extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCRegClass;
4614  extern const TargetRegisterClass GR64_NOREX_NOSPRegClass;
4615  extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass;
4616  extern const TargetRegisterClass GR64_NOSP_and_GR64_TCW64RegClass;
4617  extern const TargetRegisterClass GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass;
4618  extern const TargetRegisterClass VK64WMRegClass;
4619  extern const TargetRegisterClass GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass;
4620  extern const TargetRegisterClass GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass;
4621  extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCW64RegClass;
4622  extern const TargetRegisterClass GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass;
4623  extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass;
4624  extern const TargetRegisterClass GR64_ABCDRegClass;
4625  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass;
4626  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass;
4627  extern const TargetRegisterClass GR64_ADRegClass;
4628  extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass;
4629  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSPRegClass;
4630  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSIRegClass;
4631  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CBRegClass;
4632  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DCRegClass;
4633  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBPRegClass;
4634  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_SIDIRegClass;
4635  extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass;
4636  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass;
4637  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClass;
4638  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass;
4639  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass;
4640  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass;
4641  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClass;
4642  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass;
4643  extern const TargetRegisterClass RSTRegClass;
4644  extern const TargetRegisterClass RFP80RegClass;
4645  extern const TargetRegisterClass RFP80_7RegClass;
4646  extern const TargetRegisterClass VR128XRegClass;
4647  extern const TargetRegisterClass VR128RegClass;
4648  extern const TargetRegisterClass VR256XRegClass;
4649  extern const TargetRegisterClass VR256RegClass;
4650  extern const TargetRegisterClass VR512RegClass;
4651  extern const TargetRegisterClass VR512_0_15RegClass;
4652  extern const TargetRegisterClass TILERegClass;
4653} // end namespace X86
4654
4655} // end namespace llvm
4656
4657#endif // GET_REGINFO_HEADER
4658
4659/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
4660|*                                                                            *|
4661|* Target Register and Register Classes Information                           *|
4662|*                                                                            *|
4663|* Automatically generated file, do not edit!                                 *|
4664|*                                                                            *|
4665\*===----------------------------------------------------------------------===*/
4666
4667
4668#ifdef GET_REGINFO_TARGET_DESC
4669#undef GET_REGINFO_TARGET_DESC
4670
4671namespace llvm {
4672
4673extern const MCRegisterClass X86MCRegisterClasses[];
4674
4675static const MVT::SimpleValueType VTLists[] = {
4676  /* 0 */ MVT::i8, MVT::Other,
4677  /* 2 */ MVT::i16, MVT::Other,
4678  /* 4 */ MVT::i32, MVT::Other,
4679  /* 6 */ MVT::i64, MVT::Other,
4680  /* 8 */ MVT::f16, MVT::Other,
4681  /* 10 */ MVT::f80, MVT::f64, MVT::f32, MVT::Other,
4682  /* 14 */ MVT::f64, MVT::Other,
4683  /* 16 */ MVT::f80, MVT::Other,
4684  /* 18 */ MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::v8bf16, MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::f128, MVT::Other,
4685  /* 28 */ MVT::v1i1, MVT::Other,
4686  /* 30 */ MVT::v2i1, MVT::Other,
4687  /* 32 */ MVT::v4i1, MVT::Other,
4688  /* 34 */ MVT::v8i1, MVT::Other,
4689  /* 36 */ MVT::v16i1, MVT::Other,
4690  /* 38 */ MVT::v32i1, MVT::Other,
4691  /* 40 */ MVT::v64i1, MVT::Other,
4692  /* 42 */ MVT::v8f32, MVT::v4f64, MVT::v16f16, MVT::v16bf16, MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::Other,
4693  /* 51 */ MVT::v16f32, MVT::v8f64, MVT::v32f16, MVT::v32bf16, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
4694  /* 60 */ MVT::v16f32, MVT::v8f64, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
4695  /* 67 */ MVT::x86mmx, MVT::Other,
4696  /* 69 */ MVT::Untyped, MVT::Other,
4697  /* 71 */ MVT::x86amx, MVT::Other,
4698};
4699
4700static const char *SubRegIndexNameTable[] = { "sub_8bit", "sub_8bit_hi", "sub_8bit_hi_phony", "sub_16bit", "sub_16bit_hi", "sub_32bit", "sub_mask_0", "sub_mask_1", "sub_xmm", "sub_ymm", "" };
4701
4702
4703static const LaneBitmask SubRegIndexLaneMaskTable[] = {
4704  LaneBitmask::getAll(),
4705  LaneBitmask(0x0000000000000001), // sub_8bit
4706  LaneBitmask(0x0000000000000002), // sub_8bit_hi
4707  LaneBitmask(0x0000000000000004), // sub_8bit_hi_phony
4708  LaneBitmask(0x0000000000000007), // sub_16bit
4709  LaneBitmask(0x0000000000000008), // sub_16bit_hi
4710  LaneBitmask(0x000000000000000F), // sub_32bit
4711  LaneBitmask(0x0000000000000010), // sub_mask_0
4712  LaneBitmask(0x0000000000000020), // sub_mask_1
4713  LaneBitmask(0x0000000000000040), // sub_xmm
4714  LaneBitmask(0x0000000000000040), // sub_ymm
4715 };
4716
4717
4718
4719static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
4720  // Mode = 0 (Default)
4721  { 8, 8, 8, VTLists+0 },    // GR8
4722  { 8, 8, 8, VTLists+0 },    // GRH8
4723  { 8, 8, 8, VTLists+0 },    // GR8_NOREX
4724  { 8, 8, 8, VTLists+0 },    // GR8_ABCD_H
4725  { 8, 8, 8, VTLists+0 },    // GR8_ABCD_L
4726  { 16, 16, 16, VTLists+2 },    // GRH16
4727  { 16, 16, 16, VTLists+2 },    // GR16
4728  { 16, 16, 16, VTLists+2 },    // GR16_NOREX
4729  { 16, 16, 16, VTLists+28 },    // VK1
4730  { 16, 16, 16, VTLists+36 },    // VK16
4731  { 16, 16, 16, VTLists+30 },    // VK2
4732  { 16, 16, 16, VTLists+32 },    // VK4
4733  { 16, 16, 16, VTLists+34 },    // VK8
4734  { 16, 16, 16, VTLists+36 },    // VK16WM
4735  { 16, 16, 16, VTLists+28 },    // VK1WM
4736  { 16, 16, 16, VTLists+30 },    // VK2WM
4737  { 16, 16, 16, VTLists+32 },    // VK4WM
4738  { 16, 16, 16, VTLists+34 },    // VK8WM
4739  { 16, 16, 16, VTLists+2 },    // SEGMENT_REG
4740  { 16, 16, 16, VTLists+2 },    // GR16_ABCD
4741  { 16, 16, 16, VTLists+2 },    // FPCCR
4742  { 32, 32, 16, VTLists+8 },    // FR16X
4743  { 32, 32, 16, VTLists+8 },    // FR16
4744  { 32, 32, 16, VTLists+69 },    // VK16PAIR
4745  { 32, 32, 16, VTLists+69 },    // VK1PAIR
4746  { 32, 32, 16, VTLists+69 },    // VK2PAIR
4747  { 32, 32, 16, VTLists+69 },    // VK4PAIR
4748  { 32, 32, 16, VTLists+69 },    // VK8PAIR
4749  { 32, 32, 16, VTLists+69 },    // VK16PAIR_with_sub_mask_0_in_VK16WM
4750  { 32, 32, 32, VTLists+12 },    // FR32X
4751  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP
4752  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS
4753  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
4754  { 32, 32, 32, VTLists+4 },    // DEBUG_REG
4755  { 32, 32, 32, VTLists+12 },    // FR32
4756  { 32, 32, 32, VTLists+4 },    // GR32
4757  { 32, 32, 32, VTLists+4 },    // GR32_NOSP
4758  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
4759  { 32, 32, 32, VTLists+4 },    // GR32_NOREX
4760  { 32, 32, 32, VTLists+38 },    // VK32
4761  { 32, 32, 32, VTLists+4 },    // GR32_NOREX_NOSP
4762  { 32, 32, 32, VTLists+12 },    // RFP32
4763  { 32, 32, 32, VTLists+38 },    // VK32WM
4764  { 32, 32, 32, VTLists+4 },    // GR32_ABCD
4765  { 32, 32, 32, VTLists+4 },    // GR32_TC
4766  { 32, 32, 32, VTLists+4 },    // GR32_ABCD_and_GR32_TC
4767  { 32, 32, 32, VTLists+4 },    // GR32_AD
4768  { 32, 32, 32, VTLists+4 },    // GR32_BPSP
4769  { 32, 32, 32, VTLists+4 },    // GR32_BSI
4770  { 32, 32, 32, VTLists+4 },    // GR32_CB
4771  { 32, 32, 32, VTLists+4 },    // GR32_DC
4772  { 32, 32, 32, VTLists+4 },    // GR32_DIBP
4773  { 32, 32, 32, VTLists+4 },    // GR32_SIDI
4774  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
4775  { 32, 32, 32, VTLists+4 },    // CCR
4776  { 32, 32, 32, VTLists+4 },    // DFCCR
4777  { 32, 32, 32, VTLists+4 },    // GR32_ABCD_and_GR32_BSI
4778  { 32, 32, 32, VTLists+4 },    // GR32_AD_and_GR32_DC
4779  { 32, 32, 32, VTLists+4 },    // GR32_BPSP_and_GR32_DIBP
4780  { 32, 32, 32, VTLists+4 },    // GR32_BPSP_and_GR32_TC
4781  { 32, 32, 32, VTLists+4 },    // GR32_BSI_and_GR32_SIDI
4782  { 32, 32, 32, VTLists+4 },    // GR32_CB_and_GR32_DC
4783  { 32, 32, 32, VTLists+4 },    // GR32_DIBP_and_GR32_SIDI
4784  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
4785  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_with_sub_32bit
4786  { 64, 64, 32, VTLists+14 },    // RFP64
4787  { 64, 64, 64, VTLists+14 },    // FR64X
4788  { 64, 64, 64, VTLists+6 },    // GR64
4789  { 64, 64, 64, VTLists+6 },    // CONTROL_REG
4790  { 64, 64, 64, VTLists+14 },    // FR64
4791  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_8bit
4792  { 64, 64, 64, VTLists+6 },    // GR64_NOSP
4793  { 64, 64, 64, VTLists+6 },    // GR64PLTSafe
4794  { 64, 64, 64, VTLists+6 },    // GR64_TC
4795  { 64, 64, 64, VTLists+6 },    // GR64_NOREX
4796  { 64, 64, 64, VTLists+6 },    // GR64_TCW64
4797  { 64, 64, 64, VTLists+6 },    // GR64_TC_with_sub_8bit
4798  { 64, 64, 64, VTLists+6 },    // GR64_NOSP_and_GR64_TC
4799  { 64, 64, 64, VTLists+6 },    // GR64_TCW64_with_sub_8bit
4800  { 64, 64, 64, VTLists+6 },    // GR64_TC_and_GR64_TCW64
4801  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_16bit_in_GR16_NOREX
4802  { 64, 64, 64, VTLists+40 },    // VK64
4803  { 64, 64, 64, VTLists+67 },    // VR64
4804  { 64, 64, 64, VTLists+6 },    // GR64PLTSafe_and_GR64_TC
4805  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_NOSP
4806  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_and_GR64_TC
4807  { 64, 64, 64, VTLists+6 },    // GR64_NOSP_and_GR64_TCW64
4808  { 64, 64, 64, VTLists+6 },    // GR64_TCW64_and_GR64_TC_with_sub_8bit
4809  { 64, 64, 64, VTLists+40 },    // VK64WM
4810  { 64, 64, 64, VTLists+6 },    // GR64_TC_and_GR64_NOSP_and_GR64_TCW64
4811  { 64, 64, 64, VTLists+6 },    // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
4812  { 64, 64, 64, VTLists+6 },    // GR64PLTSafe_and_GR64_TCW64
4813  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
4814  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_and_GR64_TCW64
4815  { 64, 64, 64, VTLists+6 },    // GR64_ABCD
4816  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_TC
4817  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
4818  { 64, 64, 64, VTLists+6 },    // GR64_AD
4819  { 64, 64, 64, VTLists+6 },    // GR64_and_LOW32_ADDR_ACCESS_RBP
4820  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BPSP
4821  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BSI
4822  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_CB
4823  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_DC
4824  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_DIBP
4825  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_SIDI
4826  { 64, 64, 64, VTLists+6 },    // GR64_and_LOW32_ADDR_ACCESS
4827  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
4828  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
4829  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
4830  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
4831  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
4832  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
4833  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
4834  { 80, 80, 32, VTLists+10 },    // RST
4835  { 80, 80, 32, VTLists+16 },    // RFP80
4836  { 80, 80, 32, VTLists+16 },    // RFP80_7
4837  { 128, 128, 128, VTLists+18 },    // VR128X
4838  { 128, 128, 128, VTLists+18 },    // VR128
4839  { 256, 256, 256, VTLists+42 },    // VR256X
4840  { 256, 256, 256, VTLists+42 },    // VR256
4841  { 512, 512, 512, VTLists+51 },    // VR512
4842  { 512, 512, 512, VTLists+60 },    // VR512_0_15
4843  { 8192, 8192, 8192, VTLists+71 },    // TILE
4844};
4845
4846static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
4847
4848static const uint32_t GR8SubClassMask[] = {
4849  0x0000001d, 0x00000000, 0x00000000, 0x00000000,
4850  0x000800c0, 0xff1ff979, 0xded971c0, 0x0001fdfb, // sub_8bit
4851  0x00080000, 0x23066800, 0x40000000, 0x00008c63, // sub_8bit_hi
4852};
4853
4854static const uint32_t GRH8SubClassMask[] = {
4855  0x00000002, 0x00000000, 0x00000000, 0x00000000,
4856};
4857
4858static const uint32_t GR8_NOREXSubClassMask[] = {
4859  0x0000001c, 0x00000000, 0x00000000, 0x00000000,
4860  0x00080000, 0x23066800, 0x40000000, 0x00008c63, // sub_8bit
4861  0x00080000, 0x23066800, 0x40000000, 0x00008c63, // sub_8bit_hi
4862};
4863
4864static const uint32_t GR8_ABCD_HSubClassMask[] = {
4865  0x00000008, 0x00000000, 0x00000000, 0x00000000,
4866  0x00080000, 0x23066800, 0x40000000, 0x00008c63, // sub_8bit_hi
4867};
4868
4869static const uint32_t GR8_ABCD_LSubClassMask[] = {
4870  0x00000010, 0x00000000, 0x00000000, 0x00000000,
4871  0x00080000, 0x23066800, 0x40000000, 0x00008c63, // sub_8bit
4872};
4873
4874static const uint32_t GRH16SubClassMask[] = {
4875  0x00000020, 0x00000000, 0x00000000, 0x00000000,
4876};
4877
4878static const uint32_t GR16SubClassMask[] = {
4879  0x000800c0, 0x00000000, 0x00000000, 0x00000000,
4880  0x00000000, 0xff1ff979, 0xded971c0, 0x0001fdfb, // sub_16bit
4881};
4882
4883static const uint32_t GR16_NOREXSubClassMask[] = {
4884  0x00080080, 0x00000000, 0x00000000, 0x00000000,
4885  0x00000000, 0xff1ff960, 0xd4110000, 0x0001fdfb, // sub_16bit
4886};
4887
4888static const uint32_t VK1SubClassMask[] = {
4889  0x0003ff00, 0x00000480, 0x01020000, 0x00000000,
4890  0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4891  0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4892};
4893
4894static const uint32_t VK16SubClassMask[] = {
4895  0x0003ff00, 0x00000480, 0x01020000, 0x00000000,
4896  0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4897  0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4898};
4899
4900static const uint32_t VK2SubClassMask[] = {
4901  0x0003ff00, 0x00000480, 0x01020000, 0x00000000,
4902  0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4903  0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4904};
4905
4906static const uint32_t VK4SubClassMask[] = {
4907  0x0003ff00, 0x00000480, 0x01020000, 0x00000000,
4908  0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4909  0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4910};
4911
4912static const uint32_t VK8SubClassMask[] = {
4913  0x0003ff00, 0x00000480, 0x01020000, 0x00000000,
4914  0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4915  0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4916};
4917
4918static const uint32_t VK16WMSubClassMask[] = {
4919  0x0003e000, 0x00000400, 0x01000000, 0x00000000,
4920  0x10000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4921  0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4922};
4923
4924static const uint32_t VK1WMSubClassMask[] = {
4925  0x0003e000, 0x00000400, 0x01000000, 0x00000000,
4926  0x10000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4927  0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4928};
4929
4930static const uint32_t VK2WMSubClassMask[] = {
4931  0x0003e000, 0x00000400, 0x01000000, 0x00000000,
4932  0x10000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4933  0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4934};
4935
4936static const uint32_t VK4WMSubClassMask[] = {
4937  0x0003e000, 0x00000400, 0x01000000, 0x00000000,
4938  0x10000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4939  0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4940};
4941
4942static const uint32_t VK8WMSubClassMask[] = {
4943  0x0003e000, 0x00000400, 0x01000000, 0x00000000,
4944  0x10000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
4945  0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
4946};
4947
4948static const uint32_t SEGMENT_REGSubClassMask[] = {
4949  0x00040000, 0x00000000, 0x00000000, 0x00000000,
4950};
4951
4952static const uint32_t GR16_ABCDSubClassMask[] = {
4953  0x00080000, 0x00000000, 0x00000000, 0x00000000,
4954  0x00000000, 0x23066800, 0x40000000, 0x00008c63, // sub_16bit
4955};
4956
4957static const uint32_t FPCCRSubClassMask[] = {
4958  0x00100000, 0x00000000, 0x00000000, 0x00000000,
4959};
4960
4961static const uint32_t FR16XSubClassMask[] = {
4962  0x20600000, 0x00000004, 0x00000024, 0x00300000,
4963  0x00000000, 0x00000000, 0x00000000, 0x03c00000, // sub_xmm
4964};
4965
4966static const uint32_t FR16SubClassMask[] = {
4967  0x00400000, 0x00000004, 0x00000020, 0x00200000,
4968  0x00000000, 0x00000000, 0x00000000, 0x02800000, // sub_xmm
4969};
4970
4971static const uint32_t VK16PAIRSubClassMask[] = {
4972  0x1f800000, 0x00000000, 0x00000000, 0x00000000,
4973};
4974
4975static const uint32_t VK1PAIRSubClassMask[] = {
4976  0x1f800000, 0x00000000, 0x00000000, 0x00000000,
4977};
4978
4979static const uint32_t VK2PAIRSubClassMask[] = {
4980  0x1f800000, 0x00000000, 0x00000000, 0x00000000,
4981};
4982
4983static const uint32_t VK4PAIRSubClassMask[] = {
4984  0x1f800000, 0x00000000, 0x00000000, 0x00000000,
4985};
4986
4987static const uint32_t VK8PAIRSubClassMask[] = {
4988  0x1f800000, 0x00000000, 0x00000000, 0x00000000,
4989};
4990
4991static const uint32_t VK16PAIR_with_sub_mask_0_in_VK16WMSubClassMask[] = {
4992  0x10000000, 0x00000000, 0x00000000, 0x00000000,
4993};
4994
4995static const uint32_t FR32XSubClassMask[] = {
4996  0x20000000, 0x00000004, 0x00000024, 0x00300000,
4997  0x00000000, 0x00000000, 0x00000000, 0x03c00000, // sub_xmm
4998};
4999
5000static const uint32_t LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
5001  0xc0000000, 0xff3ff979, 0x00000001, 0x00001204,
5002  0x00000000, 0x80000000, 0xded971c0, 0x0001fdfb, // sub_32bit
5003};
5004
5005static const uint32_t LOW32_ADDR_ACCESSSubClassMask[] = {
5006  0x80000000, 0x7f1ff958, 0x00000001, 0x00000200,
5007  0x00000000, 0x80000000, 0xded971c0, 0x0001fdfb, // sub_32bit
5008};
5009
5010static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask[] = {
5011  0x00000000, 0xff1ff979, 0x00000000, 0x00001000,
5012  0x00000000, 0x80000000, 0xded971c0, 0x0001fdfb, // sub_32bit
5013};
5014
5015static const uint32_t DEBUG_REGSubClassMask[] = {
5016  0x00000000, 0x00000002, 0x00000000, 0x00000000,
5017};
5018
5019static const uint32_t FR32SubClassMask[] = {
5020  0x00000000, 0x00000004, 0x00000020, 0x00200000,
5021  0x00000000, 0x00000000, 0x00000000, 0x02800000, // sub_xmm
5022};
5023
5024static const uint32_t GR32SubClassMask[] = {
5025  0x00000000, 0x7f1ff958, 0x00000000, 0x00000000,
5026  0x00000000, 0x80000000, 0xded971c0, 0x0001fdfb, // sub_32bit
5027};
5028
5029static const uint32_t GR32_NOSPSubClassMask[] = {
5030  0x00000000, 0x771f6910, 0x00000000, 0x00000000,
5031  0x00000000, 0x80000000, 0x5a582180, 0x0001ddf3, // sub_32bit
5032};
5033
5034static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
5035  0x00000000, 0xff1ff960, 0x00000000, 0x00001000,
5036  0x00000000, 0x80000000, 0xd4110000, 0x0001fdfb, // sub_32bit
5037};
5038
5039static const uint32_t GR32_NOREXSubClassMask[] = {
5040  0x00000000, 0x7f1ff940, 0x00000000, 0x00000000,
5041  0x00000000, 0x80000000, 0xd4110000, 0x0001fdfb, // sub_32bit
5042};
5043
5044static const uint32_t VK32SubClassMask[] = {
5045  0x00000000, 0x00000480, 0x01020000, 0x00000000,
5046  0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5047  0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5048};
5049
5050static const uint32_t GR32_NOREX_NOSPSubClassMask[] = {
5051  0x00000000, 0x771f6900, 0x00000000, 0x00000000,
5052  0x00000000, 0x80000000, 0x50100000, 0x0001ddf3, // sub_32bit
5053};
5054
5055static const uint32_t RFP32SubClassMask[] = {
5056  0x00000000, 0x00000200, 0x00000002, 0x00040000,
5057};
5058
5059static const uint32_t VK32WMSubClassMask[] = {
5060  0x00000000, 0x00000400, 0x01000000, 0x00000000,
5061  0x10000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5062  0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5063};
5064
5065static const uint32_t GR32_ABCDSubClassMask[] = {
5066  0x00000000, 0x23066800, 0x00000000, 0x00000000,
5067  0x00000000, 0x00000000, 0x40000000, 0x00008c63, // sub_32bit
5068};
5069
5070static const uint32_t GR32_TCSubClassMask[] = {
5071  0x00000000, 0x2a047000, 0x00000000, 0x00000000,
5072  0x00000000, 0x00000000, 0x80000000, 0x0000a843, // sub_32bit
5073};
5074
5075static const uint32_t GR32_ABCD_and_GR32_TCSubClassMask[] = {
5076  0x00000000, 0x22046000, 0x00000000, 0x00000000,
5077  0x00000000, 0x00000000, 0x00000000, 0x00008843, // sub_32bit
5078};
5079
5080static const uint32_t GR32_ADSubClassMask[] = {
5081  0x00000000, 0x02004000, 0x00000000, 0x00000000,
5082  0x00000000, 0x00000000, 0x00000000, 0x00000802, // sub_32bit
5083};
5084
5085static const uint32_t GR32_BPSPSubClassMask[] = {
5086  0x00000000, 0x0c008000, 0x00000000, 0x00000000,
5087  0x00000000, 0x80000000, 0x00000000, 0x00003008, // sub_32bit
5088};
5089
5090static const uint32_t GR32_BSISubClassMask[] = {
5091  0x00000000, 0x11010000, 0x00000000, 0x00000000,
5092  0x00000000, 0x00000000, 0x00000000, 0x00004410, // sub_32bit
5093};
5094
5095static const uint32_t GR32_CBSubClassMask[] = {
5096  0x00000000, 0x21020000, 0x00000000, 0x00000000,
5097  0x00000000, 0x00000000, 0x00000000, 0x00008420, // sub_32bit
5098};
5099
5100static const uint32_t GR32_DCSubClassMask[] = {
5101  0x00000000, 0x22040000, 0x00000000, 0x00000000,
5102  0x00000000, 0x00000000, 0x00000000, 0x00008840, // sub_32bit
5103};
5104
5105static const uint32_t GR32_DIBPSubClassMask[] = {
5106  0x00000000, 0x44080000, 0x00000000, 0x00000000,
5107  0x00000000, 0x80000000, 0x00000000, 0x00011080, // sub_32bit
5108};
5109
5110static const uint32_t GR32_SIDISubClassMask[] = {
5111  0x00000000, 0x50100000, 0x00000000, 0x00000000,
5112  0x00000000, 0x00000000, 0x00000000, 0x00014100, // sub_32bit
5113};
5114
5115static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask[] = {
5116  0x00000000, 0x80200000, 0x00000001, 0x00001204,
5117};
5118
5119static const uint32_t CCRSubClassMask[] = {
5120  0x00000000, 0x00400000, 0x00000000, 0x00000000,
5121};
5122
5123static const uint32_t DFCCRSubClassMask[] = {
5124  0x00000000, 0x00800000, 0x00000000, 0x00000000,
5125};
5126
5127static const uint32_t GR32_ABCD_and_GR32_BSISubClassMask[] = {
5128  0x00000000, 0x01000000, 0x00000000, 0x00000000,
5129  0x00000000, 0x00000000, 0x00000000, 0x00000400, // sub_32bit
5130};
5131
5132static const uint32_t GR32_AD_and_GR32_DCSubClassMask[] = {
5133  0x00000000, 0x02000000, 0x00000000, 0x00000000,
5134  0x00000000, 0x00000000, 0x00000000, 0x00000800, // sub_32bit
5135};
5136
5137static const uint32_t GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
5138  0x00000000, 0x04000000, 0x00000000, 0x00000000,
5139  0x00000000, 0x80000000, 0x00000000, 0x00001000, // sub_32bit
5140};
5141
5142static const uint32_t GR32_BPSP_and_GR32_TCSubClassMask[] = {
5143  0x00000000, 0x08000000, 0x00000000, 0x00000000,
5144  0x00000000, 0x00000000, 0x00000000, 0x00002000, // sub_32bit
5145};
5146
5147static const uint32_t GR32_BSI_and_GR32_SIDISubClassMask[] = {
5148  0x00000000, 0x10000000, 0x00000000, 0x00000000,
5149  0x00000000, 0x00000000, 0x00000000, 0x00004000, // sub_32bit
5150};
5151
5152static const uint32_t GR32_CB_and_GR32_DCSubClassMask[] = {
5153  0x00000000, 0x20000000, 0x00000000, 0x00000000,
5154  0x00000000, 0x00000000, 0x00000000, 0x00008000, // sub_32bit
5155};
5156
5157static const uint32_t GR32_DIBP_and_GR32_SIDISubClassMask[] = {
5158  0x00000000, 0x40000000, 0x00000000, 0x00000000,
5159  0x00000000, 0x00000000, 0x00000000, 0x00010000, // sub_32bit
5160};
5161
5162static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask[] = {
5163  0x00000000, 0x80000000, 0x00000000, 0x00001000,
5164};
5165
5166static const uint32_t LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask[] = {
5167  0x00000000, 0x00000000, 0x00000001, 0x00000200,
5168};
5169
5170static const uint32_t RFP64SubClassMask[] = {
5171  0x00000000, 0x00000000, 0x00000002, 0x00040000,
5172};
5173
5174static const uint32_t FR64XSubClassMask[] = {
5175  0x00000000, 0x00000000, 0x00000024, 0x00300000,
5176  0x00000000, 0x00000000, 0x00000000, 0x03c00000, // sub_xmm
5177};
5178
5179static const uint32_t GR64SubClassMask[] = {
5180  0x00000000, 0x00000000, 0xfef9ffc8, 0x0001ffff,
5181};
5182
5183static const uint32_t CONTROL_REGSubClassMask[] = {
5184  0x00000000, 0x00000000, 0x00000010, 0x00000000,
5185};
5186
5187static const uint32_t FR64SubClassMask[] = {
5188  0x00000000, 0x00000000, 0x00000020, 0x00200000,
5189  0x00000000, 0x00000000, 0x00000000, 0x02800000, // sub_xmm
5190};
5191
5192static const uint32_t GR64_with_sub_8bitSubClassMask[] = {
5193  0x00000000, 0x00000000, 0xded971c0, 0x0001fdfb,
5194};
5195
5196static const uint32_t GR64_NOSPSubClassMask[] = {
5197  0x00000000, 0x00000000, 0x5a582180, 0x0001ddf3,
5198};
5199
5200static const uint32_t GR64PLTSafeSubClassMask[] = {
5201  0x00000000, 0x00000000, 0x58180100, 0x0001ddf3,
5202};
5203
5204static const uint32_t GR64_TCSubClassMask[] = {
5205  0x00000000, 0x00000000, 0xbea8b200, 0x0001eb43,
5206};
5207
5208static const uint32_t GR64_NOREXSubClassMask[] = {
5209  0x00000000, 0x00000000, 0xf4310400, 0x0001ffff,
5210};
5211
5212static const uint32_t GR64_TCW64SubClassMask[] = {
5213  0x00000000, 0x00000000, 0xaac0c800, 0x0000aa43,
5214};
5215
5216static const uint32_t GR64_TC_with_sub_8bitSubClassMask[] = {
5217  0x00000000, 0x00000000, 0x9e883000, 0x0001e943,
5218};
5219
5220static const uint32_t GR64_NOSP_and_GR64_TCSubClassMask[] = {
5221  0x00000000, 0x00000000, 0x1a082000, 0x0001c943,
5222};
5223
5224static const uint32_t GR64_TCW64_with_sub_8bitSubClassMask[] = {
5225  0x00000000, 0x00000000, 0x8ac04000, 0x0000a843,
5226};
5227
5228static const uint32_t GR64_TC_and_GR64_TCW64SubClassMask[] = {
5229  0x00000000, 0x00000000, 0xaa808000, 0x0000aa43,
5230};
5231
5232static const uint32_t GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
5233  0x00000000, 0x00000000, 0xd4110000, 0x0001fdfb,
5234};
5235
5236static const uint32_t VK64SubClassMask[] = {
5237  0x00000000, 0x00000000, 0x01020000, 0x00000000,
5238  0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5239  0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5240};
5241
5242static const uint32_t VR64SubClassMask[] = {
5243  0x00000000, 0x00000000, 0x00040000, 0x00000000,
5244};
5245
5246static const uint32_t GR64PLTSafe_and_GR64_TCSubClassMask[] = {
5247  0x00000000, 0x00000000, 0x18080000, 0x0001c943,
5248};
5249
5250static const uint32_t GR64_NOREX_NOSPSubClassMask[] = {
5251  0x00000000, 0x00000000, 0x50100000, 0x0001ddf3,
5252};
5253
5254static const uint32_t GR64_NOREX_and_GR64_TCSubClassMask[] = {
5255  0x00000000, 0x00000000, 0xb4200000, 0x0001eb43,
5256};
5257
5258static const uint32_t GR64_NOSP_and_GR64_TCW64SubClassMask[] = {
5259  0x00000000, 0x00000000, 0x0a400000, 0x00008843,
5260};
5261
5262static const uint32_t GR64_TCW64_and_GR64_TC_with_sub_8bitSubClassMask[] = {
5263  0x00000000, 0x00000000, 0x8a800000, 0x0000a843,
5264};
5265
5266static const uint32_t VK64WMSubClassMask[] = {
5267  0x00000000, 0x00000000, 0x01000000, 0x00000000,
5268  0x10000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5269  0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5270};
5271
5272static const uint32_t GR64_TC_and_GR64_NOSP_and_GR64_TCW64SubClassMask[] = {
5273  0x00000000, 0x00000000, 0x0a000000, 0x00008843,
5274};
5275
5276static const uint32_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
5277  0x00000000, 0x00000000, 0x94000000, 0x0001e943,
5278};
5279
5280static const uint32_t GR64PLTSafe_and_GR64_TCW64SubClassMask[] = {
5281  0x00000000, 0x00000000, 0x08000000, 0x00008843,
5282};
5283
5284static const uint32_t GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSubClassMask[] = {
5285  0x00000000, 0x00000000, 0x10000000, 0x0001c943,
5286};
5287
5288static const uint32_t GR64_NOREX_and_GR64_TCW64SubClassMask[] = {
5289  0x00000000, 0x00000000, 0xa0000000, 0x0000aa43,
5290};
5291
5292static const uint32_t GR64_ABCDSubClassMask[] = {
5293  0x00000000, 0x00000000, 0x40000000, 0x00008c63,
5294};
5295
5296static const uint32_t GR64_with_sub_32bit_in_GR32_TCSubClassMask[] = {
5297  0x00000000, 0x00000000, 0x80000000, 0x0000a843,
5298};
5299
5300static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSubClassMask[] = {
5301  0x00000000, 0x00000000, 0x00000000, 0x00008843,
5302};
5303
5304static const uint32_t GR64_ADSubClassMask[] = {
5305  0x00000000, 0x00000000, 0x00000000, 0x00000802,
5306};
5307
5308static const uint32_t GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
5309  0x00000000, 0x00000000, 0x00000000, 0x00001204,
5310};
5311
5312static const uint32_t GR64_with_sub_32bit_in_GR32_BPSPSubClassMask[] = {
5313  0x00000000, 0x00000000, 0x00000000, 0x00003008,
5314};
5315
5316static const uint32_t GR64_with_sub_32bit_in_GR32_BSISubClassMask[] = {
5317  0x00000000, 0x00000000, 0x00000000, 0x00004410,
5318};
5319
5320static const uint32_t GR64_with_sub_32bit_in_GR32_CBSubClassMask[] = {
5321  0x00000000, 0x00000000, 0x00000000, 0x00008420,
5322};
5323
5324static const uint32_t GR64_with_sub_32bit_in_GR32_DCSubClassMask[] = {
5325  0x00000000, 0x00000000, 0x00000000, 0x00008840,
5326};
5327
5328static const uint32_t GR64_with_sub_32bit_in_GR32_DIBPSubClassMask[] = {
5329  0x00000000, 0x00000000, 0x00000000, 0x00011080,
5330};
5331
5332static const uint32_t GR64_with_sub_32bit_in_GR32_SIDISubClassMask[] = {
5333  0x00000000, 0x00000000, 0x00000000, 0x00014100,
5334};
5335
5336static const uint32_t GR64_and_LOW32_ADDR_ACCESSSubClassMask[] = {
5337  0x00000000, 0x00000000, 0x00000000, 0x00000200,
5338};
5339
5340static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask[] = {
5341  0x00000000, 0x00000000, 0x00000000, 0x00000400,
5342};
5343
5344static const uint32_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCSubClassMask[] = {
5345  0x00000000, 0x00000000, 0x00000000, 0x00000800,
5346};
5347
5348static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
5349  0x00000000, 0x00000000, 0x00000000, 0x00001000,
5350};
5351
5352static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSubClassMask[] = {
5353  0x00000000, 0x00000000, 0x00000000, 0x00002000,
5354};
5355
5356static const uint32_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask[] = {
5357  0x00000000, 0x00000000, 0x00000000, 0x00004000,
5358};
5359
5360static const uint32_t GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCSubClassMask[] = {
5361  0x00000000, 0x00000000, 0x00000000, 0x00008000,
5362};
5363
5364static const uint32_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask[] = {
5365  0x00000000, 0x00000000, 0x00000000, 0x00010000,
5366};
5367
5368static const uint32_t RSTSubClassMask[] = {
5369  0x00000000, 0x00000000, 0x00000000, 0x00020000,
5370};
5371
5372static const uint32_t RFP80SubClassMask[] = {
5373  0x00000000, 0x00000000, 0x00000000, 0x00040000,
5374};
5375
5376static const uint32_t RFP80_7SubClassMask[] = {
5377  0x00000000, 0x00000000, 0x00000000, 0x00080000,
5378};
5379
5380static const uint32_t VR128XSubClassMask[] = {
5381  0x00000000, 0x00000000, 0x00000000, 0x00300000,
5382  0x00000000, 0x00000000, 0x00000000, 0x03c00000, // sub_xmm
5383};
5384
5385static const uint32_t VR128SubClassMask[] = {
5386  0x00000000, 0x00000000, 0x00000000, 0x00200000,
5387  0x00000000, 0x00000000, 0x00000000, 0x02800000, // sub_xmm
5388};
5389
5390static const uint32_t VR256XSubClassMask[] = {
5391  0x00000000, 0x00000000, 0x00000000, 0x00c00000,
5392  0x00000000, 0x00000000, 0x00000000, 0x03000000, // sub_ymm
5393};
5394
5395static const uint32_t VR256SubClassMask[] = {
5396  0x00000000, 0x00000000, 0x00000000, 0x00800000,
5397  0x00000000, 0x00000000, 0x00000000, 0x02000000, // sub_ymm
5398};
5399
5400static const uint32_t VR512SubClassMask[] = {
5401  0x00000000, 0x00000000, 0x00000000, 0x03000000,
5402};
5403
5404static const uint32_t VR512_0_15SubClassMask[] = {
5405  0x00000000, 0x00000000, 0x00000000, 0x02000000,
5406};
5407
5408static const uint32_t TILESubClassMask[] = {
5409  0x00000000, 0x00000000, 0x00000000, 0x04000000,
5410};
5411
5412static const uint16_t SuperRegIdxSeqs[] = {
5413  /* 0 */ 1, 0,
5414  /* 2 */ 1, 2, 0,
5415  /* 5 */ 4, 0,
5416  /* 7 */ 6, 0,
5417  /* 9 */ 7, 8, 0,
5418  /* 12 */ 9, 0,
5419  /* 14 */ 10, 0,
5420};
5421
5422static const TargetRegisterClass *const GR8_NOREXSuperclasses[] = {
5423  &X86::GR8RegClass,
5424  nullptr
5425};
5426
5427static const TargetRegisterClass *const GR8_ABCD_HSuperclasses[] = {
5428  &X86::GR8RegClass,
5429  &X86::GR8_NOREXRegClass,
5430  nullptr
5431};
5432
5433static const TargetRegisterClass *const GR8_ABCD_LSuperclasses[] = {
5434  &X86::GR8RegClass,
5435  &X86::GR8_NOREXRegClass,
5436  nullptr
5437};
5438
5439static const TargetRegisterClass *const GR16_NOREXSuperclasses[] = {
5440  &X86::GR16RegClass,
5441  nullptr
5442};
5443
5444static const TargetRegisterClass *const VK1Superclasses[] = {
5445  &X86::VK16RegClass,
5446  &X86::VK2RegClass,
5447  &X86::VK4RegClass,
5448  &X86::VK8RegClass,
5449  nullptr
5450};
5451
5452static const TargetRegisterClass *const VK16Superclasses[] = {
5453  &X86::VK1RegClass,
5454  &X86::VK2RegClass,
5455  &X86::VK4RegClass,
5456  &X86::VK8RegClass,
5457  nullptr
5458};
5459
5460static const TargetRegisterClass *const VK2Superclasses[] = {
5461  &X86::VK1RegClass,
5462  &X86::VK16RegClass,
5463  &X86::VK4RegClass,
5464  &X86::VK8RegClass,
5465  nullptr
5466};
5467
5468static const TargetRegisterClass *const VK4Superclasses[] = {
5469  &X86::VK1RegClass,
5470  &X86::VK16RegClass,
5471  &X86::VK2RegClass,
5472  &X86::VK8RegClass,
5473  nullptr
5474};
5475
5476static const TargetRegisterClass *const VK8Superclasses[] = {
5477  &X86::VK1RegClass,
5478  &X86::VK16RegClass,
5479  &X86::VK2RegClass,
5480  &X86::VK4RegClass,
5481  nullptr
5482};
5483
5484static const TargetRegisterClass *const VK16WMSuperclasses[] = {
5485  &X86::VK1RegClass,
5486  &X86::VK16RegClass,
5487  &X86::VK2RegClass,
5488  &X86::VK4RegClass,
5489  &X86::VK8RegClass,
5490  &X86::VK1WMRegClass,
5491  &X86::VK2WMRegClass,
5492  &X86::VK4WMRegClass,
5493  &X86::VK8WMRegClass,
5494  nullptr
5495};
5496
5497static const TargetRegisterClass *const VK1WMSuperclasses[] = {
5498  &X86::VK1RegClass,
5499  &X86::VK16RegClass,
5500  &X86::VK2RegClass,
5501  &X86::VK4RegClass,
5502  &X86::VK8RegClass,
5503  &X86::VK16WMRegClass,
5504  &X86::VK2WMRegClass,
5505  &X86::VK4WMRegClass,
5506  &X86::VK8WMRegClass,
5507  nullptr
5508};
5509
5510static const TargetRegisterClass *const VK2WMSuperclasses[] = {
5511  &X86::VK1RegClass,
5512  &X86::VK16RegClass,
5513  &X86::VK2RegClass,
5514  &X86::VK4RegClass,
5515  &X86::VK8RegClass,
5516  &X86::VK16WMRegClass,
5517  &X86::VK1WMRegClass,
5518  &X86::VK4WMRegClass,
5519  &X86::VK8WMRegClass,
5520  nullptr
5521};
5522
5523static const TargetRegisterClass *const VK4WMSuperclasses[] = {
5524  &X86::VK1RegClass,
5525  &X86::VK16RegClass,
5526  &X86::VK2RegClass,
5527  &X86::VK4RegClass,
5528  &X86::VK8RegClass,
5529  &X86::VK16WMRegClass,
5530  &X86::VK1WMRegClass,
5531  &X86::VK2WMRegClass,
5532  &X86::VK8WMRegClass,
5533  nullptr
5534};
5535
5536static const TargetRegisterClass *const VK8WMSuperclasses[] = {
5537  &X86::VK1RegClass,
5538  &X86::VK16RegClass,
5539  &X86::VK2RegClass,
5540  &X86::VK4RegClass,
5541  &X86::VK8RegClass,
5542  &X86::VK16WMRegClass,
5543  &X86::VK1WMRegClass,
5544  &X86::VK2WMRegClass,
5545  &X86::VK4WMRegClass,
5546  nullptr
5547};
5548
5549static const TargetRegisterClass *const GR16_ABCDSuperclasses[] = {
5550  &X86::GR16RegClass,
5551  &X86::GR16_NOREXRegClass,
5552  nullptr
5553};
5554
5555static const TargetRegisterClass *const FR16Superclasses[] = {
5556  &X86::FR16XRegClass,
5557  nullptr
5558};
5559
5560static const TargetRegisterClass *const VK16PAIRSuperclasses[] = {
5561  &X86::VK1PAIRRegClass,
5562  &X86::VK2PAIRRegClass,
5563  &X86::VK4PAIRRegClass,
5564  &X86::VK8PAIRRegClass,
5565  nullptr
5566};
5567
5568static const TargetRegisterClass *const VK1PAIRSuperclasses[] = {
5569  &X86::VK16PAIRRegClass,
5570  &X86::VK2PAIRRegClass,
5571  &X86::VK4PAIRRegClass,
5572  &X86::VK8PAIRRegClass,
5573  nullptr
5574};
5575
5576static const TargetRegisterClass *const VK2PAIRSuperclasses[] = {
5577  &X86::VK16PAIRRegClass,
5578  &X86::VK1PAIRRegClass,
5579  &X86::VK4PAIRRegClass,
5580  &X86::VK8PAIRRegClass,
5581  nullptr
5582};
5583
5584static const TargetRegisterClass *const VK4PAIRSuperclasses[] = {
5585  &X86::VK16PAIRRegClass,
5586  &X86::VK1PAIRRegClass,
5587  &X86::VK2PAIRRegClass,
5588  &X86::VK8PAIRRegClass,
5589  nullptr
5590};
5591
5592static const TargetRegisterClass *const VK8PAIRSuperclasses[] = {
5593  &X86::VK16PAIRRegClass,
5594  &X86::VK1PAIRRegClass,
5595  &X86::VK2PAIRRegClass,
5596  &X86::VK4PAIRRegClass,
5597  nullptr
5598};
5599
5600static const TargetRegisterClass *const VK16PAIR_with_sub_mask_0_in_VK16WMSuperclasses[] = {
5601  &X86::VK16PAIRRegClass,
5602  &X86::VK1PAIRRegClass,
5603  &X86::VK2PAIRRegClass,
5604  &X86::VK4PAIRRegClass,
5605  &X86::VK8PAIRRegClass,
5606  nullptr
5607};
5608
5609static const TargetRegisterClass *const FR32XSuperclasses[] = {
5610  &X86::FR16XRegClass,
5611  nullptr
5612};
5613
5614static const TargetRegisterClass *const LOW32_ADDR_ACCESSSuperclasses[] = {
5615  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5616  nullptr
5617};
5618
5619static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses[] = {
5620  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5621  nullptr
5622};
5623
5624static const TargetRegisterClass *const FR32Superclasses[] = {
5625  &X86::FR16XRegClass,
5626  &X86::FR16RegClass,
5627  &X86::FR32XRegClass,
5628  nullptr
5629};
5630
5631static const TargetRegisterClass *const GR32Superclasses[] = {
5632  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5633  &X86::LOW32_ADDR_ACCESSRegClass,
5634  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5635  nullptr
5636};
5637
5638static const TargetRegisterClass *const GR32_NOSPSuperclasses[] = {
5639  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5640  &X86::LOW32_ADDR_ACCESSRegClass,
5641  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5642  &X86::GR32RegClass,
5643  nullptr
5644};
5645
5646static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
5647  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5648  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5649  nullptr
5650};
5651
5652static const TargetRegisterClass *const GR32_NOREXSuperclasses[] = {
5653  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5654  &X86::LOW32_ADDR_ACCESSRegClass,
5655  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5656  &X86::GR32RegClass,
5657  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5658  nullptr
5659};
5660
5661static const TargetRegisterClass *const VK32Superclasses[] = {
5662  &X86::VK1RegClass,
5663  &X86::VK16RegClass,
5664  &X86::VK2RegClass,
5665  &X86::VK4RegClass,
5666  &X86::VK8RegClass,
5667  nullptr
5668};
5669
5670static const TargetRegisterClass *const GR32_NOREX_NOSPSuperclasses[] = {
5671  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5672  &X86::LOW32_ADDR_ACCESSRegClass,
5673  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5674  &X86::GR32RegClass,
5675  &X86::GR32_NOSPRegClass,
5676  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5677  &X86::GR32_NOREXRegClass,
5678  nullptr
5679};
5680
5681static const TargetRegisterClass *const VK32WMSuperclasses[] = {
5682  &X86::VK1RegClass,
5683  &X86::VK16RegClass,
5684  &X86::VK2RegClass,
5685  &X86::VK4RegClass,
5686  &X86::VK8RegClass,
5687  &X86::VK16WMRegClass,
5688  &X86::VK1WMRegClass,
5689  &X86::VK2WMRegClass,
5690  &X86::VK4WMRegClass,
5691  &X86::VK8WMRegClass,
5692  &X86::VK32RegClass,
5693  nullptr
5694};
5695
5696static const TargetRegisterClass *const GR32_ABCDSuperclasses[] = {
5697  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5698  &X86::LOW32_ADDR_ACCESSRegClass,
5699  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5700  &X86::GR32RegClass,
5701  &X86::GR32_NOSPRegClass,
5702  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5703  &X86::GR32_NOREXRegClass,
5704  &X86::GR32_NOREX_NOSPRegClass,
5705  nullptr
5706};
5707
5708static const TargetRegisterClass *const GR32_TCSuperclasses[] = {
5709  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5710  &X86::LOW32_ADDR_ACCESSRegClass,
5711  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5712  &X86::GR32RegClass,
5713  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5714  &X86::GR32_NOREXRegClass,
5715  nullptr
5716};
5717
5718static const TargetRegisterClass *const GR32_ABCD_and_GR32_TCSuperclasses[] = {
5719  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5720  &X86::LOW32_ADDR_ACCESSRegClass,
5721  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5722  &X86::GR32RegClass,
5723  &X86::GR32_NOSPRegClass,
5724  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5725  &X86::GR32_NOREXRegClass,
5726  &X86::GR32_NOREX_NOSPRegClass,
5727  &X86::GR32_ABCDRegClass,
5728  &X86::GR32_TCRegClass,
5729  nullptr
5730};
5731
5732static const TargetRegisterClass *const GR32_ADSuperclasses[] = {
5733  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5734  &X86::LOW32_ADDR_ACCESSRegClass,
5735  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5736  &X86::GR32RegClass,
5737  &X86::GR32_NOSPRegClass,
5738  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5739  &X86::GR32_NOREXRegClass,
5740  &X86::GR32_NOREX_NOSPRegClass,
5741  &X86::GR32_ABCDRegClass,
5742  &X86::GR32_TCRegClass,
5743  &X86::GR32_ABCD_and_GR32_TCRegClass,
5744  nullptr
5745};
5746
5747static const TargetRegisterClass *const GR32_BPSPSuperclasses[] = {
5748  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5749  &X86::LOW32_ADDR_ACCESSRegClass,
5750  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5751  &X86::GR32RegClass,
5752  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5753  &X86::GR32_NOREXRegClass,
5754  nullptr
5755};
5756
5757static const TargetRegisterClass *const GR32_BSISuperclasses[] = {
5758  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5759  &X86::LOW32_ADDR_ACCESSRegClass,
5760  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5761  &X86::GR32RegClass,
5762  &X86::GR32_NOSPRegClass,
5763  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5764  &X86::GR32_NOREXRegClass,
5765  &X86::GR32_NOREX_NOSPRegClass,
5766  nullptr
5767};
5768
5769static const TargetRegisterClass *const GR32_CBSuperclasses[] = {
5770  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5771  &X86::LOW32_ADDR_ACCESSRegClass,
5772  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5773  &X86::GR32RegClass,
5774  &X86::GR32_NOSPRegClass,
5775  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5776  &X86::GR32_NOREXRegClass,
5777  &X86::GR32_NOREX_NOSPRegClass,
5778  &X86::GR32_ABCDRegClass,
5779  nullptr
5780};
5781
5782static const TargetRegisterClass *const GR32_DCSuperclasses[] = {
5783  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5784  &X86::LOW32_ADDR_ACCESSRegClass,
5785  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5786  &X86::GR32RegClass,
5787  &X86::GR32_NOSPRegClass,
5788  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5789  &X86::GR32_NOREXRegClass,
5790  &X86::GR32_NOREX_NOSPRegClass,
5791  &X86::GR32_ABCDRegClass,
5792  &X86::GR32_TCRegClass,
5793  &X86::GR32_ABCD_and_GR32_TCRegClass,
5794  nullptr
5795};
5796
5797static const TargetRegisterClass *const GR32_DIBPSuperclasses[] = {
5798  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5799  &X86::LOW32_ADDR_ACCESSRegClass,
5800  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5801  &X86::GR32RegClass,
5802  &X86::GR32_NOSPRegClass,
5803  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5804  &X86::GR32_NOREXRegClass,
5805  &X86::GR32_NOREX_NOSPRegClass,
5806  nullptr
5807};
5808
5809static const TargetRegisterClass *const GR32_SIDISuperclasses[] = {
5810  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5811  &X86::LOW32_ADDR_ACCESSRegClass,
5812  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5813  &X86::GR32RegClass,
5814  &X86::GR32_NOSPRegClass,
5815  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5816  &X86::GR32_NOREXRegClass,
5817  &X86::GR32_NOREX_NOSPRegClass,
5818  nullptr
5819};
5820
5821static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses[] = {
5822  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5823  nullptr
5824};
5825
5826static const TargetRegisterClass *const GR32_ABCD_and_GR32_BSISuperclasses[] = {
5827  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5828  &X86::LOW32_ADDR_ACCESSRegClass,
5829  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5830  &X86::GR32RegClass,
5831  &X86::GR32_NOSPRegClass,
5832  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5833  &X86::GR32_NOREXRegClass,
5834  &X86::GR32_NOREX_NOSPRegClass,
5835  &X86::GR32_ABCDRegClass,
5836  &X86::GR32_BSIRegClass,
5837  &X86::GR32_CBRegClass,
5838  nullptr
5839};
5840
5841static const TargetRegisterClass *const GR32_AD_and_GR32_DCSuperclasses[] = {
5842  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5843  &X86::LOW32_ADDR_ACCESSRegClass,
5844  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5845  &X86::GR32RegClass,
5846  &X86::GR32_NOSPRegClass,
5847  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5848  &X86::GR32_NOREXRegClass,
5849  &X86::GR32_NOREX_NOSPRegClass,
5850  &X86::GR32_ABCDRegClass,
5851  &X86::GR32_TCRegClass,
5852  &X86::GR32_ABCD_and_GR32_TCRegClass,
5853  &X86::GR32_ADRegClass,
5854  &X86::GR32_DCRegClass,
5855  nullptr
5856};
5857
5858static const TargetRegisterClass *const GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
5859  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5860  &X86::LOW32_ADDR_ACCESSRegClass,
5861  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5862  &X86::GR32RegClass,
5863  &X86::GR32_NOSPRegClass,
5864  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5865  &X86::GR32_NOREXRegClass,
5866  &X86::GR32_NOREX_NOSPRegClass,
5867  &X86::GR32_BPSPRegClass,
5868  &X86::GR32_DIBPRegClass,
5869  nullptr
5870};
5871
5872static const TargetRegisterClass *const GR32_BPSP_and_GR32_TCSuperclasses[] = {
5873  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5874  &X86::LOW32_ADDR_ACCESSRegClass,
5875  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5876  &X86::GR32RegClass,
5877  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5878  &X86::GR32_NOREXRegClass,
5879  &X86::GR32_TCRegClass,
5880  &X86::GR32_BPSPRegClass,
5881  nullptr
5882};
5883
5884static const TargetRegisterClass *const GR32_BSI_and_GR32_SIDISuperclasses[] = {
5885  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5886  &X86::LOW32_ADDR_ACCESSRegClass,
5887  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5888  &X86::GR32RegClass,
5889  &X86::GR32_NOSPRegClass,
5890  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5891  &X86::GR32_NOREXRegClass,
5892  &X86::GR32_NOREX_NOSPRegClass,
5893  &X86::GR32_BSIRegClass,
5894  &X86::GR32_SIDIRegClass,
5895  nullptr
5896};
5897
5898static const TargetRegisterClass *const GR32_CB_and_GR32_DCSuperclasses[] = {
5899  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5900  &X86::LOW32_ADDR_ACCESSRegClass,
5901  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5902  &X86::GR32RegClass,
5903  &X86::GR32_NOSPRegClass,
5904  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5905  &X86::GR32_NOREXRegClass,
5906  &X86::GR32_NOREX_NOSPRegClass,
5907  &X86::GR32_ABCDRegClass,
5908  &X86::GR32_TCRegClass,
5909  &X86::GR32_ABCD_and_GR32_TCRegClass,
5910  &X86::GR32_CBRegClass,
5911  &X86::GR32_DCRegClass,
5912  nullptr
5913};
5914
5915static const TargetRegisterClass *const GR32_DIBP_and_GR32_SIDISuperclasses[] = {
5916  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5917  &X86::LOW32_ADDR_ACCESSRegClass,
5918  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5919  &X86::GR32RegClass,
5920  &X86::GR32_NOSPRegClass,
5921  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5922  &X86::GR32_NOREXRegClass,
5923  &X86::GR32_NOREX_NOSPRegClass,
5924  &X86::GR32_DIBPRegClass,
5925  &X86::GR32_SIDIRegClass,
5926  nullptr
5927};
5928
5929static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses[] = {
5930  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5931  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5932  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5933  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
5934  nullptr
5935};
5936
5937static const TargetRegisterClass *const LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses[] = {
5938  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5939  &X86::LOW32_ADDR_ACCESSRegClass,
5940  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
5941  nullptr
5942};
5943
5944static const TargetRegisterClass *const RFP64Superclasses[] = {
5945  &X86::RFP32RegClass,
5946  nullptr
5947};
5948
5949static const TargetRegisterClass *const FR64XSuperclasses[] = {
5950  &X86::FR16XRegClass,
5951  &X86::FR32XRegClass,
5952  nullptr
5953};
5954
5955static const TargetRegisterClass *const FR64Superclasses[] = {
5956  &X86::FR16XRegClass,
5957  &X86::FR16RegClass,
5958  &X86::FR32XRegClass,
5959  &X86::FR32RegClass,
5960  &X86::FR64XRegClass,
5961  nullptr
5962};
5963
5964static const TargetRegisterClass *const GR64_with_sub_8bitSuperclasses[] = {
5965  &X86::GR64RegClass,
5966  nullptr
5967};
5968
5969static const TargetRegisterClass *const GR64_NOSPSuperclasses[] = {
5970  &X86::GR64RegClass,
5971  &X86::GR64_with_sub_8bitRegClass,
5972  nullptr
5973};
5974
5975static const TargetRegisterClass *const GR64PLTSafeSuperclasses[] = {
5976  &X86::GR64RegClass,
5977  &X86::GR64_with_sub_8bitRegClass,
5978  &X86::GR64_NOSPRegClass,
5979  nullptr
5980};
5981
5982static const TargetRegisterClass *const GR64_TCSuperclasses[] = {
5983  &X86::GR64RegClass,
5984  nullptr
5985};
5986
5987static const TargetRegisterClass *const GR64_NOREXSuperclasses[] = {
5988  &X86::GR64RegClass,
5989  nullptr
5990};
5991
5992static const TargetRegisterClass *const GR64_TCW64Superclasses[] = {
5993  &X86::GR64RegClass,
5994  nullptr
5995};
5996
5997static const TargetRegisterClass *const GR64_TC_with_sub_8bitSuperclasses[] = {
5998  &X86::GR64RegClass,
5999  &X86::GR64_with_sub_8bitRegClass,
6000  &X86::GR64_TCRegClass,
6001  nullptr
6002};
6003
6004static const TargetRegisterClass *const GR64_NOSP_and_GR64_TCSuperclasses[] = {
6005  &X86::GR64RegClass,
6006  &X86::GR64_with_sub_8bitRegClass,
6007  &X86::GR64_NOSPRegClass,
6008  &X86::GR64_TCRegClass,
6009  &X86::GR64_TC_with_sub_8bitRegClass,
6010  nullptr
6011};
6012
6013static const TargetRegisterClass *const GR64_TCW64_with_sub_8bitSuperclasses[] = {
6014  &X86::GR64RegClass,
6015  &X86::GR64_with_sub_8bitRegClass,
6016  &X86::GR64_TCW64RegClass,
6017  nullptr
6018};
6019
6020static const TargetRegisterClass *const GR64_TC_and_GR64_TCW64Superclasses[] = {
6021  &X86::GR64RegClass,
6022  &X86::GR64_TCRegClass,
6023  &X86::GR64_TCW64RegClass,
6024  nullptr
6025};
6026
6027static const TargetRegisterClass *const GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
6028  &X86::GR64RegClass,
6029  &X86::GR64_with_sub_8bitRegClass,
6030  &X86::GR64_NOREXRegClass,
6031  nullptr
6032};
6033
6034static const TargetRegisterClass *const VK64Superclasses[] = {
6035  &X86::VK1RegClass,
6036  &X86::VK16RegClass,
6037  &X86::VK2RegClass,
6038  &X86::VK4RegClass,
6039  &X86::VK8RegClass,
6040  &X86::VK32RegClass,
6041  nullptr
6042};
6043
6044static const TargetRegisterClass *const GR64PLTSafe_and_GR64_TCSuperclasses[] = {
6045  &X86::GR64RegClass,
6046  &X86::GR64_with_sub_8bitRegClass,
6047  &X86::GR64_NOSPRegClass,
6048  &X86::GR64PLTSafeRegClass,
6049  &X86::GR64_TCRegClass,
6050  &X86::GR64_TC_with_sub_8bitRegClass,
6051  &X86::GR64_NOSP_and_GR64_TCRegClass,
6052  nullptr
6053};
6054
6055static const TargetRegisterClass *const GR64_NOREX_NOSPSuperclasses[] = {
6056  &X86::GR64RegClass,
6057  &X86::GR64_with_sub_8bitRegClass,
6058  &X86::GR64_NOSPRegClass,
6059  &X86::GR64PLTSafeRegClass,
6060  &X86::GR64_NOREXRegClass,
6061  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6062  nullptr
6063};
6064
6065static const TargetRegisterClass *const GR64_NOREX_and_GR64_TCSuperclasses[] = {
6066  &X86::GR64RegClass,
6067  &X86::GR64_TCRegClass,
6068  &X86::GR64_NOREXRegClass,
6069  nullptr
6070};
6071
6072static const TargetRegisterClass *const GR64_NOSP_and_GR64_TCW64Superclasses[] = {
6073  &X86::GR64RegClass,
6074  &X86::GR64_with_sub_8bitRegClass,
6075  &X86::GR64_NOSPRegClass,
6076  &X86::GR64_TCW64RegClass,
6077  &X86::GR64_TCW64_with_sub_8bitRegClass,
6078  nullptr
6079};
6080
6081static const TargetRegisterClass *const GR64_TCW64_and_GR64_TC_with_sub_8bitSuperclasses[] = {
6082  &X86::GR64RegClass,
6083  &X86::GR64_with_sub_8bitRegClass,
6084  &X86::GR64_TCRegClass,
6085  &X86::GR64_TCW64RegClass,
6086  &X86::GR64_TC_with_sub_8bitRegClass,
6087  &X86::GR64_TCW64_with_sub_8bitRegClass,
6088  &X86::GR64_TC_and_GR64_TCW64RegClass,
6089  nullptr
6090};
6091
6092static const TargetRegisterClass *const VK64WMSuperclasses[] = {
6093  &X86::VK1RegClass,
6094  &X86::VK16RegClass,
6095  &X86::VK2RegClass,
6096  &X86::VK4RegClass,
6097  &X86::VK8RegClass,
6098  &X86::VK16WMRegClass,
6099  &X86::VK1WMRegClass,
6100  &X86::VK2WMRegClass,
6101  &X86::VK4WMRegClass,
6102  &X86::VK8WMRegClass,
6103  &X86::VK32RegClass,
6104  &X86::VK32WMRegClass,
6105  &X86::VK64RegClass,
6106  nullptr
6107};
6108
6109static const TargetRegisterClass *const GR64_TC_and_GR64_NOSP_and_GR64_TCW64Superclasses[] = {
6110  &X86::GR64RegClass,
6111  &X86::GR64_with_sub_8bitRegClass,
6112  &X86::GR64_NOSPRegClass,
6113  &X86::GR64_TCRegClass,
6114  &X86::GR64_TCW64RegClass,
6115  &X86::GR64_TC_with_sub_8bitRegClass,
6116  &X86::GR64_NOSP_and_GR64_TCRegClass,
6117  &X86::GR64_TCW64_with_sub_8bitRegClass,
6118  &X86::GR64_TC_and_GR64_TCW64RegClass,
6119  &X86::GR64_NOSP_and_GR64_TCW64RegClass,
6120  &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
6121  nullptr
6122};
6123
6124static const TargetRegisterClass *const GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
6125  &X86::GR64RegClass,
6126  &X86::GR64_with_sub_8bitRegClass,
6127  &X86::GR64_TCRegClass,
6128  &X86::GR64_NOREXRegClass,
6129  &X86::GR64_TC_with_sub_8bitRegClass,
6130  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6131  &X86::GR64_NOREX_and_GR64_TCRegClass,
6132  nullptr
6133};
6134
6135static const TargetRegisterClass *const GR64PLTSafe_and_GR64_TCW64Superclasses[] = {
6136  &X86::GR64RegClass,
6137  &X86::GR64_with_sub_8bitRegClass,
6138  &X86::GR64_NOSPRegClass,
6139  &X86::GR64PLTSafeRegClass,
6140  &X86::GR64_TCRegClass,
6141  &X86::GR64_TCW64RegClass,
6142  &X86::GR64_TC_with_sub_8bitRegClass,
6143  &X86::GR64_NOSP_and_GR64_TCRegClass,
6144  &X86::GR64_TCW64_with_sub_8bitRegClass,
6145  &X86::GR64_TC_and_GR64_TCW64RegClass,
6146  &X86::GR64PLTSafe_and_GR64_TCRegClass,
6147  &X86::GR64_NOSP_and_GR64_TCW64RegClass,
6148  &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
6149  &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
6150  nullptr
6151};
6152
6153static const TargetRegisterClass *const GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSuperclasses[] = {
6154  &X86::GR64RegClass,
6155  &X86::GR64_with_sub_8bitRegClass,
6156  &X86::GR64_NOSPRegClass,
6157  &X86::GR64PLTSafeRegClass,
6158  &X86::GR64_TCRegClass,
6159  &X86::GR64_NOREXRegClass,
6160  &X86::GR64_TC_with_sub_8bitRegClass,
6161  &X86::GR64_NOSP_and_GR64_TCRegClass,
6162  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6163  &X86::GR64PLTSafe_and_GR64_TCRegClass,
6164  &X86::GR64_NOREX_NOSPRegClass,
6165  &X86::GR64_NOREX_and_GR64_TCRegClass,
6166  &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6167  nullptr
6168};
6169
6170static const TargetRegisterClass *const GR64_NOREX_and_GR64_TCW64Superclasses[] = {
6171  &X86::GR64RegClass,
6172  &X86::GR64_TCRegClass,
6173  &X86::GR64_NOREXRegClass,
6174  &X86::GR64_TCW64RegClass,
6175  &X86::GR64_TC_and_GR64_TCW64RegClass,
6176  &X86::GR64_NOREX_and_GR64_TCRegClass,
6177  nullptr
6178};
6179
6180static const TargetRegisterClass *const GR64_ABCDSuperclasses[] = {
6181  &X86::GR64RegClass,
6182  &X86::GR64_with_sub_8bitRegClass,
6183  &X86::GR64_NOSPRegClass,
6184  &X86::GR64PLTSafeRegClass,
6185  &X86::GR64_NOREXRegClass,
6186  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6187  &X86::GR64_NOREX_NOSPRegClass,
6188  nullptr
6189};
6190
6191static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_TCSuperclasses[] = {
6192  &X86::GR64RegClass,
6193  &X86::GR64_with_sub_8bitRegClass,
6194  &X86::GR64_TCRegClass,
6195  &X86::GR64_NOREXRegClass,
6196  &X86::GR64_TCW64RegClass,
6197  &X86::GR64_TC_with_sub_8bitRegClass,
6198  &X86::GR64_TCW64_with_sub_8bitRegClass,
6199  &X86::GR64_TC_and_GR64_TCW64RegClass,
6200  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6201  &X86::GR64_NOREX_and_GR64_TCRegClass,
6202  &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
6203  &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6204  &X86::GR64_NOREX_and_GR64_TCW64RegClass,
6205  nullptr
6206};
6207
6208static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSuperclasses[] = {
6209  &X86::GR64RegClass,
6210  &X86::GR64_with_sub_8bitRegClass,
6211  &X86::GR64_NOSPRegClass,
6212  &X86::GR64PLTSafeRegClass,
6213  &X86::GR64_TCRegClass,
6214  &X86::GR64_NOREXRegClass,
6215  &X86::GR64_TCW64RegClass,
6216  &X86::GR64_TC_with_sub_8bitRegClass,
6217  &X86::GR64_NOSP_and_GR64_TCRegClass,
6218  &X86::GR64_TCW64_with_sub_8bitRegClass,
6219  &X86::GR64_TC_and_GR64_TCW64RegClass,
6220  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6221  &X86::GR64PLTSafe_and_GR64_TCRegClass,
6222  &X86::GR64_NOREX_NOSPRegClass,
6223  &X86::GR64_NOREX_and_GR64_TCRegClass,
6224  &X86::GR64_NOSP_and_GR64_TCW64RegClass,
6225  &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
6226  &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
6227  &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6228  &X86::GR64PLTSafe_and_GR64_TCW64RegClass,
6229  &X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
6230  &X86::GR64_NOREX_and_GR64_TCW64RegClass,
6231  &X86::GR64_ABCDRegClass,
6232  &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
6233  nullptr
6234};
6235
6236static const TargetRegisterClass *const GR64_ADSuperclasses[] = {
6237  &X86::GR64RegClass,
6238  &X86::GR64_with_sub_8bitRegClass,
6239  &X86::GR64_NOSPRegClass,
6240  &X86::GR64PLTSafeRegClass,
6241  &X86::GR64_TCRegClass,
6242  &X86::GR64_NOREXRegClass,
6243  &X86::GR64_TCW64RegClass,
6244  &X86::GR64_TC_with_sub_8bitRegClass,
6245  &X86::GR64_NOSP_and_GR64_TCRegClass,
6246  &X86::GR64_TCW64_with_sub_8bitRegClass,
6247  &X86::GR64_TC_and_GR64_TCW64RegClass,
6248  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6249  &X86::GR64PLTSafe_and_GR64_TCRegClass,
6250  &X86::GR64_NOREX_NOSPRegClass,
6251  &X86::GR64_NOREX_and_GR64_TCRegClass,
6252  &X86::GR64_NOSP_and_GR64_TCW64RegClass,
6253  &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
6254  &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
6255  &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6256  &X86::GR64PLTSafe_and_GR64_TCW64RegClass,
6257  &X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
6258  &X86::GR64_NOREX_and_GR64_TCW64RegClass,
6259  &X86::GR64_ABCDRegClass,
6260  &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
6261  &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
6262  nullptr
6263};
6264
6265static const TargetRegisterClass *const GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses[] = {
6266  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6267  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
6268  &X86::GR64RegClass,
6269  &X86::GR64_NOREXRegClass,
6270  nullptr
6271};
6272
6273static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BPSPSuperclasses[] = {
6274  &X86::GR64RegClass,
6275  &X86::GR64_with_sub_8bitRegClass,
6276  &X86::GR64_NOREXRegClass,
6277  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6278  nullptr
6279};
6280
6281static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BSISuperclasses[] = {
6282  &X86::GR64RegClass,
6283  &X86::GR64_with_sub_8bitRegClass,
6284  &X86::GR64_NOSPRegClass,
6285  &X86::GR64PLTSafeRegClass,
6286  &X86::GR64_NOREXRegClass,
6287  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6288  &X86::GR64_NOREX_NOSPRegClass,
6289  nullptr
6290};
6291
6292static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_CBSuperclasses[] = {
6293  &X86::GR64RegClass,
6294  &X86::GR64_with_sub_8bitRegClass,
6295  &X86::GR64_NOSPRegClass,
6296  &X86::GR64PLTSafeRegClass,
6297  &X86::GR64_NOREXRegClass,
6298  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6299  &X86::GR64_NOREX_NOSPRegClass,
6300  &X86::GR64_ABCDRegClass,
6301  nullptr
6302};
6303
6304static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_DCSuperclasses[] = {
6305  &X86::GR64RegClass,
6306  &X86::GR64_with_sub_8bitRegClass,
6307  &X86::GR64_NOSPRegClass,
6308  &X86::GR64PLTSafeRegClass,
6309  &X86::GR64_TCRegClass,
6310  &X86::GR64_NOREXRegClass,
6311  &X86::GR64_TCW64RegClass,
6312  &X86::GR64_TC_with_sub_8bitRegClass,
6313  &X86::GR64_NOSP_and_GR64_TCRegClass,
6314  &X86::GR64_TCW64_with_sub_8bitRegClass,
6315  &X86::GR64_TC_and_GR64_TCW64RegClass,
6316  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6317  &X86::GR64PLTSafe_and_GR64_TCRegClass,
6318  &X86::GR64_NOREX_NOSPRegClass,
6319  &X86::GR64_NOREX_and_GR64_TCRegClass,
6320  &X86::GR64_NOSP_and_GR64_TCW64RegClass,
6321  &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
6322  &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
6323  &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6324  &X86::GR64PLTSafe_and_GR64_TCW64RegClass,
6325  &X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
6326  &X86::GR64_NOREX_and_GR64_TCW64RegClass,
6327  &X86::GR64_ABCDRegClass,
6328  &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
6329  &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
6330  nullptr
6331};
6332
6333static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_DIBPSuperclasses[] = {
6334  &X86::GR64RegClass,
6335  &X86::GR64_with_sub_8bitRegClass,
6336  &X86::GR64_NOSPRegClass,
6337  &X86::GR64PLTSafeRegClass,
6338  &X86::GR64_NOREXRegClass,
6339  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6340  &X86::GR64_NOREX_NOSPRegClass,
6341  nullptr
6342};
6343
6344static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_SIDISuperclasses[] = {
6345  &X86::GR64RegClass,
6346  &X86::GR64_with_sub_8bitRegClass,
6347  &X86::GR64_NOSPRegClass,
6348  &X86::GR64PLTSafeRegClass,
6349  &X86::GR64_TCRegClass,
6350  &X86::GR64_NOREXRegClass,
6351  &X86::GR64_TC_with_sub_8bitRegClass,
6352  &X86::GR64_NOSP_and_GR64_TCRegClass,
6353  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6354  &X86::GR64PLTSafe_and_GR64_TCRegClass,
6355  &X86::GR64_NOREX_NOSPRegClass,
6356  &X86::GR64_NOREX_and_GR64_TCRegClass,
6357  &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6358  &X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
6359  nullptr
6360};
6361
6362static const TargetRegisterClass *const GR64_and_LOW32_ADDR_ACCESSSuperclasses[] = {
6363  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6364  &X86::LOW32_ADDR_ACCESSRegClass,
6365  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
6366  &X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClass,
6367  &X86::GR64RegClass,
6368  &X86::GR64_TCRegClass,
6369  &X86::GR64_NOREXRegClass,
6370  &X86::GR64_TCW64RegClass,
6371  &X86::GR64_TC_and_GR64_TCW64RegClass,
6372  &X86::GR64_NOREX_and_GR64_TCRegClass,
6373  &X86::GR64_NOREX_and_GR64_TCW64RegClass,
6374  &X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClass,
6375  nullptr
6376};
6377
6378static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISuperclasses[] = {
6379  &X86::GR64RegClass,
6380  &X86::GR64_with_sub_8bitRegClass,
6381  &X86::GR64_NOSPRegClass,
6382  &X86::GR64PLTSafeRegClass,
6383  &X86::GR64_NOREXRegClass,
6384  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6385  &X86::GR64_NOREX_NOSPRegClass,
6386  &X86::GR64_ABCDRegClass,
6387  &X86::GR64_with_sub_32bit_in_GR32_BSIRegClass,
6388  &X86::GR64_with_sub_32bit_in_GR32_CBRegClass,
6389  nullptr
6390};
6391
6392static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCSuperclasses[] = {
6393  &X86::GR64RegClass,
6394  &X86::GR64_with_sub_8bitRegClass,
6395  &X86::GR64_NOSPRegClass,
6396  &X86::GR64PLTSafeRegClass,
6397  &X86::GR64_TCRegClass,
6398  &X86::GR64_NOREXRegClass,
6399  &X86::GR64_TCW64RegClass,
6400  &X86::GR64_TC_with_sub_8bitRegClass,
6401  &X86::GR64_NOSP_and_GR64_TCRegClass,
6402  &X86::GR64_TCW64_with_sub_8bitRegClass,
6403  &X86::GR64_TC_and_GR64_TCW64RegClass,
6404  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6405  &X86::GR64PLTSafe_and_GR64_TCRegClass,
6406  &X86::GR64_NOREX_NOSPRegClass,
6407  &X86::GR64_NOREX_and_GR64_TCRegClass,
6408  &X86::GR64_NOSP_and_GR64_TCW64RegClass,
6409  &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
6410  &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
6411  &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6412  &X86::GR64PLTSafe_and_GR64_TCW64RegClass,
6413  &X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
6414  &X86::GR64_NOREX_and_GR64_TCW64RegClass,
6415  &X86::GR64_ABCDRegClass,
6416  &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
6417  &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
6418  &X86::GR64_ADRegClass,
6419  &X86::GR64_with_sub_32bit_in_GR32_DCRegClass,
6420  nullptr
6421};
6422
6423static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
6424  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6425  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6426  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
6427  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
6428  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass,
6429  &X86::GR64RegClass,
6430  &X86::GR64_with_sub_8bitRegClass,
6431  &X86::GR64_NOSPRegClass,
6432  &X86::GR64PLTSafeRegClass,
6433  &X86::GR64_NOREXRegClass,
6434  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6435  &X86::GR64_NOREX_NOSPRegClass,
6436  &X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClass,
6437  &X86::GR64_with_sub_32bit_in_GR32_BPSPRegClass,
6438  &X86::GR64_with_sub_32bit_in_GR32_DIBPRegClass,
6439  nullptr
6440};
6441
6442static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSuperclasses[] = {
6443  &X86::GR64RegClass,
6444  &X86::GR64_with_sub_8bitRegClass,
6445  &X86::GR64_TCRegClass,
6446  &X86::GR64_NOREXRegClass,
6447  &X86::GR64_TCW64RegClass,
6448  &X86::GR64_TC_with_sub_8bitRegClass,
6449  &X86::GR64_TCW64_with_sub_8bitRegClass,
6450  &X86::GR64_TC_and_GR64_TCW64RegClass,
6451  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6452  &X86::GR64_NOREX_and_GR64_TCRegClass,
6453  &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
6454  &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6455  &X86::GR64_NOREX_and_GR64_TCW64RegClass,
6456  &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
6457  &X86::GR64_with_sub_32bit_in_GR32_BPSPRegClass,
6458  nullptr
6459};
6460
6461static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISuperclasses[] = {
6462  &X86::GR64RegClass,
6463  &X86::GR64_with_sub_8bitRegClass,
6464  &X86::GR64_NOSPRegClass,
6465  &X86::GR64PLTSafeRegClass,
6466  &X86::GR64_TCRegClass,
6467  &X86::GR64_NOREXRegClass,
6468  &X86::GR64_TC_with_sub_8bitRegClass,
6469  &X86::GR64_NOSP_and_GR64_TCRegClass,
6470  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6471  &X86::GR64PLTSafe_and_GR64_TCRegClass,
6472  &X86::GR64_NOREX_NOSPRegClass,
6473  &X86::GR64_NOREX_and_GR64_TCRegClass,
6474  &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6475  &X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
6476  &X86::GR64_with_sub_32bit_in_GR32_BSIRegClass,
6477  &X86::GR64_with_sub_32bit_in_GR32_SIDIRegClass,
6478  nullptr
6479};
6480
6481static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCSuperclasses[] = {
6482  &X86::GR64RegClass,
6483  &X86::GR64_with_sub_8bitRegClass,
6484  &X86::GR64_NOSPRegClass,
6485  &X86::GR64PLTSafeRegClass,
6486  &X86::GR64_TCRegClass,
6487  &X86::GR64_NOREXRegClass,
6488  &X86::GR64_TCW64RegClass,
6489  &X86::GR64_TC_with_sub_8bitRegClass,
6490  &X86::GR64_NOSP_and_GR64_TCRegClass,
6491  &X86::GR64_TCW64_with_sub_8bitRegClass,
6492  &X86::GR64_TC_and_GR64_TCW64RegClass,
6493  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6494  &X86::GR64PLTSafe_and_GR64_TCRegClass,
6495  &X86::GR64_NOREX_NOSPRegClass,
6496  &X86::GR64_NOREX_and_GR64_TCRegClass,
6497  &X86::GR64_NOSP_and_GR64_TCW64RegClass,
6498  &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
6499  &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
6500  &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6501  &X86::GR64PLTSafe_and_GR64_TCW64RegClass,
6502  &X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
6503  &X86::GR64_NOREX_and_GR64_TCW64RegClass,
6504  &X86::GR64_ABCDRegClass,
6505  &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
6506  &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
6507  &X86::GR64_with_sub_32bit_in_GR32_CBRegClass,
6508  &X86::GR64_with_sub_32bit_in_GR32_DCRegClass,
6509  nullptr
6510};
6511
6512static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISuperclasses[] = {
6513  &X86::GR64RegClass,
6514  &X86::GR64_with_sub_8bitRegClass,
6515  &X86::GR64_NOSPRegClass,
6516  &X86::GR64PLTSafeRegClass,
6517  &X86::GR64_TCRegClass,
6518  &X86::GR64_NOREXRegClass,
6519  &X86::GR64_TC_with_sub_8bitRegClass,
6520  &X86::GR64_NOSP_and_GR64_TCRegClass,
6521  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6522  &X86::GR64PLTSafe_and_GR64_TCRegClass,
6523  &X86::GR64_NOREX_NOSPRegClass,
6524  &X86::GR64_NOREX_and_GR64_TCRegClass,
6525  &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
6526  &X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
6527  &X86::GR64_with_sub_32bit_in_GR32_DIBPRegClass,
6528  &X86::GR64_with_sub_32bit_in_GR32_SIDIRegClass,
6529  nullptr
6530};
6531
6532static const TargetRegisterClass *const RFP80Superclasses[] = {
6533  &X86::RFP32RegClass,
6534  &X86::RFP64RegClass,
6535  nullptr
6536};
6537
6538static const TargetRegisterClass *const VR128XSuperclasses[] = {
6539  &X86::FR16XRegClass,
6540  &X86::FR32XRegClass,
6541  &X86::FR64XRegClass,
6542  nullptr
6543};
6544
6545static const TargetRegisterClass *const VR128Superclasses[] = {
6546  &X86::FR16XRegClass,
6547  &X86::FR16RegClass,
6548  &X86::FR32XRegClass,
6549  &X86::FR32RegClass,
6550  &X86::FR64XRegClass,
6551  &X86::FR64RegClass,
6552  &X86::VR128XRegClass,
6553  nullptr
6554};
6555
6556static const TargetRegisterClass *const VR256Superclasses[] = {
6557  &X86::VR256XRegClass,
6558  nullptr
6559};
6560
6561static const TargetRegisterClass *const VR512_0_15Superclasses[] = {
6562  &X86::VR512RegClass,
6563  nullptr
6564};
6565
6566
6567static inline unsigned GR8AltOrderSelect(const MachineFunction &MF) {
6568    return MF.getSubtarget<X86Subtarget>().is64Bit();
6569  }
6570
6571static ArrayRef<MCPhysReg> GR8GetRawAllocationOrder(const MachineFunction &MF) {
6572  static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B };
6573  const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8RegClassID];
6574  const ArrayRef<MCPhysReg> Order[] = {
6575    ArrayRef(MCR.begin(), MCR.getNumRegs()),
6576    ArrayRef(AltOrder1)
6577  };
6578  const unsigned Select = GR8AltOrderSelect(MF);
6579  assert(Select < 2);
6580  return Order[Select];
6581}
6582
6583static inline unsigned GR8_NOREXAltOrderSelect(const MachineFunction &MF) {
6584    return MF.getSubtarget<X86Subtarget>().is64Bit();
6585  }
6586
6587static ArrayRef<MCPhysReg> GR8_NOREXGetRawAllocationOrder(const MachineFunction &MF) {
6588  static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL };
6589  const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8_NOREXRegClassID];
6590  const ArrayRef<MCPhysReg> Order[] = {
6591    ArrayRef(MCR.begin(), MCR.getNumRegs()),
6592    ArrayRef(AltOrder1)
6593  };
6594  const unsigned Select = GR8_NOREXAltOrderSelect(MF);
6595  assert(Select < 2);
6596  return Order[Select];
6597}
6598
6599namespace X86 {   // Register class instances
6600  extern const TargetRegisterClass GR8RegClass = {
6601    &X86MCRegisterClasses[GR8RegClassID],
6602    GR8SubClassMask,
6603    SuperRegIdxSeqs + 2,
6604    LaneBitmask(0x0000000000000001),
6605    0,
6606    false,
6607    0x00, /* TSFlags */
6608    false, /* HasDisjunctSubRegs */
6609    false, /* CoveredBySubRegs */
6610    NullRegClasses,
6611    GR8GetRawAllocationOrder
6612  };
6613
6614  extern const TargetRegisterClass GRH8RegClass = {
6615    &X86MCRegisterClasses[GRH8RegClassID],
6616    GRH8SubClassMask,
6617    SuperRegIdxSeqs + 1,
6618    LaneBitmask(0x0000000000000001),
6619    0,
6620    false,
6621    0x00, /* TSFlags */
6622    false, /* HasDisjunctSubRegs */
6623    false, /* CoveredBySubRegs */
6624    NullRegClasses,
6625    nullptr
6626  };
6627
6628  extern const TargetRegisterClass GR8_NOREXRegClass = {
6629    &X86MCRegisterClasses[GR8_NOREXRegClassID],
6630    GR8_NOREXSubClassMask,
6631    SuperRegIdxSeqs + 2,
6632    LaneBitmask(0x0000000000000001),
6633    0,
6634    false,
6635    0x00, /* TSFlags */
6636    false, /* HasDisjunctSubRegs */
6637    false, /* CoveredBySubRegs */
6638    GR8_NOREXSuperclasses,
6639    GR8_NOREXGetRawAllocationOrder
6640  };
6641
6642  extern const TargetRegisterClass GR8_ABCD_HRegClass = {
6643    &X86MCRegisterClasses[GR8_ABCD_HRegClassID],
6644    GR8_ABCD_HSubClassMask,
6645    SuperRegIdxSeqs + 3,
6646    LaneBitmask(0x0000000000000001),
6647    0,
6648    false,
6649    0x00, /* TSFlags */
6650    false, /* HasDisjunctSubRegs */
6651    false, /* CoveredBySubRegs */
6652    GR8_ABCD_HSuperclasses,
6653    nullptr
6654  };
6655
6656  extern const TargetRegisterClass GR8_ABCD_LRegClass = {
6657    &X86MCRegisterClasses[GR8_ABCD_LRegClassID],
6658    GR8_ABCD_LSubClassMask,
6659    SuperRegIdxSeqs + 0,
6660    LaneBitmask(0x0000000000000001),
6661    0,
6662    false,
6663    0x00, /* TSFlags */
6664    false, /* HasDisjunctSubRegs */
6665    false, /* CoveredBySubRegs */
6666    GR8_ABCD_LSuperclasses,
6667    nullptr
6668  };
6669
6670  extern const TargetRegisterClass GRH16RegClass = {
6671    &X86MCRegisterClasses[GRH16RegClassID],
6672    GRH16SubClassMask,
6673    SuperRegIdxSeqs + 1,
6674    LaneBitmask(0x0000000000000001),
6675    0,
6676    false,
6677    0x00, /* TSFlags */
6678    false, /* HasDisjunctSubRegs */
6679    false, /* CoveredBySubRegs */
6680    NullRegClasses,
6681    nullptr
6682  };
6683
6684  extern const TargetRegisterClass GR16RegClass = {
6685    &X86MCRegisterClasses[GR16RegClassID],
6686    GR16SubClassMask,
6687    SuperRegIdxSeqs + 5,
6688    LaneBitmask(0x0000000000000003),
6689    0,
6690    false,
6691    0x00, /* TSFlags */
6692    true, /* HasDisjunctSubRegs */
6693    true, /* CoveredBySubRegs */
6694    NullRegClasses,
6695    nullptr
6696  };
6697
6698  extern const TargetRegisterClass GR16_NOREXRegClass = {
6699    &X86MCRegisterClasses[GR16_NOREXRegClassID],
6700    GR16_NOREXSubClassMask,
6701    SuperRegIdxSeqs + 5,
6702    LaneBitmask(0x0000000000000003),
6703    0,
6704    false,
6705    0x00, /* TSFlags */
6706    true, /* HasDisjunctSubRegs */
6707    true, /* CoveredBySubRegs */
6708    GR16_NOREXSuperclasses,
6709    nullptr
6710  };
6711
6712  extern const TargetRegisterClass VK1RegClass = {
6713    &X86MCRegisterClasses[VK1RegClassID],
6714    VK1SubClassMask,
6715    SuperRegIdxSeqs + 9,
6716    LaneBitmask(0x0000000000000001),
6717    0,
6718    false,
6719    0x00, /* TSFlags */
6720    false, /* HasDisjunctSubRegs */
6721    false, /* CoveredBySubRegs */
6722    VK1Superclasses,
6723    nullptr
6724  };
6725
6726  extern const TargetRegisterClass VK16RegClass = {
6727    &X86MCRegisterClasses[VK16RegClassID],
6728    VK16SubClassMask,
6729    SuperRegIdxSeqs + 9,
6730    LaneBitmask(0x0000000000000001),
6731    0,
6732    false,
6733    0x00, /* TSFlags */
6734    false, /* HasDisjunctSubRegs */
6735    false, /* CoveredBySubRegs */
6736    VK16Superclasses,
6737    nullptr
6738  };
6739
6740  extern const TargetRegisterClass VK2RegClass = {
6741    &X86MCRegisterClasses[VK2RegClassID],
6742    VK2SubClassMask,
6743    SuperRegIdxSeqs + 9,
6744    LaneBitmask(0x0000000000000001),
6745    0,
6746    false,
6747    0x00, /* TSFlags */
6748    false, /* HasDisjunctSubRegs */
6749    false, /* CoveredBySubRegs */
6750    VK2Superclasses,
6751    nullptr
6752  };
6753
6754  extern const TargetRegisterClass VK4RegClass = {
6755    &X86MCRegisterClasses[VK4RegClassID],
6756    VK4SubClassMask,
6757    SuperRegIdxSeqs + 9,
6758    LaneBitmask(0x0000000000000001),
6759    0,
6760    false,
6761    0x00, /* TSFlags */
6762    false, /* HasDisjunctSubRegs */
6763    false, /* CoveredBySubRegs */
6764    VK4Superclasses,
6765    nullptr
6766  };
6767
6768  extern const TargetRegisterClass VK8RegClass = {
6769    &X86MCRegisterClasses[VK8RegClassID],
6770    VK8SubClassMask,
6771    SuperRegIdxSeqs + 9,
6772    LaneBitmask(0x0000000000000001),
6773    0,
6774    false,
6775    0x00, /* TSFlags */
6776    false, /* HasDisjunctSubRegs */
6777    false, /* CoveredBySubRegs */
6778    VK8Superclasses,
6779    nullptr
6780  };
6781
6782  extern const TargetRegisterClass VK16WMRegClass = {
6783    &X86MCRegisterClasses[VK16WMRegClassID],
6784    VK16WMSubClassMask,
6785    SuperRegIdxSeqs + 9,
6786    LaneBitmask(0x0000000000000001),
6787    0,
6788    false,
6789    0x00, /* TSFlags */
6790    false, /* HasDisjunctSubRegs */
6791    false, /* CoveredBySubRegs */
6792    VK16WMSuperclasses,
6793    nullptr
6794  };
6795
6796  extern const TargetRegisterClass VK1WMRegClass = {
6797    &X86MCRegisterClasses[VK1WMRegClassID],
6798    VK1WMSubClassMask,
6799    SuperRegIdxSeqs + 9,
6800    LaneBitmask(0x0000000000000001),
6801    0,
6802    false,
6803    0x00, /* TSFlags */
6804    false, /* HasDisjunctSubRegs */
6805    false, /* CoveredBySubRegs */
6806    VK1WMSuperclasses,
6807    nullptr
6808  };
6809
6810  extern const TargetRegisterClass VK2WMRegClass = {
6811    &X86MCRegisterClasses[VK2WMRegClassID],
6812    VK2WMSubClassMask,
6813    SuperRegIdxSeqs + 9,
6814    LaneBitmask(0x0000000000000001),
6815    0,
6816    false,
6817    0x00, /* TSFlags */
6818    false, /* HasDisjunctSubRegs */
6819    false, /* CoveredBySubRegs */
6820    VK2WMSuperclasses,
6821    nullptr
6822  };
6823
6824  extern const TargetRegisterClass VK4WMRegClass = {
6825    &X86MCRegisterClasses[VK4WMRegClassID],
6826    VK4WMSubClassMask,
6827    SuperRegIdxSeqs + 9,
6828    LaneBitmask(0x0000000000000001),
6829    0,
6830    false,
6831    0x00, /* TSFlags */
6832    false, /* HasDisjunctSubRegs */
6833    false, /* CoveredBySubRegs */
6834    VK4WMSuperclasses,
6835    nullptr
6836  };
6837
6838  extern const TargetRegisterClass VK8WMRegClass = {
6839    &X86MCRegisterClasses[VK8WMRegClassID],
6840    VK8WMSubClassMask,
6841    SuperRegIdxSeqs + 9,
6842    LaneBitmask(0x0000000000000001),
6843    0,
6844    false,
6845    0x00, /* TSFlags */
6846    false, /* HasDisjunctSubRegs */
6847    false, /* CoveredBySubRegs */
6848    VK8WMSuperclasses,
6849    nullptr
6850  };
6851
6852  extern const TargetRegisterClass SEGMENT_REGRegClass = {
6853    &X86MCRegisterClasses[SEGMENT_REGRegClassID],
6854    SEGMENT_REGSubClassMask,
6855    SuperRegIdxSeqs + 1,
6856    LaneBitmask(0x0000000000000001),
6857    0,
6858    false,
6859    0x00, /* TSFlags */
6860    false, /* HasDisjunctSubRegs */
6861    false, /* CoveredBySubRegs */
6862    NullRegClasses,
6863    nullptr
6864  };
6865
6866  extern const TargetRegisterClass GR16_ABCDRegClass = {
6867    &X86MCRegisterClasses[GR16_ABCDRegClassID],
6868    GR16_ABCDSubClassMask,
6869    SuperRegIdxSeqs + 5,
6870    LaneBitmask(0x0000000000000003),
6871    0,
6872    false,
6873    0x00, /* TSFlags */
6874    true, /* HasDisjunctSubRegs */
6875    true, /* CoveredBySubRegs */
6876    GR16_ABCDSuperclasses,
6877    nullptr
6878  };
6879
6880  extern const TargetRegisterClass FPCCRRegClass = {
6881    &X86MCRegisterClasses[FPCCRRegClassID],
6882    FPCCRSubClassMask,
6883    SuperRegIdxSeqs + 1,
6884    LaneBitmask(0x0000000000000001),
6885    0,
6886    false,
6887    0x00, /* TSFlags */
6888    false, /* HasDisjunctSubRegs */
6889    false, /* CoveredBySubRegs */
6890    NullRegClasses,
6891    nullptr
6892  };
6893
6894  extern const TargetRegisterClass FR16XRegClass = {
6895    &X86MCRegisterClasses[FR16XRegClassID],
6896    FR16XSubClassMask,
6897    SuperRegIdxSeqs + 12,
6898    LaneBitmask(0x0000000000000001),
6899    0,
6900    false,
6901    0x00, /* TSFlags */
6902    false, /* HasDisjunctSubRegs */
6903    false, /* CoveredBySubRegs */
6904    NullRegClasses,
6905    nullptr
6906  };
6907
6908  extern const TargetRegisterClass FR16RegClass = {
6909    &X86MCRegisterClasses[FR16RegClassID],
6910    FR16SubClassMask,
6911    SuperRegIdxSeqs + 12,
6912    LaneBitmask(0x0000000000000001),
6913    0,
6914    false,
6915    0x00, /* TSFlags */
6916    false, /* HasDisjunctSubRegs */
6917    false, /* CoveredBySubRegs */
6918    FR16Superclasses,
6919    nullptr
6920  };
6921
6922  extern const TargetRegisterClass VK16PAIRRegClass = {
6923    &X86MCRegisterClasses[VK16PAIRRegClassID],
6924    VK16PAIRSubClassMask,
6925    SuperRegIdxSeqs + 1,
6926    LaneBitmask(0x0000000000000030),
6927    0,
6928    false,
6929    0x00, /* TSFlags */
6930    true, /* HasDisjunctSubRegs */
6931    true, /* CoveredBySubRegs */
6932    VK16PAIRSuperclasses,
6933    nullptr
6934  };
6935
6936  extern const TargetRegisterClass VK1PAIRRegClass = {
6937    &X86MCRegisterClasses[VK1PAIRRegClassID],
6938    VK1PAIRSubClassMask,
6939    SuperRegIdxSeqs + 1,
6940    LaneBitmask(0x0000000000000030),
6941    0,
6942    false,
6943    0x00, /* TSFlags */
6944    true, /* HasDisjunctSubRegs */
6945    true, /* CoveredBySubRegs */
6946    VK1PAIRSuperclasses,
6947    nullptr
6948  };
6949
6950  extern const TargetRegisterClass VK2PAIRRegClass = {
6951    &X86MCRegisterClasses[VK2PAIRRegClassID],
6952    VK2PAIRSubClassMask,
6953    SuperRegIdxSeqs + 1,
6954    LaneBitmask(0x0000000000000030),
6955    0,
6956    false,
6957    0x00, /* TSFlags */
6958    true, /* HasDisjunctSubRegs */
6959    true, /* CoveredBySubRegs */
6960    VK2PAIRSuperclasses,
6961    nullptr
6962  };
6963
6964  extern const TargetRegisterClass VK4PAIRRegClass = {
6965    &X86MCRegisterClasses[VK4PAIRRegClassID],
6966    VK4PAIRSubClassMask,
6967    SuperRegIdxSeqs + 1,
6968    LaneBitmask(0x0000000000000030),
6969    0,
6970    false,
6971    0x00, /* TSFlags */
6972    true, /* HasDisjunctSubRegs */
6973    true, /* CoveredBySubRegs */
6974    VK4PAIRSuperclasses,
6975    nullptr
6976  };
6977
6978  extern const TargetRegisterClass VK8PAIRRegClass = {
6979    &X86MCRegisterClasses[VK8PAIRRegClassID],
6980    VK8PAIRSubClassMask,
6981    SuperRegIdxSeqs + 1,
6982    LaneBitmask(0x0000000000000030),
6983    0,
6984    false,
6985    0x00, /* TSFlags */
6986    true, /* HasDisjunctSubRegs */
6987    true, /* CoveredBySubRegs */
6988    VK8PAIRSuperclasses,
6989    nullptr
6990  };
6991
6992  extern const TargetRegisterClass VK16PAIR_with_sub_mask_0_in_VK16WMRegClass = {
6993    &X86MCRegisterClasses[VK16PAIR_with_sub_mask_0_in_VK16WMRegClassID],
6994    VK16PAIR_with_sub_mask_0_in_VK16WMSubClassMask,
6995    SuperRegIdxSeqs + 1,
6996    LaneBitmask(0x0000000000000030),
6997    0,
6998    false,
6999    0x00, /* TSFlags */
7000    true, /* HasDisjunctSubRegs */
7001    true, /* CoveredBySubRegs */
7002    VK16PAIR_with_sub_mask_0_in_VK16WMSuperclasses,
7003    nullptr
7004  };
7005
7006  extern const TargetRegisterClass FR32XRegClass = {
7007    &X86MCRegisterClasses[FR32XRegClassID],
7008    FR32XSubClassMask,
7009    SuperRegIdxSeqs + 12,
7010    LaneBitmask(0x0000000000000001),
7011    0,
7012    false,
7013    0x00, /* TSFlags */
7014    false, /* HasDisjunctSubRegs */
7015    false, /* CoveredBySubRegs */
7016    FR32XSuperclasses,
7017    nullptr
7018  };
7019
7020  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass = {
7021    &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBPRegClassID],
7022    LOW32_ADDR_ACCESS_RBPSubClassMask,
7023    SuperRegIdxSeqs + 7,
7024    LaneBitmask(0x000000000000000F),
7025    0,
7026    false,
7027    0x00, /* TSFlags */
7028    true, /* HasDisjunctSubRegs */
7029    false, /* CoveredBySubRegs */
7030    NullRegClasses,
7031    nullptr
7032  };
7033
7034  extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass = {
7035    &X86MCRegisterClasses[LOW32_ADDR_ACCESSRegClassID],
7036    LOW32_ADDR_ACCESSSubClassMask,
7037    SuperRegIdxSeqs + 7,
7038    LaneBitmask(0x000000000000000F),
7039    0,
7040    false,
7041    0x00, /* TSFlags */
7042    true, /* HasDisjunctSubRegs */
7043    false, /* CoveredBySubRegs */
7044    LOW32_ADDR_ACCESSSuperclasses,
7045    nullptr
7046  };
7047
7048  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass = {
7049    &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID],
7050    LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask,
7051    SuperRegIdxSeqs + 7,
7052    LaneBitmask(0x000000000000000F),
7053    0,
7054    false,
7055    0x00, /* TSFlags */
7056    true, /* HasDisjunctSubRegs */
7057    false, /* CoveredBySubRegs */
7058    LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses,
7059    nullptr
7060  };
7061
7062  extern const TargetRegisterClass DEBUG_REGRegClass = {
7063    &X86MCRegisterClasses[DEBUG_REGRegClassID],
7064    DEBUG_REGSubClassMask,
7065    SuperRegIdxSeqs + 1,
7066    LaneBitmask(0x0000000000000001),
7067    0,
7068    false,
7069    0x00, /* TSFlags */
7070    false, /* HasDisjunctSubRegs */
7071    false, /* CoveredBySubRegs */
7072    NullRegClasses,
7073    nullptr
7074  };
7075
7076  extern const TargetRegisterClass FR32RegClass = {
7077    &X86MCRegisterClasses[FR32RegClassID],
7078    FR32SubClassMask,
7079    SuperRegIdxSeqs + 12,
7080    LaneBitmask(0x0000000000000001),
7081    0,
7082    false,
7083    0x00, /* TSFlags */
7084    false, /* HasDisjunctSubRegs */
7085    false, /* CoveredBySubRegs */
7086    FR32Superclasses,
7087    nullptr
7088  };
7089
7090  extern const TargetRegisterClass GR32RegClass = {
7091    &X86MCRegisterClasses[GR32RegClassID],
7092    GR32SubClassMask,
7093    SuperRegIdxSeqs + 7,
7094    LaneBitmask(0x0000000000000007),
7095    0,
7096    false,
7097    0x00, /* TSFlags */
7098    true, /* HasDisjunctSubRegs */
7099    true, /* CoveredBySubRegs */
7100    GR32Superclasses,
7101    nullptr
7102  };
7103
7104  extern const TargetRegisterClass GR32_NOSPRegClass = {
7105    &X86MCRegisterClasses[GR32_NOSPRegClassID],
7106    GR32_NOSPSubClassMask,
7107    SuperRegIdxSeqs + 7,
7108    LaneBitmask(0x0000000000000007),
7109    0,
7110    false,
7111    0x00, /* TSFlags */
7112    true, /* HasDisjunctSubRegs */
7113    true, /* CoveredBySubRegs */
7114    GR32_NOSPSuperclasses,
7115    nullptr
7116  };
7117
7118  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass = {
7119    &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID],
7120    LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask,
7121    SuperRegIdxSeqs + 7,
7122    LaneBitmask(0x000000000000000F),
7123    0,
7124    false,
7125    0x00, /* TSFlags */
7126    true, /* HasDisjunctSubRegs */
7127    false, /* CoveredBySubRegs */
7128    LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses,
7129    nullptr
7130  };
7131
7132  extern const TargetRegisterClass GR32_NOREXRegClass = {
7133    &X86MCRegisterClasses[GR32_NOREXRegClassID],
7134    GR32_NOREXSubClassMask,
7135    SuperRegIdxSeqs + 7,
7136    LaneBitmask(0x0000000000000007),
7137    0,
7138    false,
7139    0x00, /* TSFlags */
7140    true, /* HasDisjunctSubRegs */
7141    true, /* CoveredBySubRegs */
7142    GR32_NOREXSuperclasses,
7143    nullptr
7144  };
7145
7146  extern const TargetRegisterClass VK32RegClass = {
7147    &X86MCRegisterClasses[VK32RegClassID],
7148    VK32SubClassMask,
7149    SuperRegIdxSeqs + 9,
7150    LaneBitmask(0x0000000000000001),
7151    0,
7152    false,
7153    0x00, /* TSFlags */
7154    false, /* HasDisjunctSubRegs */
7155    false, /* CoveredBySubRegs */
7156    VK32Superclasses,
7157    nullptr
7158  };
7159
7160  extern const TargetRegisterClass GR32_NOREX_NOSPRegClass = {
7161    &X86MCRegisterClasses[GR32_NOREX_NOSPRegClassID],
7162    GR32_NOREX_NOSPSubClassMask,
7163    SuperRegIdxSeqs + 7,
7164    LaneBitmask(0x0000000000000007),
7165    0,
7166    false,
7167    0x00, /* TSFlags */
7168    true, /* HasDisjunctSubRegs */
7169    true, /* CoveredBySubRegs */
7170    GR32_NOREX_NOSPSuperclasses,
7171    nullptr
7172  };
7173
7174  extern const TargetRegisterClass RFP32RegClass = {
7175    &X86MCRegisterClasses[RFP32RegClassID],
7176    RFP32SubClassMask,
7177    SuperRegIdxSeqs + 1,
7178    LaneBitmask(0x0000000000000001),
7179    0,
7180    false,
7181    0x00, /* TSFlags */
7182    false, /* HasDisjunctSubRegs */
7183    false, /* CoveredBySubRegs */
7184    NullRegClasses,
7185    nullptr
7186  };
7187
7188  extern const TargetRegisterClass VK32WMRegClass = {
7189    &X86MCRegisterClasses[VK32WMRegClassID],
7190    VK32WMSubClassMask,
7191    SuperRegIdxSeqs + 9,
7192    LaneBitmask(0x0000000000000001),
7193    0,
7194    false,
7195    0x00, /* TSFlags */
7196    false, /* HasDisjunctSubRegs */
7197    false, /* CoveredBySubRegs */
7198    VK32WMSuperclasses,
7199    nullptr
7200  };
7201
7202  extern const TargetRegisterClass GR32_ABCDRegClass = {
7203    &X86MCRegisterClasses[GR32_ABCDRegClassID],
7204    GR32_ABCDSubClassMask,
7205    SuperRegIdxSeqs + 7,
7206    LaneBitmask(0x0000000000000007),
7207    0,
7208    false,
7209    0x00, /* TSFlags */
7210    true, /* HasDisjunctSubRegs */
7211    true, /* CoveredBySubRegs */
7212    GR32_ABCDSuperclasses,
7213    nullptr
7214  };
7215
7216  extern const TargetRegisterClass GR32_TCRegClass = {
7217    &X86MCRegisterClasses[GR32_TCRegClassID],
7218    GR32_TCSubClassMask,
7219    SuperRegIdxSeqs + 7,
7220    LaneBitmask(0x0000000000000007),
7221    0,
7222    false,
7223    0x00, /* TSFlags */
7224    true, /* HasDisjunctSubRegs */
7225    true, /* CoveredBySubRegs */
7226    GR32_TCSuperclasses,
7227    nullptr
7228  };
7229
7230  extern const TargetRegisterClass GR32_ABCD_and_GR32_TCRegClass = {
7231    &X86MCRegisterClasses[GR32_ABCD_and_GR32_TCRegClassID],
7232    GR32_ABCD_and_GR32_TCSubClassMask,
7233    SuperRegIdxSeqs + 7,
7234    LaneBitmask(0x0000000000000007),
7235    0,
7236    false,
7237    0x00, /* TSFlags */
7238    true, /* HasDisjunctSubRegs */
7239    true, /* CoveredBySubRegs */
7240    GR32_ABCD_and_GR32_TCSuperclasses,
7241    nullptr
7242  };
7243
7244  extern const TargetRegisterClass GR32_ADRegClass = {
7245    &X86MCRegisterClasses[GR32_ADRegClassID],
7246    GR32_ADSubClassMask,
7247    SuperRegIdxSeqs + 7,
7248    LaneBitmask(0x0000000000000007),
7249    0,
7250    false,
7251    0x00, /* TSFlags */
7252    true, /* HasDisjunctSubRegs */
7253    true, /* CoveredBySubRegs */
7254    GR32_ADSuperclasses,
7255    nullptr
7256  };
7257
7258  extern const TargetRegisterClass GR32_BPSPRegClass = {
7259    &X86MCRegisterClasses[GR32_BPSPRegClassID],
7260    GR32_BPSPSubClassMask,
7261    SuperRegIdxSeqs + 7,
7262    LaneBitmask(0x0000000000000007),
7263    0,
7264    false,
7265    0x00, /* TSFlags */
7266    true, /* HasDisjunctSubRegs */
7267    true, /* CoveredBySubRegs */
7268    GR32_BPSPSuperclasses,
7269    nullptr
7270  };
7271
7272  extern const TargetRegisterClass GR32_BSIRegClass = {
7273    &X86MCRegisterClasses[GR32_BSIRegClassID],
7274    GR32_BSISubClassMask,
7275    SuperRegIdxSeqs + 7,
7276    LaneBitmask(0x0000000000000007),
7277    0,
7278    false,
7279    0x00, /* TSFlags */
7280    true, /* HasDisjunctSubRegs */
7281    true, /* CoveredBySubRegs */
7282    GR32_BSISuperclasses,
7283    nullptr
7284  };
7285
7286  extern const TargetRegisterClass GR32_CBRegClass = {
7287    &X86MCRegisterClasses[GR32_CBRegClassID],
7288    GR32_CBSubClassMask,
7289    SuperRegIdxSeqs + 7,
7290    LaneBitmask(0x0000000000000007),
7291    0,
7292    false,
7293    0x00, /* TSFlags */
7294    true, /* HasDisjunctSubRegs */
7295    true, /* CoveredBySubRegs */
7296    GR32_CBSuperclasses,
7297    nullptr
7298  };
7299
7300  extern const TargetRegisterClass GR32_DCRegClass = {
7301    &X86MCRegisterClasses[GR32_DCRegClassID],
7302    GR32_DCSubClassMask,
7303    SuperRegIdxSeqs + 7,
7304    LaneBitmask(0x0000000000000007),
7305    0,
7306    false,
7307    0x00, /* TSFlags */
7308    true, /* HasDisjunctSubRegs */
7309    true, /* CoveredBySubRegs */
7310    GR32_DCSuperclasses,
7311    nullptr
7312  };
7313
7314  extern const TargetRegisterClass GR32_DIBPRegClass = {
7315    &X86MCRegisterClasses[GR32_DIBPRegClassID],
7316    GR32_DIBPSubClassMask,
7317    SuperRegIdxSeqs + 7,
7318    LaneBitmask(0x0000000000000007),
7319    0,
7320    false,
7321    0x00, /* TSFlags */
7322    true, /* HasDisjunctSubRegs */
7323    true, /* CoveredBySubRegs */
7324    GR32_DIBPSuperclasses,
7325    nullptr
7326  };
7327
7328  extern const TargetRegisterClass GR32_SIDIRegClass = {
7329    &X86MCRegisterClasses[GR32_SIDIRegClassID],
7330    GR32_SIDISubClassMask,
7331    SuperRegIdxSeqs + 7,
7332    LaneBitmask(0x0000000000000007),
7333    0,
7334    false,
7335    0x00, /* TSFlags */
7336    true, /* HasDisjunctSubRegs */
7337    true, /* CoveredBySubRegs */
7338    GR32_SIDISuperclasses,
7339    nullptr
7340  };
7341
7342  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass = {
7343    &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID],
7344    LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask,
7345    SuperRegIdxSeqs + 1,
7346    LaneBitmask(0x000000000000000F),
7347    0,
7348    false,
7349    0x00, /* TSFlags */
7350    true, /* HasDisjunctSubRegs */
7351    false, /* CoveredBySubRegs */
7352    LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses,
7353    nullptr
7354  };
7355
7356  extern const TargetRegisterClass CCRRegClass = {
7357    &X86MCRegisterClasses[CCRRegClassID],
7358    CCRSubClassMask,
7359    SuperRegIdxSeqs + 1,
7360    LaneBitmask(0x0000000000000001),
7361    0,
7362    false,
7363    0x00, /* TSFlags */
7364    false, /* HasDisjunctSubRegs */
7365    false, /* CoveredBySubRegs */
7366    NullRegClasses,
7367    nullptr
7368  };
7369
7370  extern const TargetRegisterClass DFCCRRegClass = {
7371    &X86MCRegisterClasses[DFCCRRegClassID],
7372    DFCCRSubClassMask,
7373    SuperRegIdxSeqs + 1,
7374    LaneBitmask(0x0000000000000001),
7375    0,
7376    false,
7377    0x00, /* TSFlags */
7378    false, /* HasDisjunctSubRegs */
7379    false, /* CoveredBySubRegs */
7380    NullRegClasses,
7381    nullptr
7382  };
7383
7384  extern const TargetRegisterClass GR32_ABCD_and_GR32_BSIRegClass = {
7385    &X86MCRegisterClasses[GR32_ABCD_and_GR32_BSIRegClassID],
7386    GR32_ABCD_and_GR32_BSISubClassMask,
7387    SuperRegIdxSeqs + 7,
7388    LaneBitmask(0x0000000000000007),
7389    0,
7390    false,
7391    0x00, /* TSFlags */
7392    true, /* HasDisjunctSubRegs */
7393    true, /* CoveredBySubRegs */
7394    GR32_ABCD_and_GR32_BSISuperclasses,
7395    nullptr
7396  };
7397
7398  extern const TargetRegisterClass GR32_AD_and_GR32_DCRegClass = {
7399    &X86MCRegisterClasses[GR32_AD_and_GR32_DCRegClassID],
7400    GR32_AD_and_GR32_DCSubClassMask,
7401    SuperRegIdxSeqs + 7,
7402    LaneBitmask(0x0000000000000007),
7403    0,
7404    false,
7405    0x00, /* TSFlags */
7406    true, /* HasDisjunctSubRegs */
7407    true, /* CoveredBySubRegs */
7408    GR32_AD_and_GR32_DCSuperclasses,
7409    nullptr
7410  };
7411
7412  extern const TargetRegisterClass GR32_BPSP_and_GR32_DIBPRegClass = {
7413    &X86MCRegisterClasses[GR32_BPSP_and_GR32_DIBPRegClassID],
7414    GR32_BPSP_and_GR32_DIBPSubClassMask,
7415    SuperRegIdxSeqs + 7,
7416    LaneBitmask(0x0000000000000007),
7417    0,
7418    false,
7419    0x00, /* TSFlags */
7420    true, /* HasDisjunctSubRegs */
7421    true, /* CoveredBySubRegs */
7422    GR32_BPSP_and_GR32_DIBPSuperclasses,
7423    nullptr
7424  };
7425
7426  extern const TargetRegisterClass GR32_BPSP_and_GR32_TCRegClass = {
7427    &X86MCRegisterClasses[GR32_BPSP_and_GR32_TCRegClassID],
7428    GR32_BPSP_and_GR32_TCSubClassMask,
7429    SuperRegIdxSeqs + 7,
7430    LaneBitmask(0x0000000000000007),
7431    0,
7432    false,
7433    0x00, /* TSFlags */
7434    true, /* HasDisjunctSubRegs */
7435    true, /* CoveredBySubRegs */
7436    GR32_BPSP_and_GR32_TCSuperclasses,
7437    nullptr
7438  };
7439
7440  extern const TargetRegisterClass GR32_BSI_and_GR32_SIDIRegClass = {
7441    &X86MCRegisterClasses[GR32_BSI_and_GR32_SIDIRegClassID],
7442    GR32_BSI_and_GR32_SIDISubClassMask,
7443    SuperRegIdxSeqs + 7,
7444    LaneBitmask(0x0000000000000007),
7445    0,
7446    false,
7447    0x00, /* TSFlags */
7448    true, /* HasDisjunctSubRegs */
7449    true, /* CoveredBySubRegs */
7450    GR32_BSI_and_GR32_SIDISuperclasses,
7451    nullptr
7452  };
7453
7454  extern const TargetRegisterClass GR32_CB_and_GR32_DCRegClass = {
7455    &X86MCRegisterClasses[GR32_CB_and_GR32_DCRegClassID],
7456    GR32_CB_and_GR32_DCSubClassMask,
7457    SuperRegIdxSeqs + 7,
7458    LaneBitmask(0x0000000000000007),
7459    0,
7460    false,
7461    0x00, /* TSFlags */
7462    true, /* HasDisjunctSubRegs */
7463    true, /* CoveredBySubRegs */
7464    GR32_CB_and_GR32_DCSuperclasses,
7465    nullptr
7466  };
7467
7468  extern const TargetRegisterClass GR32_DIBP_and_GR32_SIDIRegClass = {
7469    &X86MCRegisterClasses[GR32_DIBP_and_GR32_SIDIRegClassID],
7470    GR32_DIBP_and_GR32_SIDISubClassMask,
7471    SuperRegIdxSeqs + 7,
7472    LaneBitmask(0x0000000000000007),
7473    0,
7474    false,
7475    0x00, /* TSFlags */
7476    true, /* HasDisjunctSubRegs */
7477    true, /* CoveredBySubRegs */
7478    GR32_DIBP_and_GR32_SIDISuperclasses,
7479    nullptr
7480  };
7481
7482  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass = {
7483    &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID],
7484    LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask,
7485    SuperRegIdxSeqs + 1,
7486    LaneBitmask(0x000000000000000F),
7487    0,
7488    false,
7489    0x00, /* TSFlags */
7490    true, /* HasDisjunctSubRegs */
7491    false, /* CoveredBySubRegs */
7492    LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses,
7493    nullptr
7494  };
7495
7496  extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass = {
7497    &X86MCRegisterClasses[LOW32_ADDR_ACCESS_with_sub_32bitRegClassID],
7498    LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask,
7499    SuperRegIdxSeqs + 1,
7500    LaneBitmask(0x000000000000000F),
7501    0,
7502    false,
7503    0x00, /* TSFlags */
7504    true, /* HasDisjunctSubRegs */
7505    false, /* CoveredBySubRegs */
7506    LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses,
7507    nullptr
7508  };
7509
7510  extern const TargetRegisterClass RFP64RegClass = {
7511    &X86MCRegisterClasses[RFP64RegClassID],
7512    RFP64SubClassMask,
7513    SuperRegIdxSeqs + 1,
7514    LaneBitmask(0x0000000000000001),
7515    0,
7516    false,
7517    0x00, /* TSFlags */
7518    false, /* HasDisjunctSubRegs */
7519    false, /* CoveredBySubRegs */
7520    RFP64Superclasses,
7521    nullptr
7522  };
7523
7524  extern const TargetRegisterClass FR64XRegClass = {
7525    &X86MCRegisterClasses[FR64XRegClassID],
7526    FR64XSubClassMask,
7527    SuperRegIdxSeqs + 12,
7528    LaneBitmask(0x0000000000000001),
7529    0,
7530    false,
7531    0x00, /* TSFlags */
7532    false, /* HasDisjunctSubRegs */
7533    false, /* CoveredBySubRegs */
7534    FR64XSuperclasses,
7535    nullptr
7536  };
7537
7538  extern const TargetRegisterClass GR64RegClass = {
7539    &X86MCRegisterClasses[GR64RegClassID],
7540    GR64SubClassMask,
7541    SuperRegIdxSeqs + 1,
7542    LaneBitmask(0x000000000000000F),
7543    0,
7544    false,
7545    0x00, /* TSFlags */
7546    true, /* HasDisjunctSubRegs */
7547    false, /* CoveredBySubRegs */
7548    NullRegClasses,
7549    nullptr
7550  };
7551
7552  extern const TargetRegisterClass CONTROL_REGRegClass = {
7553    &X86MCRegisterClasses[CONTROL_REGRegClassID],
7554    CONTROL_REGSubClassMask,
7555    SuperRegIdxSeqs + 1,
7556    LaneBitmask(0x0000000000000001),
7557    0,
7558    false,
7559    0x00, /* TSFlags */
7560    false, /* HasDisjunctSubRegs */
7561    false, /* CoveredBySubRegs */
7562    NullRegClasses,
7563    nullptr
7564  };
7565
7566  extern const TargetRegisterClass FR64RegClass = {
7567    &X86MCRegisterClasses[FR64RegClassID],
7568    FR64SubClassMask,
7569    SuperRegIdxSeqs + 12,
7570    LaneBitmask(0x0000000000000001),
7571    0,
7572    false,
7573    0x00, /* TSFlags */
7574    false, /* HasDisjunctSubRegs */
7575    false, /* CoveredBySubRegs */
7576    FR64Superclasses,
7577    nullptr
7578  };
7579
7580  extern const TargetRegisterClass GR64_with_sub_8bitRegClass = {
7581    &X86MCRegisterClasses[GR64_with_sub_8bitRegClassID],
7582    GR64_with_sub_8bitSubClassMask,
7583    SuperRegIdxSeqs + 1,
7584    LaneBitmask(0x000000000000000F),
7585    0,
7586    false,
7587    0x00, /* TSFlags */
7588    true, /* HasDisjunctSubRegs */
7589    false, /* CoveredBySubRegs */
7590    GR64_with_sub_8bitSuperclasses,
7591    nullptr
7592  };
7593
7594  extern const TargetRegisterClass GR64_NOSPRegClass = {
7595    &X86MCRegisterClasses[GR64_NOSPRegClassID],
7596    GR64_NOSPSubClassMask,
7597    SuperRegIdxSeqs + 1,
7598    LaneBitmask(0x000000000000000F),
7599    0,
7600    false,
7601    0x00, /* TSFlags */
7602    true, /* HasDisjunctSubRegs */
7603    false, /* CoveredBySubRegs */
7604    GR64_NOSPSuperclasses,
7605    nullptr
7606  };
7607
7608  extern const TargetRegisterClass GR64PLTSafeRegClass = {
7609    &X86MCRegisterClasses[GR64PLTSafeRegClassID],
7610    GR64PLTSafeSubClassMask,
7611    SuperRegIdxSeqs + 1,
7612    LaneBitmask(0x000000000000000F),
7613    0,
7614    false,
7615    0x00, /* TSFlags */
7616    true, /* HasDisjunctSubRegs */
7617    false, /* CoveredBySubRegs */
7618    GR64PLTSafeSuperclasses,
7619    nullptr
7620  };
7621
7622  extern const TargetRegisterClass GR64_TCRegClass = {
7623    &X86MCRegisterClasses[GR64_TCRegClassID],
7624    GR64_TCSubClassMask,
7625    SuperRegIdxSeqs + 1,
7626    LaneBitmask(0x000000000000000F),
7627    0,
7628    false,
7629    0x00, /* TSFlags */
7630    true, /* HasDisjunctSubRegs */
7631    false, /* CoveredBySubRegs */
7632    GR64_TCSuperclasses,
7633    nullptr
7634  };
7635
7636  extern const TargetRegisterClass GR64_NOREXRegClass = {
7637    &X86MCRegisterClasses[GR64_NOREXRegClassID],
7638    GR64_NOREXSubClassMask,
7639    SuperRegIdxSeqs + 1,
7640    LaneBitmask(0x000000000000000F),
7641    0,
7642    false,
7643    0x00, /* TSFlags */
7644    true, /* HasDisjunctSubRegs */
7645    false, /* CoveredBySubRegs */
7646    GR64_NOREXSuperclasses,
7647    nullptr
7648  };
7649
7650  extern const TargetRegisterClass GR64_TCW64RegClass = {
7651    &X86MCRegisterClasses[GR64_TCW64RegClassID],
7652    GR64_TCW64SubClassMask,
7653    SuperRegIdxSeqs + 1,
7654    LaneBitmask(0x000000000000000F),
7655    0,
7656    false,
7657    0x00, /* TSFlags */
7658    true, /* HasDisjunctSubRegs */
7659    false, /* CoveredBySubRegs */
7660    GR64_TCW64Superclasses,
7661    nullptr
7662  };
7663
7664  extern const TargetRegisterClass GR64_TC_with_sub_8bitRegClass = {
7665    &X86MCRegisterClasses[GR64_TC_with_sub_8bitRegClassID],
7666    GR64_TC_with_sub_8bitSubClassMask,
7667    SuperRegIdxSeqs + 1,
7668    LaneBitmask(0x000000000000000F),
7669    0,
7670    false,
7671    0x00, /* TSFlags */
7672    true, /* HasDisjunctSubRegs */
7673    false, /* CoveredBySubRegs */
7674    GR64_TC_with_sub_8bitSuperclasses,
7675    nullptr
7676  };
7677
7678  extern const TargetRegisterClass GR64_NOSP_and_GR64_TCRegClass = {
7679    &X86MCRegisterClasses[GR64_NOSP_and_GR64_TCRegClassID],
7680    GR64_NOSP_and_GR64_TCSubClassMask,
7681    SuperRegIdxSeqs + 1,
7682    LaneBitmask(0x000000000000000F),
7683    0,
7684    false,
7685    0x00, /* TSFlags */
7686    true, /* HasDisjunctSubRegs */
7687    false, /* CoveredBySubRegs */
7688    GR64_NOSP_and_GR64_TCSuperclasses,
7689    nullptr
7690  };
7691
7692  extern const TargetRegisterClass GR64_TCW64_with_sub_8bitRegClass = {
7693    &X86MCRegisterClasses[GR64_TCW64_with_sub_8bitRegClassID],
7694    GR64_TCW64_with_sub_8bitSubClassMask,
7695    SuperRegIdxSeqs + 1,
7696    LaneBitmask(0x000000000000000F),
7697    0,
7698    false,
7699    0x00, /* TSFlags */
7700    true, /* HasDisjunctSubRegs */
7701    false, /* CoveredBySubRegs */
7702    GR64_TCW64_with_sub_8bitSuperclasses,
7703    nullptr
7704  };
7705
7706  extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass = {
7707    &X86MCRegisterClasses[GR64_TC_and_GR64_TCW64RegClassID],
7708    GR64_TC_and_GR64_TCW64SubClassMask,
7709    SuperRegIdxSeqs + 1,
7710    LaneBitmask(0x000000000000000F),
7711    0,
7712    false,
7713    0x00, /* TSFlags */
7714    true, /* HasDisjunctSubRegs */
7715    false, /* CoveredBySubRegs */
7716    GR64_TC_and_GR64_TCW64Superclasses,
7717    nullptr
7718  };
7719
7720  extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass = {
7721    &X86MCRegisterClasses[GR64_with_sub_16bit_in_GR16_NOREXRegClassID],
7722    GR64_with_sub_16bit_in_GR16_NOREXSubClassMask,
7723    SuperRegIdxSeqs + 1,
7724    LaneBitmask(0x000000000000000F),
7725    0,
7726    false,
7727    0x00, /* TSFlags */
7728    true, /* HasDisjunctSubRegs */
7729    false, /* CoveredBySubRegs */
7730    GR64_with_sub_16bit_in_GR16_NOREXSuperclasses,
7731    nullptr
7732  };
7733
7734  extern const TargetRegisterClass VK64RegClass = {
7735    &X86MCRegisterClasses[VK64RegClassID],
7736    VK64SubClassMask,
7737    SuperRegIdxSeqs + 9,
7738    LaneBitmask(0x0000000000000001),
7739    0,
7740    false,
7741    0x00, /* TSFlags */
7742    false, /* HasDisjunctSubRegs */
7743    false, /* CoveredBySubRegs */
7744    VK64Superclasses,
7745    nullptr
7746  };
7747
7748  extern const TargetRegisterClass VR64RegClass = {
7749    &X86MCRegisterClasses[VR64RegClassID],
7750    VR64SubClassMask,
7751    SuperRegIdxSeqs + 1,
7752    LaneBitmask(0x0000000000000001),
7753    0,
7754    false,
7755    0x00, /* TSFlags */
7756    false, /* HasDisjunctSubRegs */
7757    false, /* CoveredBySubRegs */
7758    NullRegClasses,
7759    nullptr
7760  };
7761
7762  extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCRegClass = {
7763    &X86MCRegisterClasses[GR64PLTSafe_and_GR64_TCRegClassID],
7764    GR64PLTSafe_and_GR64_TCSubClassMask,
7765    SuperRegIdxSeqs + 1,
7766    LaneBitmask(0x000000000000000F),
7767    0,
7768    false,
7769    0x00, /* TSFlags */
7770    true, /* HasDisjunctSubRegs */
7771    false, /* CoveredBySubRegs */
7772    GR64PLTSafe_and_GR64_TCSuperclasses,
7773    nullptr
7774  };
7775
7776  extern const TargetRegisterClass GR64_NOREX_NOSPRegClass = {
7777    &X86MCRegisterClasses[GR64_NOREX_NOSPRegClassID],
7778    GR64_NOREX_NOSPSubClassMask,
7779    SuperRegIdxSeqs + 1,
7780    LaneBitmask(0x000000000000000F),
7781    0,
7782    false,
7783    0x00, /* TSFlags */
7784    true, /* HasDisjunctSubRegs */
7785    false, /* CoveredBySubRegs */
7786    GR64_NOREX_NOSPSuperclasses,
7787    nullptr
7788  };
7789
7790  extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass = {
7791    &X86MCRegisterClasses[GR64_NOREX_and_GR64_TCRegClassID],
7792    GR64_NOREX_and_GR64_TCSubClassMask,
7793    SuperRegIdxSeqs + 1,
7794    LaneBitmask(0x000000000000000F),
7795    0,
7796    false,
7797    0x00, /* TSFlags */
7798    true, /* HasDisjunctSubRegs */
7799    false, /* CoveredBySubRegs */
7800    GR64_NOREX_and_GR64_TCSuperclasses,
7801    nullptr
7802  };
7803
7804  extern const TargetRegisterClass GR64_NOSP_and_GR64_TCW64RegClass = {
7805    &X86MCRegisterClasses[GR64_NOSP_and_GR64_TCW64RegClassID],
7806    GR64_NOSP_and_GR64_TCW64SubClassMask,
7807    SuperRegIdxSeqs + 1,
7808    LaneBitmask(0x000000000000000F),
7809    0,
7810    false,
7811    0x00, /* TSFlags */
7812    true, /* HasDisjunctSubRegs */
7813    false, /* CoveredBySubRegs */
7814    GR64_NOSP_and_GR64_TCW64Superclasses,
7815    nullptr
7816  };
7817
7818  extern const TargetRegisterClass GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass = {
7819    &X86MCRegisterClasses[GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID],
7820    GR64_TCW64_and_GR64_TC_with_sub_8bitSubClassMask,
7821    SuperRegIdxSeqs + 1,
7822    LaneBitmask(0x000000000000000F),
7823    0,
7824    false,
7825    0x00, /* TSFlags */
7826    true, /* HasDisjunctSubRegs */
7827    false, /* CoveredBySubRegs */
7828    GR64_TCW64_and_GR64_TC_with_sub_8bitSuperclasses,
7829    nullptr
7830  };
7831
7832  extern const TargetRegisterClass VK64WMRegClass = {
7833    &X86MCRegisterClasses[VK64WMRegClassID],
7834    VK64WMSubClassMask,
7835    SuperRegIdxSeqs + 9,
7836    LaneBitmask(0x0000000000000001),
7837    0,
7838    false,
7839    0x00, /* TSFlags */
7840    false, /* HasDisjunctSubRegs */
7841    false, /* CoveredBySubRegs */
7842    VK64WMSuperclasses,
7843    nullptr
7844  };
7845
7846  extern const TargetRegisterClass GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass = {
7847    &X86MCRegisterClasses[GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID],
7848    GR64_TC_and_GR64_NOSP_and_GR64_TCW64SubClassMask,
7849    SuperRegIdxSeqs + 1,
7850    LaneBitmask(0x000000000000000F),
7851    0,
7852    false,
7853    0x00, /* TSFlags */
7854    true, /* HasDisjunctSubRegs */
7855    false, /* CoveredBySubRegs */
7856    GR64_TC_and_GR64_NOSP_and_GR64_TCW64Superclasses,
7857    nullptr
7858  };
7859
7860  extern const TargetRegisterClass GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass = {
7861    &X86MCRegisterClasses[GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID],
7862    GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSubClassMask,
7863    SuperRegIdxSeqs + 1,
7864    LaneBitmask(0x000000000000000F),
7865    0,
7866    false,
7867    0x00, /* TSFlags */
7868    true, /* HasDisjunctSubRegs */
7869    false, /* CoveredBySubRegs */
7870    GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSuperclasses,
7871    nullptr
7872  };
7873
7874  extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCW64RegClass = {
7875    &X86MCRegisterClasses[GR64PLTSafe_and_GR64_TCW64RegClassID],
7876    GR64PLTSafe_and_GR64_TCW64SubClassMask,
7877    SuperRegIdxSeqs + 1,
7878    LaneBitmask(0x000000000000000F),
7879    0,
7880    false,
7881    0x00, /* TSFlags */
7882    true, /* HasDisjunctSubRegs */
7883    false, /* CoveredBySubRegs */
7884    GR64PLTSafe_and_GR64_TCW64Superclasses,
7885    nullptr
7886  };
7887
7888  extern const TargetRegisterClass GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass = {
7889    &X86MCRegisterClasses[GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID],
7890    GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSubClassMask,
7891    SuperRegIdxSeqs + 1,
7892    LaneBitmask(0x000000000000000F),
7893    0,
7894    false,
7895    0x00, /* TSFlags */
7896    true, /* HasDisjunctSubRegs */
7897    false, /* CoveredBySubRegs */
7898    GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSuperclasses,
7899    nullptr
7900  };
7901
7902  extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass = {
7903    &X86MCRegisterClasses[GR64_NOREX_and_GR64_TCW64RegClassID],
7904    GR64_NOREX_and_GR64_TCW64SubClassMask,
7905    SuperRegIdxSeqs + 1,
7906    LaneBitmask(0x000000000000000F),
7907    0,
7908    false,
7909    0x00, /* TSFlags */
7910    true, /* HasDisjunctSubRegs */
7911    false, /* CoveredBySubRegs */
7912    GR64_NOREX_and_GR64_TCW64Superclasses,
7913    nullptr
7914  };
7915
7916  extern const TargetRegisterClass GR64_ABCDRegClass = {
7917    &X86MCRegisterClasses[GR64_ABCDRegClassID],
7918    GR64_ABCDSubClassMask,
7919    SuperRegIdxSeqs + 1,
7920    LaneBitmask(0x000000000000000F),
7921    0,
7922    false,
7923    0x00, /* TSFlags */
7924    true, /* HasDisjunctSubRegs */
7925    false, /* CoveredBySubRegs */
7926    GR64_ABCDSuperclasses,
7927    nullptr
7928  };
7929
7930  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass = {
7931    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_TCRegClassID],
7932    GR64_with_sub_32bit_in_GR32_TCSubClassMask,
7933    SuperRegIdxSeqs + 1,
7934    LaneBitmask(0x000000000000000F),
7935    0,
7936    false,
7937    0x00, /* TSFlags */
7938    true, /* HasDisjunctSubRegs */
7939    false, /* CoveredBySubRegs */
7940    GR64_with_sub_32bit_in_GR32_TCSuperclasses,
7941    nullptr
7942  };
7943
7944  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass = {
7945    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID],
7946    GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSubClassMask,
7947    SuperRegIdxSeqs + 1,
7948    LaneBitmask(0x000000000000000F),
7949    0,
7950    false,
7951    0x00, /* TSFlags */
7952    true, /* HasDisjunctSubRegs */
7953    false, /* CoveredBySubRegs */
7954    GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSuperclasses,
7955    nullptr
7956  };
7957
7958  extern const TargetRegisterClass GR64_ADRegClass = {
7959    &X86MCRegisterClasses[GR64_ADRegClassID],
7960    GR64_ADSubClassMask,
7961    SuperRegIdxSeqs + 1,
7962    LaneBitmask(0x000000000000000F),
7963    0,
7964    false,
7965    0x00, /* TSFlags */
7966    true, /* HasDisjunctSubRegs */
7967    false, /* CoveredBySubRegs */
7968    GR64_ADSuperclasses,
7969    nullptr
7970  };
7971
7972  extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass = {
7973    &X86MCRegisterClasses[GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID],
7974    GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask,
7975    SuperRegIdxSeqs + 1,
7976    LaneBitmask(0x000000000000000F),
7977    0,
7978    false,
7979    0x00, /* TSFlags */
7980    true, /* HasDisjunctSubRegs */
7981    false, /* CoveredBySubRegs */
7982    GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses,
7983    nullptr
7984  };
7985
7986  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSPRegClass = {
7987    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSPRegClassID],
7988    GR64_with_sub_32bit_in_GR32_BPSPSubClassMask,
7989    SuperRegIdxSeqs + 1,
7990    LaneBitmask(0x000000000000000F),
7991    0,
7992    false,
7993    0x00, /* TSFlags */
7994    true, /* HasDisjunctSubRegs */
7995    false, /* CoveredBySubRegs */
7996    GR64_with_sub_32bit_in_GR32_BPSPSuperclasses,
7997    nullptr
7998  };
7999
8000  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSIRegClass = {
8001    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BSIRegClassID],
8002    GR64_with_sub_32bit_in_GR32_BSISubClassMask,
8003    SuperRegIdxSeqs + 1,
8004    LaneBitmask(0x000000000000000F),
8005    0,
8006    false,
8007    0x00, /* TSFlags */
8008    true, /* HasDisjunctSubRegs */
8009    false, /* CoveredBySubRegs */
8010    GR64_with_sub_32bit_in_GR32_BSISuperclasses,
8011    nullptr
8012  };
8013
8014  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CBRegClass = {
8015    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_CBRegClassID],
8016    GR64_with_sub_32bit_in_GR32_CBSubClassMask,
8017    SuperRegIdxSeqs + 1,
8018    LaneBitmask(0x000000000000000F),
8019    0,
8020    false,
8021    0x00, /* TSFlags */
8022    true, /* HasDisjunctSubRegs */
8023    false, /* CoveredBySubRegs */
8024    GR64_with_sub_32bit_in_GR32_CBSuperclasses,
8025    nullptr
8026  };
8027
8028  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DCRegClass = {
8029    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DCRegClassID],
8030    GR64_with_sub_32bit_in_GR32_DCSubClassMask,
8031    SuperRegIdxSeqs + 1,
8032    LaneBitmask(0x000000000000000F),
8033    0,
8034    false,
8035    0x00, /* TSFlags */
8036    true, /* HasDisjunctSubRegs */
8037    false, /* CoveredBySubRegs */
8038    GR64_with_sub_32bit_in_GR32_DCSuperclasses,
8039    nullptr
8040  };
8041
8042  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBPRegClass = {
8043    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DIBPRegClassID],
8044    GR64_with_sub_32bit_in_GR32_DIBPSubClassMask,
8045    SuperRegIdxSeqs + 1,
8046    LaneBitmask(0x000000000000000F),
8047    0,
8048    false,
8049    0x00, /* TSFlags */
8050    true, /* HasDisjunctSubRegs */
8051    false, /* CoveredBySubRegs */
8052    GR64_with_sub_32bit_in_GR32_DIBPSuperclasses,
8053    nullptr
8054  };
8055
8056  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_SIDIRegClass = {
8057    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_SIDIRegClassID],
8058    GR64_with_sub_32bit_in_GR32_SIDISubClassMask,
8059    SuperRegIdxSeqs + 1,
8060    LaneBitmask(0x000000000000000F),
8061    0,
8062    false,
8063    0x00, /* TSFlags */
8064    true, /* HasDisjunctSubRegs */
8065    false, /* CoveredBySubRegs */
8066    GR64_with_sub_32bit_in_GR32_SIDISuperclasses,
8067    nullptr
8068  };
8069
8070  extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass = {
8071    &X86MCRegisterClasses[GR64_and_LOW32_ADDR_ACCESSRegClassID],
8072    GR64_and_LOW32_ADDR_ACCESSSubClassMask,
8073    SuperRegIdxSeqs + 1,
8074    LaneBitmask(0x000000000000000F),
8075    0,
8076    false,
8077    0x00, /* TSFlags */
8078    true, /* HasDisjunctSubRegs */
8079    false, /* CoveredBySubRegs */
8080    GR64_and_LOW32_ADDR_ACCESSSuperclasses,
8081    nullptr
8082  };
8083
8084  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass = {
8085    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID],
8086    GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask,
8087    SuperRegIdxSeqs + 1,
8088    LaneBitmask(0x000000000000000F),
8089    0,
8090    false,
8091    0x00, /* TSFlags */
8092    true, /* HasDisjunctSubRegs */
8093    false, /* CoveredBySubRegs */
8094    GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISuperclasses,
8095    nullptr
8096  };
8097
8098  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClass = {
8099    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID],
8100    GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCSubClassMask,
8101    SuperRegIdxSeqs + 1,
8102    LaneBitmask(0x000000000000000F),
8103    0,
8104    false,
8105    0x00, /* TSFlags */
8106    true, /* HasDisjunctSubRegs */
8107    false, /* CoveredBySubRegs */
8108    GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCSuperclasses,
8109    nullptr
8110  };
8111
8112  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass = {
8113    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID],
8114    GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask,
8115    SuperRegIdxSeqs + 1,
8116    LaneBitmask(0x000000000000000F),
8117    0,
8118    false,
8119    0x00, /* TSFlags */
8120    true, /* HasDisjunctSubRegs */
8121    false, /* CoveredBySubRegs */
8122    GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSuperclasses,
8123    nullptr
8124  };
8125
8126  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass = {
8127    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID],
8128    GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSubClassMask,
8129    SuperRegIdxSeqs + 1,
8130    LaneBitmask(0x000000000000000F),
8131    0,
8132    false,
8133    0x00, /* TSFlags */
8134    true, /* HasDisjunctSubRegs */
8135    false, /* CoveredBySubRegs */
8136    GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSuperclasses,
8137    nullptr
8138  };
8139
8140  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass = {
8141    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID],
8142    GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask,
8143    SuperRegIdxSeqs + 1,
8144    LaneBitmask(0x000000000000000F),
8145    0,
8146    false,
8147    0x00, /* TSFlags */
8148    true, /* HasDisjunctSubRegs */
8149    false, /* CoveredBySubRegs */
8150    GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISuperclasses,
8151    nullptr
8152  };
8153
8154  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClass = {
8155    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID],
8156    GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCSubClassMask,
8157    SuperRegIdxSeqs + 1,
8158    LaneBitmask(0x000000000000000F),
8159    0,
8160    false,
8161    0x00, /* TSFlags */
8162    true, /* HasDisjunctSubRegs */
8163    false, /* CoveredBySubRegs */
8164    GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCSuperclasses,
8165    nullptr
8166  };
8167
8168  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass = {
8169    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID],
8170    GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask,
8171    SuperRegIdxSeqs + 1,
8172    LaneBitmask(0x000000000000000F),
8173    0,
8174    false,
8175    0x00, /* TSFlags */
8176    true, /* HasDisjunctSubRegs */
8177    false, /* CoveredBySubRegs */
8178    GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISuperclasses,
8179    nullptr
8180  };
8181
8182  extern const TargetRegisterClass RSTRegClass = {
8183    &X86MCRegisterClasses[RSTRegClassID],
8184    RSTSubClassMask,
8185    SuperRegIdxSeqs + 1,
8186    LaneBitmask(0x0000000000000001),
8187    0,
8188    false,
8189    0x00, /* TSFlags */
8190    false, /* HasDisjunctSubRegs */
8191    false, /* CoveredBySubRegs */
8192    NullRegClasses,
8193    nullptr
8194  };
8195
8196  extern const TargetRegisterClass RFP80RegClass = {
8197    &X86MCRegisterClasses[RFP80RegClassID],
8198    RFP80SubClassMask,
8199    SuperRegIdxSeqs + 1,
8200    LaneBitmask(0x0000000000000001),
8201    0,
8202    false,
8203    0x00, /* TSFlags */
8204    false, /* HasDisjunctSubRegs */
8205    false, /* CoveredBySubRegs */
8206    RFP80Superclasses,
8207    nullptr
8208  };
8209
8210  extern const TargetRegisterClass RFP80_7RegClass = {
8211    &X86MCRegisterClasses[RFP80_7RegClassID],
8212    RFP80_7SubClassMask,
8213    SuperRegIdxSeqs + 1,
8214    LaneBitmask(0x0000000000000001),
8215    0,
8216    false,
8217    0x00, /* TSFlags */
8218    false, /* HasDisjunctSubRegs */
8219    false, /* CoveredBySubRegs */
8220    NullRegClasses,
8221    nullptr
8222  };
8223
8224  extern const TargetRegisterClass VR128XRegClass = {
8225    &X86MCRegisterClasses[VR128XRegClassID],
8226    VR128XSubClassMask,
8227    SuperRegIdxSeqs + 12,
8228    LaneBitmask(0x0000000000000001),
8229    0,
8230    false,
8231    0x00, /* TSFlags */
8232    false, /* HasDisjunctSubRegs */
8233    false, /* CoveredBySubRegs */
8234    VR128XSuperclasses,
8235    nullptr
8236  };
8237
8238  extern const TargetRegisterClass VR128RegClass = {
8239    &X86MCRegisterClasses[VR128RegClassID],
8240    VR128SubClassMask,
8241    SuperRegIdxSeqs + 12,
8242    LaneBitmask(0x0000000000000001),
8243    0,
8244    false,
8245    0x00, /* TSFlags */
8246    false, /* HasDisjunctSubRegs */
8247    false, /* CoveredBySubRegs */
8248    VR128Superclasses,
8249    nullptr
8250  };
8251
8252  extern const TargetRegisterClass VR256XRegClass = {
8253    &X86MCRegisterClasses[VR256XRegClassID],
8254    VR256XSubClassMask,
8255    SuperRegIdxSeqs + 14,
8256    LaneBitmask(0x0000000000000040),
8257    0,
8258    false,
8259    0x00, /* TSFlags */
8260    false, /* HasDisjunctSubRegs */
8261    false, /* CoveredBySubRegs */
8262    NullRegClasses,
8263    nullptr
8264  };
8265
8266  extern const TargetRegisterClass VR256RegClass = {
8267    &X86MCRegisterClasses[VR256RegClassID],
8268    VR256SubClassMask,
8269    SuperRegIdxSeqs + 14,
8270    LaneBitmask(0x0000000000000040),
8271    0,
8272    false,
8273    0x00, /* TSFlags */
8274    false, /* HasDisjunctSubRegs */
8275    false, /* CoveredBySubRegs */
8276    VR256Superclasses,
8277    nullptr
8278  };
8279
8280  extern const TargetRegisterClass VR512RegClass = {
8281    &X86MCRegisterClasses[VR512RegClassID],
8282    VR512SubClassMask,
8283    SuperRegIdxSeqs + 1,
8284    LaneBitmask(0x0000000000000040),
8285    0,
8286    false,
8287    0x00, /* TSFlags */
8288    false, /* HasDisjunctSubRegs */
8289    false, /* CoveredBySubRegs */
8290    NullRegClasses,
8291    nullptr
8292  };
8293
8294  extern const TargetRegisterClass VR512_0_15RegClass = {
8295    &X86MCRegisterClasses[VR512_0_15RegClassID],
8296    VR512_0_15SubClassMask,
8297    SuperRegIdxSeqs + 1,
8298    LaneBitmask(0x0000000000000040),
8299    0,
8300    false,
8301    0x00, /* TSFlags */
8302    false, /* HasDisjunctSubRegs */
8303    false, /* CoveredBySubRegs */
8304    VR512_0_15Superclasses,
8305    nullptr
8306  };
8307
8308  extern const TargetRegisterClass TILERegClass = {
8309    &X86MCRegisterClasses[TILERegClassID],
8310    TILESubClassMask,
8311    SuperRegIdxSeqs + 1,
8312    LaneBitmask(0x0000000000000001),
8313    0,
8314    false,
8315    0x00, /* TSFlags */
8316    false, /* HasDisjunctSubRegs */
8317    false, /* CoveredBySubRegs */
8318    NullRegClasses,
8319    nullptr
8320  };
8321
8322} // end namespace X86
8323
8324namespace {
8325  const TargetRegisterClass *const RegisterClasses[] = {
8326    &X86::GR8RegClass,
8327    &X86::GRH8RegClass,
8328    &X86::GR8_NOREXRegClass,
8329    &X86::GR8_ABCD_HRegClass,
8330    &X86::GR8_ABCD_LRegClass,
8331    &X86::GRH16RegClass,
8332    &X86::GR16RegClass,
8333    &X86::GR16_NOREXRegClass,
8334    &X86::VK1RegClass,
8335    &X86::VK16RegClass,
8336    &X86::VK2RegClass,
8337    &X86::VK4RegClass,
8338    &X86::VK8RegClass,
8339    &X86::VK16WMRegClass,
8340    &X86::VK1WMRegClass,
8341    &X86::VK2WMRegClass,
8342    &X86::VK4WMRegClass,
8343    &X86::VK8WMRegClass,
8344    &X86::SEGMENT_REGRegClass,
8345    &X86::GR16_ABCDRegClass,
8346    &X86::FPCCRRegClass,
8347    &X86::FR16XRegClass,
8348    &X86::FR16RegClass,
8349    &X86::VK16PAIRRegClass,
8350    &X86::VK1PAIRRegClass,
8351    &X86::VK2PAIRRegClass,
8352    &X86::VK4PAIRRegClass,
8353    &X86::VK8PAIRRegClass,
8354    &X86::VK16PAIR_with_sub_mask_0_in_VK16WMRegClass,
8355    &X86::FR32XRegClass,
8356    &X86::LOW32_ADDR_ACCESS_RBPRegClass,
8357    &X86::LOW32_ADDR_ACCESSRegClass,
8358    &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
8359    &X86::DEBUG_REGRegClass,
8360    &X86::FR32RegClass,
8361    &X86::GR32RegClass,
8362    &X86::GR32_NOSPRegClass,
8363    &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
8364    &X86::GR32_NOREXRegClass,
8365    &X86::VK32RegClass,
8366    &X86::GR32_NOREX_NOSPRegClass,
8367    &X86::RFP32RegClass,
8368    &X86::VK32WMRegClass,
8369    &X86::GR32_ABCDRegClass,
8370    &X86::GR32_TCRegClass,
8371    &X86::GR32_ABCD_and_GR32_TCRegClass,
8372    &X86::GR32_ADRegClass,
8373    &X86::GR32_BPSPRegClass,
8374    &X86::GR32_BSIRegClass,
8375    &X86::GR32_CBRegClass,
8376    &X86::GR32_DCRegClass,
8377    &X86::GR32_DIBPRegClass,
8378    &X86::GR32_SIDIRegClass,
8379    &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
8380    &X86::CCRRegClass,
8381    &X86::DFCCRRegClass,
8382    &X86::GR32_ABCD_and_GR32_BSIRegClass,
8383    &X86::GR32_AD_and_GR32_DCRegClass,
8384    &X86::GR32_BPSP_and_GR32_DIBPRegClass,
8385    &X86::GR32_BPSP_and_GR32_TCRegClass,
8386    &X86::GR32_BSI_and_GR32_SIDIRegClass,
8387    &X86::GR32_CB_and_GR32_DCRegClass,
8388    &X86::GR32_DIBP_and_GR32_SIDIRegClass,
8389    &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass,
8390    &X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClass,
8391    &X86::RFP64RegClass,
8392    &X86::FR64XRegClass,
8393    &X86::GR64RegClass,
8394    &X86::CONTROL_REGRegClass,
8395    &X86::FR64RegClass,
8396    &X86::GR64_with_sub_8bitRegClass,
8397    &X86::GR64_NOSPRegClass,
8398    &X86::GR64PLTSafeRegClass,
8399    &X86::GR64_TCRegClass,
8400    &X86::GR64_NOREXRegClass,
8401    &X86::GR64_TCW64RegClass,
8402    &X86::GR64_TC_with_sub_8bitRegClass,
8403    &X86::GR64_NOSP_and_GR64_TCRegClass,
8404    &X86::GR64_TCW64_with_sub_8bitRegClass,
8405    &X86::GR64_TC_and_GR64_TCW64RegClass,
8406    &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
8407    &X86::VK64RegClass,
8408    &X86::VR64RegClass,
8409    &X86::GR64PLTSafe_and_GR64_TCRegClass,
8410    &X86::GR64_NOREX_NOSPRegClass,
8411    &X86::GR64_NOREX_and_GR64_TCRegClass,
8412    &X86::GR64_NOSP_and_GR64_TCW64RegClass,
8413    &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
8414    &X86::VK64WMRegClass,
8415    &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
8416    &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
8417    &X86::GR64PLTSafe_and_GR64_TCW64RegClass,
8418    &X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
8419    &X86::GR64_NOREX_and_GR64_TCW64RegClass,
8420    &X86::GR64_ABCDRegClass,
8421    &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
8422    &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
8423    &X86::GR64_ADRegClass,
8424    &X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClass,
8425    &X86::GR64_with_sub_32bit_in_GR32_BPSPRegClass,
8426    &X86::GR64_with_sub_32bit_in_GR32_BSIRegClass,
8427    &X86::GR64_with_sub_32bit_in_GR32_CBRegClass,
8428    &X86::GR64_with_sub_32bit_in_GR32_DCRegClass,
8429    &X86::GR64_with_sub_32bit_in_GR32_DIBPRegClass,
8430    &X86::GR64_with_sub_32bit_in_GR32_SIDIRegClass,
8431    &X86::GR64_and_LOW32_ADDR_ACCESSRegClass,
8432    &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass,
8433    &X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClass,
8434    &X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass,
8435    &X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass,
8436    &X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass,
8437    &X86::GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClass,
8438    &X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass,
8439    &X86::RSTRegClass,
8440    &X86::RFP80RegClass,
8441    &X86::RFP80_7RegClass,
8442    &X86::VR128XRegClass,
8443    &X86::VR128RegClass,
8444    &X86::VR256XRegClass,
8445    &X86::VR256RegClass,
8446    &X86::VR512RegClass,
8447    &X86::VR512_0_15RegClass,
8448    &X86::TILERegClass,
8449  };
8450} // end anonymous namespace
8451
8452static const uint8_t CostPerUseTable[] = {
84530, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
8454
8455
8456static const bool InAllocatableClassTable[] = {
8457false, true, true, true, true, true, true, false, true, true, true, true, true, true, false, true, true, false, true, true, true, true, true, true, true, true, true, true, false, false, false, true, true, true, false, false, true, false, true, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, true, false, true, true, true, false, true, true, false, true, true, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, };
8458
8459
8460static const TargetRegisterInfoDesc X86RegInfoDesc = { // Extra Descriptors
8461CostPerUseTable, 1, InAllocatableClassTable};
8462
8463unsigned X86GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
8464  static const uint8_t Rows[1][10] = {
8465    { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
8466  };
8467
8468  --IdxA; assert(IdxA < 10); (void) IdxA;
8469  --IdxB; assert(IdxB < 10);
8470  return Rows[0][IdxB];
8471}
8472
8473  struct MaskRolOp {
8474    LaneBitmask Mask;
8475    uint8_t  RotateLeft;
8476  };
8477  static const MaskRolOp LaneMaskComposeSequences[] = {
8478    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
8479    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
8480    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
8481    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 6
8482    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 8
8483    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 10
8484    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  6 }, { LaneBitmask::getNone(), 0 }  // Sequence 12
8485  };
8486  static const uint8_t CompositeSequences[] = {
8487    0, // to sub_8bit
8488    2, // to sub_8bit_hi
8489    4, // to sub_8bit_hi_phony
8490    0, // to sub_16bit
8491    6, // to sub_16bit_hi
8492    0, // to sub_32bit
8493    8, // to sub_mask_0
8494    10, // to sub_mask_1
8495    12, // to sub_xmm
8496    0 // to sub_ymm
8497  };
8498
8499LaneBitmask X86GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
8500  --IdxA; assert(IdxA < 10 && "Subregister index out of bounds");
8501  LaneBitmask Result;
8502  for (const MaskRolOp *Ops =
8503       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
8504       Ops->Mask.any(); ++Ops) {
8505    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
8506    if (unsigned S = Ops->RotateLeft)
8507      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
8508    else
8509      Result |= LaneBitmask(M);
8510  }
8511  return Result;
8512}
8513
8514LaneBitmask X86GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
8515  LaneMask &= getSubRegIndexLaneMask(IdxA);
8516  --IdxA; assert(IdxA < 10 && "Subregister index out of bounds");
8517  LaneBitmask Result;
8518  for (const MaskRolOp *Ops =
8519       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
8520       Ops->Mask.any(); ++Ops) {
8521    LaneBitmask::Type M = LaneMask.getAsInteger();
8522    if (unsigned S = Ops->RotateLeft)
8523      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
8524    else
8525      Result |= LaneBitmask(M);
8526  }
8527  return Result;
8528}
8529
8530const TargetRegisterClass *X86GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
8531  static const uint8_t Table[123][10] = {
8532    {	// GR8
8533      0,	// sub_8bit
8534      0,	// sub_8bit_hi
8535      0,	// sub_8bit_hi_phony
8536      0,	// sub_16bit
8537      0,	// sub_16bit_hi
8538      0,	// sub_32bit
8539      0,	// sub_mask_0
8540      0,	// sub_mask_1
8541      0,	// sub_xmm
8542      0,	// sub_ymm
8543    },
8544    {	// GRH8
8545      0,	// sub_8bit
8546      0,	// sub_8bit_hi
8547      0,	// sub_8bit_hi_phony
8548      0,	// sub_16bit
8549      0,	// sub_16bit_hi
8550      0,	// sub_32bit
8551      0,	// sub_mask_0
8552      0,	// sub_mask_1
8553      0,	// sub_xmm
8554      0,	// sub_ymm
8555    },
8556    {	// GR8_NOREX
8557      0,	// sub_8bit
8558      0,	// sub_8bit_hi
8559      0,	// sub_8bit_hi_phony
8560      0,	// sub_16bit
8561      0,	// sub_16bit_hi
8562      0,	// sub_32bit
8563      0,	// sub_mask_0
8564      0,	// sub_mask_1
8565      0,	// sub_xmm
8566      0,	// sub_ymm
8567    },
8568    {	// GR8_ABCD_H
8569      0,	// sub_8bit
8570      0,	// sub_8bit_hi
8571      0,	// sub_8bit_hi_phony
8572      0,	// sub_16bit
8573      0,	// sub_16bit_hi
8574      0,	// sub_32bit
8575      0,	// sub_mask_0
8576      0,	// sub_mask_1
8577      0,	// sub_xmm
8578      0,	// sub_ymm
8579    },
8580    {	// GR8_ABCD_L
8581      0,	// sub_8bit
8582      0,	// sub_8bit_hi
8583      0,	// sub_8bit_hi_phony
8584      0,	// sub_16bit
8585      0,	// sub_16bit_hi
8586      0,	// sub_32bit
8587      0,	// sub_mask_0
8588      0,	// sub_mask_1
8589      0,	// sub_xmm
8590      0,	// sub_ymm
8591    },
8592    {	// GRH16
8593      0,	// sub_8bit
8594      0,	// sub_8bit_hi
8595      0,	// sub_8bit_hi_phony
8596      0,	// sub_16bit
8597      0,	// sub_16bit_hi
8598      0,	// sub_32bit
8599      0,	// sub_mask_0
8600      0,	// sub_mask_1
8601      0,	// sub_xmm
8602      0,	// sub_ymm
8603    },
8604    {	// GR16
8605      7,	// sub_8bit -> GR16
8606      20,	// sub_8bit_hi -> GR16_ABCD
8607      0,	// sub_8bit_hi_phony
8608      0,	// sub_16bit
8609      0,	// sub_16bit_hi
8610      0,	// sub_32bit
8611      0,	// sub_mask_0
8612      0,	// sub_mask_1
8613      0,	// sub_xmm
8614      0,	// sub_ymm
8615    },
8616    {	// GR16_NOREX
8617      8,	// sub_8bit -> GR16_NOREX
8618      20,	// sub_8bit_hi -> GR16_ABCD
8619      0,	// sub_8bit_hi_phony
8620      0,	// sub_16bit
8621      0,	// sub_16bit_hi
8622      0,	// sub_32bit
8623      0,	// sub_mask_0
8624      0,	// sub_mask_1
8625      0,	// sub_xmm
8626      0,	// sub_ymm
8627    },
8628    {	// VK1
8629      0,	// sub_8bit
8630      0,	// sub_8bit_hi
8631      0,	// sub_8bit_hi_phony
8632      0,	// sub_16bit
8633      0,	// sub_16bit_hi
8634      0,	// sub_32bit
8635      0,	// sub_mask_0
8636      0,	// sub_mask_1
8637      0,	// sub_xmm
8638      0,	// sub_ymm
8639    },
8640    {	// VK16
8641      0,	// sub_8bit
8642      0,	// sub_8bit_hi
8643      0,	// sub_8bit_hi_phony
8644      0,	// sub_16bit
8645      0,	// sub_16bit_hi
8646      0,	// sub_32bit
8647      0,	// sub_mask_0
8648      0,	// sub_mask_1
8649      0,	// sub_xmm
8650      0,	// sub_ymm
8651    },
8652    {	// VK2
8653      0,	// sub_8bit
8654      0,	// sub_8bit_hi
8655      0,	// sub_8bit_hi_phony
8656      0,	// sub_16bit
8657      0,	// sub_16bit_hi
8658      0,	// sub_32bit
8659      0,	// sub_mask_0
8660      0,	// sub_mask_1
8661      0,	// sub_xmm
8662      0,	// sub_ymm
8663    },
8664    {	// VK4
8665      0,	// sub_8bit
8666      0,	// sub_8bit_hi
8667      0,	// sub_8bit_hi_phony
8668      0,	// sub_16bit
8669      0,	// sub_16bit_hi
8670      0,	// sub_32bit
8671      0,	// sub_mask_0
8672      0,	// sub_mask_1
8673      0,	// sub_xmm
8674      0,	// sub_ymm
8675    },
8676    {	// VK8
8677      0,	// sub_8bit
8678      0,	// sub_8bit_hi
8679      0,	// sub_8bit_hi_phony
8680      0,	// sub_16bit
8681      0,	// sub_16bit_hi
8682      0,	// sub_32bit
8683      0,	// sub_mask_0
8684      0,	// sub_mask_1
8685      0,	// sub_xmm
8686      0,	// sub_ymm
8687    },
8688    {	// VK16WM
8689      0,	// sub_8bit
8690      0,	// sub_8bit_hi
8691      0,	// sub_8bit_hi_phony
8692      0,	// sub_16bit
8693      0,	// sub_16bit_hi
8694      0,	// sub_32bit
8695      0,	// sub_mask_0
8696      0,	// sub_mask_1
8697      0,	// sub_xmm
8698      0,	// sub_ymm
8699    },
8700    {	// VK1WM
8701      0,	// sub_8bit
8702      0,	// sub_8bit_hi
8703      0,	// sub_8bit_hi_phony
8704      0,	// sub_16bit
8705      0,	// sub_16bit_hi
8706      0,	// sub_32bit
8707      0,	// sub_mask_0
8708      0,	// sub_mask_1
8709      0,	// sub_xmm
8710      0,	// sub_ymm
8711    },
8712    {	// VK2WM
8713      0,	// sub_8bit
8714      0,	// sub_8bit_hi
8715      0,	// sub_8bit_hi_phony
8716      0,	// sub_16bit
8717      0,	// sub_16bit_hi
8718      0,	// sub_32bit
8719      0,	// sub_mask_0
8720      0,	// sub_mask_1
8721      0,	// sub_xmm
8722      0,	// sub_ymm
8723    },
8724    {	// VK4WM
8725      0,	// sub_8bit
8726      0,	// sub_8bit_hi
8727      0,	// sub_8bit_hi_phony
8728      0,	// sub_16bit
8729      0,	// sub_16bit_hi
8730      0,	// sub_32bit
8731      0,	// sub_mask_0
8732      0,	// sub_mask_1
8733      0,	// sub_xmm
8734      0,	// sub_ymm
8735    },
8736    {	// VK8WM
8737      0,	// sub_8bit
8738      0,	// sub_8bit_hi
8739      0,	// sub_8bit_hi_phony
8740      0,	// sub_16bit
8741      0,	// sub_16bit_hi
8742      0,	// sub_32bit
8743      0,	// sub_mask_0
8744      0,	// sub_mask_1
8745      0,	// sub_xmm
8746      0,	// sub_ymm
8747    },
8748    {	// SEGMENT_REG
8749      0,	// sub_8bit
8750      0,	// sub_8bit_hi
8751      0,	// sub_8bit_hi_phony
8752      0,	// sub_16bit
8753      0,	// sub_16bit_hi
8754      0,	// sub_32bit
8755      0,	// sub_mask_0
8756      0,	// sub_mask_1
8757      0,	// sub_xmm
8758      0,	// sub_ymm
8759    },
8760    {	// GR16_ABCD
8761      20,	// sub_8bit -> GR16_ABCD
8762      20,	// sub_8bit_hi -> GR16_ABCD
8763      0,	// sub_8bit_hi_phony
8764      0,	// sub_16bit
8765      0,	// sub_16bit_hi
8766      0,	// sub_32bit
8767      0,	// sub_mask_0
8768      0,	// sub_mask_1
8769      0,	// sub_xmm
8770      0,	// sub_ymm
8771    },
8772    {	// FPCCR
8773      0,	// sub_8bit
8774      0,	// sub_8bit_hi
8775      0,	// sub_8bit_hi_phony
8776      0,	// sub_16bit
8777      0,	// sub_16bit_hi
8778      0,	// sub_32bit
8779      0,	// sub_mask_0
8780      0,	// sub_mask_1
8781      0,	// sub_xmm
8782      0,	// sub_ymm
8783    },
8784    {	// FR16X
8785      0,	// sub_8bit
8786      0,	// sub_8bit_hi
8787      0,	// sub_8bit_hi_phony
8788      0,	// sub_16bit
8789      0,	// sub_16bit_hi
8790      0,	// sub_32bit
8791      0,	// sub_mask_0
8792      0,	// sub_mask_1
8793      0,	// sub_xmm
8794      0,	// sub_ymm
8795    },
8796    {	// FR16
8797      0,	// sub_8bit
8798      0,	// sub_8bit_hi
8799      0,	// sub_8bit_hi_phony
8800      0,	// sub_16bit
8801      0,	// sub_16bit_hi
8802      0,	// sub_32bit
8803      0,	// sub_mask_0
8804      0,	// sub_mask_1
8805      0,	// sub_xmm
8806      0,	// sub_ymm
8807    },
8808    {	// VK16PAIR
8809      0,	// sub_8bit
8810      0,	// sub_8bit_hi
8811      0,	// sub_8bit_hi_phony
8812      0,	// sub_16bit
8813      0,	// sub_16bit_hi
8814      0,	// sub_32bit
8815      24,	// sub_mask_0 -> VK16PAIR
8816      24,	// sub_mask_1 -> VK16PAIR
8817      0,	// sub_xmm
8818      0,	// sub_ymm
8819    },
8820    {	// VK1PAIR
8821      0,	// sub_8bit
8822      0,	// sub_8bit_hi
8823      0,	// sub_8bit_hi_phony
8824      0,	// sub_16bit
8825      0,	// sub_16bit_hi
8826      0,	// sub_32bit
8827      25,	// sub_mask_0 -> VK1PAIR
8828      25,	// sub_mask_1 -> VK1PAIR
8829      0,	// sub_xmm
8830      0,	// sub_ymm
8831    },
8832    {	// VK2PAIR
8833      0,	// sub_8bit
8834      0,	// sub_8bit_hi
8835      0,	// sub_8bit_hi_phony
8836      0,	// sub_16bit
8837      0,	// sub_16bit_hi
8838      0,	// sub_32bit
8839      26,	// sub_mask_0 -> VK2PAIR
8840      26,	// sub_mask_1 -> VK2PAIR
8841      0,	// sub_xmm
8842      0,	// sub_ymm
8843    },
8844    {	// VK4PAIR
8845      0,	// sub_8bit
8846      0,	// sub_8bit_hi
8847      0,	// sub_8bit_hi_phony
8848      0,	// sub_16bit
8849      0,	// sub_16bit_hi
8850      0,	// sub_32bit
8851      27,	// sub_mask_0 -> VK4PAIR
8852      27,	// sub_mask_1 -> VK4PAIR
8853      0,	// sub_xmm
8854      0,	// sub_ymm
8855    },
8856    {	// VK8PAIR
8857      0,	// sub_8bit
8858      0,	// sub_8bit_hi
8859      0,	// sub_8bit_hi_phony
8860      0,	// sub_16bit
8861      0,	// sub_16bit_hi
8862      0,	// sub_32bit
8863      28,	// sub_mask_0 -> VK8PAIR
8864      28,	// sub_mask_1 -> VK8PAIR
8865      0,	// sub_xmm
8866      0,	// sub_ymm
8867    },
8868    {	// VK16PAIR_with_sub_mask_0_in_VK16WM
8869      0,	// sub_8bit
8870      0,	// sub_8bit_hi
8871      0,	// sub_8bit_hi_phony
8872      0,	// sub_16bit
8873      0,	// sub_16bit_hi
8874      0,	// sub_32bit
8875      29,	// sub_mask_0 -> VK16PAIR_with_sub_mask_0_in_VK16WM
8876      29,	// sub_mask_1 -> VK16PAIR_with_sub_mask_0_in_VK16WM
8877      0,	// sub_xmm
8878      0,	// sub_ymm
8879    },
8880    {	// FR32X
8881      0,	// sub_8bit
8882      0,	// sub_8bit_hi
8883      0,	// sub_8bit_hi_phony
8884      0,	// sub_16bit
8885      0,	// sub_16bit_hi
8886      0,	// sub_32bit
8887      0,	// sub_mask_0
8888      0,	// sub_mask_1
8889      0,	// sub_xmm
8890      0,	// sub_ymm
8891    },
8892    {	// LOW32_ADDR_ACCESS_RBP
8893      33,	// sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
8894      44,	// sub_8bit_hi -> GR32_ABCD
8895      0,	// sub_8bit_hi_phony
8896      31,	// sub_16bit -> LOW32_ADDR_ACCESS_RBP
8897      0,	// sub_16bit_hi
8898      54,	// sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
8899      0,	// sub_mask_0
8900      0,	// sub_mask_1
8901      0,	// sub_xmm
8902      0,	// sub_ymm
8903    },
8904    {	// LOW32_ADDR_ACCESS
8905      36,	// sub_8bit -> GR32
8906      44,	// sub_8bit_hi -> GR32_ABCD
8907      0,	// sub_8bit_hi_phony
8908      32,	// sub_16bit -> LOW32_ADDR_ACCESS
8909      0,	// sub_16bit_hi
8910      65,	// sub_32bit -> LOW32_ADDR_ACCESS_with_sub_32bit
8911      0,	// sub_mask_0
8912      0,	// sub_mask_1
8913      0,	// sub_xmm
8914      0,	// sub_ymm
8915    },
8916    {	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit
8917      33,	// sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
8918      44,	// sub_8bit_hi -> GR32_ABCD
8919      0,	// sub_8bit_hi_phony
8920      33,	// sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
8921      0,	// sub_16bit_hi
8922      64,	// sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
8923      0,	// sub_mask_0
8924      0,	// sub_mask_1
8925      0,	// sub_xmm
8926      0,	// sub_ymm
8927    },
8928    {	// DEBUG_REG
8929      0,	// sub_8bit
8930      0,	// sub_8bit_hi
8931      0,	// sub_8bit_hi_phony
8932      0,	// sub_16bit
8933      0,	// sub_16bit_hi
8934      0,	// sub_32bit
8935      0,	// sub_mask_0
8936      0,	// sub_mask_1
8937      0,	// sub_xmm
8938      0,	// sub_ymm
8939    },
8940    {	// FR32
8941      0,	// sub_8bit
8942      0,	// sub_8bit_hi
8943      0,	// sub_8bit_hi_phony
8944      0,	// sub_16bit
8945      0,	// sub_16bit_hi
8946      0,	// sub_32bit
8947      0,	// sub_mask_0
8948      0,	// sub_mask_1
8949      0,	// sub_xmm
8950      0,	// sub_ymm
8951    },
8952    {	// GR32
8953      36,	// sub_8bit -> GR32
8954      44,	// sub_8bit_hi -> GR32_ABCD
8955      0,	// sub_8bit_hi_phony
8956      36,	// sub_16bit -> GR32
8957      0,	// sub_16bit_hi
8958      0,	// sub_32bit
8959      0,	// sub_mask_0
8960      0,	// sub_mask_1
8961      0,	// sub_xmm
8962      0,	// sub_ymm
8963    },
8964    {	// GR32_NOSP
8965      37,	// sub_8bit -> GR32_NOSP
8966      44,	// sub_8bit_hi -> GR32_ABCD
8967      0,	// sub_8bit_hi_phony
8968      37,	// sub_16bit -> GR32_NOSP
8969      0,	// sub_16bit_hi
8970      0,	// sub_32bit
8971      0,	// sub_mask_0
8972      0,	// sub_mask_1
8973      0,	// sub_xmm
8974      0,	// sub_ymm
8975    },
8976    {	// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
8977      38,	// sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
8978      44,	// sub_8bit_hi -> GR32_ABCD
8979      0,	// sub_8bit_hi_phony
8980      38,	// sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
8981      0,	// sub_16bit_hi
8982      64,	// sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
8983      0,	// sub_mask_0
8984      0,	// sub_mask_1
8985      0,	// sub_xmm
8986      0,	// sub_ymm
8987    },
8988    {	// GR32_NOREX
8989      39,	// sub_8bit -> GR32_NOREX
8990      44,	// sub_8bit_hi -> GR32_ABCD
8991      0,	// sub_8bit_hi_phony
8992      39,	// sub_16bit -> GR32_NOREX
8993      0,	// sub_16bit_hi
8994      0,	// sub_32bit
8995      0,	// sub_mask_0
8996      0,	// sub_mask_1
8997      0,	// sub_xmm
8998      0,	// sub_ymm
8999    },
9000    {	// VK32
9001      0,	// sub_8bit
9002      0,	// sub_8bit_hi
9003      0,	// sub_8bit_hi_phony
9004      0,	// sub_16bit
9005      0,	// sub_16bit_hi
9006      0,	// sub_32bit
9007      0,	// sub_mask_0
9008      0,	// sub_mask_1
9009      0,	// sub_xmm
9010      0,	// sub_ymm
9011    },
9012    {	// GR32_NOREX_NOSP
9013      41,	// sub_8bit -> GR32_NOREX_NOSP
9014      44,	// sub_8bit_hi -> GR32_ABCD
9015      0,	// sub_8bit_hi_phony
9016      41,	// sub_16bit -> GR32_NOREX_NOSP
9017      0,	// sub_16bit_hi
9018      0,	// sub_32bit
9019      0,	// sub_mask_0
9020      0,	// sub_mask_1
9021      0,	// sub_xmm
9022      0,	// sub_ymm
9023    },
9024    {	// RFP32
9025      0,	// sub_8bit
9026      0,	// sub_8bit_hi
9027      0,	// sub_8bit_hi_phony
9028      0,	// sub_16bit
9029      0,	// sub_16bit_hi
9030      0,	// sub_32bit
9031      0,	// sub_mask_0
9032      0,	// sub_mask_1
9033      0,	// sub_xmm
9034      0,	// sub_ymm
9035    },
9036    {	// VK32WM
9037      0,	// sub_8bit
9038      0,	// sub_8bit_hi
9039      0,	// sub_8bit_hi_phony
9040      0,	// sub_16bit
9041      0,	// sub_16bit_hi
9042      0,	// sub_32bit
9043      0,	// sub_mask_0
9044      0,	// sub_mask_1
9045      0,	// sub_xmm
9046      0,	// sub_ymm
9047    },
9048    {	// GR32_ABCD
9049      44,	// sub_8bit -> GR32_ABCD
9050      44,	// sub_8bit_hi -> GR32_ABCD
9051      0,	// sub_8bit_hi_phony
9052      44,	// sub_16bit -> GR32_ABCD
9053      0,	// sub_16bit_hi
9054      0,	// sub_32bit
9055      0,	// sub_mask_0
9056      0,	// sub_mask_1
9057      0,	// sub_xmm
9058      0,	// sub_ymm
9059    },
9060    {	// GR32_TC
9061      45,	// sub_8bit -> GR32_TC
9062      46,	// sub_8bit_hi -> GR32_ABCD_and_GR32_TC
9063      0,	// sub_8bit_hi_phony
9064      45,	// sub_16bit -> GR32_TC
9065      0,	// sub_16bit_hi
9066      0,	// sub_32bit
9067      0,	// sub_mask_0
9068      0,	// sub_mask_1
9069      0,	// sub_xmm
9070      0,	// sub_ymm
9071    },
9072    {	// GR32_ABCD_and_GR32_TC
9073      46,	// sub_8bit -> GR32_ABCD_and_GR32_TC
9074      46,	// sub_8bit_hi -> GR32_ABCD_and_GR32_TC
9075      0,	// sub_8bit_hi_phony
9076      46,	// sub_16bit -> GR32_ABCD_and_GR32_TC
9077      0,	// sub_16bit_hi
9078      0,	// sub_32bit
9079      0,	// sub_mask_0
9080      0,	// sub_mask_1
9081      0,	// sub_xmm
9082      0,	// sub_ymm
9083    },
9084    {	// GR32_AD
9085      47,	// sub_8bit -> GR32_AD
9086      47,	// sub_8bit_hi -> GR32_AD
9087      0,	// sub_8bit_hi_phony
9088      47,	// sub_16bit -> GR32_AD
9089      0,	// sub_16bit_hi
9090      0,	// sub_32bit
9091      0,	// sub_mask_0
9092      0,	// sub_mask_1
9093      0,	// sub_xmm
9094      0,	// sub_ymm
9095    },
9096    {	// GR32_BPSP
9097      48,	// sub_8bit -> GR32_BPSP
9098      0,	// sub_8bit_hi
9099      0,	// sub_8bit_hi_phony
9100      48,	// sub_16bit -> GR32_BPSP
9101      0,	// sub_16bit_hi
9102      0,	// sub_32bit
9103      0,	// sub_mask_0
9104      0,	// sub_mask_1
9105      0,	// sub_xmm
9106      0,	// sub_ymm
9107    },
9108    {	// GR32_BSI
9109      49,	// sub_8bit -> GR32_BSI
9110      57,	// sub_8bit_hi -> GR32_ABCD_and_GR32_BSI
9111      0,	// sub_8bit_hi_phony
9112      49,	// sub_16bit -> GR32_BSI
9113      0,	// sub_16bit_hi
9114      0,	// sub_32bit
9115      0,	// sub_mask_0
9116      0,	// sub_mask_1
9117      0,	// sub_xmm
9118      0,	// sub_ymm
9119    },
9120    {	// GR32_CB
9121      50,	// sub_8bit -> GR32_CB
9122      50,	// sub_8bit_hi -> GR32_CB
9123      0,	// sub_8bit_hi_phony
9124      50,	// sub_16bit -> GR32_CB
9125      0,	// sub_16bit_hi
9126      0,	// sub_32bit
9127      0,	// sub_mask_0
9128      0,	// sub_mask_1
9129      0,	// sub_xmm
9130      0,	// sub_ymm
9131    },
9132    {	// GR32_DC
9133      51,	// sub_8bit -> GR32_DC
9134      51,	// sub_8bit_hi -> GR32_DC
9135      0,	// sub_8bit_hi_phony
9136      51,	// sub_16bit -> GR32_DC
9137      0,	// sub_16bit_hi
9138      0,	// sub_32bit
9139      0,	// sub_mask_0
9140      0,	// sub_mask_1
9141      0,	// sub_xmm
9142      0,	// sub_ymm
9143    },
9144    {	// GR32_DIBP
9145      52,	// sub_8bit -> GR32_DIBP
9146      0,	// sub_8bit_hi
9147      0,	// sub_8bit_hi_phony
9148      52,	// sub_16bit -> GR32_DIBP
9149      0,	// sub_16bit_hi
9150      0,	// sub_32bit
9151      0,	// sub_mask_0
9152      0,	// sub_mask_1
9153      0,	// sub_xmm
9154      0,	// sub_ymm
9155    },
9156    {	// GR32_SIDI
9157      53,	// sub_8bit -> GR32_SIDI
9158      0,	// sub_8bit_hi
9159      0,	// sub_8bit_hi_phony
9160      53,	// sub_16bit -> GR32_SIDI
9161      0,	// sub_16bit_hi
9162      0,	// sub_32bit
9163      0,	// sub_mask_0
9164      0,	// sub_mask_1
9165      0,	// sub_xmm
9166      0,	// sub_ymm
9167    },
9168    {	// LOW32_ADDR_ACCESS_RBP_with_sub_32bit
9169      64,	// sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
9170      0,	// sub_8bit_hi
9171      0,	// sub_8bit_hi_phony
9172      54,	// sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
9173      0,	// sub_16bit_hi
9174      54,	// sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
9175      0,	// sub_mask_0
9176      0,	// sub_mask_1
9177      0,	// sub_xmm
9178      0,	// sub_ymm
9179    },
9180    {	// CCR
9181      0,	// sub_8bit
9182      0,	// sub_8bit_hi
9183      0,	// sub_8bit_hi_phony
9184      0,	// sub_16bit
9185      0,	// sub_16bit_hi
9186      0,	// sub_32bit
9187      0,	// sub_mask_0
9188      0,	// sub_mask_1
9189      0,	// sub_xmm
9190      0,	// sub_ymm
9191    },
9192    {	// DFCCR
9193      0,	// sub_8bit
9194      0,	// sub_8bit_hi
9195      0,	// sub_8bit_hi_phony
9196      0,	// sub_16bit
9197      0,	// sub_16bit_hi
9198      0,	// sub_32bit
9199      0,	// sub_mask_0
9200      0,	// sub_mask_1
9201      0,	// sub_xmm
9202      0,	// sub_ymm
9203    },
9204    {	// GR32_ABCD_and_GR32_BSI
9205      57,	// sub_8bit -> GR32_ABCD_and_GR32_BSI
9206      57,	// sub_8bit_hi -> GR32_ABCD_and_GR32_BSI
9207      0,	// sub_8bit_hi_phony
9208      57,	// sub_16bit -> GR32_ABCD_and_GR32_BSI
9209      0,	// sub_16bit_hi
9210      0,	// sub_32bit
9211      0,	// sub_mask_0
9212      0,	// sub_mask_1
9213      0,	// sub_xmm
9214      0,	// sub_ymm
9215    },
9216    {	// GR32_AD_and_GR32_DC
9217      58,	// sub_8bit -> GR32_AD_and_GR32_DC
9218      58,	// sub_8bit_hi -> GR32_AD_and_GR32_DC
9219      0,	// sub_8bit_hi_phony
9220      58,	// sub_16bit -> GR32_AD_and_GR32_DC
9221      0,	// sub_16bit_hi
9222      0,	// sub_32bit
9223      0,	// sub_mask_0
9224      0,	// sub_mask_1
9225      0,	// sub_xmm
9226      0,	// sub_ymm
9227    },
9228    {	// GR32_BPSP_and_GR32_DIBP
9229      59,	// sub_8bit -> GR32_BPSP_and_GR32_DIBP
9230      0,	// sub_8bit_hi
9231      0,	// sub_8bit_hi_phony
9232      59,	// sub_16bit -> GR32_BPSP_and_GR32_DIBP
9233      0,	// sub_16bit_hi
9234      0,	// sub_32bit
9235      0,	// sub_mask_0
9236      0,	// sub_mask_1
9237      0,	// sub_xmm
9238      0,	// sub_ymm
9239    },
9240    {	// GR32_BPSP_and_GR32_TC
9241      60,	// sub_8bit -> GR32_BPSP_and_GR32_TC
9242      0,	// sub_8bit_hi
9243      0,	// sub_8bit_hi_phony
9244      60,	// sub_16bit -> GR32_BPSP_and_GR32_TC
9245      0,	// sub_16bit_hi
9246      0,	// sub_32bit
9247      0,	// sub_mask_0
9248      0,	// sub_mask_1
9249      0,	// sub_xmm
9250      0,	// sub_ymm
9251    },
9252    {	// GR32_BSI_and_GR32_SIDI
9253      61,	// sub_8bit -> GR32_BSI_and_GR32_SIDI
9254      0,	// sub_8bit_hi
9255      0,	// sub_8bit_hi_phony
9256      61,	// sub_16bit -> GR32_BSI_and_GR32_SIDI
9257      0,	// sub_16bit_hi
9258      0,	// sub_32bit
9259      0,	// sub_mask_0
9260      0,	// sub_mask_1
9261      0,	// sub_xmm
9262      0,	// sub_ymm
9263    },
9264    {	// GR32_CB_and_GR32_DC
9265      62,	// sub_8bit -> GR32_CB_and_GR32_DC
9266      62,	// sub_8bit_hi -> GR32_CB_and_GR32_DC
9267      0,	// sub_8bit_hi_phony
9268      62,	// sub_16bit -> GR32_CB_and_GR32_DC
9269      0,	// sub_16bit_hi
9270      0,	// sub_32bit
9271      0,	// sub_mask_0
9272      0,	// sub_mask_1
9273      0,	// sub_xmm
9274      0,	// sub_ymm
9275    },
9276    {	// GR32_DIBP_and_GR32_SIDI
9277      63,	// sub_8bit -> GR32_DIBP_and_GR32_SIDI
9278      0,	// sub_8bit_hi
9279      0,	// sub_8bit_hi_phony
9280      63,	// sub_16bit -> GR32_DIBP_and_GR32_SIDI
9281      0,	// sub_16bit_hi
9282      0,	// sub_32bit
9283      0,	// sub_mask_0
9284      0,	// sub_mask_1
9285      0,	// sub_xmm
9286      0,	// sub_ymm
9287    },
9288    {	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
9289      64,	// sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
9290      0,	// sub_8bit_hi
9291      0,	// sub_8bit_hi_phony
9292      64,	// sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
9293      0,	// sub_16bit_hi
9294      64,	// sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
9295      0,	// sub_mask_0
9296      0,	// sub_mask_1
9297      0,	// sub_xmm
9298      0,	// sub_ymm
9299    },
9300    {	// LOW32_ADDR_ACCESS_with_sub_32bit
9301      0,	// sub_8bit
9302      0,	// sub_8bit_hi
9303      0,	// sub_8bit_hi_phony
9304      65,	// sub_16bit -> LOW32_ADDR_ACCESS_with_sub_32bit
9305      0,	// sub_16bit_hi
9306      65,	// sub_32bit -> LOW32_ADDR_ACCESS_with_sub_32bit
9307      0,	// sub_mask_0
9308      0,	// sub_mask_1
9309      0,	// sub_xmm
9310      0,	// sub_ymm
9311    },
9312    {	// RFP64
9313      0,	// sub_8bit
9314      0,	// sub_8bit_hi
9315      0,	// sub_8bit_hi_phony
9316      0,	// sub_16bit
9317      0,	// sub_16bit_hi
9318      0,	// sub_32bit
9319      0,	// sub_mask_0
9320      0,	// sub_mask_1
9321      0,	// sub_xmm
9322      0,	// sub_ymm
9323    },
9324    {	// FR64X
9325      0,	// sub_8bit
9326      0,	// sub_8bit_hi
9327      0,	// sub_8bit_hi_phony
9328      0,	// sub_16bit
9329      0,	// sub_16bit_hi
9330      0,	// sub_32bit
9331      0,	// sub_mask_0
9332      0,	// sub_mask_1
9333      0,	// sub_xmm
9334      0,	// sub_ymm
9335    },
9336    {	// GR64
9337      71,	// sub_8bit -> GR64_with_sub_8bit
9338      95,	// sub_8bit_hi -> GR64_ABCD
9339      0,	// sub_8bit_hi_phony
9340      68,	// sub_16bit -> GR64
9341      0,	// sub_16bit_hi
9342      68,	// sub_32bit -> GR64
9343      0,	// sub_mask_0
9344      0,	// sub_mask_1
9345      0,	// sub_xmm
9346      0,	// sub_ymm
9347    },
9348    {	// CONTROL_REG
9349      0,	// sub_8bit
9350      0,	// sub_8bit_hi
9351      0,	// sub_8bit_hi_phony
9352      0,	// sub_16bit
9353      0,	// sub_16bit_hi
9354      0,	// sub_32bit
9355      0,	// sub_mask_0
9356      0,	// sub_mask_1
9357      0,	// sub_xmm
9358      0,	// sub_ymm
9359    },
9360    {	// FR64
9361      0,	// sub_8bit
9362      0,	// sub_8bit_hi
9363      0,	// sub_8bit_hi_phony
9364      0,	// sub_16bit
9365      0,	// sub_16bit_hi
9366      0,	// sub_32bit
9367      0,	// sub_mask_0
9368      0,	// sub_mask_1
9369      0,	// sub_xmm
9370      0,	// sub_ymm
9371    },
9372    {	// GR64_with_sub_8bit
9373      71,	// sub_8bit -> GR64_with_sub_8bit
9374      95,	// sub_8bit_hi -> GR64_ABCD
9375      0,	// sub_8bit_hi_phony
9376      71,	// sub_16bit -> GR64_with_sub_8bit
9377      0,	// sub_16bit_hi
9378      71,	// sub_32bit -> GR64_with_sub_8bit
9379      0,	// sub_mask_0
9380      0,	// sub_mask_1
9381      0,	// sub_xmm
9382      0,	// sub_ymm
9383    },
9384    {	// GR64_NOSP
9385      72,	// sub_8bit -> GR64_NOSP
9386      95,	// sub_8bit_hi -> GR64_ABCD
9387      0,	// sub_8bit_hi_phony
9388      72,	// sub_16bit -> GR64_NOSP
9389      0,	// sub_16bit_hi
9390      72,	// sub_32bit -> GR64_NOSP
9391      0,	// sub_mask_0
9392      0,	// sub_mask_1
9393      0,	// sub_xmm
9394      0,	// sub_ymm
9395    },
9396    {	// GR64PLTSafe
9397      73,	// sub_8bit -> GR64PLTSafe
9398      95,	// sub_8bit_hi -> GR64_ABCD
9399      0,	// sub_8bit_hi_phony
9400      73,	// sub_16bit -> GR64PLTSafe
9401      0,	// sub_16bit_hi
9402      73,	// sub_32bit -> GR64PLTSafe
9403      0,	// sub_mask_0
9404      0,	// sub_mask_1
9405      0,	// sub_xmm
9406      0,	// sub_ymm
9407    },
9408    {	// GR64_TC
9409      77,	// sub_8bit -> GR64_TC_with_sub_8bit
9410      97,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
9411      0,	// sub_8bit_hi_phony
9412      74,	// sub_16bit -> GR64_TC
9413      0,	// sub_16bit_hi
9414      74,	// sub_32bit -> GR64_TC
9415      0,	// sub_mask_0
9416      0,	// sub_mask_1
9417      0,	// sub_xmm
9418      0,	// sub_ymm
9419    },
9420    {	// GR64_NOREX
9421      81,	// sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX
9422      95,	// sub_8bit_hi -> GR64_ABCD
9423      0,	// sub_8bit_hi_phony
9424      75,	// sub_16bit -> GR64_NOREX
9425      0,	// sub_16bit_hi
9426      75,	// sub_32bit -> GR64_NOREX
9427      0,	// sub_mask_0
9428      0,	// sub_mask_1
9429      0,	// sub_xmm
9430      0,	// sub_ymm
9431    },
9432    {	// GR64_TCW64
9433      79,	// sub_8bit -> GR64_TCW64_with_sub_8bit
9434      97,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
9435      0,	// sub_8bit_hi_phony
9436      76,	// sub_16bit -> GR64_TCW64
9437      0,	// sub_16bit_hi
9438      76,	// sub_32bit -> GR64_TCW64
9439      0,	// sub_mask_0
9440      0,	// sub_mask_1
9441      0,	// sub_xmm
9442      0,	// sub_ymm
9443    },
9444    {	// GR64_TC_with_sub_8bit
9445      77,	// sub_8bit -> GR64_TC_with_sub_8bit
9446      97,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
9447      0,	// sub_8bit_hi_phony
9448      77,	// sub_16bit -> GR64_TC_with_sub_8bit
9449      0,	// sub_16bit_hi
9450      77,	// sub_32bit -> GR64_TC_with_sub_8bit
9451      0,	// sub_mask_0
9452      0,	// sub_mask_1
9453      0,	// sub_xmm
9454      0,	// sub_ymm
9455    },
9456    {	// GR64_NOSP_and_GR64_TC
9457      78,	// sub_8bit -> GR64_NOSP_and_GR64_TC
9458      97,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
9459      0,	// sub_8bit_hi_phony
9460      78,	// sub_16bit -> GR64_NOSP_and_GR64_TC
9461      0,	// sub_16bit_hi
9462      78,	// sub_32bit -> GR64_NOSP_and_GR64_TC
9463      0,	// sub_mask_0
9464      0,	// sub_mask_1
9465      0,	// sub_xmm
9466      0,	// sub_ymm
9467    },
9468    {	// GR64_TCW64_with_sub_8bit
9469      79,	// sub_8bit -> GR64_TCW64_with_sub_8bit
9470      97,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
9471      0,	// sub_8bit_hi_phony
9472      79,	// sub_16bit -> GR64_TCW64_with_sub_8bit
9473      0,	// sub_16bit_hi
9474      79,	// sub_32bit -> GR64_TCW64_with_sub_8bit
9475      0,	// sub_mask_0
9476      0,	// sub_mask_1
9477      0,	// sub_xmm
9478      0,	// sub_ymm
9479    },
9480    {	// GR64_TC_and_GR64_TCW64
9481      88,	// sub_8bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
9482      97,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
9483      0,	// sub_8bit_hi_phony
9484      80,	// sub_16bit -> GR64_TC_and_GR64_TCW64
9485      0,	// sub_16bit_hi
9486      80,	// sub_32bit -> GR64_TC_and_GR64_TCW64
9487      0,	// sub_mask_0
9488      0,	// sub_mask_1
9489      0,	// sub_xmm
9490      0,	// sub_ymm
9491    },
9492    {	// GR64_with_sub_16bit_in_GR16_NOREX
9493      81,	// sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX
9494      95,	// sub_8bit_hi -> GR64_ABCD
9495      0,	// sub_8bit_hi_phony
9496      81,	// sub_16bit -> GR64_with_sub_16bit_in_GR16_NOREX
9497      0,	// sub_16bit_hi
9498      81,	// sub_32bit -> GR64_with_sub_16bit_in_GR16_NOREX
9499      0,	// sub_mask_0
9500      0,	// sub_mask_1
9501      0,	// sub_xmm
9502      0,	// sub_ymm
9503    },
9504    {	// VK64
9505      0,	// sub_8bit
9506      0,	// sub_8bit_hi
9507      0,	// sub_8bit_hi_phony
9508      0,	// sub_16bit
9509      0,	// sub_16bit_hi
9510      0,	// sub_32bit
9511      0,	// sub_mask_0
9512      0,	// sub_mask_1
9513      0,	// sub_xmm
9514      0,	// sub_ymm
9515    },
9516    {	// VR64
9517      0,	// sub_8bit
9518      0,	// sub_8bit_hi
9519      0,	// sub_8bit_hi_phony
9520      0,	// sub_16bit
9521      0,	// sub_16bit_hi
9522      0,	// sub_32bit
9523      0,	// sub_mask_0
9524      0,	// sub_mask_1
9525      0,	// sub_xmm
9526      0,	// sub_ymm
9527    },
9528    {	// GR64PLTSafe_and_GR64_TC
9529      84,	// sub_8bit -> GR64PLTSafe_and_GR64_TC
9530      97,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
9531      0,	// sub_8bit_hi_phony
9532      84,	// sub_16bit -> GR64PLTSafe_and_GR64_TC
9533      0,	// sub_16bit_hi
9534      84,	// sub_32bit -> GR64PLTSafe_and_GR64_TC
9535      0,	// sub_mask_0
9536      0,	// sub_mask_1
9537      0,	// sub_xmm
9538      0,	// sub_ymm
9539    },
9540    {	// GR64_NOREX_NOSP
9541      85,	// sub_8bit -> GR64_NOREX_NOSP
9542      95,	// sub_8bit_hi -> GR64_ABCD
9543      0,	// sub_8bit_hi_phony
9544      85,	// sub_16bit -> GR64_NOREX_NOSP
9545      0,	// sub_16bit_hi
9546      85,	// sub_32bit -> GR64_NOREX_NOSP
9547      0,	// sub_mask_0
9548      0,	// sub_mask_1
9549      0,	// sub_xmm
9550      0,	// sub_ymm
9551    },
9552    {	// GR64_NOREX_and_GR64_TC
9553      91,	// sub_8bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
9554      97,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
9555      0,	// sub_8bit_hi_phony
9556      86,	// sub_16bit -> GR64_NOREX_and_GR64_TC
9557      0,	// sub_16bit_hi
9558      86,	// sub_32bit -> GR64_NOREX_and_GR64_TC
9559      0,	// sub_mask_0
9560      0,	// sub_mask_1
9561      0,	// sub_xmm
9562      0,	// sub_ymm
9563    },
9564    {	// GR64_NOSP_and_GR64_TCW64
9565      87,	// sub_8bit -> GR64_NOSP_and_GR64_TCW64
9566      97,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
9567      0,	// sub_8bit_hi_phony
9568      87,	// sub_16bit -> GR64_NOSP_and_GR64_TCW64
9569      0,	// sub_16bit_hi
9570      87,	// sub_32bit -> GR64_NOSP_and_GR64_TCW64
9571      0,	// sub_mask_0
9572      0,	// sub_mask_1
9573      0,	// sub_xmm
9574      0,	// sub_ymm
9575    },
9576    {	// GR64_TCW64_and_GR64_TC_with_sub_8bit
9577      88,	// sub_8bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
9578      97,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
9579      0,	// sub_8bit_hi_phony
9580      88,	// sub_16bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
9581      0,	// sub_16bit_hi
9582      88,	// sub_32bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
9583      0,	// sub_mask_0
9584      0,	// sub_mask_1
9585      0,	// sub_xmm
9586      0,	// sub_ymm
9587    },
9588    {	// VK64WM
9589      0,	// sub_8bit
9590      0,	// sub_8bit_hi
9591      0,	// sub_8bit_hi_phony
9592      0,	// sub_16bit
9593      0,	// sub_16bit_hi
9594      0,	// sub_32bit
9595      0,	// sub_mask_0
9596      0,	// sub_mask_1
9597      0,	// sub_xmm
9598      0,	// sub_ymm
9599    },
9600    {	// GR64_TC_and_GR64_NOSP_and_GR64_TCW64
9601      90,	// sub_8bit -> GR64_TC_and_GR64_NOSP_and_GR64_TCW64
9602      97,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
9603      0,	// sub_8bit_hi_phony
9604      90,	// sub_16bit -> GR64_TC_and_GR64_NOSP_and_GR64_TCW64
9605      0,	// sub_16bit_hi
9606      90,	// sub_32bit -> GR64_TC_and_GR64_NOSP_and_GR64_TCW64
9607      0,	// sub_mask_0
9608      0,	// sub_mask_1
9609      0,	// sub_xmm
9610      0,	// sub_ymm
9611    },
9612    {	// GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
9613      91,	// sub_8bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
9614      97,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
9615      0,	// sub_8bit_hi_phony
9616      91,	// sub_16bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
9617      0,	// sub_16bit_hi
9618      91,	// sub_32bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
9619      0,	// sub_mask_0
9620      0,	// sub_mask_1
9621      0,	// sub_xmm
9622      0,	// sub_ymm
9623    },
9624    {	// GR64PLTSafe_and_GR64_TCW64
9625      92,	// sub_8bit -> GR64PLTSafe_and_GR64_TCW64
9626      97,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
9627      0,	// sub_8bit_hi_phony
9628      92,	// sub_16bit -> GR64PLTSafe_and_GR64_TCW64
9629      0,	// sub_16bit_hi
9630      92,	// sub_32bit -> GR64PLTSafe_and_GR64_TCW64
9631      0,	// sub_mask_0
9632      0,	// sub_mask_1
9633      0,	// sub_xmm
9634      0,	// sub_ymm
9635    },
9636    {	// GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
9637      93,	// sub_8bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
9638      97,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
9639      0,	// sub_8bit_hi_phony
9640      93,	// sub_16bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
9641      0,	// sub_16bit_hi
9642      93,	// sub_32bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
9643      0,	// sub_mask_0
9644      0,	// sub_mask_1
9645      0,	// sub_xmm
9646      0,	// sub_ymm
9647    },
9648    {	// GR64_NOREX_and_GR64_TCW64
9649      96,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_TC
9650      97,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
9651      0,	// sub_8bit_hi_phony
9652      94,	// sub_16bit -> GR64_NOREX_and_GR64_TCW64
9653      0,	// sub_16bit_hi
9654      94,	// sub_32bit -> GR64_NOREX_and_GR64_TCW64
9655      0,	// sub_mask_0
9656      0,	// sub_mask_1
9657      0,	// sub_xmm
9658      0,	// sub_ymm
9659    },
9660    {	// GR64_ABCD
9661      95,	// sub_8bit -> GR64_ABCD
9662      95,	// sub_8bit_hi -> GR64_ABCD
9663      0,	// sub_8bit_hi_phony
9664      95,	// sub_16bit -> GR64_ABCD
9665      0,	// sub_16bit_hi
9666      95,	// sub_32bit -> GR64_ABCD
9667      0,	// sub_mask_0
9668      0,	// sub_mask_1
9669      0,	// sub_xmm
9670      0,	// sub_ymm
9671    },
9672    {	// GR64_with_sub_32bit_in_GR32_TC
9673      96,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_TC
9674      97,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
9675      0,	// sub_8bit_hi_phony
9676      96,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_TC
9677      0,	// sub_16bit_hi
9678      96,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_TC
9679      0,	// sub_mask_0
9680      0,	// sub_mask_1
9681      0,	// sub_xmm
9682      0,	// sub_ymm
9683    },
9684    {	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
9685      97,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
9686      97,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
9687      0,	// sub_8bit_hi_phony
9688      97,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
9689      0,	// sub_16bit_hi
9690      97,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
9691      0,	// sub_mask_0
9692      0,	// sub_mask_1
9693      0,	// sub_xmm
9694      0,	// sub_ymm
9695    },
9696    {	// GR64_AD
9697      98,	// sub_8bit -> GR64_AD
9698      98,	// sub_8bit_hi -> GR64_AD
9699      0,	// sub_8bit_hi_phony
9700      98,	// sub_16bit -> GR64_AD
9701      0,	// sub_16bit_hi
9702      98,	// sub_32bit -> GR64_AD
9703      0,	// sub_mask_0
9704      0,	// sub_mask_1
9705      0,	// sub_xmm
9706      0,	// sub_ymm
9707    },
9708    {	// GR64_and_LOW32_ADDR_ACCESS_RBP
9709      109,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
9710      0,	// sub_8bit_hi
9711      0,	// sub_8bit_hi_phony
9712      99,	// sub_16bit -> GR64_and_LOW32_ADDR_ACCESS_RBP
9713      0,	// sub_16bit_hi
9714      99,	// sub_32bit -> GR64_and_LOW32_ADDR_ACCESS_RBP
9715      0,	// sub_mask_0
9716      0,	// sub_mask_1
9717      0,	// sub_xmm
9718      0,	// sub_ymm
9719    },
9720    {	// GR64_with_sub_32bit_in_GR32_BPSP
9721      100,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP
9722      0,	// sub_8bit_hi
9723      0,	// sub_8bit_hi_phony
9724      100,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP
9725      0,	// sub_16bit_hi
9726      100,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP
9727      0,	// sub_mask_0
9728      0,	// sub_mask_1
9729      0,	// sub_xmm
9730      0,	// sub_ymm
9731    },
9732    {	// GR64_with_sub_32bit_in_GR32_BSI
9733      101,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_BSI
9734      107,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
9735      0,	// sub_8bit_hi_phony
9736      101,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_BSI
9737      0,	// sub_16bit_hi
9738      101,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_BSI
9739      0,	// sub_mask_0
9740      0,	// sub_mask_1
9741      0,	// sub_xmm
9742      0,	// sub_ymm
9743    },
9744    {	// GR64_with_sub_32bit_in_GR32_CB
9745      102,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_CB
9746      102,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_CB
9747      0,	// sub_8bit_hi_phony
9748      102,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_CB
9749      0,	// sub_16bit_hi
9750      102,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_CB
9751      0,	// sub_mask_0
9752      0,	// sub_mask_1
9753      0,	// sub_xmm
9754      0,	// sub_ymm
9755    },
9756    {	// GR64_with_sub_32bit_in_GR32_DC
9757      103,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_DC
9758      103,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_DC
9759      0,	// sub_8bit_hi_phony
9760      103,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_DC
9761      0,	// sub_16bit_hi
9762      103,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_DC
9763      0,	// sub_mask_0
9764      0,	// sub_mask_1
9765      0,	// sub_xmm
9766      0,	// sub_ymm
9767    },
9768    {	// GR64_with_sub_32bit_in_GR32_DIBP
9769      104,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_DIBP
9770      0,	// sub_8bit_hi
9771      0,	// sub_8bit_hi_phony
9772      104,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_DIBP
9773      0,	// sub_16bit_hi
9774      104,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_DIBP
9775      0,	// sub_mask_0
9776      0,	// sub_mask_1
9777      0,	// sub_xmm
9778      0,	// sub_ymm
9779    },
9780    {	// GR64_with_sub_32bit_in_GR32_SIDI
9781      105,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_SIDI
9782      0,	// sub_8bit_hi
9783      0,	// sub_8bit_hi_phony
9784      105,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_SIDI
9785      0,	// sub_16bit_hi
9786      105,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_SIDI
9787      0,	// sub_mask_0
9788      0,	// sub_mask_1
9789      0,	// sub_xmm
9790      0,	// sub_ymm
9791    },
9792    {	// GR64_and_LOW32_ADDR_ACCESS
9793      0,	// sub_8bit
9794      0,	// sub_8bit_hi
9795      0,	// sub_8bit_hi_phony
9796      106,	// sub_16bit -> GR64_and_LOW32_ADDR_ACCESS
9797      0,	// sub_16bit_hi
9798      106,	// sub_32bit -> GR64_and_LOW32_ADDR_ACCESS
9799      0,	// sub_mask_0
9800      0,	// sub_mask_1
9801      0,	// sub_xmm
9802      0,	// sub_ymm
9803    },
9804    {	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
9805      107,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
9806      107,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
9807      0,	// sub_8bit_hi_phony
9808      107,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
9809      0,	// sub_16bit_hi
9810      107,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
9811      0,	// sub_mask_0
9812      0,	// sub_mask_1
9813      0,	// sub_xmm
9814      0,	// sub_ymm
9815    },
9816    {	// GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
9817      108,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
9818      108,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
9819      0,	// sub_8bit_hi_phony
9820      108,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
9821      0,	// sub_16bit_hi
9822      108,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
9823      0,	// sub_mask_0
9824      0,	// sub_mask_1
9825      0,	// sub_xmm
9826      0,	// sub_ymm
9827    },
9828    {	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
9829      109,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
9830      0,	// sub_8bit_hi
9831      0,	// sub_8bit_hi_phony
9832      109,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
9833      0,	// sub_16bit_hi
9834      109,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
9835      0,	// sub_mask_0
9836      0,	// sub_mask_1
9837      0,	// sub_xmm
9838      0,	// sub_ymm
9839    },
9840    {	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
9841      110,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
9842      0,	// sub_8bit_hi
9843      0,	// sub_8bit_hi_phony
9844      110,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
9845      0,	// sub_16bit_hi
9846      110,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
9847      0,	// sub_mask_0
9848      0,	// sub_mask_1
9849      0,	// sub_xmm
9850      0,	// sub_ymm
9851    },
9852    {	// GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
9853      111,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
9854      0,	// sub_8bit_hi
9855      0,	// sub_8bit_hi_phony
9856      111,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
9857      0,	// sub_16bit_hi
9858      111,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
9859      0,	// sub_mask_0
9860      0,	// sub_mask_1
9861      0,	// sub_xmm
9862      0,	// sub_ymm
9863    },
9864    {	// GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
9865      112,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
9866      112,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
9867      0,	// sub_8bit_hi_phony
9868      112,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
9869      0,	// sub_16bit_hi
9870      112,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
9871      0,	// sub_mask_0
9872      0,	// sub_mask_1
9873      0,	// sub_xmm
9874      0,	// sub_ymm
9875    },
9876    {	// GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
9877      113,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
9878      0,	// sub_8bit_hi
9879      0,	// sub_8bit_hi_phony
9880      113,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
9881      0,	// sub_16bit_hi
9882      113,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
9883      0,	// sub_mask_0
9884      0,	// sub_mask_1
9885      0,	// sub_xmm
9886      0,	// sub_ymm
9887    },
9888    {	// RST
9889      0,	// sub_8bit
9890      0,	// sub_8bit_hi
9891      0,	// sub_8bit_hi_phony
9892      0,	// sub_16bit
9893      0,	// sub_16bit_hi
9894      0,	// sub_32bit
9895      0,	// sub_mask_0
9896      0,	// sub_mask_1
9897      0,	// sub_xmm
9898      0,	// sub_ymm
9899    },
9900    {	// RFP80
9901      0,	// sub_8bit
9902      0,	// sub_8bit_hi
9903      0,	// sub_8bit_hi_phony
9904      0,	// sub_16bit
9905      0,	// sub_16bit_hi
9906      0,	// sub_32bit
9907      0,	// sub_mask_0
9908      0,	// sub_mask_1
9909      0,	// sub_xmm
9910      0,	// sub_ymm
9911    },
9912    {	// RFP80_7
9913      0,	// sub_8bit
9914      0,	// sub_8bit_hi
9915      0,	// sub_8bit_hi_phony
9916      0,	// sub_16bit
9917      0,	// sub_16bit_hi
9918      0,	// sub_32bit
9919      0,	// sub_mask_0
9920      0,	// sub_mask_1
9921      0,	// sub_xmm
9922      0,	// sub_ymm
9923    },
9924    {	// VR128X
9925      0,	// sub_8bit
9926      0,	// sub_8bit_hi
9927      0,	// sub_8bit_hi_phony
9928      0,	// sub_16bit
9929      0,	// sub_16bit_hi
9930      0,	// sub_32bit
9931      0,	// sub_mask_0
9932      0,	// sub_mask_1
9933      0,	// sub_xmm
9934      0,	// sub_ymm
9935    },
9936    {	// VR128
9937      0,	// sub_8bit
9938      0,	// sub_8bit_hi
9939      0,	// sub_8bit_hi_phony
9940      0,	// sub_16bit
9941      0,	// sub_16bit_hi
9942      0,	// sub_32bit
9943      0,	// sub_mask_0
9944      0,	// sub_mask_1
9945      0,	// sub_xmm
9946      0,	// sub_ymm
9947    },
9948    {	// VR256X
9949      0,	// sub_8bit
9950      0,	// sub_8bit_hi
9951      0,	// sub_8bit_hi_phony
9952      0,	// sub_16bit
9953      0,	// sub_16bit_hi
9954      0,	// sub_32bit
9955      0,	// sub_mask_0
9956      0,	// sub_mask_1
9957      119,	// sub_xmm -> VR256X
9958      0,	// sub_ymm
9959    },
9960    {	// VR256
9961      0,	// sub_8bit
9962      0,	// sub_8bit_hi
9963      0,	// sub_8bit_hi_phony
9964      0,	// sub_16bit
9965      0,	// sub_16bit_hi
9966      0,	// sub_32bit
9967      0,	// sub_mask_0
9968      0,	// sub_mask_1
9969      120,	// sub_xmm -> VR256
9970      0,	// sub_ymm
9971    },
9972    {	// VR512
9973      0,	// sub_8bit
9974      0,	// sub_8bit_hi
9975      0,	// sub_8bit_hi_phony
9976      0,	// sub_16bit
9977      0,	// sub_16bit_hi
9978      0,	// sub_32bit
9979      0,	// sub_mask_0
9980      0,	// sub_mask_1
9981      121,	// sub_xmm -> VR512
9982      121,	// sub_ymm -> VR512
9983    },
9984    {	// VR512_0_15
9985      0,	// sub_8bit
9986      0,	// sub_8bit_hi
9987      0,	// sub_8bit_hi_phony
9988      0,	// sub_16bit
9989      0,	// sub_16bit_hi
9990      0,	// sub_32bit
9991      0,	// sub_mask_0
9992      0,	// sub_mask_1
9993      122,	// sub_xmm -> VR512_0_15
9994      122,	// sub_ymm -> VR512_0_15
9995    },
9996    {	// TILE
9997      0,	// sub_8bit
9998      0,	// sub_8bit_hi
9999      0,	// sub_8bit_hi_phony
10000      0,	// sub_16bit
10001      0,	// sub_16bit_hi
10002      0,	// sub_32bit
10003      0,	// sub_mask_0
10004      0,	// sub_mask_1
10005      0,	// sub_xmm
10006      0,	// sub_ymm
10007    },
10008  };
10009  assert(RC && "Missing regclass");
10010  if (!Idx) return RC;
10011  --Idx;
10012  assert(Idx < 10 && "Bad subreg");
10013  unsigned TV = Table[RC->getID()][Idx];
10014  return TV ? getRegClass(TV - 1) : nullptr;
10015}
10016
10017const TargetRegisterClass *X86GenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
10018  static const uint8_t Table[123][10] = {
10019    {	// GR8
10020      0,	// GR8:sub_8bit
10021      0,	// GR8:sub_8bit_hi
10022      0,	// GR8:sub_8bit_hi_phony
10023      0,	// GR8:sub_16bit
10024      0,	// GR8:sub_16bit_hi
10025      0,	// GR8:sub_32bit
10026      0,	// GR8:sub_mask_0
10027      0,	// GR8:sub_mask_1
10028      0,	// GR8:sub_xmm
10029      0,	// GR8:sub_ymm
10030    },
10031    {	// GRH8
10032      0,	// GRH8:sub_8bit
10033      0,	// GRH8:sub_8bit_hi
10034      0,	// GRH8:sub_8bit_hi_phony
10035      0,	// GRH8:sub_16bit
10036      0,	// GRH8:sub_16bit_hi
10037      0,	// GRH8:sub_32bit
10038      0,	// GRH8:sub_mask_0
10039      0,	// GRH8:sub_mask_1
10040      0,	// GRH8:sub_xmm
10041      0,	// GRH8:sub_ymm
10042    },
10043    {	// GR8_NOREX
10044      0,	// GR8_NOREX:sub_8bit
10045      0,	// GR8_NOREX:sub_8bit_hi
10046      0,	// GR8_NOREX:sub_8bit_hi_phony
10047      0,	// GR8_NOREX:sub_16bit
10048      0,	// GR8_NOREX:sub_16bit_hi
10049      0,	// GR8_NOREX:sub_32bit
10050      0,	// GR8_NOREX:sub_mask_0
10051      0,	// GR8_NOREX:sub_mask_1
10052      0,	// GR8_NOREX:sub_xmm
10053      0,	// GR8_NOREX:sub_ymm
10054    },
10055    {	// GR8_ABCD_H
10056      0,	// GR8_ABCD_H:sub_8bit
10057      0,	// GR8_ABCD_H:sub_8bit_hi
10058      0,	// GR8_ABCD_H:sub_8bit_hi_phony
10059      0,	// GR8_ABCD_H:sub_16bit
10060      0,	// GR8_ABCD_H:sub_16bit_hi
10061      0,	// GR8_ABCD_H:sub_32bit
10062      0,	// GR8_ABCD_H:sub_mask_0
10063      0,	// GR8_ABCD_H:sub_mask_1
10064      0,	// GR8_ABCD_H:sub_xmm
10065      0,	// GR8_ABCD_H:sub_ymm
10066    },
10067    {	// GR8_ABCD_L
10068      0,	// GR8_ABCD_L:sub_8bit
10069      0,	// GR8_ABCD_L:sub_8bit_hi
10070      0,	// GR8_ABCD_L:sub_8bit_hi_phony
10071      0,	// GR8_ABCD_L:sub_16bit
10072      0,	// GR8_ABCD_L:sub_16bit_hi
10073      0,	// GR8_ABCD_L:sub_32bit
10074      0,	// GR8_ABCD_L:sub_mask_0
10075      0,	// GR8_ABCD_L:sub_mask_1
10076      0,	// GR8_ABCD_L:sub_xmm
10077      0,	// GR8_ABCD_L:sub_ymm
10078    },
10079    {	// GRH16
10080      0,	// GRH16:sub_8bit
10081      0,	// GRH16:sub_8bit_hi
10082      0,	// GRH16:sub_8bit_hi_phony
10083      0,	// GRH16:sub_16bit
10084      0,	// GRH16:sub_16bit_hi
10085      0,	// GRH16:sub_32bit
10086      0,	// GRH16:sub_mask_0
10087      0,	// GRH16:sub_mask_1
10088      0,	// GRH16:sub_xmm
10089      0,	// GRH16:sub_ymm
10090    },
10091    {	// GR16
10092      1,	// GR16:sub_8bit -> GR8
10093      4,	// GR16:sub_8bit_hi -> GR8_ABCD_H
10094      0,	// GR16:sub_8bit_hi_phony
10095      0,	// GR16:sub_16bit
10096      0,	// GR16:sub_16bit_hi
10097      0,	// GR16:sub_32bit
10098      0,	// GR16:sub_mask_0
10099      0,	// GR16:sub_mask_1
10100      0,	// GR16:sub_xmm
10101      0,	// GR16:sub_ymm
10102    },
10103    {	// GR16_NOREX
10104      1,	// GR16_NOREX:sub_8bit -> GR8
10105      4,	// GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
10106      0,	// GR16_NOREX:sub_8bit_hi_phony
10107      0,	// GR16_NOREX:sub_16bit
10108      0,	// GR16_NOREX:sub_16bit_hi
10109      0,	// GR16_NOREX:sub_32bit
10110      0,	// GR16_NOREX:sub_mask_0
10111      0,	// GR16_NOREX:sub_mask_1
10112      0,	// GR16_NOREX:sub_xmm
10113      0,	// GR16_NOREX:sub_ymm
10114    },
10115    {	// VK1
10116      0,	// VK1:sub_8bit
10117      0,	// VK1:sub_8bit_hi
10118      0,	// VK1:sub_8bit_hi_phony
10119      0,	// VK1:sub_16bit
10120      0,	// VK1:sub_16bit_hi
10121      0,	// VK1:sub_32bit
10122      0,	// VK1:sub_mask_0
10123      0,	// VK1:sub_mask_1
10124      0,	// VK1:sub_xmm
10125      0,	// VK1:sub_ymm
10126    },
10127    {	// VK16
10128      0,	// VK16:sub_8bit
10129      0,	// VK16:sub_8bit_hi
10130      0,	// VK16:sub_8bit_hi_phony
10131      0,	// VK16:sub_16bit
10132      0,	// VK16:sub_16bit_hi
10133      0,	// VK16:sub_32bit
10134      0,	// VK16:sub_mask_0
10135      0,	// VK16:sub_mask_1
10136      0,	// VK16:sub_xmm
10137      0,	// VK16:sub_ymm
10138    },
10139    {	// VK2
10140      0,	// VK2:sub_8bit
10141      0,	// VK2:sub_8bit_hi
10142      0,	// VK2:sub_8bit_hi_phony
10143      0,	// VK2:sub_16bit
10144      0,	// VK2:sub_16bit_hi
10145      0,	// VK2:sub_32bit
10146      0,	// VK2:sub_mask_0
10147      0,	// VK2:sub_mask_1
10148      0,	// VK2:sub_xmm
10149      0,	// VK2:sub_ymm
10150    },
10151    {	// VK4
10152      0,	// VK4:sub_8bit
10153      0,	// VK4:sub_8bit_hi
10154      0,	// VK4:sub_8bit_hi_phony
10155      0,	// VK4:sub_16bit
10156      0,	// VK4:sub_16bit_hi
10157      0,	// VK4:sub_32bit
10158      0,	// VK4:sub_mask_0
10159      0,	// VK4:sub_mask_1
10160      0,	// VK4:sub_xmm
10161      0,	// VK4:sub_ymm
10162    },
10163    {	// VK8
10164      0,	// VK8:sub_8bit
10165      0,	// VK8:sub_8bit_hi
10166      0,	// VK8:sub_8bit_hi_phony
10167      0,	// VK8:sub_16bit
10168      0,	// VK8:sub_16bit_hi
10169      0,	// VK8:sub_32bit
10170      0,	// VK8:sub_mask_0
10171      0,	// VK8:sub_mask_1
10172      0,	// VK8:sub_xmm
10173      0,	// VK8:sub_ymm
10174    },
10175    {	// VK16WM
10176      0,	// VK16WM:sub_8bit
10177      0,	// VK16WM:sub_8bit_hi
10178      0,	// VK16WM:sub_8bit_hi_phony
10179      0,	// VK16WM:sub_16bit
10180      0,	// VK16WM:sub_16bit_hi
10181      0,	// VK16WM:sub_32bit
10182      0,	// VK16WM:sub_mask_0
10183      0,	// VK16WM:sub_mask_1
10184      0,	// VK16WM:sub_xmm
10185      0,	// VK16WM:sub_ymm
10186    },
10187    {	// VK1WM
10188      0,	// VK1WM:sub_8bit
10189      0,	// VK1WM:sub_8bit_hi
10190      0,	// VK1WM:sub_8bit_hi_phony
10191      0,	// VK1WM:sub_16bit
10192      0,	// VK1WM:sub_16bit_hi
10193      0,	// VK1WM:sub_32bit
10194      0,	// VK1WM:sub_mask_0
10195      0,	// VK1WM:sub_mask_1
10196      0,	// VK1WM:sub_xmm
10197      0,	// VK1WM:sub_ymm
10198    },
10199    {	// VK2WM
10200      0,	// VK2WM:sub_8bit
10201      0,	// VK2WM:sub_8bit_hi
10202      0,	// VK2WM:sub_8bit_hi_phony
10203      0,	// VK2WM:sub_16bit
10204      0,	// VK2WM:sub_16bit_hi
10205      0,	// VK2WM:sub_32bit
10206      0,	// VK2WM:sub_mask_0
10207      0,	// VK2WM:sub_mask_1
10208      0,	// VK2WM:sub_xmm
10209      0,	// VK2WM:sub_ymm
10210    },
10211    {	// VK4WM
10212      0,	// VK4WM:sub_8bit
10213      0,	// VK4WM:sub_8bit_hi
10214      0,	// VK4WM:sub_8bit_hi_phony
10215      0,	// VK4WM:sub_16bit
10216      0,	// VK4WM:sub_16bit_hi
10217      0,	// VK4WM:sub_32bit
10218      0,	// VK4WM:sub_mask_0
10219      0,	// VK4WM:sub_mask_1
10220      0,	// VK4WM:sub_xmm
10221      0,	// VK4WM:sub_ymm
10222    },
10223    {	// VK8WM
10224      0,	// VK8WM:sub_8bit
10225      0,	// VK8WM:sub_8bit_hi
10226      0,	// VK8WM:sub_8bit_hi_phony
10227      0,	// VK8WM:sub_16bit
10228      0,	// VK8WM:sub_16bit_hi
10229      0,	// VK8WM:sub_32bit
10230      0,	// VK8WM:sub_mask_0
10231      0,	// VK8WM:sub_mask_1
10232      0,	// VK8WM:sub_xmm
10233      0,	// VK8WM:sub_ymm
10234    },
10235    {	// SEGMENT_REG
10236      0,	// SEGMENT_REG:sub_8bit
10237      0,	// SEGMENT_REG:sub_8bit_hi
10238      0,	// SEGMENT_REG:sub_8bit_hi_phony
10239      0,	// SEGMENT_REG:sub_16bit
10240      0,	// SEGMENT_REG:sub_16bit_hi
10241      0,	// SEGMENT_REG:sub_32bit
10242      0,	// SEGMENT_REG:sub_mask_0
10243      0,	// SEGMENT_REG:sub_mask_1
10244      0,	// SEGMENT_REG:sub_xmm
10245      0,	// SEGMENT_REG:sub_ymm
10246    },
10247    {	// GR16_ABCD
10248      5,	// GR16_ABCD:sub_8bit -> GR8_ABCD_L
10249      4,	// GR16_ABCD:sub_8bit_hi -> GR8_ABCD_H
10250      0,	// GR16_ABCD:sub_8bit_hi_phony
10251      0,	// GR16_ABCD:sub_16bit
10252      0,	// GR16_ABCD:sub_16bit_hi
10253      0,	// GR16_ABCD:sub_32bit
10254      0,	// GR16_ABCD:sub_mask_0
10255      0,	// GR16_ABCD:sub_mask_1
10256      0,	// GR16_ABCD:sub_xmm
10257      0,	// GR16_ABCD:sub_ymm
10258    },
10259    {	// FPCCR
10260      0,	// FPCCR:sub_8bit
10261      0,	// FPCCR:sub_8bit_hi
10262      0,	// FPCCR:sub_8bit_hi_phony
10263      0,	// FPCCR:sub_16bit
10264      0,	// FPCCR:sub_16bit_hi
10265      0,	// FPCCR:sub_32bit
10266      0,	// FPCCR:sub_mask_0
10267      0,	// FPCCR:sub_mask_1
10268      0,	// FPCCR:sub_xmm
10269      0,	// FPCCR:sub_ymm
10270    },
10271    {	// FR16X
10272      0,	// FR16X:sub_8bit
10273      0,	// FR16X:sub_8bit_hi
10274      0,	// FR16X:sub_8bit_hi_phony
10275      0,	// FR16X:sub_16bit
10276      0,	// FR16X:sub_16bit_hi
10277      0,	// FR16X:sub_32bit
10278      0,	// FR16X:sub_mask_0
10279      0,	// FR16X:sub_mask_1
10280      0,	// FR16X:sub_xmm
10281      0,	// FR16X:sub_ymm
10282    },
10283    {	// FR16
10284      0,	// FR16:sub_8bit
10285      0,	// FR16:sub_8bit_hi
10286      0,	// FR16:sub_8bit_hi_phony
10287      0,	// FR16:sub_16bit
10288      0,	// FR16:sub_16bit_hi
10289      0,	// FR16:sub_32bit
10290      0,	// FR16:sub_mask_0
10291      0,	// FR16:sub_mask_1
10292      0,	// FR16:sub_xmm
10293      0,	// FR16:sub_ymm
10294    },
10295    {	// VK16PAIR
10296      0,	// VK16PAIR:sub_8bit
10297      0,	// VK16PAIR:sub_8bit_hi
10298      0,	// VK16PAIR:sub_8bit_hi_phony
10299      0,	// VK16PAIR:sub_16bit
10300      0,	// VK16PAIR:sub_16bit_hi
10301      0,	// VK16PAIR:sub_32bit
10302      82,	// VK16PAIR:sub_mask_0 -> VK64
10303      89,	// VK16PAIR:sub_mask_1 -> VK64WM
10304      0,	// VK16PAIR:sub_xmm
10305      0,	// VK16PAIR:sub_ymm
10306    },
10307    {	// VK1PAIR
10308      0,	// VK1PAIR:sub_8bit
10309      0,	// VK1PAIR:sub_8bit_hi
10310      0,	// VK1PAIR:sub_8bit_hi_phony
10311      0,	// VK1PAIR:sub_16bit
10312      0,	// VK1PAIR:sub_16bit_hi
10313      0,	// VK1PAIR:sub_32bit
10314      82,	// VK1PAIR:sub_mask_0 -> VK64
10315      89,	// VK1PAIR:sub_mask_1 -> VK64WM
10316      0,	// VK1PAIR:sub_xmm
10317      0,	// VK1PAIR:sub_ymm
10318    },
10319    {	// VK2PAIR
10320      0,	// VK2PAIR:sub_8bit
10321      0,	// VK2PAIR:sub_8bit_hi
10322      0,	// VK2PAIR:sub_8bit_hi_phony
10323      0,	// VK2PAIR:sub_16bit
10324      0,	// VK2PAIR:sub_16bit_hi
10325      0,	// VK2PAIR:sub_32bit
10326      82,	// VK2PAIR:sub_mask_0 -> VK64
10327      89,	// VK2PAIR:sub_mask_1 -> VK64WM
10328      0,	// VK2PAIR:sub_xmm
10329      0,	// VK2PAIR:sub_ymm
10330    },
10331    {	// VK4PAIR
10332      0,	// VK4PAIR:sub_8bit
10333      0,	// VK4PAIR:sub_8bit_hi
10334      0,	// VK4PAIR:sub_8bit_hi_phony
10335      0,	// VK4PAIR:sub_16bit
10336      0,	// VK4PAIR:sub_16bit_hi
10337      0,	// VK4PAIR:sub_32bit
10338      82,	// VK4PAIR:sub_mask_0 -> VK64
10339      89,	// VK4PAIR:sub_mask_1 -> VK64WM
10340      0,	// VK4PAIR:sub_xmm
10341      0,	// VK4PAIR:sub_ymm
10342    },
10343    {	// VK8PAIR
10344      0,	// VK8PAIR:sub_8bit
10345      0,	// VK8PAIR:sub_8bit_hi
10346      0,	// VK8PAIR:sub_8bit_hi_phony
10347      0,	// VK8PAIR:sub_16bit
10348      0,	// VK8PAIR:sub_16bit_hi
10349      0,	// VK8PAIR:sub_32bit
10350      82,	// VK8PAIR:sub_mask_0 -> VK64
10351      89,	// VK8PAIR:sub_mask_1 -> VK64WM
10352      0,	// VK8PAIR:sub_xmm
10353      0,	// VK8PAIR:sub_ymm
10354    },
10355    {	// VK16PAIR_with_sub_mask_0_in_VK16WM
10356      0,	// VK16PAIR_with_sub_mask_0_in_VK16WM:sub_8bit
10357      0,	// VK16PAIR_with_sub_mask_0_in_VK16WM:sub_8bit_hi
10358      0,	// VK16PAIR_with_sub_mask_0_in_VK16WM:sub_8bit_hi_phony
10359      0,	// VK16PAIR_with_sub_mask_0_in_VK16WM:sub_16bit
10360      0,	// VK16PAIR_with_sub_mask_0_in_VK16WM:sub_16bit_hi
10361      0,	// VK16PAIR_with_sub_mask_0_in_VK16WM:sub_32bit
10362      89,	// VK16PAIR_with_sub_mask_0_in_VK16WM:sub_mask_0 -> VK64WM
10363      89,	// VK16PAIR_with_sub_mask_0_in_VK16WM:sub_mask_1 -> VK64WM
10364      0,	// VK16PAIR_with_sub_mask_0_in_VK16WM:sub_xmm
10365      0,	// VK16PAIR_with_sub_mask_0_in_VK16WM:sub_ymm
10366    },
10367    {	// FR32X
10368      0,	// FR32X:sub_8bit
10369      0,	// FR32X:sub_8bit_hi
10370      0,	// FR32X:sub_8bit_hi_phony
10371      0,	// FR32X:sub_16bit
10372      0,	// FR32X:sub_16bit_hi
10373      0,	// FR32X:sub_32bit
10374      0,	// FR32X:sub_mask_0
10375      0,	// FR32X:sub_mask_1
10376      0,	// FR32X:sub_xmm
10377      0,	// FR32X:sub_ymm
10378    },
10379    {	// LOW32_ADDR_ACCESS_RBP
10380      1,	// LOW32_ADDR_ACCESS_RBP:sub_8bit -> GR8
10381      4,	// LOW32_ADDR_ACCESS_RBP:sub_8bit_hi -> GR8_ABCD_H
10382      0,	// LOW32_ADDR_ACCESS_RBP:sub_8bit_hi_phony
10383      7,	// LOW32_ADDR_ACCESS_RBP:sub_16bit -> GR16
10384      0,	// LOW32_ADDR_ACCESS_RBP:sub_16bit_hi
10385      59,	// LOW32_ADDR_ACCESS_RBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
10386      0,	// LOW32_ADDR_ACCESS_RBP:sub_mask_0
10387      0,	// LOW32_ADDR_ACCESS_RBP:sub_mask_1
10388      0,	// LOW32_ADDR_ACCESS_RBP:sub_xmm
10389      0,	// LOW32_ADDR_ACCESS_RBP:sub_ymm
10390    },
10391    {	// LOW32_ADDR_ACCESS
10392      1,	// LOW32_ADDR_ACCESS:sub_8bit -> GR8
10393      4,	// LOW32_ADDR_ACCESS:sub_8bit_hi -> GR8_ABCD_H
10394      0,	// LOW32_ADDR_ACCESS:sub_8bit_hi_phony
10395      7,	// LOW32_ADDR_ACCESS:sub_16bit -> GR16
10396      0,	// LOW32_ADDR_ACCESS:sub_16bit_hi
10397      0,	// LOW32_ADDR_ACCESS:sub_32bit
10398      0,	// LOW32_ADDR_ACCESS:sub_mask_0
10399      0,	// LOW32_ADDR_ACCESS:sub_mask_1
10400      0,	// LOW32_ADDR_ACCESS:sub_xmm
10401      0,	// LOW32_ADDR_ACCESS:sub_ymm
10402    },
10403    {	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit
10404      1,	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit -> GR8
10405      4,	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
10406      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit_hi_phony
10407      7,	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_16bit -> GR16
10408      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_16bit_hi
10409      59,	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
10410      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_mask_0
10411      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_mask_1
10412      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_xmm
10413      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_ymm
10414    },
10415    {	// DEBUG_REG
10416      0,	// DEBUG_REG:sub_8bit
10417      0,	// DEBUG_REG:sub_8bit_hi
10418      0,	// DEBUG_REG:sub_8bit_hi_phony
10419      0,	// DEBUG_REG:sub_16bit
10420      0,	// DEBUG_REG:sub_16bit_hi
10421      0,	// DEBUG_REG:sub_32bit
10422      0,	// DEBUG_REG:sub_mask_0
10423      0,	// DEBUG_REG:sub_mask_1
10424      0,	// DEBUG_REG:sub_xmm
10425      0,	// DEBUG_REG:sub_ymm
10426    },
10427    {	// FR32
10428      0,	// FR32:sub_8bit
10429      0,	// FR32:sub_8bit_hi
10430      0,	// FR32:sub_8bit_hi_phony
10431      0,	// FR32:sub_16bit
10432      0,	// FR32:sub_16bit_hi
10433      0,	// FR32:sub_32bit
10434      0,	// FR32:sub_mask_0
10435      0,	// FR32:sub_mask_1
10436      0,	// FR32:sub_xmm
10437      0,	// FR32:sub_ymm
10438    },
10439    {	// GR32
10440      1,	// GR32:sub_8bit -> GR8
10441      4,	// GR32:sub_8bit_hi -> GR8_ABCD_H
10442      0,	// GR32:sub_8bit_hi_phony
10443      7,	// GR32:sub_16bit -> GR16
10444      0,	// GR32:sub_16bit_hi
10445      0,	// GR32:sub_32bit
10446      0,	// GR32:sub_mask_0
10447      0,	// GR32:sub_mask_1
10448      0,	// GR32:sub_xmm
10449      0,	// GR32:sub_ymm
10450    },
10451    {	// GR32_NOSP
10452      1,	// GR32_NOSP:sub_8bit -> GR8
10453      4,	// GR32_NOSP:sub_8bit_hi -> GR8_ABCD_H
10454      0,	// GR32_NOSP:sub_8bit_hi_phony
10455      7,	// GR32_NOSP:sub_16bit -> GR16
10456      0,	// GR32_NOSP:sub_16bit_hi
10457      0,	// GR32_NOSP:sub_32bit
10458      0,	// GR32_NOSP:sub_mask_0
10459      0,	// GR32_NOSP:sub_mask_1
10460      0,	// GR32_NOSP:sub_xmm
10461      0,	// GR32_NOSP:sub_ymm
10462    },
10463    {	// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
10464      1,	// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8
10465      4,	// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
10466      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
10467      8,	// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
10468      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
10469      59,	// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_BPSP_and_GR32_DIBP
10470      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_mask_0
10471      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_mask_1
10472      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_xmm
10473      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_ymm
10474    },
10475    {	// GR32_NOREX
10476      1,	// GR32_NOREX:sub_8bit -> GR8
10477      4,	// GR32_NOREX:sub_8bit_hi -> GR8_ABCD_H
10478      0,	// GR32_NOREX:sub_8bit_hi_phony
10479      8,	// GR32_NOREX:sub_16bit -> GR16_NOREX
10480      0,	// GR32_NOREX:sub_16bit_hi
10481      0,	// GR32_NOREX:sub_32bit
10482      0,	// GR32_NOREX:sub_mask_0
10483      0,	// GR32_NOREX:sub_mask_1
10484      0,	// GR32_NOREX:sub_xmm
10485      0,	// GR32_NOREX:sub_ymm
10486    },
10487    {	// VK32
10488      0,	// VK32:sub_8bit
10489      0,	// VK32:sub_8bit_hi
10490      0,	// VK32:sub_8bit_hi_phony
10491      0,	// VK32:sub_16bit
10492      0,	// VK32:sub_16bit_hi
10493      0,	// VK32:sub_32bit
10494      0,	// VK32:sub_mask_0
10495      0,	// VK32:sub_mask_1
10496      0,	// VK32:sub_xmm
10497      0,	// VK32:sub_ymm
10498    },
10499    {	// GR32_NOREX_NOSP
10500      1,	// GR32_NOREX_NOSP:sub_8bit -> GR8
10501      4,	// GR32_NOREX_NOSP:sub_8bit_hi -> GR8_ABCD_H
10502      0,	// GR32_NOREX_NOSP:sub_8bit_hi_phony
10503      8,	// GR32_NOREX_NOSP:sub_16bit -> GR16_NOREX
10504      0,	// GR32_NOREX_NOSP:sub_16bit_hi
10505      0,	// GR32_NOREX_NOSP:sub_32bit
10506      0,	// GR32_NOREX_NOSP:sub_mask_0
10507      0,	// GR32_NOREX_NOSP:sub_mask_1
10508      0,	// GR32_NOREX_NOSP:sub_xmm
10509      0,	// GR32_NOREX_NOSP:sub_ymm
10510    },
10511    {	// RFP32
10512      0,	// RFP32:sub_8bit
10513      0,	// RFP32:sub_8bit_hi
10514      0,	// RFP32:sub_8bit_hi_phony
10515      0,	// RFP32:sub_16bit
10516      0,	// RFP32:sub_16bit_hi
10517      0,	// RFP32:sub_32bit
10518      0,	// RFP32:sub_mask_0
10519      0,	// RFP32:sub_mask_1
10520      0,	// RFP32:sub_xmm
10521      0,	// RFP32:sub_ymm
10522    },
10523    {	// VK32WM
10524      0,	// VK32WM:sub_8bit
10525      0,	// VK32WM:sub_8bit_hi
10526      0,	// VK32WM:sub_8bit_hi_phony
10527      0,	// VK32WM:sub_16bit
10528      0,	// VK32WM:sub_16bit_hi
10529      0,	// VK32WM:sub_32bit
10530      0,	// VK32WM:sub_mask_0
10531      0,	// VK32WM:sub_mask_1
10532      0,	// VK32WM:sub_xmm
10533      0,	// VK32WM:sub_ymm
10534    },
10535    {	// GR32_ABCD
10536      5,	// GR32_ABCD:sub_8bit -> GR8_ABCD_L
10537      4,	// GR32_ABCD:sub_8bit_hi -> GR8_ABCD_H
10538      0,	// GR32_ABCD:sub_8bit_hi_phony
10539      20,	// GR32_ABCD:sub_16bit -> GR16_ABCD
10540      0,	// GR32_ABCD:sub_16bit_hi
10541      0,	// GR32_ABCD:sub_32bit
10542      0,	// GR32_ABCD:sub_mask_0
10543      0,	// GR32_ABCD:sub_mask_1
10544      0,	// GR32_ABCD:sub_xmm
10545      0,	// GR32_ABCD:sub_ymm
10546    },
10547    {	// GR32_TC
10548      1,	// GR32_TC:sub_8bit -> GR8
10549      4,	// GR32_TC:sub_8bit_hi -> GR8_ABCD_H
10550      0,	// GR32_TC:sub_8bit_hi_phony
10551      8,	// GR32_TC:sub_16bit -> GR16_NOREX
10552      0,	// GR32_TC:sub_16bit_hi
10553      0,	// GR32_TC:sub_32bit
10554      0,	// GR32_TC:sub_mask_0
10555      0,	// GR32_TC:sub_mask_1
10556      0,	// GR32_TC:sub_xmm
10557      0,	// GR32_TC:sub_ymm
10558    },
10559    {	// GR32_ABCD_and_GR32_TC
10560      5,	// GR32_ABCD_and_GR32_TC:sub_8bit -> GR8_ABCD_L
10561      4,	// GR32_ABCD_and_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
10562      0,	// GR32_ABCD_and_GR32_TC:sub_8bit_hi_phony
10563      20,	// GR32_ABCD_and_GR32_TC:sub_16bit -> GR16_ABCD
10564      0,	// GR32_ABCD_and_GR32_TC:sub_16bit_hi
10565      0,	// GR32_ABCD_and_GR32_TC:sub_32bit
10566      0,	// GR32_ABCD_and_GR32_TC:sub_mask_0
10567      0,	// GR32_ABCD_and_GR32_TC:sub_mask_1
10568      0,	// GR32_ABCD_and_GR32_TC:sub_xmm
10569      0,	// GR32_ABCD_and_GR32_TC:sub_ymm
10570    },
10571    {	// GR32_AD
10572      5,	// GR32_AD:sub_8bit -> GR8_ABCD_L
10573      4,	// GR32_AD:sub_8bit_hi -> GR8_ABCD_H
10574      0,	// GR32_AD:sub_8bit_hi_phony
10575      20,	// GR32_AD:sub_16bit -> GR16_ABCD
10576      0,	// GR32_AD:sub_16bit_hi
10577      0,	// GR32_AD:sub_32bit
10578      0,	// GR32_AD:sub_mask_0
10579      0,	// GR32_AD:sub_mask_1
10580      0,	// GR32_AD:sub_xmm
10581      0,	// GR32_AD:sub_ymm
10582    },
10583    {	// GR32_BPSP
10584      1,	// GR32_BPSP:sub_8bit -> GR8
10585      0,	// GR32_BPSP:sub_8bit_hi
10586      0,	// GR32_BPSP:sub_8bit_hi_phony
10587      8,	// GR32_BPSP:sub_16bit -> GR16_NOREX
10588      0,	// GR32_BPSP:sub_16bit_hi
10589      0,	// GR32_BPSP:sub_32bit
10590      0,	// GR32_BPSP:sub_mask_0
10591      0,	// GR32_BPSP:sub_mask_1
10592      0,	// GR32_BPSP:sub_xmm
10593      0,	// GR32_BPSP:sub_ymm
10594    },
10595    {	// GR32_BSI
10596      1,	// GR32_BSI:sub_8bit -> GR8
10597      4,	// GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
10598      0,	// GR32_BSI:sub_8bit_hi_phony
10599      8,	// GR32_BSI:sub_16bit -> GR16_NOREX
10600      0,	// GR32_BSI:sub_16bit_hi
10601      0,	// GR32_BSI:sub_32bit
10602      0,	// GR32_BSI:sub_mask_0
10603      0,	// GR32_BSI:sub_mask_1
10604      0,	// GR32_BSI:sub_xmm
10605      0,	// GR32_BSI:sub_ymm
10606    },
10607    {	// GR32_CB
10608      5,	// GR32_CB:sub_8bit -> GR8_ABCD_L
10609      4,	// GR32_CB:sub_8bit_hi -> GR8_ABCD_H
10610      0,	// GR32_CB:sub_8bit_hi_phony
10611      20,	// GR32_CB:sub_16bit -> GR16_ABCD
10612      0,	// GR32_CB:sub_16bit_hi
10613      0,	// GR32_CB:sub_32bit
10614      0,	// GR32_CB:sub_mask_0
10615      0,	// GR32_CB:sub_mask_1
10616      0,	// GR32_CB:sub_xmm
10617      0,	// GR32_CB:sub_ymm
10618    },
10619    {	// GR32_DC
10620      5,	// GR32_DC:sub_8bit -> GR8_ABCD_L
10621      4,	// GR32_DC:sub_8bit_hi -> GR8_ABCD_H
10622      0,	// GR32_DC:sub_8bit_hi_phony
10623      20,	// GR32_DC:sub_16bit -> GR16_ABCD
10624      0,	// GR32_DC:sub_16bit_hi
10625      0,	// GR32_DC:sub_32bit
10626      0,	// GR32_DC:sub_mask_0
10627      0,	// GR32_DC:sub_mask_1
10628      0,	// GR32_DC:sub_xmm
10629      0,	// GR32_DC:sub_ymm
10630    },
10631    {	// GR32_DIBP
10632      1,	// GR32_DIBP:sub_8bit -> GR8
10633      0,	// GR32_DIBP:sub_8bit_hi
10634      0,	// GR32_DIBP:sub_8bit_hi_phony
10635      8,	// GR32_DIBP:sub_16bit -> GR16_NOREX
10636      0,	// GR32_DIBP:sub_16bit_hi
10637      0,	// GR32_DIBP:sub_32bit
10638      0,	// GR32_DIBP:sub_mask_0
10639      0,	// GR32_DIBP:sub_mask_1
10640      0,	// GR32_DIBP:sub_xmm
10641      0,	// GR32_DIBP:sub_ymm
10642    },
10643    {	// GR32_SIDI
10644      1,	// GR32_SIDI:sub_8bit -> GR8
10645      0,	// GR32_SIDI:sub_8bit_hi
10646      0,	// GR32_SIDI:sub_8bit_hi_phony
10647      8,	// GR32_SIDI:sub_16bit -> GR16_NOREX
10648      0,	// GR32_SIDI:sub_16bit_hi
10649      0,	// GR32_SIDI:sub_32bit
10650      0,	// GR32_SIDI:sub_mask_0
10651      0,	// GR32_SIDI:sub_mask_1
10652      0,	// GR32_SIDI:sub_xmm
10653      0,	// GR32_SIDI:sub_ymm
10654    },
10655    {	// LOW32_ADDR_ACCESS_RBP_with_sub_32bit
10656      1,	// LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit -> GR8
10657      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit_hi
10658      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit_hi_phony
10659      8,	// LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_16bit -> GR16_NOREX
10660      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_16bit_hi
10661      59,	// LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
10662      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_mask_0
10663      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_mask_1
10664      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_xmm
10665      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_ymm
10666    },
10667    {	// CCR
10668      0,	// CCR:sub_8bit
10669      0,	// CCR:sub_8bit_hi
10670      0,	// CCR:sub_8bit_hi_phony
10671      0,	// CCR:sub_16bit
10672      0,	// CCR:sub_16bit_hi
10673      0,	// CCR:sub_32bit
10674      0,	// CCR:sub_mask_0
10675      0,	// CCR:sub_mask_1
10676      0,	// CCR:sub_xmm
10677      0,	// CCR:sub_ymm
10678    },
10679    {	// DFCCR
10680      0,	// DFCCR:sub_8bit
10681      0,	// DFCCR:sub_8bit_hi
10682      0,	// DFCCR:sub_8bit_hi_phony
10683      0,	// DFCCR:sub_16bit
10684      0,	// DFCCR:sub_16bit_hi
10685      0,	// DFCCR:sub_32bit
10686      0,	// DFCCR:sub_mask_0
10687      0,	// DFCCR:sub_mask_1
10688      0,	// DFCCR:sub_xmm
10689      0,	// DFCCR:sub_ymm
10690    },
10691    {	// GR32_ABCD_and_GR32_BSI
10692      5,	// GR32_ABCD_and_GR32_BSI:sub_8bit -> GR8_ABCD_L
10693      4,	// GR32_ABCD_and_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
10694      0,	// GR32_ABCD_and_GR32_BSI:sub_8bit_hi_phony
10695      20,	// GR32_ABCD_and_GR32_BSI:sub_16bit -> GR16_ABCD
10696      0,	// GR32_ABCD_and_GR32_BSI:sub_16bit_hi
10697      0,	// GR32_ABCD_and_GR32_BSI:sub_32bit
10698      0,	// GR32_ABCD_and_GR32_BSI:sub_mask_0
10699      0,	// GR32_ABCD_and_GR32_BSI:sub_mask_1
10700      0,	// GR32_ABCD_and_GR32_BSI:sub_xmm
10701      0,	// GR32_ABCD_and_GR32_BSI:sub_ymm
10702    },
10703    {	// GR32_AD_and_GR32_DC
10704      5,	// GR32_AD_and_GR32_DC:sub_8bit -> GR8_ABCD_L
10705      4,	// GR32_AD_and_GR32_DC:sub_8bit_hi -> GR8_ABCD_H
10706      0,	// GR32_AD_and_GR32_DC:sub_8bit_hi_phony
10707      20,	// GR32_AD_and_GR32_DC:sub_16bit -> GR16_ABCD
10708      0,	// GR32_AD_and_GR32_DC:sub_16bit_hi
10709      0,	// GR32_AD_and_GR32_DC:sub_32bit
10710      0,	// GR32_AD_and_GR32_DC:sub_mask_0
10711      0,	// GR32_AD_and_GR32_DC:sub_mask_1
10712      0,	// GR32_AD_and_GR32_DC:sub_xmm
10713      0,	// GR32_AD_and_GR32_DC:sub_ymm
10714    },
10715    {	// GR32_BPSP_and_GR32_DIBP
10716      1,	// GR32_BPSP_and_GR32_DIBP:sub_8bit -> GR8
10717      0,	// GR32_BPSP_and_GR32_DIBP:sub_8bit_hi
10718      0,	// GR32_BPSP_and_GR32_DIBP:sub_8bit_hi_phony
10719      8,	// GR32_BPSP_and_GR32_DIBP:sub_16bit -> GR16_NOREX
10720      0,	// GR32_BPSP_and_GR32_DIBP:sub_16bit_hi
10721      0,	// GR32_BPSP_and_GR32_DIBP:sub_32bit
10722      0,	// GR32_BPSP_and_GR32_DIBP:sub_mask_0
10723      0,	// GR32_BPSP_and_GR32_DIBP:sub_mask_1
10724      0,	// GR32_BPSP_and_GR32_DIBP:sub_xmm
10725      0,	// GR32_BPSP_and_GR32_DIBP:sub_ymm
10726    },
10727    {	// GR32_BPSP_and_GR32_TC
10728      1,	// GR32_BPSP_and_GR32_TC:sub_8bit -> GR8
10729      0,	// GR32_BPSP_and_GR32_TC:sub_8bit_hi
10730      0,	// GR32_BPSP_and_GR32_TC:sub_8bit_hi_phony
10731      8,	// GR32_BPSP_and_GR32_TC:sub_16bit -> GR16_NOREX
10732      0,	// GR32_BPSP_and_GR32_TC:sub_16bit_hi
10733      0,	// GR32_BPSP_and_GR32_TC:sub_32bit
10734      0,	// GR32_BPSP_and_GR32_TC:sub_mask_0
10735      0,	// GR32_BPSP_and_GR32_TC:sub_mask_1
10736      0,	// GR32_BPSP_and_GR32_TC:sub_xmm
10737      0,	// GR32_BPSP_and_GR32_TC:sub_ymm
10738    },
10739    {	// GR32_BSI_and_GR32_SIDI
10740      1,	// GR32_BSI_and_GR32_SIDI:sub_8bit -> GR8
10741      0,	// GR32_BSI_and_GR32_SIDI:sub_8bit_hi
10742      0,	// GR32_BSI_and_GR32_SIDI:sub_8bit_hi_phony
10743      8,	// GR32_BSI_and_GR32_SIDI:sub_16bit -> GR16_NOREX
10744      0,	// GR32_BSI_and_GR32_SIDI:sub_16bit_hi
10745      0,	// GR32_BSI_and_GR32_SIDI:sub_32bit
10746      0,	// GR32_BSI_and_GR32_SIDI:sub_mask_0
10747      0,	// GR32_BSI_and_GR32_SIDI:sub_mask_1
10748      0,	// GR32_BSI_and_GR32_SIDI:sub_xmm
10749      0,	// GR32_BSI_and_GR32_SIDI:sub_ymm
10750    },
10751    {	// GR32_CB_and_GR32_DC
10752      5,	// GR32_CB_and_GR32_DC:sub_8bit -> GR8_ABCD_L
10753      4,	// GR32_CB_and_GR32_DC:sub_8bit_hi -> GR8_ABCD_H
10754      0,	// GR32_CB_and_GR32_DC:sub_8bit_hi_phony
10755      20,	// GR32_CB_and_GR32_DC:sub_16bit -> GR16_ABCD
10756      0,	// GR32_CB_and_GR32_DC:sub_16bit_hi
10757      0,	// GR32_CB_and_GR32_DC:sub_32bit
10758      0,	// GR32_CB_and_GR32_DC:sub_mask_0
10759      0,	// GR32_CB_and_GR32_DC:sub_mask_1
10760      0,	// GR32_CB_and_GR32_DC:sub_xmm
10761      0,	// GR32_CB_and_GR32_DC:sub_ymm
10762    },
10763    {	// GR32_DIBP_and_GR32_SIDI
10764      1,	// GR32_DIBP_and_GR32_SIDI:sub_8bit -> GR8
10765      0,	// GR32_DIBP_and_GR32_SIDI:sub_8bit_hi
10766      0,	// GR32_DIBP_and_GR32_SIDI:sub_8bit_hi_phony
10767      8,	// GR32_DIBP_and_GR32_SIDI:sub_16bit -> GR16_NOREX
10768      0,	// GR32_DIBP_and_GR32_SIDI:sub_16bit_hi
10769      0,	// GR32_DIBP_and_GR32_SIDI:sub_32bit
10770      0,	// GR32_DIBP_and_GR32_SIDI:sub_mask_0
10771      0,	// GR32_DIBP_and_GR32_SIDI:sub_mask_1
10772      0,	// GR32_DIBP_and_GR32_SIDI:sub_xmm
10773      0,	// GR32_DIBP_and_GR32_SIDI:sub_ymm
10774    },
10775    {	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
10776      1,	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit -> GR8
10777      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit_hi
10778      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit_hi_phony
10779      8,	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_16bit -> GR16_NOREX
10780      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_16bit_hi
10781      59,	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
10782      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_mask_0
10783      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_mask_1
10784      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_xmm
10785      0,	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_ymm
10786    },
10787    {	// LOW32_ADDR_ACCESS_with_sub_32bit
10788      0,	// LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit
10789      0,	// LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit_hi
10790      0,	// LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit_hi_phony
10791      0,	// LOW32_ADDR_ACCESS_with_sub_32bit:sub_16bit
10792      0,	// LOW32_ADDR_ACCESS_with_sub_32bit:sub_16bit_hi
10793      0,	// LOW32_ADDR_ACCESS_with_sub_32bit:sub_32bit
10794      0,	// LOW32_ADDR_ACCESS_with_sub_32bit:sub_mask_0
10795      0,	// LOW32_ADDR_ACCESS_with_sub_32bit:sub_mask_1
10796      0,	// LOW32_ADDR_ACCESS_with_sub_32bit:sub_xmm
10797      0,	// LOW32_ADDR_ACCESS_with_sub_32bit:sub_ymm
10798    },
10799    {	// RFP64
10800      0,	// RFP64:sub_8bit
10801      0,	// RFP64:sub_8bit_hi
10802      0,	// RFP64:sub_8bit_hi_phony
10803      0,	// RFP64:sub_16bit
10804      0,	// RFP64:sub_16bit_hi
10805      0,	// RFP64:sub_32bit
10806      0,	// RFP64:sub_mask_0
10807      0,	// RFP64:sub_mask_1
10808      0,	// RFP64:sub_xmm
10809      0,	// RFP64:sub_ymm
10810    },
10811    {	// FR64X
10812      0,	// FR64X:sub_8bit
10813      0,	// FR64X:sub_8bit_hi
10814      0,	// FR64X:sub_8bit_hi_phony
10815      0,	// FR64X:sub_16bit
10816      0,	// FR64X:sub_16bit_hi
10817      0,	// FR64X:sub_32bit
10818      0,	// FR64X:sub_mask_0
10819      0,	// FR64X:sub_mask_1
10820      0,	// FR64X:sub_xmm
10821      0,	// FR64X:sub_ymm
10822    },
10823    {	// GR64
10824      1,	// GR64:sub_8bit -> GR8
10825      4,	// GR64:sub_8bit_hi -> GR8_ABCD_H
10826      0,	// GR64:sub_8bit_hi_phony
10827      7,	// GR64:sub_16bit -> GR16
10828      0,	// GR64:sub_16bit_hi
10829      36,	// GR64:sub_32bit -> GR32
10830      0,	// GR64:sub_mask_0
10831      0,	// GR64:sub_mask_1
10832      0,	// GR64:sub_xmm
10833      0,	// GR64:sub_ymm
10834    },
10835    {	// CONTROL_REG
10836      0,	// CONTROL_REG:sub_8bit
10837      0,	// CONTROL_REG:sub_8bit_hi
10838      0,	// CONTROL_REG:sub_8bit_hi_phony
10839      0,	// CONTROL_REG:sub_16bit
10840      0,	// CONTROL_REG:sub_16bit_hi
10841      0,	// CONTROL_REG:sub_32bit
10842      0,	// CONTROL_REG:sub_mask_0
10843      0,	// CONTROL_REG:sub_mask_1
10844      0,	// CONTROL_REG:sub_xmm
10845      0,	// CONTROL_REG:sub_ymm
10846    },
10847    {	// FR64
10848      0,	// FR64:sub_8bit
10849      0,	// FR64:sub_8bit_hi
10850      0,	// FR64:sub_8bit_hi_phony
10851      0,	// FR64:sub_16bit
10852      0,	// FR64:sub_16bit_hi
10853      0,	// FR64:sub_32bit
10854      0,	// FR64:sub_mask_0
10855      0,	// FR64:sub_mask_1
10856      0,	// FR64:sub_xmm
10857      0,	// FR64:sub_ymm
10858    },
10859    {	// GR64_with_sub_8bit
10860      1,	// GR64_with_sub_8bit:sub_8bit -> GR8
10861      4,	// GR64_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
10862      0,	// GR64_with_sub_8bit:sub_8bit_hi_phony
10863      7,	// GR64_with_sub_8bit:sub_16bit -> GR16
10864      0,	// GR64_with_sub_8bit:sub_16bit_hi
10865      36,	// GR64_with_sub_8bit:sub_32bit -> GR32
10866      0,	// GR64_with_sub_8bit:sub_mask_0
10867      0,	// GR64_with_sub_8bit:sub_mask_1
10868      0,	// GR64_with_sub_8bit:sub_xmm
10869      0,	// GR64_with_sub_8bit:sub_ymm
10870    },
10871    {	// GR64_NOSP
10872      1,	// GR64_NOSP:sub_8bit -> GR8
10873      4,	// GR64_NOSP:sub_8bit_hi -> GR8_ABCD_H
10874      0,	// GR64_NOSP:sub_8bit_hi_phony
10875      7,	// GR64_NOSP:sub_16bit -> GR16
10876      0,	// GR64_NOSP:sub_16bit_hi
10877      37,	// GR64_NOSP:sub_32bit -> GR32_NOSP
10878      0,	// GR64_NOSP:sub_mask_0
10879      0,	// GR64_NOSP:sub_mask_1
10880      0,	// GR64_NOSP:sub_xmm
10881      0,	// GR64_NOSP:sub_ymm
10882    },
10883    {	// GR64PLTSafe
10884      1,	// GR64PLTSafe:sub_8bit -> GR8
10885      4,	// GR64PLTSafe:sub_8bit_hi -> GR8_ABCD_H
10886      0,	// GR64PLTSafe:sub_8bit_hi_phony
10887      7,	// GR64PLTSafe:sub_16bit -> GR16
10888      0,	// GR64PLTSafe:sub_16bit_hi
10889      37,	// GR64PLTSafe:sub_32bit -> GR32_NOSP
10890      0,	// GR64PLTSafe:sub_mask_0
10891      0,	// GR64PLTSafe:sub_mask_1
10892      0,	// GR64PLTSafe:sub_xmm
10893      0,	// GR64PLTSafe:sub_ymm
10894    },
10895    {	// GR64_TC
10896      1,	// GR64_TC:sub_8bit -> GR8
10897      4,	// GR64_TC:sub_8bit_hi -> GR8_ABCD_H
10898      0,	// GR64_TC:sub_8bit_hi_phony
10899      7,	// GR64_TC:sub_16bit -> GR16
10900      0,	// GR64_TC:sub_16bit_hi
10901      36,	// GR64_TC:sub_32bit -> GR32
10902      0,	// GR64_TC:sub_mask_0
10903      0,	// GR64_TC:sub_mask_1
10904      0,	// GR64_TC:sub_xmm
10905      0,	// GR64_TC:sub_ymm
10906    },
10907    {	// GR64_NOREX
10908      1,	// GR64_NOREX:sub_8bit -> GR8
10909      4,	// GR64_NOREX:sub_8bit_hi -> GR8_ABCD_H
10910      0,	// GR64_NOREX:sub_8bit_hi_phony
10911      8,	// GR64_NOREX:sub_16bit -> GR16_NOREX
10912      0,	// GR64_NOREX:sub_16bit_hi
10913      39,	// GR64_NOREX:sub_32bit -> GR32_NOREX
10914      0,	// GR64_NOREX:sub_mask_0
10915      0,	// GR64_NOREX:sub_mask_1
10916      0,	// GR64_NOREX:sub_xmm
10917      0,	// GR64_NOREX:sub_ymm
10918    },
10919    {	// GR64_TCW64
10920      1,	// GR64_TCW64:sub_8bit -> GR8
10921      4,	// GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
10922      0,	// GR64_TCW64:sub_8bit_hi_phony
10923      7,	// GR64_TCW64:sub_16bit -> GR16
10924      0,	// GR64_TCW64:sub_16bit_hi
10925      36,	// GR64_TCW64:sub_32bit -> GR32
10926      0,	// GR64_TCW64:sub_mask_0
10927      0,	// GR64_TCW64:sub_mask_1
10928      0,	// GR64_TCW64:sub_xmm
10929      0,	// GR64_TCW64:sub_ymm
10930    },
10931    {	// GR64_TC_with_sub_8bit
10932      1,	// GR64_TC_with_sub_8bit:sub_8bit -> GR8
10933      4,	// GR64_TC_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
10934      0,	// GR64_TC_with_sub_8bit:sub_8bit_hi_phony
10935      7,	// GR64_TC_with_sub_8bit:sub_16bit -> GR16
10936      0,	// GR64_TC_with_sub_8bit:sub_16bit_hi
10937      36,	// GR64_TC_with_sub_8bit:sub_32bit -> GR32
10938      0,	// GR64_TC_with_sub_8bit:sub_mask_0
10939      0,	// GR64_TC_with_sub_8bit:sub_mask_1
10940      0,	// GR64_TC_with_sub_8bit:sub_xmm
10941      0,	// GR64_TC_with_sub_8bit:sub_ymm
10942    },
10943    {	// GR64_NOSP_and_GR64_TC
10944      1,	// GR64_NOSP_and_GR64_TC:sub_8bit -> GR8
10945      4,	// GR64_NOSP_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
10946      0,	// GR64_NOSP_and_GR64_TC:sub_8bit_hi_phony
10947      7,	// GR64_NOSP_and_GR64_TC:sub_16bit -> GR16
10948      0,	// GR64_NOSP_and_GR64_TC:sub_16bit_hi
10949      37,	// GR64_NOSP_and_GR64_TC:sub_32bit -> GR32_NOSP
10950      0,	// GR64_NOSP_and_GR64_TC:sub_mask_0
10951      0,	// GR64_NOSP_and_GR64_TC:sub_mask_1
10952      0,	// GR64_NOSP_and_GR64_TC:sub_xmm
10953      0,	// GR64_NOSP_and_GR64_TC:sub_ymm
10954    },
10955    {	// GR64_TCW64_with_sub_8bit
10956      1,	// GR64_TCW64_with_sub_8bit:sub_8bit -> GR8
10957      4,	// GR64_TCW64_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
10958      0,	// GR64_TCW64_with_sub_8bit:sub_8bit_hi_phony
10959      7,	// GR64_TCW64_with_sub_8bit:sub_16bit -> GR16
10960      0,	// GR64_TCW64_with_sub_8bit:sub_16bit_hi
10961      36,	// GR64_TCW64_with_sub_8bit:sub_32bit -> GR32
10962      0,	// GR64_TCW64_with_sub_8bit:sub_mask_0
10963      0,	// GR64_TCW64_with_sub_8bit:sub_mask_1
10964      0,	// GR64_TCW64_with_sub_8bit:sub_xmm
10965      0,	// GR64_TCW64_with_sub_8bit:sub_ymm
10966    },
10967    {	// GR64_TC_and_GR64_TCW64
10968      1,	// GR64_TC_and_GR64_TCW64:sub_8bit -> GR8
10969      4,	// GR64_TC_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
10970      0,	// GR64_TC_and_GR64_TCW64:sub_8bit_hi_phony
10971      7,	// GR64_TC_and_GR64_TCW64:sub_16bit -> GR16
10972      0,	// GR64_TC_and_GR64_TCW64:sub_16bit_hi
10973      36,	// GR64_TC_and_GR64_TCW64:sub_32bit -> GR32
10974      0,	// GR64_TC_and_GR64_TCW64:sub_mask_0
10975      0,	// GR64_TC_and_GR64_TCW64:sub_mask_1
10976      0,	// GR64_TC_and_GR64_TCW64:sub_xmm
10977      0,	// GR64_TC_and_GR64_TCW64:sub_ymm
10978    },
10979    {	// GR64_with_sub_16bit_in_GR16_NOREX
10980      1,	// GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8
10981      4,	// GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
10982      0,	// GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
10983      8,	// GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
10984      0,	// GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
10985      39,	// GR64_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_NOREX
10986      0,	// GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_0
10987      0,	// GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_1
10988      0,	// GR64_with_sub_16bit_in_GR16_NOREX:sub_xmm
10989      0,	// GR64_with_sub_16bit_in_GR16_NOREX:sub_ymm
10990    },
10991    {	// VK64
10992      0,	// VK64:sub_8bit
10993      0,	// VK64:sub_8bit_hi
10994      0,	// VK64:sub_8bit_hi_phony
10995      0,	// VK64:sub_16bit
10996      0,	// VK64:sub_16bit_hi
10997      0,	// VK64:sub_32bit
10998      0,	// VK64:sub_mask_0
10999      0,	// VK64:sub_mask_1
11000      0,	// VK64:sub_xmm
11001      0,	// VK64:sub_ymm
11002    },
11003    {	// VR64
11004      0,	// VR64:sub_8bit
11005      0,	// VR64:sub_8bit_hi
11006      0,	// VR64:sub_8bit_hi_phony
11007      0,	// VR64:sub_16bit
11008      0,	// VR64:sub_16bit_hi
11009      0,	// VR64:sub_32bit
11010      0,	// VR64:sub_mask_0
11011      0,	// VR64:sub_mask_1
11012      0,	// VR64:sub_xmm
11013      0,	// VR64:sub_ymm
11014    },
11015    {	// GR64PLTSafe_and_GR64_TC
11016      1,	// GR64PLTSafe_and_GR64_TC:sub_8bit -> GR8
11017      4,	// GR64PLTSafe_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
11018      0,	// GR64PLTSafe_and_GR64_TC:sub_8bit_hi_phony
11019      7,	// GR64PLTSafe_and_GR64_TC:sub_16bit -> GR16
11020      0,	// GR64PLTSafe_and_GR64_TC:sub_16bit_hi
11021      37,	// GR64PLTSafe_and_GR64_TC:sub_32bit -> GR32_NOSP
11022      0,	// GR64PLTSafe_and_GR64_TC:sub_mask_0
11023      0,	// GR64PLTSafe_and_GR64_TC:sub_mask_1
11024      0,	// GR64PLTSafe_and_GR64_TC:sub_xmm
11025      0,	// GR64PLTSafe_and_GR64_TC:sub_ymm
11026    },
11027    {	// GR64_NOREX_NOSP
11028      1,	// GR64_NOREX_NOSP:sub_8bit -> GR8
11029      4,	// GR64_NOREX_NOSP:sub_8bit_hi -> GR8_ABCD_H
11030      0,	// GR64_NOREX_NOSP:sub_8bit_hi_phony
11031      8,	// GR64_NOREX_NOSP:sub_16bit -> GR16_NOREX
11032      0,	// GR64_NOREX_NOSP:sub_16bit_hi
11033      41,	// GR64_NOREX_NOSP:sub_32bit -> GR32_NOREX_NOSP
11034      0,	// GR64_NOREX_NOSP:sub_mask_0
11035      0,	// GR64_NOREX_NOSP:sub_mask_1
11036      0,	// GR64_NOREX_NOSP:sub_xmm
11037      0,	// GR64_NOREX_NOSP:sub_ymm
11038    },
11039    {	// GR64_NOREX_and_GR64_TC
11040      1,	// GR64_NOREX_and_GR64_TC:sub_8bit -> GR8
11041      4,	// GR64_NOREX_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
11042      0,	// GR64_NOREX_and_GR64_TC:sub_8bit_hi_phony
11043      8,	// GR64_NOREX_and_GR64_TC:sub_16bit -> GR16_NOREX
11044      0,	// GR64_NOREX_and_GR64_TC:sub_16bit_hi
11045      39,	// GR64_NOREX_and_GR64_TC:sub_32bit -> GR32_NOREX
11046      0,	// GR64_NOREX_and_GR64_TC:sub_mask_0
11047      0,	// GR64_NOREX_and_GR64_TC:sub_mask_1
11048      0,	// GR64_NOREX_and_GR64_TC:sub_xmm
11049      0,	// GR64_NOREX_and_GR64_TC:sub_ymm
11050    },
11051    {	// GR64_NOSP_and_GR64_TCW64
11052      1,	// GR64_NOSP_and_GR64_TCW64:sub_8bit -> GR8
11053      4,	// GR64_NOSP_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
11054      0,	// GR64_NOSP_and_GR64_TCW64:sub_8bit_hi_phony
11055      7,	// GR64_NOSP_and_GR64_TCW64:sub_16bit -> GR16
11056      0,	// GR64_NOSP_and_GR64_TCW64:sub_16bit_hi
11057      37,	// GR64_NOSP_and_GR64_TCW64:sub_32bit -> GR32_NOSP
11058      0,	// GR64_NOSP_and_GR64_TCW64:sub_mask_0
11059      0,	// GR64_NOSP_and_GR64_TCW64:sub_mask_1
11060      0,	// GR64_NOSP_and_GR64_TCW64:sub_xmm
11061      0,	// GR64_NOSP_and_GR64_TCW64:sub_ymm
11062    },
11063    {	// GR64_TCW64_and_GR64_TC_with_sub_8bit
11064      1,	// GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit -> GR8
11065      4,	// GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
11066      0,	// GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit_hi_phony
11067      7,	// GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_16bit -> GR16
11068      0,	// GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_16bit_hi
11069      36,	// GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_32bit -> GR32
11070      0,	// GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_mask_0
11071      0,	// GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_mask_1
11072      0,	// GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_xmm
11073      0,	// GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_ymm
11074    },
11075    {	// VK64WM
11076      0,	// VK64WM:sub_8bit
11077      0,	// VK64WM:sub_8bit_hi
11078      0,	// VK64WM:sub_8bit_hi_phony
11079      0,	// VK64WM:sub_16bit
11080      0,	// VK64WM:sub_16bit_hi
11081      0,	// VK64WM:sub_32bit
11082      0,	// VK64WM:sub_mask_0
11083      0,	// VK64WM:sub_mask_1
11084      0,	// VK64WM:sub_xmm
11085      0,	// VK64WM:sub_ymm
11086    },
11087    {	// GR64_TC_and_GR64_NOSP_and_GR64_TCW64
11088      1,	// GR64_TC_and_GR64_NOSP_and_GR64_TCW64:sub_8bit -> GR8
11089      4,	// GR64_TC_and_GR64_NOSP_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
11090      0,	// GR64_TC_and_GR64_NOSP_and_GR64_TCW64:sub_8bit_hi_phony
11091      7,	// GR64_TC_and_GR64_NOSP_and_GR64_TCW64:sub_16bit -> GR16
11092      0,	// GR64_TC_and_GR64_NOSP_and_GR64_TCW64:sub_16bit_hi
11093      37,	// GR64_TC_and_GR64_NOSP_and_GR64_TCW64:sub_32bit -> GR32_NOSP
11094      0,	// GR64_TC_and_GR64_NOSP_and_GR64_TCW64:sub_mask_0
11095      0,	// GR64_TC_and_GR64_NOSP_and_GR64_TCW64:sub_mask_1
11096      0,	// GR64_TC_and_GR64_NOSP_and_GR64_TCW64:sub_xmm
11097      0,	// GR64_TC_and_GR64_NOSP_and_GR64_TCW64:sub_ymm
11098    },
11099    {	// GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
11100      1,	// GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8
11101      4,	// GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
11102      0,	// GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
11103      8,	// GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
11104      0,	// GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
11105      39,	// GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_NOREX
11106      0,	// GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_0
11107      0,	// GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_1
11108      0,	// GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_xmm
11109      0,	// GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_ymm
11110    },
11111    {	// GR64PLTSafe_and_GR64_TCW64
11112      1,	// GR64PLTSafe_and_GR64_TCW64:sub_8bit -> GR8
11113      4,	// GR64PLTSafe_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
11114      0,	// GR64PLTSafe_and_GR64_TCW64:sub_8bit_hi_phony
11115      7,	// GR64PLTSafe_and_GR64_TCW64:sub_16bit -> GR16
11116      0,	// GR64PLTSafe_and_GR64_TCW64:sub_16bit_hi
11117      37,	// GR64PLTSafe_and_GR64_TCW64:sub_32bit -> GR32_NOSP
11118      0,	// GR64PLTSafe_and_GR64_TCW64:sub_mask_0
11119      0,	// GR64PLTSafe_and_GR64_TCW64:sub_mask_1
11120      0,	// GR64PLTSafe_and_GR64_TCW64:sub_xmm
11121      0,	// GR64PLTSafe_and_GR64_TCW64:sub_ymm
11122    },
11123    {	// GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
11124      1,	// GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit -> GR8
11125      4,	// GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
11126      0,	// GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit_hi_phony
11127      8,	// GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_16bit -> GR16_NOREX
11128      0,	// GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_16bit_hi
11129      41,	// GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_32bit -> GR32_NOREX_NOSP
11130      0,	// GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_mask_0
11131      0,	// GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_mask_1
11132      0,	// GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_xmm
11133      0,	// GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_ymm
11134    },
11135    {	// GR64_NOREX_and_GR64_TCW64
11136      1,	// GR64_NOREX_and_GR64_TCW64:sub_8bit -> GR8
11137      4,	// GR64_NOREX_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
11138      0,	// GR64_NOREX_and_GR64_TCW64:sub_8bit_hi_phony
11139      8,	// GR64_NOREX_and_GR64_TCW64:sub_16bit -> GR16_NOREX
11140      0,	// GR64_NOREX_and_GR64_TCW64:sub_16bit_hi
11141      45,	// GR64_NOREX_and_GR64_TCW64:sub_32bit -> GR32_TC
11142      0,	// GR64_NOREX_and_GR64_TCW64:sub_mask_0
11143      0,	// GR64_NOREX_and_GR64_TCW64:sub_mask_1
11144      0,	// GR64_NOREX_and_GR64_TCW64:sub_xmm
11145      0,	// GR64_NOREX_and_GR64_TCW64:sub_ymm
11146    },
11147    {	// GR64_ABCD
11148      5,	// GR64_ABCD:sub_8bit -> GR8_ABCD_L
11149      4,	// GR64_ABCD:sub_8bit_hi -> GR8_ABCD_H
11150      0,	// GR64_ABCD:sub_8bit_hi_phony
11151      20,	// GR64_ABCD:sub_16bit -> GR16_ABCD
11152      0,	// GR64_ABCD:sub_16bit_hi
11153      44,	// GR64_ABCD:sub_32bit -> GR32_ABCD
11154      0,	// GR64_ABCD:sub_mask_0
11155      0,	// GR64_ABCD:sub_mask_1
11156      0,	// GR64_ABCD:sub_xmm
11157      0,	// GR64_ABCD:sub_ymm
11158    },
11159    {	// GR64_with_sub_32bit_in_GR32_TC
11160      1,	// GR64_with_sub_32bit_in_GR32_TC:sub_8bit -> GR8
11161      4,	// GR64_with_sub_32bit_in_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
11162      0,	// GR64_with_sub_32bit_in_GR32_TC:sub_8bit_hi_phony
11163      8,	// GR64_with_sub_32bit_in_GR32_TC:sub_16bit -> GR16_NOREX
11164      0,	// GR64_with_sub_32bit_in_GR32_TC:sub_16bit_hi
11165      45,	// GR64_with_sub_32bit_in_GR32_TC:sub_32bit -> GR32_TC
11166      0,	// GR64_with_sub_32bit_in_GR32_TC:sub_mask_0
11167      0,	// GR64_with_sub_32bit_in_GR32_TC:sub_mask_1
11168      0,	// GR64_with_sub_32bit_in_GR32_TC:sub_xmm
11169      0,	// GR64_with_sub_32bit_in_GR32_TC:sub_ymm
11170    },
11171    {	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11172      5,	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit -> GR8_ABCD_L
11173      4,	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
11174      0,	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit_hi_phony
11175      20,	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_16bit -> GR16_ABCD
11176      0,	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_16bit_hi
11177      46,	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_32bit -> GR32_ABCD_and_GR32_TC
11178      0,	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_mask_0
11179      0,	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_mask_1
11180      0,	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_xmm
11181      0,	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_ymm
11182    },
11183    {	// GR64_AD
11184      5,	// GR64_AD:sub_8bit -> GR8_ABCD_L
11185      4,	// GR64_AD:sub_8bit_hi -> GR8_ABCD_H
11186      0,	// GR64_AD:sub_8bit_hi_phony
11187      20,	// GR64_AD:sub_16bit -> GR16_ABCD
11188      0,	// GR64_AD:sub_16bit_hi
11189      47,	// GR64_AD:sub_32bit -> GR32_AD
11190      0,	// GR64_AD:sub_mask_0
11191      0,	// GR64_AD:sub_mask_1
11192      0,	// GR64_AD:sub_xmm
11193      0,	// GR64_AD:sub_ymm
11194    },
11195    {	// GR64_and_LOW32_ADDR_ACCESS_RBP
11196      1,	// GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit -> GR8
11197      0,	// GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit_hi
11198      0,	// GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit_hi_phony
11199      8,	// GR64_and_LOW32_ADDR_ACCESS_RBP:sub_16bit -> GR16_NOREX
11200      0,	// GR64_and_LOW32_ADDR_ACCESS_RBP:sub_16bit_hi
11201      59,	// GR64_and_LOW32_ADDR_ACCESS_RBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
11202      0,	// GR64_and_LOW32_ADDR_ACCESS_RBP:sub_mask_0
11203      0,	// GR64_and_LOW32_ADDR_ACCESS_RBP:sub_mask_1
11204      0,	// GR64_and_LOW32_ADDR_ACCESS_RBP:sub_xmm
11205      0,	// GR64_and_LOW32_ADDR_ACCESS_RBP:sub_ymm
11206    },
11207    {	// GR64_with_sub_32bit_in_GR32_BPSP
11208      1,	// GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit -> GR8
11209      0,	// GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit_hi
11210      0,	// GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit_hi_phony
11211      8,	// GR64_with_sub_32bit_in_GR32_BPSP:sub_16bit -> GR16_NOREX
11212      0,	// GR64_with_sub_32bit_in_GR32_BPSP:sub_16bit_hi
11213      48,	// GR64_with_sub_32bit_in_GR32_BPSP:sub_32bit -> GR32_BPSP
11214      0,	// GR64_with_sub_32bit_in_GR32_BPSP:sub_mask_0
11215      0,	// GR64_with_sub_32bit_in_GR32_BPSP:sub_mask_1
11216      0,	// GR64_with_sub_32bit_in_GR32_BPSP:sub_xmm
11217      0,	// GR64_with_sub_32bit_in_GR32_BPSP:sub_ymm
11218    },
11219    {	// GR64_with_sub_32bit_in_GR32_BSI
11220      1,	// GR64_with_sub_32bit_in_GR32_BSI:sub_8bit -> GR8
11221      4,	// GR64_with_sub_32bit_in_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
11222      0,	// GR64_with_sub_32bit_in_GR32_BSI:sub_8bit_hi_phony
11223      8,	// GR64_with_sub_32bit_in_GR32_BSI:sub_16bit -> GR16_NOREX
11224      0,	// GR64_with_sub_32bit_in_GR32_BSI:sub_16bit_hi
11225      49,	// GR64_with_sub_32bit_in_GR32_BSI:sub_32bit -> GR32_BSI
11226      0,	// GR64_with_sub_32bit_in_GR32_BSI:sub_mask_0
11227      0,	// GR64_with_sub_32bit_in_GR32_BSI:sub_mask_1
11228      0,	// GR64_with_sub_32bit_in_GR32_BSI:sub_xmm
11229      0,	// GR64_with_sub_32bit_in_GR32_BSI:sub_ymm
11230    },
11231    {	// GR64_with_sub_32bit_in_GR32_CB
11232      5,	// GR64_with_sub_32bit_in_GR32_CB:sub_8bit -> GR8_ABCD_L
11233      4,	// GR64_with_sub_32bit_in_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
11234      0,	// GR64_with_sub_32bit_in_GR32_CB:sub_8bit_hi_phony
11235      20,	// GR64_with_sub_32bit_in_GR32_CB:sub_16bit -> GR16_ABCD
11236      0,	// GR64_with_sub_32bit_in_GR32_CB:sub_16bit_hi
11237      50,	// GR64_with_sub_32bit_in_GR32_CB:sub_32bit -> GR32_CB
11238      0,	// GR64_with_sub_32bit_in_GR32_CB:sub_mask_0
11239      0,	// GR64_with_sub_32bit_in_GR32_CB:sub_mask_1
11240      0,	// GR64_with_sub_32bit_in_GR32_CB:sub_xmm
11241      0,	// GR64_with_sub_32bit_in_GR32_CB:sub_ymm
11242    },
11243    {	// GR64_with_sub_32bit_in_GR32_DC
11244      5,	// GR64_with_sub_32bit_in_GR32_DC:sub_8bit -> GR8_ABCD_L
11245      4,	// GR64_with_sub_32bit_in_GR32_DC:sub_8bit_hi -> GR8_ABCD_H
11246      0,	// GR64_with_sub_32bit_in_GR32_DC:sub_8bit_hi_phony
11247      20,	// GR64_with_sub_32bit_in_GR32_DC:sub_16bit -> GR16_ABCD
11248      0,	// GR64_with_sub_32bit_in_GR32_DC:sub_16bit_hi
11249      51,	// GR64_with_sub_32bit_in_GR32_DC:sub_32bit -> GR32_DC
11250      0,	// GR64_with_sub_32bit_in_GR32_DC:sub_mask_0
11251      0,	// GR64_with_sub_32bit_in_GR32_DC:sub_mask_1
11252      0,	// GR64_with_sub_32bit_in_GR32_DC:sub_xmm
11253      0,	// GR64_with_sub_32bit_in_GR32_DC:sub_ymm
11254    },
11255    {	// GR64_with_sub_32bit_in_GR32_DIBP
11256      1,	// GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit -> GR8
11257      0,	// GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit_hi
11258      0,	// GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit_hi_phony
11259      8,	// GR64_with_sub_32bit_in_GR32_DIBP:sub_16bit -> GR16_NOREX
11260      0,	// GR64_with_sub_32bit_in_GR32_DIBP:sub_16bit_hi
11261      52,	// GR64_with_sub_32bit_in_GR32_DIBP:sub_32bit -> GR32_DIBP
11262      0,	// GR64_with_sub_32bit_in_GR32_DIBP:sub_mask_0
11263      0,	// GR64_with_sub_32bit_in_GR32_DIBP:sub_mask_1
11264      0,	// GR64_with_sub_32bit_in_GR32_DIBP:sub_xmm
11265      0,	// GR64_with_sub_32bit_in_GR32_DIBP:sub_ymm
11266    },
11267    {	// GR64_with_sub_32bit_in_GR32_SIDI
11268      1,	// GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit -> GR8
11269      0,	// GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit_hi
11270      0,	// GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit_hi_phony
11271      8,	// GR64_with_sub_32bit_in_GR32_SIDI:sub_16bit -> GR16_NOREX
11272      0,	// GR64_with_sub_32bit_in_GR32_SIDI:sub_16bit_hi
11273      53,	// GR64_with_sub_32bit_in_GR32_SIDI:sub_32bit -> GR32_SIDI
11274      0,	// GR64_with_sub_32bit_in_GR32_SIDI:sub_mask_0
11275      0,	// GR64_with_sub_32bit_in_GR32_SIDI:sub_mask_1
11276      0,	// GR64_with_sub_32bit_in_GR32_SIDI:sub_xmm
11277      0,	// GR64_with_sub_32bit_in_GR32_SIDI:sub_ymm
11278    },
11279    {	// GR64_and_LOW32_ADDR_ACCESS
11280      0,	// GR64_and_LOW32_ADDR_ACCESS:sub_8bit
11281      0,	// GR64_and_LOW32_ADDR_ACCESS:sub_8bit_hi
11282      0,	// GR64_and_LOW32_ADDR_ACCESS:sub_8bit_hi_phony
11283      0,	// GR64_and_LOW32_ADDR_ACCESS:sub_16bit
11284      0,	// GR64_and_LOW32_ADDR_ACCESS:sub_16bit_hi
11285      0,	// GR64_and_LOW32_ADDR_ACCESS:sub_32bit
11286      0,	// GR64_and_LOW32_ADDR_ACCESS:sub_mask_0
11287      0,	// GR64_and_LOW32_ADDR_ACCESS:sub_mask_1
11288      0,	// GR64_and_LOW32_ADDR_ACCESS:sub_xmm
11289      0,	// GR64_and_LOW32_ADDR_ACCESS:sub_ymm
11290    },
11291    {	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
11292      5,	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit -> GR8_ABCD_L
11293      4,	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
11294      0,	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit_hi_phony
11295      20,	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_16bit -> GR16_ABCD
11296      0,	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_16bit_hi
11297      57,	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_32bit -> GR32_ABCD_and_GR32_BSI
11298      0,	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_mask_0
11299      0,	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_mask_1
11300      0,	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_xmm
11301      0,	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_ymm
11302    },
11303    {	// GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
11304      5,	// GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC:sub_8bit -> GR8_ABCD_L
11305      4,	// GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC:sub_8bit_hi -> GR8_ABCD_H
11306      0,	// GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC:sub_8bit_hi_phony
11307      20,	// GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC:sub_16bit -> GR16_ABCD
11308      0,	// GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC:sub_16bit_hi
11309      58,	// GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC:sub_32bit -> GR32_AD_and_GR32_DC
11310      0,	// GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC:sub_mask_0
11311      0,	// GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC:sub_mask_1
11312      0,	// GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC:sub_xmm
11313      0,	// GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC:sub_ymm
11314    },
11315    {	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
11316      1,	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit -> GR8
11317      0,	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit_hi
11318      0,	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit_hi_phony
11319      8,	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_16bit -> GR16_NOREX
11320      0,	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_16bit_hi
11321      59,	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
11322      0,	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_mask_0
11323      0,	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_mask_1
11324      0,	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_xmm
11325      0,	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_ymm
11326    },
11327    {	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
11328      1,	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit -> GR8
11329      0,	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit_hi
11330      0,	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit_hi_phony
11331      8,	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_16bit -> GR16_NOREX
11332      0,	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_16bit_hi
11333      60,	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_32bit -> GR32_BPSP_and_GR32_TC
11334      0,	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_mask_0
11335      0,	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_mask_1
11336      0,	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_xmm
11337      0,	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_ymm
11338    },
11339    {	// GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
11340      1,	// GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit -> GR8
11341      0,	// GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit_hi
11342      0,	// GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit_hi_phony
11343      8,	// GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_16bit -> GR16_NOREX
11344      0,	// GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_16bit_hi
11345      61,	// GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_32bit -> GR32_BSI_and_GR32_SIDI
11346      0,	// GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_mask_0
11347      0,	// GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_mask_1
11348      0,	// GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_xmm
11349      0,	// GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_ymm
11350    },
11351    {	// GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
11352      5,	// GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC:sub_8bit -> GR8_ABCD_L
11353      4,	// GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC:sub_8bit_hi -> GR8_ABCD_H
11354      0,	// GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC:sub_8bit_hi_phony
11355      20,	// GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC:sub_16bit -> GR16_ABCD
11356      0,	// GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC:sub_16bit_hi
11357      62,	// GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC:sub_32bit -> GR32_CB_and_GR32_DC
11358      0,	// GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC:sub_mask_0
11359      0,	// GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC:sub_mask_1
11360      0,	// GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC:sub_xmm
11361      0,	// GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC:sub_ymm
11362    },
11363    {	// GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
11364      1,	// GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit -> GR8
11365      0,	// GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit_hi
11366      0,	// GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit_hi_phony
11367      8,	// GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_16bit -> GR16_NOREX
11368      0,	// GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_16bit_hi
11369      63,	// GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_32bit -> GR32_DIBP_and_GR32_SIDI
11370      0,	// GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_mask_0
11371      0,	// GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_mask_1
11372      0,	// GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_xmm
11373      0,	// GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_ymm
11374    },
11375    {	// RST
11376      0,	// RST:sub_8bit
11377      0,	// RST:sub_8bit_hi
11378      0,	// RST:sub_8bit_hi_phony
11379      0,	// RST:sub_16bit
11380      0,	// RST:sub_16bit_hi
11381      0,	// RST:sub_32bit
11382      0,	// RST:sub_mask_0
11383      0,	// RST:sub_mask_1
11384      0,	// RST:sub_xmm
11385      0,	// RST:sub_ymm
11386    },
11387    {	// RFP80
11388      0,	// RFP80:sub_8bit
11389      0,	// RFP80:sub_8bit_hi
11390      0,	// RFP80:sub_8bit_hi_phony
11391      0,	// RFP80:sub_16bit
11392      0,	// RFP80:sub_16bit_hi
11393      0,	// RFP80:sub_32bit
11394      0,	// RFP80:sub_mask_0
11395      0,	// RFP80:sub_mask_1
11396      0,	// RFP80:sub_xmm
11397      0,	// RFP80:sub_ymm
11398    },
11399    {	// RFP80_7
11400      0,	// RFP80_7:sub_8bit
11401      0,	// RFP80_7:sub_8bit_hi
11402      0,	// RFP80_7:sub_8bit_hi_phony
11403      0,	// RFP80_7:sub_16bit
11404      0,	// RFP80_7:sub_16bit_hi
11405      0,	// RFP80_7:sub_32bit
11406      0,	// RFP80_7:sub_mask_0
11407      0,	// RFP80_7:sub_mask_1
11408      0,	// RFP80_7:sub_xmm
11409      0,	// RFP80_7:sub_ymm
11410    },
11411    {	// VR128X
11412      0,	// VR128X:sub_8bit
11413      0,	// VR128X:sub_8bit_hi
11414      0,	// VR128X:sub_8bit_hi_phony
11415      0,	// VR128X:sub_16bit
11416      0,	// VR128X:sub_16bit_hi
11417      0,	// VR128X:sub_32bit
11418      0,	// VR128X:sub_mask_0
11419      0,	// VR128X:sub_mask_1
11420      0,	// VR128X:sub_xmm
11421      0,	// VR128X:sub_ymm
11422    },
11423    {	// VR128
11424      0,	// VR128:sub_8bit
11425      0,	// VR128:sub_8bit_hi
11426      0,	// VR128:sub_8bit_hi_phony
11427      0,	// VR128:sub_16bit
11428      0,	// VR128:sub_16bit_hi
11429      0,	// VR128:sub_32bit
11430      0,	// VR128:sub_mask_0
11431      0,	// VR128:sub_mask_1
11432      0,	// VR128:sub_xmm
11433      0,	// VR128:sub_ymm
11434    },
11435    {	// VR256X
11436      0,	// VR256X:sub_8bit
11437      0,	// VR256X:sub_8bit_hi
11438      0,	// VR256X:sub_8bit_hi_phony
11439      0,	// VR256X:sub_16bit
11440      0,	// VR256X:sub_16bit_hi
11441      0,	// VR256X:sub_32bit
11442      0,	// VR256X:sub_mask_0
11443      0,	// VR256X:sub_mask_1
11444      22,	// VR256X:sub_xmm -> FR16X
11445      0,	// VR256X:sub_ymm
11446    },
11447    {	// VR256
11448      0,	// VR256:sub_8bit
11449      0,	// VR256:sub_8bit_hi
11450      0,	// VR256:sub_8bit_hi_phony
11451      0,	// VR256:sub_16bit
11452      0,	// VR256:sub_16bit_hi
11453      0,	// VR256:sub_32bit
11454      0,	// VR256:sub_mask_0
11455      0,	// VR256:sub_mask_1
11456      23,	// VR256:sub_xmm -> FR16
11457      0,	// VR256:sub_ymm
11458    },
11459    {	// VR512
11460      0,	// VR512:sub_8bit
11461      0,	// VR512:sub_8bit_hi
11462      0,	// VR512:sub_8bit_hi_phony
11463      0,	// VR512:sub_16bit
11464      0,	// VR512:sub_16bit_hi
11465      0,	// VR512:sub_32bit
11466      0,	// VR512:sub_mask_0
11467      0,	// VR512:sub_mask_1
11468      22,	// VR512:sub_xmm -> FR16X
11469      119,	// VR512:sub_ymm -> VR256X
11470    },
11471    {	// VR512_0_15
11472      0,	// VR512_0_15:sub_8bit
11473      0,	// VR512_0_15:sub_8bit_hi
11474      0,	// VR512_0_15:sub_8bit_hi_phony
11475      0,	// VR512_0_15:sub_16bit
11476      0,	// VR512_0_15:sub_16bit_hi
11477      0,	// VR512_0_15:sub_32bit
11478      0,	// VR512_0_15:sub_mask_0
11479      0,	// VR512_0_15:sub_mask_1
11480      23,	// VR512_0_15:sub_xmm -> FR16
11481      120,	// VR512_0_15:sub_ymm -> VR256
11482    },
11483    {	// TILE
11484      0,	// TILE:sub_8bit
11485      0,	// TILE:sub_8bit_hi
11486      0,	// TILE:sub_8bit_hi_phony
11487      0,	// TILE:sub_16bit
11488      0,	// TILE:sub_16bit_hi
11489      0,	// TILE:sub_32bit
11490      0,	// TILE:sub_mask_0
11491      0,	// TILE:sub_mask_1
11492      0,	// TILE:sub_xmm
11493      0,	// TILE:sub_ymm
11494    },
11495  };
11496  assert(RC && "Missing regclass");
11497  if (!Idx) return RC;
11498  --Idx;
11499  assert(Idx < 10 && "Bad subreg");
11500  unsigned TV = Table[RC->getID()][Idx];
11501  return TV ? getRegClass(TV - 1) : nullptr;
11502}
11503
11504/// Get the weight in units of pressure for this register class.
11505const RegClassWeight &X86GenRegisterInfo::
11506getRegClassWeight(const TargetRegisterClass *RC) const {
11507  static const RegClassWeight RCWeightTable[] = {
11508    {1, 20},  	// GR8
11509    {0, 0},  	// GRH8
11510    {1, 8},  	// GR8_NOREX
11511    {1, 4},  	// GR8_ABCD_H
11512    {1, 4},  	// GR8_ABCD_L
11513    {0, 0},  	// GRH16
11514    {2, 32},  	// GR16
11515    {2, 16},  	// GR16_NOREX
11516    {1, 8},  	// VK1
11517    {1, 8},  	// VK16
11518    {1, 8},  	// VK2
11519    {1, 8},  	// VK4
11520    {1, 8},  	// VK8
11521    {1, 7},  	// VK16WM
11522    {1, 7},  	// VK1WM
11523    {1, 7},  	// VK2WM
11524    {1, 7},  	// VK4WM
11525    {1, 7},  	// VK8WM
11526    {1, 6},  	// SEGMENT_REG
11527    {2, 8},  	// GR16_ABCD
11528    {0, 0},  	// FPCCR
11529    {1, 32},  	// FR16X
11530    {1, 16},  	// FR16
11531    {2, 8},  	// VK16PAIR
11532    {2, 8},  	// VK1PAIR
11533    {2, 8},  	// VK2PAIR
11534    {2, 8},  	// VK4PAIR
11535    {2, 8},  	// VK8PAIR
11536    {2, 6},  	// VK16PAIR_with_sub_mask_0_in_VK16WM
11537    {1, 32},  	// FR32X
11538    {2, 34},  	// LOW32_ADDR_ACCESS_RBP
11539    {2, 34},  	// LOW32_ADDR_ACCESS
11540    {2, 32},  	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit
11541    {1, 16},  	// DEBUG_REG
11542    {1, 16},  	// FR32
11543    {2, 32},  	// GR32
11544    {2, 30},  	// GR32_NOSP
11545    {2, 16},  	// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
11546    {2, 16},  	// GR32_NOREX
11547    {1, 8},  	// VK32
11548    {2, 14},  	// GR32_NOREX_NOSP
11549    {1, 7},  	// RFP32
11550    {1, 7},  	// VK32WM
11551    {2, 8},  	// GR32_ABCD
11552    {2, 8},  	// GR32_TC
11553    {2, 6},  	// GR32_ABCD_and_GR32_TC
11554    {2, 4},  	// GR32_AD
11555    {2, 4},  	// GR32_BPSP
11556    {2, 4},  	// GR32_BSI
11557    {2, 4},  	// GR32_CB
11558    {2, 4},  	// GR32_DC
11559    {2, 4},  	// GR32_DIBP
11560    {2, 4},  	// GR32_SIDI
11561    {2, 4},  	// LOW32_ADDR_ACCESS_RBP_with_sub_32bit
11562    {0, 0},  	// CCR
11563    {0, 0},  	// DFCCR
11564    {2, 2},  	// GR32_ABCD_and_GR32_BSI
11565    {2, 2},  	// GR32_AD_and_GR32_DC
11566    {2, 2},  	// GR32_BPSP_and_GR32_DIBP
11567    {2, 2},  	// GR32_BPSP_and_GR32_TC
11568    {2, 2},  	// GR32_BSI_and_GR32_SIDI
11569    {2, 2},  	// GR32_CB_and_GR32_DC
11570    {2, 2},  	// GR32_DIBP_and_GR32_SIDI
11571    {2, 2},  	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
11572    {2, 2},  	// LOW32_ADDR_ACCESS_with_sub_32bit
11573    {1, 7},  	// RFP64
11574    {1, 32},  	// FR64X
11575    {2, 34},  	// GR64
11576    {1, 16},  	// CONTROL_REG
11577    {1, 16},  	// FR64
11578    {2, 32},  	// GR64_with_sub_8bit
11579    {2, 30},  	// GR64_NOSP
11580    {2, 26},  	// GR64PLTSafe
11581    {2, 20},  	// GR64_TC
11582    {2, 18},  	// GR64_NOREX
11583    {2, 18},  	// GR64_TCW64
11584    {2, 18},  	// GR64_TC_with_sub_8bit
11585    {2, 16},  	// GR64_NOSP_and_GR64_TC
11586    {2, 16},  	// GR64_TCW64_with_sub_8bit
11587    {2, 16},  	// GR64_TC_and_GR64_TCW64
11588    {2, 16},  	// GR64_with_sub_16bit_in_GR16_NOREX
11589    {1, 8},  	// VK64
11590    {1, 8},  	// VR64
11591    {2, 14},  	// GR64PLTSafe_and_GR64_TC
11592    {2, 14},  	// GR64_NOREX_NOSP
11593    {2, 14},  	// GR64_NOREX_and_GR64_TC
11594    {2, 14},  	// GR64_NOSP_and_GR64_TCW64
11595    {2, 14},  	// GR64_TCW64_and_GR64_TC_with_sub_8bit
11596    {1, 7},  	// VK64WM
11597    {2, 12},  	// GR64_TC_and_GR64_NOSP_and_GR64_TCW64
11598    {2, 12},  	// GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
11599    {2, 10},  	// GR64PLTSafe_and_GR64_TCW64
11600    {2, 10},  	// GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
11601    {2, 10},  	// GR64_NOREX_and_GR64_TCW64
11602    {2, 8},  	// GR64_ABCD
11603    {2, 8},  	// GR64_with_sub_32bit_in_GR32_TC
11604    {2, 6},  	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11605    {2, 4},  	// GR64_AD
11606    {2, 4},  	// GR64_and_LOW32_ADDR_ACCESS_RBP
11607    {2, 4},  	// GR64_with_sub_32bit_in_GR32_BPSP
11608    {2, 4},  	// GR64_with_sub_32bit_in_GR32_BSI
11609    {2, 4},  	// GR64_with_sub_32bit_in_GR32_CB
11610    {2, 4},  	// GR64_with_sub_32bit_in_GR32_DC
11611    {2, 4},  	// GR64_with_sub_32bit_in_GR32_DIBP
11612    {2, 4},  	// GR64_with_sub_32bit_in_GR32_SIDI
11613    {2, 2},  	// GR64_and_LOW32_ADDR_ACCESS
11614    {2, 2},  	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
11615    {2, 2},  	// GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
11616    {2, 2},  	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
11617    {2, 2},  	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
11618    {2, 2},  	// GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
11619    {2, 2},  	// GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
11620    {2, 2},  	// GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
11621    {0, 0},  	// RST
11622    {1, 7},  	// RFP80
11623    {0, 0},  	// RFP80_7
11624    {1, 32},  	// VR128X
11625    {1, 16},  	// VR128
11626    {1, 32},  	// VR256X
11627    {1, 16},  	// VR256
11628    {1, 32},  	// VR512
11629    {1, 16},  	// VR512_0_15
11630    {1, 8},  	// TILE
11631  };
11632  return RCWeightTable[RC->getID()];
11633}
11634
11635/// Get the weight in units of pressure for this register unit.
11636unsigned X86GenRegisterInfo::
11637getRegUnitWeight(unsigned RegUnit) const {
11638  assert(RegUnit < 173 && "invalid register unit");
11639  // All register units have unit weight.
11640  return 1;
11641}
11642
11643
11644// Get the number of dimensions of register pressure.
11645unsigned X86GenRegisterInfo::getNumRegPressureSets() const {
11646  return 34;
11647}
11648
11649// Get the name of this register unit pressure set.
11650const char *X86GenRegisterInfo::
11651getRegPressureSetName(unsigned Idx) const {
11652  static const char *PressureNameTable[] = {
11653    "SEGMENT_REG",
11654    "GR32_BPSP",
11655    "LOW32_ADDR_ACCESS_with_sub_32bit",
11656    "GR32_BSI",
11657    "GR32_SIDI",
11658    "GR32_DIBP_with_GR32_SIDI",
11659    "GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit",
11660    "RFP32",
11661    "GR8_ABCD_H_with_GR32_BSI",
11662    "GR8_ABCD_L_with_GR32_BSI",
11663    "VK1",
11664    "VR64",
11665    "TILE",
11666    "GR8_NOREX",
11667    "GR32_TC",
11668    "GR32_BPSP_with_GR32_TC",
11669    "FR16",
11670    "DEBUG_REG",
11671    "CONTROL_REG",
11672    "GR64_NOREX",
11673    "GR64_TCW64",
11674    "GR32_BPSP_with_GR64_TCW64",
11675    "GR8",
11676    "GR8_with_GR32_DIBP",
11677    "GR8_with_GR32_BSI",
11678    "GR64_TC_with_GR64_TCW64",
11679    "GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit",
11680    "GR8_with_GR64_NOREX",
11681    "GR64_TC",
11682    "GR8_with_GR64_TCW64",
11683    "GR8_with_GR64_TC",
11684    "GR8_with_GR64PLTSafe",
11685    "FR16X",
11686    "GR16",
11687  };
11688  return PressureNameTable[Idx];
11689}
11690
11691// Get the register unit pressure limit for this dimension.
11692// This limit must be adjusted dynamically for reserved registers.
11693unsigned X86GenRegisterInfo::
11694getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
11695  static const uint8_t PressureLimitTable[] = {
11696    6,  	// 0: SEGMENT_REG
11697    6,  	// 1: GR32_BPSP
11698    6,  	// 2: LOW32_ADDR_ACCESS_with_sub_32bit
11699    6,  	// 3: GR32_BSI
11700    6,  	// 4: GR32_SIDI
11701    6,  	// 5: GR32_DIBP_with_GR32_SIDI
11702    6,  	// 6: GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit
11703    7,  	// 7: RFP32
11704    7,  	// 8: GR8_ABCD_H_with_GR32_BSI
11705    7,  	// 9: GR8_ABCD_L_with_GR32_BSI
11706    8,  	// 10: VK1
11707    8,  	// 11: VR64
11708    8,  	// 12: TILE
11709    10,  	// 13: GR8_NOREX
11710    12,  	// 14: GR32_TC
11711    12,  	// 15: GR32_BPSP_with_GR32_TC
11712    16,  	// 16: FR16
11713    16,  	// 17: DEBUG_REG
11714    16,  	// 18: CONTROL_REG
11715    18,  	// 19: GR64_NOREX
11716    20,  	// 20: GR64_TCW64
11717    20,  	// 21: GR32_BPSP_with_GR64_TCW64
11718    22,  	// 22: GR8
11719    22,  	// 23: GR8_with_GR32_DIBP
11720    22,  	// 24: GR8_with_GR32_BSI
11721    22,  	// 25: GR64_TC_with_GR64_TCW64
11722    23,  	// 26: GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit
11723    26,  	// 27: GR8_with_GR64_NOREX
11724    26,  	// 28: GR64_TC
11725    27,  	// 29: GR8_with_GR64_TCW64
11726    28,  	// 30: GR8_with_GR64_TC
11727    29,  	// 31: GR8_with_GR64PLTSafe
11728    32,  	// 32: FR16X
11729    34,  	// 33: GR16
11730  };
11731  return PressureLimitTable[Idx];
11732}
11733
11734/// Table of pressure sets per register class or unit.
11735static const int RCSetsTable[] = {
11736  /* 0 */ 0, -1,
11737  /* 2 */ 7, -1,
11738  /* 4 */ 10, -1,
11739  /* 6 */ 11, -1,
11740  /* 8 */ 12, -1,
11741  /* 10 */ 17, -1,
11742  /* 12 */ 18, -1,
11743  /* 14 */ 16, 32, -1,
11744  /* 17 */ 19, 27, 28, 33, -1,
11745  /* 22 */ 1, 2, 15, 19, 21, 22, 27, 28, 33, -1,
11746  /* 32 */ 2, 6, 15, 19, 21, 26, 27, 28, 33, -1,
11747  /* 42 */ 20, 21, 25, 28, 29, 33, -1,
11748  /* 49 */ 25, 28, 30, 33, -1,
11749  /* 54 */ 19, 25, 27, 28, 30, 33, -1,
11750  /* 61 */ 20, 21, 25, 28, 29, 30, 33, -1,
11751  /* 69 */ 14, 15, 19, 20, 21, 25, 27, 28, 29, 30, 33, -1,
11752  /* 81 */ 1, 2, 14, 15, 19, 20, 21, 22, 25, 27, 28, 29, 30, 33, -1,
11753  /* 96 */ 2, 6, 14, 15, 19, 20, 21, 25, 26, 27, 28, 29, 30, 33, -1,
11754  /* 111 */ 19, 27, 28, 31, 33, -1,
11755  /* 117 */ 1, 5, 6, 19, 23, 27, 28, 31, 33, -1,
11756  /* 127 */ 1, 2, 5, 6, 15, 19, 21, 22, 23, 26, 27, 28, 31, 33, -1,
11757  /* 142 */ 25, 28, 30, 31, 33, -1,
11758  /* 148 */ 3, 4, 8, 9, 13, 19, 24, 27, 28, 30, 31, 33, -1,
11759  /* 161 */ 4, 5, 19, 24, 25, 27, 28, 30, 31, 33, -1,
11760  /* 172 */ 3, 4, 5, 8, 9, 13, 19, 24, 25, 27, 28, 30, 31, 33, -1,
11761  /* 187 */ 1, 4, 5, 6, 19, 23, 24, 25, 27, 28, 30, 31, 33, -1,
11762  /* 201 */ 22, 23, 24, 26, 27, 29, 30, 31, 33, -1,
11763  /* 211 */ 20, 21, 25, 28, 29, 30, 31, 33, -1,
11764  /* 220 */ 3, 13, 14, 19, 20, 22, 23, 24, 26, 27, 28, 29, 30, 31, 33, -1,
11765  /* 236 */ 8, 13, 14, 19, 20, 22, 23, 24, 26, 27, 28, 29, 30, 31, 33, -1,
11766  /* 252 */ 3, 4, 8, 9, 13, 14, 19, 20, 22, 23, 24, 26, 27, 28, 29, 30, 31, 33, -1,
11767  /* 271 */ 1, 2, 5, 6, 15, 19, 21, 22, 23, 24, 26, 27, 28, 29, 30, 31, 33, -1,
11768  /* 289 */ 1, 4, 5, 6, 19, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 33, -1,
11769  /* 306 */ 3, 4, 5, 8, 9, 13, 19, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 33, -1,
11770  /* 325 */ 1, 2, 14, 15, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 33, -1,
11771  /* 344 */ 3, 13, 14, 15, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 33, -1,
11772  /* 363 */ 3, 8, 13, 14, 15, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 33, -1,
11773  /* 383 */ 3, 9, 13, 14, 15, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 33, -1,
11774};
11775
11776/// Get the dimensions of register pressure impacted by this register class.
11777/// Returns a -1 terminated array of pressure set IDs
11778const int *X86GenRegisterInfo::
11779getRegClassPressureSets(const TargetRegisterClass *RC) const {
11780  static const uint16_t RCSetStartTable[] = {
11781    201,1,221,236,255,1,20,17,4,4,4,4,4,4,4,4,4,4,0,221,1,15,14,4,4,4,4,4,4,15,20,20,20,10,14,20,20,17,17,4,111,2,4,221,83,345,345,22,148,220,345,117,161,32,1,1,252,345,127,81,172,344,187,127,96,2,15,20,12,14,20,20,114,49,17,42,49,49,42,61,17,4,6,142,111,54,42,61,4,61,54,211,163,69,221,83,345,345,32,22,148,220,345,117,161,96,252,345,127,81,172,344,187,1,2,1,15,14,15,14,15,14,8,};
11782  return &RCSetsTable[RCSetStartTable[RC->getID()]];
11783}
11784
11785/// Get the dimensions of register pressure impacted by this register unit.
11786/// Returns a -1 terminated array of pressure set IDs
11787const int *X86GenRegisterInfo::
11788getRegUnitPressureSets(unsigned RegUnit) const {
11789  assert(RegUnit < 173 && "invalid register unit");
11790  static const uint16_t RUSetStartTable[] = {
11791    364,384,252,252,271,1,363,383,0,1,364,289,1,384,0,1,1,1,1,1,1,1,96,1,1,0,306,1,1,325,1,1,1,1,0,1,0,1,1,1,1,0,1,1,1,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,2,2,2,2,2,2,2,1,4,4,4,4,4,4,4,4,6,6,6,6,6,6,6,6,330,1,1,330,1,1,330,1,1,330,1,1,201,1,1,201,1,1,201,1,1,201,1,1,1,1,1,1,1,1,1,1,8,8,8,8,8,8,8,8,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,};
11792  return &RCSetsTable[RUSetStartTable[RegUnit]];
11793}
11794
11795extern const MCRegisterDesc X86RegDesc[];
11796extern const MCPhysReg X86RegDiffLists[];
11797extern const LaneBitmask X86LaneMaskLists[];
11798extern const char X86RegStrings[];
11799extern const char X86RegClassStrings[];
11800extern const MCPhysReg X86RegUnitRoots[][2];
11801extern const uint16_t X86SubRegIdxLists[];
11802extern const MCRegisterInfo::SubRegCoveredBits X86SubRegIdxRanges[];
11803extern const uint16_t X86RegEncodingTable[];
11804// X86 Dwarf<->LLVM register mappings.
11805extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[];
11806extern const unsigned X86DwarfFlavour0Dwarf2LSize;
11807
11808extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[];
11809extern const unsigned X86DwarfFlavour1Dwarf2LSize;
11810
11811extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[];
11812extern const unsigned X86DwarfFlavour2Dwarf2LSize;
11813
11814extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[];
11815extern const unsigned X86EHFlavour0Dwarf2LSize;
11816
11817extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[];
11818extern const unsigned X86EHFlavour1Dwarf2LSize;
11819
11820extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[];
11821extern const unsigned X86EHFlavour2Dwarf2LSize;
11822
11823extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[];
11824extern const unsigned X86DwarfFlavour0L2DwarfSize;
11825
11826extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[];
11827extern const unsigned X86DwarfFlavour1L2DwarfSize;
11828
11829extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[];
11830extern const unsigned X86DwarfFlavour2L2DwarfSize;
11831
11832extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[];
11833extern const unsigned X86EHFlavour0L2DwarfSize;
11834
11835extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[];
11836extern const unsigned X86EHFlavour1L2DwarfSize;
11837
11838extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[];
11839extern const unsigned X86EHFlavour2L2DwarfSize;
11840
11841X86GenRegisterInfo::
11842X86GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
11843      unsigned PC, unsigned HwMode)
11844  : TargetRegisterInfo(&X86RegInfoDesc, RegisterClasses, RegisterClasses+123,
11845             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
11846             LaneBitmask(0xFFFFFFFFFFFFFFB0), RegClassInfos, HwMode) {
11847  InitMCRegisterInfo(X86RegDesc, 292, RA, PC,
11848                     X86MCRegisterClasses, 123,
11849                     X86RegUnitRoots,
11850                     173,
11851                     X86RegDiffLists,
11852                     X86LaneMaskLists,
11853                     X86RegStrings,
11854                     X86RegClassStrings,
11855                     X86SubRegIdxLists,
11856                     11,
11857                     X86SubRegIdxRanges,
11858                     X86RegEncodingTable);
11859
11860  switch (DwarfFlavour) {
11861  default:
11862    llvm_unreachable("Unknown DWARF flavour");
11863  case 0:
11864    mapDwarfRegsToLLVMRegs(X86DwarfFlavour0Dwarf2L, X86DwarfFlavour0Dwarf2LSize, false);
11865    break;
11866  case 1:
11867    mapDwarfRegsToLLVMRegs(X86DwarfFlavour1Dwarf2L, X86DwarfFlavour1Dwarf2LSize, false);
11868    break;
11869  case 2:
11870    mapDwarfRegsToLLVMRegs(X86DwarfFlavour2Dwarf2L, X86DwarfFlavour2Dwarf2LSize, false);
11871    break;
11872  }
11873  switch (EHFlavour) {
11874  default:
11875    llvm_unreachable("Unknown DWARF flavour");
11876  case 0:
11877    mapDwarfRegsToLLVMRegs(X86EHFlavour0Dwarf2L, X86EHFlavour0Dwarf2LSize, true);
11878    break;
11879  case 1:
11880    mapDwarfRegsToLLVMRegs(X86EHFlavour1Dwarf2L, X86EHFlavour1Dwarf2LSize, true);
11881    break;
11882  case 2:
11883    mapDwarfRegsToLLVMRegs(X86EHFlavour2Dwarf2L, X86EHFlavour2Dwarf2LSize, true);
11884    break;
11885  }
11886  switch (DwarfFlavour) {
11887  default:
11888    llvm_unreachable("Unknown DWARF flavour");
11889  case 0:
11890    mapLLVMRegsToDwarfRegs(X86DwarfFlavour0L2Dwarf, X86DwarfFlavour0L2DwarfSize, false);
11891    break;
11892  case 1:
11893    mapLLVMRegsToDwarfRegs(X86DwarfFlavour1L2Dwarf, X86DwarfFlavour1L2DwarfSize, false);
11894    break;
11895  case 2:
11896    mapLLVMRegsToDwarfRegs(X86DwarfFlavour2L2Dwarf, X86DwarfFlavour2L2DwarfSize, false);
11897    break;
11898  }
11899  switch (EHFlavour) {
11900  default:
11901    llvm_unreachable("Unknown DWARF flavour");
11902  case 0:
11903    mapLLVMRegsToDwarfRegs(X86EHFlavour0L2Dwarf, X86EHFlavour0L2DwarfSize, true);
11904    break;
11905  case 1:
11906    mapLLVMRegsToDwarfRegs(X86EHFlavour1L2Dwarf, X86EHFlavour1L2DwarfSize, true);
11907    break;
11908  case 2:
11909    mapLLVMRegsToDwarfRegs(X86EHFlavour2L2Dwarf, X86EHFlavour2L2DwarfSize, true);
11910    break;
11911  }
11912}
11913
11914static const MCPhysReg CSR_32_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
11915static const uint32_t CSR_32_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
11916static const MCPhysReg CSR_32EHRet_SaveList[] = { X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
11917static const uint32_t CSR_32EHRet_RegMask[] = { 0x0def83fe, 0xc000b701, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
11918static const MCPhysReg CSR_32_AllRegs_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, 0 };
11919static const uint32_t CSR_32_AllRegs_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
11920static const MCPhysReg CSR_32_AllRegs_AVX_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, 0 };
11921static const uint32_t CSR_32_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0xff000000, 0xff000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
11922static const MCPhysReg CSR_32_AllRegs_AVX512_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
11923static const uint32_t CSR_32_AllRegs_AVX512_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00ff0000, 0xff000000, 0xff000000, 0xff000000, 0x00000000, 0x00000000, 0x0000000f, };
11924static const MCPhysReg CSR_32_AllRegs_SSE_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
11925static const uint32_t CSR_32_AllRegs_SSE_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0xff000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
11926static const MCPhysReg CSR_32_RegCall_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
11927static const uint32_t CSR_32_RegCall_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0xf0000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
11928static const MCPhysReg CSR_32_RegCall_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
11929static const uint32_t CSR_32_RegCall_NoSSE_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
11930static const MCPhysReg CSR_64_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
11931static const uint32_t CSR_64_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x000000f0, 0x00000000, 0x00000000, 0xf0000000, 0xf0f0f0f0, 0x00000000, };
11932static const MCPhysReg CSR_64EHRet_SaveList[] = { X86::RAX, X86::RDX, X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
11933static const uint32_t CSR_64EHRet_RegMask[] = { 0x09e883fe, 0x01382700, 0x00000000, 0x00000000, 0x000000f0, 0x00000000, 0x00000000, 0xf0000000, 0xf0f0f0f0, 0x00000000, };
11934static const MCPhysReg CSR_64_AllRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::RAX, 0 };
11935static const uint32_t CSR_64_AllRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x00000000, 0xff0000ff, 0x000000ff, 0x00000000, 0xff000000, 0xffffffff, 0x00000000, };
11936static const MCPhysReg CSR_64_AllRegs_AVX_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
11937static const uint32_t CSR_64_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x00000000, 0xff0000ff, 0xff0000ff, 0x000000ff, 0xff000000, 0xffffffff, 0x00000000, };
11938static const MCPhysReg CSR_64_AllRegs_AVX512_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
11939static const uint32_t CSR_64_AllRegs_AVX512_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x00ff0000, 0xff0000ff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0000000f, };
11940static const MCPhysReg CSR_64_AllRegs_NoSSE_SaveList[] = { X86::RAX, X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
11941static const uint32_t CSR_64_AllRegs_NoSSE_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x00000000, 0x000000ff, 0x00000000, 0x00000000, 0xff000000, 0xffffffff, 0x00000000, };
11942static const MCPhysReg CSR_64_CXX_TLS_Darwin_PE_SaveList[] = { X86::RBP, 0 };
11943static const uint32_t CSR_64_CXX_TLS_Darwin_PE_RegMask[] = { 0x008001c0, 0x00100200, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
11944static const MCPhysReg CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 };
11945static const uint32_t CSR_64_CXX_TLS_Darwin_ViaCopy_RegMask[] = { 0x0b28ae30, 0xd160ac01, 0x00000001, 0x00000000, 0x000000ff, 0x00000000, 0x00000000, 0xff000000, 0xffffffff, 0x00000000, };
11946static const MCPhysReg CSR_64_HHVM_SaveList[] = { X86::R12, 0 };
11947static const uint32_t CSR_64_HHVM_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x10000000, 0x10101010, 0x00000000, };
11948static const MCPhysReg CSR_64_Intel_OCL_BI_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
11949static const uint32_t CSR_64_Intel_OCL_BI_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x000000f0, 0x000000ff, 0x00000000, 0xf0000000, 0xf0f0f0f0, 0x00000000, };
11950static const MCPhysReg CSR_64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
11951static const uint32_t CSR_64_Intel_OCL_BI_AVX_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x000000f0, 0x000000ff, 0x000000ff, 0xf0000000, 0xf0f0f0f0, 0x00000000, };
11952static const MCPhysReg CSR_64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RSI, X86::R14, X86::R15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
11953static const uint32_t CSR_64_Intel_OCL_BI_AVX512_RegMask[] = { 0x01000230, 0xd0208401, 0x00000001, 0x00f00000, 0x000000c0, 0x00ffff00, 0x00ffff00, 0xc0ffff00, 0xc0c0c0c0, 0x0000000c, };
11954static const MCPhysReg CSR_64_MostRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
11955static const uint32_t CSR_64_MostRegs_RegMask[] = { 0x0fafaff0, 0xd1f0be01, 0x00000001, 0x00000000, 0xff0000ff, 0x000000ff, 0x00000000, 0xff000000, 0xffffffff, 0x00000000, };
11956static const MCPhysReg CSR_64_RT_AllRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
11957static const uint32_t CSR_64_RT_AllRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x00000000, 0xff0000f7, 0x000000ff, 0x00000000, 0xf7000000, 0xf7f7f7f7, 0x00000000, };
11958static const MCPhysReg CSR_64_RT_AllRegs_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
11959static const uint32_t CSR_64_RT_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x00000000, 0xff0000f7, 0xff0000ff, 0x000000ff, 0xf7000000, 0xf7f7f7f7, 0x00000000, };
11960static const MCPhysReg CSR_64_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, 0 };
11961static const uint32_t CSR_64_RT_MostRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x00000000, 0x000000f7, 0x00000000, 0x00000000, 0xf7000000, 0xf7f7f7f7, 0x00000000, };
11962static const MCPhysReg CSR_64_SwiftError_SaveList[] = { X86::RBX, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
11963static const uint32_t CSR_64_SwiftError_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x000000e0, 0x00000000, 0x00000000, 0xe0000000, 0xe0e0e0e0, 0x00000000, };
11964static const MCPhysReg CSR_64_SwiftTail_SaveList[] = { X86::RBX, X86::R12, X86::R15, X86::RBP, 0 };
11965static const uint32_t CSR_64_SwiftTail_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x00000090, 0x00000000, 0x00000000, 0x90000000, 0x90909090, 0x00000000, };
11966static const MCPhysReg CSR_64_TLS_Darwin_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 };
11967static const uint32_t CSR_64_TLS_Darwin_RegMask[] = { 0x0ba8aff0, 0xd170ae01, 0x00000001, 0x00000000, 0x000000ff, 0x00000000, 0x00000000, 0xff000000, 0xffffffff, 0x00000000, };
11968static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
11969static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
11970static const MCPhysReg CSR_SysV64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
11971static const uint32_t CSR_SysV64_RegCall_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x000000f0, 0x000000ff, 0x00000000, 0xf0000000, 0xf0f0f0f0, 0x00000000, };
11972static const MCPhysReg CSR_SysV64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
11973static const uint32_t CSR_SysV64_RegCall_NoSSE_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x000000f0, 0x00000000, 0x00000000, 0xf0000000, 0xf0f0f0f0, 0x00000000, };
11974static const MCPhysReg CSR_Win32_CFGuard_Check_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::ECX, 0 };
11975static const uint32_t CSR_Win32_CFGuard_Check_RegMask[] = { 0x07872ff0, 0xc0009e01, 0x00000001, 0x00000000, 0xf0000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
11976static const MCPhysReg CSR_Win32_CFGuard_Check_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ECX, 0 };
11977static const uint32_t CSR_Win32_CFGuard_Check_NoSSE_RegMask[] = { 0x07872ff0, 0xc0009e01, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
11978static const MCPhysReg CSR_Win64_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
11979static const uint32_t CSR_Win64_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x00000000, 0xc00000f0, 0x000000ff, 0x00000000, 0xf0000000, 0xf0f0f0f0, 0x00000000, };
11980static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
11981static const uint32_t CSR_Win64_Intel_OCL_BI_AVX_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x00000000, 0xc00000f0, 0xc00000ff, 0x000000ff, 0xf0000000, 0xf0f0f0f0, 0x00000000, };
11982static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
11983static const uint32_t CSR_Win64_Intel_OCL_BI_AVX512_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x00f00000, 0xc00000f0, 0xc0003fff, 0xc0003fff, 0xf0003fff, 0xf0f0f0f0, 0x0000000c, };
11984static const MCPhysReg CSR_Win64_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
11985static const uint32_t CSR_Win64_NoSSE_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x00000000, 0x000000f0, 0x00000000, 0x00000000, 0xf0000000, 0xf0f0f0f0, 0x00000000, };
11986static const MCPhysReg CSR_Win64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
11987static const uint32_t CSR_Win64_RegCall_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x000000fc, 0x000000ff, 0x00000000, 0xfc000000, 0xfcfcfcfc, 0x00000000, };
11988static const MCPhysReg CSR_Win64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
11989static const uint32_t CSR_Win64_RegCall_NoSSE_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x000000fc, 0x00000000, 0x00000000, 0xfc000000, 0xfcfcfcfc, 0x00000000, };
11990static const MCPhysReg CSR_Win64_SwiftError_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
11991static const uint32_t CSR_Win64_SwiftError_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x00000000, 0xc00000e0, 0x000000ff, 0x00000000, 0xe0000000, 0xe0e0e0e0, 0x00000000, };
11992static const MCPhysReg CSR_Win64_SwiftTail_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
11993static const uint32_t CSR_Win64_SwiftTail_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x00000000, 0xc0000090, 0x000000ff, 0x00000000, 0x90000000, 0x90909090, 0x00000000, };
11994
11995
11996ArrayRef<const uint32_t *> X86GenRegisterInfo::getRegMasks() const {
11997  static const uint32_t *const Masks[] = {
11998    CSR_32_RegMask,
11999    CSR_32EHRet_RegMask,
12000    CSR_32_AllRegs_RegMask,
12001    CSR_32_AllRegs_AVX_RegMask,
12002    CSR_32_AllRegs_AVX512_RegMask,
12003    CSR_32_AllRegs_SSE_RegMask,
12004    CSR_32_RegCall_RegMask,
12005    CSR_32_RegCall_NoSSE_RegMask,
12006    CSR_64_RegMask,
12007    CSR_64EHRet_RegMask,
12008    CSR_64_AllRegs_RegMask,
12009    CSR_64_AllRegs_AVX_RegMask,
12010    CSR_64_AllRegs_AVX512_RegMask,
12011    CSR_64_AllRegs_NoSSE_RegMask,
12012    CSR_64_CXX_TLS_Darwin_PE_RegMask,
12013    CSR_64_CXX_TLS_Darwin_ViaCopy_RegMask,
12014    CSR_64_HHVM_RegMask,
12015    CSR_64_Intel_OCL_BI_RegMask,
12016    CSR_64_Intel_OCL_BI_AVX_RegMask,
12017    CSR_64_Intel_OCL_BI_AVX512_RegMask,
12018    CSR_64_MostRegs_RegMask,
12019    CSR_64_RT_AllRegs_RegMask,
12020    CSR_64_RT_AllRegs_AVX_RegMask,
12021    CSR_64_RT_MostRegs_RegMask,
12022    CSR_64_SwiftError_RegMask,
12023    CSR_64_SwiftTail_RegMask,
12024    CSR_64_TLS_Darwin_RegMask,
12025    CSR_NoRegs_RegMask,
12026    CSR_SysV64_RegCall_RegMask,
12027    CSR_SysV64_RegCall_NoSSE_RegMask,
12028    CSR_Win32_CFGuard_Check_RegMask,
12029    CSR_Win32_CFGuard_Check_NoSSE_RegMask,
12030    CSR_Win64_RegMask,
12031    CSR_Win64_Intel_OCL_BI_AVX_RegMask,
12032    CSR_Win64_Intel_OCL_BI_AVX512_RegMask,
12033    CSR_Win64_NoSSE_RegMask,
12034    CSR_Win64_RegCall_RegMask,
12035    CSR_Win64_RegCall_NoSSE_RegMask,
12036    CSR_Win64_SwiftError_RegMask,
12037    CSR_Win64_SwiftTail_RegMask,
12038  };
12039  return ArrayRef(Masks);
12040}
12041
12042bool X86GenRegisterInfo::
12043isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
12044  return
12045      X86::GR64RegClass.contains(PhysReg) ||
12046      X86::GR32RegClass.contains(PhysReg) ||
12047      X86::GR16RegClass.contains(PhysReg) ||
12048      X86::GR8RegClass.contains(PhysReg) ||
12049      false;
12050}
12051
12052bool X86GenRegisterInfo::
12053isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
12054  return
12055      X86::DEBUG_REGRegClass.contains(PhysReg) ||
12056      X86::CONTROL_REGRegClass.contains(PhysReg) ||
12057      X86::CCRRegClass.contains(PhysReg) ||
12058      X86::FPCCRRegClass.contains(PhysReg) ||
12059      X86::DFCCRRegClass.contains(PhysReg) ||
12060      X86::TILERegClass.contains(PhysReg) ||
12061      X86::VK1PAIRRegClass.contains(PhysReg) ||
12062      X86::VK2PAIRRegClass.contains(PhysReg) ||
12063      X86::VK4PAIRRegClass.contains(PhysReg) ||
12064      X86::VK8PAIRRegClass.contains(PhysReg) ||
12065      X86::VK16PAIRRegClass.contains(PhysReg) ||
12066      false;
12067}
12068
12069bool X86GenRegisterInfo::
12070isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
12071  return
12072      false;
12073}
12074
12075bool X86GenRegisterInfo::
12076isConstantPhysReg(MCRegister PhysReg) const {
12077  return
12078      false;
12079}
12080
12081ArrayRef<const char *> X86GenRegisterInfo::getRegMaskNames() const {
12082  static const char *Names[] = {
12083    "CSR_32",
12084    "CSR_32EHRet",
12085    "CSR_32_AllRegs",
12086    "CSR_32_AllRegs_AVX",
12087    "CSR_32_AllRegs_AVX512",
12088    "CSR_32_AllRegs_SSE",
12089    "CSR_32_RegCall",
12090    "CSR_32_RegCall_NoSSE",
12091    "CSR_64",
12092    "CSR_64EHRet",
12093    "CSR_64_AllRegs",
12094    "CSR_64_AllRegs_AVX",
12095    "CSR_64_AllRegs_AVX512",
12096    "CSR_64_AllRegs_NoSSE",
12097    "CSR_64_CXX_TLS_Darwin_PE",
12098    "CSR_64_CXX_TLS_Darwin_ViaCopy",
12099    "CSR_64_HHVM",
12100    "CSR_64_Intel_OCL_BI",
12101    "CSR_64_Intel_OCL_BI_AVX",
12102    "CSR_64_Intel_OCL_BI_AVX512",
12103    "CSR_64_MostRegs",
12104    "CSR_64_RT_AllRegs",
12105    "CSR_64_RT_AllRegs_AVX",
12106    "CSR_64_RT_MostRegs",
12107    "CSR_64_SwiftError",
12108    "CSR_64_SwiftTail",
12109    "CSR_64_TLS_Darwin",
12110    "CSR_NoRegs",
12111    "CSR_SysV64_RegCall",
12112    "CSR_SysV64_RegCall_NoSSE",
12113    "CSR_Win32_CFGuard_Check",
12114    "CSR_Win32_CFGuard_Check_NoSSE",
12115    "CSR_Win64",
12116    "CSR_Win64_Intel_OCL_BI_AVX",
12117    "CSR_Win64_Intel_OCL_BI_AVX512",
12118    "CSR_Win64_NoSSE",
12119    "CSR_Win64_RegCall",
12120    "CSR_Win64_RegCall_NoSSE",
12121    "CSR_Win64_SwiftError",
12122    "CSR_Win64_SwiftTail",
12123  };
12124  return ArrayRef(Names);
12125}
12126
12127const X86FrameLowering *
12128X86GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
12129  return static_cast<const X86FrameLowering *>(
12130      MF.getSubtarget().getFrameLowering());
12131}
12132
12133} // end namespace llvm
12134
12135#endif // GET_REGINFO_TARGET_DESC
12136
12137