1 /*
2 * Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
3 * Copyright (c) 2024, Altera Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9 #include <errno.h>
10 #include <stdbool.h>
11 #include <stddef.h>
12 #include <string.h>
13
14 #include <arch_helpers.h>
15 #include <common/debug.h>
16 #include <drivers/cadence/cdns_sdmmc.h>
17 #include <drivers/delay_timer.h>
18 #include <drivers/mmc.h>
19 #include <lib/mmio.h>
20 #include <lib/utils.h>
21
22 void cdns_init(void);
23 int cdns_send_cmd(struct mmc_cmd *cmd);
24 int cdns_set_ios(unsigned int clk, unsigned int width);
25 int cdns_prepare(int lba, uintptr_t buf, size_t size);
26 int cdns_read(int lba, uintptr_t buf, size_t size);
27 int cdns_write(int lba, uintptr_t buf, size_t size);
28
29 const struct mmc_ops cdns_sdmmc_ops = {
30 .init = cdns_init,
31 .send_cmd = cdns_send_cmd,
32 .set_ios = cdns_set_ios,
33 .prepare = cdns_prepare,
34 .read = cdns_read,
35 .write = cdns_write,
36 };
37 void sd_host_adma_prepare(struct cdns_idmac_desc *desc_ptr, uintptr_t buf,
38 size_t size);
39 struct cdns_sdmmc_params cdns_params;
40 struct cdns_sdmmc_combo_phy sdmmc_combo_phy_reg;
41 struct cdns_sdmmc_sdhc sdmmc_sdhc_reg;
42 #ifdef CONFIG_DMA_ADDR_T_64BIT
43 struct cdns_idmac_desc cdns_desc[CONFIG_CDNS_DESC_COUNT];
44 #else
45 struct cdns_idmac_desc cdns_desc[CONFIG_CDNS_DESC_COUNT] __aligned(32);
46 #endif
47
48 bool data_cmd;
49
cdns_wait_ics(uint16_t timeout,uint32_t cdn_srs_res)50 int cdns_wait_ics(uint16_t timeout, uint32_t cdn_srs_res)
51 {
52 /* Clock for sdmclk and sdclk */
53 uint32_t count = 0;
54 uint32_t data = 0;
55
56 /* Wait status command response ready */
57 do {
58 data = mmio_read_32(cdn_srs_res);
59 count++;
60 if (count >= timeout) {
61 return -ETIMEDOUT;
62 }
63 } while ((data & (1 << SDMMC_CDN_ICS)) == 0);
64
65 return 0;
66 }
67
cdns_set_sdmmc_var(struct cdns_sdmmc_combo_phy * combo_phy_reg,struct cdns_sdmmc_sdhc * sdhc_reg)68 void cdns_set_sdmmc_var(struct cdns_sdmmc_combo_phy *combo_phy_reg,
69 struct cdns_sdmmc_sdhc *sdhc_reg)
70 {
71 /* Values are taken by the reference of cadence IP documents */
72 combo_phy_reg->cp_clk_wr_delay = 0;
73 combo_phy_reg->cp_clk_wrdqs_delay = 0;
74 combo_phy_reg->cp_data_select_oe_end = 1;
75 combo_phy_reg->cp_dll_bypass_mode = 1;
76 combo_phy_reg->cp_dll_locked_mode = 0;
77 combo_phy_reg->cp_dll_start_point = 254;
78 combo_phy_reg->cp_gate_cfg_always_on = 1;
79 combo_phy_reg->cp_io_mask_always_on = 0;
80 combo_phy_reg->cp_io_mask_end = 5;
81 combo_phy_reg->cp_io_mask_start = 0;
82 combo_phy_reg->cp_rd_del_sel = 52;
83 combo_phy_reg->cp_read_dqs_cmd_delay = 0;
84 combo_phy_reg->cp_read_dqs_delay = 0;
85 combo_phy_reg->cp_sw_half_cycle_shift = 0;
86 combo_phy_reg->cp_sync_method = 1;
87 combo_phy_reg->cp_underrun_suppress = 1;
88 combo_phy_reg->cp_use_ext_lpbk_dqs = 1;
89 combo_phy_reg->cp_use_lpbk_dqs = 1;
90 combo_phy_reg->cp_use_phony_dqs = 1;
91 combo_phy_reg->cp_use_phony_dqs_cmd = 1;
92
93 sdhc_reg->sdhc_extended_rd_mode = 1;
94 sdhc_reg->sdhc_extended_wr_mode = 1;
95 sdhc_reg->sdhc_hcsdclkadj = 3;
96 sdhc_reg->sdhc_idelay_val = 0;
97 sdhc_reg->sdhc_rdcmd_en = 1;
98 sdhc_reg->sdhc_rddata_en = 1;
99 sdhc_reg->sdhc_rw_compensate = 10;
100 sdhc_reg->sdhc_sdcfsh = 0;
101 sdhc_reg->sdhc_sdcfsl = 0;
102 sdhc_reg->sdhc_wrcmd0_dly = 1;
103 sdhc_reg->sdhc_wrcmd0_sdclk_dly = 0;
104 sdhc_reg->sdhc_wrcmd1_dly = 0;
105 sdhc_reg->sdhc_wrcmd1_sdclk_dly = 0;
106 sdhc_reg->sdhc_wrdata0_dly = 0;
107 sdhc_reg->sdhc_wrdata0_sdclk_dly = 0;
108 sdhc_reg->sdhc_wrdata1_dly = 0;
109 sdhc_reg->sdhc_wrdata1_sdclk_dly = 0;
110 }
111
cdns_program_phy_reg(struct cdns_sdmmc_combo_phy * combo_phy_reg,struct cdns_sdmmc_sdhc * sdhc_reg)112 int cdns_program_phy_reg(struct cdns_sdmmc_combo_phy *combo_phy_reg,
113 struct cdns_sdmmc_sdhc *sdhc_reg)
114 {
115 uint32_t value = 0;
116 int ret = 0;
117 uint32_t timeout = 0;
118
119 /* HRS00 - Software Reset */
120 mmio_write_32((cdns_params.reg_base + SDHC_CDNS_HRS00), SDHC_CDNS_HRS00_SWR);
121
122 /* Waiting for SDHC_CDNS_HRS00_SWR reset */
123 timeout = TIMEOUT;
124 do {
125 udelay(250);
126 if (--timeout <= 0) {
127 NOTICE(" SDHC Software Reset failed!!!\n");
128 panic();
129 }
130 } while (((mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS00) &
131 SDHC_CDNS_HRS00_SWR) == 1));
132
133 /* Step 1, switch on DLL_RESET */
134 value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09);
135 value &= ~SDHC_PHY_SW_RESET;
136 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09, value);
137
138 /* program PHY_DQS_TIMING_REG */
139 value = (CP_USE_EXT_LPBK_DQS(combo_phy_reg->cp_use_ext_lpbk_dqs)) |
140 (CP_USE_LPBK_DQS(combo_phy_reg->cp_use_lpbk_dqs)) |
141 (CP_USE_PHONY_DQS(combo_phy_reg->cp_use_phony_dqs)) |
142 (CP_USE_PHONY_DQS_CMD(combo_phy_reg->cp_use_phony_dqs_cmd));
143 ret = cdns_sdmmc_write_phy_reg(cdns_params.reg_base + SDHC_CDNS_HRS04,
144 COMBO_PHY_REG + PHY_DQS_TIMING_REG,
145 cdns_params.reg_base + SDHC_CDNS_HRS05, value);
146 if (ret != 0U) {
147 return ret;
148 }
149
150 /* program PHY_GATE_LPBK_CTRL_REG */
151 value = (CP_SYNC_METHOD(combo_phy_reg->cp_sync_method)) |
152 (CP_SW_HALF_CYCLE_SHIFT(combo_phy_reg->cp_sw_half_cycle_shift)) |
153 (CP_RD_DEL_SEL(combo_phy_reg->cp_rd_del_sel)) |
154 (CP_UNDERRUN_SUPPRESS(combo_phy_reg->cp_underrun_suppress)) |
155 (CP_GATE_CFG_ALWAYS_ON(combo_phy_reg->cp_gate_cfg_always_on));
156 ret = cdns_sdmmc_write_phy_reg(cdns_params.reg_base + SDHC_CDNS_HRS04,
157 COMBO_PHY_REG + PHY_GATE_LPBK_CTRL_REG,
158 cdns_params.reg_base + SDHC_CDNS_HRS05, value);
159 if (ret != 0U) {
160 return -ret;
161 }
162
163 /* program PHY_DLL_MASTER_CTRL_REG */
164 value = (CP_DLL_BYPASS_MODE(combo_phy_reg->cp_dll_bypass_mode)) | (2 << 20) |
165 (CP_DLL_START_POINT(combo_phy_reg->cp_dll_start_point));
166 ret = cdns_sdmmc_write_phy_reg(cdns_params.reg_base + SDHC_CDNS_HRS04,
167 COMBO_PHY_REG + PHY_DLL_MASTER_CTRL_REG,
168 cdns_params.reg_base + SDHC_CDNS_HRS05, value);
169 if (ret != 0U) {
170 return ret;
171 }
172
173 /* program PHY_DLL_SLAVE_CTRL_REG */
174 value = (CP_READ_DQS_CMD_DELAY(combo_phy_reg->cp_read_dqs_cmd_delay)) |
175 (CP_CLK_WRDQS_DELAY(combo_phy_reg->cp_clk_wrdqs_delay)) |
176 (CP_CLK_WR_DELAY(combo_phy_reg->cp_clk_wr_delay)) |
177 (CP_READ_DQS_DELAY(combo_phy_reg->cp_read_dqs_delay));
178 ret = cdns_sdmmc_write_phy_reg(cdns_params.reg_base + SDHC_CDNS_HRS04,
179 COMBO_PHY_REG + PHY_DLL_SLAVE_CTRL_REG,
180 cdns_params.reg_base + SDHC_CDNS_HRS05, value);
181 if (ret != 0U) {
182 return ret;
183 }
184
185 /* program PHY_CTRL_REG */
186 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS04, COMBO_PHY_REG + PHY_CTRL_REG);
187 value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS05);
188
189 /* phony_dqs_timing=0 */
190 value &= ~(CP_PHONY_DQS_TIMING_MASK << CP_PHONY_DQS_TIMING_SHIFT);
191 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS05, value);
192
193 /* switch off DLL_RESET */
194 do {
195 value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09);
196 value |= SDHC_PHY_SW_RESET;
197 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09, value);
198 value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09);
199 /* polling PHY_INIT_COMPLETE */
200 } while ((value & SDHC_PHY_INIT_COMPLETE) != SDHC_PHY_INIT_COMPLETE);
201
202 /* program PHY_DQ_TIMING_REG */
203 value = (CP_IO_MASK_ALWAYS_ON(combo_phy_reg->cp_io_mask_always_on)) |
204 (CP_IO_MASK_END(combo_phy_reg->cp_io_mask_end)) |
205 (CP_IO_MASK_START(combo_phy_reg->cp_io_mask_start)) |
206 (CP_DATA_SELECT_OE_END(combo_phy_reg->cp_data_select_oe_end));
207
208 ret = cdns_sdmmc_write_phy_reg(cdns_params.reg_base + SDHC_CDNS_HRS04,
209 COMBO_PHY_REG + PHY_DQ_TIMING_REG,
210 cdns_params.reg_base + SDHC_CDNS_HRS05, value);
211 if (ret != 0U) {
212 return ret;
213 }
214
215 value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09);
216 value |= (HRS_09_EXTENDED_RD_MODE | HRS_09_EXTENDED_WR_MODE |
217 HRS_09_RDCMD_EN | HRS_09_RDDATA_EN);
218 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09, value);
219
220 value = 0;
221 value = SDHC_HCSDCLKADJ(HRS_10_HCSDCLKADJ_VAL);
222 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS10, value);
223
224 value = 0;
225 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS16, value);
226
227 value = (10 << 16);
228 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS07, value);
229
230 return 0;
231 }
232
cdns_read(int lba,uintptr_t buf,size_t size)233 int cdns_read(int lba, uintptr_t buf, size_t size)
234 {
235 return 0;
236 }
237
cdns_write(int lba,uintptr_t buf,size_t size)238 int cdns_write(int lba, uintptr_t buf, size_t size)
239 {
240 return 0;
241 }
242
cdns_init(void)243 void cdns_init(void)
244 {
245 /* Dummy function pointer for cdns_init. */
246 }
247
cdns_prepare(int dma_start_addr,uintptr_t dma_buff,size_t size)248 int cdns_prepare(int dma_start_addr, uintptr_t dma_buff, size_t size)
249 {
250 struct cdns_idmac_desc *cdns_desc_data;
251 assert(((dma_buff & CDNSMMC_ADDRESS_MASK) == 0) &&
252 (cdns_params.desc_size > 0));
253
254 cdns_desc_data = (struct cdns_idmac_desc *)cdns_params.desc_base;
255 sd_host_adma_prepare(cdns_desc_data, dma_buff, size);
256
257 return 0;
258 }
259
cdns_host_set_clk(uint32_t clk)260 void cdns_host_set_clk(uint32_t clk)
261 {
262 uint32_t ret = 0;
263 uint32_t sdclkfsval = 0;
264 uint32_t dtcvval = 0xE;
265
266 sdclkfsval = (SD_HOST_CLK / 2) / clk;
267 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS11, 0);
268 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS11,
269 (dtcvval << SDMMC_CDN_DTCV) | (sdclkfsval << SDMMC_CDN_SDCLKFS) |
270 (1 << SDMMC_CDN_ICE));
271
272 ret = cdns_wait_ics(5000, cdns_params.reg_base + SDHC_CDNS_SRS11);
273 if (ret != 0) {
274 ERROR("Waiting ICS timeout");
275 }
276 /* Enable DLL reset */
277 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09,
278 mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09) & ~0x00000001);
279 /* Set extended_wr_mode */
280 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09,
281 (mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09) & 0xFFFFFFF7) |
282 (1 << EXTENDED_WR_MODE));
283 /* Release DLL reset */
284 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09,
285 mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09) | PHY_SW_RESET_EN);
286 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09,
287 mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09) | RDCMD_EN);
288
289 do {
290 mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09);
291 } while (~mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09) &
292 (PHY_INIT_COMPLETE_BIT));
293
294 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS11, (dtcvval << SDMMC_CDN_DTCV) |
295 (sdclkfsval << SDMMC_CDN_SDCLKFS) | (1 << SDMMC_CDN_ICE) |
296 (1 << SDMMC_CDN_SDCE));
297 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS13, 0xFFFFFFFF);
298 }
299
cdns_set_ios(unsigned int clk,unsigned int width)300 int cdns_set_ios(unsigned int clk, unsigned int width)
301 {
302 uint32_t _status = 0;
303
304 _status = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
305 switch (width) {
306 case MMC_BUS_WIDTH_1:
307 _status &= ~(BIT4);
308 break;
309
310 case MMC_BUS_WIDTH_4:
311 _status |= BIT4;
312 break;
313
314 case MMC_BUS_WIDTH_8:
315 _status |= BIT8;
316 break;
317
318 default:
319 assert(0);
320 break;
321 }
322 mmio_write_32((cdns_params.reg_base + SDHC_CDNS_SRS10), _status);
323 cdns_host_set_clk(clk);
324
325 return 0;
326 }
327
cdns_sdmmc_write_sd_host_reg(uint32_t addr,uint32_t data)328 int cdns_sdmmc_write_sd_host_reg(uint32_t addr, uint32_t data)
329 {
330 uint32_t value = 0;
331
332 value = mmio_read_32(addr);
333 value &= ~SDHC_REG_MASK;
334 value |= data;
335 mmio_write_32(addr, value);
336 value = mmio_read_32(addr);
337
338 if (value != data) {
339 ERROR("SD host address is not set properly\n");
340 return -ENXIO;
341 }
342
343 return 0;
344 }
345
346
347
sd_host_oper_mode(enum sd_opr_modes opr_mode)348 void sd_host_oper_mode(enum sd_opr_modes opr_mode)
349 {
350
351 uint32_t reg = 0;
352
353 switch (opr_mode) {
354 case SD_HOST_OPR_MODE_HV4E_0_SDMA_32:
355 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
356 reg &= ~(DMA_SEL_BIT);
357 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg);
358 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS15);
359 reg &= ~(HV4E | BIT_AD_64);
360 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS15, reg);
361 break;
362
363 case SD_HOST_OPR_MODE_HV4E_1_SDMA_32:
364 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
365 reg &= ~(DMA_SEL_BIT);
366 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg);
367 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS15);
368 reg &= ~(HV4E | BIT_AD_64);
369 reg |= (HV4E);
370 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS15, reg);
371 break;
372
373 case SD_HOST_OPR_MODE_HV4E_1_SDMA_64:
374 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
375 reg &= ~(DMA_SEL_BIT);
376 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg);
377 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS15);
378 reg |= (HV4E | BIT_AD_64);
379 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS15, reg);
380 break;
381
382 case SD_HOST_OPR_MODE_HV4E_0_ADMA_32:
383 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
384 reg &= ~(DMA_SEL_BIT);
385 reg |= DMA_SEL_BIT_2;
386 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg);
387 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS15);
388 reg &= ~(HV4E | BIT_AD_64);
389 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS15, reg);
390 break;
391
392 case SD_HOST_OPR_MODE_HV4E_0_ADMA_64:
393 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
394 reg &= ~(DMA_SEL_BIT);
395 reg |= DMA_SEL_BIT_3;
396 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg);
397 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS15);
398 reg &= ~(HV4E | BIT_AD_64);
399 reg |= BIT_AD_64;
400 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS15, reg);
401 break;
402
403 case SD_HOST_OPR_MODE_HV4E_1_ADMA_32:
404 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
405 reg &= ~(DMA_SEL_BIT);
406 reg |= DMA_SEL_BIT_2;
407 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg);
408 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS15);
409 reg &= ~(HV4E | BIT_AD_64);
410 reg |= HV4E;
411 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS15, reg);
412 break;
413
414 case SD_HOST_OPR_MODE_HV4E_1_ADMA_64:
415 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
416 reg &= ~(DMA_SEL_BIT);
417 reg |= DMA_SEL_BIT_2;
418 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg);
419 reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS15);
420 reg |= (HV4E | BIT_AD_64);
421 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS15, reg);
422 break;
423 }
424 }
425
card_reset(bool power_enable)426 void card_reset(bool power_enable)
427 {
428 uint32_t reg_value = 0;
429
430 /* Reading SRS10 value before writing */
431 reg_value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
432
433 if (power_enable == true) {
434 reg_value &= ~((7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP));
435 reg_value = ((1 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP));
436 } else {
437 reg_value &= ~((7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP));
438 }
439 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg_value);
440 }
441
high_speed_enable(bool mode)442 void high_speed_enable(bool mode)
443 {
444
445 uint32_t reg_value = 0;
446 /* Reading SRS10 value before writing */
447 reg_value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
448
449 if (mode == true) {
450 reg_value |= HS_EN;
451 } else {
452 reg_value &= ~HS_EN;
453 }
454
455 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg_value);
456 }
457
cdns_reset(void)458 int cdns_reset(void)
459 {
460 volatile uint32_t data = 0;
461 uint32_t count = 0;
462
463 /* Software reset */
464 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS11, SRS11_SRFA);
465 /* Wait status command response ready */
466 do {
467 data = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS00);
468 count++;
469 if (count >= CDNS_TIMEOUT) {
470 return -ETIMEDOUT;
471 }
472 /* Wait for SRS11 */
473 } while (((SRS11_SRFA_CHK(data)) & 1) == 1);
474
475 return 0;
476 }
477
sdmmc_host_init(bool uhs2_enable)478 void sdmmc_host_init(bool uhs2_enable)
479 {
480 uint32_t timeout;
481
482 /* SRS11 - Host Control default value set */
483 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS11, 0x0);
484
485 /* Waiting for detect card */
486 timeout = TIMEOUT;
487 do {
488 udelay(250);
489 if (--timeout <= 0) {
490 NOTICE(" SDHC Card Detecion failed!!!\n");
491 panic();
492 }
493 } while (((mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS09) & CHECK_CARD) == 0));
494
495 /* UHS2 Host setting */
496 if (uhs2_enable == true) {
497 /** need to implement*/
498 }
499
500 /* Card reset */
501
502 card_reset(1);
503 udelay(2500);
504 card_reset(0);
505 udelay(2500);
506 card_reset(1);
507 udelay(2500);
508
509 /* Enable Interrupt Flags*/
510 mmio_write_32((cdns_params.reg_base + SDHC_CDNS_SRS13), ~0);
511 high_speed_enable(true);
512 }
513
cdns_sd_host_init(struct cdns_sdmmc_combo_phy * mmc_combo_phy_reg,struct cdns_sdmmc_sdhc * mmc_sdhc_reg)514 int cdns_sd_host_init(struct cdns_sdmmc_combo_phy *mmc_combo_phy_reg,
515 struct cdns_sdmmc_sdhc *mmc_sdhc_reg)
516 {
517 int ret = 0;
518
519 ret = cdns_reset();
520 if (ret != 0U) {
521 ERROR("Program phy reg init failed");
522 return ret;
523 }
524
525 ret = cdns_program_phy_reg(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg);
526 if (ret != 0U) {
527 ERROR("Program phy reg init failed");
528 return ret;
529 }
530 sdmmc_host_init(0);
531 cdns_host_set_clk(100000);
532
533 sd_host_oper_mode(SD_HOST_OPR_MODE_HV4E_0_ADMA_64);
534
535 return 0;
536 }
537
cdns_send_cmd(struct mmc_cmd * cmd)538 int cdns_send_cmd(struct mmc_cmd *cmd)
539 {
540 uint32_t cmd_flags = 0;
541 uint32_t timeout = 0;
542 uint32_t status_check = 0;
543 uint32_t mode = 0;
544 uint32_t status;
545
546 assert(cmd);
547
548 cmd_flags = CDNS_HOST_CMD_INHIBIT | CDNS_HOST_DATA_INHIBIT;
549
550 if ((cmd->cmd_idx == SD_STOP_TRANSMISSION) && (!data_cmd)) {
551 cmd_flags &= ~CDNS_HOST_DATA_INHIBIT;
552 }
553
554 timeout = TIMEOUT;
555 do {
556 udelay(100);
557 if (--timeout <= 0) {
558 udelay(50);
559 NOTICE("Timeout occur data and cmd line %x\n",
560 mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS09));
561 panic();
562 }
563 } while ((mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS09) & (cmd_flags)));
564
565 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS12, 0xFFFFFFFF);
566 cmd_flags = 0;
567 cmd_flags = (cmd->cmd_idx) << COM_IDX;
568
569 if ((cmd->resp_type & MMC_RSP_136) != 0) {
570 cmd_flags |= RES_TYPE_SEL_136;
571 } else if (((cmd->resp_type & MMC_RSP_48) != 0) &&
572 ((cmd->resp_type & MMC_RSP_BUSY) != 0)) {
573 cmd_flags |= RES_TYPE_SEL_48_B;
574 } else if ((cmd->resp_type & MMC_RSP_48) != 0) {
575 cmd_flags |= RES_TYPE_SEL_48;
576 } else {
577 cmd_flags &= ~RES_TYPE_SEL_NO;
578 }
579
580 if ((cmd->resp_type & MMC_RSP_CRC) != 0) {
581 cmd_flags |= CMD_CHECK_RESP_CRC;
582 }
583
584 if ((cmd->resp_type & MMC_RSP_CMD_IDX) != 0) {
585 cmd_flags |= CMD_IDX_CHK_ENABLE;
586 }
587
588 if ((cmd->cmd_idx == MMC_ACMD(51)) || (cmd->cmd_idx == MMC_CMD(17)) ||
589 (cmd->cmd_idx == MMC_CMD(18)) || (cmd->cmd_idx == MMC_CMD(24)) ||
590 (cmd->cmd_idx == MMC_CMD(25))) {
591 mmio_write_8((cdns_params.reg_base + DTCV_OFFSET), DTCV_VAL);
592 cmd_flags |= DATA_PRESENT;
593 mode |= BLK_CNT_EN;
594
595 mode |= (DMA_ENABLED);
596 if ((cmd->cmd_idx == SD_WRITE_MULTIPLE_BLOCK) ||
597 (cmd->cmd_idx == SD_READ_MULTIPLE_BLOCK)) {
598 mode |= (MULTI_BLK_READ);
599 } else {
600 mode &= ~(MULTI_BLK_READ);
601 }
602 if ((cmd->cmd_idx == SD_WRITE_MULTIPLE_BLOCK) ||
603 (cmd->cmd_idx == SD_WRITE_SINGLE_BLOCK)) {
604 mode &= ~CMD_READ;
605 } else {
606 mode |= CMD_READ;
607 }
608 mmio_write_16(cdns_params.reg_base + SDHC_CDNS_SRS03, mode);
609
610 } else {
611 mmio_write_8((cdns_params.reg_base + DTCV_OFFSET), DTCV_VAL);
612 }
613
614 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS02, cmd->cmd_arg);
615 mmio_write_16((cdns_params.reg_base + CICE_OFFSET),
616 SDHCI_MAKE_CMD(cmd->cmd_idx, cmd_flags));
617
618 timeout = TIMEOUT;
619
620 do {
621 udelay(CDNS_TIMEOUT);
622 status = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS12);
623 } while (((status & (INT_CMD_DONE | ERROR_INT)) == 0) && (timeout-- > 0));
624
625 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS12, (SRS_12_CC_EN));
626 status_check = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS12) & 0xffff8000;
627 if (status_check != 0U) {
628 timeout = TIMEOUT;
629 ERROR("SD host controller send command failed, SRS12 = %x", status_check);
630 return -1;
631 }
632
633 if (!((cmd_flags & RES_TYPE_SEL_NO) == 0)) {
634 cmd->resp_data[0] = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS04);
635 if ((cmd_flags & RES_TYPE_SEL_NO) == RES_TYPE_SEL_136) {
636 cmd->resp_data[1] = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS05);
637 cmd->resp_data[2] = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS06);
638 cmd->resp_data[3] = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS07);
639 /* 136-bit: RTS=01b, Response field R[127:8] - RESP3[23:0],
640 * RESP2[31:0], RESP1[31:0], RESP0[31:0]
641 * Subsystem expects 128 bits response but cadence SDHC sends
642 * 120 bits response from R[127:8]. Bits manupulation to address
643 * the correct responses for the 136 bit response type.
644 */
645 cmd->resp_data[3] = ((cmd->resp_data[3] << 8) |
646 ((cmd->resp_data[2] >> 24) &
647 CDNS_CSD_BYTE_MASK));
648 cmd->resp_data[2] = ((cmd->resp_data[2] << 8) |
649 ((cmd->resp_data[1] >> 24) &
650 CDNS_CSD_BYTE_MASK));
651 cmd->resp_data[1] = ((cmd->resp_data[1] << 8) |
652 ((cmd->resp_data[0] >> 24) &
653 CDNS_CSD_BYTE_MASK));
654 cmd->resp_data[0] = (cmd->resp_data[0] << 8);
655 }
656 }
657
658 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS12, (SRS_12_CC_EN));
659
660 return 0;
661 }
662
sd_host_adma_prepare(struct cdns_idmac_desc * desc_ptr,uint64_t buf,size_t size)663 void sd_host_adma_prepare(struct cdns_idmac_desc *desc_ptr, uint64_t buf,
664 size_t size)
665 {
666 uint32_t full_desc_cnt = 0;
667 uint32_t non_full_desc_cnt = 0;
668 uint64_t desc_address;
669 uint32_t block_count;
670 uint32_t transfer_block_size;
671
672 full_desc_cnt = (size / PAGE_BUFFER_LEN);
673 non_full_desc_cnt = (size % PAGE_BUFFER_LEN);
674 for (int i = 0; i < full_desc_cnt; i++) {
675 desc_ptr->attr = (ADMA_DESC_TRANSFER_DATA | ADMA_DESC_ATTR_VALID);
676 desc_ptr->len = 0; // 0 means 64kb page size it will take
677 desc_ptr->addr_lo = 0;
678 #if CONFIG_DMA_ADDR_T_64BIT == 1
679 desc_ptr->addr_hi = (uint32_t)((buf >> 32) & 0xffffffff);
680 #endif
681 if (non_full_desc_cnt == 0) {
682 desc_ptr->attr |= (ADMA_DESC_ATTR_END);
683 }
684 buf += PAGE_BUFFER_LEN;
685 }
686
687 if (non_full_desc_cnt != 0) {
688 desc_ptr->attr =
689 (ADMA_DESC_TRANSFER_DATA | ADMA_DESC_ATTR_END | ADMA_DESC_ATTR_VALID);
690 desc_ptr->addr_lo = buf & 0xffffffff;
691 desc_ptr->len = size;
692 #if CONFIG_DMA_ADDR_T_64BIT == 1
693 desc_ptr->addr_hi = (uint32_t)((buf >> 32) & 0xffffffff);
694 #endif
695 desc_address = (uint64_t)desc_ptr;
696 if (size > MMC_MAX_BLOCK_LEN) {
697 transfer_block_size = MMC_MAX_BLOCK_LEN;
698 } else {
699 transfer_block_size = size;
700 }
701
702 block_count = (size / transfer_block_size);
703 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS01,
704 ((transfer_block_size << BLOCK_SIZE) | SDMA_BUF |
705 (block_count << BLK_COUNT_CT)));
706 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS22,
707 (uint32_t)desc_address & 0xFFFFFFFF);
708 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS23,
709 (uint32_t)(desc_address >> 32 & 0xFFFFFFFF));
710 }
711 }
712
cdns_mmc_init(struct cdns_sdmmc_params * params,struct mmc_device_info * info)713 int cdns_mmc_init(struct cdns_sdmmc_params *params,
714 struct mmc_device_info *info)
715 {
716
717 int result = 0;
718
719 assert((params != NULL) &&
720 ((params->reg_base & MMC_BLOCK_MASK) == 0) &&
721 ((params->desc_size & MMC_BLOCK_MASK) == 0) &&
722 ((params->reg_pinmux & MMC_BLOCK_MASK) == 0) &&
723 ((params->reg_phy & MMC_BLOCK_MASK) == 0) &&
724 (params->desc_size > 0) &&
725 (params->clk_rate > 0) &&
726 ((params->bus_width == MMC_BUS_WIDTH_1) ||
727 (params->bus_width == MMC_BUS_WIDTH_4) ||
728 (params->bus_width == MMC_BUS_WIDTH_8)));
729
730 memcpy(&cdns_params, params, sizeof(struct cdns_sdmmc_params));
731
732 cdns_set_sdmmc_var(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg);
733 result = cdns_sd_host_init(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg);
734 if (result < 0) {
735 return result;
736 }
737
738 cdns_params.cdn_sdmmc_dev_type = info->mmc_dev_type;
739 cdns_params.cdn_sdmmc_dev_mode = SD_DS;
740
741 result = mmc_init(&cdns_sdmmc_ops, params->clk_rate, params->bus_width,
742 params->flags, info);
743
744 return result;
745 }
746