1 /* 2 * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MNPMUSRAMMSGBLOCK_DDR3_H 8 #define MNPMUSRAMMSGBLOCK_DDR3_H 9 10 /* 11 * DDR3U_1D training firmware message block structure 12 * 13 * Please refer to the Training Firmware App Note for futher information about 14 * the usage for Message Block. 15 */ 16 struct pmu_smb_ddr_1d { 17 uint8_t reserved00; /* 18 * Byte offset 0x00, CSR Addr 0x54000, Direction=In 19 * reserved00[0:4] RFU, must be zero 20 * 21 * reserved00[5] = Train vrefDAC0 During Read Deskew 22 * 0x1 = Read Deskew will begin by enabling and roughly 23 * training the phy's per-lane reference voltages. 24 * Training the vrefDACs CSRs will increase the maximum 1D 25 * training time by around half a millisecond, but will 26 * improve 1D training accuracy on systems with 27 * significant voltage-offsets between lane read eyes. 28 * 0x0 = Read Deskew will assume the messageblock's 29 * phyVref setting will work for all lanes. 30 * 31 * reserved00[6] = Enable High Effort WrDQ1D 32 * 0x1 = WrDQ1D will conditionally retry training at 33 * several extra RxClkDly Timings. This will increase the 34 * maximum 1D training time by up to 4 extra iterations of 35 * WrDQ1D. This is only required in systems that suffer 36 * from very large, asymmetric eye-collapse when receiving 37 * PRBS patterns. 38 * 0x0 = WrDQ1D assume rxClkDly values found by SI 39 * Friendly RdDqs1D will work for receiving PRBS patterns 40 * 41 * reserved00[7] = Optimize for the special hard macros in 42 * TSMC28. 43 * 0x1 = set if the phy being trained was manufactured in 44 * any TSMC28 process node. 45 * 0x0 = otherwise, when not training a TSMC28 phy, leave 46 * this field as 0. 47 */ 48 uint8_t msgmisc; /* 49 * Byte offset 0x01, CSR Addr 0x54000, Direction=In 50 * Contains various global options for training. 51 * 52 * Bit fields: 53 * 54 * msgmisc[0] = MTESTEnable 55 * 0x1 = Pulse primary digital test output bump at the end 56 * of each major training stage. This enables observation 57 * of training stage completion by observing the digital 58 * test output. 59 * 0x0 = Do not pulse primary digital test output bump 60 * 61 * msgmisc[1] = SimulationOnlyReset 62 * 0x1 = Verilog only simulation option to shorten 63 * duration of DRAM reset pulse length to 1ns. 64 * Must never be set to 1 in silicon. 65 * 0x0 = Use reset pulse length specified by JEDEC 66 * standard. 67 * 68 * msgmisc[2] = SimulationOnlyTraining 69 * 0x1 = Verilog only simulation option to shorten the 70 * duration of the training steps by performing fewer 71 * iterations. 72 * Must never be set to 1 in silicon. 73 * 0x0 = Use standard training duration. 74 * 75 * msgmisc[3] = RFU, must be zero 76 * 77 * msgmisc[4] = Suppress streaming messages, including 78 * assertions, regardless of hdtctrl setting. 79 * Stage Completion messages, as well as training completion 80 * and error messages are still sent depending on hdtctrl 81 * setting. 82 * 83 * msgmisc[5] = PerByteMaxRdLat 84 * 0x1 = Each DBYTE will return dfi_rddata_valid at the 85 * lowest possible latency. This may result in unaligned 86 * data between bytes to be returned to the DFI. 87 * 0x0 = Every DBYTE will return dfi_rddata_valid 88 * simultaneously. This will ensure that data bytes will 89 * return aligned accesses to the DFI. 90 * 91 * msgmisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, 92 * otherwise RFU, must be zero) 93 * 0x1 = Support rank populated with a subset of byte, but 94 * where even-odd pair of rank support all the byte 95 * 0x0 = All rank populated with all the byte (tyical 96 * configuration) 97 * 98 * msgmisc[7] RFU, must be zero 99 * 100 * Notes: 101 * 102 * - SimulationOnlyReset and SimulationOnlyTraining can be 103 * used to speed up simulation run times, and must never 104 * be used in real silicon. Some VIPs may have checks on 105 * DRAM reset parameters that may need to be disabled when 106 * using SimulationOnlyReset. 107 */ 108 uint16_t pmurevision; /* 109 * Byte offset 0x02, CSR Addr 0x54001, Direction=Out 110 * PMU firmware revision ID 111 * After training is run, this address will contain the 112 * revision ID of the firmware. 113 * Please reference this revision ID when filing support 114 * cases. 115 */ 116 uint8_t pstate; /* 117 * Byte offset 0x04, CSR Addr 0x54002, Direction=In 118 * Must be set to the target pstate to be trained 119 * 0x0 = pstate 0 120 * 0x1 = pstate 1 121 * 0x2 = pstate 2 122 * 0x3 = pstate 3 123 * All other encodings are reserved 124 */ 125 uint8_t pllbypassen; /* 126 * Byte offset 0x05, CSR Addr 0x54002, Direction=In 127 * Set according to whether target pstate uses PHY PLL 128 * bypass 129 * 0x0 = PHY PLL is enabled for target pstate 130 * 0x1 = PHY PLL is bypassed for target pstate 131 */ 132 uint16_t dramfreq; /* 133 * Byte offset 0x06, CSR Addr 0x54003, Direction=In 134 * DDR data rate for the target pstate in units of MT/s. 135 * For example enter 0x0640 for DDR1600. 136 */ 137 uint8_t dfifreqratio; /* 138 * Byte offset 0x08, CSR Addr 0x54004, Direction=In 139 * Frequency ratio betwen DfiCtlClk and SDRAM memclk. 140 * 0x1 = 1:1 141 * 0x2 = 1:2 142 * 0x4 = 1:4 143 */ 144 uint8_t bpznresval; /* 145 * Byte offset 0x09, CSR Addr 0x54004, Direction=In 146 * Overwrite the value of precision resistor connected to 147 * Phy BP_ZN 148 * 0x00 = Do not program. Use current CSR value. 149 * 0xf0 = 240 Ohm 150 * 0x78 = 120 Ohm 151 * 0x28 = 40 Ohm 152 * All other values are reserved. 153 * It is recommended to set this to 0x00. 154 */ 155 uint8_t phyodtimpedance; /* 156 * Byte offset 0x0a, CSR Addr 0x54005, Direction=In 157 * Must be programmed to the termination impedance in ohms 158 * used by PHY during reads. 159 * 160 * 0x0 = Firmware skips programming (must be manually 161 * programmed by user prior to training start) 162 * 163 * See PHY databook for legal termination impedance values. 164 * 165 * For digital simulation, any legal value can be used. For 166 * silicon, the users must determine the correct value 167 * through SI simulation or other methods. 168 */ 169 uint8_t phydrvimpedance; /* 170 * Byte offset 0x0b, CSR Addr 0x54005, Direction=In 171 * Must be programmed to the driver impedance in ohms used 172 * by PHY during writes for all DBYTE drivers 173 * (DQ/DM/DBI/DQS). 174 * 175 * 0x0 = Firmware skips programming (must be manually 176 * programmed by user prior to training start) 177 * 178 * See PHY databook for legal R_on driver impedance values. 179 * 180 * For digital simulation, any value can be used that is not 181 * Hi-Z. For silicon, the users must determine the correct 182 * value through SI simulation or other methods. 183 */ 184 uint8_t phyvref; /* 185 * Byte offset 0x0c, CSR Addr 0x54006, Direction=In 186 * Must be programmed with the Vref level to be used by the 187 * PHY during reads 188 * 189 * The units of this field are a percentage of VDDQ 190 * according to the following equation: 191 * 192 * Receiver Vref = VDDQ*phyvref[6:0]/128 193 * 194 * For example to set Vref at 0.75*VDDQ, set this field to 195 * 0x60. 196 * 197 * For digital simulation, any legal value can be used. For 198 * silicon, the users must calculate the analytical Vref by 199 * using the impedances, terminations, and series resistance 200 * present in the system. 201 */ 202 uint8_t dramtype; /* 203 * Byte offset 0x0d, CSR Addr 0x54006, Direction=In 204 * Module Type: 205 * 0x01 = DDR3 unbuffered 206 * 0x02 = Reserved 207 * 0x03 = Reserved 208 * 0x04 = Reserved 209 * 0x05 = Reserved 210 */ 211 uint8_t disableddbyte; /* 212 * Byte offset 0x0e, CSR Addr 0x54007, Direction=In 213 * Bitmap to indicate which Dbyte are not connected (for 214 * DByte 0 to 7): 215 * Set disableddbyte[i] to 1 only to specify that DByte is 216 * not need to be trained (DByte 8 can be disabled via 217 * enableddqs setting) 218 */ 219 uint8_t enableddqs; /* 220 * Byte offset 0x0f, CSR Addr 0x54007, Direction=In 221 * Total number of DQ bits enabled in PHY 222 */ 223 uint8_t cspresent; /* 224 * Byte offset 0x10, CSR Addr 0x54008, Direction=In 225 * Indicates presence of DRAM at each chip select for PHY. 226 * Each bit corresponds to a logical CS. 227 * 228 * If the bit is set to 1, the CS is connected to DRAM. 229 * If the bit is set to 0, the CS is not connected to DRAM. 230 * 231 * cspresent[0] = CS0 is populated with DRAM 232 * cspresent[1] = CS1 is populated with DRAM 233 * cspresent[2] = CS2 is populated with DRAM 234 * cspresent[3] = CS3 is populated with DRAM 235 * cspresent[7:4] = Reserved (must be programmed to 0) 236 */ 237 uint8_t cspresentd0; /* 238 * Byte offset 0x11, CSR Addr 0x54008, Direction=In 239 * The CS signals from field cspresent that are routed to 240 * DIMM connector 0 241 */ 242 uint8_t cspresentd1; /* 243 * Byte offset 0x12, CSR Addr 0x54009, Direction=In 244 * The CS signals from field cspresent that are routed to 245 * DIMM connector 1 246 */ 247 uint8_t addrmirror; /* 248 * Byte offset 0x13, CSR Addr 0x54009, Direction=In 249 * Corresponds to CS[3:0] 250 * 1 = Address Mirror. 251 * 0 = No Address Mirror. 252 */ 253 uint8_t cstestfail; /* 254 * Byte offset 0x14, CSR Addr 0x5400a, Direction=Out 255 * This field will be set if training fails on any rank. 256 * 0x0 = No failures 257 * non-zero = one or more ranks failed training 258 */ 259 uint8_t phycfg; /* 260 * Byte offset 0x15, CSR Addr 0x5400a, Direction=In 261 * Additional mode bits. 262 * 263 * Bit fields: 264 * [0] SlowAccessMode: 265 * 1 = 2T Address Timing. 266 * 0 = 1T Address Timing. 267 * [7-1] RFU, must be zero 268 * 269 * WARNING: In case of DDR4 Geardown Mode (mr3[A3] == 1), 270 * phycfg[0] must be 0. 271 */ 272 uint16_t sequencectrl; /* 273 * Byte offset 0x16, CSR Addr 0x5400b, Direction=In 274 * Controls the training steps to be run. Each bit 275 * corresponds to a training step. 276 * 277 * If the bit is set to 1, the training step will run. 278 * If the bit is set to 0, the training step will be 279 * skipped. 280 * 281 * Training step to bit mapping: 282 * sequencectrl[0] = Run DevInit - Device/phy 283 * initialization. Should always be set. 284 * sequencectrl[1] = Run WrLvl - Write leveling 285 * sequencectrl[2] = Run RxEn - Read gate training 286 * sequencectrl[3] = Run RdDQS1D - 1d read dqs training 287 * sequencectrl[4] = Run WrDQ1D - 1d write dq training 288 * sequencectrl[5] = RFU, must be zero 289 * sequencectrl[6] = RFU, must be zero 290 * sequencectrl[7] = RFU, must be zero 291 * sequencectrl[8] = Run RdDeskew - Per lane read dq deskew 292 * training 293 * sequencectrl[9] = Run MxRdLat - Max read latency training 294 * sequencectrl[10] = RFU, must be zero 295 * sequencectrl[11] = RFU, must be zero 296 * sequencectrl[12] = RFU, must be zero 297 * sequencectrl[13] = RFU, must be zero 298 * sequencectrl[15-14] = RFU, must be zero 299 */ 300 uint8_t hdtctrl; /* 301 * Byte offset 0x18, CSR Addr 0x5400c, Direction=In 302 * To control the total number of debug messages, a 303 * verbosity subfield (hdtctrl, Hardware Debug Trace 304 * Control) exists in the message block. Every message has a 305 * verbosity level associated with it, and as the hdtctrl 306 * value is increased, less important s messages stop being 307 * sent through the mailboxes. The meanings of several major 308 * hdtctrl thresholds are explained below: 309 * 310 * 0x04 = Maximal debug messages (e.g., Eye contours) 311 * 0x05 = Detailed debug messages (e.g. Eye delays) 312 * 0x0A = Coarse debug messages (e.g. rank information) 313 * 0xC8 = Stage completion 314 * 0xC9 = Assertion messages 315 * 0xFF = Firmware completion messages only 316 */ 317 uint8_t reserved19; /* Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A */ 318 uint8_t reserved1a; /* Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A */ 319 uint8_t share2dvrefresult; /* 320 * Byte offset 0x1b, CSR Addr 0x5400d, Direction=In 321 * Bitmap that designates the phy's vref source for every 322 * pstate 323 * If share2dvrefresult[x] = 0, then after 2D training, 324 * pstate x will continue using the phyVref provided in 325 * pstate x's 1D messageblock. 326 * If share2dvrefresult[x] = 1, then after 2D training, 327 * pstate x will use the per-lane VrefDAC0/1 CSRs trained by 328 * 2d training. 329 */ 330 uint8_t reserved1c; /* Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A */ 331 uint8_t reserved1d; /* Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A */ 332 uint8_t reserved1e; /* 333 * Byte offset 0x1e, CSR Addr 0x5400f, Direction=In 334 * Input for constraining the range of vref(DQ) values 335 * training will collect data for, usually reducing training 336 * time. However, too large of a voltage range may cause 337 * longer 2D training times while too small of a voltage 338 * range may truncate passing regions. When in doubt, leave 339 * this field set to 0. 340 * Used by 2D training in: Rd2D, Wr2D 341 * 342 * reserved1E[0-3]: Rd2D Voltage Range 343 * 0 = Training will search all phy vref(DQ) settings 344 * 1 = limit to +/-2 %VDDQ from phyVref 345 * 2 = limit to +/-4 %VDDQ from phyVref 346 * . . . 347 * 15 = limit to +/-30% VDDQ from phyVref 348 * 349 * reserved1E[4-7]: Wr2D Voltage Range 350 * 0 = Training will search all dram vref(DQ) settings 351 * 1 = limit to +/-2 %VDDQ from mr6 352 * 2 = limit to +/-4 %VDDQ from mr6 353 * . . . 354 * 15 = limit to +/-30% VDDQ from mr6 355 */ 356 uint8_t reserved1f; /* 357 * Byte offset 0x1f, CSR Addr 0x5400f, Direction=In 358 * Extended training option: 359 * 360 * reserved1F[1:0]: Configured RxClkDly offset try during 361 * WrDq1D high-effort (i.e., when reserved00[6] is set) 362 * 0: -8, +8, -16, +16 363 * 1: -4, +4, -8, +8, -12, +12, -16, +16 364 * 2: -2, +2, -4, +4, -6, +6, -8, +8 365 * 3: -2, +2, -4, +4, -6, +6, -8, +8, -10, +10, -12, +12, 366 * -14, +14, -16, +16 367 * 368 * reserved1F[2]: When set, execute again WrDq1D after 369 * RdDqs1D PRBS 370 * 371 * reserved1F[3]: When set redo RdDeskew with PRBS after 372 * (first) WrDqs1D 373 * 374 * reserved1F[7:4]: This field is reserved and must be 375 * programmed to 0x00. 376 */ 377 uint8_t reserved20; /* 378 * Byte offset 0x20, CSR Addr 0x54010, Direction=In 379 * This field is reserved and must be programmed to 0x00, 380 * excepted for Reserved: 381 * Reserved MREP assume raising edge is found when 382 * reserved20[3:0]+3 consecutive 1 are received during MREP 383 * fine delay swept; reserved20[6:0] thus permits to 384 * increase tolerance for noisy system. And if reserved20[7] 385 * is set, MREP training is failing if no raising edge is 386 * found (otherwise the raising edge is assume close to 387 * delay 0). 388 */ 389 uint8_t reserved21; /* 390 * Byte offset 0x21, CSR Addr 0x54010, Direction=In 391 * This field is reserved and must be programmed to 0x00, 392 * excepted for Reserved: 393 * Reserved DWL assume raising edge is found when 394 * reserved21[3:0]+3 consecutive 1 are received during DWL 395 * fine delay swept; reserved21[6:0] thus permits to 396 * increase tolerance for noisy system. And if reserved21[7] 397 * is set, DWL training is failing if no raising edge is 398 * found (otherwise the raising edge is assume close to 399 * delay 0). 400 */ 401 uint16_t phyconfigoverride; /* 402 * Byte offset 0x22, CSR Addr 0x54011, Direction=In 403 * Override PhyConfig csr. 404 * 0x0: Use hardware csr value for PhyConfing 405 * (recommended) 406 * Other values: Use value for PhyConfig instead of 407 * Hardware value. 408 */ 409 uint8_t dfimrlmargin; /* 410 * Byte offset 0x24, CSR Addr 0x54012, Direction=In 411 * Margin added to smallest passing trained DFI Max Read 412 * Latency value, in units of DFI clocks. Recommended to be 413 * >= 1. 414 */ 415 int8_t cdd_rr_3_2; /* 416 * Byte offset 0x25, CSR Addr 0x54012, Direction=Out 417 * This is a signed integer value. 418 * Read to read critical delay difference from cs 3 to cs 2. 419 */ 420 int8_t cdd_rr_3_1; /* 421 * Byte offset 0x26, CSR Addr 0x54013, Direction=Out 422 * This is a signed integer value. 423 * Read to read critical delay difference from cs 3 to cs 1. 424 */ 425 int8_t cdd_rr_3_0; /* 426 * Byte offset 0x27, CSR Addr 0x54013, Direction=Out 427 * This is a signed integer value. 428 * Read to read critical delay difference from cs 3 to cs 0. 429 */ 430 int8_t cdd_rr_2_3; /* 431 * Byte offset 0x28, CSR Addr 0x54014, Direction=Out 432 * This is a signed integer value. 433 * Read to read critical delay difference from cs 2 to cs 3. 434 */ 435 int8_t cdd_rr_2_1; /* 436 * Byte offset 0x29, CSR Addr 0x54014, Direction=Out 437 * This is a signed integer value. 438 * Read to read critical delay difference from cs 2 to cs 1. 439 */ 440 int8_t cdd_rr_2_0; /* 441 * Byte offset 0x2a, CSR Addr 0x54015, Direction=Out 442 * This is a signed integer value. 443 * Read to read critical delay difference from cs 2 to cs 0. 444 */ 445 int8_t cdd_rr_1_3; /* 446 * Byte offset 0x2b, CSR Addr 0x54015, Direction=Out 447 * This is a signed integer value. 448 * Read to read critical delay difference from cs 1 to cs 3. 449 */ 450 int8_t cdd_rr_1_2; /* 451 * Byte offset 0x2c, CSR Addr 0x54016, Direction=Out 452 * This is a signed integer value. 453 * Read to read critical delay difference from cs 1 to cs 2. 454 */ 455 int8_t cdd_rr_1_0; /* 456 * Byte offset 0x2d, CSR Addr 0x54016, Direction=Out 457 * This is a signed integer value. 458 * Read to read critical delay difference from cs 1 to cs 0. 459 */ 460 int8_t cdd_rr_0_3; /* 461 * Byte offset 0x2e, CSR Addr 0x54017, Direction=Out 462 * This is a signed integer value. 463 * Read to read critical delay difference from cs 0 to cs 3. 464 */ 465 int8_t cdd_rr_0_2; /* 466 * Byte offset 0x2f, CSR Addr 0x54017, Direction=Out 467 * This is a signed integer value. 468 * Read to read critical delay difference from cs 0 to cs 2. 469 */ 470 int8_t cdd_rr_0_1; /* 471 * Byte offset 0x30, CSR Addr 0x54018, Direction=Out 472 * This is a signed integer value. 473 * Read to read critical delay difference from cs 0 to cs 1. 474 */ 475 int8_t cdd_ww_3_2; /* 476 * Byte offset 0x31, CSR Addr 0x54018, Direction=Out 477 * This is a signed integer value. 478 * Write to write critical delay difference from cs 3 to cs 479 * 2. 480 */ 481 int8_t cdd_ww_3_1; /* 482 * Byte offset 0x32, CSR Addr 0x54019, Direction=Out 483 * This is a signed integer value. 484 * Write to write critical delay difference from cs 3 to cs 485 * 1. 486 */ 487 int8_t cdd_ww_3_0; /* 488 * Byte offset 0x33, CSR Addr 0x54019, Direction=Out 489 * This is a signed integer value. 490 * Write to write critical delay difference from cs 3 to cs 491 * 0. 492 */ 493 int8_t cdd_ww_2_3; /* 494 * Byte offset 0x34, CSR Addr 0x5401a, Direction=Out 495 * This is a signed integer value. 496 * Write to write critical delay difference from cs 2 to cs 497 * 3. 498 */ 499 int8_t cdd_ww_2_1; /* 500 * Byte offset 0x35, CSR Addr 0x5401a, Direction=Out 501 * This is a signed integer value. 502 * Write to write critical delay difference from cs 2 to cs 503 * 1. 504 */ 505 int8_t cdd_ww_2_0; /* 506 * Byte offset 0x36, CSR Addr 0x5401b, Direction=Out 507 * This is a signed integer value. 508 * Write to write critical delay difference from cs 2 to cs 509 * 0. 510 */ 511 int8_t cdd_ww_1_3; /* 512 * Byte offset 0x37, CSR Addr 0x5401b, Direction=Out 513 * This is a signed integer value. 514 * Write to write critical delay difference from cs 1 to cs 515 * 3. 516 */ 517 int8_t cdd_ww_1_2; /* 518 * Byte offset 0x38, CSR Addr 0x5401c, Direction=Out 519 * This is a signed integer value. 520 * Write to write critical delay difference from cs 1 to cs 521 * 2. 522 */ 523 int8_t cdd_ww_1_0; /* 524 * Byte offset 0x39, CSR Addr 0x5401c, Direction=Out 525 * This is a signed integer value. 526 * Write to write critical delay difference from cs 1 to cs 527 * 0. 528 */ 529 int8_t cdd_ww_0_3; /* 530 * Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out 531 * This is a signed integer value. 532 * Write to write critical delay difference from cs 0 to cs 533 * 3. 534 */ 535 int8_t cdd_ww_0_2; /* 536 * Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out 537 * This is a signed integer value. 538 * Write to write critical delay difference from cs 0 to cs 539 * 2. 540 */ 541 int8_t cdd_ww_0_1; /* 542 * Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out 543 * This is a signed integer value. 544 * Write to write critical delay difference from cs 0 to cs 545 * 1. 546 */ 547 int8_t cdd_rw_3_3; /* 548 * Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out 549 * This is a signed integer value. 550 * Read to write critical delay difference from cs 3 to 551 * cs 3. 552 */ 553 int8_t cdd_rw_3_2; /* 554 * Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out 555 * This is a signed integer value. 556 * Read to write critical delay difference from cs 3 to 557 * cs 2. 558 */ 559 int8_t cdd_rw_3_1; /* 560 * Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out 561 * This is a signed integer value. 562 * Read to write critical delay difference from cs 3 to 563 * cs 1. 564 */ 565 int8_t cdd_rw_3_0; /* 566 * Byte offset 0x40, CSR Addr 0x54020, Direction=Out 567 * This is a signed integer value. 568 * Read to write critical delay difference from cs 3 to 569 * cs 0. 570 */ 571 int8_t cdd_rw_2_3; /* 572 * Byte offset 0x41, CSR Addr 0x54020, Direction=Out 573 * This is a signed integer value. 574 * Read to write critical delay difference from cs 2 to 575 * cs 3. 576 */ 577 int8_t cdd_rw_2_2; /* 578 * Byte offset 0x42, CSR Addr 0x54021, Direction=Out 579 * This is a signed integer value. 580 * Read to write critical delay difference from cs 2 to 581 * cs 2. 582 */ 583 int8_t cdd_rw_2_1; /* 584 * Byte offset 0x43, CSR Addr 0x54021, Direction=Out 585 * This is a signed integer value. 586 * Read to write critical delay difference from cs 2 to 587 * cs 1. 588 */ 589 int8_t cdd_rw_2_0; /* 590 * Byte offset 0x44, CSR Addr 0x54022, Direction=Out 591 * This is a signed integer value. 592 * Read to write critical delay difference from cs 2 to 593 * cs 0. 594 */ 595 int8_t cdd_rw_1_3; /* 596 * Byte offset 0x45, CSR Addr 0x54022, Direction=Out 597 * This is a signed integer value. 598 * Read to write critical delay difference from cs 1 to 599 * cs 3. 600 */ 601 int8_t cdd_rw_1_2; /* 602 * Byte offset 0x46, CSR Addr 0x54023, Direction=Out 603 * This is a signed integer value. 604 * Read to write critical delay difference from cs 1 to 605 * cs 2. 606 */ 607 int8_t cdd_rw_1_1; /* 608 * Byte offset 0x47, CSR Addr 0x54023, Direction=Out 609 * This is a signed integer value. 610 * Read to write critical delay difference from cs 1 to 611 * cs 1. 612 */ 613 int8_t cdd_rw_1_0; /* 614 * Byte offset 0x48, CSR Addr 0x54024, Direction=Out 615 * This is a signed integer value. 616 * Read to write critical delay difference from cs 1 to 617 * cs 0. 618 */ 619 int8_t cdd_rw_0_3; /* 620 * Byte offset 0x49, CSR Addr 0x54024, Direction=Out 621 * This is a signed integer value. 622 * Read to write critical delay difference from cs 0 to 623 * cs 3. 624 */ 625 int8_t cdd_rw_0_2; /* 626 * Byte offset 0x4a, CSR Addr 0x54025, Direction=Out 627 * This is a signed integer value. 628 * Read to write critical delay difference from cs 0 to 629 * cs 2. 630 */ 631 int8_t cdd_rw_0_1; /* 632 * Byte offset 0x4b, CSR Addr 0x54025, Direction=Out 633 * This is a signed integer value. 634 * Read to write critical delay difference from cs 0 to 635 * cs 1. 636 */ 637 int8_t cdd_rw_0_0; /* 638 * Byte offset 0x4c, CSR Addr 0x54026, Direction=Out 639 * This is a signed integer value. 640 * Read to write critical delay difference from cs 0 to 641 * cs 0. 642 */ 643 int8_t cdd_wr_3_3; /* 644 * Byte offset 0x4d, CSR Addr 0x54026, Direction=Out 645 * This is a signed integer value. 646 * Write to read critical delay difference from cs 3 to 647 * cs 3. 648 */ 649 int8_t cdd_wr_3_2; /* 650 * Byte offset 0x4e, CSR Addr 0x54027, Direction=Out 651 * This is a signed integer value. 652 * Write to read critical delay difference from cs 3 to 653 * cs 2. 654 */ 655 int8_t cdd_wr_3_1; /* 656 * Byte offset 0x4f, CSR Addr 0x54027, Direction=Out 657 * This is a signed integer value. 658 * Write to read critical delay difference from cs 3 to 659 * cs 1. 660 */ 661 int8_t cdd_wr_3_0; /* 662 * Byte offset 0x50, CSR Addr 0x54028, Direction=Out 663 * This is a signed integer value. 664 * Write to read critical delay difference from cs 3 to 665 * cs 0. 666 */ 667 int8_t cdd_wr_2_3; /* 668 * Byte offset 0x51, CSR Addr 0x54028, Direction=Out 669 * This is a signed integer value. 670 * Write to read critical delay difference from cs 2 to 671 * cs 3. 672 */ 673 int8_t cdd_wr_2_2; /* 674 * Byte offset 0x52, CSR Addr 0x54029, Direction=Out 675 * This is a signed integer value. 676 * Write to read critical delay difference from cs 2 to 677 * cs 2. 678 */ 679 int8_t cdd_wr_2_1; /* 680 * Byte offset 0x53, CSR Addr 0x54029, Direction=Out 681 * This is a signed integer value. 682 * Write to read critical delay difference from cs 2 to 683 * cs 1. 684 */ 685 int8_t cdd_wr_2_0; /* 686 * Byte offset 0x54, CSR Addr 0x5402a, Direction=Out 687 * This is a signed integer value. 688 * Write to read critical delay difference from cs 2 to 689 * cs 0. 690 */ 691 int8_t cdd_wr_1_3; /* 692 * Byte offset 0x55, CSR Addr 0x5402a, Direction=Out 693 * This is a signed integer value. 694 * Write to read critical delay difference from cs 1 to 695 * cs 3. 696 */ 697 int8_t cdd_wr_1_2; /* 698 * Byte offset 0x56, CSR Addr 0x5402b, Direction=Out 699 * This is a signed integer value. 700 * Write to read critical delay difference from cs 1 to 701 * cs 2. 702 */ 703 int8_t cdd_wr_1_1; /* 704 * Byte offset 0x57, CSR Addr 0x5402b, Direction=Out 705 * This is a signed integer value. 706 * Write to read critical delay difference from cs 1 to 707 * cs 1. 708 */ 709 int8_t cdd_wr_1_0; /* 710 * Byte offset 0x58, CSR Addr 0x5402c, Direction=Out 711 * This is a signed integer value. 712 * Write to read critical delay difference from cs 1 to 713 * cs 0. 714 */ 715 int8_t cdd_wr_0_3; /* 716 * Byte offset 0x59, CSR Addr 0x5402c, Direction=Out 717 * This is a signed integer value. 718 * Write to read critical delay difference from cs 0 to 719 * cs 3. 720 */ 721 int8_t cdd_wr_0_2; /* 722 * Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out 723 * This is a signed integer value. 724 * Write to read critical delay difference from cs 0 to 725 * cs 2. 726 */ 727 int8_t cdd_wr_0_1; /* 728 * Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out 729 * This is a signed integer value. 730 * Write to read critical delay difference from cs 0 to 731 * cs 1. 732 */ 733 int8_t cdd_wr_0_0; /* 734 * Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out 735 * This is a signed integer value. 736 * Write to read critical delay difference from cs 0 to 737 * cs 0. 738 */ 739 uint8_t reserved5d; /* 740 * Byte offset 0x5d, CSR Addr 0x5402e, Direction=In 741 * This field is reserved and must be programmed to 0x00, 742 * excepted for DDR4: 743 * By default, if this parameter is 0, the offset applied at 744 * the end of DDR4 RxEn training resulting in the trained 745 * RxEnDly is 3/8 of the RX preamble width; if reserved5D is 746 * non zero, this offset is used instead (in fine step). 747 */ 748 uint16_t mr0; /* 749 * Byte offset 0x5e, CSR Addr 0x5402f, Direction=In 750 * Value of DDR mode register mr0 for all ranks for current 751 * pstate. 752 */ 753 uint16_t mr1; /* 754 * Byte offset 0x60, CSR Addr 0x54030, Direction=In 755 * Value of DDR mode register mr1 for all ranks for current 756 * pstate. 757 */ 758 uint16_t mr2; /* 759 * Byte offset 0x62, CSR Addr 0x54031, Direction=In 760 * Value of DDR mode register mr2 for all ranks for current 761 * pstate. 762 */ 763 uint8_t reserved64; /* 764 * Byte offset 0x64, CSR Addr 0x54032, Direction=In 765 * Reserved64[0] = protect memory reset 766 * 0x0 = dfi_reset_n cannot control CP_MEMRESET_L to 767 * devices after training. (Default value) 768 * 0x1 = dfi_reset_n can control CP_MEMRESET_L to 769 * devices after training. 770 * 771 * Reserved64[7:1] RFU, must be zero 772 */ 773 uint8_t reserved65; /* 774 * Byte offset 0x65, CSR Addr 0x54032, Direction=N/A 775 * This field is reserved and must be programmed to 0x00. 776 */ 777 uint8_t reserved66; /* 778 * Byte offset 0x66, CSR Addr 0x54033, Direction=N/A 779 * This field is reserved and must be programmed to 0x00. 780 */ 781 uint8_t reserved67; /* 782 * Byte offset 0x67, CSR Addr 0x54033, Direction=N/A 783 * This field is reserved and must be programmed to 0x00. 784 */ 785 uint8_t reserved68; /* 786 * Byte offset 0x68, CSR Addr 0x54034, Direction=N/A 787 * This field is reserved and must be programmed to 0x00. 788 */ 789 uint8_t reserved69; /* 790 * Byte offset 0x69, CSR Addr 0x54034, Direction=N/A 791 * This field is reserved and must be programmed to 0x00. 792 */ 793 uint8_t reserved6a; /* 794 * Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A 795 * This field is reserved and must be programmed to 0x00. 796 */ 797 uint8_t reserved6b; /* 798 * Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A 799 * This field is reserved and must be programmed to 0x00. 800 */ 801 uint8_t reserved6c; /* 802 * Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A 803 * This field is reserved and must be programmed to 0x00. 804 */ 805 uint8_t reserved6d; /* 806 * Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A 807 * This field is reserved and must be programmed to 0x00. 808 */ 809 uint8_t reserved6e; /* 810 * Byte offset 0x6e, CSR Addr 0x54037, Direction=N/A 811 * This field is reserved and must be programmed to 0x00. 812 */ 813 uint8_t reserved6f; /* 814 * Byte offset 0x6f, CSR Addr 0x54037, Direction=N/A 815 * This field is reserved and must be programmed to 0x00. 816 */ 817 uint8_t reserved70; /* 818 * Byte offset 0x70, CSR Addr 0x54038, Direction=N/A 819 * This field is reserved and must be programmed to 0x00. 820 */ 821 uint8_t reserved71; /* 822 * Byte offset 0x71, CSR Addr 0x54038, Direction=N/A 823 * This field is reserved and must be programmed to 0x00. 824 */ 825 uint8_t reserved72; /* 826 * Byte offset 0x72, CSR Addr 0x54039, Direction=N/A 827 * This field is reserved and must be programmed to 0x00. 828 */ 829 uint8_t reserved73; /* 830 * Byte offset 0x73, CSR Addr 0x54039, Direction=N/A 831 * This field is reserved and must be programmed to 0x00. 832 */ 833 uint8_t acsmodtctrl0; /* 834 * Byte offset 0x74, CSR Addr 0x5403a, Direction=In 835 * Odt pattern for accesses targeting rank 0. [3:0] is used 836 * for write ODT [7:4] is used for read ODT 837 */ 838 uint8_t acsmodtctrl1; /* 839 * Byte offset 0x75, CSR Addr 0x5403a, Direction=In 840 * Odt pattern for accesses targeting rank 1. [3:0] is used 841 * for write ODT [7:4] is used for read ODT 842 */ 843 uint8_t acsmodtctrl2; /* 844 * Byte offset 0x76, CSR Addr 0x5403b, Direction=In 845 * Odt pattern for accesses targeting rank 2. [3:0] is used 846 * for write ODT [7:4] is used for read ODT 847 */ 848 uint8_t acsmodtctrl3; /* 849 * Byte offset 0x77, CSR Addr 0x5403b, Direction=In 850 * Odt pattern for accesses targeting rank 3. [3:0] is used 851 * for write ODT [7:4] is used for read ODT 852 */ 853 uint8_t acsmodtctrl4; /* 854 * Byte offset 0x78, CSR Addr 0x5403c, Direction=In 855 * This field is reserved and must be programmed to 0x00. 856 */ 857 uint8_t acsmodtctrl5; /* 858 * Byte offset 0x79, CSR Addr 0x5403c, Direction=In 859 * This field is reserved and must be programmed to 0x00. 860 */ 861 uint8_t acsmodtctrl6; /* 862 * Byte offset 0x7a, CSR Addr 0x5403d, Direction=In 863 * This field is reserved and must be programmed to 0x00. 864 */ 865 uint8_t acsmodtctrl7; /* 866 * Byte offset 0x7b, CSR Addr 0x5403d, Direction=In 867 * This field is reserved and must be programmed to 0x00. 868 */ 869 uint8_t reserved7c; /* 870 * Byte offset 0x7c, CSR Addr 0x5403e, Direction=N/A 871 * This field is reserved and must be programmed to 0x00. 872 */ 873 uint8_t reserved7d; /* 874 * Byte offset 0x7d, CSR Addr 0x5403e, Direction=N/A 875 * This field is reserved and must be programmed to 0x00. 876 */ 877 uint8_t reserved7e; /* 878 * Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A 879 * This field is reserved and must be programmed to 0x00. 880 */ 881 uint8_t reserved7f; /* 882 * Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A 883 * This field is reserved and must be programmed to 0x00. 884 */ 885 uint8_t reserved80; /* 886 * Byte offset 0x80, CSR Addr 0x54040, Direction=N/A 887 * This field is reserved and must be programmed to 0x00. 888 */ 889 uint8_t reserved81; /* 890 * Byte offset 0x81, CSR Addr 0x54040, Direction=N/A 891 * This field is reserved and must be programmed to 0x00. 892 */ 893 uint8_t reserved82; /* 894 * Byte offset 0x82, CSR Addr 0x54041, Direction=N/A 895 * This field is reserved and must be programmed to 0x00. 896 */ 897 uint8_t reserved83; /* 898 * Byte offset 0x83, CSR Addr 0x54041, Direction=N/A 899 * This field is reserved and must be programmed to 0x00. 900 */ 901 uint8_t reserved84; /* Byte offset 0x84, CSR Addr 0x54042, Direction=N/A */ 902 uint8_t reserved85; /* Byte offset 0x85, CSR Addr 0x54042, Direction=N/A */ 903 uint8_t reserved86; /* Byte offset 0x86, CSR Addr 0x54043, Direction=N/A */ 904 uint8_t reserved87; /* Byte offset 0x87, CSR Addr 0x54043, Direction=N/A */ 905 uint8_t reserved88; /* Byte offset 0x88, CSR Addr 0x54044, Direction=N/A */ 906 uint8_t reserved89; /* Byte offset 0x89, CSR Addr 0x54044, Direction=N/A */ 907 uint8_t reserved8a; /* Byte offset 0x8a, CSR Addr 0x54045, Direction=N/A */ 908 uint8_t reserved8b; /* Byte offset 0x8b, CSR Addr 0x54045, Direction=N/A */ 909 uint8_t reserved8c; /* Byte offset 0x8c, CSR Addr 0x54046, Direction=N/A */ 910 uint8_t reserved8d; /* Byte offset 0x8d, CSR Addr 0x54046, Direction=N/A */ 911 uint8_t reserved8e; /* Byte offset 0x8e, CSR Addr 0x54047, Direction=N/A */ 912 uint8_t reserved8f; /* Byte offset 0x8f, CSR Addr 0x54047, Direction=N/A */ 913 uint8_t reserved90; /* Byte offset 0x90, CSR Addr 0x54048, Direction=N/A */ 914 uint8_t reserved91; /* Byte offset 0x91, CSR Addr 0x54048, Direction=N/A */ 915 uint8_t reserved92; /* Byte offset 0x92, CSR Addr 0x54049, Direction=N/A */ 916 uint8_t reserved93; /* Byte offset 0x93, CSR Addr 0x54049, Direction=N/A */ 917 uint8_t reserved94; /* Byte offset 0x94, CSR Addr 0x5404a, Direction=N/A */ 918 uint8_t reserved95; /* Byte offset 0x95, CSR Addr 0x5404a, Direction=N/A */ 919 uint8_t reserved96; /* Byte offset 0x96, CSR Addr 0x5404b, Direction=N/A */ 920 uint8_t reserved97; /* Byte offset 0x97, CSR Addr 0x5404b, Direction=N/A */ 921 uint8_t reserved98; /* Byte offset 0x98, CSR Addr 0x5404c, Direction=N/A */ 922 uint8_t reserved99; /* Byte offset 0x99, CSR Addr 0x5404c, Direction=N/A */ 923 uint8_t reserved9a; /* Byte offset 0x9a, CSR Addr 0x5404d, Direction=N/A */ 924 uint8_t reserved9b; /* Byte offset 0x9b, CSR Addr 0x5404d, Direction=N/A */ 925 uint8_t reserved9c; /* Byte offset 0x9c, CSR Addr 0x5404e, Direction=N/A */ 926 uint8_t reserved9d; /* Byte offset 0x9d, CSR Addr 0x5404e, Direction=N/A */ 927 uint8_t reserved9e; /* Byte offset 0x9e, CSR Addr 0x5404f, Direction=N/A */ 928 uint8_t reserved9f; /* Byte offset 0x9f, CSR Addr 0x5404f, Direction=N/A */ 929 uint8_t reserveda0; /* Byte offset 0xa0, CSR Addr 0x54050, Direction=N/A */ 930 uint8_t reserveda1; /* Byte offset 0xa1, CSR Addr 0x54050, Direction=N/A */ 931 uint8_t reserveda2; /* Byte offset 0xa2, CSR Addr 0x54051, Direction=N/A */ 932 uint8_t reserveda3; /* Byte offset 0xa3, CSR Addr 0x54051, Direction=N/A */ 933 } __packed __aligned(2); 934 935 #endif /* MNPMUSRAMMSGBLOCK_DDR3_H */ 936