1/* 2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/* Configuration: 1 cluster with up to 4 CPUs */ 8 9/dts-v1/; 10 11#define AFF 12#define CLUSTER_COUNT 1 13 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include "fvp-defs.dtsi" 16 17/memreserve/ 0x80000000 0x00010000; 18 19/ { 20}; 21 22/ { 23 model = "FVP Foundation"; 24 compatible = "arm,fvp-base", "arm,vexpress"; 25 interrupt-parent = <&gic>; 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { 30 stdout-path = "serial0:115200n8"; 31 }; 32 33 aliases { 34 serial0 = &v2m_serial0; 35 serial1 = &v2m_serial1; 36 serial2 = &v2m_serial2; 37 serial3 = &v2m_serial3; 38 }; 39 40 psci { 41 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 42 method = "smc"; 43 cpu_suspend = <0xc4000001>; 44 cpu_off = <0x84000002>; 45 cpu_on = <0xc4000003>; 46 sys_poweroff = <0x84000008>; 47 sys_reset = <0x84000009>; 48 max-pwr-lvl = <2>; 49 }; 50 51 cpus { 52 #address-cells = <2>; 53 #size-cells = <0>; 54 55 CPU_MAP 56 57 idle-states { 58 entry-method = "arm,psci"; 59 60 CPU_SLEEP_0: cpu-sleep-0 { 61 compatible = "arm,idle-state"; 62 local-timer-stop; 63 arm,psci-suspend-param = <0x0010000>; 64 entry-latency-us = <40>; 65 exit-latency-us = <100>; 66 min-residency-us = <150>; 67 }; 68 69 CLUSTER_SLEEP_0: cluster-sleep-0 { 70 compatible = "arm,idle-state"; 71 local-timer-stop; 72 arm,psci-suspend-param = <0x1010000>; 73 entry-latency-us = <500>; 74 exit-latency-us = <1000>; 75 min-residency-us = <2500>; 76 }; 77 }; 78 79 CPUS 80 81 L2_0: l2-cache0 { 82 compatible = "cache"; 83 }; 84 }; 85 86 memory@80000000 { 87 device_type = "memory"; 88 reg = <0x00000000 0x80000000 0 0x7F000000>, 89 <0x00000008 0x80000000 0 0x80000000>; 90 }; 91 92 gic: interrupt-controller@2f000000 { 93 compatible = "arm,gic-v3"; 94 #interrupt-cells = <3>; 95 #address-cells = <2>; 96 #size-cells = <2>; 97 ranges; 98 interrupt-controller; 99 reg = <0x0 0x2f000000 0 0x10000>, // GICD 100 <0x0 0x2f100000 0 0x200000>, // GICR 101 <0x0 0x2c000000 0 0x2000>, // GICC 102 <0x0 0x2c010000 0 0x2000>, // GICH 103 <0x0 0x2c02f000 0 0x2000>; // GICV 104 interrupts = <1 9 4>; 105 106 its: its@2f020000 { 107 compatible = "arm,gic-v3-its"; 108 msi-controller; 109 reg = <0x0 0x2f020000 0x0 0x20000>; // GITS 110 }; 111 }; 112 113 timer { 114 compatible = "arm,armv8-timer"; 115 interrupts = <GIC_PPI 13 116 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 117 <GIC_PPI 14 118 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 119 <GIC_PPI 11 120 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 121 <GIC_PPI 10 122 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 123 clock-frequency = <100000000>; 124 }; 125 126 timer@2a810000 { 127 compatible = "arm,armv7-timer-mem"; 128 reg = <0x0 0x2a810000 0x0 0x10000>; 129 clock-frequency = <100000000>; 130 #address-cells = <2>; 131 #size-cells = <2>; 132 ranges; 133 frame@2a830000 { 134 frame-number = <1>; 135 interrupts = <0 26 4>; 136 reg = <0x0 0x2a830000 0x0 0x10000>; 137 }; 138 }; 139 140 pmu { 141 compatible = "arm,armv8-pmuv3"; 142 interrupts = <0 60 4>, 143 <0 61 4>, 144 <0 62 4>, 145 <0 63 4>; 146 }; 147 148 smb { 149 compatible = "simple-bus"; 150 151 #address-cells = <2>; 152 #size-cells = <1>; 153 ranges = <0 0 0 0x08000000 0x04000000>, 154 <1 0 0 0x14000000 0x04000000>, 155 <2 0 0 0x18000000 0x04000000>, 156 <3 0 0 0x1c000000 0x04000000>, 157 <4 0 0 0x0c000000 0x04000000>, 158 <5 0 0 0x10000000 0x04000000>; 159 160 #include "fvp-foundation-motherboard.dtsi" 161 }; 162}; 163