1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2021-2024, STMicroelectronics - All Rights Reserved 4 */ 5 6#include <common/tbbr/tbbr_img_def.h> 7#include <dt-bindings/soc/stm32mp15-tzc400.h> 8 9#include <platform_def.h> 10 11#ifndef DDR_SIZE 12#error "DDR_SIZE is not defined" 13#endif 14 15#define DDR_NS_BASE STM32MP_DDR_BASE 16#ifdef AARCH32_SP_OPTEE 17/* OP-TEE secure memory: located at DDR top */ 18#define DDR_SEC_SIZE STM32MP_DDR_S_SIZE 19#define DDR_SEC_BASE (STM32MP_DDR_BASE + (DDR_SIZE - DDR_SEC_SIZE)) 20#define DDR_NS_SIZE (DDR_SEC_BASE - DDR_NS_BASE) 21#else /* !AARCH32_SP_OPTEE */ 22#define DDR_NS_SIZE DDR_SIZE 23#endif /* AARCH32_SP_OPTEE */ 24 25/dts-v1/; 26 27/ { 28 dtb-registry { 29 compatible = "fconf,dyn_cfg-dtb_registry"; 30 31 hw-config { 32 load-address = <0x0 STM32MP_HW_CONFIG_BASE>; 33 max-size = <STM32MP_HW_CONFIG_MAX_SIZE>; 34 id = <HW_CONFIG_ID>; 35 }; 36 37 nt_fw { 38 load-address = <0x0 STM32MP_BL33_BASE>; 39 max-size = <STM32MP_BL33_MAX_SIZE>; 40 id = <BL33_IMAGE_ID>; 41 }; 42 43#ifdef AARCH32_SP_OPTEE 44 tos_fw { 45 load-address = <0x0 STM32MP_OPTEE_BASE>; 46 max-size = <STM32MP_OPTEE_SIZE>; 47 id = <BL32_IMAGE_ID>; 48 }; 49#else 50 tos_fw { 51 load-address = <0x0 STM32MP_BL32_BASE>; 52 max-size = <STM32MP_BL32_SIZE>; 53 id = <BL32_IMAGE_ID>; 54 }; 55 56 tos_fw-config { 57 load-address = <0x0 STM32MP_BL32_DTB_BASE>; 58 max-size = <STM32MP_BL32_DTB_SIZE>; 59 id = <TOS_FW_CONFIG_ID>; 60 }; 61#endif 62 }; 63 64 st-mem-firewall { 65 compatible = "st,mem-firewall"; 66#ifdef AARCH32_SP_OPTEE 67 memory-ranges = < 68 DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR 69 DDR_SEC_BASE DDR_SEC_SIZE TZC_REGION_S_RDWR 0 70 >; 71#else 72 memory-ranges = < 73 DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR>; 74#endif 75 }; 76}; 77