1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) 2023, Protonic Holland - All Rights Reserved 4 * Copyright (C) 2024, STMicroelectronics - All Rights Reserved 5 * Author: David Jander <david@protonic.nl> 6 */ 7/dts-v1/; 8 9#include "stm32mp151.dtsi" 10#include "stm32mp15-pinctrl.dtsi" 11#include "stm32mp15xxad-pinctrl.dtsi" 12#include <dt-bindings/clock/stm32mp1-clksrc.h> 13#include "stm32mp15-ddr3-1x2Gb-1066-binG.dtsi" 14 15/ { 16 model = "Protonic PRTT1A"; 17 compatible = "prt,prtt1a", "st,stm32mp151"; 18 19 chosen { 20 stdout-path = "serial0:115200n8"; 21 }; 22 23 aliases { 24 mmc0 = &sdmmc1; 25 mmc1 = &sdmmc2; 26 serial0 = &uart4; 27 }; 28 29 memory@c0000000 { 30 device_type = "memory"; 31 reg = <0xC0000000 0x10000000>; 32 }; 33}; 34 35&iwdg2 { 36 timeout-sec = <32>; 37 status = "okay"; 38 secure-status = "okay"; 39}; 40 41&qspi { 42 pinctrl-names = "default", "sleep"; 43 pinctrl-0 = <&qspi_clk_pins_a 44 &qspi_bk1_pins_a 45 &qspi_cs1_pins_a>; 46 reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; 47 #address-cells = <1>; 48 #size-cells = <0>; 49 status = "okay"; 50 51 flash@0 { 52 compatible = "spi-nand"; 53 reg = <0>; 54 spi-rx-bus-width = <4>; 55 spi-max-frequency = <104000000>; 56 #address-cells = <1>; 57 #size-cells = <1>; 58 }; 59}; 60 61&qspi_bk1_pins_a { 62 pins { 63 bias-pull-up; 64 drive-push-pull; 65 slew-rate = <1>; 66 }; 67}; 68 69&rcc { 70 st,clksrc = < 71 CLK_MPU_PLL1P 72 CLK_AXI_PLL2P 73 CLK_MCU_PLL3P 74 CLK_PLL12_HSE 75 CLK_PLL3_HSE 76 CLK_PLL4_HSE 77 CLK_RTC_LSI 78 CLK_MCO1_DISABLED 79 CLK_MCO2_DISABLED 80 >; 81 82 st,clkdiv = < 83 1 /*MPU*/ 84 0 /*AXI*/ 85 0 /*MCU*/ 86 1 /*APB1*/ 87 1 /*APB2*/ 88 1 /*APB3*/ 89 1 /*APB4*/ 90 2 /*APB5*/ 91 23 /*RTC*/ 92 0 /*MCO1*/ 93 0 /*MCO2*/ 94 >; 95 96 st,pkcs = < 97 CLK_CKPER_HSE 98 CLK_FMC_ACLK 99 CLK_QSPI_ACLK 100 CLK_ETH_DISABLED 101 CLK_SDMMC12_PLL4P 102 CLK_DSI_DSIPLL 103 CLK_STGEN_HSE 104 CLK_USBPHY_HSE 105 CLK_SPI2S1_PLL3Q 106 CLK_SPI2S23_PLL3Q 107 CLK_SPI45_HSI 108 CLK_SPI6_HSI 109 CLK_I2C46_HSI 110 CLK_SDMMC3_PLL4P 111 CLK_USBO_USBPHY 112 CLK_ADC_CKPER 113 CLK_CEC_LSI 114 CLK_I2C12_HSI 115 CLK_I2C35_HSI 116 CLK_UART1_HSI 117 CLK_UART24_HSI 118 CLK_UART35_HSI 119 CLK_UART6_HSI 120 CLK_UART78_HSI 121 CLK_SPDIF_PLL4P 122 CLK_FDCAN_PLL4R 123 CLK_SAI1_PLL3Q 124 CLK_SAI2_PLL3Q 125 CLK_SAI3_PLL3Q 126 CLK_SAI4_PLL3Q 127 CLK_RNG1_CSI 128 CLK_RNG2_LSI 129 CLK_LPTIM1_PCLK1 130 CLK_LPTIM23_PCLK3 131 CLK_LPTIM45_LSI 132 >; 133 134 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 135 pll1: st,pll@0 { 136 compatible = "st,stm32mp1-pll"; 137 reg = <0>; 138 cfg = <2 80 0 0 0 PQR(1,0,0)>; 139 frac = <0x800>; 140 }; 141 142 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 143 pll2: st,pll@1 { 144 compatible = "st,stm32mp1-pll"; 145 reg = <1>; 146 cfg = <2 65 1 0 0 PQR(1,1,1)>; 147 frac = <0x1400>; 148 }; 149 150 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 151 pll3: st,pll@2 { 152 compatible = "st,stm32mp1-pll"; 153 reg = <2>; 154 cfg = <1 33 1 16 36 PQR(1,1,1)>; 155 frac = <0x1a04>; 156 }; 157 158 /* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */ 159 pll4: st,pll@3 { 160 compatible = "st,stm32mp1-pll"; 161 reg = <3>; 162 cfg = <1 39 3 11 4 PQR(1,1,1)>; 163 }; 164}; 165 166&rng1 { 167 status = "okay"; 168}; 169 170&rtc { 171 status = "okay"; 172}; 173 174&sdmmc1 { 175 pinctrl-names = "default"; 176 pinctrl-0 = <&sdmmc1_b4_pins_a>; 177 bus-width = <4>; 178 status = "okay"; 179}; 180 181&sdmmc1_b4_pins_a { 182 pins1 { 183 bias-pull-up; 184 }; 185 pins2 { 186 bias-pull-up; 187 }; 188}; 189 190/* NOTE: Although the PRTT1A does not have an eMMC, we declare it 191 * anyway, in order to be able to use the same binary for the 192 * PRTT1C also. All involved pins are N.C. on PRTT1A/S for that 193 * reason, so it should do no harm. All inputs configured with 194 * pull-ups to avoid floating inputs. */ 195&sdmmc2 { 196 pinctrl-names = "default"; 197 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; 198 bus-width = <8>; 199 status = "okay"; 200}; 201 202&sdmmc2_b4_pins_a { 203 pins1 { 204 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 205 <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */ 206 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 207 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ 208 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 209 }; 210}; 211 212&sdmmc2_d47_pins_a { 213 pins { 214 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 215 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 216 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ 217 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ 218 }; 219}; 220 221&uart4 { 222 pinctrl-names = "default"; 223 pinctrl-0 = <&uart4_pins_a>; 224 status = "okay"; 225}; 226 227&uart4_pins_a { 228 pins1 { 229 pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */ 230 bias-disable; 231 drive-push-pull; 232 slew-rate = <0>; 233 }; 234 pins2 { 235 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 236 bias-pull-up; 237 }; 238}; 239