1/* 2 * Copyright (C) 2019-2024, STMicroelectronics. All Rights Reserved. 3 * Copyright (C) 2021, Grzegorz Szymaszek. 4 * 5 * SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 6 */ 7 8#include "stm32mp157.dtsi" 9#include "stm32mp15xc.dtsi" 10#include "stm32mp15-pinctrl.dtsi" 11#include "stm32mp15xxac-pinctrl.dtsi" 12#include <dt-bindings/clock/stm32mp1-clksrc.h> 13#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi" 14 15/ { 16 memory@c0000000 { 17 device_type = "memory"; 18 reg = <0xc0000000 0x20000000>; 19 }; 20 21 vin: vin { 22 compatible = "regulator-fixed"; 23 regulator-name = "vin"; 24 regulator-min-microvolt = <5000000>; 25 regulator-max-microvolt = <5000000>; 26 regulator-always-on; 27 }; 28}; 29 30&bsec { 31 board_id: board-id@ec { 32 reg = <0xec 0x4>; 33 st,non-secure-otp; 34 }; 35}; 36 37&clk_hse { 38 st,digbypass; 39}; 40 41&cpu0 { 42 cpu-supply = <&vddcore>; 43}; 44 45&cpu1 { 46 cpu-supply = <&vddcore>; 47}; 48 49&cryp1 { 50 status = "okay"; 51}; 52 53&hash1 { 54 status = "okay"; 55}; 56 57&i2c2 { 58 pinctrl-names = "default"; 59 pinctrl-0 = <&i2c2_pins_a>; 60 clock-frequency = <400000>; 61 i2c-scl-rising-time-ns = <185>; 62 i2c-scl-falling-time-ns = <20>; 63 status = "okay"; 64 65 pmic: stpmic@33 { 66 compatible = "st,stpmic1"; 67 reg = <0x33>; 68 interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; 69 interrupt-controller; 70 #interrupt-cells = <2>; 71 status = "okay"; 72 73 regulators { 74 compatible = "st,stpmic1-regulators"; 75 buck1-supply = <&vin>; 76 buck2-supply = <&vin>; 77 buck3-supply = <&vin>; 78 buck4-supply = <&vin>; 79 ldo1-supply = <&v3v3>; 80 ldo2-supply = <&vin>; 81 ldo3-supply = <&vdd_ddr>; 82 ldo4-supply = <&vin>; 83 ldo5-supply = <&vin>; 84 ldo6-supply = <&v3v3>; 85 vref_ddr-supply = <&vin>; 86 boost-supply = <&vin>; 87 pwr_sw1-supply = <&bst_out>; 88 pwr_sw2-supply = <&bst_out>; 89 90 vddcore: buck1 { 91 regulator-name = "vddcore"; 92 regulator-min-microvolt = <1200000>; 93 regulator-max-microvolt = <1350000>; 94 regulator-always-on; 95 regulator-initial-mode = <0>; 96 regulator-over-current-protection; 97 }; 98 99 vdd_ddr: buck2 { 100 regulator-name = "vdd_ddr"; 101 regulator-min-microvolt = <1350000>; 102 regulator-max-microvolt = <1350000>; 103 regulator-always-on; 104 regulator-initial-mode = <0>; 105 regulator-over-current-protection; 106 }; 107 108 vdd: buck3 { 109 regulator-name = "vdd"; 110 regulator-min-microvolt = <3300000>; 111 regulator-max-microvolt = <3300000>; 112 regulator-always-on; 113 st,mask-reset; 114 regulator-initial-mode = <0>; 115 regulator-over-current-protection; 116 }; 117 118 v3v3: buck4 { 119 regulator-name = "v3v3"; 120 regulator-min-microvolt = <3300000>; 121 regulator-max-microvolt = <3300000>; 122 regulator-always-on; 123 regulator-over-current-protection; 124 regulator-initial-mode = <0>; 125 }; 126 127 v1v8_audio: ldo1 { 128 regulator-name = "v1v8_audio"; 129 regulator-min-microvolt = <1800000>; 130 regulator-max-microvolt = <1800000>; 131 regulator-always-on; 132 }; 133 134 v3v3_hdmi: ldo2 { 135 regulator-name = "v3v3_hdmi"; 136 regulator-min-microvolt = <3300000>; 137 regulator-max-microvolt = <3300000>; 138 regulator-always-on; 139 }; 140 141 vtt_ddr: ldo3 { 142 regulator-name = "vtt_ddr"; 143 regulator-always-on; 144 regulator-over-current-protection; 145 st,regulator-sink-source; 146 }; 147 148 vdd_usb: ldo4 { 149 regulator-name = "vdd_usb"; 150 regulator-min-microvolt = <3300000>; 151 regulator-max-microvolt = <3300000>; 152 regulator-always-on; 153 }; 154 155 vdda: ldo5 { 156 regulator-name = "vdda"; 157 regulator-min-microvolt = <2900000>; 158 regulator-max-microvolt = <2900000>; 159 regulator-boot-on; 160 }; 161 162 v1v2_hdmi: ldo6 { 163 regulator-name = "v1v2_hdmi"; 164 regulator-min-microvolt = <1200000>; 165 regulator-max-microvolt = <1200000>; 166 regulator-always-on; 167 }; 168 169 vref_ddr: vref_ddr { 170 regulator-name = "vref_ddr"; 171 regulator-always-on; 172 }; 173 174 bst_out: boost { 175 regulator-name = "bst_out"; 176 }; 177 178 vbus_otg: pwr_sw1 { 179 regulator-name = "vbus_otg"; 180 }; 181 182 vbus_sw: pwr_sw2 { 183 regulator-name = "vbus_sw"; 184 regulator-active-discharge = <1>; 185 }; 186 }; 187 188 pmic_watchdog: watchdog { 189 compatible = "st,stpmic1-wdt"; 190 status = "disabled"; 191 }; 192 }; 193}; 194 195&iwdg2 { 196 timeout-sec = <32>; 197 status = "okay"; 198}; 199 200&pwr_regulators { 201 vdd-supply = <&vdd>; 202 vdd_3v3_usbfs-supply = <&vdd_usb>; 203}; 204 205&rcc { 206 st,clksrc = < 207 CLK_MPU_PLL1P 208 CLK_AXI_PLL2P 209 CLK_MCU_PLL3P 210 CLK_RTC_LSE 211 CLK_MCO1_DISABLED 212 CLK_MCO2_DISABLED 213 CLK_CKPER_HSE 214 CLK_FMC_ACLK 215 CLK_QSPI_ACLK 216 CLK_ETH_PLL4P 217 CLK_SDMMC12_PLL4P 218 CLK_DSI_DSIPLL 219 CLK_STGEN_HSE 220 CLK_USBPHY_HSE 221 CLK_SPI2S1_PLL3Q 222 CLK_SPI2S23_PLL3Q 223 CLK_SPI45_HSI 224 CLK_SPI6_HSI 225 CLK_I2C46_HSI 226 CLK_SDMMC3_PLL4P 227 CLK_USBO_USBPHY 228 CLK_ADC_CKPER 229 CLK_CEC_LSE 230 CLK_I2C12_HSI 231 CLK_I2C35_HSI 232 CLK_UART1_HSI 233 CLK_UART24_HSI 234 CLK_UART35_HSI 235 CLK_UART6_HSI 236 CLK_UART78_HSI 237 CLK_SPDIF_PLL4P 238 CLK_FDCAN_PLL4R 239 CLK_SAI1_PLL3Q 240 CLK_SAI2_PLL3Q 241 CLK_SAI3_PLL3Q 242 CLK_SAI4_PLL3Q 243 CLK_RNG1_CSI 244 CLK_RNG2_LSI 245 CLK_LPTIM1_PCLK1 246 CLK_LPTIM23_PCLK3 247 CLK_LPTIM45_LSE 248 >; 249 250 st,clkdiv = < 251 DIV(DIV_MPU, 1) 252 DIV(DIV_AXI, 0) 253 DIV(DIV_MCU, 0) 254 DIV(DIV_APB1, 1) 255 DIV(DIV_APB2, 1) 256 DIV(DIV_APB3, 1) 257 DIV(DIV_APB4, 1) 258 DIV(DIV_APB5, 2) 259 DIV(DIV_RTC, 23) 260 DIV(DIV_MCO1, 0) 261 DIV(DIV_MCO2, 0) 262 >; 263 264 st,pll_vco { 265 pll2_vco_1066Mhz: pll2-vco-1066Mhz { 266 src = <CLK_PLL12_HSE>; 267 divmn = <2 65>; 268 frac = <0x1400>; 269 }; 270 271 pll3_vco_417Mhz: pll3-vco-417Mhz { 272 src = <CLK_PLL3_HSE>; 273 divmn = <1 33>; 274 frac = <0x1a04>; 275 }; 276 277 pll4_vco_594Mhz: pll4-vco-594Mhz { 278 src = <CLK_PLL4_HSE>; 279 divmn = <3 98>; 280 }; 281 }; 282 283 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 284 pll2: st,pll@1 { 285 compatible = "st,stm32mp1-pll"; 286 reg = <1>; 287 288 st,pll = <&pll2_cfg1>; 289 290 pll2_cfg1: pll2_cfg1 { 291 st,pll_vco = <&pll2_vco_1066Mhz>; 292 st,pll_div_pqr = <1 0 0>; 293 }; 294 }; 295 296 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 297 pll3: st,pll@2 { 298 compatible = "st,stm32mp1-pll"; 299 reg = <2>; 300 301 st,pll = <&pll3_cfg1>; 302 303 pll3_cfg1: pll3_cfg1 { 304 st,pll_vco = <&pll3_vco_417Mhz>; 305 st,pll_div_pqr = <1 16 36>; 306 }; 307 }; 308 309 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ 310 pll4: st,pll@3 { 311 compatible = "st,stm32mp1-pll"; 312 reg = <3>; 313 314 st,pll = <&pll4_cfg1>; 315 316 pll4_cfg1: pll4_cfg1 { 317 st,pll_vco = <&pll4_vco_594Mhz>; 318 st,pll_div_pqr = <5 7 7>; 319 }; 320 }; 321}; 322 323&rng1 { 324 status = "okay"; 325}; 326 327&rtc { 328 status = "okay"; 329}; 330 331&sdmmc2 { 332 pinctrl-names = "default"; 333 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_d>; 334 non-removable; 335 no-sd; 336 no-sdio; 337 st,neg-edge; 338 bus-width = <8>; 339 vmmc-supply = <&v3v3>; 340 vqmmc-supply = <&vdd>; 341 mmc-ddr-3_3v; 342 status = "okay"; 343}; 344