1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* 3 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved 4 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 5 * Copyright (C) 2020 Marek Vasut <marex@denx.de> 6 * Copyright (C) 2022 DH electronics GmbH 7 * Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved 8 */ 9 10#include "stm32mp15-pinctrl.dtsi" 11#include "stm32mp15xxaa-pinctrl.dtsi" 12#include <dt-bindings/clock/stm32mp1-clksrc.h> 13#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi" 14 15/ { 16 memory@c0000000 { 17 device_type = "memory"; 18 reg = <0xc0000000 0x40000000>; 19 }; 20}; 21 22&cpu0 { 23 cpu-supply = <&vddcore>; 24}; 25 26&cpu1 { 27 cpu-supply = <&vddcore>; 28}; 29 30&hash1 { 31 status = "okay"; 32}; 33 34&i2c4 { 35 pinctrl-names = "default"; 36 pinctrl-0 = <&i2c4_pins_a>; 37 i2c-scl-rising-time-ns = <185>; 38 i2c-scl-falling-time-ns = <20>; 39 status = "okay"; 40 41 pmic: stpmic@33 { 42 compatible = "st,stpmic1"; 43 reg = <0x33>; 44 interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; 45 interrupt-controller; 46 #interrupt-cells = <2>; 47 status = "okay"; 48 49 regulators { 50 compatible = "st,stpmic1-regulators"; 51 ldo1-supply = <&v3v3>; 52 ldo2-supply = <&v3v3>; 53 ldo3-supply = <&vdd_ddr>; 54 ldo5-supply = <&v3v3>; 55 ldo6-supply = <&v3v3>; 56 pwr_sw1-supply = <&bst_out>; 57 pwr_sw2-supply = <&bst_out>; 58 59 vddcore: buck1 { 60 regulator-name = "vddcore"; 61 regulator-min-microvolt = <1200000>; 62 regulator-max-microvolt = <1350000>; 63 regulator-always-on; 64 regulator-initial-mode = <0>; 65 regulator-over-current-protection; 66 }; 67 68 vdd_ddr: buck2 { 69 regulator-name = "vdd_ddr"; 70 regulator-min-microvolt = <1350000>; 71 regulator-max-microvolt = <1350000>; 72 regulator-always-on; 73 regulator-initial-mode = <0>; 74 regulator-over-current-protection; 75 }; 76 77 vdd: buck3 { 78 regulator-name = "vdd"; 79 regulator-min-microvolt = <3300000>; 80 regulator-max-microvolt = <3300000>; 81 regulator-always-on; 82 regulator-initial-mode = <0>; 83 regulator-over-current-protection; 84 }; 85 86 v3v3: buck4 { 87 regulator-name = "v3v3"; 88 regulator-min-microvolt = <3300000>; 89 regulator-max-microvolt = <3300000>; 90 regulator-always-on; 91 regulator-over-current-protection; 92 regulator-initial-mode = <0>; 93 }; 94 95 vdda: ldo1 { 96 regulator-name = "vdda"; 97 regulator-min-microvolt = <2900000>; 98 regulator-max-microvolt = <2900000>; 99 }; 100 101 v2v8: ldo2 { 102 regulator-name = "v2v8"; 103 regulator-min-microvolt = <2800000>; 104 regulator-max-microvolt = <2800000>; 105 }; 106 107 vtt_ddr: ldo3 { 108 regulator-name = "vtt_ddr"; 109 regulator-always-on; 110 regulator-over-current-protection; 111 st,regulator-sink-source; 112 }; 113 114 vdd_usb: ldo4 { 115 regulator-name = "vdd_usb"; 116 regulator-min-microvolt = <3300000>; 117 regulator-max-microvolt = <3300000>; 118 }; 119 120 vdd_sd: ldo5 { 121 regulator-name = "vdd_sd"; 122 regulator-min-microvolt = <2900000>; 123 regulator-max-microvolt = <2900000>; 124 regulator-boot-on; 125 }; 126 127 v1v8: ldo6 { 128 regulator-name = "v1v8"; 129 regulator-min-microvolt = <1800000>; 130 regulator-max-microvolt = <1800000>; 131 regulator-enable-ramp-delay = <300000>; 132 }; 133 134 vref_ddr: vref_ddr { 135 regulator-name = "vref_ddr"; 136 regulator-always-on; 137 }; 138 139 bst_out: boost { 140 regulator-name = "bst_out"; 141 }; 142 143 vbus_otg: pwr_sw1 { 144 regulator-name = "vbus_otg"; 145 regulator-active-discharge = <1>; 146 }; 147 148 vbus_sw: pwr_sw2 { 149 regulator-name = "vbus_sw"; 150 regulator-active-discharge = <1>; 151 }; 152 }; 153 }; 154}; 155 156&iwdg2 { 157 timeout-sec = <32>; 158 status = "okay"; 159}; 160 161&pwr_regulators { 162 vdd-supply = <&vdd>; 163 vdd_3v3_usbfs-supply = <&vdd_usb>; 164}; 165 166&qspi { 167 pinctrl-names = "default"; 168 pinctrl-0 = <&qspi_clk_pins_a 169 &qspi_bk1_pins_a 170 &qspi_cs1_pins_a>; 171 reg = <0x58003000 0x1000>, <0x70000000 0x200000>; 172 #address-cells = <1>; 173 #size-cells = <0>; 174 status = "okay"; 175 176 flash0: flash@0 { 177 compatible = "jedec,spi-nor"; 178 reg = <0>; 179 spi-rx-bus-width = <4>; 180 spi-max-frequency = <50000000>; 181 #address-cells = <1>; 182 #size-cells = <1>; 183 }; 184}; 185 186&rcc { 187 st,clksrc = < 188 CLK_MPU_PLL1P 189 CLK_AXI_PLL2P 190 CLK_MCU_PLL3P 191 CLK_RTC_LSE 192 CLK_MCO1_DISABLED 193 CLK_MCO2_DISABLED 194 CLK_CKPER_HSE 195 CLK_FMC_ACLK 196 CLK_QSPI_ACLK 197 CLK_ETH_DISABLED 198 CLK_SDMMC12_PLL4P 199 CLK_DSI_DSIPLL 200 CLK_STGEN_HSE 201 CLK_USBPHY_HSE 202 CLK_SPI2S1_PLL3Q 203 CLK_SPI2S23_PLL3Q 204 CLK_SPI45_HSI 205 CLK_SPI6_HSI 206 CLK_I2C46_HSI 207 CLK_SDMMC3_PLL4P 208 CLK_USBO_USBPHY 209 CLK_ADC_CKPER 210 CLK_CEC_LSE 211 CLK_I2C12_HSI 212 CLK_I2C35_HSI 213 CLK_UART1_HSI 214 CLK_UART24_HSI 215 CLK_UART35_HSI 216 CLK_UART6_HSI 217 CLK_UART78_HSI 218 CLK_SPDIF_PLL4P 219 CLK_FDCAN_PLL4R 220 CLK_SAI1_PLL3Q 221 CLK_SAI2_PLL3Q 222 CLK_SAI3_PLL3Q 223 CLK_SAI4_PLL3Q 224 CLK_RNG1_CSI 225 CLK_RNG2_LSI 226 CLK_LPTIM1_PCLK1 227 CLK_LPTIM23_PCLK3 228 CLK_LPTIM45_LSE 229 >; 230 231 st,clkdiv = < 232 DIV(DIV_MPU, 1) 233 DIV(DIV_AXI, 0) 234 DIV(DIV_MCU, 0) 235 DIV(DIV_APB1, 1) 236 DIV(DIV_APB2, 1) 237 DIV(DIV_APB3, 1) 238 DIV(DIV_APB4, 1) 239 DIV(DIV_APB5, 2) 240 DIV(DIV_RTC, 23) 241 DIV(DIV_MCO1, 0) 242 DIV(DIV_MCO2, 0) 243 >; 244 245 st,pll_vco { 246 pll2_vco_1066Mhz: pll2-vco-1066Mhz { 247 src = <CLK_PLL12_HSE>; 248 divmn = <2 65>; 249 frac = <0x1400>; 250 }; 251 252 pll3_vco_417Mhz: pll3-vco-417Mhz { 253 src = <CLK_PLL3_HSE>; 254 divmn = <1 33>; 255 frac = <0x1a04>; 256 }; 257 258 pll4_vco_594Mhz: pll4-vco-594Mhz { 259 src = <CLK_PLL4_HSE>; 260 divmn = <3 98>; 261 }; 262 }; 263 264 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 265 pll2: st,pll@1 { 266 compatible = "st,stm32mp1-pll"; 267 reg = <1>; 268 269 st,pll = <&pll2_cfg1>; 270 271 pll2_cfg1: pll2_cfg1 { 272 st,pll_vco = <&pll2_vco_1066Mhz>; 273 st,pll_div_pqr = <1 0 0>; 274 }; 275 }; 276 277 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 278 pll3: st,pll@2 { 279 compatible = "st,stm32mp1-pll"; 280 reg = <2>; 281 282 st,pll = <&pll3_cfg1>; 283 284 pll3_cfg1: pll3_cfg1 { 285 st,pll_vco = <&pll3_vco_417Mhz>; 286 st,pll_div_pqr = <1 16 36>; 287 }; 288 }; 289 290 /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */ /* @TOCHECK */ 291 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ 292 pll4: st,pll@3 { 293 compatible = "st,stm32mp1-pll"; 294 reg = <3>; 295 296 st,pll = <&pll4_cfg1>; 297 298 pll4_cfg1: pll4_cfg1 { 299 st,pll_vco = <&pll4_vco_594Mhz>; 300 st,pll_div_pqr = <5 7 7>; 301 }; 302 }; 303}; 304 305&rng1 { 306 status = "okay"; 307}; 308 309&rtc { 310 status = "okay"; 311}; 312