1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#define LIT_CAPACITY 239 8#define MID_CAPACITY 686 9#define BIG_CAPACITY 1024 10 11#define MHU_TX_COMPAT "arm,mhuv3" 12#define MHU_TX_INT_NAME "" 13 14#define MHU_RX_COMPAT "arm,mhuv3" 15#define MHU_OFFSET 0x10000 16#define MHU_MBOX_CELLS 3 17#define MHU_RX_INT_NUM 300 18#define MHU_RX_INT_NAME "combined" 19 20#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */ 21#define UARTCLK_FREQ 3750000 22 23#if TARGET_FLAVOUR_FVP 24#define DPU_ADDR 4000000000 25#define DPU_IRQ 579 26#elif TARGET_FLAVOUR_FPGA 27#define DPU_ADDR 2cc00000 28#define DPU_IRQ 69 29#endif 30#include "tc-base.dtsi" 31 32/ { 33 cpus { 34 CPU2:cpu@200 { 35 clocks = <&scmi_dvfs 1>; 36 capacity-dmips-mhz = <MID_CAPACITY>; 37 }; 38 39 CPU3:cpu@300 { 40 clocks = <&scmi_dvfs 1>; 41 capacity-dmips-mhz = <MID_CAPACITY>; 42 }; 43 44 CPU6:cpu@600 { 45 clocks = <&scmi_dvfs 2>; 46 capacity-dmips-mhz = <BIG_CAPACITY>; 47 }; 48 49 CPU7:cpu@700 { 50 clocks = <&scmi_dvfs 2>; 51 capacity-dmips-mhz = <BIG_CAPACITY>; 52 }; 53 }; 54 55 gic: interrupt-controller@GIC_CTRL_ADDR { 56 ppi-partitions { 57 ppi_partition_little: interrupt-partition-0 { 58 affinity = <&CPU0>, <&CPU1>; 59 }; 60 61 ppi_partition_mid: interrupt-partition-1 { 62 affinity = <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>; 63 }; 64 65 ppi_partition_big: interrupt-partition-2 { 66 affinity = <&CPU6>, <&CPU7>; 67 }; 68 }; 69 }; 70 71 sram: sram@6000000 { 72 cpu_scp_scmi_p2a: scp-shmem@80 { 73 compatible = "arm,scmi-shmem"; 74 reg = <0x80 0x80>; 75 }; 76 }; 77 78 firmware { 79 scmi { 80 mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>; 81 shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>; 82 }; 83 }; 84}; 85