1 /*
2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef ARCH_HELPERS_H
8 #define ARCH_HELPERS_H
9
10 #include <cdefs.h>
11 #include <stdbool.h>
12 #include <stdint.h>
13 #include <string.h>
14
15 #include <arch.h>
16 #include <lib/extensions/sysreg128.h>
17
18 /**********************************************************************
19 * Macros which create inline functions to read or write CPU system
20 * registers
21 *********************************************************************/
22
23 #define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
24 static inline u_register_t read_ ## _name(void) \
25 { \
26 u_register_t v; \
27 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \
28 return v; \
29 }
30
31 #define _DEFINE_SYSREG_READ_FUNC_NV(_name, _reg_name) \
32 static inline u_register_t read_ ## _name(void) \
33 { \
34 u_register_t v; \
35 __asm__ ("mrs %0, " #_reg_name : "=r" (v)); \
36 return v; \
37 }
38
39 #define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
40 static inline void write_ ## _name(u_register_t v) \
41 { \
42 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \
43 }
44
45 #define SYSREG_WRITE_CONST(reg_name, v) \
46 __asm__ volatile ("msr " #reg_name ", %0" : : "i" (v))
47
48 /* Define read function for system register */
49 #define DEFINE_SYSREG_READ_FUNC(_name) \
50 _DEFINE_SYSREG_READ_FUNC(_name, _name)
51
52 /* Define read & write function for system register */
53 #define DEFINE_SYSREG_RW_FUNCS(_name) \
54 _DEFINE_SYSREG_READ_FUNC(_name, _name) \
55 _DEFINE_SYSREG_WRITE_FUNC(_name, _name)
56
57 /* Define read & write function for renamed system register */
58 #define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \
59 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
60 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
61
62 /* Define read function for renamed system register */
63 #define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \
64 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name)
65
66 /* Define write function for renamed system register */
67 #define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \
68 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
69
70 /* Define read function for ID register (w/o volatile qualifier) */
71 #define DEFINE_IDREG_READ_FUNC(_name) \
72 _DEFINE_SYSREG_READ_FUNC_NV(_name, _name)
73
74 /* Define read function for renamed ID register (w/o volatile qualifier) */
75 #define DEFINE_RENAME_IDREG_READ_FUNC(_name, _reg_name) \
76 _DEFINE_SYSREG_READ_FUNC_NV(_name, _reg_name)
77
78 /**********************************************************************
79 * Macros to create inline functions for system instructions
80 *********************************************************************/
81
82 /* Define function for simple system instruction */
83 #define DEFINE_SYSOP_FUNC(_op) \
84 static inline void _op(void) \
85 { \
86 __asm__ (#_op); \
87 }
88
89 /* Define function for system instruction with register parameter */
90 #define DEFINE_SYSOP_PARAM_FUNC(_op) \
91 static inline void _op(uint64_t v) \
92 { \
93 __asm__ (#_op " %0" : : "r" (v)); \
94 }
95
96 /* Define function for system instruction with type specifier */
97 #define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
98 static inline void _op ## _type(void) \
99 { \
100 __asm__ (#_op " " #_type : : : "memory"); \
101 }
102
103 /* Define function for system instruction with register parameter */
104 #define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \
105 static inline void _op ## _type(uint64_t v) \
106 { \
107 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \
108 }
109
110 /*******************************************************************************
111 * TLB maintenance accessor prototypes
112 ******************************************************************************/
113
114 #if ERRATA_A57_813419 || ERRATA_A76_1286807
115 /*
116 * Define function for TLBI instruction with type specifier that implements
117 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of
118 * Cortex-A76.
119 */
120 #define DEFINE_TLBIOP_ERRATA_TYPE_FUNC(_type)\
121 static inline void tlbi ## _type(void) \
122 { \
123 __asm__("tlbi " #_type "\n" \
124 "dsb ish\n" \
125 "tlbi " #_type); \
126 }
127
128 /*
129 * Define function for TLBI instruction with register parameter that implements
130 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of
131 * Cortex-A76.
132 */
133 #define DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(_type) \
134 static inline void tlbi ## _type(uint64_t v) \
135 { \
136 __asm__("tlbi " #_type ", %0\n" \
137 "dsb ish\n" \
138 "tlbi " #_type ", %0" : : "r" (v)); \
139 }
140 #endif /* ERRATA_A57_813419 */
141
142 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
143 /*
144 * Define function for DC instruction with register parameter that enables
145 * the workaround for errata 819472, 824069 and 827319 of Cortex-A53.
146 */
147 #define DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(_name, _type) \
148 static inline void dc ## _name(uint64_t v) \
149 { \
150 __asm__("dc " #_type ", %0" : : "r" (v)); \
151 }
152 #endif /* ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 */
153
154 #if ERRATA_A57_813419
155 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
156 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
157 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
158 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
159 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3)
160 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is)
161 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
162 #elif ERRATA_A76_1286807
163 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1)
164 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1is)
165 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2)
166 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2is)
167 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3)
168 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is)
169 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(vmalle1)
170 #else
171 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
172 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
173 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
174 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
175 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3)
176 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is)
177 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
178 #endif
179
180 #if ERRATA_A57_813419
181 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
182 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
183 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
184 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
185 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is)
186 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is)
187 #elif ERRATA_A76_1286807
188 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaae1is)
189 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaale1is)
190 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae2is)
191 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale2is)
192 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is)
193 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is)
194 #else
195 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
196 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
197 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
198 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
199 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is)
200 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is)
201 #endif
202
203 /*******************************************************************************
204 * Cache maintenance accessor prototypes
205 ******************************************************************************/
206 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw)
207 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw)
208 #if ERRATA_A53_827319
209 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(csw, cisw)
210 #else
211 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw)
212 #endif
213 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
214 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvac, civac)
215 #else
216 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac)
217 #endif
218 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac)
219 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac)
220 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
221 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvau, civac)
222 #else
223 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau)
224 #endif
225 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva)
226
227 /*******************************************************************************
228 * Address translation accessor prototypes
229 ******************************************************************************/
230 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r)
231 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w)
232 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r)
233 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w)
234 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r)
235 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r)
236 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r)
237
238 /*******************************************************************************
239 * Strip Pointer Authentication Code
240 ******************************************************************************/
241 DEFINE_SYSOP_PARAM_FUNC(xpaci)
242
243 void flush_dcache_range(uintptr_t addr, size_t size);
244 void flush_dcache_to_popa_range(uintptr_t addr, size_t size);
245 void flush_dcache_to_popa_range_mte2(uintptr_t addr, size_t size);
246 void clean_dcache_range(uintptr_t addr, size_t size);
247 void inv_dcache_range(uintptr_t addr, size_t size);
248 bool is_dcache_enabled(void);
249
250 void dcsw_op_louis(u_register_t op_type);
251 void dcsw_op_all(u_register_t op_type);
252
253 void disable_mmu_el1(void);
254 void disable_mmu_el3(void);
255 void disable_mpu_el2(void);
256 void disable_mmu_icache_el1(void);
257 void disable_mmu_icache_el3(void);
258 void disable_mpu_icache_el2(void);
259
260 /*******************************************************************************
261 * Misc. accessor prototypes
262 ******************************************************************************/
263
264 #define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val)
265 #define write_daifset(val) SYSREG_WRITE_CONST(daifset, val)
266
267 #if ENABLE_FEAT_D128
268 DECLARE_SYSREG128_RW_FUNCS(par_el1)
269 #else
270 DEFINE_SYSREG_RW_FUNCS(par_el1)
271 #endif
272
DEFINE_IDREG_READ_FUNC(id_pfr1_el1)273 DEFINE_IDREG_READ_FUNC(id_pfr1_el1)
274 DEFINE_IDREG_READ_FUNC(id_aa64isar0_el1)
275 DEFINE_IDREG_READ_FUNC(id_aa64isar1_el1)
276 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64isar2_el1, ID_AA64ISAR2_EL1)
277 DEFINE_IDREG_READ_FUNC(id_aa64pfr0_el1)
278 DEFINE_IDREG_READ_FUNC(id_aa64pfr1_el1)
279 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64pfr2_el1, ID_AA64PFR2_EL1)
280 DEFINE_IDREG_READ_FUNC(id_aa64dfr0_el1)
281 DEFINE_IDREG_READ_FUNC(id_aa64dfr1_el1)
282 DEFINE_IDREG_READ_FUNC(id_afr0_el1)
283 DEFINE_SYSREG_READ_FUNC(CurrentEl)
284 DEFINE_SYSREG_READ_FUNC(ctr_el0)
285 DEFINE_SYSREG_RW_FUNCS(daif)
286 DEFINE_SYSREG_RW_FUNCS(spsr_el1)
287 DEFINE_SYSREG_RW_FUNCS(spsr_el2)
288 DEFINE_SYSREG_RW_FUNCS(spsr_el3)
289 DEFINE_SYSREG_RW_FUNCS(elr_el1)
290 DEFINE_SYSREG_RW_FUNCS(elr_el2)
291 DEFINE_SYSREG_RW_FUNCS(elr_el3)
292 DEFINE_SYSREG_RW_FUNCS(mdccsr_el0)
293 DEFINE_SYSREG_RW_FUNCS(mdccint_el1)
294 DEFINE_SYSREG_RW_FUNCS(dbgdtrrx_el0)
295 DEFINE_SYSREG_RW_FUNCS(dbgdtrtx_el0)
296 DEFINE_SYSREG_RW_FUNCS(sp_el1)
297 DEFINE_SYSREG_RW_FUNCS(sp_el2)
298
299 DEFINE_SYSOP_FUNC(wfi)
300 DEFINE_SYSOP_FUNC(wfe)
301 DEFINE_SYSOP_FUNC(sev)
302 DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
303 DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
304 DEFINE_SYSOP_TYPE_FUNC(dmb, st)
305 DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
306 DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
307 DEFINE_SYSOP_TYPE_FUNC(dsb, osh)
308 DEFINE_SYSOP_TYPE_FUNC(dsb, nsh)
309 DEFINE_SYSOP_TYPE_FUNC(dsb, ishst)
310 DEFINE_SYSOP_TYPE_FUNC(dsb, oshst)
311 DEFINE_SYSOP_TYPE_FUNC(dmb, oshld)
312 DEFINE_SYSOP_TYPE_FUNC(dmb, oshst)
313 DEFINE_SYSOP_TYPE_FUNC(dmb, osh)
314 DEFINE_SYSOP_TYPE_FUNC(dmb, nshld)
315 DEFINE_SYSOP_TYPE_FUNC(dmb, nshst)
316 DEFINE_SYSOP_TYPE_FUNC(dmb, nsh)
317 DEFINE_SYSOP_TYPE_FUNC(dmb, ishld)
318 DEFINE_SYSOP_TYPE_FUNC(dmb, ishst)
319 DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
320 DEFINE_SYSOP_FUNC(isb)
321
322 static inline void enable_irq(void)
323 {
324 /*
325 * The compiler memory barrier will prevent the compiler from
326 * scheduling non-volatile memory access after the write to the
327 * register.
328 *
329 * This could happen if some initialization code issues non-volatile
330 * accesses to an area used by an interrupt handler, in the assumption
331 * that it is safe as the interrupts are disabled at the time it does
332 * that (according to program order). However, non-volatile accesses
333 * are not necessarily in program order relatively with volatile inline
334 * assembly statements (and volatile accesses).
335 */
336 COMPILER_BARRIER();
337 write_daifclr(DAIF_IRQ_BIT);
338 isb();
339 }
340
enable_fiq(void)341 static inline void enable_fiq(void)
342 {
343 COMPILER_BARRIER();
344 write_daifclr(DAIF_FIQ_BIT);
345 isb();
346 }
347
enable_serror(void)348 static inline void enable_serror(void)
349 {
350 COMPILER_BARRIER();
351 write_daifclr(DAIF_ABT_BIT);
352 isb();
353 }
354
enable_debug_exceptions(void)355 static inline void enable_debug_exceptions(void)
356 {
357 COMPILER_BARRIER();
358 write_daifclr(DAIF_DBG_BIT);
359 isb();
360 }
361
disable_irq(void)362 static inline void disable_irq(void)
363 {
364 COMPILER_BARRIER();
365 write_daifset(DAIF_IRQ_BIT);
366 isb();
367 }
368
disable_fiq(void)369 static inline void disable_fiq(void)
370 {
371 COMPILER_BARRIER();
372 write_daifset(DAIF_FIQ_BIT);
373 isb();
374 }
375
disable_serror(void)376 static inline void disable_serror(void)
377 {
378 COMPILER_BARRIER();
379 write_daifset(DAIF_ABT_BIT);
380 isb();
381 }
382
disable_debug_exceptions(void)383 static inline void disable_debug_exceptions(void)
384 {
385 COMPILER_BARRIER();
386 write_daifset(DAIF_DBG_BIT);
387 isb();
388 }
389
390 void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
391 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
392
393 /*******************************************************************************
394 * System register accessor prototypes
395 ******************************************************************************/
396 DEFINE_IDREG_READ_FUNC(midr_el1)
DEFINE_SYSREG_READ_FUNC(mpidr_el1)397 DEFINE_SYSREG_READ_FUNC(mpidr_el1)
398 DEFINE_IDREG_READ_FUNC(id_aa64mmfr0_el1)
399 DEFINE_IDREG_READ_FUNC(id_aa64mmfr1_el1)
400
401 DEFINE_SYSREG_RW_FUNCS(scr_el3)
402 DEFINE_SYSREG_RW_FUNCS(hcr_el2)
403
404 DEFINE_SYSREG_RW_FUNCS(vbar_el1)
405 DEFINE_SYSREG_RW_FUNCS(vbar_el2)
406 DEFINE_SYSREG_RW_FUNCS(vbar_el3)
407
408 DEFINE_SYSREG_RW_FUNCS(sctlr_el1)
409 DEFINE_SYSREG_RW_FUNCS(sctlr_el2)
410 DEFINE_SYSREG_RW_FUNCS(sctlr_el3)
411
412 DEFINE_SYSREG_RW_FUNCS(actlr_el1)
413 DEFINE_SYSREG_RW_FUNCS(actlr_el2)
414 DEFINE_SYSREG_RW_FUNCS(actlr_el3)
415
416 DEFINE_SYSREG_RW_FUNCS(esr_el1)
417 DEFINE_SYSREG_RW_FUNCS(esr_el2)
418 DEFINE_SYSREG_RW_FUNCS(esr_el3)
419
420 DEFINE_SYSREG_RW_FUNCS(afsr0_el1)
421 DEFINE_SYSREG_RW_FUNCS(afsr0_el2)
422 DEFINE_SYSREG_RW_FUNCS(afsr0_el3)
423
424 DEFINE_SYSREG_RW_FUNCS(afsr1_el1)
425 DEFINE_SYSREG_RW_FUNCS(afsr1_el2)
426 DEFINE_SYSREG_RW_FUNCS(afsr1_el3)
427
428 DEFINE_SYSREG_RW_FUNCS(far_el1)
429 DEFINE_SYSREG_RW_FUNCS(far_el2)
430 DEFINE_SYSREG_RW_FUNCS(far_el3)
431
432 DEFINE_SYSREG_RW_FUNCS(mair_el1)
433 DEFINE_SYSREG_RW_FUNCS(mair_el2)
434 DEFINE_SYSREG_RW_FUNCS(mair_el3)
435
436 DEFINE_SYSREG_RW_FUNCS(amair_el1)
437 DEFINE_SYSREG_RW_FUNCS(amair_el2)
438 DEFINE_SYSREG_RW_FUNCS(amair_el3)
439
440 DEFINE_SYSREG_READ_FUNC(rvbar_el1)
441 DEFINE_SYSREG_READ_FUNC(rvbar_el2)
442 DEFINE_SYSREG_READ_FUNC(rvbar_el3)
443
444 DEFINE_SYSREG_RW_FUNCS(rmr_el1)
445 DEFINE_SYSREG_RW_FUNCS(rmr_el2)
446 DEFINE_SYSREG_RW_FUNCS(rmr_el3)
447
448 DEFINE_SYSREG_RW_FUNCS(tcr_el1)
449 DEFINE_SYSREG_RW_FUNCS(tcr_el2)
450 DEFINE_SYSREG_RW_FUNCS(tcr_el3)
451
452 #if ENABLE_FEAT_D128
453 DECLARE_SYSREG128_RW_FUNCS(ttbr0_el1)
454 DECLARE_SYSREG128_RW_FUNCS(ttbr1_el1)
455 DECLARE_SYSREG128_RW_FUNCS(ttbr0_el2)
456 DECLARE_SYSREG128_RW_FUNCS(ttbr1_el2)
457 DECLARE_SYSREG128_RW_FUNCS(vttbr_el2)
458 #else
459 DEFINE_SYSREG_RW_FUNCS(ttbr0_el1)
460 DEFINE_SYSREG_RW_FUNCS(ttbr1_el1)
461 DEFINE_SYSREG_RW_FUNCS(ttbr0_el2)
462 DEFINE_RENAME_SYSREG_RW_FUNCS(ttbr1_el2, TTBR1_EL2)
463 DEFINE_SYSREG_RW_FUNCS(vttbr_el2)
464 #endif
465
466 DEFINE_SYSREG_RW_FUNCS(ttbr0_el3)
467
468 DEFINE_SYSREG_RW_FUNCS(cptr_el2)
469 DEFINE_SYSREG_RW_FUNCS(cptr_el3)
470
471 DEFINE_SYSREG_RW_FUNCS(cpacr_el1)
472 DEFINE_SYSREG_RW_FUNCS(cntfrq_el0)
473 DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2)
474 DEFINE_SYSREG_RW_FUNCS(cnthp_tval_el2)
475 DEFINE_SYSREG_RW_FUNCS(cnthp_cval_el2)
476 DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1)
477 DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1)
478 DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1)
479 DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0)
480 DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0)
481 DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0)
482 DEFINE_SYSREG_READ_FUNC(cntpct_el0)
483 DEFINE_SYSREG_RW_FUNCS(cnthctl_el2)
484 DEFINE_SYSREG_RW_FUNCS(cntv_ctl_el0)
485 DEFINE_SYSREG_RW_FUNCS(cntv_cval_el0)
486 DEFINE_SYSREG_RW_FUNCS(cntkctl_el1)
487
488 DEFINE_SYSREG_RW_FUNCS(vtcr_el2)
489
490 #define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \
491 CNTP_CTL_ENABLE_MASK)
492 #define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \
493 CNTP_CTL_IMASK_MASK)
494 #define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \
495 CNTP_CTL_ISTATUS_MASK)
496
497 #define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT))
498 #define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT))
499
500 #define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT))
501 #define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT))
502
503 DEFINE_SYSREG_RW_FUNCS(tpidr_el0)
504 DEFINE_SYSREG_RW_FUNCS(tpidr_el1)
505 DEFINE_SYSREG_RW_FUNCS(tpidr_el2)
506 DEFINE_SYSREG_RW_FUNCS(tpidr_el3)
507
508 DEFINE_SYSREG_RW_FUNCS(cntvoff_el2)
509
510 DEFINE_SYSREG_RW_FUNCS(vpidr_el2)
511 DEFINE_SYSREG_RW_FUNCS(vmpidr_el2)
512
513 DEFINE_SYSREG_RW_FUNCS(hacr_el2)
514 DEFINE_SYSREG_RW_FUNCS(hpfar_el2)
515
516 DEFINE_SYSREG_RW_FUNCS(dbgvcr32_el2)
517 DEFINE_RENAME_SYSREG_RW_FUNCS(ich_hcr_el2, ICH_HCR_EL2)
518 DEFINE_RENAME_SYSREG_RW_FUNCS(ich_vmcr_el2, ICH_VMCR_EL2)
519
520 DEFINE_SYSREG_READ_FUNC(isr_el1)
521
522 DEFINE_SYSREG_RW_FUNCS(mdscr_el1)
523 DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
524 DEFINE_SYSREG_RW_FUNCS(mdcr_el3)
525 DEFINE_SYSREG_RW_FUNCS(hstr_el2)
526 DEFINE_SYSREG_RW_FUNCS(pmcr_el0)
527
528 DEFINE_SYSREG_RW_FUNCS(csselr_el1)
529 DEFINE_SYSREG_RW_FUNCS(tpidrro_el0)
530 DEFINE_SYSREG_RW_FUNCS(contextidr_el1)
531 DEFINE_SYSREG_RW_FUNCS(spsr_abt)
532 DEFINE_SYSREG_RW_FUNCS(spsr_und)
533 DEFINE_SYSREG_RW_FUNCS(spsr_irq)
534 DEFINE_SYSREG_RW_FUNCS(spsr_fiq)
535 DEFINE_SYSREG_RW_FUNCS(dacr32_el2)
536 DEFINE_SYSREG_RW_FUNCS(ifsr32_el2)
537
538 /* GICv3 System Registers */
539
540 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
541 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2)
542 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3)
543 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1)
544 DEFINE_RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1)
545 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3)
546 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1)
547 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1)
548 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1)
549 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1)
550 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1)
551 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1)
552 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1)
553 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1)
554 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1)
555 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R)
556 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_asgi1r, ICC_ASGI1R)
557
558 DEFINE_RENAME_SYSREG_READ_FUNC(amcfgr_el0, AMCFGR_EL0)
559 DEFINE_RENAME_SYSREG_READ_FUNC(amcgcr_el0, AMCGCR_EL0)
560 DEFINE_RENAME_SYSREG_READ_FUNC(amcg1idr_el0, AMCG1IDR_EL0)
561 DEFINE_RENAME_SYSREG_RW_FUNCS(amcr_el0, AMCR_EL0)
562 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0)
563 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0)
564 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0)
565 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0)
566
567 DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1)
568
569 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3)
570 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2)
571
572 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64smfr0_el1, ID_AA64SMFR0_EL1)
573 DEFINE_RENAME_SYSREG_RW_FUNCS(smcr_el3, SMCR_EL3)
574
575 DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1)
576 DEFINE_RENAME_SYSREG_WRITE_FUNC(errselr_el1, ERRSELR_EL1)
577
578 DEFINE_RENAME_SYSREG_READ_FUNC(erxfr_el1, ERXFR_EL1)
579 DEFINE_RENAME_SYSREG_RW_FUNCS(erxctlr_el1, ERXCTLR_EL1)
580 DEFINE_RENAME_SYSREG_RW_FUNCS(erxstatus_el1, ERXSTATUS_EL1)
581 DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1)
582 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1)
583 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1)
584
585 DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el2, SCXTNUM_EL2)
586 DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el1, SCXTNUM_EL1)
587 DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el0, SCXTNUM_EL0)
588
589 /* Armv8.1 VHE Registers */
590 DEFINE_RENAME_SYSREG_RW_FUNCS(contextidr_el2, CONTEXTIDR_EL2)
591
592 /* Armv8.2 ID Registers */
593 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1)
594
595 /* Armv8.2 RAS Registers */
596 DEFINE_RENAME_SYSREG_RW_FUNCS(disr_el1, DISR_EL1)
597 DEFINE_RENAME_SYSREG_RW_FUNCS(vdisr_el2, VDISR_EL2)
598 DEFINE_RENAME_SYSREG_RW_FUNCS(vsesr_el2, VSESR_EL2)
599
600 /* Armv8.2 MPAM Registers */
601 DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1)
602 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3)
603 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2)
604 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2)
605 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm0_el2, MPAMVPM0_EL2)
606 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm1_el2, MPAMVPM1_EL2)
607 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm2_el2, MPAMVPM2_EL2)
608 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm3_el2, MPAMVPM3_EL2)
609 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm4_el2, MPAMVPM4_EL2)
610 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm5_el2, MPAMVPM5_EL2)
611 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm6_el2, MPAMVPM6_EL2)
612 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm7_el2, MPAMVPM7_EL2)
613 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpmv_el2, MPAMVPMV_EL2)
614
615 /* Armv8.3 Pointer Authentication Registers */
616 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1)
617 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1)
618
619 /* Armv8.4 Data Independent Timing Register */
620 DEFINE_RENAME_SYSREG_RW_FUNCS(dit, DIT)
621
622 /* Armv8.4 FEAT_TRF Register */
623 DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el2, TRFCR_EL2)
624 DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el1, TRFCR_EL1)
625 DEFINE_RENAME_SYSREG_RW_FUNCS(vncr_el2, VNCR_EL2)
626
627 /* Armv8.5 MTE Registers */
628 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1)
629 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1)
630 DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1)
631 DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1)
632 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el2, TFSR_EL2)
633
634 /* Armv8.5 FEAT_RNG Registers */
635 DEFINE_RENAME_SYSREG_READ_FUNC(rndr, RNDR)
636 DEFINE_RENAME_SYSREG_READ_FUNC(rndrrs, RNDRRS)
637
638 /* Armv8.6 FEAT_FGT Registers */
639 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgrtr_el2, HDFGRTR_EL2)
640 DEFINE_RENAME_SYSREG_RW_FUNCS(hafgrtr_el2, HAFGRTR_EL2)
641 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgwtr_el2, HDFGWTR_EL2)
642 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgitr_el2, HFGITR_EL2)
643 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgrtr_el2, HFGRTR_EL2)
644 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgwtr_el2, HFGWTR_EL2)
645
646 /* ARMv8.6 FEAT_ECV Register */
647 DEFINE_RENAME_SYSREG_RW_FUNCS(cntpoff_el2, CNTPOFF_EL2)
648
649 /* FEAT_HCX Register */
650 DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2)
651
652 /* Armv8.9 system registers */
653 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr3_el1, ID_AA64MMFR3_EL1)
654
655 /* Armv8.9 FEAT_FGT2 Registers */
656 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgrtr2_el2, HDFGRTR2_EL2)
657 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgwtr2_el2, HDFGWTR2_EL2)
658 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgitr2_el2, HFGITR2_EL2)
659 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgrtr2_el2, HFGRTR2_EL2)
660 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgwtr2_el2, HFGWTR2_EL2)
661
662 /* FEAT_TCR2 Register */
663 DEFINE_RENAME_SYSREG_RW_FUNCS(tcr2_el1, TCR2_EL1)
664 DEFINE_RENAME_SYSREG_RW_FUNCS(tcr2_el2, TCR2_EL2)
665
666 /* FEAT_SxPIE Registers */
667 DEFINE_RENAME_SYSREG_RW_FUNCS(pire0_el1, PIRE0_EL1)
668 DEFINE_RENAME_SYSREG_RW_FUNCS(pire0_el2, PIRE0_EL2)
669 DEFINE_RENAME_SYSREG_RW_FUNCS(pir_el1, PIR_EL1)
670 DEFINE_RENAME_SYSREG_RW_FUNCS(pir_el2, PIR_EL2)
671 DEFINE_RENAME_SYSREG_RW_FUNCS(s2pir_el2, S2PIR_EL2)
672
673 /* FEAT_SxPOE Registers */
674 DEFINE_RENAME_SYSREG_RW_FUNCS(por_el1, POR_EL1)
675 DEFINE_RENAME_SYSREG_RW_FUNCS(por_el2, POR_EL2)
676 DEFINE_RENAME_SYSREG_RW_FUNCS(s2por_el1, S2POR_EL1)
677
678 /* FEAT_GCS Registers */
679 DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el2, GCSCR_EL2)
680 DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el2, GCSPR_EL2)
681 DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el1, GCSCR_EL1)
682 DEFINE_RENAME_SYSREG_RW_FUNCS(gcscre0_el1, GCSCRE0_EL1)
683 DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el1, GCSPR_EL1)
684 DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el0, GCSPR_EL0)
685
686 /* FEAT_THE Registers */
687 #if ENABLE_FEAT_D128
688 DECLARE_SYSREG128_RW_FUNCS(rcwmask_el1)
689 DECLARE_SYSREG128_RW_FUNCS(rcwsmask_el1)
690 #else
691 DEFINE_RENAME_SYSREG_RW_FUNCS(rcwmask_el1, RCWMASK_EL1)
692 DEFINE_RENAME_SYSREG_RW_FUNCS(rcwsmask_el1, RCWSMASK_EL1)
693 #endif
694
695 /* FEAT_SCTLR2 Registers */
696 DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el1, SCTLR2_EL1)
697 DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el2, SCTLR2_EL2)
698
699 /* FEAT_LS64_ACCDATA Registers */
700 DEFINE_RENAME_SYSREG_RW_FUNCS(accdata_el1, ACCDATA_EL1)
701
702 /* DynamIQ Control registers */
703 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)
704 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmcr_el1, CLUSTERPMCR_EL1)
705 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmcntenset_el1, CLUSTERPMCNTENSET_EL1)
706 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmccntr_el1, CLUSTERPMCCNTR_EL1)
707 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmovsset_el1, CLUSTERPMOVSSET_EL1)
708 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmovsclr_el1, CLUSTERPMOVSCLR_EL1)
709 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmselr_el1, CLUSTERPMSELR_EL1)
710 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmxevcntr_el1, CLUSTERPMXEVCNTR_EL1)
711 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmxevtyper_el1, CLUSTERPMXEVTYPER_EL1)
712
713 /* CPU Power/Performance Management registers */
714 DEFINE_RENAME_SYSREG_RW_FUNCS(cpuppmcr_el3, CPUPPMCR_EL3)
715 DEFINE_RENAME_SYSREG_RW_FUNCS(cpumpmmcr_el3, CPUMPMMCR_EL3)
716
717 /* Armv9.2 RME Registers */
718 DEFINE_RENAME_SYSREG_RW_FUNCS(gptbr_el3, GPTBR_EL3)
719 DEFINE_RENAME_SYSREG_RW_FUNCS(gpccr_el3, GPCCR_EL3)
720
721 #define IS_IN_EL(x) \
722 (GET_EL(read_CurrentEl()) == MODE_EL##x)
723
724 #define IS_IN_EL1() IS_IN_EL(1)
725 #define IS_IN_EL2() IS_IN_EL(2)
726 #define IS_IN_EL3() IS_IN_EL(3)
727
728 static inline unsigned int get_current_el(void)
729 {
730 return GET_EL(read_CurrentEl());
731 }
732
get_current_el_maybe_constant(void)733 static inline unsigned int get_current_el_maybe_constant(void)
734 {
735 #if defined(IMAGE_AT_EL1)
736 return 1;
737 #elif defined(IMAGE_AT_EL2)
738 return 2; /* no use-case in TF-A */
739 #elif defined(IMAGE_AT_EL3)
740 return 3;
741 #else
742 /*
743 * If we do not know which exception level this is being built for
744 * (e.g. built for library), fall back to run-time detection.
745 */
746 return get_current_el();
747 #endif
748 }
749
750 /*
751 * Check if an EL is implemented from AA64PFR0 register fields.
752 */
el_implemented(unsigned int el)753 static inline uint64_t el_implemented(unsigned int el)
754 {
755 if (el > 3U) {
756 return EL_IMPL_NONE;
757 } else {
758 unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el;
759
760 return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK;
761 }
762 }
763
764 /*
765 * TLBI PAALLOS instruction
766 * (TLB Invalidate GPT Information by PA, All Entries, Outer Shareable)
767 */
tlbipaallos(void)768 static inline void tlbipaallos(void)
769 {
770 __asm__("sys #6, c8, c1, #4");
771 }
772
773 /*
774 * TLBI RPALOS instructions
775 * (TLB Range Invalidate GPT Information by PA, Last level, Outer Shareable)
776 *
777 * command SIZE, bits [47:44] field:
778 * 0b0000 4KB
779 * 0b0001 16KB
780 * 0b0010 64KB
781 * 0b0011 2MB
782 * 0b0100 32MB
783 * 0b0101 512MB
784 * 0b0110 1GB
785 * 0b0111 16GB
786 * 0b1000 64GB
787 * 0b1001 512GB
788 */
789 #define TLBI_SZ_4K 0UL
790 #define TLBI_SZ_16K 1UL
791 #define TLBI_SZ_64K 2UL
792 #define TLBI_SZ_2M 3UL
793 #define TLBI_SZ_32M 4UL
794 #define TLBI_SZ_512M 5UL
795 #define TLBI_SZ_1G 6UL
796 #define TLBI_SZ_16G 7UL
797 #define TLBI_SZ_64G 8UL
798 #define TLBI_SZ_512G 9UL
799
800 #define TLBI_ADDR_SHIFT U(12)
801 #define TLBI_SIZE_SHIFT U(44)
802
803 #define TLBIRPALOS(_addr, _size) \
804 { \
805 u_register_t arg = ((_addr) >> TLBI_ADDR_SHIFT) | \
806 ((_size) << TLBI_SIZE_SHIFT); \
807 __asm__("sys #6, c8, c4, #7, %0" : : "r" (arg)); \
808 }
809
810 /* Note: addr must be aligned to 4KB */
tlbirpalos_4k(uintptr_t addr)811 static inline void tlbirpalos_4k(uintptr_t addr)
812 {
813 TLBIRPALOS(addr, TLBI_SZ_4K);
814 }
815
816 /* Note: addr must be aligned to 16KB */
tlbirpalos_16k(uintptr_t addr)817 static inline void tlbirpalos_16k(uintptr_t addr)
818 {
819 TLBIRPALOS(addr, TLBI_SZ_16K);
820 }
821
822 /* Note: addr must be aligned to 64KB */
tlbirpalos_64k(uintptr_t addr)823 static inline void tlbirpalos_64k(uintptr_t addr)
824 {
825 TLBIRPALOS(addr, TLBI_SZ_64K);
826 }
827
828 /* Note: addr must be aligned to 2MB */
tlbirpalos_2m(uintptr_t addr)829 static inline void tlbirpalos_2m(uintptr_t addr)
830 {
831 TLBIRPALOS(addr, TLBI_SZ_2M);
832 }
833
834 /* Note: addr must be aligned to 32MB */
tlbirpalos_32m(uintptr_t addr)835 static inline void tlbirpalos_32m(uintptr_t addr)
836 {
837 TLBIRPALOS(addr, TLBI_SZ_32M);
838 }
839
840 /* Note: addr must be aligned to 512MB */
tlbirpalos_512m(uintptr_t addr)841 static inline void tlbirpalos_512m(uintptr_t addr)
842 {
843 TLBIRPALOS(addr, TLBI_SZ_512M);
844 }
845
846 /* Previously defined accessor functions with incomplete register names */
847
848 #define read_current_el() read_CurrentEl()
849
850 #define dsb() dsbsy()
851
852 #define read_midr() read_midr_el1()
853
854 #define read_mpidr() read_mpidr_el1()
855
856 #define read_scr() read_scr_el3()
857 #define write_scr(_v) write_scr_el3(_v)
858
859 #define read_hcr() read_hcr_el2()
860 #define write_hcr(_v) write_hcr_el2(_v)
861
862 #define read_cpacr() read_cpacr_el1()
863 #define write_cpacr(_v) write_cpacr_el1(_v)
864
865 #define read_clusterpwrdn() read_clusterpwrdn_el1()
866 #define write_clusterpwrdn(_v) write_clusterpwrdn_el1(_v)
867
868 #define read_clusterpmcr() read_clusterpmcr_el1()
869 #define write_clusterpmcr(_v) write_clusterpmcr_el1(_v)
870
871 #define read_clusterpmcntenset() read_clusterpmcntenset_el1()
872 #define write_clusterpmcntenset(_v) write_clusterpmcntenset_el1(_v)
873
874 #define read_clusterpmccntr() read_clusterpmccntr_el1()
875 #define write_clusterpmccntr(_v) write_clusterpmccntr_el1(_v)
876
877 #define read_clusterpmovsset() read_clusterpmovsset_el1()
878 #define write_clusterpmovsset(_v) write_clusterpmovsset_el1(_v)
879
880 #define read_clusterpmovsclr() read_clusterpmovsclr_el1()
881 #define write_clusterpmovsclr(_v) write_clusterpmovsclr_el1(_v)
882
883 #define read_clusterpmselr() read_clusterpmselr_el1()
884 #define write_clusterpmselr(_v) write_clusterpmselr_el1(_v)
885
886 #define read_clusterpmxevcntr() read_clusterpmxevcntr_el1()
887 #define write_clusterpmxevcntr(_v) write_clusterpmxevcntr_el1(_v)
888
889 #define read_clusterpmxevtyper() read_clusterpmxevtyper_el1()
890 #define write_clusterpmxevtyper(_v) write_clusterpmxevtyper_el1(_v)
891
892 #if ERRATA_SPECULATIVE_AT
893 /*
894 * Assuming SCTLR.M bit is already enabled
895 * 1. Enable page table walk by clearing TCR_EL1.EPDx bits
896 * 2. Execute AT instruction for lower EL1/0
897 * 3. Disable page table walk by setting TCR_EL1.EPDx bits
898 */
899 #define AT(_at_inst, _va) \
900 { \
901 assert((read_sctlr_el1() & SCTLR_M_BIT) != 0ULL); \
902 write_tcr_el1(read_tcr_el1() & ~(TCR_EPD0_BIT | TCR_EPD1_BIT)); \
903 isb(); \
904 _at_inst(_va); \
905 write_tcr_el1(read_tcr_el1() | (TCR_EPD0_BIT | TCR_EPD1_BIT)); \
906 isb(); \
907 }
908 #else
909 #define AT(_at_inst, _va) _at_inst(_va)
910 #endif
911
912 #endif /* ARCH_HELPERS_H */
913