1 /* 2 * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef CDN_MMC_H 10 #define CDN_MMC_H 11 12 #include <drivers/cadence/cdns_combo_phy.h> 13 #include <drivers/mmc.h> 14 15 #if MMC_DEVICE_TYPE == 0 16 #define CONFIG_DMA_ADDR_T_64BIT 0 17 #endif 18 19 #define MMC_REG_BASE SOCFPGA_MMC_REG_BASE 20 #define COMBO_PHY_REG 0x0 21 #define SDHC_EXTENDED_WR_MODE_MASK 0xFFFFFFF7 22 #define SDHC_DLL_RESET_MASK 0x00000001 23 #define MMC_MAX_BLOCK_LEN 512U 24 25 /* HRS09 */ 26 #define SDHC_PHY_SW_RESET BIT(0) 27 #define SDHC_PHY_INIT_COMPLETE BIT(1) 28 #define SDHC_EXTENDED_RD_MODE(x) ((x) << 2) 29 #define EXTENDED_WR_MODE 3 30 #define SDHC_EXTENDED_WR_MODE(x) ((x) << 3) 31 #define RDCMD_EN (3 << 15) 32 #define PHY_SW_RESET_EN (1 << 0) 33 #define PHY_INIT_COMPLETE_BIT (1 << 1) 34 #define SDHC_RDCMD_EN(x) ((x) << 15) 35 #define SDHC_RDDATA_EN(x) ((x) << 16) 36 37 /* CMD_DATA_OUTPUT */ 38 #define SDHC_CDNS_HRS16 0x40 39 40 /* This value determines the interval by which DAT line timeouts are detected */ 41 /* The interval can be computed as below: */ 42 /* • 1111b - Reserved */ 43 /* • 1110b - t_sdmclk*2(27+2) */ 44 /* • 1101b - t_sdmclk*2(26+2) */ 45 #define READ_CLK 0xa << 16 46 #define WRITE_CLK 0xe << 16 47 #define DTC_VAL 0xE 48 49 /* SRS00 */ 50 /* System Address / Argument 2 / 32-bit block count 51 * This field is used as: 52 * • 32-bit Block Count register 53 * • SDMA system memory address 54 * • Auto CMD23 Argument 55 */ 56 #define SAAR (1) 57 58 /* SRS01 */ 59 /* Transfer Block Size 60 * This field defines block size for block data transfers 61 */ 62 #define BLOCK_SIZE 0 63 64 /* SDMA Buffer Boundary 65 * System address boundary can be set for SDMA engine. 66 */ 67 #define SDMA_BUF 7 << 12 68 69 /* Block Count For Current Transfer 70 * To set the number of data blocks can be defined for next transfer 71 */ 72 #define BLK_COUNT_CT 16 73 74 /* SRS03 */ 75 #define CMD_START (U(1) << 31) 76 #define CMD_USE_HOLD_REG (1 << 29) 77 #define CMD_UPDATE_CLK_ONLY (1 << 21) 78 #define CMD_SEND_INIT (1 << 15) 79 #define CMD_STOP_ABORT_CMD (4 << 22) 80 #define CMD_RESUME_CMD (2 << 22) 81 #define CMD_SUSPEND_CMD (1 << 22) 82 #define DATA_PRESENT (0x20) 83 #define CMD_IDX_CHK_ENABLE (0x10) 84 #define CMD_WRITE (0 << 4) 85 #define CMD_READ (1 << 4) 86 #define MULTI_BLK_READ (1 << 5) 87 #define RESP_ERR (1 << 7) 88 #define CMD_CHECK_RESP_CRC (0x08) 89 #define RES_TYPE_SEL_48 (0x2) 90 #define RES_TYPE_SEL_136 (0x1) 91 #define RES_TYPE_SEL_48_B (0x3) 92 #define RES_TYPE_SEL_NO (0x3) 93 #define DMA_ENABLED (1 << 0) 94 #define BLK_CNT_EN (1 << 1) 95 #define AUTO_CMD_EN (2 << 2) 96 #define COM_IDX 24 97 #define ERROR_INT (1 << 15) 98 #define INT_SBE (1 << 13) 99 #define INT_HLE (1 << 12) 100 #define INT_FRUN (1 << 11) 101 #define INT_DRT (1 << 9) 102 #define INT_RTO (1 << 8) 103 #define INT_DCRC (1 << 7) 104 #define INT_RCRC (1 << 6) 105 #define INT_RXDR (1 << 5) 106 #define INT_TXDR (1 << 4) 107 #define INT_DTO (1 << 3) 108 #define INT_CMD_DONE (1 << 0) 109 #define TRAN_COMP (1 << 1) 110 111 /* SRS09 */ 112 #define STATUS_DATA_BUSY BIT(2) 113 #define CI 16 114 #define CHECK_CARD BIT(CI) 115 116 /* SRS10 */ 117 #define BIT1 (0 << 1) 118 #define BIT4 (1 << 1) 119 #define BIT8 (1 << 5) 120 121 /* LED Control 122 * State of this bit directly drives led port of the host 123 * in order to control the external LED diode 124 * Default value 0 << 1 125 */ 126 #define LEDC BIT(0) 127 #define LEDC_OFF (0 << 1) 128 129 /* Data Transfer Width 130 * Bit used to configure DAT bus width to 1 or 4 131 * Default value 1 << 1 132 */ 133 #define DT_WIDTH BIT(1) 134 #define DTW_4BIT (1 << 1) 135 136 /* Extended Data Transfer Width 137 * This bit is to enable/disable 8-bit DAT bus width mode 138 * Default value 1 << 5 139 */ 140 #define EDTW_8BIT BIT(5) 141 142 /* High Speed Enable 143 * Selects operating mode to Default Speed (HSE=0) or High Speed (HSE=1) 144 */ 145 #define HS_EN BIT(2) 146 147 /* here 0 defines the 64 Kb size */ 148 #define MAX_64KB_PAGE 0 149 #define EMMC_DESC_SIZE (1<<20) 150 #define DTCV_OFFSET (0x22E) 151 #define DTCV_VAL (0xE) 152 #define CICE_OFFSET (0x20E) 153 #define SRS_12_CC_EN (1 << 0) 154 /* SRS11 */ 155 /* Software Reset For All 156 * When set to 1, the entire slot is reset 157 * After completing the reset operation, SRFA bit is automatically cleared 158 */ 159 #define SRFA BIT(24) 160 161 /* Software Reset For CMD Line 162 * When set to 1, resets the logic related to the command generation and response checking 163 */ 164 #define SRCMD BIT(25) 165 166 /* Software Reset For DAT Line 167 * When set to 1, resets the logic related to the data path, 168 * including data buffers and the DMA logic 169 */ 170 #define SRDAT BIT(26) 171 172 173 /* SRS12 */ 174 /* Error mask */ 175 #define SRS12_ERR_MASK 0xFFFF8000U 176 #define CDNS_CSD_BYTE_MASK 0x000000FFU 177 178 /* SRS15 */ 179 /* UHS Mode Select 180 * Used to select one of UHS-I modes. 181 * • 000b - SDR12 182 * • 001b - SDR25 183 * • 010b - SDR50 184 * • 011b - SDR104 185 * • 100b - DDR50 186 */ 187 #define SDR12_MODE 0 << 16 188 #define SDR25_MODE 1 << 16 189 #define SDR50_MODE 2 << 16 190 #define SDR104_MODE 3 << 16 191 #define DDR50_MODE 4 << 16 192 /* 1.8V Signaling Enable 193 * • 0 - for Default Speed, High Speed mode 194 * • 1 - for UHS-I mode 195 */ 196 #define V18SE BIT(19) 197 198 /* CMD23 Enable 199 * In result of Card Identification process, 200 * Host Driver set this bit to 1 if Card supports CMD23 201 */ 202 #define CMD23_EN BIT(27) 203 204 /* Host Version 4.00 Enable 205 * • 0 - Version 3.00 206 * • 1 - Version 4.00 207 */ 208 #define HV4E BIT(28) 209 /* Conf depends on SRS15.HV4E */ 210 #define SDMA 0 << 3 211 #define ADMA2_32 2 << 3 212 #define ADMA2_64 3 << 3 213 #define DMA_SEL_BIT 3 << 3 214 #define DMA_SEL_BIT_2 2 << 3 215 #define DMA_SEL_BIT_3 3 << 3 216 217 /* Preset Value Enable 218 * Setting this bit to 1 triggers an automatically update of SRS11 219 */ 220 #define PVE BIT(31) 221 222 #define BIT_AD_32 0 << 29 223 #define BIT_AD_64 1 << 29 224 225 /* SW RESET REG*/ 226 #define SDHC_CDNS_HRS00 (0x00) 227 #define SDHC_CDNS_HRS00_SWR BIT(0) 228 229 /* PHY access port */ 230 #define SDHC_CDNS_HRS04 0x10 231 #define SDHC_CDNS_HRS04_ADDR GENMASK(5, 0) 232 233 /* PHY data access port */ 234 #define SDHC_CDNS_HRS05 0x14 235 236 /* eMMC control registers */ 237 #define SDHC_CDNS_HRS06 0x18 238 239 /* SRS */ 240 #define SDHC_CDNS_SRS_BASE 0x200 241 #define SDHC_CDNS_SRS00 0x200 242 #define SDHC_CDNS_SRS01 0x204 243 #define SDHC_CDNS_SRS02 0x208 244 #define SDHC_CDNS_SRS03 0x20c 245 #define SDHC_CDNS_SRS04 0x210 246 #define SDHC_CDNS_SRS05 0x214 247 #define SDHC_CDNS_SRS06 0x218 248 #define SDHC_CDNS_SRS07 0x21C 249 #define SDHC_CDNS_SRS08 0x220 250 #define SDHC_CDNS_SRS09 0x224 251 #define SDHC_CDNS_SRS09_CI BIT(16) 252 #define SDHC_CDNS_SRS10 0x228 253 #define SDHC_CDNS_SRS11 0x22C 254 #define SDHC_CDNS_SRS12 0x230 255 #define SDHC_CDNS_SRS13 0x234 256 #define SDHC_CDNS_SRS14 0x238 257 #define SDHC_CDNS_SRS15 0x23c 258 #define SDHC_CDNS_SRS16 0x240 259 #define SDHC_CDNS_SRS21 0x254 260 #define SDHC_CDNS_SRS22 0x258 261 #define SDHC_CDNS_SRS23 0x25c 262 #define SDHC_CDNS_SRS24 0x260 263 #define SDHC_CDNS_SRS25 0x264 264 265 /* SRS00 */ 266 #define SAAR (1) 267 268 /* SRS03 */ 269 #define CMD_START (U(1) << 31) 270 #define CMD_USE_HOLD_REG (1 << 29) 271 #define CMD_UPDATE_CLK_ONLY (1 << 21) 272 #define CMD_SEND_INIT (1 << 15) 273 #define CMD_STOP_ABORT_CMD (4 << 22) 274 #define CMD_RESUME_CMD (2 << 22) 275 #define CMD_SUSPEND_CMD (1 << 22) 276 #define DMA_ENABLED (1 << 0) 277 #define BLK_CNT_EN (1 << 1) 278 #define AUTO_CMD_EN (2 << 2) 279 #define COM_IDX 24 280 #define ERROR_INT (1 << 15) 281 #define INT_SBE (1 << 13) 282 #define INT_HLE (1 << 12) 283 #define INT_FRUN (1 << 11) 284 #define INT_DRT (1 << 9) 285 #define INT_RTO (1 << 8) 286 #define INT_DCRC (1 << 7) 287 #define INT_RCRC (1 << 6) 288 #define INT_RXDR (1 << 5) 289 #define INT_TXDR (1 << 4) 290 #define INT_DTO (1 << 3) 291 #define INT_CMD_DONE (1 << 0) 292 #define TRAN_COMP (1 << 1) 293 #define CDNS_HOST_CMD_INHIBIT (BIT(0)) 294 #define CDNS_HOST_DATA_INHIBIT (BIT(1)) 295 #define ACE_CMD_12 (BIT(2)) 296 297 #define PAGE_BUFFER_LEN (64 * 1024) 298 299 /* HRS07 */ 300 #define SDHC_CDNS_HRS07 0x1c 301 #define SDHC_IDELAY_VAL(x) ((x) << 0) 302 #define SDHC_RW_COMPENSATE(x) ((x) << 16) 303 304 /* PHY reset port */ 305 #define SDHC_CDNS_HRS09 0x24 306 307 /* HRS10 */ 308 /* PHY reset port */ 309 #define SDHC_CDNS_HRS10 0x28 310 311 /* HCSDCLKADJ DATA; DDR Mode */ 312 #define SDHC_HCSDCLKADJ(x) ((x) << 16) 313 314 /* Pinmux headers will reomove after ATF driver implementation */ 315 #define PINMUX_SDMMC_SEL 0x0 316 #define PIN0SEL 0x00 317 #define PIN1SEL 0x04 318 #define PIN2SEL 0x08 319 #define PIN3SEL 0x0C 320 #define PIN4SEL 0x10 321 #define PIN5SEL 0x14 322 #define PIN6SEL 0x18 323 #define PIN7SEL 0x1C 324 #define PIN8SEL 0x20 325 #define PIN9SEL 0x24 326 #define PIN10SEL 0x28 327 328 /* HRS16 */ 329 #define SDHC_WRCMD0_DLY(x) ((x) << 0) 330 #define SDHC_WRCMD1_DLY(x) ((x) << 4) 331 #define SDHC_WRDATA0_DLY(x) ((x) << 8) 332 #define SDHC_WRDATA1_DLY(x) ((x) << 12) 333 #define SDHC_WRCMD0_SDCLK_DLY(x) ((x) << 16) 334 #define SDHC_WRCMD1_SDCLK_DLY(x) ((x) << 20) 335 #define SDHC_WRDATA0_SDCLK_DLY(x) ((x) << 24) 336 #define SDHC_WRDATA1_SDCLK_DLY(x) ((x) << 28) 337 338 /* Shared Macros */ 339 #define SDMMC_CDN(_reg) (SDMMC_CDN_REG_BASE + \ 340 (SDMMC_CDN_##_reg)) 341 342 /* MMC Peripheral Definition */ 343 #define SOCFPGA_MMC_BLOCK_MASK (SOCFPGA_MMC_BLOCK_SIZE - U(1)) 344 #define SOCFPGA_MMC_BOOT_CLK_RATE (400 * 1000) 345 #define MMC_RESPONSE_NONE 0 346 #define SDHC_CDNS_SRS03_VALUE 0x01020013 347 348 /* Value randomly chosen for eMMC RCA, it should be > 1 */ 349 #define MMC_FIX_RCA 6 350 #define RCA_SHIFT_OFFSET 16 351 352 #define CMD_EXTCSD_PARTITION_CONFIG 179 353 #define CMD_EXTCSD_BUS_WIDTH 183 354 #define CMD_EXTCSD_HS_TIMING 185 355 #define CMD_EXTCSD_SEC_CNT 212 356 357 #define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3) 358 #define PART_CFG_PARTITION1_ACCESS (U(1) << 0) 359 360 /* Values in EXT CSD register */ 361 #define MMC_BUS_WIDTH_1 U(0) 362 #define MMC_BUS_WIDTH_4 U(1) 363 #define MMC_BUS_WIDTH_8 U(2) 364 #define MMC_BUS_WIDTH_DDR_4 U(5) 365 #define MMC_BUS_WIDTH_DDR_8 U(6) 366 #define MMC_BOOT_MODE_BACKWARD (U(0) << 3) 367 #define MMC_BOOT_MODE_HS_TIMING (U(1) << 3) 368 #define MMC_BOOT_MODE_DDR (U(2) << 3) 369 370 #define EXTCSD_SET_CMD (U(0) << 24) 371 #define EXTCSD_SET_BITS (U(1) << 24) 372 #define EXTCSD_CLR_BITS (U(2) << 24) 373 #define EXTCSD_WRITE_BYTES (U(3) << 24) 374 #define EXTCSD_CMD(x) (((x) & 0xff) << 16) 375 #define EXTCSD_VALUE(x) (((x) & 0xff) << 8) 376 #define EXTCSD_CMD_SET_NORMAL U(1) 377 378 #define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0) 379 #define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3) 380 #define CSD_TRAN_SPEED_MULT_SHIFT 3 381 382 #define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9) 383 #define STATUS_READY_FOR_DATA BIT(8) 384 #define STATUS_SWITCH_ERROR BIT(7) 385 #define MMC_GET_STATE(x) (((x) >> 9) & 0xf) 386 #define MMC_STATE_IDLE 0 387 #define MMC_STATE_READY 1 388 #define MMC_STATE_IDENT 2 389 #define MMC_STATE_STBY 3 390 #define MMC_STATE_TRAN 4 391 #define MMC_STATE_DATA 5 392 #define MMC_STATE_RCV 6 393 #define MMC_STATE_PRG 7 394 #define MMC_STATE_DIS 8 395 #define MMC_STATE_BTST 9 396 #define MMC_STATE_SLP 10 397 398 #define MMC_FLAG_CMD23 (U(1) << 0) 399 400 #define CMD8_CHECK_PATTERN U(0xAA) 401 #define VHS_2_7_3_6_V BIT(8) 402 403 /*ADMA table component*/ 404 #define ADMA_DESC_ATTR_VALID BIT(0) 405 #define ADMA_DESC_ATTR_END BIT(1) 406 #define ADMA_DESC_ATTR_INT BIT(2) 407 #define ADMA_DESC_ATTR_ACT1 BIT(4) 408 #define ADMA_DESC_ATTR_ACT2 BIT(5) 409 #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2 410 411 #define HRS_09_EXTENDED_RD_MODE (1 << 2) 412 #define HRS_09_EXTENDED_WR_MODE (1 << 3) 413 #define HRS_09_RDCMD_EN (1 << 15) 414 #define HRS_09_RDDATA_EN (1 << 16) 415 #define HRS_10_HCSDCLKADJ_VAL (3) 416 417 #define SRS11_SRFA (1 << 24) 418 #define SRS11_SRFA_CHK(x) (x >> 24) 419 #define CDNS_TIMEOUT (5000) 420 421 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 422 423 /* Card busy and present */ 424 #define CARD_BUSY 1 425 #define CARD_NOT_BUSY 0 426 427 /* 500 ms delay to read the RINST register */ 428 #define DELAY_MS_SRS_READ 500 429 #define DELAY_RES 10 430 431 /* Check DV dfi_init val=0 */ 432 #define IO_MASK_END_DATA 0x0 433 434 /* Check DV dfi_init val=2; DDR Mode */ 435 #define IO_MASK_END_DATA_DDR 0x2 436 #define IO_MASK_START_DATA 0x0 437 #define DATA_SELECT_OE_END_DATA 0x1 438 439 #define TIMEOUT 100000 440 441 /* General define */ 442 #define SDHC_REG_MASK UINT_MAX 443 #define SD_HOST_BLOCK_SIZE 0x200 444 #define DTCVVAL_DEFAULT_VAL 0xE 445 #define CDMMC_DMA_MAX_BUFFER_SIZE 64*1024 446 #define CDNSMMC_ADDRESS_MASK U(0x0f) 447 #define CONFIG_CDNS_DESC_COUNT 8 448 #define SD_HOST_CLK 200000000 449 450 enum sd_opcode { 451 SD_GO_IDLE_STATE = 0, 452 SD_ALL_SEND_CID = 2, 453 SD_SEND_RELATIVE_ADDR = 3, 454 SDIO_SEND_OP_COND = 5, /* SDIO cards only */ 455 SD_SWITCH = 6, 456 SD_SELECT_CARD = 7, 457 SD_SEND_IF_COND = 8, 458 SD_SEND_CSD = 9, 459 SD_SEND_CID = 10, 460 SD_VOL_SWITCH = 11, 461 SD_STOP_TRANSMISSION = 12, 462 SD_SEND_STATUS = 13, 463 SD_GO_INACTIVE_STATE = 15, 464 SD_SET_BLOCK_SIZE = 16, 465 SD_READ_SINGLE_BLOCK = 17, 466 SD_READ_MULTIPLE_BLOCK = 18, 467 SD_SEND_TUNING_BLOCK = 19, 468 SD_SET_BLOCK_COUNT = 23, 469 SD_WRITE_SINGLE_BLOCK = 24, 470 SD_WRITE_MULTIPLE_BLOCK = 25, 471 SD_ERASE_BLOCK_START = 32, 472 SD_ERASE_BLOCK_END = 33, 473 SD_ERASE_BLOCK_OPERATION = 38, 474 SD_APP_CMD = 55, 475 SD_SPI_READ_OCR = 58, /* SPI mode only */ 476 SD_SPI_CRC_ON_OFF = 59, /* SPI mode only */ 477 }; 478 479 enum sd_app_cmd { 480 SD_APP_SET_BUS_WIDTH = 6, 481 SD_APP_SEND_STATUS = 13, 482 SD_APP_SEND_NUM_WRITTEN_BLK = 22, 483 SD_APP_SET_WRITE_BLK_ERASE_CNT = 23, 484 SD_APP_SEND_OP_COND = 41, 485 SD_APP_CLEAR_CARD_DETECT = 42, 486 SD_APP_SEND_SCR = 51, 487 }; 488 489 enum sd_opr_modes { 490 SD_HOST_OPR_MODE_HV4E_0_SDMA_32 = 0, 491 SD_HOST_OPR_MODE_HV4E_1_SDMA_32, 492 SD_HOST_OPR_MODE_HV4E_1_SDMA_64, 493 SD_HOST_OPR_MODE_HV4E_0_ADMA_32, 494 SD_HOST_OPR_MODE_HV4E_0_ADMA_64, 495 SD_HOST_OPR_MODE_HV4E_1_ADMA_32, 496 SD_HOST_OPR_MODE_HV4E_1_ADMA_64, 497 }; 498 499 struct cdns_sdmmc_sdhc { 500 uint32_t sdhc_extended_rd_mode; 501 uint32_t sdhc_extended_wr_mode; 502 uint32_t sdhc_hcsdclkadj; 503 uint32_t sdhc_idelay_val; 504 uint32_t sdhc_rdcmd_en; 505 uint32_t sdhc_rddata_en; 506 uint32_t sdhc_rw_compensate; 507 uint32_t sdhc_sdcfsh; 508 uint32_t sdhc_sdcfsl; 509 uint32_t sdhc_wrcmd0_dly; 510 uint32_t sdhc_wrcmd0_sdclk_dly; 511 uint32_t sdhc_wrcmd1_dly; 512 uint32_t sdhc_wrcmd1_sdclk_dly; 513 uint32_t sdhc_wrdata0_dly; 514 uint32_t sdhc_wrdata0_sdclk_dly; 515 uint32_t sdhc_wrdata1_dly; 516 uint32_t sdhc_wrdata1_sdclk_dly; 517 }; 518 519 enum sdmmc_device_mode { 520 SD_DS_ID, /* Identification */ 521 SD_DS, /* Default speed */ 522 SD_HS, /* High speed */ 523 SD_UHS_SDR12, /* Ultra high speed SDR12 */ 524 SD_UHS_SDR25, /* Ultra high speed SDR25 */ 525 SD_UHS_SDR50, /* Ultra high speed SDR`50 */ 526 SD_UHS_SDR104, /* Ultra high speed SDR104 */ 527 SD_UHS_DDR50, /* Ultra high speed DDR50 */ 528 EMMC_SDR_BC, /* SDR backward compatible */ 529 EMMC_SDR, /* SDR */ 530 EMMC_DDR, /* DDR */ 531 EMMC_HS200, /* High speed 200Mhz in SDR */ 532 EMMC_HS400, /* High speed 200Mhz in DDR */ 533 EMMC_HS400es, /* High speed 200Mhz in SDR with enhanced strobe*/ 534 }; 535 536 struct cdns_sdmmc_params { 537 uintptr_t reg_base; 538 uintptr_t reg_pinmux; 539 uintptr_t reg_phy; 540 uintptr_t desc_base; 541 size_t desc_size; 542 int clk_rate; 543 int bus_width; 544 unsigned int flags; 545 enum sdmmc_device_mode cdn_sdmmc_dev_mode; 546 enum mmc_device_type cdn_sdmmc_dev_type; 547 uint32_t combophy; 548 }; 549 550 551 struct cdns_idmac_desc { 552 /*8 bit attribute*/ 553 uint8_t attr; 554 /*reserved bits in desc*/ 555 uint8_t reserved; 556 /*page length for the descriptor*/ 557 uint16_t len; 558 /*lower 32 bits for buffer (64 bit addressing)*/ 559 uint32_t addr_lo; 560 #if CONFIG_DMA_ADDR_T_64BIT == 1 561 /*higher 32 bits for buffer (64 bit addressing)*/ 562 uint32_t addr_hi; 563 } __aligned(8); 564 #else 565 } __packed; 566 #endif 567 568 569 570 /* Function Prototype */ 571 int cdns_sd_host_init(struct cdns_sdmmc_combo_phy *mmc_combo_phy_reg, 572 struct cdns_sdmmc_sdhc *mmc_sdhc_reg); 573 void cdns_set_sdmmc_var(struct cdns_sdmmc_combo_phy *combo_phy_reg, 574 struct cdns_sdmmc_sdhc *sdhc_reg); 575 int cdns_mmc_init(struct cdns_sdmmc_params *params, struct mmc_device_info *info); 576 int cdns_program_phy_reg(struct cdns_sdmmc_combo_phy *combo_phy_reg, 577 struct cdns_sdmmc_sdhc *sdhc_reg); 578 void cdns_host_set_clk(uint32_t clk); 579 #endif 580