1 /* 2 * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CONTEXT_EL2_H 8 #define CONTEXT_EL2_H 9 10 #include <lib/extensions/sysreg128.h> 11 12 #ifndef __ASSEMBLER__ 13 14 /******************************************************************************* 15 * EL2 Registers: 16 * AArch64 EL2 system register context structure for preserving the 17 * architectural state during world switches. 18 ******************************************************************************/ 19 typedef struct el2_common_regs { 20 uint64_t actlr_el2; 21 uint64_t afsr0_el2; 22 uint64_t afsr1_el2; 23 uint64_t amair_el2; 24 uint64_t cnthctl_el2; 25 uint64_t cntvoff_el2; 26 uint64_t cptr_el2; 27 uint64_t dbgvcr32_el2; 28 uint64_t elr_el2; 29 uint64_t esr_el2; 30 uint64_t far_el2; 31 uint64_t hacr_el2; 32 uint64_t hcr_el2; 33 uint64_t hpfar_el2; 34 uint64_t hstr_el2; 35 uint64_t icc_sre_el2; 36 uint64_t ich_hcr_el2; 37 uint64_t ich_vmcr_el2; 38 uint64_t mair_el2; 39 uint64_t mdcr_el2; 40 uint64_t pmscr_el2; 41 uint64_t sctlr_el2; 42 uint64_t spsr_el2; 43 uint64_t sp_el2; 44 uint64_t tcr_el2; 45 uint64_t tpidr_el2; 46 uint64_t vbar_el2; 47 uint64_t vmpidr_el2; 48 uint64_t vpidr_el2; 49 uint64_t vtcr_el2; 50 sysreg_t vttbr_el2; 51 sysreg_t ttbr0_el2; 52 } el2_common_regs_t; 53 54 typedef struct el2_mte2_regs { 55 uint64_t tfsr_el2; 56 } el2_mte2_regs_t; 57 58 typedef struct el2_fgt_regs { 59 uint64_t hdfgrtr_el2; 60 uint64_t hafgrtr_el2; 61 uint64_t hdfgwtr_el2; 62 uint64_t hfgitr_el2; 63 uint64_t hfgrtr_el2; 64 uint64_t hfgwtr_el2; 65 } el2_fgt_regs_t; 66 67 typedef struct el2_fgt2_regs { 68 uint64_t hdfgrtr2_el2; 69 uint64_t hdfgwtr2_el2; 70 uint64_t hfgitr2_el2; 71 uint64_t hfgrtr2_el2; 72 uint64_t hfgwtr2_el2; 73 } el2_fgt2_regs_t; 74 75 typedef struct el2_ecv_regs { 76 uint64_t cntpoff_el2; 77 } el2_ecv_regs_t; 78 79 typedef struct el2_vhe_regs { 80 uint64_t contextidr_el2; 81 sysreg_t ttbr1_el2; 82 } el2_vhe_regs_t; 83 84 typedef struct el2_ras_regs { 85 uint64_t vdisr_el2; 86 uint64_t vsesr_el2; 87 } el2_ras_regs_t; 88 89 typedef struct el2_neve_regs { 90 uint64_t vncr_el2; 91 } el2_neve_regs_t; 92 93 typedef struct el2_trf_regs { 94 uint64_t trfcr_el2; 95 } el2_trf_regs_t; 96 97 typedef struct el2_csv2_regs { 98 uint64_t scxtnum_el2; 99 } el2_csv2_regs_t; 100 101 typedef struct el2_hcx_regs { 102 uint64_t hcrx_el2; 103 } el2_hcx_regs_t; 104 105 typedef struct el2_tcr2_regs { 106 uint64_t tcr2_el2; 107 } el2_tcr2_regs_t; 108 109 typedef struct el2_sxpoe_regs { 110 uint64_t por_el2; 111 } el2_sxpoe_regs_t; 112 113 typedef struct el2_sxpie_regs { 114 uint64_t pire0_el2; 115 uint64_t pir_el2; 116 } el2_sxpie_regs_t; 117 118 typedef struct el2_s2pie_regs { 119 uint64_t s2pir_el2; 120 } el2_s2pie_regs_t; 121 122 typedef struct el2_gcs_regs { 123 uint64_t gcscr_el2; 124 uint64_t gcspr_el2; 125 } el2_gcs_regs_t; 126 127 typedef struct el2_mpam_regs { 128 uint64_t mpam2_el2; 129 uint64_t mpamhcr_el2; 130 uint64_t mpamvpm0_el2; 131 uint64_t mpamvpm1_el2; 132 uint64_t mpamvpm2_el2; 133 uint64_t mpamvpm3_el2; 134 uint64_t mpamvpm4_el2; 135 uint64_t mpamvpm5_el2; 136 uint64_t mpamvpm6_el2; 137 uint64_t mpamvpm7_el2; 138 uint64_t mpamvpmv_el2; 139 } el2_mpam_regs_t; 140 141 typedef struct el2_sctlr2_regs { 142 uint64_t sctlr2_el2; 143 } el2_sctlr2_regs_t; 144 145 typedef struct el2_sysregs { 146 147 el2_common_regs_t common; 148 149 #if ENABLE_FEAT_MTE2 150 el2_mte2_regs_t mte2; 151 #endif 152 153 #if ENABLE_FEAT_FGT 154 el2_fgt_regs_t fgt; 155 #endif 156 157 #if ENABLE_FEAT_FGT2 158 el2_fgt2_regs_t fgt2; 159 #endif 160 161 #if ENABLE_FEAT_ECV 162 el2_ecv_regs_t ecv; 163 #endif 164 165 #if ENABLE_FEAT_VHE 166 el2_vhe_regs_t vhe; 167 #endif 168 169 #if ENABLE_FEAT_RAS 170 el2_ras_regs_t ras; 171 #endif 172 173 #if CTX_INCLUDE_NEVE_REGS 174 el2_neve_regs_t neve; 175 #endif 176 177 #if ENABLE_TRF_FOR_NS 178 el2_trf_regs_t trf; 179 #endif 180 181 #if ENABLE_FEAT_CSV2_2 182 el2_csv2_regs_t csv2; 183 #endif 184 185 #if ENABLE_FEAT_HCX 186 el2_hcx_regs_t hcx; 187 #endif 188 189 #if ENABLE_FEAT_TCR2 190 el2_tcr2_regs_t tcr2; 191 #endif 192 193 #if (ENABLE_FEAT_S1POE || ENABLE_FEAT_S2POE) 194 el2_sxpoe_regs_t sxpoe; 195 #endif 196 197 #if (ENABLE_FEAT_S1PIE || ENABLE_FEAT_S2PIE) 198 el2_sxpie_regs_t sxpie; 199 #endif 200 201 #if ENABLE_FEAT_S2PIE 202 el2_s2pie_regs_t s2pie; 203 #endif 204 205 #if ENABLE_FEAT_GCS 206 el2_gcs_regs_t gcs; 207 #endif 208 209 #if CTX_INCLUDE_MPAM_REGS 210 el2_mpam_regs_t mpam; 211 #endif 212 213 #if ENABLE_FEAT_SCTLR2 214 el2_sctlr2_regs_t sctlr2; 215 #endif 216 217 } el2_sysregs_t; 218 219 /* 220 * Macros to access members related to individual features of the el2_sysregs_t 221 * structures. 222 */ 223 #define read_el2_ctx_common(ctx, reg) (((ctx)->common).reg) 224 225 #define write_el2_ctx_common(ctx, reg, val) ((((ctx)->common).reg) \ 226 = (uint64_t) (val)) 227 228 #define write_el2_ctx_sysreg128(ctx, reg, val) ((((ctx)->common).reg) \ 229 = (sysreg_t) (val)) 230 231 #if ENABLE_FEAT_MTE2 232 #define read_el2_ctx_mte2(ctx, reg) (((ctx)->mte2).reg) 233 #define write_el2_ctx_mte2(ctx, reg, val) ((((ctx)->mte2).reg) \ 234 = (uint64_t) (val)) 235 #else 236 #define read_el2_ctx_mte2(ctx, reg) ULL(0) 237 #define write_el2_ctx_mte2(ctx, reg, val) 238 #endif /* ENABLE_FEAT_MTE2 */ 239 240 #if ENABLE_FEAT_FGT 241 #define read_el2_ctx_fgt(ctx, reg) (((ctx)->fgt).reg) 242 #define write_el2_ctx_fgt(ctx, reg, val) ((((ctx)->fgt).reg) \ 243 = (uint64_t) (val)) 244 #else 245 #define read_el2_ctx_fgt(ctx, reg) ULL(0) 246 #define write_el2_ctx_fgt(ctx, reg, val) 247 #endif /* ENABLE_FEAT_FGT */ 248 249 #if ENABLE_FEAT_FGT2 250 #define read_el2_ctx_fgt2(ctx, reg) (((ctx)->fgt2).reg) 251 #define write_el2_ctx_fgt2(ctx, reg, val) ((((ctx)->fgt2).reg) \ 252 = (uint64_t) (val)) 253 #else 254 #define read_el2_ctx_fgt2(ctx, reg) ULL(0) 255 #define write_el2_ctx_fgt2(ctx, reg, val) 256 #endif /* ENABLE_FEAT_FGT */ 257 258 #if ENABLE_FEAT_ECV 259 #define read_el2_ctx_ecv(ctx, reg) (((ctx)->ecv).reg) 260 #define write_el2_ctx_ecv(ctx, reg, val) ((((ctx)->ecv).reg) \ 261 = (uint64_t) (val)) 262 #else 263 #define read_el2_ctx_ecv(ctx, reg) ULL(0) 264 #define write_el2_ctx_ecv(ctx, reg, val) 265 #endif /* ENABLE_FEAT_ECV */ 266 267 #if ENABLE_FEAT_VHE 268 #define read_el2_ctx_vhe(ctx, reg) (((ctx)->vhe).reg) 269 #define write_el2_ctx_vhe(ctx, reg, val) ((((ctx)->vhe).reg) \ 270 = (uint64_t) (val)) 271 272 #define write_el2_ctx_vhe_sysreg128(ctx, reg, val) ((((ctx)->vhe).reg) \ 273 = (sysreg_t) (val)) 274 #else 275 #define read_el2_ctx_vhe(ctx, reg) ULL(0) 276 #define write_el2_ctx_vhe(ctx, reg, val) 277 #endif /* ENABLE_FEAT_VHE */ 278 279 #if ENABLE_FEAT_RAS 280 #define read_el2_ctx_ras(ctx, reg) (((ctx)->ras).reg) 281 #define write_el2_ctx_ras(ctx, reg, val) ((((ctx)->ras).reg) \ 282 = (uint64_t) (val)) 283 #else 284 #define read_el2_ctx_ras(ctx, reg) ULL(0) 285 #define write_el2_ctx_ras(ctx, reg, val) 286 #endif /* ENABLE_FEAT_RAS */ 287 288 #if CTX_INCLUDE_NEVE_REGS 289 #define read_el2_ctx_neve(ctx, reg) (((ctx)->neve).reg) 290 #define write_el2_ctx_neve(ctx, reg, val) ((((ctx)->neve).reg) \ 291 = (uint64_t) (val)) 292 #else 293 #define read_el2_ctx_neve(ctx, reg) ULL(0) 294 #define write_el2_ctx_neve(ctx, reg, val) 295 #endif /* CTX_INCLUDE_NEVE_REGS */ 296 297 #if ENABLE_TRF_FOR_NS 298 #define read_el2_ctx_trf(ctx, reg) (((ctx)->trf).reg) 299 #define write_el2_ctx_trf(ctx, reg, val) ((((ctx)->trf).reg) \ 300 = (uint64_t) (val)) 301 #else 302 #define read_el2_ctx_trf(ctx, reg) ULL(0) 303 #define write_el2_ctx_trf(ctx, reg, val) 304 #endif /* ENABLE_TRF_FOR_NS */ 305 306 #if ENABLE_FEAT_CSV2_2 307 #define read_el2_ctx_csv2_2(ctx, reg) (((ctx)->csv2).reg) 308 #define write_el2_ctx_csv2_2(ctx, reg, val) ((((ctx)->csv2).reg) \ 309 = (uint64_t) (val)) 310 #else 311 #define read_el2_ctx_csv2_2(ctx, reg) ULL(0) 312 #define write_el2_ctx_csv2_2(ctx, reg, val) 313 #endif /* ENABLE_FEAT_CSV2_2 */ 314 315 #if ENABLE_FEAT_HCX 316 #define read_el2_ctx_hcx(ctx, reg) (((ctx)->hcx).reg) 317 #define write_el2_ctx_hcx(ctx, reg, val) ((((ctx)->hcx).reg) \ 318 = (uint64_t) (val)) 319 #else 320 #define read_el2_ctx_hcx(ctx, reg) ULL(0) 321 #define write_el2_ctx_hcx(ctx, reg, val) 322 #endif /* ENABLE_FEAT_HCX */ 323 324 #if ENABLE_FEAT_TCR2 325 #define read_el2_ctx_tcr2(ctx, reg) (((ctx)->tcr2).reg) 326 #define write_el2_ctx_tcr2(ctx, reg, val) ((((ctx)->tcr2).reg) \ 327 = (uint64_t) (val)) 328 #else 329 #define read_el2_ctx_tcr2(ctx, reg) ULL(0) 330 #define write_el2_ctx_tcr2(ctx, reg, val) 331 #endif /* ENABLE_FEAT_TCR2 */ 332 333 #if (ENABLE_FEAT_S1POE || ENABLE_FEAT_S2POE) 334 #define read_el2_ctx_sxpoe(ctx, reg) (((ctx)->sxpoe).reg) 335 #define write_el2_ctx_sxpoe(ctx, reg, val) ((((ctx)->sxpoe).reg) \ 336 = (uint64_t) (val)) 337 #else 338 #define read_el2_ctx_sxpoe(ctx, reg) ULL(0) 339 #define write_el2_ctx_sxpoe(ctx, reg, val) 340 #endif /*(ENABLE_FEAT_S1POE || ENABLE_FEAT_S2POE) */ 341 342 #if (ENABLE_FEAT_S1PIE || ENABLE_FEAT_S2PIE) 343 #define read_el2_ctx_sxpie(ctx, reg) (((ctx)->sxpie).reg) 344 #define write_el2_ctx_sxpie(ctx, reg, val) ((((ctx)->sxpie).reg) \ 345 = (uint64_t) (val)) 346 #else 347 #define read_el2_ctx_sxpie(ctx, reg) ULL(0) 348 #define write_el2_ctx_sxpie(ctx, reg, val) 349 #endif /*(ENABLE_FEAT_S1PIE || ENABLE_FEAT_S2PIE) */ 350 351 #if ENABLE_FEAT_S2PIE 352 #define read_el2_ctx_s2pie(ctx, reg) (((ctx)->s2pie).reg) 353 #define write_el2_ctx_s2pie(ctx, reg, val) ((((ctx)->s2pie).reg) \ 354 = (uint64_t) (val)) 355 #else 356 #define read_el2_ctx_s2pie(ctx, reg) ULL(0) 357 #define write_el2_ctx_s2pie(ctx, reg, val) 358 #endif /* ENABLE_FEAT_S2PIE */ 359 360 #if ENABLE_FEAT_GCS 361 #define read_el2_ctx_gcs(ctx, reg) (((ctx)->gcs).reg) 362 #define write_el2_ctx_gcs(ctx, reg, val) ((((ctx)->gcs).reg) \ 363 = (uint64_t) (val)) 364 #else 365 #define read_el2_ctx_gcs(ctx, reg) ULL(0) 366 #define write_el2_ctx_gcs(ctx, reg, val) 367 #endif /* ENABLE_FEAT_GCS */ 368 369 #if CTX_INCLUDE_MPAM_REGS 370 #define read_el2_ctx_mpam(ctx, reg) (((ctx)->mpam).reg) 371 #define write_el2_ctx_mpam(ctx, reg, val) ((((ctx)->mpam).reg) \ 372 = (uint64_t) (val)) 373 #else 374 #define read_el2_ctx_mpam(ctx, reg) ULL(0) 375 #define write_el2_ctx_mpam(ctx, reg, val) 376 #endif /* CTX_INCLUDE_MPAM_REGS */ 377 378 #if ENABLE_FEAT_SCTLR2 379 #define read_el2_ctx_sctlr2(ctx, reg) (((ctx)->sctlr2).reg) 380 #define write_el2_ctx_sctlr2(ctx, reg, val) ((((ctx)->sctlr2).reg) \ 381 = (uint64_t) (val)) 382 #else 383 #define read_el2_ctx_sctlr2(ctx, reg) ULL(0) 384 #define write_el2_ctx_sctlr2(ctx, reg, val) 385 #endif /* ENABLE_FEAT_SCTLR2 */ 386 387 /******************************************************************************/ 388 389 #endif /* __ASSEMBLER__ */ 390 391 #endif /* CONTEXT_EL2_H */ 392