1/* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#ifndef ARM_MACROS_S 7#define ARM_MACROS_S 8 9#include <drivers/arm/gic_common.h> 10#include <drivers/arm/gicv2.h> 11#include <drivers/arm/gicv3.h> 12#include <platform_def.h> 13 14.section .rodata.gic_reg_name, "aS" 15/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ 16gicc_regs: 17 .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 18 19/* Applicable only to GICv3 with SRE enabled */ 20icc_regs: 21 .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" 22 23/* Registers common to both GICv2 and GICv3 */ 24gicd_pend_reg: 25 .asciz "gicd_ispendr regs (Offsets 0x200-0x278)\nOffset\t\t\tValue\n" 26newline: 27 .asciz "\n" 28spacer: 29 .asciz ":\t\t 0x" 30prefix: 31 .asciz "0x" 32 33 /* --------------------------------------------- 34 * The below utility macro prints out relevant GIC 35 * registers whenever an unhandled exception is 36 * taken in BL31 on ARM standard platforms. 37 * Expects: GICD base in x16, GICC base in x17 38 * Clobbers: x0 - x10, sp 39 * --------------------------------------------- 40 */ 41 .macro arm_print_gic_regs 42 /* Check for GICv3/v4 system register access. 43 * ID_AA64PFR0_GIC indicates presence of the CPU 44 * system registers by either 0b0011 or 0xb0001. 45 * A value of 0b000 means CPU system registers aren't 46 * available and the code needs to use the memory 47 * mapped registers like in GICv2. 48 */ 49 mrs x7, id_aa64pfr0_el1 50 ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH 51 cmp x7, #0 52 b.eq print_gicv2 53 54 /* Check for SRE enable */ 55 mrs x8, ICC_SRE_EL3 56 tst x8, #ICC_SRE_SRE_BIT 57 b.eq print_gicv2 58 59 /* Load the icc reg list to x6 */ 60 adr x6, icc_regs 61 /* Load the icc regs to gp regs used by str_in_crash_buf_print */ 62 mrs x8, ICC_HPPIR0_EL1 63 mrs x9, ICC_HPPIR1_EL1 64 mrs x10, ICC_CTLR_EL3 65 /* Store to the crash buf and print to console */ 66 bl str_in_crash_buf_print 67 b print_gic_common 68 69print_gicv2: 70 /* Load the gicc reg list to x6 */ 71 adr x6, gicc_regs 72 /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 73 ldr w8, [x17, #GICC_HPPIR] 74 ldr w9, [x17, #GICC_AHPPIR] 75 ldr w10, [x17, #GICC_CTLR] 76 /* Store to the crash buf and print to console */ 77 bl str_in_crash_buf_print 78 79print_gic_common: 80 /* Print the GICD_ISPENDR regs */ 81 add x7, x16, #GICD_ISPENDR 82 adr x4, gicd_pend_reg 83 bl asm_print_str 84gicd_ispendr_loop: 85 sub x4, x7, x16 86 cmp x4, #0x280 87 b.eq exit_print_gic_regs 88 89 /* Print "0x" */ 90 adr x4, prefix 91 bl asm_print_str 92 93 /* Print offset */ 94 sub x4, x7, x16 95 mov x5, #12 96 bl asm_print_hex_bits 97 98 adr x4, spacer 99 bl asm_print_str 100 101 ldr x4, [x7], #8 102 bl asm_print_hex 103 104 adr x4, newline 105 bl asm_print_str 106 b gicd_ispendr_loop 107exit_print_gic_regs: 108 .endm 109 110#endif /* ARM_MACROS_S */ 111