1/* 2 * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a35.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14 /* --------------------------------------------- 15 * Disable L1 data cache and unified L2 cache 16 * --------------------------------------------- 17 */ 18func cortex_a35_disable_dcache 19 sysreg_bit_clear sctlr_el3, SCTLR_C_BIT 20 isb 21 ret 22endfunc cortex_a35_disable_dcache 23 24 /* --------------------------------------------- 25 * Disable intra-cluster coherency 26 * --------------------------------------------- 27 */ 28func cortex_a35_disable_smp 29 sysreg_bit_clear CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT 30 isb 31 dsb sy 32 ret 33endfunc cortex_a35_disable_smp 34 35workaround_reset_start cortex_a35, ERRATUM(855472), ERRATA_A35_855472 36 sysreg_bit_set CORTEX_A35_CPUACTLR_EL1, CORTEX_A35_CPUACTLR_EL1_ENDCCASCI 37workaround_reset_end cortex_a35, ERRATUM(855472) 38 39check_erratum_ls cortex_a35, ERRATUM(855472), CPU_REV(0, 0) 40 41 /* ------------------------------------------------- 42 * The CPU Ops reset function for Cortex-A35. 43 * ------------------------------------------------- 44 */ 45cpu_reset_func_start cortex_a35 46 /* --------------------------------------------- 47 * Enable the SMP bit. 48 * --------------------------------------------- 49 */ 50 sysreg_bit_set CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT 51cpu_reset_func_end cortex_a35 52 53func cortex_a35_core_pwr_dwn 54 mov x18, x30 55 56 /* --------------------------------------------- 57 * Turn off caches. 58 * --------------------------------------------- 59 */ 60 bl cortex_a35_disable_dcache 61 62 /* --------------------------------------------- 63 * Flush L1 caches. 64 * --------------------------------------------- 65 */ 66 mov x0, #DCCISW 67 bl dcsw_op_level1 68 69 /* --------------------------------------------- 70 * Come out of intra cluster coherency 71 * --------------------------------------------- 72 */ 73 mov x30, x18 74 b cortex_a35_disable_smp 75endfunc cortex_a35_core_pwr_dwn 76 77func cortex_a35_cluster_pwr_dwn 78 mov x18, x30 79 80 /* --------------------------------------------- 81 * Turn off caches. 82 * --------------------------------------------- 83 */ 84 bl cortex_a35_disable_dcache 85 86 /* --------------------------------------------- 87 * Flush L1 caches. 88 * --------------------------------------------- 89 */ 90 mov x0, #DCCISW 91 bl dcsw_op_level1 92 93 /* --------------------------------------------- 94 * Disable the optional ACP. 95 * --------------------------------------------- 96 */ 97 bl plat_disable_acp 98 99 /* --------------------------------------------- 100 * Flush L2 caches. 101 * --------------------------------------------- 102 */ 103 mov x0, #DCCISW 104 bl dcsw_op_level2 105 106 /* --------------------------------------------- 107 * Come out of intra cluster coherency 108 * --------------------------------------------- 109 */ 110 mov x30, x18 111 b cortex_a35_disable_smp 112endfunc cortex_a35_cluster_pwr_dwn 113 114 /* --------------------------------------------- 115 * This function provides cortex_a35 specific 116 * register information for crash reporting. 117 * It needs to return with x6 pointing to 118 * a list of register names in ascii and 119 * x8 - x15 having values of registers to be 120 * reported. 121 * --------------------------------------------- 122 */ 123.section .rodata.cortex_a35_regs, "aS" 124cortex_a35_regs: /* The ascii list of register names to be reported */ 125 .asciz "cpuectlr_el1", "" 126 127func cortex_a35_cpu_reg_dump 128 adr x6, cortex_a35_regs 129 mrs x8, CORTEX_A35_CPUECTLR_EL1 130 ret 131endfunc cortex_a35_cpu_reg_dump 132 133declare_cpu_ops cortex_a35, CORTEX_A35_MIDR, \ 134 cortex_a35_reset_func, \ 135 cortex_a35_core_pwr_dwn, \ 136 cortex_a35_cluster_pwr_dwn 137