1/* 2 * Copyright (c) 2023-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a510.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-A510 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24workaround_reset_start cortex_a510, ERRATUM(1922240), ERRATA_A510_1922240 25 /* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */ 26 sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE, \ 27 CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH 28workaround_reset_end cortex_a510, ERRATUM(1922240) 29 30check_erratum_ls cortex_a510, ERRATUM(1922240), CPU_REV(0, 0) 31 32workaround_reset_start cortex_a510, ERRATUM(2041909), ERRATA_A510_2041909 33 /* Apply workaround */ 34 mov x0, xzr 35 msr S3_6_C15_C4_0, x0 36 isb 37 38 mov x0, #0x8500000 39 msr S3_6_C15_C4_2, x0 40 41 mov x0, #0x1F700000 42 movk x0, #0x8, lsl #32 43 msr S3_6_C15_C4_3, x0 44 45 mov x0, #0x3F1 46 movk x0, #0x110, lsl #16 47 msr S3_6_C15_C4_1, x0 48workaround_reset_end cortex_a510, ERRATUM(2041909) 49 50check_erratum_range cortex_a510, ERRATUM(2041909), CPU_REV(0, 2), CPU_REV(0, 2) 51 52workaround_reset_start cortex_a510, ERRATUM(2042739), ERRATA_A510_2042739 53 /* Apply the workaround by disabling ReadPreferUnique. */ 54 sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE, \ 55 CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH 56workaround_reset_end cortex_a510, ERRATUM(2042739) 57 58check_erratum_ls cortex_a510, ERRATUM(2042739), CPU_REV(0, 2) 59 60workaround_reset_start cortex_a510, ERRATUM(2080326), ERRATA_A510_2080326 61 /* Apply workaround */ 62 mov x0, #1 63 msr S3_6_C15_C4_0, x0 64 isb 65 66 mov x0, #0x0100 67 movk x0, #0x0E08, lsl #16 68 msr S3_6_C15_C4_2, x0 69 70 mov x0, #0x0300 71 movk x0, #0x0F1F, lsl #16 72 movk x0, #0x0008, lsl #32 73 msr S3_6_C15_C4_3, x0 74 75 mov x0, #0x03F1 76 movk x0, #0x00C0, lsl #16 77 msr S3_6_C15_C4_1, x0 78 79 isb 80workaround_reset_end cortex_a510, ERRATUM(2080326) 81 82check_erratum_range cortex_a510, ERRATUM(2080326), CPU_REV(0, 2), CPU_REV(0, 2) 83 84workaround_reset_start cortex_a510, ERRATUM(2172148), ERRATA_A510_2172148 85 /* 86 * Force L2 allocation of transient lines by setting 87 * CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01. 88 */ 89 mrs x0, CORTEX_A510_CPUECTLR_EL1 90 mov x1, #1 91 bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2 92 bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2 93 msr CORTEX_A510_CPUECTLR_EL1, x0 94workaround_reset_end cortex_a510, ERRATUM(2172148) 95 96check_erratum_ls cortex_a510, ERRATUM(2172148), CPU_REV(1, 0) 97 98workaround_reset_start cortex_a510, ERRATUM(2218950), ERRATA_A510_2218950 99 /* Set bit 18 in CPUACTLR_EL1 */ 100 sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \ 101 CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH 102 103 /* Set bit 25 in CMPXACTLR_EL1 */ 104 sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \ 105 CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH 106 107workaround_reset_end cortex_a510, ERRATUM(2218950) 108 109check_erratum_ls cortex_a510, ERRATUM(2218950), CPU_REV(1, 0) 110 111 /* -------------------------------------------------- 112 * This workaround is not a typical errata fix. MPMM 113 * is disabled here, but this conflicts with the BL31 114 * MPMM support. So in addition to simply disabling 115 * the feature, a flag is set in the MPMM library 116 * indicating that it should not be enabled even if 117 * ENABLE_MPMM=1. 118 * -------------------------------------------------- 119 */ 120workaround_reset_start cortex_a510, ERRATUM(2250311), ERRATA_A510_2250311 121 /* Disable MPMM */ 122 mrs x0, CPUMPMMCR_EL3 123 bfm x0, xzr, #0, #0 /* bfc instruction does not work in GCC */ 124 msr CPUMPMMCR_EL3, x0 125 126#if ENABLE_MPMM && IMAGE_BL31 127 /* If ENABLE_MPMM is set, tell the runtime lib to skip enabling it. */ 128 bl mpmm_errata_disable 129#endif 130workaround_reset_end cortex_a510, ERRATUM(2250311) 131 132check_erratum_ls cortex_a510, ERRATUM(2250311), CPU_REV(1, 0) 133 134workaround_reset_start cortex_a510, ERRATUM(2288014), ERRATA_A510_2288014 135 /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */ 136 sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE, \ 137 CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH 138workaround_reset_end cortex_a510, ERRATUM(2288014) 139 140check_erratum_ls cortex_a510, ERRATUM(2288014), CPU_REV(1, 0) 141 142workaround_reset_start cortex_a510, ERRATUM(2347730), ERRATA_A510_2347730 143 /* 144 * Set CPUACTLR_EL1[17] to 1'b1, which disables 145 * specific microarchitectural clock gating 146 * behaviour. 147 */ 148 sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_17 149workaround_reset_end cortex_a510, ERRATUM(2347730) 150 151check_erratum_ls cortex_a510, ERRATUM(2347730), CPU_REV(1, 1) 152 153workaround_reset_start cortex_a510, ERRATUM(2371937), ERRATA_A510_2371937 154 /* 155 * Cacheable atomic operations can be forced 156 * to be executed near by setting 157 * IMP_CPUECTLR_EL1.ATOM=0b010. ATOM is found 158 * in [40:38] of CPUECTLR_EL1. 159 */ 160 sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR, \ 161 CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT, CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH 162workaround_reset_end cortex_a510, ERRATUM(2371937) 163 164check_erratum_ls cortex_a510, ERRATUM(2371937), CPU_REV(1, 1) 165 166workaround_reset_start cortex_a510, ERRATUM(2666669), ERRATA_A510_2666669 167 sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_38 168workaround_reset_end cortex_a510, ERRATUM(2666669) 169 170check_erratum_ls cortex_a510, ERRATUM(2666669), CPU_REV(1, 1) 171 172.global erratum_cortex_a510_2684597_wa 173workaround_runtime_start cortex_a510, ERRATUM(2684597), ERRATA_A510_2684597, CORTEX_A510_MIDR 174 /* 175 * Many assemblers do not yet understand the "tsb csync" mnemonic, 176 * so use the equivalent hint instruction. 177 */ 178 hint #18 /* tsb csync */ 179workaround_runtime_end cortex_a510, ERRATUM(2684597) 180 181check_erratum_ls cortex_a510, ERRATUM(2684597), CPU_REV(1, 2) 182 183/* 184 * ERRATA_DSU_2313941 : 185 * The errata is defined in dsu_helpers.S but applies to cortex_a510 186 * as well. Henceforth creating symbolic names to the already existing errata 187 * workaround functions to get them registered under the Errata Framework. 188 */ 189.equ check_erratum_cortex_a510_2313941, check_errata_dsu_2313941 190.equ erratum_cortex_a510_2313941_wa, errata_dsu_2313941_wa 191add_erratum_entry cortex_a510, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET 192 193 /* ---------------------------------------------------- 194 * HW will do the cache maintenance while powering down 195 * ---------------------------------------------------- 196 */ 197func cortex_a510_core_pwr_dwn 198 /* --------------------------------------------------- 199 * Enable CPU power down bit in power control register 200 * --------------------------------------------------- 201 */ 202 sysreg_bit_set CORTEX_A510_CPUPWRCTLR_EL1, CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 203 isb 204 ret 205endfunc cortex_a510_core_pwr_dwn 206 207cpu_reset_func_start cortex_a510 208 /* Disable speculative loads */ 209 msr SSBS, xzr 210cpu_reset_func_end cortex_a510 211 212 /* --------------------------------------------- 213 * This function provides Cortex-A510 specific 214 * register information for crash reporting. 215 * It needs to return with x6 pointing to 216 * a list of register names in ascii and 217 * x8 - x15 having values of registers to be 218 * reported. 219 * --------------------------------------------- 220 */ 221.section .rodata.cortex_a510_regs, "aS" 222cortex_a510_regs: /* The ascii list of register names to be reported */ 223 .asciz "cpuectlr_el1", "" 224 225func cortex_a510_cpu_reg_dump 226 adr x6, cortex_a510_regs 227 mrs x8, CORTEX_A510_CPUECTLR_EL1 228 ret 229endfunc cortex_a510_cpu_reg_dump 230 231declare_cpu_ops cortex_a510, CORTEX_A510_MIDR, \ 232 cortex_a510_reset_func, \ 233 cortex_a510_core_pwr_dwn 234