1/* 2 * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <common/bl_common.h> 9#include <common/debug.h> 10#include <cortex_a53.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include <lib/cpus/errata.h> 14 15 /* --------------------------------------------- 16 * Disable L1 data cache and unified L2 cache 17 * --------------------------------------------- 18 */ 19func cortex_a53_disable_dcache 20 sysreg_bit_clear sctlr_el3, SCTLR_C_BIT 21 isb 22 ret 23endfunc cortex_a53_disable_dcache 24 25 /* --------------------------------------------- 26 * Disable intra-cluster coherency 27 * --------------------------------------------- 28 */ 29func cortex_a53_disable_smp 30 sysreg_bit_clear CORTEX_A53_ECTLR_EL1, CORTEX_A53_ECTLR_SMP_BIT 31 isb 32 dsb sy 33 ret 34endfunc cortex_a53_disable_smp 35 36/* Due to the nature of the errata it is applied unconditionally when chosen */ 37check_erratum_ls cortex_a53, ERRATUM(819472), CPU_REV(0, 1) 38/* erratum workaround is interleaved with generic code */ 39add_erratum_entry cortex_a53, ERRATUM(819472), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET 40 41/* Due to the nature of the errata it is applied unconditionally when chosen */ 42check_erratum_ls cortex_a53, ERRATUM(824069), CPU_REV(0, 2) 43/* erratum workaround is interleaved with generic code */ 44add_erratum_entry cortex_a53, ERRATUM(824069), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET 45 46workaround_reset_start cortex_a53, ERRATUM(826319), ERRATA_A53_826319 47 mrs x1, CORTEX_A53_L2ACTLR_EL1 48 bic x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN 49 orr x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH 50 msr CORTEX_A53_L2ACTLR_EL1, x1 51workaround_reset_end cortex_a53, ERRATUM(826319) 52 53check_erratum_ls cortex_a53, ERRATUM(826319), CPU_REV(0, 2) 54 55/* Due to the nature of the errata it is applied unconditionally when chosen */ 56check_erratum_ls cortex_a53, ERRATUM(827319), CPU_REV(0, 2) 57/* erratum workaround is interleaved with generic code */ 58add_erratum_entry cortex_a53, ERRATUM(827319), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET 59 60check_erratum_custom_start cortex_a53, ERRATUM(835769) 61 cmp x0, CPU_REV(0, 4) 62 b.hi errata_not_applies 63 /* 64 * Fix potentially available for revisions r0p2, r0p3 and r0p4. 65 * If r0p2, r0p3 or r0p4; check for fix in REVIDR, else exit. 66 */ 67 cmp x0, #0x01 68 mov x0, #ERRATA_APPLIES 69 b.ls exit_check_errata_835769 70 /* Load REVIDR. */ 71 mrs x1, revidr_el1 72 /* If REVIDR[7] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */ 73 tbz x1, #7, exit_check_errata_835769 74errata_not_applies: 75 mov x0, #ERRATA_NOT_APPLIES 76exit_check_errata_835769: 77 ret 78check_erratum_custom_end cortex_a53, ERRATUM(835769) 79 80/* workaround at build time */ 81add_erratum_entry cortex_a53, ERRATUM(835769), ERRATA_A53_835769, NO_APPLY_AT_RESET 82 83 /* 84 * Disable the cache non-temporal hint. 85 * 86 * This ignores the Transient allocation hint in the MAIR and treats 87 * allocations the same as non-transient allocation types. As a result, 88 * the LDNP and STNP instructions in AArch64 behave the same as the 89 * equivalent LDP and STP instructions. 90 */ 91workaround_reset_start cortex_a53, ERRATUM(836870), ERRATA_A53_836870 | A53_DISABLE_NON_TEMPORAL_HINT 92 sysreg_bit_set CORTEX_A53_CPUACTLR_EL1, CORTEX_A53_CPUACTLR_EL1_DTAH 93workaround_reset_end cortex_a53, ERRATUM(836870) 94 95check_erratum_ls cortex_a53, ERRATUM(836870), CPU_REV(0, 3) 96 97check_erratum_custom_start cortex_a53, ERRATUM(843419) 98 mov x1, #ERRATA_APPLIES 99 mov x2, #ERRATA_NOT_APPLIES 100 cmp x0, CPU_REV(0, 4) 101 csel x0, x1, x2, ls 102 /* 103 * Fix potentially available for revision r0p4. 104 * If r0p4 check for fix in REVIDR, else exit. 105 */ 106 b.ne exit_check_errata_843419 107 /* Load REVIDR. */ 108 mrs x3, revidr_el1 109 /* If REVIDR[8] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */ 110 tbz x3, #8, exit_check_errata_843419 111 mov x0, x2 112exit_check_errata_843419: 113 ret 114check_erratum_custom_end cortex_a53, ERRATUM(843419) 115 116/* workaround at build time */ 117add_erratum_entry cortex_a53, ERRATUM(843419), ERRATA_A53_843419, NO_APPLY_AT_RESET 118 119 /* 120 * Earlier revisions of the core are affected as well, but don't 121 * have the chicken bit in the CPUACTLR register. It is expected that 122 * the rich OS takes care of that, especially as the workaround is 123 * shared with other erratas in those revisions of the CPU. 124 */ 125workaround_reset_start cortex_a53, ERRATUM(855873), ERRATA_A53_855873 126 sysreg_bit_set CORTEX_A53_CPUACTLR_EL1, CORTEX_A53_CPUACTLR_EL1_ENDCCASCI 127workaround_reset_end cortex_a53, ERRATUM(855873) 128 129check_erratum_hs cortex_a53, ERRATUM(855873), CPU_REV(0, 3) 130 131check_erratum_chosen cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924 132 133/* erratum has no workaround in the cpu. Generic code must take care */ 134add_erratum_entry cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924, NO_APPLY_AT_RESET 135 136cpu_reset_func_start cortex_a53 137 /* Enable the SMP bit. */ 138 sysreg_bit_set CORTEX_A53_ECTLR_EL1, CORTEX_A53_ECTLR_SMP_BIT 139cpu_reset_func_end cortex_a53 140 141func cortex_a53_core_pwr_dwn 142 mov x18, x30 143 144 /* --------------------------------------------- 145 * Turn off caches. 146 * --------------------------------------------- 147 */ 148 bl cortex_a53_disable_dcache 149 150 /* --------------------------------------------- 151 * Flush L1 caches. 152 * --------------------------------------------- 153 */ 154 mov x0, #DCCISW 155 bl dcsw_op_level1 156 157 /* --------------------------------------------- 158 * Come out of intra cluster coherency 159 * --------------------------------------------- 160 */ 161 mov x30, x18 162 b cortex_a53_disable_smp 163endfunc cortex_a53_core_pwr_dwn 164 165func cortex_a53_cluster_pwr_dwn 166 mov x18, x30 167 168 /* --------------------------------------------- 169 * Turn off caches. 170 * --------------------------------------------- 171 */ 172 bl cortex_a53_disable_dcache 173 174 /* --------------------------------------------- 175 * Flush L1 caches. 176 * --------------------------------------------- 177 */ 178 mov x0, #DCCISW 179 bl dcsw_op_level1 180 181 /* --------------------------------------------- 182 * Disable the optional ACP. 183 * --------------------------------------------- 184 */ 185 bl plat_disable_acp 186 187 /* --------------------------------------------- 188 * Flush L2 caches. 189 * --------------------------------------------- 190 */ 191 mov x0, #DCCISW 192 bl dcsw_op_level2 193 194 /* --------------------------------------------- 195 * Come out of intra cluster coherency 196 * --------------------------------------------- 197 */ 198 mov x30, x18 199 b cortex_a53_disable_smp 200endfunc cortex_a53_cluster_pwr_dwn 201 202 /* --------------------------------------------- 203 * This function provides cortex_a53 specific 204 * register information for crash reporting. 205 * It needs to return with x6 pointing to 206 * a list of register names in ascii and 207 * x8 - x15 having values of registers to be 208 * reported. 209 * --------------------------------------------- 210 */ 211.section .rodata.cortex_a53_regs, "aS" 212cortex_a53_regs: /* The ascii list of register names to be reported */ 213 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", \ 214 "cpuactlr_el1", "" 215 216func cortex_a53_cpu_reg_dump 217 adr x6, cortex_a53_regs 218 mrs x8, CORTEX_A53_ECTLR_EL1 219 mrs x9, CORTEX_A53_MERRSR_EL1 220 mrs x10, CORTEX_A53_L2MERRSR_EL1 221 mrs x11, CORTEX_A53_CPUACTLR_EL1 222 ret 223endfunc cortex_a53_cpu_reg_dump 224 225declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \ 226 cortex_a53_reset_func, \ 227 cortex_a53_core_pwr_dwn, \ 228 cortex_a53_cluster_pwr_dwn 229