1/* 2 * Copyright (c) 2019-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <common/debug.h> 11#include <cortex_a65.h> 12#include <cpu_macros.S> 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if !HW_ASSISTED_COHERENCY 17#error "Cortex-A65 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS 22#error "Cortex-A65 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25/* ------------------------------------------------- 26 * The CPU Ops reset function for Cortex-A65. 27 * Shall clobber: x0-x19 28 * ------------------------------------------------- 29 */ 30func cortex_a65_reset_func 31 mov x19, x30 32 33#if ERRATA_DSU_936184 34 bl errata_dsu_936184_wa 35#endif 36 37 ret x19 38endfunc cortex_a65_reset_func 39 40func cortex_a65_cpu_pwr_dwn 41 mrs x0, CORTEX_A65_CPUPWRCTLR_EL1 42 orr x0, x0, #CORTEX_A65_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 43 msr CORTEX_A65_CPUPWRCTLR_EL1, x0 44 isb 45 ret 46endfunc cortex_a65_cpu_pwr_dwn 47 48 49.section .rodata.cortex_a65_regs, "aS" 50cortex_a65_regs: /* The ascii list of register names to be reported */ 51 .asciz "cpuectlr_el1", "" 52 53func cortex_a65_cpu_reg_dump 54 adr x6, cortex_a65_regs 55 mrs x8, CORTEX_A65_ECTLR_EL1 56 ret 57endfunc cortex_a65_cpu_reg_dump 58 59declare_cpu_ops cortex_a65, CORTEX_A65_MIDR, \ 60 cortex_a65_reset_func, \ 61 cortex_a65_cpu_pwr_dwn 62