1/* 2 * Copyright (c) 2019-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <common/debug.h> 11#include <cortex_a65ae.h> 12#include <cpu_macros.S> 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if !HW_ASSISTED_COHERENCY 17#error "Cortex-A65AE must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS 22#error "Cortex-A65AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25 /* 26 * ERRATA_DSU_936184 : 27 * The errata is defined in dsu_helpers.S but applies to cortex_a65ae 28 * as well. Henceforth creating symbolic names to the already existing errata 29 * workaround functions to get them registered under the Errata Framework. 30 */ 31.equ check_erratum_cortex_a65ae_936184, check_errata_dsu_936184 32.equ erratum_cortex_a65ae_936184_wa, errata_dsu_936184_wa 33add_erratum_entry cortex_a65ae, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET 34 35cpu_reset_func_start cortex_a65ae 36cpu_reset_func_end cortex_a65ae 37 38func cortex_a65ae_cpu_pwr_dwn 39 sysreg_bit_set CORTEX_A65AE_CPUPWRCTLR_EL1, CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 40 isb 41 ret 42endfunc cortex_a65ae_cpu_pwr_dwn 43 44.section .rodata.cortex_a65ae_regs, "aS" 45cortex_a65ae_regs: /* The ascii list of register names to be reported */ 46 .asciz "cpuectlr_el1", "" 47 48func cortex_a65ae_cpu_reg_dump 49 adr x6, cortex_a65ae_regs 50 mrs x8, CORTEX_A65AE_ECTLR_EL1 51 ret 52endfunc cortex_a65ae_cpu_reg_dump 53 54declare_cpu_ops cortex_a65ae, CORTEX_A65AE_MIDR, \ 55 cortex_a65ae_reset_func, \ 56 cortex_a65ae_cpu_pwr_dwn 57