1/* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <cortex_a72.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12#include "wa_cve_2022_23960_bhb_vector.S" 13 14#if WORKAROUND_CVE_2022_23960 15 wa_cve_2022_23960_bhb_vector_table CORTEX_A72_BHB_LOOP_COUNT, cortex_a72 16#endif /* WORKAROUND_CVE_2022_23960 */ 17 18 /* --------------------------------------------- 19 * Disable L1 data cache and unified L2 cache 20 * --------------------------------------------- 21 */ 22func cortex_a72_disable_dcache 23 mrs x1, sctlr_el3 24 bic x1, x1, #SCTLR_C_BIT 25 msr sctlr_el3, x1 26 isb 27 ret 28endfunc cortex_a72_disable_dcache 29 30 /* --------------------------------------------- 31 * Disable all types of L2 prefetches. 32 * --------------------------------------------- 33 */ 34func cortex_a72_disable_l2_prefetch 35 mrs x0, CORTEX_A72_ECTLR_EL1 36 orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT 37 mov x1, #CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK 38 orr x1, x1, #CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK 39 bic x0, x0, x1 40 msr CORTEX_A72_ECTLR_EL1, x0 41 isb 42 ret 43endfunc cortex_a72_disable_l2_prefetch 44 45 /* --------------------------------------------- 46 * Disable the load-store hardware prefetcher. 47 * --------------------------------------------- 48 */ 49func cortex_a72_disable_hw_prefetcher 50 sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH 51 isb 52 dsb ish 53 ret 54endfunc cortex_a72_disable_hw_prefetcher 55 56 /* --------------------------------------------- 57 * Disable intra-cluster coherency 58 * --------------------------------------------- 59 */ 60func cortex_a72_disable_smp 61 sysreg_bit_clear CORTEX_A72_ECTLR_EL1, CORTEX_A72_ECTLR_SMP_BIT 62 ret 63endfunc cortex_a72_disable_smp 64 65 /* --------------------------------------------- 66 * Disable debug interfaces 67 * --------------------------------------------- 68 */ 69func cortex_a72_disable_ext_debug 70 mov x0, #1 71 msr osdlr_el1, x0 72 isb 73 dsb sy 74 ret 75endfunc cortex_a72_disable_ext_debug 76 77func check_smccc_arch_workaround_3 78 cpu_check_csv2 x0, 1f 79 mov x0, #ERRATA_APPLIES 80 ret 811: 82 mov x0, #ERRATA_NOT_APPLIES 83 ret 84endfunc check_smccc_arch_workaround_3 85 86workaround_reset_start cortex_a72, ERRATUM(859971), ERRATA_A72_859971 87 sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH 88workaround_reset_end cortex_a72, ERRATUM(859971) 89 90check_erratum_ls cortex_a72, ERRATUM(859971), CPU_REV(0, 3) 91 92/* Due to the nature of the errata it is applied unconditionally when chosen */ 93check_erratum_chosen cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367 94/* erratum workaround is interleaved with generic code */ 95add_erratum_entry cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367, NO_APPLY_AT_RESET 96 97workaround_reset_start cortex_a72, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 98#if IMAGE_BL31 99 override_vector_table wa_cve_2017_5715_mmu_vbar 100#endif 101workaround_reset_end cortex_a72, CVE(2017, 5715) 102 103check_erratum_custom_start cortex_a72, CVE(2017, 5715) 104 cpu_check_csv2 x0, 1f 105#if WORKAROUND_CVE_2017_5715 106 mov x0, #ERRATA_APPLIES 107#else 108 mov x0, #ERRATA_MISSING 109#endif 110 ret 1111: 112 mov x0, #ERRATA_NOT_APPLIES 113 ret 114check_erratum_custom_end cortex_a72, CVE(2017, 5715) 115 116workaround_reset_start cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 117 sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE 118 isb 119 dsb sy 120workaround_reset_end cortex_a72, CVE(2018, 3639) 121check_erratum_chosen cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 122 123workaround_reset_start cortex_a72, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 124#if IMAGE_BL31 125 /* Skip installing vector table again if already done for CVE(2017, 5715) */ 126 /* 127 * The Cortex-A72 generic vectors are overridden to apply the 128 * mitigation on exception entry from lower ELs for revisions >= r1p0 129 * which has CSV2 implemented. 130 */ 131 adr x0, wa_cve_vbar_cortex_a72 132 mrs x1, vbar_el3 133 cmp x0, x1 134 b.eq 1f 135 msr vbar_el3, x0 1361: 137#endif /* IMAGE_BL31 */ 138workaround_reset_end cortex_a72, CVE(2022, 23960) 139 140check_erratum_custom_start cortex_a72, CVE(2022, 23960) 141#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 142 cpu_check_csv2 x0, 1f 143 mov x0, #ERRATA_APPLIES 144 ret 1451: 146#if WORKAROUND_CVE_2022_23960 147 mov x0, #ERRATA_APPLIES 148#else 149 mov x0, #ERRATA_MISSING 150#endif /* WORKAROUND_CVE_2022_23960 */ 151 ret 152#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ 153 mov x0, #ERRATA_MISSING 154 ret 155check_erratum_custom_end cortex_a72, CVE(2022, 23960) 156 157cpu_reset_func_start cortex_a72 158 159 /* --------------------------------------------- 160 * Enable the SMP bit. 161 * --------------------------------------------- 162 */ 163 sysreg_bit_set CORTEX_A72_ECTLR_EL1, CORTEX_A72_ECTLR_SMP_BIT 164 165cpu_reset_func_end cortex_a72 166 167 /* ---------------------------------------------------- 168 * The CPU Ops core power down function for Cortex-A72. 169 * ---------------------------------------------------- 170 */ 171func cortex_a72_core_pwr_dwn 172 mov x18, x30 173 174 /* --------------------------------------------- 175 * Turn off caches. 176 * --------------------------------------------- 177 */ 178 bl cortex_a72_disable_dcache 179 180 /* --------------------------------------------- 181 * Disable the L2 prefetches. 182 * --------------------------------------------- 183 */ 184 bl cortex_a72_disable_l2_prefetch 185 186 /* --------------------------------------------- 187 * Disable the load-store hardware prefetcher. 188 * --------------------------------------------- 189 */ 190 bl cortex_a72_disable_hw_prefetcher 191 192 /* --------------------------------------------- 193 * Flush L1 caches. 194 * --------------------------------------------- 195 */ 196 mov x0, #DCCISW 197 bl dcsw_op_level1 198 199 /* --------------------------------------------- 200 * Come out of intra cluster coherency 201 * --------------------------------------------- 202 */ 203 bl cortex_a72_disable_smp 204 205 /* --------------------------------------------- 206 * Force the debug interfaces to be quiescent 207 * --------------------------------------------- 208 */ 209 mov x30, x18 210 b cortex_a72_disable_ext_debug 211endfunc cortex_a72_core_pwr_dwn 212 213 /* ------------------------------------------------------- 214 * The CPU Ops cluster power down function for Cortex-A72. 215 * ------------------------------------------------------- 216 */ 217func cortex_a72_cluster_pwr_dwn 218 mov x18, x30 219 220 /* --------------------------------------------- 221 * Turn off caches. 222 * --------------------------------------------- 223 */ 224 bl cortex_a72_disable_dcache 225 226 /* --------------------------------------------- 227 * Disable the L2 prefetches. 228 * --------------------------------------------- 229 */ 230 bl cortex_a72_disable_l2_prefetch 231 232 /* --------------------------------------------- 233 * Disable the load-store hardware prefetcher. 234 * --------------------------------------------- 235 */ 236 bl cortex_a72_disable_hw_prefetcher 237 238#if !SKIP_A72_L1_FLUSH_PWR_DWN 239 /* --------------------------------------------- 240 * Flush L1 caches. 241 * --------------------------------------------- 242 */ 243 mov x0, #DCCISW 244 bl dcsw_op_level1 245#endif 246 247 /* --------------------------------------------- 248 * Disable the optional ACP. 249 * --------------------------------------------- 250 */ 251 bl plat_disable_acp 252 253 /* ------------------------------------------------- 254 * Flush the L2 caches. 255 * ------------------------------------------------- 256 */ 257 mov x0, #DCCISW 258 bl dcsw_op_level2 259 260 /* --------------------------------------------- 261 * Come out of intra cluster coherency 262 * --------------------------------------------- 263 */ 264 bl cortex_a72_disable_smp 265 266 /* --------------------------------------------- 267 * Force the debug interfaces to be quiescent 268 * --------------------------------------------- 269 */ 270 mov x30, x18 271 b cortex_a72_disable_ext_debug 272endfunc cortex_a72_cluster_pwr_dwn 273 274 /* --------------------------------------------- 275 * This function provides cortex_a72 specific 276 * register information for crash reporting. 277 * It needs to return with x6 pointing to 278 * a list of register names in ascii and 279 * x8 - x15 having values of registers to be 280 * reported. 281 * --------------------------------------------- 282 */ 283.section .rodata.cortex_a72_regs, "aS" 284cortex_a72_regs: /* The ascii list of register names to be reported */ 285 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" 286 287func cortex_a72_cpu_reg_dump 288 adr x6, cortex_a72_regs 289 mrs x8, CORTEX_A72_ECTLR_EL1 290 mrs x9, CORTEX_A72_MERRSR_EL1 291 mrs x10, CORTEX_A72_L2MERRSR_EL1 292 ret 293endfunc cortex_a72_cpu_reg_dump 294 295declare_cpu_ops_wa cortex_a72, CORTEX_A72_MIDR, \ 296 cortex_a72_reset_func, \ 297 check_erratum_cortex_a72_5715, \ 298 CPU_NO_EXTRA2_FUNC, \ 299 check_smccc_arch_workaround_3, \ 300 cortex_a72_core_pwr_dwn, \ 301 cortex_a72_cluster_pwr_dwn 302