1/* 2 * Copyright (c) 2021-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a720.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex A720 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex A720 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29workaround_reset_start cortex_a720, ERRATUM(2792132), ERRATA_A720_2792132 30 sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(26) 31workaround_reset_end cortex_a720, ERRATUM(2792132) 32 33check_erratum_ls cortex_a720, ERRATUM(2792132), CPU_REV(0, 1) 34 35workaround_reset_start cortex_a720, ERRATUM(2844092), ERRATA_A720_2844092 36 sysreg_bit_set CORTEX_A720_CPUACTLR4_EL1, BIT(11) 37workaround_reset_end cortex_a720, ERRATUM(2844092) 38 39check_erratum_ls cortex_a720, ERRATUM(2844092), CPU_REV(0, 1) 40 41workaround_reset_start cortex_a720, ERRATUM(2926083), ERRATA_A720_2926083 42/* Erratum 2926083 workaround is required only if SPE is enabled */ 43#if ENABLE_SPE_FOR_NS != 0 44 /* Check if Static profiling extension is implemented or present. */ 45 mrs x1, id_aa64dfr0_el1 46 ubfx x0, x1, ID_AA64DFR0_PMS_SHIFT, #4 47 cbz x0, 1f 48 /* Apply the workaround by setting CPUACTLR_EL1[58:57] = 0b11. */ 49 sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, BIT(57) 50 sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, BIT(58) 511: 52#endif 53workaround_reset_end cortex_a720, ERRATUM(2926083) 54 55check_erratum_ls cortex_a720, ERRATUM(2926083), CPU_REV(0, 1) 56 57workaround_reset_start cortex_a720, ERRATUM(2940794), ERRATA_A720_2940794 58 sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(37) 59workaround_reset_end cortex_a720, ERRATUM(2940794) 60 61check_erratum_ls cortex_a720, ERRATUM(2940794), CPU_REV(0, 1) 62 63workaround_reset_start cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 64#if IMAGE_BL31 65 /* 66 * The Cortex A720 generic vectors are overridden to apply errata 67 * mitigation on exception entry from lower ELs. 68 */ 69 override_vector_table wa_cve_vbar_cortex_a720 70#endif /* IMAGE_BL31 */ 71workaround_reset_end cortex_a720, CVE(2022, 23960) 72 73check_erratum_chosen cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 74 75cpu_reset_func_start cortex_a720 76 /* Disable speculative loads */ 77 msr SSBS, xzr 78cpu_reset_func_end cortex_a720 79 80 /* ---------------------------------------------------- 81 * HW will do the cache maintenance while powering down 82 * ---------------------------------------------------- 83 */ 84func cortex_a720_core_pwr_dwn 85 /* --------------------------------------------------- 86 * Enable CPU power down bit in power control register 87 * --------------------------------------------------- 88 */ 89 sysreg_bit_set CORTEX_A720_CPUPWRCTLR_EL1, CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 90 91 isb 92 ret 93endfunc cortex_a720_core_pwr_dwn 94 95 /* --------------------------------------------- 96 * This function provides Cortex A720-specific 97 * register information for crash reporting. 98 * It needs to return with x6 pointing to 99 * a list of register names in ascii and 100 * x8 - x15 having values of registers to be 101 * reported. 102 * --------------------------------------------- 103 */ 104.section .rodata.cortex_a720_regs, "aS" 105cortex_a720_regs: /* The ascii list of register names to be reported */ 106 .asciz "cpuectlr_el1", "" 107 108func cortex_a720_cpu_reg_dump 109 adr x6, cortex_a720_regs 110 mrs x8, CORTEX_A720_CPUECTLR_EL1 111 ret 112endfunc cortex_a720_cpu_reg_dump 113 114declare_cpu_ops cortex_a720, CORTEX_A720_MIDR, \ 115 cortex_a720_reset_func, \ 116 cortex_a720_core_pwr_dwn 117