1/* 2 * Copyright (c) 2023-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a725.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-A725 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-A725 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24cpu_reset_func_start cortex_a725 25 /* Disable speculative loads */ 26 msr SSBS, xzr 27cpu_reset_func_end cortex_a725 28 29 /* ---------------------------------------------------- 30 * HW will do the cache maintenance while powering down 31 * ---------------------------------------------------- 32 */ 33func cortex_a725_core_pwr_dwn 34 /* --------------------------------------------------- 35 * Enable CPU power down bit in power control register 36 * --------------------------------------------------- 37 */ 38 sysreg_bit_set CORTEX_A725_CPUPWRCTLR_EL1, CORTEX_A725_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 39 isb 40 ret 41endfunc cortex_a725_core_pwr_dwn 42 43 /* --------------------------------------------- 44 * This function provides Cortex-A725 specific 45 * register information for crash reporting. 46 * It needs to return with x6 pointing to 47 * a list of register names in ascii and 48 * x8 - x15 having values of registers to be 49 * reported. 50 * --------------------------------------------- 51 */ 52.section .rodata.cortex_a725_regs, "aS" 53cortex_a725_regs: /* The ascii list of register names to be reported */ 54 .asciz "cpuectlr_el1", "" 55 56func cortex_a725_cpu_reg_dump 57 adr x6, cortex_a725_regs 58 mrs x8, CORTEX_A725_CPUECTLR_EL1 59 ret 60endfunc cortex_a725_cpu_reg_dump 61 62declare_cpu_ops cortex_a725, CORTEX_A725_MIDR, \ 63 cortex_a725_reset_func, \ 64 cortex_a725_core_pwr_dwn 65