1/* 2 * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <common/bl_common.h> 9#include <cortex_a73.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12 13 /* --------------------------------------------- 14 * Disable L1 data cache 15 * --------------------------------------------- 16 */ 17func cortex_a73_disable_dcache 18 sysreg_bit_clear sctlr_el3, SCTLR_C_BIT 19 isb 20 ret 21endfunc cortex_a73_disable_dcache 22 23 /* --------------------------------------------- 24 * Disable intra-cluster coherency 25 * --------------------------------------------- 26 */ 27func cortex_a73_disable_smp 28 sysreg_bit_clear CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT 29 isb 30 dsb sy 31 ret 32endfunc cortex_a73_disable_smp 33 34func check_smccc_arch_workaround_3 35 mov x0, #ERRATA_APPLIES 36 ret 37endfunc check_smccc_arch_workaround_3 38 39workaround_reset_start cortex_a73, ERRATUM(852427), ERRATA_A73_852427 40 sysreg_bit_set CORTEX_A73_DIAGNOSTIC_REGISTER, BIT(12) 41workaround_reset_end cortex_a73, ERRATUM(852427) 42 43check_erratum_ls cortex_a73, ERRATUM(852427), CPU_REV(0, 0) 44 45workaround_reset_start cortex_a73, ERRATUM(855423), ERRATA_A73_855423 46 sysreg_bit_set CORTEX_A73_IMP_DEF_REG2, BIT(7) 47workaround_reset_end cortex_a73, ERRATUM(855423) 48 49check_erratum_ls cortex_a73, ERRATUM(855423), CPU_REV(0, 1) 50 51workaround_reset_start cortex_a73, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 52#if IMAGE_BL31 53 override_vector_table wa_cve_2017_5715_bpiall_vbar 54#endif /* IMAGE_BL31 */ 55workaround_reset_end cortex_a73, CVE(2017, 5715) 56 57check_erratum_custom_start cortex_a73, CVE(2017, 5715) 58 cpu_check_csv2 x0, 1f 59#if WORKAROUND_CVE_2017_5715 60 mov x0, #ERRATA_APPLIES 61#else 62 mov x0, #ERRATA_MISSING 63#endif 64 ret 651: 66 mov x0, #ERRATA_NOT_APPLIES 67 ret 68check_erratum_custom_end cortex_a73, CVE(2017, 5715) 69 70workaround_reset_start cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 71 sysreg_bit_set CORTEX_A73_IMP_DEF_REG1, CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE 72workaround_reset_end cortex_a73, CVE(2018, 3639) 73 74check_erratum_chosen cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 75 76workaround_reset_start cortex_a73, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 77#if IMAGE_BL31 78 /* Skip installing vector table again for CVE_2022_23960 */ 79 adr x0, wa_cve_2017_5715_bpiall_vbar 80 mrs x1, vbar_el3 81 82 cmp x0, x1 83 b.eq 1f 84 msr vbar_el3, x0 851: 86#endif /* IMAGE_BL31 */ 87workaround_reset_end cortex_a73, CVE(2022, 23960) 88 89check_erratum_custom_start cortex_a73, CVE(2022, 23960) 90#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 91 cpu_check_csv2 x0, 1f 92 mov x0, #ERRATA_APPLIES 93 ret 94 1: 95#if WORKAROUND_CVE_2022_23960 96 mov x0, #ERRATA_APPLIES 97#else 98 mov x0, #ERRATA_MISSING 99#endif /* WORKAROUND_CVE_2022_23960 */ 100 ret 101#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ 102 mov x0, #ERRATA_MISSING 103 ret 104check_erratum_custom_end cortex_a73, CVE(2022, 23960) 105 106 /* ------------------------------------------------- 107 * The CPU Ops reset function for Cortex-A73. 108 * ------------------------------------------------- 109 */ 110 111cpu_reset_func_start cortex_a73 112 /* --------------------------------------------- 113 * Enable the SMP bit. 114 * Clobbers : x0 115 * --------------------------------------------- 116 */ 117 sysreg_bit_set CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT 118cpu_reset_func_end cortex_a73 119 120func cortex_a73_core_pwr_dwn 121 mov x18, x30 122 123 /* --------------------------------------------- 124 * Turn off caches. 125 * --------------------------------------------- 126 */ 127 bl cortex_a73_disable_dcache 128 129 /* --------------------------------------------- 130 * Flush L1 caches. 131 * --------------------------------------------- 132 */ 133 mov x0, #DCCISW 134 bl dcsw_op_level1 135 136 /* --------------------------------------------- 137 * Come out of intra cluster coherency 138 * --------------------------------------------- 139 */ 140 mov x30, x18 141 b cortex_a73_disable_smp 142endfunc cortex_a73_core_pwr_dwn 143 144func cortex_a73_cluster_pwr_dwn 145 mov x18, x30 146 147 /* --------------------------------------------- 148 * Turn off caches. 149 * --------------------------------------------- 150 */ 151 bl cortex_a73_disable_dcache 152 153 /* --------------------------------------------- 154 * Flush L1 caches. 155 * --------------------------------------------- 156 */ 157 mov x0, #DCCISW 158 bl dcsw_op_level1 159 160 /* --------------------------------------------- 161 * Disable the optional ACP. 162 * --------------------------------------------- 163 */ 164 bl plat_disable_acp 165 166 /* --------------------------------------------- 167 * Flush L2 caches. 168 * --------------------------------------------- 169 */ 170 mov x0, #DCCISW 171 bl dcsw_op_level2 172 173 /* --------------------------------------------- 174 * Come out of intra cluster coherency 175 * --------------------------------------------- 176 */ 177 mov x30, x18 178 b cortex_a73_disable_smp 179endfunc cortex_a73_cluster_pwr_dwn 180 181 /* --------------------------------------------- 182 * This function provides cortex_a73 specific 183 * register information for crash reporting. 184 * It needs to return with x6 pointing to 185 * a list of register names in ascii and 186 * x8 - x15 having values of registers to be 187 * reported. 188 * --------------------------------------------- 189 */ 190.section .rodata.cortex_a73_regs, "aS" 191cortex_a73_regs: /* The ascii list of register names to be reported */ 192 .asciz "cpuectlr_el1", "l2merrsr_el1", "" 193 194func cortex_a73_cpu_reg_dump 195 adr x6, cortex_a73_regs 196 mrs x8, CORTEX_A73_CPUECTLR_EL1 197 mrs x9, CORTEX_A73_L2MERRSR_EL1 198 ret 199endfunc cortex_a73_cpu_reg_dump 200 201declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \ 202 cortex_a73_reset_func, \ 203 check_erratum_cortex_a73_5715, \ 204 CPU_NO_EXTRA2_FUNC, \ 205 check_smccc_arch_workaround_3, \ 206 cortex_a73_core_pwr_dwn, \ 207 cortex_a73_cluster_pwr_dwn 208