1/* 2 * Copyright (c) 2019-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a76ae.h> 11#include <cpu_macros.S> 12#include "wa_cve_2022_23960_bhb_vector.S" 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-A76AE must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-A76AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24#if WORKAROUND_CVE_2022_23960 25 wa_cve_2022_23960_bhb_vector_table CORTEX_A76AE_BHB_LOOP_COUNT, cortex_a76ae 26#endif /* WORKAROUND_CVE_2022_23960 */ 27 28check_erratum_chosen cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 29 30workaround_reset_start cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 31#if IMAGE_BL31 32 /* 33 * The Cortex-A76ae generic vectors are overridden to apply errata 34 * mitigation on exception entry from lower ELs. 35 */ 36 override_vector_table wa_cve_vbar_cortex_a76ae 37 isb 38#endif /* IMAGE_BL31 */ 39workaround_reset_end cortex_a76ae, CVE(2022, 23960) 40 41cpu_reset_func_start cortex_a76ae 42cpu_reset_func_end cortex_a76ae 43 44 /* ---------------------------------------------------- 45 * HW will do the cache maintenance while powering down 46 * ---------------------------------------------------- 47 */ 48func cortex_a76ae_core_pwr_dwn 49 sysreg_bit_set CORTEX_A76AE_CPUPWRCTLR_EL1, CORTEX_A76AE_CORE_PWRDN_EN_MASK 50 isb 51 ret 52endfunc cortex_a76ae_core_pwr_dwn 53 54 /* --------------------------------------------- 55 * This function provides cortex_a76ae specific 56 * register information for crash reporting. 57 * It needs to return with x6 pointing to 58 * a list of register names in ascii and 59 * x8 - x15 having values of registers to be 60 * reported. 61 * --------------------------------------------- 62 */ 63.section .rodata.cortex_a76ae_regs, "aS" 64cortex_a76ae_regs: /* The ASCII list of register names to be reported */ 65 .asciz "cpuectlr_el1", "" 66 67func cortex_a76ae_cpu_reg_dump 68 adr x6, cortex_a76ae_regs 69 mrs x8, CORTEX_A76AE_CPUECTLR_EL1 70 ret 71endfunc cortex_a76ae_cpu_reg_dump 72 73declare_cpu_ops cortex_a76ae, CORTEX_A76AE_MIDR, cortex_a76ae_reset_func, \ 74 cortex_a76ae_core_pwr_dwn 75