1/* 2 * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a77.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A77_BHB_LOOP_COUNT, cortex_a77 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29workaround_reset_start cortex_a77, ERRATUM(1508412), ERRATA_A77_1508412 30 /* move cpu revision in again and compare against r0p0 */ 31 mov x0, x7 32 mov x1, #CPU_REV(0, 0) 33 bl cpu_rev_var_ls 34 cbz x0, 1f 35 36 ldr x0, =0x0 37 msr CORTEX_A77_CPUPSELR_EL3, x0 38 ldr x0, =0x00E8400000 39 msr CORTEX_A77_CPUPOR_EL3, x0 40 ldr x0, =0x00FFE00000 41 msr CORTEX_A77_CPUPMR_EL3, x0 42 ldr x0, =0x4004003FF 43 msr CORTEX_A77_CPUPCR_EL3, x0 44 ldr x0, =0x1 45 msr CORTEX_A77_CPUPSELR_EL3, x0 46 ldr x0, =0x00E8C00040 47 msr CORTEX_A77_CPUPOR_EL3, x0 48 ldr x0, =0x00FFE00040 49 msr CORTEX_A77_CPUPMR_EL3, x0 50 b 2f 511: 52 ldr x0, =0x0 53 msr CORTEX_A77_CPUPSELR_EL3, x0 54 ldr x0, =0x00E8400000 55 msr CORTEX_A77_CPUPOR_EL3, x0 56 ldr x0, =0x00FF600000 57 msr CORTEX_A77_CPUPMR_EL3, x0 58 ldr x0, =0x00E8E00080 59 msr CORTEX_A77_CPUPOR2_EL3, x0 60 ldr x0, =0x00FFE000C0 61 msr CORTEX_A77_CPUPMR2_EL3, x0 622: 63 ldr x0, =0x04004003FF 64 msr CORTEX_A77_CPUPCR_EL3, x0 65workaround_reset_end cortex_a77, ERRATUM(1508412) 66 67check_erratum_ls cortex_a77, ERRATUM(1508412), CPU_REV(1, 0) 68 69workaround_reset_start cortex_a77, ERRATUM(1791578), ERRATA_A77_1791578 70 sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_2 71workaround_reset_end cortex_a77, ERRATUM(1791578) 72 73check_erratum_ls cortex_a77, ERRATUM(1791578), CPU_REV(1, 1) 74 75workaround_reset_start cortex_a77, ERRATUM(1800714), ERRATA_A77_1800714 76 /* Disable allocation of splintered pages in the L2 TLB */ 77 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_53 78workaround_reset_end cortex_a77, ERRATUM(1800714) 79 80check_erratum_ls cortex_a77, ERRATUM(1800714), CPU_REV(1, 1) 81 82workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769 83 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8 84workaround_reset_end cortex_a77, ERRATUM(1925769) 85 86check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1) 87 88workaround_reset_start cortex_a77, ERRATUM(1946167), ERRATA_A77_1946167 89 ldr x0,=0x4 90 msr CORTEX_A77_CPUPSELR_EL3,x0 91 ldr x0,=0x10E3900002 92 msr CORTEX_A77_CPUPOR_EL3,x0 93 ldr x0,=0x10FFF00083 94 msr CORTEX_A77_CPUPMR_EL3,x0 95 ldr x0,=0x2001003FF 96 msr CORTEX_A77_CPUPCR_EL3,x0 97 98 ldr x0,=0x5 99 msr CORTEX_A77_CPUPSELR_EL3,x0 100 ldr x0,=0x10E3800082 101 msr CORTEX_A77_CPUPOR_EL3,x0 102 ldr x0,=0x10FFF00083 103 msr CORTEX_A77_CPUPMR_EL3,x0 104 ldr x0,=0x2001003FF 105 msr CORTEX_A77_CPUPCR_EL3,x0 106 107 ldr x0,=0x6 108 msr CORTEX_A77_CPUPSELR_EL3,x0 109 ldr x0,=0x10E3800200 110 msr CORTEX_A77_CPUPOR_EL3,x0 111 ldr x0,=0x10FFF003E0 112 msr CORTEX_A77_CPUPMR_EL3,x0 113 ldr x0,=0x2001003FF 114 msr CORTEX_A77_CPUPCR_EL3,x0 115workaround_reset_end cortex_a77, ERRATUM(1946167) 116 117check_erratum_ls cortex_a77, ERRATUM(1946167), CPU_REV(1, 1) 118 119workaround_reset_start cortex_a77, ERRATUM(2356587), ERRATA_A77_2356587 120 sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_0 121workaround_reset_end cortex_a77, ERRATUM(2356587) 122 123check_erratum_ls cortex_a77, ERRATUM(2356587), CPU_REV(1, 1) 124 125workaround_runtime_start cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100 126 /* dsb before isb of power down sequence */ 127 dsb sy 128workaround_runtime_end cortex_a77, ERRATUM(2743100), NO_ISB 129 130check_erratum_ls cortex_a77, ERRATUM(2743100), CPU_REV(1, 1) 131 132workaround_reset_start cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 133#if IMAGE_BL31 134 /* 135 * The Cortex-A77 generic vectors are overridden to apply errata 136 * mitigation on exception entry from lower ELs. 137 */ 138 adr x0, wa_cve_vbar_cortex_a77 139 msr vbar_el3, x0 140#endif /* IMAGE_BL31 */ 141workaround_reset_end cortex_a77, CVE(2022, 23960) 142 143check_erratum_chosen cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 144 145 /* ------------------------------------------------- 146 * The CPU Ops reset function for Cortex-A77. Must follow AAPCS. 147 * ------------------------------------------------- 148 */ 149cpu_reset_func_start cortex_a77 150cpu_reset_func_end cortex_a77 151 152 /* --------------------------------------------- 153 * HW will do the cache maintenance while powering down 154 * --------------------------------------------- 155 */ 156func cortex_a77_core_pwr_dwn 157 /* --------------------------------------------- 158 * Enable CPU power down bit in power control register 159 * --------------------------------------------- 160 */ 161 sysreg_bit_set CORTEX_A77_CPUPWRCTLR_EL1, \ 162 CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 163 164 apply_erratum cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100, NO_GET_CPU_REV 165 166 isb 167 ret 168endfunc cortex_a77_core_pwr_dwn 169 170 /* --------------------------------------------- 171 * This function provides Cortex-A77 specific 172 * register information for crash reporting. 173 * It needs to return with x6 pointing to 174 * a list of register names in ascii and 175 * x8 - x15 having values of registers to be 176 * reported. 177 * --------------------------------------------- 178 */ 179.section .rodata.cortex_a77_regs, "aS" 180cortex_a77_regs: /* The ascii list of register names to be reported */ 181 .asciz "cpuectlr_el1", "" 182 183func cortex_a77_cpu_reg_dump 184 adr x6, cortex_a77_regs 185 mrs x8, CORTEX_A77_CPUECTLR_EL1 186 ret 187endfunc cortex_a77_cpu_reg_dump 188 189declare_cpu_ops cortex_a77, CORTEX_A77_MIDR, \ 190 cortex_a77_reset_func, \ 191 cortex_a77_core_pwr_dwn 192