1/* 2 * Copyright (c) 2021-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x2.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765 30 ldr x0, =0x6 31 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */ 32 ldr x0, =0xF3A08002 33 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */ 34 ldr x0, =0xFFF0F7FE 35 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */ 36 ldr x0, =0x40000001003ff 37 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */ 38workaround_reset_end cortex_x2, ERRATUM(2002765) 39 40check_erratum_ls cortex_x2, ERRATUM(2002765), CPU_REV(2, 0) 41 42workaround_reset_start cortex_x2, ERRATUM(2017096), ERRATA_X2_2017096 43 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT 44workaround_reset_end cortex_x2, ERRATUM(2017096) 45 46check_erratum_ls cortex_x2, ERRATUM(2017096), CPU_REV(2, 0) 47 48workaround_reset_start cortex_x2, ERRATUM(2058056), ERRATA_X2_2058056 49 sysreg_bitfield_insert CORTEX_X2_CPUECTLR2_EL1, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV, \ 50 CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH 51workaround_reset_end cortex_x2, ERRATUM(2058056) 52 53check_erratum_ls cortex_x2, ERRATUM(2058056), CPU_REV(2, 1) 54 55workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180 56 /* Apply instruction patching sequence */ 57 ldr x0, =0x3 58 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 59 ldr x0, =0xF3A08002 60 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 61 ldr x0, =0xFFF0F7FE 62 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 63 ldr x0, =0x10002001003FF 64 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 65 ldr x0, =0x4 66 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 67 ldr x0, =0xBF200000 68 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 69 ldr x0, =0xFFEF0000 70 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 71 ldr x0, =0x10002001003F3 72 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 73workaround_reset_end cortex_x2, ERRATUM(2081180) 74 75check_erratum_ls cortex_x2, ERRATUM(2081180), CPU_REV(2, 0) 76 77workaround_reset_start cortex_x2, ERRATUM(2083908), ERRATA_X2_2083908 78 /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */ 79 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(13) 80workaround_reset_end cortex_x2, ERRATUM(2083908) 81 82check_erratum_range cortex_x2, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 83 84workaround_reset_start cortex_x2, ERRATUM(2147715), ERRATA_X2_2147715 85 /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */ 86 sysreg_bit_set CORTEX_X2_CPUACTLR_EL1, CORTEX_X2_CPUACTLR_EL1_BIT_22 87workaround_reset_end cortex_x2, ERRATUM(2147715) 88 89check_erratum_range cortex_x2, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 90 91workaround_reset_start cortex_x2, ERRATUM(2216384), ERRATA_X2_2216384 92 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, CORTEX_X2_CPUACTLR5_EL1_BIT_17 93 94 /* Apply instruction patching sequence */ 95 ldr x0, =0x5 96 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 97 ldr x0, =0x10F600E000 98 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 99 ldr x0, =0x10FF80E000 100 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 101 ldr x0, =0x80000000003FF 102 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 103workaround_reset_end cortex_x2, ERRATUM(2216384) 104 105check_erratum_ls cortex_x2, ERRATUM(2216384), CPU_REV(2, 0) 106 107workaround_reset_start cortex_x2, ERRATUM(2282622), ERRATA_X2_2282622 108 /* Apply the workaround */ 109 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, BIT(0) 110workaround_reset_end cortex_x2, ERRATUM(2282622) 111 112check_erratum_ls cortex_x2, ERRATUM(2282622), CPU_REV(2, 1) 113 114workaround_reset_start cortex_x2, ERRATUM(2371105), ERRATA_X2_2371105 115 /* Set bit 40 in CPUACTLR2_EL1 */ 116 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, CORTEX_X2_CPUACTLR2_EL1_BIT_40 117workaround_reset_end cortex_x2, ERRATUM(2371105) 118 119check_erratum_ls cortex_x2, ERRATUM(2371105), CPU_REV(2, 0) 120 121workaround_reset_start cortex_x2, ERRATUM(2742423), ERRATA_X2_2742423 122 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 123 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(55) 124 sysreg_bit_clear CORTEX_X2_CPUACTLR5_EL1, BIT(56) 125workaround_reset_end cortex_x2, ERRATUM(2742423) 126 127check_erratum_ls cortex_x2, ERRATUM(2742423), CPU_REV(2, 1) 128 129workaround_runtime_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515 130 /* dsb before isb of power down sequence */ 131 dsb sy 132workaround_runtime_end cortex_x2, ERRATUM(2768515) 133 134check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1) 135 136workaround_reset_start cortex_x2, ERRATUM(2778471), ERRATA_X2_2778471 137 sysreg_bit_set CORTEX_X2_CPUACTLR3_EL1, BIT(47) 138workaround_reset_end cortex_x2, ERRATUM(2778471) 139 140check_erratum_ls cortex_x2, ERRATUM(2778471), CPU_REV(2, 1) 141 142workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 143#if IMAGE_BL31 144 /* 145 * The Cortex-X2 generic vectors are overridden to apply errata 146 * mitigation on exception entry from lower ELs. 147 */ 148 override_vector_table wa_cve_vbar_cortex_x2 149#endif /* IMAGE_BL31 */ 150workaround_reset_end cortex_x2, CVE(2022, 23960) 151 152check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 153 154/* 155 * ERRATA_DSU_2313941 : 156 * The errata is defined in dsu_helpers.S but applies to cortex_x2 157 * as well. Henceforth creating symbolic names to the already existing errata 158 * workaround functions to get them registered under the Errata Framework. 159 */ 160.equ check_erratum_cortex_x2_2313941, check_errata_dsu_2313941 161.equ erratum_cortex_x2_2313941_wa, errata_dsu_2313941_wa 162add_erratum_entry cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET 163 164 /* ---------------------------------------------------- 165 * HW will do the cache maintenance while powering down 166 * ---------------------------------------------------- 167 */ 168func cortex_x2_core_pwr_dwn 169 /* --------------------------------------------------- 170 * Enable CPU power down bit in power control register 171 * --------------------------------------------------- 172 */ 173 sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 174 175 apply_erratum cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515, NO_GET_CPU_REV 176 isb 177 ret 178endfunc cortex_x2_core_pwr_dwn 179 180cpu_reset_func_start cortex_x2 181 /* Disable speculative loads */ 182 msr SSBS, xzr 183cpu_reset_func_end cortex_x2 184 185 /* --------------------------------------------- 186 * This function provides Cortex X2 specific 187 * register information for crash reporting. 188 * It needs to return with x6 pointing to 189 * a list of register names in ascii and 190 * x8 - x15 having values of registers to be 191 * reported. 192 * --------------------------------------------- 193 */ 194.section .rodata.cortex_x2_regs, "aS" 195cortex_x2_regs: /* The ascii list of register names to be reported */ 196 .asciz "cpuectlr_el1", "" 197 198func cortex_x2_cpu_reg_dump 199 adr x6, cortex_x2_regs 200 mrs x8, CORTEX_X2_CPUECTLR_EL1 201 ret 202endfunc cortex_x2_cpu_reg_dump 203 204declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \ 205 cortex_x2_reset_func, \ 206 cortex_x2_core_pwr_dwn 207