1/* 2 * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <common/bl_common.h> 9#include <common/debug.h> 10#include <neoverse_e1.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse E1 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24/* 25 * ERRATA_DSU_936184: 26 * The errata is defined in dsu_helpers.S and applies to neoverse_e1. 27 * Henceforth creating symbolic names to the already existing errata 28 * workaround functions to get them registered under the Errata Framework. 29 */ 30.equ check_erratum_neoverse_e1_936184, check_errata_dsu_936184 31.equ erratum_neoverse_e1_936184_wa, errata_dsu_936184_wa 32add_erratum_entry neoverse_e1, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET 33 34cpu_reset_func_start neoverse_e1 35cpu_reset_func_end neoverse_e1 36 37func neoverse_e1_cpu_pwr_dwn 38 mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1 39 orr x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 40 msr NEOVERSE_E1_CPUPWRCTLR_EL1, x0 41 isb 42 ret 43endfunc neoverse_e1_cpu_pwr_dwn 44 45.section .rodata.neoverse_e1_regs, "aS" 46neoverse_e1_regs: /* The ascii list of register names to be reported */ 47 .asciz "cpuectlr_el1", "" 48 49func neoverse_e1_cpu_reg_dump 50 adr x6, neoverse_e1_regs 51 mrs x8, NEOVERSE_E1_ECTLR_EL1 52 ret 53endfunc neoverse_e1_cpu_reg_dump 54 55declare_cpu_ops neoverse_e1, NEOVERSE_E1_MIDR, \ 56 neoverse_e1_reset_func, \ 57 neoverse_e1_cpu_pwr_dwn 58