1/* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <assert_macros.S> 10#include <context.h> 11#include <el3_common_macros.S> 12#include <platform_def.h> 13 14#if CTX_INCLUDE_FPREGS 15 .global fpregs_context_save 16 .global fpregs_context_restore 17#endif /* CTX_INCLUDE_FPREGS */ 18 19#if CTX_INCLUDE_SVE_REGS 20 .global sve_context_save 21 .global sve_context_restore 22#endif /* CTX_INCLUDE_SVE_REGS */ 23 24#if ERRATA_SPECULATIVE_AT 25 .global save_and_update_ptw_el1_sys_regs 26#endif /* ERRATA_SPECULATIVE_AT */ 27 28 .global prepare_el3_entry 29 .global restore_gp_pmcr_pauth_regs 30 .global el3_exit 31 32/* Following macros will be used if any of CTX_INCLUDE_FPREGS or CTX_INCLUDE_SVE_REGS is enabled */ 33#if CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS 34.macro fpregs_state_save base:req hold:req 35 mrs \hold, fpsr 36 str \hold, [\base, #CTX_SIMD_FPSR] 37 38 mrs \hold, fpcr 39 str \hold, [\base, #CTX_SIMD_FPCR] 40 41#if CTX_INCLUDE_AARCH32_REGS && CTX_INCLUDE_FPREGS 42 mrs \hold, fpexc32_el2 43 str \hold, [\base, #CTX_SIMD_FPEXC32] 44#endif 45.endm 46 47.macro fpregs_state_restore base:req hold:req 48 ldr \hold, [\base, #CTX_SIMD_FPSR] 49 msr fpsr, \hold 50 51 ldr \hold, [\base, #CTX_SIMD_FPCR] 52 msr fpcr, \hold 53 54#if CTX_INCLUDE_AARCH32_REGS && CTX_INCLUDE_FPREGS 55 ldr \hold, [\base, #CTX_SIMD_FPEXC32] 56 msr fpexc32_el2, \hold 57#endif 58.endm 59 60#endif /* CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS */ 61 62/* ------------------------------------------------------------------ 63 * The following function follows the aapcs_64 strictly to use 64 * x9-x17 (temporary caller-saved registers according to AArch64 PCS) 65 * to save floating point register context. It assumes that 'x0' is 66 * pointing to a 'fp_regs' structure where the register context will 67 * be saved. 68 * 69 * Access to VFP registers will trap if CPTR_EL3.TFP is set. 70 * However currently we don't use VFP registers nor set traps in 71 * Trusted Firmware, and assume it's cleared. 72 * 73 * TODO: Revisit when VFP is used in secure world 74 * ------------------------------------------------------------------ 75 */ 76#if CTX_INCLUDE_FPREGS 77func fpregs_context_save 78.arch_extension fp 79 /* Temporarily enable floating point */ 80 stp q0, q1, [x0], #32 81 stp q2, q3, [x0], #32 82 stp q4, q5, [x0], #32 83 stp q6, q7, [x0], #32 84 stp q8, q9, [x0], #32 85 stp q10, q11, [x0], #32 86 stp q12, q13, [x0], #32 87 stp q14, q15, [x0], #32 88 stp q16, q17, [x0], #32 89 stp q18, q19, [x0], #32 90 stp q20, q21, [x0], #32 91 stp q22, q23, [x0], #32 92 stp q24, q25, [x0], #32 93 stp q26, q27, [x0], #32 94 stp q28, q29, [x0], #32 95 stp q30, q31, [x0], #32 96 97 # Reset x0 back to the base of simd_regs_t 98 # because the macro use CTX_SIMD_* offsets from x0 99 sub x0, x0, #(16 * 32) 100 fpregs_state_save x0, x9 101.arch_extension nofp 102 103 ret 104endfunc fpregs_context_save 105 106/* ------------------------------------------------------------------ 107 * The following function follows the aapcs_64 strictly to use x9-x17 108 * (temporary caller-saved registers according to AArch64 PCS) to 109 * restore floating point register context. It assumes that 'x0' is 110 * pointing to a 'fp_regs' structure from where the register context 111 * will be restored. 112 * 113 * Access to VFP registers will trap if CPTR_EL3.TFP is set. 114 * However currently we don't use VFP registers nor set traps in 115 * Trusted Firmware, and assume it's cleared. 116 * 117 * TODO: Revisit when VFP is used in secure world 118 * ------------------------------------------------------------------ 119 */ 120func fpregs_context_restore 121.arch_extension fp 122 /* Temporarily enable floating point */ 123 ldp q0, q1, [x0], #32 124 ldp q2, q3, [x0], #32 125 ldp q4, q5, [x0], #32 126 ldp q6, q7, [x0], #32 127 ldp q8, q9, [x0], #32 128 ldp q10, q11, [x0], #32 129 ldp q12, q13, [x0], #32 130 ldp q14, q15, [x0], #32 131 ldp q16, q17, [x0], #32 132 ldp q18, q19, [x0], #32 133 ldp q20, q21, [x0], #32 134 ldp q22, q23, [x0], #32 135 ldp q24, q25, [x0], #32 136 ldp q26, q27, [x0], #32 137 ldp q28, q29, [x0], #32 138 ldp q30, q31, [x0], #32 139 140 # Reset x0 back to the base of simd_regs_t 141 # because the macro use CTX_SIMD_* offsets from x0 142 sub x0, x0, #(16 * 32) 143 fpregs_state_restore x0, x9 144.arch_extension nofp 145 146 ret 147endfunc fpregs_context_restore 148#endif /* CTX_INCLUDE_FPREGS */ 149 150#if CTX_INCLUDE_SVE_REGS 151/* 152 * Helper macros for SVE predicates save/restore operations. 153 */ 154.macro sve_predicate_op op:req reg:req 155 \op p0, [\reg, #0, MUL VL] 156 \op p1, [\reg, #1, MUL VL] 157 \op p2, [\reg, #2, MUL VL] 158 \op p3, [\reg, #3, MUL VL] 159 \op p4, [\reg, #4, MUL VL] 160 \op p5, [\reg, #5, MUL VL] 161 \op p6, [\reg, #6, MUL VL] 162 \op p7, [\reg, #7, MUL VL] 163 \op p8, [\reg, #8, MUL VL] 164 \op p9, [\reg, #9, MUL VL] 165 \op p10, [\reg, #10, MUL VL] 166 \op p11, [\reg, #11, MUL VL] 167 \op p12, [\reg, #12, MUL VL] 168 \op p13, [\reg, #13, MUL VL] 169 \op p14, [\reg, #14, MUL VL] 170 \op p15, [\reg, #15, MUL VL] 171.endm 172 173.macro sve_vectors_op op:req reg:req 174 \op z0, [\reg, #0, MUL VL] 175 \op z1, [\reg, #1, MUL VL] 176 \op z2, [\reg, #2, MUL VL] 177 \op z3, [\reg, #3, MUL VL] 178 \op z4, [\reg, #4, MUL VL] 179 \op z5, [\reg, #5, MUL VL] 180 \op z6, [\reg, #6, MUL VL] 181 \op z7, [\reg, #7, MUL VL] 182 \op z8, [\reg, #8, MUL VL] 183 \op z9, [\reg, #9, MUL VL] 184 \op z10, [\reg, #10, MUL VL] 185 \op z11, [\reg, #11, MUL VL] 186 \op z12, [\reg, #12, MUL VL] 187 \op z13, [\reg, #13, MUL VL] 188 \op z14, [\reg, #14, MUL VL] 189 \op z15, [\reg, #15, MUL VL] 190 \op z16, [\reg, #16, MUL VL] 191 \op z17, [\reg, #17, MUL VL] 192 \op z18, [\reg, #18, MUL VL] 193 \op z19, [\reg, #19, MUL VL] 194 \op z20, [\reg, #20, MUL VL] 195 \op z21, [\reg, #21, MUL VL] 196 \op z22, [\reg, #22, MUL VL] 197 \op z23, [\reg, #23, MUL VL] 198 \op z24, [\reg, #24, MUL VL] 199 \op z25, [\reg, #25, MUL VL] 200 \op z26, [\reg, #26, MUL VL] 201 \op z27, [\reg, #27, MUL VL] 202 \op z28, [\reg, #28, MUL VL] 203 \op z29, [\reg, #29, MUL VL] 204 \op z30, [\reg, #30, MUL VL] 205 \op z31, [\reg, #31, MUL VL] 206.endm 207 208/* ------------------------------------------------------------------ 209 * The following function follows the aapcs_64 strictly to use x9-x17 210 * (temporary caller-saved registers according to AArch64 PCS) to 211 * restore SVE register context. It assumes that 'x0' is 212 * pointing to a 'sve_regs_t' structure to which the register context 213 * will be saved. 214 * ------------------------------------------------------------------ 215 */ 216func sve_context_save 217.arch_extension sve 218 /* Temporarily enable SVE */ 219 mrs x10, cptr_el3 220 orr x11, x10, #CPTR_EZ_BIT 221 bic x11, x11, #TFP_BIT 222 msr cptr_el3, x11 223 isb 224 225 /* zcr_el3 */ 226 mrs x12, S3_6_C1_C2_0 227 mov x13, #((SVE_VECTOR_LEN >> 7) - 1) 228 msr S3_6_C1_C2_0, x13 229 isb 230 231 /* Predicate registers */ 232 mov x13, #CTX_SIMD_PREDICATES 233 add x9, x0, x13 234 sve_predicate_op str, x9 235 236 /* Save FFR after predicates */ 237 mov x13, #CTX_SIMD_FFR 238 add x9, x0, x13 239 rdffr p0.b 240 str p0, [x9] 241 242 /* Save vector registers */ 243 mov x13, #CTX_SIMD_VECTORS 244 add x9, x0, x13 245 sve_vectors_op str, x9 246 247 /* Restore SVE enablement */ 248 msr S3_6_C1_C2_0, x12 /* zcr_el3 */ 249 msr cptr_el3, x10 250 isb 251.arch_extension nosve 252 253 /* Save FPSR, FPCR and FPEXC32 */ 254 fpregs_state_save x0, x9 255 256 ret 257endfunc sve_context_save 258 259/* ------------------------------------------------------------------ 260 * The following function follows the aapcs_64 strictly to use x9-x17 261 * (temporary caller-saved registers according to AArch64 PCS) to 262 * restore SVE register context. It assumes that 'x0' is pointing to 263 * a 'sve_regs_t' structure from where the register context will be 264 * restored. 265 * ------------------------------------------------------------------ 266 */ 267func sve_context_restore 268.arch_extension sve 269 /* Temporarily enable SVE for EL3 */ 270 mrs x10, cptr_el3 271 orr x11, x10, #CPTR_EZ_BIT 272 bic x11, x11, #TFP_BIT 273 msr cptr_el3, x11 274 isb 275 276 /* zcr_el3 */ 277 mrs x12, S3_6_C1_C2_0 278 mov x13, #((SVE_VECTOR_LEN >> 7) - 1) 279 msr S3_6_C1_C2_0, x13 280 isb 281 282 /* Restore FFR register before predicates */ 283 mov x13, #CTX_SIMD_FFR 284 add x9, x0, x13 285 ldr p0, [x9] 286 wrffr p0.b 287 288 /* Restore predicate registers */ 289 mov x13, #CTX_SIMD_PREDICATES 290 add x9, x0, x13 291 sve_predicate_op ldr, x9 292 293 /* Restore vector registers */ 294 mov x13, #CTX_SIMD_VECTORS 295 add x9, x0, x13 296 sve_vectors_op ldr, x9 297 298 /* Restore SVE enablement */ 299 msr S3_6_C1_C2_0, x12 /* zcr_el3 */ 300 msr cptr_el3, x10 301 isb 302.arch_extension nosve 303 304 /* Restore FPSR, FPCR and FPEXC32 */ 305 fpregs_state_restore x0, x9 306 ret 307endfunc sve_context_restore 308#endif /* CTX_INCLUDE_SVE_REGS */ 309 310 /* 311 * Set SCR_EL3.EA bit to enable SErrors at EL3 312 */ 313 .macro enable_serror_at_el3 314 mrs x8, scr_el3 315 orr x8, x8, #SCR_EA_BIT 316 msr scr_el3, x8 317 .endm 318 319 /* 320 * Set the PSTATE bits not set when the exception was taken as 321 * described in the AArch64.TakeException() pseudocode function 322 * in ARM DDI 0487F.c page J1-7635 to a default value. 323 */ 324 .macro set_unset_pstate_bits 325 /* 326 * If Data Independent Timing (DIT) functionality is implemented, 327 * always enable DIT in EL3 328 */ 329#if ENABLE_FEAT_DIT 330#if ENABLE_FEAT_DIT >= 2 331 mrs x8, id_aa64pfr0_el1 332 and x8, x8, #(ID_AA64PFR0_DIT_MASK << ID_AA64PFR0_DIT_SHIFT) 333 cbz x8, 1f 334#endif 335 mov x8, #DIT_BIT 336 msr DIT, x8 3371: 338#endif /* ENABLE_FEAT_DIT */ 339 .endm /* set_unset_pstate_bits */ 340 341/*------------------------------------------------------------------------- 342 * This macro checks the ENABLE_FEAT_MPAM state, performs ID register 343 * check to see if the platform supports MPAM extension and restores MPAM3 344 * register value if it is FEAT_STATE_ENABLED/FEAT_STATE_CHECKED. 345 * 346 * This is particularly more complicated because we can't check 347 * if the platform supports MPAM by looking for status of a particular bit 348 * in the MDCR_EL3 or CPTR_EL3 register like other extensions. 349 * ------------------------------------------------------------------------ 350 */ 351 352 .macro restore_mpam3_el3 353#if ENABLE_FEAT_MPAM 354#if ENABLE_FEAT_MPAM >= 2 355 mrs x8, id_aa64pfr0_el1 356 lsr x8, x8, #(ID_AA64PFR0_MPAM_SHIFT) 357 and x8, x8, #(ID_AA64PFR0_MPAM_MASK) 358 mrs x7, id_aa64pfr1_el1 359 lsr x7, x7, #(ID_AA64PFR1_MPAM_FRAC_SHIFT) 360 and x7, x7, #(ID_AA64PFR1_MPAM_FRAC_MASK) 361 orr x7, x7, x8 362 cbz x7, no_mpam 363#endif 364 /* ----------------------------------------------------------- 365 * Restore MPAM3_EL3 register as per context state 366 * Currently we only enable MPAM for NS world and trap to EL3 367 * for MPAM access in lower ELs of Secure and Realm world 368 * x9 holds address of the per_world context 369 * ----------------------------------------------------------- 370 */ 371 372 ldr x17, [x9, #CTX_MPAM3_EL3] 373 msr S3_6_C10_C5_0, x17 /* mpam3_el3 */ 374 375no_mpam: 376#endif 377 .endm /* restore_mpam3_el3 */ 378 379/* ------------------------------------------------------------------ 380 * The following macro is used to save and restore all the general 381 * purpose and ARMv8.3-PAuth (if enabled) registers. 382 * It also checks if the Secure Cycle Counter (PMCCNTR_EL0) 383 * is disabled in EL3/Secure (ARMv8.5-PMU), wherein PMCCNTR_EL0 384 * needs not to be saved/restored during world switch. 385 * 386 * Ideally we would only save and restore the callee saved registers 387 * when a world switch occurs but that type of implementation is more 388 * complex. So currently we will always save and restore these 389 * registers on entry and exit of EL3. 390 * clobbers: x18 391 * ------------------------------------------------------------------ 392 */ 393 .macro save_gp_pmcr_pauth_regs 394 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 395 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 396 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 397 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 398 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 399 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 400 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 401 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 402 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 403 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 404 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 405 stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 406 stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 407 stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 408 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 409 mrs x18, sp_el0 410 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 411 412 /* PMUv3 is presumed to be always present */ 413 mrs x9, pmcr_el0 414 str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] 415 isb 416#if CTX_INCLUDE_PAUTH_REGS 417 /* ---------------------------------------------------------- 418 * Save the ARMv8.3-PAuth keys as they are not banked 419 * by exception level 420 * ---------------------------------------------------------- 421 */ 422 add x19, sp, #CTX_PAUTH_REGS_OFFSET 423 424 mrs x20, APIAKeyLo_EL1 /* x21:x20 = APIAKey */ 425 mrs x21, APIAKeyHi_EL1 426 mrs x22, APIBKeyLo_EL1 /* x23:x22 = APIBKey */ 427 mrs x23, APIBKeyHi_EL1 428 mrs x24, APDAKeyLo_EL1 /* x25:x24 = APDAKey */ 429 mrs x25, APDAKeyHi_EL1 430 mrs x26, APDBKeyLo_EL1 /* x27:x26 = APDBKey */ 431 mrs x27, APDBKeyHi_EL1 432 mrs x28, APGAKeyLo_EL1 /* x29:x28 = APGAKey */ 433 mrs x29, APGAKeyHi_EL1 434 435 stp x20, x21, [x19, #CTX_PACIAKEY_LO] 436 stp x22, x23, [x19, #CTX_PACIBKEY_LO] 437 stp x24, x25, [x19, #CTX_PACDAKEY_LO] 438 stp x26, x27, [x19, #CTX_PACDBKEY_LO] 439 stp x28, x29, [x19, #CTX_PACGAKEY_LO] 440#endif /* CTX_INCLUDE_PAUTH_REGS */ 441 .endm /* save_gp_pmcr_pauth_regs */ 442 443/* ----------------------------------------------------------------- 444 * This function saves the context and sets the PSTATE to a known 445 * state, preparing entry to el3. 446 * Save all the general purpose and ARMv8.3-PAuth (if enabled) 447 * registers. 448 * Then set any of the PSTATE bits that are not set by hardware 449 * according to the Aarch64.TakeException pseudocode in the Arm 450 * Architecture Reference Manual to a default value for EL3. 451 * clobbers: x17 452 * ----------------------------------------------------------------- 453 */ 454func prepare_el3_entry 455 save_gp_pmcr_pauth_regs 456 setup_el3_execution_context 457 ret 458endfunc prepare_el3_entry 459 460/* ------------------------------------------------------------------ 461 * This function restores ARMv8.3-PAuth (if enabled) and all general 462 * purpose registers except x30 from the CPU context. 463 * x30 register must be explicitly restored by the caller. 464 * ------------------------------------------------------------------ 465 */ 466func restore_gp_pmcr_pauth_regs 467#if CTX_INCLUDE_PAUTH_REGS 468 /* Restore the ARMv8.3 PAuth keys */ 469 add x10, sp, #CTX_PAUTH_REGS_OFFSET 470 471 ldp x0, x1, [x10, #CTX_PACIAKEY_LO] /* x1:x0 = APIAKey */ 472 ldp x2, x3, [x10, #CTX_PACIBKEY_LO] /* x3:x2 = APIBKey */ 473 ldp x4, x5, [x10, #CTX_PACDAKEY_LO] /* x5:x4 = APDAKey */ 474 ldp x6, x7, [x10, #CTX_PACDBKEY_LO] /* x7:x6 = APDBKey */ 475 ldp x8, x9, [x10, #CTX_PACGAKEY_LO] /* x9:x8 = APGAKey */ 476 477 msr APIAKeyLo_EL1, x0 478 msr APIAKeyHi_EL1, x1 479 msr APIBKeyLo_EL1, x2 480 msr APIBKeyHi_EL1, x3 481 msr APDAKeyLo_EL1, x4 482 msr APDAKeyHi_EL1, x5 483 msr APDBKeyLo_EL1, x6 484 msr APDBKeyHi_EL1, x7 485 msr APGAKeyLo_EL1, x8 486 msr APGAKeyHi_EL1, x9 487#endif /* CTX_INCLUDE_PAUTH_REGS */ 488 489 /* PMUv3 is presumed to be always present */ 490 ldr x0, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] 491 msr pmcr_el0, x0 492 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 493 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 494 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 495 ldp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 496 ldp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 497 ldp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 498 ldp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 499 ldp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 500 ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 501 ldp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 502 ldp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 503 ldp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 504 ldp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 505 ldp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 506 ldr x28, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 507 msr sp_el0, x28 508 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 509 ret 510endfunc restore_gp_pmcr_pauth_regs 511 512#if ERRATA_SPECULATIVE_AT 513/* -------------------------------------------------------------------- 514 * In case of ERRATA_SPECULATIVE_AT, save SCTLR_EL1 and TCR_EL1 515 * registers and update EL1 registers to disable stage1 and stage2 516 * page table walk. 517 * -------------------------------------------------------------------- 518 */ 519func save_and_update_ptw_el1_sys_regs 520 /* ---------------------------------------------------------- 521 * Save only sctlr_el1 and tcr_el1 registers 522 * ---------------------------------------------------------- 523 */ 524 mrs x29, sctlr_el1 525 str x29, [sp, #(CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_SCTLR_EL1)] 526 mrs x29, tcr_el1 527 str x29, [sp, #(CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_TCR_EL1)] 528 529 /* ------------------------------------------------------------ 530 * Must follow below order in order to disable page table 531 * walk for lower ELs (EL1 and EL0). First step ensures that 532 * page table walk is disabled for stage1 and second step 533 * ensures that page table walker should use TCR_EL1.EPDx 534 * bits to perform address translation. ISB ensures that CPU 535 * does these 2 steps in order. 536 * 537 * 1. Update TCR_EL1.EPDx bits to disable page table walk by 538 * stage1. 539 * 2. Enable MMU bit to avoid identity mapping via stage2 540 * and force TCR_EL1.EPDx to be used by the page table 541 * walker. 542 * ------------------------------------------------------------ 543 */ 544 orr x29, x29, #(TCR_EPD0_BIT) 545 orr x29, x29, #(TCR_EPD1_BIT) 546 msr tcr_el1, x29 547 isb 548 mrs x29, sctlr_el1 549 orr x29, x29, #SCTLR_M_BIT 550 msr sctlr_el1, x29 551 isb 552 ret 553endfunc save_and_update_ptw_el1_sys_regs 554 555#endif /* ERRATA_SPECULATIVE_AT */ 556 557/* ----------------------------------------------------------------- 558* The below macro returns the address of the per_world context for 559* the security state, retrieved through "get_security_state" macro. 560* The per_world context address is returned in the register argument. 561* Clobbers: x9, x10 562* ------------------------------------------------------------------ 563*/ 564 565.macro get_per_world_context _reg:req 566 ldr x10, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 567 get_security_state x9, x10 568 mov_imm x10, (CTX_PERWORLD_EL3STATE_END - CTX_CPTR_EL3) 569 mul x9, x9, x10 570 adrp x10, per_world_context 571 add x10, x10, :lo12:per_world_context 572 add x9, x9, x10 573 mov \_reg, x9 574.endm 575 576/* ------------------------------------------------------------------ 577 * This routine assumes that the SP_EL3 is pointing to a valid 578 * context structure from where the gp regs and other special 579 * registers can be retrieved. 580 * ------------------------------------------------------------------ 581 */ 582func el3_exit 583#if ENABLE_ASSERTIONS 584 /* el3_exit assumes SP_EL0 on entry */ 585 mrs x17, spsel 586 cmp x17, #MODE_SP_EL0 587 ASM_ASSERT(eq) 588#endif /* ENABLE_ASSERTIONS */ 589 590 /* ---------------------------------------------------------- 591 * Save the current SP_EL0 i.e. the EL3 runtime stack which 592 * will be used for handling the next SMC. 593 * Then switch to SP_EL3. 594 * ---------------------------------------------------------- 595 */ 596 mov x17, sp 597 msr spsel, #MODE_SP_ELX 598 str x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 599 600 /* ---------------------------------------------------------- 601 * Restore CPTR_EL3. 602 * ZCR is only restored if SVE is supported and enabled. 603 * Synchronization is required before zcr_el3 is addressed. 604 * ---------------------------------------------------------- 605 */ 606 607 /* The address of the per_world context is stored in x9 */ 608 get_per_world_context x9 609 610 ldp x19, x20, [x9, #CTX_CPTR_EL3] 611 msr cptr_el3, x19 612 613#if IMAGE_BL31 614 ands x19, x19, #CPTR_EZ_BIT 615 beq sve_not_enabled 616 617 isb 618 msr S3_6_C1_C2_0, x20 /* zcr_el3 */ 619sve_not_enabled: 620 621 restore_mpam3_el3 622 623#endif /* IMAGE_BL31 */ 624 625#if IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 626 /* ---------------------------------------------------------- 627 * Restore mitigation state as it was on entry to EL3 628 * ---------------------------------------------------------- 629 */ 630 ldr x17, [sp, #CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_DISABLE] 631 cbz x17, 1f 632 blr x17 6331: 634#endif /* IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 */ 635 636#if IMAGE_BL31 637 synchronize_errors 638#endif /* IMAGE_BL31 */ 639 640 /* -------------------------------------------------------------- 641 * Restore MDCR_EL3, SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET 642 * -------------------------------------------------------------- 643 */ 644 ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 645 ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 646 ldr x19, [sp, #CTX_EL3STATE_OFFSET + CTX_MDCR_EL3] 647 msr spsr_el3, x16 648 msr elr_el3, x17 649 msr scr_el3, x18 650 msr mdcr_el3, x19 651 652 restore_ptw_el1_sys_regs 653 654 /* ---------------------------------------------------------- 655 * Restore general purpose (including x30), PMCR_EL0 and 656 * ARMv8.3-PAuth registers. 657 * Exit EL3 via ERET to a lower exception level. 658 * ---------------------------------------------------------- 659 */ 660 bl restore_gp_pmcr_pauth_regs 661 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 662 663#ifdef IMAGE_BL31 664 /* Clear the EL3 flag as we are exiting el3 */ 665 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG] 666#endif /* IMAGE_BL31 */ 667 668 exception_return 669 670endfunc el3_exit 671