1 /* 2 * Copyright (c) 2022-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef GPT_RME_PRIVATE_H 8 #define GPT_RME_PRIVATE_H 9 10 #include <arch.h> 11 #include <lib/gpt_rme/gpt_rme.h> 12 #include <lib/spinlock.h> 13 #include <lib/utils_def.h> 14 15 /******************************************************************************/ 16 /* GPT descriptor definitions */ 17 /******************************************************************************/ 18 19 /* GPT level 0 descriptor bit definitions */ 20 #define GPT_L0_TYPE_MASK UL(0xF) 21 #define GPT_L0_TYPE_SHIFT U(0) 22 23 /* GPT level 0 table and block descriptors */ 24 #define GPT_L0_TYPE_TBL_DESC UL(3) 25 #define GPT_L0_TYPE_BLK_DESC UL(1) 26 27 #define GPT_L0_TBL_DESC_L1ADDR_MASK UL(0xFFFFFFFFFF) 28 #define GPT_L0_TBL_DESC_L1ADDR_SHIFT U(12) 29 30 #define GPT_L0_BLK_DESC_GPI_MASK UL(0xF) 31 #define GPT_L0_BLK_DESC_GPI_SHIFT U(4) 32 33 /* GPT level 1 Contiguous descriptor */ 34 #define GPT_L1_TYPE_CONT_DESC_MASK UL(0xF) 35 #define GPT_L1_TYPE_CONT_DESC UL(1) 36 37 /* GPT level 1 Contiguous descriptor definitions */ 38 #define GPT_L1_CONTIG_2MB UL(1) 39 #define GPT_L1_CONTIG_32MB UL(2) 40 #define GPT_L1_CONTIG_512MB UL(3) 41 42 #define GPT_L1_CONT_DESC_GPI_SHIFT U(4) 43 #define GPT_L1_CONT_DESC_GPI_MASK UL(0xF) 44 #define GPT_L1_CONT_DESC_CONTIG_SHIFT U(8) 45 #define GPT_L1_CONT_DESC_CONTIG_MASK UL(3) 46 47 /* GPT level 1 Granules descriptor bit definitions */ 48 #define GPT_L1_GRAN_DESC_GPI_MASK UL(0xF) 49 50 /* L1 Contiguous descriptors templates */ 51 #define GPT_L1_CONT_DESC_2MB \ 52 (GPT_L1_TYPE_CONT_DESC | \ 53 (GPT_L1_CONTIG_2MB << GPT_L1_CONT_DESC_CONTIG_SHIFT)) 54 #define GPT_L1_CONT_DESC_32MB \ 55 (GPT_L1_TYPE_CONT_DESC | \ 56 (GPT_L1_CONTIG_32MB << GPT_L1_CONT_DESC_CONTIG_SHIFT)) 57 #define GPT_L1_CONT_DESC_512MB \ 58 (GPT_L1_TYPE_CONT_DESC | \ 59 (GPT_L1_CONTIG_512MB << GPT_L1_CONT_DESC_CONTIG_SHIFT)) 60 61 /* Create L1 Contiguous descriptor from GPI and template */ 62 #define GPT_L1_GPI_CONT_DESC(_gpi, _desc) \ 63 ((_desc) | ((uint64_t)(_gpi) << GPT_L1_CONT_DESC_GPI_SHIFT)) 64 65 /* Create L1 Contiguous descriptor from Granules descriptor and size */ 66 #define GPT_L1_CONT_DESC(_desc, _size) \ 67 (GPT_L1_CONT_DESC_##_size | \ 68 (((_desc) & GPT_L1_GRAN_DESC_GPI_MASK) << \ 69 GPT_L1_CONT_DESC_GPI_SHIFT)) 70 71 /* Create L1 Contiguous descriptor from GPI and size */ 72 #define GPT_L1_CONT_DESC_SIZE(_gpi, _size) \ 73 (GPT_L1_CONT_DESC_##_size | \ 74 (((uint64_t)(_gpi) << GPT_L1_CONT_DESC_GPI_SHIFT)) 75 76 #define GPT_L1_GPI_BYTE(_gpi) (uint64_t)((_gpi) | ((_gpi) << 4)) 77 #define GPT_L1_GPI_HALF(_gpi) (GPT_L1_GPI_BYTE(_gpi) | (GPT_L1_GPI_BYTE(_gpi) << 8)) 78 #define GPT_L1_GPI_WORD(_gpi) (GPT_L1_GPI_HALF(_gpi) | (GPT_L1_GPI_HALF(_gpi) << 16)) 79 80 /* 81 * This macro generates a Granules descriptor 82 * with the same value for every GPI entry. 83 */ 84 #define GPT_BUILD_L1_DESC(_gpi) (GPT_L1_GPI_WORD(_gpi) | (GPT_L1_GPI_WORD(_gpi) << 32)) 85 86 #define GPT_L1_SECURE_DESC GPT_BUILD_L1_DESC(GPT_GPI_SECURE) 87 #define GPT_L1_NS_DESC GPT_BUILD_L1_DESC(GPT_GPI_NS) 88 #define GPT_L1_REALM_DESC GPT_BUILD_L1_DESC(GPT_GPI_REALM) 89 #define GPT_L1_ANY_DESC GPT_BUILD_L1_DESC(GPT_GPI_ANY) 90 91 /******************************************************************************/ 92 /* GPT platform configuration */ 93 /******************************************************************************/ 94 95 /* This value comes from GPCCR_EL3 so no externally supplied definition */ 96 #define GPT_L0GPTSZ ((unsigned int)((read_gpccr_el3() >> \ 97 GPCCR_L0GPTSZ_SHIFT) & GPCCR_L0GPTSZ_MASK)) 98 99 /* The "S" value is directly related to L0GPTSZ */ 100 #define GPT_S_VAL (GPT_L0GPTSZ + 30U) 101 102 /* 103 * Map PPS values to T values. 104 * 105 * PPS Size T 106 * 0b000 4GB 32 107 * 0b001 64GB 36 108 * 0b010 1TB 40 109 * 0b011 4TB 42 110 * 0b100 16TB 44 111 * 0b101 256TB 48 112 * 0b110 4PB 52 113 * 114 * See section 15.1.27 of the RME specification. 115 */ 116 typedef enum { 117 PPS_4GB_T = 32U, 118 PPS_64GB_T = 36U, 119 PPS_1TB_T = 40U, 120 PPS_4TB_T = 42U, 121 PPS_16TB_T = 44U, 122 PPS_256TB_T = 48U, 123 PPS_4PB_T = 52U 124 } gpt_t_val_e; 125 126 /* 127 * Map PGS values to P values. 128 * 129 * PGS Size P 130 * 0b00 4KB 12 131 * 0b10 16KB 14 132 * 0b01 64KB 16 133 * 134 * Note that pgs=0b10 is 16KB and pgs=0b01 is 64KB, this is not a typo. 135 * 136 * See section 15.1.27 of the RME specification. 137 */ 138 typedef enum { 139 PGS_4KB_P = 12U, 140 PGS_16KB_P = 14U, 141 PGS_64KB_P = 16U 142 } gpt_p_val_e; 143 144 #define LOCK_SIZE sizeof(((bitlock_t *)NULL)->lock) 145 #define LOCK_TYPE typeof(((bitlock_t *)NULL)->lock) 146 #define LOCK_BITS (LOCK_SIZE * 8U) 147 148 /* 149 * Internal structure to retrieve the values from get_gpi_params(); 150 */ 151 typedef struct { 152 uint64_t gpt_l1_desc; 153 uint64_t *gpt_l1_addr; 154 unsigned int idx; 155 unsigned int gpi_shift; 156 unsigned int gpi; 157 #if (RME_GPT_BITLOCK_BLOCK != 0) 158 bitlock_t *lock; 159 LOCK_TYPE mask; 160 #endif 161 } gpi_info_t; 162 163 /* 164 * Look up structure for contiguous blocks and descriptors 165 */ 166 typedef struct { 167 size_t size; 168 unsigned int desc; 169 } gpt_fill_lookup_t; 170 171 typedef void (*gpt_shatter_func)(uintptr_t base, const gpi_info_t *gpi_info, 172 uint64_t l1_desc); 173 typedef void (*gpt_tlbi_func)(uintptr_t base); 174 175 /* 176 * Look-up structure for 177 * invalidating TLBs of GPT entries by Physical address, last level. 178 */ 179 typedef struct { 180 gpt_tlbi_func function; 181 size_t mask; 182 } gpt_tlbi_lookup_t; 183 184 /* Max valid value for PGS */ 185 #define GPT_PGS_MAX (2U) 186 187 /* Max valid value for PPS */ 188 #define GPT_PPS_MAX (6U) 189 190 /******************************************************************************/ 191 /* L0 address attribute macros */ 192 /******************************************************************************/ 193 194 /* 195 * Width of the L0 index field. 196 * 197 * If S is greater than or equal to T then there is a single L0 region covering 198 * the entire protected space so there is no L0 index, so the width (and the 199 * derivative mask value) are both zero. If we don't specifically handle this 200 * special case we'll get a negative width value which does not make sense and 201 * would cause problems. 202 */ 203 #define GPT_L0_IDX_WIDTH(_t) (((unsigned int)(_t) > GPT_S_VAL) ? \ 204 ((unsigned int)(_t) - GPT_S_VAL) : (0U)) 205 206 /* Bit shift for the L0 index field in a PA */ 207 #define GPT_L0_IDX_SHIFT (GPT_S_VAL) 208 209 /* 210 * Mask for the L0 index field, must be shifted. 211 * 212 * The value 0x3FFFFF is 22 bits wide which is the maximum possible width of the 213 * L0 index within a physical address. This is calculated by 214 * ((t_max - 1) - s_min + 1) where t_max is 52 for 4PB, the largest PPS, and 215 * s_min is 30 for 1GB, the smallest L0GPTSZ. 216 */ 217 #define GPT_L0_IDX_MASK(_t) (0x3FFFFFUL >> (22U - \ 218 (GPT_L0_IDX_WIDTH(_t)))) 219 220 /* Total number of L0 regions */ 221 #define GPT_L0_REGION_COUNT(_t) ((GPT_L0_IDX_MASK(_t)) + 1U) 222 223 /* Total size of each GPT L0 region in bytes */ 224 #define GPT_L0_REGION_SIZE (1UL << (GPT_L0_IDX_SHIFT)) 225 226 /* Total size in bytes of the whole L0 table */ 227 #define GPT_L0_TABLE_SIZE(_t) ((GPT_L0_REGION_COUNT(_t)) << 3U) 228 229 /******************************************************************************/ 230 /* L1 address attribute macros */ 231 /******************************************************************************/ 232 233 /* 234 * Width of the L1 index field. 235 * 236 * This field does not have a special case to handle widths less than zero like 237 * the L0 index field above since all valid combinations of PGS (p) and L0GPTSZ 238 * (s) will result in a positive width value. 239 */ 240 #define GPT_L1_IDX_WIDTH(_p) ((GPT_S_VAL - 1U) - \ 241 ((unsigned int)(_p) + 3U)) 242 243 /* Bit shift for the L1 index field */ 244 #define GPT_L1_IDX_SHIFT(_p) ((unsigned int)(_p) + 4U) 245 246 /* 247 * Mask for the L1 index field, must be shifted. 248 * 249 * The value 0x7FFFFF is 23 bits wide and is the maximum possible width of the 250 * L1 index within a physical address. It is calculated by 251 * ((s_max - 1) - (p_min + 4) + 1) where s_max is 39 for 512GB, the largest 252 * L0GPTSZ, and p_min is 12 for 4KB granules, the smallest PGS. 253 */ 254 #define GPT_L1_IDX_MASK(_p) (0x7FFFFFUL >> (23U - \ 255 (GPT_L1_IDX_WIDTH(_p)))) 256 257 /* Bit shift for the index of the L1 GPI in a PA */ 258 #define GPT_L1_GPI_IDX_SHIFT(_p) (_p) 259 260 /* Mask for the index of the L1 GPI in a PA */ 261 #define GPT_L1_GPI_IDX_MASK (0xF) 262 263 /* Total number of entries in each L1 table */ 264 #define GPT_L1_ENTRY_COUNT(_p) ((GPT_L1_IDX_MASK(_p)) + 1UL) 265 266 /* Number of L1 entries in 2MB block */ 267 #define GPT_L1_ENTRY_COUNT_2MB(_p) (SZ_2M >> GPT_L1_IDX_SHIFT(_p)) 268 269 /* Total size in bytes of each L1 table */ 270 #define GPT_L1_TABLE_SIZE(_p) ((GPT_L1_ENTRY_COUNT(_p)) << 3U) 271 272 /******************************************************************************/ 273 /* General helper macros */ 274 /******************************************************************************/ 275 276 /* Protected space actual size in bytes */ 277 #define GPT_PPS_ACTUAL_SIZE(_t) (1UL << (unsigned int)(_t)) 278 279 /* Granule actual size in bytes */ 280 #define GPT_PGS_ACTUAL_SIZE(_p) (1UL << (unsigned int)(_p)) 281 282 /* Number of granules in 2MB block */ 283 #define GPT_PGS_COUNT_2MB(_p) (1UL << (21U - (unsigned int)(_p))) 284 285 /* L0 GPT region size in bytes */ 286 #define GPT_L0GPTSZ_ACTUAL_SIZE (1UL << GPT_S_VAL) 287 288 /* Get the index of the L0 entry from a physical address */ 289 #define GPT_L0_IDX(_pa) ((_pa) >> GPT_L0_IDX_SHIFT) 290 291 /* 292 * This definition is used to determine if a physical address lies on an L0 293 * region boundary. 294 */ 295 #define GPT_IS_L0_ALIGNED(_pa) \ 296 (((_pa) & (GPT_L0_REGION_SIZE - UL(1))) == UL(0)) 297 298 /* Get the type field from an L0 descriptor */ 299 #define GPT_L0_TYPE(_desc) (((_desc) >> GPT_L0_TYPE_SHIFT) & \ 300 GPT_L0_TYPE_MASK) 301 302 /* Create an L0 block descriptor */ 303 #define GPT_L0_BLK_DESC(_gpi) (GPT_L0_TYPE_BLK_DESC | \ 304 (((_gpi) & GPT_L0_BLK_DESC_GPI_MASK) << \ 305 GPT_L0_BLK_DESC_GPI_SHIFT)) 306 307 /* Create an L0 table descriptor with an L1 table address */ 308 #define GPT_L0_TBL_DESC(_pa) (GPT_L0_TYPE_TBL_DESC | ((uint64_t)(_pa) & \ 309 (GPT_L0_TBL_DESC_L1ADDR_MASK << \ 310 GPT_L0_TBL_DESC_L1ADDR_SHIFT))) 311 312 /* Get the GPI from an L0 block descriptor */ 313 #define GPT_L0_BLKD_GPI(_desc) (((_desc) >> GPT_L0_BLK_DESC_GPI_SHIFT) & \ 314 GPT_L0_BLK_DESC_GPI_MASK) 315 316 /* Get the L1 address from an L0 table descriptor */ 317 #define GPT_L0_TBLD_ADDR(_desc) ((uint64_t *)(((_desc) & \ 318 (GPT_L0_TBL_DESC_L1ADDR_MASK << \ 319 GPT_L0_TBL_DESC_L1ADDR_SHIFT)))) 320 321 /* Get the GPI from L1 Contiguous descriptor */ 322 #define GPT_L1_CONT_GPI(_desc) \ 323 (((_desc) >> GPT_L1_CONT_DESC_GPI_SHIFT) & GPT_L1_CONT_DESC_GPI_MASK) 324 325 /* Get the GPI from L1 Granules descriptor */ 326 #define GPT_L1_GRAN_GPI(_desc) ((_desc) & GPT_L1_GRAN_DESC_GPI_MASK) 327 328 /* Get the Contig from L1 Contiguous descriptor */ 329 #define GPT_L1_CONT_CONTIG(_desc) \ 330 (((_desc) >> GPT_L1_CONT_DESC_CONTIG_SHIFT) & \ 331 GPT_L1_CONT_DESC_CONTIG_MASK) 332 333 /* Get the index into the L1 table from a physical address */ 334 #define GPT_L1_IDX(_p, _pa) \ 335 (((_pa) >> GPT_L1_IDX_SHIFT(_p)) & GPT_L1_IDX_MASK(_p)) 336 337 /* Get the index of the GPI within an L1 table entry from a physical address */ 338 #define GPT_L1_GPI_IDX(_p, _pa) \ 339 (((_pa) >> GPT_L1_GPI_IDX_SHIFT(_p)) & GPT_L1_GPI_IDX_MASK) 340 341 /* Determine if an address is granule-aligned */ 342 #define GPT_IS_L1_ALIGNED(_p, _pa) \ 343 (((_pa) & (GPT_PGS_ACTUAL_SIZE(_p) - UL(1))) == UL(0)) 344 345 /* Get aligned addresses */ 346 #define ALIGN_2MB(_addr) ((_addr) & ~(SZ_2M - 1UL)) 347 #define ALIGN_32MB(_addr) ((_addr) & ~(SZ_32M - 1UL)) 348 #define ALIGN_512MB(_addr) ((_addr) & ~(SZ_512M - 1UL)) 349 350 /* Determine if region is contiguous */ 351 #define GPT_REGION_IS_CONT(_len, _addr, _size) \ 352 (((_len) >= (_size)) && (((_addr) & ((_size) - UL(1))) == UL(0))) 353 354 /* Get 32MB block number in 512MB block: 0-15 */ 355 #define GET_32MB_NUM(_addr) ((_addr >> 25) & 0xF) 356 357 /* Get 2MB block number in 32MB block: 0-15 */ 358 #define GET_2MB_NUM(_addr) ((_addr >> 21) & 0xF) 359 360 #endif /* GPT_RME_PRIVATE_H */ 361