1 /*
2 * Copyright (c) 2017-2020, ARM Limited. All rights reserved.
3 * Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io>
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <errno.h>
9 #include <string.h>
10
11 #include <arch_helpers.h>
12 #include <common/debug.h>
13 #include <common/fdt_wrappers.h>
14 #include <drivers/allwinner/axp.h>
15 #include <drivers/allwinner/sunxi_rsb.h>
16 #include <drivers/mentor/mi2cv.h>
17 #include <lib/mmio.h>
18 #include <libfdt.h>
19
20 #include <sunxi_cpucfg.h>
21 #include <sunxi_def.h>
22 #include <sunxi_mmap.h>
23 #include <sunxi_private.h>
24
25 static uint16_t pmic_bus_addr;
26 static uint8_t rsb_rt_addr;
27
is_using_rsb(void)28 static bool is_using_rsb(void)
29 {
30 return rsb_rt_addr != 0;
31 }
32
33 static enum pmic_type {
34 UNKNOWN,
35 AXP305,
36 AXP313,
37 AXP717,
38 } pmic;
39
get_rsb_rt_address(uint16_t hw_addr)40 static uint8_t get_rsb_rt_address(uint16_t hw_addr)
41 {
42 switch (hw_addr) {
43 case 0x3a3: return 0x2d;
44 case 0x745: return 0x3a;
45 }
46
47 return 0;
48 }
49
axp_read(uint8_t reg)50 int axp_read(uint8_t reg)
51 {
52 uint8_t val;
53 int ret;
54
55 if (is_using_rsb()) {
56 return rsb_read(rsb_rt_addr, reg);
57 }
58
59 ret = i2c_write(pmic_bus_addr, 0, 0, ®, 1);
60 if (ret == 0) {
61 ret = i2c_read(pmic_bus_addr, 0, 0, &val, 1);
62 }
63 if (ret) {
64 ERROR("PMIC: Cannot read PMIC register %02x\n", reg);
65 return ret;
66 }
67
68 return val;
69 }
70
axp_write(uint8_t reg,uint8_t val)71 int axp_write(uint8_t reg, uint8_t val)
72 {
73 int ret;
74
75 if (is_using_rsb()) {
76 return rsb_write(rsb_rt_addr, reg, val);
77 }
78
79 ret = i2c_write(pmic_bus_addr, reg, 1, &val, 1);
80 if (ret) {
81 ERROR("PMIC: Cannot write PMIC register %02x\n", reg);
82 }
83
84 return ret;
85 }
86
rsb_init(int rsb_hw_addr)87 static int rsb_init(int rsb_hw_addr)
88 {
89 int ret;
90
91 ret = rsb_init_controller();
92 if (ret) {
93 return ret;
94 }
95
96 /* Switch to the recommended 3 MHz bus clock. */
97 ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000);
98 if (ret) {
99 return ret;
100 }
101
102 /* Initiate an I2C transaction to switch the PMIC to RSB mode. */
103 ret = rsb_set_device_mode(AXP20X_MODE_RSB << 16 | AXP20X_MODE_REG << 8);
104 if (ret) {
105 return ret;
106 }
107
108 /* Associate the 8-bit runtime address with the 12-bit bus address. */
109 ret = rsb_assign_runtime_address(rsb_hw_addr, rsb_rt_addr);
110 if (ret) {
111 return ret;
112 }
113
114 return 0;
115 }
116
pmic_bus_init(uint16_t socid,uint16_t rsb_hw_addr)117 static int pmic_bus_init(uint16_t socid, uint16_t rsb_hw_addr)
118 {
119 int ret;
120
121 ret = sunxi_init_platform_r_twi(socid, is_using_rsb());
122 if (ret) {
123 INFO("Could not init platform bus: %d\n", ret);
124 pmic = UNKNOWN;
125 return ret;
126 }
127
128 if (is_using_rsb()) {
129 ret = rsb_init(rsb_hw_addr);
130 if (ret) {
131 pmic = UNKNOWN;
132 return ret;
133 }
134 } else {
135 /* initialise mi2cv driver */
136 i2c_init((void *)SUNXI_R_I2C_BASE);
137 }
138
139 return 0;
140 }
141
sunxi_pmic_setup(uint16_t socid,const void * fdt)142 int sunxi_pmic_setup(uint16_t socid, const void *fdt)
143 {
144 int node, parent, ret;
145 uint32_t reg;
146
147 node = fdt_node_offset_by_compatible(fdt, 0, "x-powers,axp806");
148 if (node >= 0) {
149 pmic = AXP305;
150 }
151
152 if (pmic == UNKNOWN) {
153 node = fdt_node_offset_by_compatible(fdt, 0, "x-powers,axp313a");
154 if (node >= 0) {
155 pmic = AXP313;
156 }
157 }
158
159 if (pmic == UNKNOWN) {
160 node = fdt_node_offset_by_compatible(fdt, 0, "x-powers,axp717");
161 if (node >= 0) {
162 pmic = AXP717;
163 }
164 }
165
166 if (pmic == UNKNOWN) {
167 INFO("PMIC: No known PMIC in DT, skipping setup.\n");
168 return -ENODEV;
169 }
170
171 if (fdt_read_uint32(fdt, node, "reg", ®)) {
172 ERROR("PMIC: PMIC DT node does not contain reg property.\n");
173 return -EINVAL;
174 }
175
176 pmic_bus_addr = reg;
177 parent = fdt_parent_offset(fdt, node);
178 ret = fdt_node_check_compatible(fdt, parent, "allwinner,sun8i-a23-rsb");
179 if (ret == 0) {
180 rsb_rt_addr = get_rsb_rt_address(pmic_bus_addr);
181 if (rsb_rt_addr == 0) {
182 ERROR("PMIC: no mapping for RSB address 0x%x\n",
183 pmic_bus_addr);
184 return -EINVAL;
185 }
186 }
187
188 INFO("Probing for PMIC on %s:\n", is_using_rsb() ? "RSB" : "I2C");
189
190 ret = pmic_bus_init(socid, pmic_bus_addr);
191 if (ret) {
192 return ret;
193 }
194
195 ret = axp_read(0x03);
196 switch (ret & 0xcf) {
197 case 0x40: /* AXP305 */
198 if (pmic == AXP305) {
199 INFO("PMIC: found AXP305, setting up regulators\n");
200 axp_setup_regulators(fdt);
201 } else {
202 pmic = UNKNOWN;
203 }
204 break;
205 case 0x48: /* AXP1530 */
206 case 0x4b: /* AXP313A */
207 case 0x4c: /* AXP313B */
208 if (pmic == AXP313) {
209 INFO("PMIC: found AXP313\n");
210 /* no regulators to set up */
211 } else {
212 pmic = UNKNOWN;
213 }
214 break;
215 case 0xcf: /* version reg not implemented on AXP717 */
216 if (pmic == AXP717) {
217 INFO("PMIC: found AXP717\n");
218 /* no regulators to set up, U-Boot takes care of this */
219 } else {
220 pmic = UNKNOWN;
221 }
222 break;
223 }
224
225 if (is_using_rsb()) {
226 /* Switch the PMIC back to I2C mode. */
227 return rsb_write(rsb_rt_addr, AXP20X_MODE_REG, AXP20X_MODE_I2C);
228 }
229
230 if (pmic == UNKNOWN) {
231 INFO("Incompatible or unknown PMIC found.\n");
232 return -ENODEV;
233 }
234
235 return 0;
236 }
237
sunxi_power_down(void)238 void sunxi_power_down(void)
239 {
240 int ret;
241
242 if (pmic == UNKNOWN) {
243 return;
244 }
245
246 /* Re-initialise after rich OS might have used it. */
247 ret = pmic_bus_init(SUNXI_SOC_H616, pmic_bus_addr);
248 if (ret) {
249 return;
250 }
251
252 switch (pmic) {
253 case AXP305:
254 axp_setbits(0x32, BIT(7));
255 break;
256 case AXP313:
257 axp_setbits(0x1a, BIT(7));
258 break;
259 case AXP717:
260 axp_setbits(0x27, BIT(0));
261 break;
262 default:
263 break;
264 }
265 }
266
sunxi_cpu_power_off_self(void)267 void sunxi_cpu_power_off_self(void)
268 {
269 u_register_t mpidr = read_mpidr();
270 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
271
272 /* Enable the CPUIDLE hardware (only really needs to be done once). */
273 mmio_write_32(SUNXI_CPUIDLE_EN_REG, 0x16aa0000);
274 mmio_write_32(SUNXI_CPUIDLE_EN_REG, 0xaa160001);
275
276 /* Trigger power off for this core. */
277 mmio_write_32(SUNXI_CORE_CLOSE_REG, BIT_32(core));
278 }
279