1 /*
2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <common/debug.h>
10 #include <common/desc_image_load.h>
11 #include <drivers/arm/sp804_delay_timer.h>
12 #include <fvp_pas_def.h>
13 #include <lib/fconf/fconf.h>
14 #include <lib/fconf/fconf_dyn_cfg_getter.h>
15 #include <lib/transfer_list.h>
16
17 #include <plat/arm/common/plat_arm.h>
18 #include <plat/common/platform.h>
19 #include <platform_def.h>
20
21 #include "fvp_private.h"
22
23 #if ENABLE_RME
24 /*
25 * The GPT library might modify the gpt regions structure to optimize
26 * the layout, so the array cannot be constant.
27 */
28 static pas_region_t pas_regions[] = {
29 ARM_PAS_KERNEL,
30 ARM_PAS_SECURE,
31 ARM_PAS_REALM,
32 ARM_PAS_EL3_DRAM,
33 ARM_PAS_GPTS,
34 ARM_PAS_KERNEL_1
35 };
36
37 static const arm_gpt_info_t arm_gpt_info = {
38 .pas_region_base = pas_regions,
39 .pas_region_count = (unsigned int)ARRAY_SIZE(pas_regions),
40 .l0_base = (uintptr_t)ARM_L0_GPT_BASE,
41 .l1_base = (uintptr_t)ARM_L1_GPT_BASE,
42 .l0_size = (size_t)ARM_L0_GPT_SIZE,
43 .l1_size = (size_t)ARM_L1_GPT_SIZE,
44 .pps = GPCCR_PPS_64GB,
45 .pgs = GPCCR_PGS_4K
46 };
47 #endif
48
bl2_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)49 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
50 {
51 struct transfer_list_entry *te __unused;
52
53 #if TRANSFER_LIST
54 arg0 = arg3;
55 #endif
56 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
57
58 /* Initialize the platform config for future decision making */
59 fvp_config_setup();
60 }
61
bl2_platform_setup(void)62 void bl2_platform_setup(void)
63 {
64 arm_bl2_platform_setup();
65
66 /* Initialize System level generic or SP804 timer */
67 fvp_timer_init();
68 }
69
70 #if ENABLE_RME
plat_arm_get_gpt_info(void)71 const arm_gpt_info_t *plat_arm_get_gpt_info(void)
72 {
73 return &arm_gpt_info;
74 }
75 #endif /* ENABLE_RME */
76
77 /*******************************************************************************
78 * This function returns the list of executable images
79 ******************************************************************************/
plat_get_next_bl_params(void)80 struct bl_params *plat_get_next_bl_params(void)
81 {
82 struct bl_params *arm_bl_params;
83 bl_mem_params_node_t *param_node __unused;
84 const struct dyn_cfg_dtb_info_t *fw_config_info __unused;
85 const struct dyn_cfg_dtb_info_t *hw_config_info __unused;
86 entry_point_info_t *ep __unused;
87 uint32_t next_exe_img_id __unused;
88 uintptr_t fw_config_base __unused;
89
90 arm_bl_params = arm_get_next_bl_params();
91
92 #if __aarch64__
93 /* Get BL31 image node */
94 param_node = get_bl_mem_params_node(BL31_IMAGE_ID);
95 #else /* aarch32 */
96 /* Get SP_MIN image node */
97 param_node = get_bl_mem_params_node(BL32_IMAGE_ID);
98 #endif /* __aarch64__ */
99 assert(param_node != NULL);
100
101 #if TRANSFER_LIST
102 arm_bl_params->head = ¶m_node->params_node_mem;
103 arm_bl_params->head->ep_info = ¶m_node->ep_info;
104 arm_bl_params->head->image_id = param_node->image_id;
105
106 arm_bl2_setup_next_ep_info(param_node);
107 #elif !RESET_TO_BL2 && !EL3_PAYLOAD_BASE
108 fw_config_base = 0UL;
109
110 /* Update the next image's ep info with the FW config address */
111 fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
112 assert(fw_config_info != NULL);
113
114 fw_config_base = fw_config_info->config_addr;
115 assert(fw_config_base != 0UL);
116
117 param_node->ep_info.args.arg1 = (uint32_t)fw_config_base;
118
119 /* Update BL33's ep info with the NS HW config address */
120 param_node = get_bl_mem_params_node(BL33_IMAGE_ID);
121 assert(param_node != NULL);
122
123 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
124 assert(hw_config_info != NULL);
125
126 param_node->ep_info.args.arg1 = hw_config_info->secondary_config_addr;
127 #endif /* TRANSFER_LIST */
128
129 return arm_bl_params;
130 }
131
bl2_plat_handle_post_image_load(unsigned int image_id)132 int bl2_plat_handle_post_image_load(unsigned int image_id)
133 {
134 #if !RESET_TO_BL2 && !EL3_PAYLOAD_BASE && !TRANSFER_LIST
135 if (image_id == HW_CONFIG_ID) {
136 const struct dyn_cfg_dtb_info_t *hw_config_info __unused;
137 struct transfer_list_entry *te __unused;
138 bl_mem_params_node_t *param_node __unused;
139
140 param_node = get_bl_mem_params_node(image_id);
141 assert(param_node != NULL);
142
143 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
144 assert(hw_config_info != NULL);
145
146 memcpy((void *)hw_config_info->secondary_config_addr,
147 (void *)hw_config_info->config_addr,
148 (size_t)param_node->image_info.image_size);
149
150 /*
151 * Ensure HW-config device tree is committed to memory, as the HW-Config
152 * might be used without cache and MMU enabled at BL33.
153 */
154 flush_dcache_range(hw_config_info->secondary_config_addr,
155 param_node->image_info.image_size);
156 }
157 #endif /* !RESET_TO_BL2 && !EL3_PAYLOAD_BASE && !TRANSFER_LIST*/
158
159 return arm_bl2_plat_handle_post_image_load(image_id);
160 }
161