1 /* 2 * Copyright (c) 2018-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <plat/arm/board/common/v2m_def.h> 11 #include <plat/arm/common/arm_def.h> 12 #include <plat/arm/css/common/css_def.h> 13 14 /* UART related constants */ 15 #define PLAT_ARM_BOOT_UART_BASE 0x2A400000 16 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ 50000000 17 18 /* IOFPGA UART0 */ 19 #define PLAT_ARM_RUN_UART_BASE 0x1C090000 20 #define PLAT_ARM_RUN_UART_CLK_IN_HZ 24000000 21 22 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 23 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 24 25 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) 26 #define PLAT_ARM_DRAM2_SIZE ULL(0xF80000000) 27 28 #define MAX_IO_DEVICES U(3) 29 #define MAX_IO_HANDLES U(4) 30 31 #define PLAT_ARM_FLASH_IMAGE_BASE 0x18200000 32 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE 0x00800000 33 34 #define PLAT_ARM_NVM_BASE 0x18200000 35 #define PLAT_ARM_NVM_SIZE 0x00800000 36 37 #if defined NS_BL1U_BASE 38 # undef NS_BL1U_BASE 39 # define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x00800000)) 40 #endif 41 42 /* Non-volatile counters */ 43 #define SOC_TRUSTED_NVCTR_BASE 0x7fe70000 44 #define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE) 45 #define TFW_NVCTR_SIZE U(4) 46 #define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004) 47 #define NTFW_CTR_SIZE U(4) 48 49 /* N1SDP remote chip at 4 TB offset */ 50 #define PLAT_ARM_REMOTE_CHIP_OFFSET (ULL(1) << 42) 51 52 #define N1SDP_REMOTE_DRAM1_BASE ARM_DRAM1_BASE + \ 53 PLAT_ARM_REMOTE_CHIP_OFFSET 54 #define N1SDP_REMOTE_DRAM1_SIZE ARM_DRAM1_SIZE 55 56 #define N1SDP_REMOTE_DRAM2_BASE PLAT_ARM_DRAM2_BASE + \ 57 PLAT_ARM_REMOTE_CHIP_OFFSET 58 #define N1SDP_REMOTE_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 59 60 /* 61 * N1SDP platform supports RDIMMs with ECC capability. To use the ECC 62 * capability, the entire DDR memory space has to be zeroed out before 63 * enabling the ECC bits in DMC620. To access the complete DDR memory 64 * along with remote chip's DDR memory, which is at 4 TB offset, physical 65 * and virtual address space limits are extended to 43-bits. 66 */ 67 #ifdef __aarch64__ 68 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 43) 69 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 43) 70 #else 71 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 72 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 73 #endif 74 75 #if CSS_USE_SCMI_SDS_DRIVER 76 #define N1SDP_SCMI_PAYLOAD_BASE 0x45400000 77 /* 78 * Index of SDS region used in the communication with SCP 79 */ 80 #define SDS_SCP_AP_REGION_ID U(0) 81 #else 82 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000 83 #endif 84 85 /* 86 * Trusted SRAM in N1SDP is 512 KB but only the bottom 384 KB 87 * is used for trusted board boot flow. The top 128 KB is used 88 * to load AP-BL1 image. 89 */ 90 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00060000 /* 384 KB */ 91 92 /* 93 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 94 * plus a little space for growth. 95 */ 96 #define PLAT_ARM_MAX_BL1_RW_SIZE 0xC000 97 98 /* 99 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 100 */ 101 102 #if USE_ROMLIB 103 # define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 104 # define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 105 #else 106 # define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0) 107 # define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0) 108 #endif 109 110 /* 111 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 112 * little space for growth. 113 */ 114 #if TRUSTED_BOARD_BOOT 115 # define PLAT_ARM_MAX_BL2_SIZE 0x22000 116 #else 117 # define PLAT_ARM_MAX_BL2_SIZE 0x14000 118 #endif 119 120 #define PLAT_ARM_MAX_BL31_SIZE UL(0x40000) 121 122 #define PLAT_ARM_SPMC_BASE U(0x08000000) 123 #define PLAT_ARM_SPMC_SIZE UL(0x02000000) /* 32 MB */ 124 125 126 /******************************************************************************* 127 * N1SDP topology related constants 128 ******************************************************************************/ 129 #define N1SDP_MAX_CPUS_PER_CLUSTER U(2) 130 #define PLAT_ARM_CLUSTER_COUNT U(2) 131 #define PLAT_N1SDP_CHIP_COUNT U(2) 132 #define N1SDP_MAX_CLUSTERS_PER_CHIP U(2) 133 #define N1SDP_MAX_PE_PER_CPU U(1) 134 135 #define PLATFORM_CORE_COUNT (PLAT_N1SDP_CHIP_COUNT * \ 136 PLAT_ARM_CLUSTER_COUNT * \ 137 N1SDP_MAX_CPUS_PER_CLUSTER * \ 138 N1SDP_MAX_PE_PER_CPU) 139 140 /* System power domain level */ 141 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3 142 143 /* 144 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 145 * plat_arm_mmap array defined for each BL stage. 146 */ 147 148 #ifdef IMAGE_BL1 149 # define PLAT_ARM_MMAP_ENTRIES U(6) 150 # define MAX_XLAT_TABLES U(5) 151 #endif 152 153 #ifdef IMAGE_BL2 154 # define PLAT_ARM_MMAP_ENTRIES U(11) 155 # define MAX_XLAT_TABLES U(10) 156 #endif 157 158 #ifdef IMAGE_BL31 159 # define PLAT_ARM_MMAP_ENTRIES U(12) 160 # define MAX_XLAT_TABLES U(12) 161 #endif 162 163 /* 164 * Size of cacheable stacks 165 */ 166 #if defined(IMAGE_BL1) 167 # if TRUSTED_BOARD_BOOT 168 # define PLATFORM_STACK_SIZE 0x1000 169 # else 170 # define PLATFORM_STACK_SIZE 0x440 171 # endif 172 #elif defined(IMAGE_BL2) 173 # if TRUSTED_BOARD_BOOT 174 # define PLATFORM_STACK_SIZE 0x1000 175 # else 176 # define PLATFORM_STACK_SIZE 0x400 177 # endif 178 #elif defined(IMAGE_BL2U) 179 # define PLATFORM_STACK_SIZE 0x400 180 #elif defined(IMAGE_BL31) 181 # if SPM_MM 182 # define PLATFORM_STACK_SIZE 0x500 183 # else 184 # define PLATFORM_STACK_SIZE 0x400 185 # endif 186 #elif defined(IMAGE_BL32) 187 # define PLATFORM_STACK_SIZE 0x440 188 #endif 189 190 #define PLAT_ARM_NSTIMER_FRAME_ID 0 191 #define PLAT_CSS_MHU_BASE 0x45000000 192 #define PLAT_MAX_PWR_LVL 2 193 194 /* Interrupt handling constants */ 195 #define N1SDP_IRQ_MMU_TCU1_EVENT_Q_SEC U(257) 196 #define N1SDP_IRQ_MMU_TCU1_CMD_SYNC_SEC U(258) 197 #define N1SDP_IRQ_MMU_TCU1_GLOBAL U(259) 198 #define N1SDP_IRQ_MMU_TCU2_EVENT_Q_SEC U(264) 199 #define N1SDP_IRQ_MMU_TCU2_CMD_SYNC_SEC U(265) 200 #define N1SDP_IRQ_MMU_TCU2_GLOBAL U(266) 201 #define N1SDP_IRQ_CLUSTER0_MHU U(349) 202 #define N1SDP_IRQ_CLUSTER1_MHU U(351) 203 #define N1SDP_IRQ_P0_REFCLK U(412) 204 #define N1SDP_IRQ_P1_REFCLK U(413) 205 206 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 207 ARM_G1S_IRQ_PROPS(grp), \ 208 INTR_PROP_DESC(CSS_IRQ_MHU, \ 209 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 210 INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, \ 211 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 212 INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, \ 213 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 214 INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU1_EVENT_Q_SEC, \ 215 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 216 INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU1_CMD_SYNC_SEC, \ 217 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 218 INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU1_GLOBAL, \ 219 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 220 INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU2_EVENT_Q_SEC, \ 221 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 222 INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU2_CMD_SYNC_SEC, \ 223 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 224 INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU2_GLOBAL, \ 225 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 226 INTR_PROP_DESC(N1SDP_IRQ_CLUSTER0_MHU, \ 227 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 228 INTR_PROP_DESC(N1SDP_IRQ_CLUSTER1_MHU, \ 229 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 230 INTR_PROP_DESC(N1SDP_IRQ_P0_REFCLK, \ 231 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 232 INTR_PROP_DESC(N1SDP_IRQ_P1_REFCLK, \ 233 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL) 234 235 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 236 237 238 #define N1SDP_DEVICE_BASE ULL(0x08000000) 239 #define N1SDP_DEVICE_SIZE ULL(0x48000000) 240 #define N1SDP_REMOTE_DEVICE_BASE N1SDP_DEVICE_BASE + \ 241 PLAT_ARM_REMOTE_CHIP_OFFSET 242 #define N1SDP_REMOTE_DEVICE_SIZE N1SDP_DEVICE_SIZE 243 244 /* Real base is 0x0. Changed to load BL1 at this address */ 245 # define PLAT_ARM_TRUSTED_ROM_BASE 0x04060000 246 # define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 /* 128KB */ 247 248 #define N1SDP_MAP_DEVICE MAP_REGION_FLAT( \ 249 N1SDP_DEVICE_BASE, \ 250 N1SDP_DEVICE_SIZE, \ 251 MT_DEVICE | MT_RW | MT_SECURE) 252 253 #define ARM_MAP_DRAM1 MAP_REGION_FLAT( \ 254 ARM_DRAM1_BASE, \ 255 ARM_DRAM1_SIZE, \ 256 MT_MEMORY | MT_RW | MT_NS) 257 258 #define N1SDP_MAP_REMOTE_DEVICE MAP_REGION_FLAT( \ 259 N1SDP_REMOTE_DEVICE_BASE, \ 260 N1SDP_REMOTE_DEVICE_SIZE, \ 261 MT_DEVICE | MT_RW | MT_SECURE) 262 263 #define N1SDP_MAP_REMOTE_DRAM1 MAP_REGION_FLAT( \ 264 N1SDP_REMOTE_DRAM1_BASE, \ 265 N1SDP_REMOTE_DRAM1_SIZE, \ 266 MT_MEMORY | MT_RW | MT_NS) 267 268 #define N1SDP_MAP_REMOTE_DRAM2 MAP_REGION_FLAT( \ 269 N1SDP_REMOTE_DRAM2_BASE, \ 270 N1SDP_REMOTE_DRAM2_SIZE, \ 271 MT_MEMORY | MT_RW | MT_NS) 272 273 /* GIC related constants */ 274 #define PLAT_ARM_GICD_BASE 0x30000000 275 #define PLAT_ARM_GICC_BASE 0x2C000000 276 #define PLAT_ARM_GICR_BASE 0x300C0000 277 278 /* Platform ID address */ 279 #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) 280 281 /* Secure Watchdog Constants */ 282 #define SBSA_SECURE_WDOG_BASE UL(0x2A480000) 283 #define SBSA_SECURE_WDOG_TIMEOUT UL(100) 284 285 /* Number of SCMI channels on the platform */ 286 #define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) 287 288 #endif /* PLATFORM_DEF_H */ 289