1 /*
2 * Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch.h>
12 #include <arch_helpers.h>
13 #include <common/debug.h>
14 #include <common/romlib.h>
15 #include <common/par.h>
16 #include <lib/extensions/sysreg128.h>
17 #include <lib/mmio.h>
18 #include <lib/smccc.h>
19 #include <lib/xlat_tables/xlat_tables_compat.h>
20 #include <services/arm_arch_svc.h>
21 #include <plat/arm/common/plat_arm.h>
22 #include <plat/common/platform.h>
23
24 /* Weak definitions may be overridden in specific ARM standard platform */
25 #pragma weak plat_get_ns_image_entrypoint
26 #pragma weak plat_arm_get_mmap
27
28 /* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid
29 * conflicts with the definition in plat/common. */
30 #pragma weak plat_get_syscnt_freq2
31
32 /* Get ARM SOC-ID */
33 #pragma weak plat_arm_get_soc_id
34
35 /*******************************************************************************
36 * Changes the memory attributes for the region of mapped memory where the BL
37 * image's translation tables are located such that the tables will have
38 * read-only permissions.
39 ******************************************************************************/
40 #if PLAT_RO_XLAT_TABLES
arm_xlat_make_tables_readonly(void)41 void arm_xlat_make_tables_readonly(void)
42 {
43 int rc = xlat_make_tables_readonly();
44
45 if (rc != 0) {
46 ERROR("Failed to make translation tables read-only at EL%u.\n",
47 get_current_el());
48 panic();
49 }
50
51 INFO("Translation tables are now read-only at EL%u.\n",
52 get_current_el());
53 }
54 #endif
55
arm_setup_romlib(void)56 void arm_setup_romlib(void)
57 {
58 #if USE_ROMLIB
59 if (!rom_lib_init(ROMLIB_VERSION))
60 panic();
61 #endif
62 }
63
plat_get_ns_image_entrypoint(void)64 uintptr_t plat_get_ns_image_entrypoint(void)
65 {
66 #ifdef PRELOADED_BL33_BASE
67 return PRELOADED_BL33_BASE;
68 #else
69 return PLAT_ARM_NS_IMAGE_BASE;
70 #endif
71 }
72
73 /*******************************************************************************
74 * Gets SPSR for BL32 entry
75 ******************************************************************************/
arm_get_spsr_for_bl32_entry(void)76 uint32_t arm_get_spsr_for_bl32_entry(void)
77 {
78 /*
79 * The Secure Payload Dispatcher service is responsible for
80 * setting the SPSR prior to entry into the BL32 image.
81 */
82 return 0;
83 }
84
85 /*******************************************************************************
86 * Gets SPSR for BL33 entry
87 ******************************************************************************/
88 #ifdef __aarch64__
arm_get_spsr_for_bl33_entry(void)89 uint32_t arm_get_spsr_for_bl33_entry(void)
90 {
91 unsigned int mode;
92 uint32_t spsr;
93
94 /* Figure out what mode we enter the non-secure world in */
95 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
96
97 /*
98 * TODO: Consider the possibility of specifying the SPSR in
99 * the FIP ToC and allowing the platform to have a say as
100 * well.
101 */
102 spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
103 return spsr;
104 }
105 #else
106 /*******************************************************************************
107 * Gets SPSR for BL33 entry
108 ******************************************************************************/
arm_get_spsr_for_bl33_entry(void)109 uint32_t arm_get_spsr_for_bl33_entry(void)
110 {
111 unsigned int hyp_status, mode, spsr;
112
113 hyp_status = GET_VIRT_EXT(read_id_pfr1());
114
115 mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
116
117 /*
118 * TODO: Consider the possibility of specifying the SPSR in
119 * the FIP ToC and allowing the platform to have a say as
120 * well.
121 */
122 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
123 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
124 return spsr;
125 }
126 #endif /* __aarch64__ */
127
128 /*******************************************************************************
129 * Configures access to the system counter timer module.
130 ******************************************************************************/
131 #ifdef ARM_SYS_TIMCTL_BASE
arm_configure_sys_timer(void)132 void arm_configure_sys_timer(void)
133 {
134 unsigned int reg_val;
135
136 /* Read the frequency of the system counter */
137 unsigned int freq_val = plat_get_syscnt_freq2();
138
139 #if ARM_CONFIG_CNTACR
140 reg_val = (1U << CNTACR_RPCT_SHIFT) | (1U << CNTACR_RVCT_SHIFT);
141 reg_val |= (1U << CNTACR_RFRQ_SHIFT) | (1U << CNTACR_RVOFF_SHIFT);
142 reg_val |= (1U << CNTACR_RWVT_SHIFT) | (1U << CNTACR_RWPT_SHIFT);
143 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val);
144 #endif /* ARM_CONFIG_CNTACR */
145
146 reg_val = (1U << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID));
147 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val);
148
149 /*
150 * Initialize CNTFRQ register in CNTCTLBase frame. The CNTFRQ
151 * system register initialized during psci_arch_setup() is different
152 * from this and has to be updated independently.
153 */
154 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val);
155
156 #if defined(PLAT_juno) || defined(PLAT_n1sdp) || defined(PLAT_morello)
157 /*
158 * Initialize CNTFRQ register in Non-secure CNTBase frame.
159 * This is required for Juno, N1SDP and Morello because they do not
160 * follow ARM ARM in that the value updated in CNTFRQ is not
161 * reflected in CNTBASEN_CNTFRQ. Hence update the value manually.
162 */
163 mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASEN_CNTFRQ, freq_val);
164 #endif
165 }
166 #endif /* ARM_SYS_TIMCTL_BASE */
167
168 /*******************************************************************************
169 * Returns ARM platform specific memory map regions.
170 ******************************************************************************/
plat_arm_get_mmap(void)171 const mmap_region_t *plat_arm_get_mmap(void)
172 {
173 return plat_arm_mmap;
174 }
175
176 #ifdef ARM_SYS_CNTCTL_BASE
177
plat_get_syscnt_freq2(void)178 unsigned int plat_get_syscnt_freq2(void)
179 {
180 unsigned int counter_base_frequency;
181
182 /* Read the frequency from Frequency modes table */
183 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
184
185 /* The first entry of the frequency modes table must not be 0 */
186 if (counter_base_frequency == 0U)
187 panic();
188
189 return counter_base_frequency;
190 }
191
192 #endif /* ARM_SYS_CNTCTL_BASE */
193
194 #if SDEI_SUPPORT
195 /*
196 * Translate SDEI entry point to PA, and perform standard ARM entry point
197 * validation on it.
198 */
plat_sdei_validate_entry_point(uintptr_t ep,unsigned int client_mode)199 int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode)
200 {
201 uint64_t pa;
202 sysreg_t par;
203 u_register_t scr_el3;
204
205 /* Doing Non-secure address translation requires SCR_EL3.NS set */
206 scr_el3 = read_scr_el3();
207 write_scr_el3(scr_el3 | SCR_NS_BIT);
208 isb();
209
210 assert((client_mode == MODE_EL2) || (client_mode == MODE_EL1));
211 if (client_mode == MODE_EL2) {
212 /*
213 * Translate entry point to Physical Address using the EL2
214 * translation regime.
215 */
216 ats1e2r(ep);
217 } else {
218 /*
219 * Translate entry point to Physical Address using the EL1&0
220 * translation regime, including stage 2.
221 */
222 AT(ats12e1r, ep);
223 }
224 isb();
225 par = read_par_el1();
226
227 /* Restore original SCRL_EL3 */
228 write_scr_el3(scr_el3);
229 isb();
230
231 /* If the translation resulted in fault, return failure */
232 if ((par & PAR_F_MASK) != 0)
233 return -1;
234
235 /* Extract Physical Address from PAR */
236 pa = get_par_el1_pa(par);
237
238 /* Perform NS entry point validation on the physical address */
239 return arm_validate_ns_entrypoint(pa);
240 }
241 #endif
242
plat_get_addr_mmap(void)243 const mmap_region_t *plat_get_addr_mmap(void)
244 {
245 return plat_arm_mmap;
246 }
247
248 #if ENABLE_RME
arm_gpt_setup(void)249 void arm_gpt_setup(void)
250 {
251 /*
252 * It is to be noted that any Arm platform that reuses arm_gpt_setup
253 * must implement plat_arm_get_gpt_info within its platform code
254 */
255 const arm_gpt_info_t *arm_gpt_info =
256 plat_arm_get_gpt_info();
257
258 if (arm_gpt_info == NULL) {
259 ERROR("arm_gpt_info not initialized!!\n");
260 panic();
261 }
262
263 /* Initialize entire protected space to GPT_GPI_ANY. */
264 if (gpt_init_l0_tables(arm_gpt_info->pps, arm_gpt_info->l0_base,
265 arm_gpt_info->l0_size) < 0) {
266 ERROR("gpt_init_l0_tables() failed!\n");
267 panic();
268 }
269
270 /* Carve out defined PAS ranges. */
271 if (gpt_init_pas_l1_tables(arm_gpt_info->pgs,
272 arm_gpt_info->l1_base,
273 arm_gpt_info->l1_size,
274 arm_gpt_info->pas_region_base,
275 arm_gpt_info->pas_region_count) < 0) {
276 ERROR("gpt_init_pas_l1_tables() failed!\n");
277 panic();
278 }
279
280 INFO("Enabling Granule Protection Checks\n");
281 if (gpt_enable() < 0) {
282 ERROR("gpt_enable() failed!\n");
283 panic();
284 }
285 }
286 #endif /* ENABLE_RME */
287