1 /* 2 * Copyright (c) 2023, Aspeed Technology Inc. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <plat/common/common_def.h> 12 #include <platform_reg.h> 13 14 #define PLATFORM_STACK_SIZE UL(0x1000) 15 16 /* cpu topology */ 17 #define PLATFORM_SYSTEM_COUNT U(1) 18 #define PLATFORM_CLUSTER_COUNT U(1) 19 #define PLATFORM_CORE_PRIMARY U(0) 20 #define PLATFORM_CORE_COUNT_PER_CLUSTER U(4) 21 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 22 PLATFORM_CORE_COUNT_PER_CLUSTER) 23 24 /* power domain */ 25 #define PLAT_MAX_PWR_LVL U(1) 26 #define PLAT_NUM_PWR_DOMAINS U(5) 27 #define PLAT_MAX_RET_STATE U(1) 28 #define PLAT_MAX_OFF_STATE U(2) 29 30 /* cache line size */ 31 #define CACHE_WRITEBACK_SHIFT U(6) 32 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 33 34 /* translation tables */ 35 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 36) 36 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40) 37 #define MAX_XLAT_TABLES U(8) 38 #define MAX_MMAP_REGIONS U(32) 39 40 /* BL31 region */ 41 #define BL31_BASE ULL(0x430000000) 42 #define BL31_SIZE SZ_512K 43 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 44 45 /* BL32 region */ 46 #define BL32_BASE BL31_LIMIT 47 #define BL32_SIZE SZ_16M 48 #define BL32_LIMIT (BL32_BASE + BL32_SIZE) 49 50 /* console */ 51 #define CONSOLE_UART_BASE UART12_BASE 52 #define CONSOLE_UART_CLKIN_HZ U(1846153) 53 #define CONSOLE_UART_BAUDRATE U(115200) 54 55 /* CLK information */ 56 #define CLKIN_25M UL(25000000) 57 58 #define PLAT_CLK_GATE_NUM U(29) 59 #define PLAT_CLK_HPLL (PLAT_CLK_GATE_NUM + 5) 60 #define PLAT_CLK_DPLL (PLAT_CLK_GATE_NUM + 6) 61 #define PLAT_CLK_MPLL (PLAT_CLK_GATE_NUM + 7) 62 63 #endif /* PLATFORM_DEF_H */ 64