1 /* 2 * Copyright 2020-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef IMX_SEC_DEF_H 8 #define IMX_SEC_DEF_H 9 10 /* RDC MDA index */ 11 enum rdc_mda_idx { 12 RDC_MDA_A53 = 0, 13 RDC_MDA_M4 = 1, 14 RDC_MDA_PCIE_CTRL1 = 2, 15 RDC_MDA_SDMA3p = 3, 16 RDC_MDA_VPU_Decoders = 4, 17 RDC_MDA_LCDIF = 5, 18 RDC_MDA_CSI1 = 6, 19 RDC_MDA_SDMA3b = 7, 20 RDC_MDA_Coresight = 8, 21 RDC_MDA_DAP = 9, 22 RDC_MDA_CAAM = 10, 23 RDC_MDA_SDMA1p = 11, 24 RDC_MDA_SDMA1b = 12, 25 RDC_MDA_APBHDMA = 13, 26 RDC_MDA_NAND = 14, 27 RDC_MDA_uSDHC1 = 15, 28 RDC_MDA_uSDHC2 = 16, 29 RDC_MDA_uSDHC3 = 17, 30 RDC_MDA_GPU = 18, 31 RDC_MDA_USB1 = 19, 32 RDC_MDA_USB2 = 20, 33 RDC_MDA_TESTPORT = 21, 34 RDC_MDA_ENET1_TX = 22, 35 RDC_MDA_ENET1_RX = 23, 36 RDC_MDA_SDMA2p = 24, 37 RDC_MDA_SDMA2b = 24, 38 RDC_MDA_SDMA2_to_SPBA2 = 24, 39 RDC_MDA_SDMA3_to_SPBA2 = 25, 40 RDC_MDA_SDMA1_to_SPBA1 = 26, 41 }; 42 43 /* RDC Peripherals index */ 44 enum rdc_pdap_idx { 45 RDC_PDAP_GPIO2 = 1, 46 RDC_PDAP_GPIO3 = 2, 47 RDC_PDAP_GPIO4 = 3, 48 RDC_PDAP_GPIO5 = 4, 49 RDC_PDAP_ANA_TSENSOR = 6, 50 RDC_PDAP_ANA_OSC = 7, 51 RDC_PDAP_WDOG1 = 8, 52 RDC_PDAP_WDOG2 = 9, 53 RDC_PDAP_WDOG3 = 10, 54 RDC_PDAP_SDMA3 = 11, 55 RDC_PDAP_SDMA2 = 12, 56 RDC_PDAP_GPT1 = 13, 57 RDC_PDAP_GPT2 = 14, 58 RDC_PDAP_GPT3 = 15, 59 RDC_PDAP_ROMCP = 17, 60 RDC_PDAP_IOMUXC = 19, 61 RDC_PDAP_IOMUXC_GPR = 20, 62 RDC_PDAP_OCOTP_CTRL = 21, 63 RDC_PDAP_ANA_PLL = 22, 64 RDC_PDAP_SNVS_HP = 23, 65 RDC_PDAP_CCM = 24, 66 RDC_PDAP_SRC = 25, 67 RDC_PDAP_GPC = 26, 68 RDC_PDAP_SEMAPHORE1 = 27, 69 RDC_PDAP_SEMAPHORE2 = 28, 70 RDC_PDAP_RDC = 29, 71 RDC_PDAP_CSU = 30, 72 RDC_PDAP_LCDIF = 32, 73 RDC_PDAP_MIPI_DSI = 33, 74 RDC_PDAP_CSI = 34, 75 RDC_PDAP_MIPI_CSI = 35, 76 RDC_PDAP_USB1 = 36, 77 RDC_PDAP_PWM1 = 38, 78 RDC_PDAP_PWM2 = 39, 79 RDC_PDAP_PWM3 = 40, 80 RDC_PDAP_PWM4 = 41, 81 RDC_PDAP_System_Counter_RD = 42, 82 RDC_PDAP_System_Counter_CMP = 43, 83 RDC_PDAP_System_Counter_CTRL = 44, 84 RDC_PDAP_GPT6 = 46, 85 RDC_PDAP_GPT5 = 47, 86 RDC_PDAP_GPT4 = 48, 87 RDC_PDAP_TZASC = 56, 88 RDC_PDAP_USB2 = 59, 89 RDC_PDAP_PERFMON1 = 60, 90 RDC_PDAP_PERFMON2 = 61, 91 RDC_PDAP_PLATFORM_CTRL = 62, 92 RDC_PDAP_QoSC = 63, 93 RDC_PDAP_I2C1 = 66, 94 RDC_PDAP_I2C2 = 67, 95 RDC_PDAP_I2C3 = 68, 96 RDC_PDAP_I2C4 = 69, 97 RDC_PDAP_UART4 = 70, 98 RDC_PDAP_MU_A = 74, 99 RDC_PDAP_MU_B = 75, 100 RDC_PDAP_SEMAPHORE_HS = 76, 101 RDC_PDAP_SAI1 = 78, 102 RDC_PDAP_SAI2 = 79, 103 RDC_PDAP_SAI3 = 80, 104 RDC_PDAP_SAI5 = 82, 105 RDC_PDAP_SAI6 = 83, 106 RDC_PDAP_uSDHC1 = 84, 107 RDC_PDAP_uSDHC2 = 85, 108 RDC_PDAP_uSDHC3 = 86, 109 RDC_PDAP_PCIE_PHY1 = 88, 110 RDC_PDAP_SPBA2 = 90, 111 RDC_PDAP_QSPI = 91, 112 RDC_PDAP_SDMA1 = 93, 113 RDC_PDAP_ENET1 = 94, 114 RDC_PDAP_SPDIF1 = 97, 115 RDC_PDAP_eCSPI1 = 98, 116 RDC_PDAP_eCSPI2 = 99, 117 RDC_PDAP_eCSPI3 = 100, 118 RDC_PDAP_MICFIL = 101, 119 RDC_PDAP_UART1 = 102, 120 RDC_PDAP_UART3 = 104, 121 RDC_PDAP_UART2 = 105, 122 RDC_PDAP_SPDIF2 = 106, 123 RDC_PDAP_SPBA1 = 111, 124 RDC_PDAP_CAAM = 114, 125 }; 126 127 enum csu_csl_idx { 128 CSU_CSL_GPIO1 = 0, 129 CSU_CSL_GPIO2 = 1, 130 CSU_CSL_GPIO3 = 2, 131 CSU_CSL_GPIO4 = 3, 132 CSU_CSL_GPIO5 = 4, 133 CSU_CSL_ANA_TSENSOR = 6, 134 CSU_CSL_ANA_OSC = 7, 135 CSU_CSL_WDOG1 = 8, 136 CSU_CSL_WDOG2 = 9, 137 CSU_CSL_WDOG3 = 10, 138 CSU_CSL_SDMA2 = 12, 139 CSU_CSL_GPT1 = 13, 140 CSU_CSL_GPT2 = 14, 141 CSU_CSL_GPT3 = 15, 142 CSU_CSL_ROMCP = 17, 143 CSU_CSL_LCDIF = 18, 144 CSU_CSL_IOMUXC = 19, 145 CSU_CSL_IOMUXC_GPR = 20, 146 CSU_CSL_OCOTP_CTRL = 21, 147 CSU_CSL_ANA_PLL = 22, 148 CSU_CSL_SNVS_HP = 23, 149 CSU_CSL_CCM = 24, 150 CSU_CSL_SRC = 25, 151 CSU_CSL_GPC = 26, 152 CSU_CSL_SEMAPHORE1 = 27, 153 CSU_CSL_SEMAPHORE2 = 28, 154 CSU_CSL_RDC = 29, 155 CSU_CSL_CSU = 30, 156 CSU_CSL_DC_MST0 = 32, 157 CSU_CSL_DC_MST1 = 33, 158 CSU_CSL_DC_MST2 = 34, 159 CSU_CSL_DC_MST3 = 35, 160 CSU_CSL_PWM1 = 38, 161 CSU_CSL_PWM2 = 39, 162 CSU_CSL_PWM3 = 40, 163 CSU_CSL_PWM4 = 41, 164 CSU_CSL_System_Counter_RD = 42, 165 CSU_CSL_System_Counter_CMP = 43, 166 CSU_CSL_System_Counter_CTRL = 44, 167 CSU_CSL_GPT6 = 46, 168 CSU_CSL_GPT5 = 47, 169 CSU_CSL_GPT4 = 48, 170 CSU_CSL_TZASC = 56, 171 CSU_CSL_MTR = 59, 172 CSU_CSL_PERFMON1 = 60, 173 CSU_CSL_PERFMON2 = 61, 174 CSU_CSL_PLATFORM_CTRL = 62, 175 CSU_CSL_QoSC = 63, 176 CSU_CSL_MIPI_PHY = 64, 177 CSU_CSL_MIPI_DSI = 65, 178 CSU_CSL_I2C1 = 66, 179 CSU_CSL_I2C2 = 67, 180 CSU_CSL_I2C3 = 68, 181 CSU_CSL_I2C4 = 69, 182 CSU_CSL_UART4 = 70, 183 CSU_CSL_MIPI_CSI1 = 71, 184 CSU_CSL_MIPI_CSI_PHY1 = 72, 185 CSU_CSL_CSI1 = 73, 186 CSU_CSL_MU_A = 74, 187 CSU_CSL_MU_B = 75, 188 CSU_CSL_SEMAPHORE_HS = 76, 189 CSU_CSL_SAI1 = 78, 190 CSU_CSL_SAI6 = 80, 191 CSU_CSL_SAI5 = 81, 192 CSU_CSL_SAI4 = 82, 193 CSU_CSL_uSDHC1 = 84, 194 CSU_CSL_uSDHC2 = 85, 195 CSU_CSL_MIPI_CSI2 = 86, 196 CSU_CSL_MIPI_CSI_PHY2 = 87, 197 CSU_CSL_CSI2 = 88, 198 CSU_CSL_SPBA2 = 90, 199 CSU_CSL_QSPI = 91, 200 CSU_CSL_SDMA1 = 93, 201 CSU_CSL_ENET1 = 94, 202 CSU_CSL_SPDIF1 = 97, 203 CSU_CSL_eCSPI1 = 98, 204 CSU_CSL_eCSPI2 = 99, 205 CSU_CSL_eCSPI3 = 100, 206 CSU_CSL_UART1 = 102, 207 CSU_CSL_UART3 = 104, 208 CSU_CSL_UART2 = 105, 209 CSU_CSL_SPDIF2 = 106, 210 CSU_CSL_SAI2 = 107, 211 CSU_CSL_SAI3 = 108, 212 CSU_CSL_SPBA1 = 111, 213 CSU_CSL_CAAM = 114, 214 }; 215 216 enum csu_sa_idx { 217 CSU_SA_M4 = 1, 218 CSU_SA_SDMA1 = 2, 219 CSU_SA_PCIE_CTRL1 = 3, 220 CSU_SA_USB1 = 4, 221 CSU_SA_USB2 = 5, 222 CSU_SA_VPU = 6, 223 CSU_SA_GPU = 7, 224 CSU_SA_APBHDMA = 8, 225 CSU_SA_ENET = 9, 226 CSU_SA_USDHC1 = 10, 227 CSU_SA_USDHC2 = 11, 228 CSU_SA_USDHC3 = 12, 229 CSU_SA_HUGO = 13, 230 CSU_SA_DAP = 14, 231 CSU_SA_SDMA2 = 15, 232 CSU_SA_CAAM = 16, 233 CSU_SA_SDMA3 = 17, 234 CSU_SA_LCDIF = 18, 235 CSU_SA_CSI = 19, 236 }; 237 238 #endif /* IMX_SEC_DEF_H */ 239