1 /* 2 * Copyright 2020-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef PLATFORM_DEF_H 7 #define PLATFORM_DEF_H 8 9 #include <lib/utils_def.h> 10 #include <lib/xlat_tables/xlat_tables_v2.h> 11 #include <plat/common/common_def.h> 12 13 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 14 #define PLATFORM_LINKER_ARCH aarch64 15 16 #define PLATFORM_STACK_SIZE 0xB00 17 #define CACHE_WRITEBACK_GRANULE 64 18 19 #define PLAT_PRIMARY_CPU U(0x0) 20 #define PLATFORM_MAX_CPU_PER_CLUSTER U(4) 21 #define PLATFORM_CLUSTER_COUNT U(1) 22 #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 23 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 24 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 25 26 #define IMX_PWR_LVL0 MPIDR_AFFLVL0 27 #define IMX_PWR_LVL1 MPIDR_AFFLVL1 28 #define IMX_PWR_LVL2 MPIDR_AFFLVL2 29 30 #define PWR_DOMAIN_AT_MAX_LVL U(1) 31 #define PLAT_MAX_PWR_LVL U(2) 32 #define PLAT_MAX_OFF_STATE U(4) 33 #define PLAT_MAX_RET_STATE U(2) 34 35 #define PLAT_WAIT_RET_STATE U(1) 36 #define PLAT_STOP_OFF_STATE U(3) 37 38 #define PLAT_PRI_BITS U(3) 39 #define PLAT_SDEI_CRITICAL_PRI 0x10 40 #define PLAT_SDEI_NORMAL_PRI 0x20 41 #define PLAT_SDEI_SGI_PRIVATE U(9) 42 43 #define BL31_BASE U(0x960000) 44 #define BL31_SIZE SZ_128K 45 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 46 47 /* non-secure uboot base */ 48 #ifndef PLAT_NS_IMAGE_OFFSET 49 #define PLAT_NS_IMAGE_OFFSET U(0x40200000) 50 #endif 51 52 #define BL32_FDT_OVERLAY_ADDR (PLAT_NS_IMAGE_OFFSET + 0x3000000) 53 54 /* GICv3 base address */ 55 #define PLAT_GICD_BASE U(0x38800000) 56 #define PLAT_GICR_BASE U(0x38880000) 57 58 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 59 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 60 61 #define MAX_XLAT_TABLES 8 62 #define MAX_MMAP_REGIONS 16 63 64 #define HAB_RVT_BASE U(0x00000900) /* HAB_RVT for i.MX8MM */ 65 66 #define IMX_BOOT_UART_CLK_IN_HZ 24000000 /* Select 24MHz oscillator */ 67 #define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE 68 #define PLAT_CRASH_UART_CLK_IN_HZ 24000000 69 #define IMX_CONSOLE_BAUDRATE 115200 70 71 #define IMX_UART1_BASE U(0x30860000) 72 #define IMX_UART2_BASE U(0x30890000) 73 #define IMX_UART3_BASE U(0x30880000) 74 #define IMX_UART4_BASE U(0x30a60000) 75 76 #define IMX_AIPSTZ1 U(0x301f0000) 77 #define IMX_AIPSTZ2 U(0x305f0000) 78 #define IMX_AIPSTZ3 U(0x309f0000) 79 #define IMX_AIPSTZ4 U(0x32df0000) 80 81 #define IMX_AIPS_BASE U(0x30000000) 82 #define IMX_AIPS_SIZE U(0x3000000) 83 #define IMX_GPV_BASE U(0x32000000) 84 #define IMX_GPV_SIZE U(0x800000) 85 #define IMX_AIPS1_BASE U(0x30200000) 86 #define IMX_AIPS4_BASE U(0x32c00000) 87 #define IMX_ANAMIX_BASE U(0x30360000) 88 #define IMX_CCM_BASE U(0x30380000) 89 #define IMX_SRC_BASE U(0x30390000) 90 #define IMX_GPC_BASE U(0x303a0000) 91 #define IMX_RDC_BASE U(0x303d0000) 92 #define IMX_CSU_BASE U(0x303e0000) 93 #define IMX_WDOG_BASE U(0x30280000) 94 #define IMX_SNVS_BASE U(0x30370000) 95 #define IMX_NOC_BASE U(0x32700000) 96 #define IMX_TZASC_BASE U(0x32F80000) 97 #define IMX_IOMUX_GPR_BASE U(0x30340000) 98 #define IMX_CAAM_BASE U(0x30900000) 99 #define IMX_DDRC_BASE U(0x3d400000) 100 #define IMX_DDRPHY_BASE U(0x3c000000) 101 #define IMX_DDR_IPS_BASE U(0x3d000000) 102 #define IMX_DDR_IPS_SIZE U(0x1800000) 103 #define IMX_ROM_BASE U(0x0) 104 #define IMX_ROM_SIZE U(0x40000) 105 #define IMX_NS_OCRAM_BASE U(0x900000) 106 #define IMX_NS_OCRAM_SIZE U(0x60000) 107 #define IMX_CAAM_RAM_BASE U(0x100000) 108 #define IMX_CAAM_RAM_SIZE U(0x10000) 109 #define IMX_DRAM_BASE U(0x40000000) 110 #define IMX_DRAM_SIZE U(0xc0000000) 111 112 #define IMX_GIC_BASE PLAT_GICD_BASE 113 #define IMX_GIC_SIZE U(0x200000) 114 115 #define WDOG_WSR U(0x2) 116 #define WDOG_WCR_WDZST BIT(0) 117 #define WDOG_WCR_WDBG BIT(1) 118 #define WDOG_WCR_WDE BIT(2) 119 #define WDOG_WCR_WDT BIT(3) 120 #define WDOG_WCR_SRS BIT(4) 121 #define WDOG_WCR_WDA BIT(5) 122 #define WDOG_WCR_SRE BIT(6) 123 #define WDOG_WCR_WDW BIT(7) 124 125 #define SRC_A53RCR0 U(0x4) 126 #define SRC_A53RCR1 U(0x8) 127 #define SRC_OTG1PHY_SCR U(0x20) 128 #define SRC_GPR1_OFFSET U(0x74) 129 130 #define SNVS_LPCR U(0x38) 131 #define SNVS_LPCR_SRTC_ENV BIT(0) 132 #define SNVS_LPCR_DP_EN BIT(5) 133 #define SNVS_LPCR_TOP BIT(6) 134 135 #define IOMUXC_GPR10 U(0x28) 136 #define GPR_TZASC_EN BIT(0) 137 #define GPR_TZASC_EN_LOCK BIT(16) 138 139 #define ANAMIX_MISC_CTL U(0x124) 140 #define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50) 141 142 #define MAX_CSU_NUM U(64) 143 144 #define OCRAM_S_BASE U(0x00180000) 145 #define OCRAM_S_SIZE U(0x8000) 146 #define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE) 147 #define SAVED_DRAM_TIMING_BASE OCRAM_S_BASE 148 #define IMX_TCM_BASE U(0x7E0000) 149 #define IMX_TCM_SIZE U(0x40000) 150 151 #define COUNTER_FREQUENCY 8000000 /* 8MHz */ 152 153 #define GPV5_BASE_ADDR U(0x32500000) 154 #define FORCE_INCR_OFFSET U(0x4044) 155 #define FORCE_INCR_BIT_MASK U(0x2) 156 157 #define IMX_WDOG_B_RESET 158 159 #define GIC_MAP MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW) 160 #define AIPS_MAP MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW) /* AIPS map */ 161 #define OCRAM_S_MAP MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_DEVICE | MT_RW) /* OCRAM_S */ 162 #define DDRC_MAP MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW) /* DDRMIX */ 163 #define CAAM_RAM_MAP MAP_REGION_FLAT(IMX_CAAM_RAM_BASE, IMX_CAAM_RAM_SIZE, MT_MEMORY | MT_RW) /* CAMM RAM */ 164 #define NS_OCRAM_MAP MAP_REGION_FLAT(IMX_NS_OCRAM_BASE, IMX_NS_OCRAM_SIZE, MT_MEMORY | MT_RW) /* NS OCRAM */ 165 #define ROM_MAP MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO) /* ROM code */ 166 167 /* 168 * Note: DRAM region is mapped with entire size available and uses MT_RW 169 * attributes. 170 * See details in docs/plat/imx8m.rst "High Assurance Boot (HABv4)" section 171 * for explanation of this mapping scheme. 172 */ 173 #define DRAM_MAP MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS) /* DRAM */ 174 175 #endif /* platform_def.h */ 176