1 /*
2 * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
4 * Copyright (c) 2024, Altera Corporation. All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include <arch.h>
10 #include <arch_helpers.h>
11 #include <assert.h>
12 #include <common/bl_common.h>
13 #include <drivers/arm/gicv2.h>
14 #include <drivers/ti/uart/uart_16550.h>
15 #include <lib/mmio.h>
16 #include <lib/xlat_tables/xlat_tables.h>
17 #include <plat/common/platform.h>
18
19 #include "ccu/ncore_ccu.h"
20 #include "socfpga_mailbox.h"
21 #include "socfpga_private.h"
22 #include "socfpga_sip_svc.h"
23
24 /* Get non-secure SPSR for BL33. Zephyr and Linux */
25 uint32_t arm_get_spsr_for_bl33_entry(void);
26
27 static entry_point_info_t bl32_image_ep_info;
28 static entry_point_info_t bl33_image_ep_info;
29
bl31_plat_get_next_image_ep_info(uint32_t type)30 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
31 {
32 entry_point_info_t *next_image_info;
33
34 next_image_info = (type == NON_SECURE) ?
35 &bl33_image_ep_info : &bl32_image_ep_info;
36
37 /* None of the images on this platform can have 0x0 as the entrypoint */
38 if (next_image_info->pc)
39 return next_image_info;
40 else
41 return NULL;
42 }
43
setup_smmu_secure_context(void)44 void setup_smmu_secure_context(void)
45 {
46 /*
47 * Program SCR0 register (0xFA000000)
48 * to set SMCFCFG bit[21] to 0x1 which raise stream match conflict fault
49 * to set CLIENTPD bit[0] to 0x0 which enables SMMU for secure context
50 */
51 mmio_write_32(0xFA000000, 0x00200000);
52
53 /*
54 * Program SCR1 register (0xFA000004)
55 * to set NSNUMSMRGO bit[14:8] to 0x4 which stream mapping register
56 * for non-secure context and the rest will be secure context
57 * to set NSNUMCBO bit[5:0] to 0x4 which allocate context bank
58 * for non-secure context and the rest will be secure context
59 */
60 mmio_write_32(0xFA000004, 0x00000404);
61 }
62
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)63 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
64 u_register_t arg2, u_register_t arg3)
65 {
66 static console_t console;
67 mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY);
68 console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
69 PLAT_BAUDRATE, &console);
70 /*
71 * Check params passed from BL31 should not be NULL,
72 */
73 void *from_bl2 = (void *) arg0;
74
75 #if RESET_TO_BL31
76 /* There are no parameters from BL2 if BL31 is a reset vector */
77 assert(from_bl2 == NULL);
78 void *plat_params_from_bl2 = (void *) arg3;
79
80 assert(plat_params_from_bl2 == NULL);
81
82 /* Populate entry point information for BL33 */
83 SET_PARAM_HEAD(&bl33_image_ep_info,
84 PARAM_EP,
85 VERSION_1,
86 0);
87
88 # if ARM_LINUX_KERNEL_AS_BL33
89 /*
90 * According to the file ``Documentation/arm64/booting.txt`` of the
91 * Linux kernel tree, Linux expects the physical address of the device
92 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
93 * must be 0.
94 */
95 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
96 bl33_image_ep_info.args.arg1 = 0U;
97 bl33_image_ep_info.args.arg2 = 0U;
98 bl33_image_ep_info.args.arg3 = 0U;
99 # endif
100
101 #else /* RESET_TO_BL31 */
102 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
103 assert(params_from_bl2 != NULL);
104
105 /*
106 * Copy BL32 (if populated by BL31) and BL33 entry point information.
107 * They are stored in Secure RAM, in BL31's address space.
108 */
109 if (params_from_bl2->h.type == PARAM_BL_PARAMS &&
110 params_from_bl2->h.version >= VERSION_2) {
111 bl_params_node_t *bl_params = params_from_bl2->head;
112 while (bl_params) {
113 if (bl_params->image_id == BL33_IMAGE_ID)
114 bl33_image_ep_info = *bl_params->ep_info;
115 bl_params = bl_params->next_params_info;
116 }
117 } else {
118 struct socfpga_bl31_params *arg_from_bl2 =
119 (struct socfpga_bl31_params *) from_bl2;
120 assert(arg_from_bl2->h.type == PARAM_BL31);
121 assert(arg_from_bl2->h.version >= VERSION_1);
122 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
123 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
124 }
125
126 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
127 bl33_image_ep_info.args.arg1 = 0U;
128 bl33_image_ep_info.args.arg2 = 0U;
129 bl33_image_ep_info.args.arg3 = 0U;
130 #endif
131
132 /*
133 * Tell BL31 where the non-trusted software image
134 * is located and the entry state information
135 */
136 # if ARM_LINUX_KERNEL_AS_BL33
137 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
138 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
139 #endif
140
141 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
142 }
143
144 static const interrupt_prop_t s10_interrupt_props[] = {
145 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
146 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
147 };
148
149 static unsigned int target_mask_array[PLATFORM_CORE_COUNT];
150
151 static const gicv2_driver_data_t plat_gicv2_gic_data = {
152 .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE,
153 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE,
154 .interrupt_props = s10_interrupt_props,
155 .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props),
156 .target_masks = target_mask_array,
157 .target_masks_num = ARRAY_SIZE(target_mask_array),
158 };
159
160 /*******************************************************************************
161 * Perform any BL3-1 platform setup code
162 ******************************************************************************/
bl31_platform_setup(void)163 void bl31_platform_setup(void)
164 {
165 socfpga_delay_timer_init();
166
167 /* Initialize the gic cpu and distributor interfaces */
168 gicv2_driver_init(&plat_gicv2_gic_data);
169 gicv2_distif_init();
170 gicv2_pcpu_distif_init();
171 gicv2_cpuif_enable();
172 setup_smmu_secure_context();
173
174 /* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */
175 mmio_write_64(PLAT_CPU_RELEASE_ADDR,
176 (uint64_t)plat_secondary_cpus_bl31_entry);
177
178 mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
179 }
180
181 const mmap_region_t plat_agilex_mmap[] = {
182 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
183 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS),
184 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
185 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
186 MT_NON_CACHEABLE | MT_RW | MT_SECURE),
187 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
188 MT_DEVICE | MT_RW | MT_SECURE),
189 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS),
190 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS),
191 {0}
192 };
193
194 /*******************************************************************************
195 * Perform the very early platform specific architectural setup here. At the
196 * moment this is only initializes the mmu in a quick and dirty way.
197 ******************************************************************************/
bl31_plat_arch_setup(void)198 void bl31_plat_arch_setup(void)
199 {
200 const mmap_region_t bl_regions[] = {
201 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
202 MT_MEMORY | MT_RW | MT_SECURE),
203 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
204 MT_CODE | MT_SECURE),
205 MAP_REGION_FLAT(BL_RO_DATA_BASE,
206 BL_RO_DATA_END - BL_RO_DATA_BASE,
207 MT_RO_DATA | MT_SECURE),
208 #if USE_COHERENT_MEM
209 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
210 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
211 MT_DEVICE | MT_RW | MT_SECURE),
212 #endif
213 {0}
214 };
215 setup_page_tables(bl_regions, plat_agilex_mmap);
216 enable_mmu_el3(0);
217 }
218
219 /* Get non-secure image entrypoint for BL33. Zephyr and Linux */
plat_get_ns_image_entrypoint(void)220 uintptr_t plat_get_ns_image_entrypoint(void)
221 {
222 #ifdef PRELOADED_BL33_BASE
223 return PRELOADED_BL33_BASE;
224 #else
225 return PLAT_NS_IMAGE_OFFSET;
226 #endif
227 }
228
229 /* Get non-secure SPSR for BL33. Zephyr and Linux */
arm_get_spsr_for_bl33_entry(void)230 uint32_t arm_get_spsr_for_bl33_entry(void)
231 {
232 unsigned int mode;
233 uint32_t spsr;
234
235 /* Figure out what mode we enter the non-secure world in */
236 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
237
238 /*
239 * TODO: Consider the possibility of specifying the SPSR in
240 * the FIP ToC and allowing the platform to have a say as
241 * well.
242 */
243 spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
244 return spsr;
245 }
246