1 /* 2 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef AGX_PINMUX_H 8 #define AGX_PINMUX_H 9 10 #define AGX_PINMUX_BASE 0xffd13000 11 #define AGX_PINMUX_PIN0SEL (AGX_PINMUX_BASE + 0x000) 12 #define AGX_PINMUX_IO0CTRL (AGX_PINMUX_BASE + 0x130) 13 #define AGX_PINMUX_EMAC0_USEFPGA (AGX_PINMUX_BASE + 0x300) 14 #define AGX_PINMUX_EMAC1_USEFPGA (AGX_PINMUX_BASE + 0x304) 15 #define AGX_PINMUX_EMAC2_USEFPGA (AGX_PINMUX_BASE + 0x308) 16 #define AGX_PINMUX_NAND_USEFPGA (AGX_PINMUX_BASE + 0x320) 17 #define AGX_PINMUX_SPIM0_USEFPGA (AGX_PINMUX_BASE + 0x328) 18 #define AGX_PINMUX_SPIM1_USEFPGA (AGX_PINMUX_BASE + 0x32c) 19 #define AGX_PINMUX_SDMMC_USEFPGA (AGX_PINMUX_BASE + 0x354) 20 #define AGX_PINMUX_IO0_DELAY (AGX_PINMUX_BASE + 0x400) 21 22 #define AGX_PINMUX_NAND_USEFPGA_VAL BIT(4) 23 #define AGX_PINMUX_SDMMC_USEFPGA_VAL BIT(8) 24 #define AGX_PINMUX_SPIM0_USEFPGA_VAL BIT(16) 25 #define AGX_PINMUX_SPIM1_USEFPGA_VAL BIT(24) 26 #define AGX_PINMUX_EMAC0_USEFPGA_VAL BIT(0) 27 #define AGX_PINMUX_EMAC1_USEFPGA_VAL BIT(8) 28 #define AGX_PINMUX_EMAC2_USEFPGA_VAL BIT(16) 29 30 #include "socfpga_handoff.h" 31 32 void config_pinmux(handoff *handoff); 33 34 #endif 35 36