1 /* 2 * Copyright (c) 2024, Altera Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef AGILEX5_IOSSM_MAILBOX_H 8 #define AGILEX5_IOSSM_MAILBOX_H 9 10 #include <stdbool.h> 11 #include <stdint.h> 12 #include <stdlib.h> 13 14 #include "lib/mmio.h" 15 #include "agilex5_ddr.h" 16 17 #define TIMEOUT_5000MS 5000 18 #define TIMEOUT TIMEOUT_5000MS 19 #define IOSSM_STATUS_CAL_SUCCESS BIT(0) 20 #define IOSSM_STATUS_CAL_FAIL BIT(1) 21 #define IOSSM_STATUS_CAL_BUSY BIT(2) 22 #define IOSSM_STATUS_COMMAND_RESPONSE_READY 1 23 #define IOSSM_CMD_RESPONSE_STATUS_OFFSET 0x45C 24 #define IOSSM_CMD_RESPONSE_DATA_0_OFFSET 0x458 25 #define IOSSM_CMD_RESPONSE_DATA_1_OFFSET 0x454 26 #define IOSSM_CMD_RESPONSE_DATA_2_OFFSET 0x450 27 #define IOSSM_CMD_REQ_OFFSET 0x43C 28 #define IOSSM_CMD_PARAM_0_OFFSET 0x438 29 #define IOSSM_CMD_PARAM_1_OFFSET 0x434 30 #define IOSSM_CMD_PARAM_2_OFFSET 0x430 31 #define IOSSM_CMD_PARAM_3_OFFSET 0x42C 32 #define IOSSM_CMD_PARAM_4_OFFSET 0x428 33 #define IOSSM_CMD_PARAM_5_OFFSET 0x424 34 #define IOSSM_CMD_PARAM_6_OFFSET 0x420 35 #define IOSSM_STATUS_OFFSET 0x400 36 #define IOSSM_CMD_RESPONSE_DATA_SHORT_MASK GENMASK(31, 16) 37 #define IOSSM_CMD_RESPONSE_DATA_SHORT(data) (((data) & \ 38 IOSSM_CMD_RESPONSE_DATA_SHORT_MASK) >> 16) 39 #define MAX_IO96B_SUPPORTED 2 40 #define MAX_MEM_INTERFACES_SUPPORTED 2 41 42 /* supported mailbox command type */ 43 enum iossm_mailbox_cmd_type { 44 CMD_NOP, 45 CMD_GET_SYS_INFO, 46 CMD_GET_MEM_INFO, 47 CMD_GET_MEM_CAL_INFO, 48 CMD_TRIG_CONTROLLER_OP, 49 CMD_TRIG_MEM_CAL_OP 50 }; 51 52 /* supported mailbox command opcode */ 53 enum iossm_mailbox_cmd_opcode { 54 GET_MEM_INTF_INFO = 0x0001, 55 GET_MEM_TECHNOLOGY, 56 GET_MEMCLK_FREQ_KHZ, 57 GET_MEM_WIDTH_INFO, 58 ECC_ENABLE_SET = 0x0101, 59 ECC_ENABLE_STATUS, 60 ECC_INTERRUPT_STATUS, 61 ECC_INTERRUPT_ACK, 62 ECC_INTERRUPT_MASK, 63 ECC_WRITEBACK_ENABLE, 64 ECC_SCRUB_IN_PROGRESS_STATUS = 0x0201, 65 ECC_SCRUB_MODE_0_START, 66 ECC_SCRUB_MODE_1_START, 67 BIST_STANDARD_MODE_START = 0x0301, 68 BIST_RESULTS_STATUS, 69 BIST_MEM_INIT_START, 70 BIST_MEM_INIT_STATUS, 71 BIST_SET_DATA_PATTERN_UPPER, 72 BIST_SET_DATA_PATTERN_LOWER, 73 TRIG_MEM_CAL = 0x000a, 74 GET_MEM_CAL_STATUS 75 }; 76 77 /* 78 * IOSSM mailbox required information 79 * 80 * @num_mem_interface: Number of memory interfaces instantiated 81 * @ip_type: IP type implemented on the IO96B 82 * @ip_instance_id: IP identifier for every IP instance implemented on the IO96B 83 */ 84 struct io96b_mb_ctrl { 85 uint32_t num_mem_interface; 86 uint32_t ip_type[2]; 87 uint32_t ip_instance_id[2]; 88 }; 89 90 /* 91 * IOSSM mailbox response outputs 92 * 93 * @cmd_resp_status: Command Interface status 94 * @cmd_resp_data_*: More spaces for command response 95 */ 96 struct io96b_mb_resp { 97 uint32_t cmd_resp_status; 98 uint32_t cmd_resp_data_0; 99 uint32_t cmd_resp_data_1; 100 uint32_t cmd_resp_data_2; 101 }; 102 103 /* 104 * IO96B instance specific information 105 * 106 * @size: Memory size 107 * @io96b_csr_addr: IO96B instance CSR address 108 * @cal_status: IO96B instance calibration status 109 * @mb_ctrl: IOSSM mailbox required information 110 */ 111 struct io96b_instance { 112 uint16_t size; 113 phys_addr_t io96b_csr_addr; 114 bool cal_status; 115 struct io96b_mb_ctrl mb_ctrl; 116 }; 117 118 /* 119 * Overall IO96B instance(s) information 120 * 121 * @num_instance: Number of instance(s) assigned to HPS 122 * @overall_cal_status: Overall calibration status for all IO96B instance(s) 123 * @ddr_type: DDR memory type 124 * @ecc_status: ECC enable status (false = disabled, true = enabled) 125 * @overall_size: Total DDR memory size 126 * @io96b_0: IO96B 0 instance specific information 127 * @io96b_1: IO96B 1 instance specific information 128 */ 129 struct io96b_info { 130 uint8_t num_instance; 131 bool overall_cal_status; 132 const char *ddr_type; 133 bool ecc_status; 134 uint16_t overall_size; 135 struct io96b_instance io96b_0; 136 struct io96b_instance io96b_1; 137 }; 138 139 int io96b_mb_req(phys_addr_t io96b_csr_addr, uint32_t ip_type, uint32_t instance_id, 140 uint32_t usr_cmd_type, uint32_t usr_cmd_opcode, uint32_t cmd_param_0, 141 uint32_t cmd_param_1, uint32_t cmd_param_2, uint32_t cmd_param_3, 142 uint32_t cmd_param_4, uint32_t cmd_param_5, uint32_t cmd_param_6, 143 uint32_t resp_data_len, struct io96b_mb_resp *resp); 144 145 /* Supported IOSSM mailbox function */ 146 void io96b_mb_init(struct io96b_info *io96b_ctrl); 147 int io96b_cal_status(phys_addr_t addr); 148 void init_mem_cal(struct io96b_info *io96b_ctrl); 149 int trig_mem_cal(struct io96b_info *io96b_ctrl); 150 int get_mem_technology(struct io96b_info *io96b_ctrl); 151 int get_mem_width_info(struct io96b_info *io96b_ctrl); 152 int ecc_enable_status(struct io96b_info *io96b_ctrl); 153 int bist_mem_init_start(struct io96b_info *io96b_ctrl); 154 155 #endif /* AGILEX5_IOSSM_MAILBOX_H */ 156