1 /*
2 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
3 * Copyright (c) 2024, Altera Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <lib/mmio.h>
9
10 #include "agilex5_pinmux.h"
11 #include "agilex5_system_manager.h"
12
13 const uint32_t sysmgr_pinmux_array_sel[] = {
14 0x00000000, 0x00000001, /* usb */
15 0x00000004, 0x00000001,
16 0x00000008, 0x00000001,
17 0x0000000c, 0x00000001,
18 0x00000010, 0x00000001,
19 0x00000014, 0x00000001,
20 0x00000018, 0x00000001,
21 0x0000001c, 0x00000001,
22 0x00000020, 0x00000001,
23 0x00000024, 0x00000001,
24 0x00000028, 0x00000001,
25 0x0000002c, 0x00000001,
26 0x00000030, 0x00000000, /* emac0 */
27 0x00000034, 0x00000000,
28 0x00000038, 0x00000000,
29 0x0000003c, 0x00000000,
30 0x00000040, 0x00000000,
31 0x00000044, 0x00000000,
32 0x00000048, 0x00000000,
33 0x0000004c, 0x00000000,
34 0x00000050, 0x00000000,
35 0x00000054, 0x00000000,
36 0x00000058, 0x00000000,
37 0x0000005c, 0x00000000,
38 0x00000060, 0x00000008, /* gpio1 */
39 0x00000064, 0x00000008,
40 0x00000068, 0x00000005, /* uart0 tx */
41 0x0000006c, 0x00000005, /* uart 0 rx */
42 0x00000070, 0x00000008, /* gpio */
43 0x00000074, 0x00000008,
44 0x00000078, 0x00000004, /* i2c1 */
45 0x0000007c, 0x00000004,
46 0x00000080, 0x00000007, /* jtag */
47 0x00000084, 0x00000007,
48 0x00000088, 0x00000007,
49 0x0000008c, 0x00000007,
50 0x00000090, 0x00000001, /* sdmmc data0 */
51 0x00000094, 0x00000001,
52 0x00000098, 0x00000001,
53 0x0000009c, 0x00000001,
54 0x00000100, 0x00000001,
55 0x00000104, 0x00000001, /* sdmmc.data3 */
56 0x00000108, 0x00000008, /* loan */
57 0x0000010c, 0x00000008, /* gpio */
58 0x00000110, 0x00000008,
59 0x00000114, 0x00000008, /* gpio1.io21 */
60 0x00000118, 0x00000005, /* mdio0.mdio */
61 0x0000011c, 0x00000005 /* mdio0.mdc */
62 };
63
64 const uint32_t sysmgr_pinmux_array_ctrl[] = {
65 0x00000000, 0x00502c38, /* Q1_1 */
66 0x00000004, 0x00102c38,
67 0x00000008, 0x00502c38,
68 0x0000000c, 0x00502c38,
69 0x00000010, 0x00502c38,
70 0x00000014, 0x00502c38,
71 0x00000018, 0x00502c38,
72 0x0000001c, 0x00502c38,
73 0x00000020, 0x00502c38,
74 0x00000024, 0x00502c38,
75 0x00000028, 0x00502c38,
76 0x0000002c, 0x00502c38,
77 0x00000030, 0x00102c38, /* Q2_1 */
78 0x00000034, 0x00102c38,
79 0x00000038, 0x00502c38,
80 0x0000003c, 0x00502c38,
81 0x00000040, 0x00102c38,
82 0x00000044, 0x00102c38,
83 0x00000048, 0x00502c38,
84 0x0000004c, 0x00502c38,
85 0x00000050, 0x00102c38,
86 0x00000054, 0x00102c38,
87 0x00000058, 0x00502c38,
88 0x0000005c, 0x00502c38,
89 0x00000060, 0x00502c38, /* Q3_1 */
90 0x00000064, 0x00502c38,
91 0x00000068, 0x00102c38,
92 0x0000006c, 0x00502c38,
93 0x000000d0, 0x00502c38,
94 0x000000d4, 0x00502c38,
95 0x000000d8, 0x00542c38,
96 0x000000dc, 0x00542c38,
97 0x000000e0, 0x00502c38,
98 0x000000e4, 0x00502c38,
99 0x000000e8, 0x00102c38,
100 0x000000ec, 0x00502c38,
101 0x000000f0, 0x00502c38, /* Q4_1 */
102 0x000000f4, 0x00502c38,
103 0x000000f8, 0x00102c38,
104 0x000000fc, 0x00502c38,
105 0x00000100, 0x00502c38,
106 0x00000104, 0x00502c38,
107 0x00000108, 0x00102c38,
108 0x0000010c, 0x00502c38,
109 0x00000110, 0x00502c38,
110 0x00000114, 0x00502c38,
111 0x00000118, 0x00542c38,
112 0x0000011c, 0x00102c38
113 };
114
115 const uint32_t sysmgr_pinmux_array_fpga[] = {
116 0x00000000, 0x00000000,
117 0x00000004, 0x00000000,
118 0x00000008, 0x00000000,
119 0x0000000c, 0x00000000,
120 0x00000010, 0x00000000,
121 0x00000014, 0x00000000,
122 0x00000018, 0x00000000,
123 0x0000001c, 0x00000000,
124 0x00000020, 0x00000000,
125 0x00000028, 0x00000000,
126 0x0000002c, 0x00000000,
127 0x00000030, 0x00000000,
128 0x00000034, 0x00000000,
129 0x00000038, 0x00000000,
130 0x0000003c, 0x00000000,
131 0x00000040, 0x00000000,
132 0x00000044, 0x00000000,
133 0x00000048, 0x00000000,
134 0x00000050, 0x00000000,
135 0x00000054, 0x00000000,
136 0x00000058, 0x0000002a
137 };
138
139 const uint32_t sysmgr_pinmux_array_iodelay[] = {
140 0x00000000, 0x00000000,
141 0x00000004, 0x00000000,
142 0x00000008, 0x00000000,
143 0x0000000c, 0x00000000,
144 0x00000010, 0x00000000,
145 0x00000014, 0x00000000,
146 0x00000018, 0x00000000,
147 0x0000001c, 0x00000000,
148 0x00000020, 0x00000000,
149 0x00000024, 0x00000000,
150 0x00000028, 0x00000000,
151 0x0000002c, 0x00000000,
152 0x00000030, 0x00000000,
153 0x00000034, 0x00000000,
154 0x00000038, 0x00000000,
155 0x0000003c, 0x00000000,
156 0x00000040, 0x00000000,
157 0x00000044, 0x00000000,
158 0x00000048, 0x00000000,
159 0x0000004c, 0x00000000,
160 0x00000050, 0x00000000,
161 0x00000054, 0x00000000,
162 0x00000058, 0x00000000,
163 0x0000005c, 0x00000000,
164 0x00000060, 0x00000000,
165 0x00000064, 0x00000000,
166 0x00000068, 0x00000000,
167 0x0000006c, 0x00000000,
168 0x00000070, 0x00000000,
169 0x00000074, 0x00000000,
170 0x00000078, 0x00000000,
171 0x0000007c, 0x00000000,
172 0x00000080, 0x00000000,
173 0x00000084, 0x00000000,
174 0x00000088, 0x00000000,
175 0x0000008c, 0x00000000,
176 0x00000090, 0x00000000,
177 0x00000094, 0x00000000,
178 0x00000098, 0x00000000,
179 0x0000009c, 0x00000000,
180 0x00000100, 0x00000000,
181 0x00000104, 0x00000000,
182 0x00000108, 0x00000000,
183 0x0000010c, 0x00000000,
184 0x00000110, 0x00000000,
185 0x00000114, 0x00000000,
186 0x00000118, 0x00000000,
187 0x0000011c, 0x00000000
188 };
189
config_fpgaintf_mod(void)190 static void config_fpgaintf_mod(void)
191 {
192 uint32_t fpgaintf_en_val;
193
194 /*
195 * System manager FPGA interface enable2 register, disable individual
196 * interfaces between the FPGA and HPS.
197 */
198 fpgaintf_en_val = 0U;
199 if ((mmio_read_32(SOCFPGA_PINUMX_USEFPGA(NAND_USEFPGA)) & 0x01) != 0)
200 fpgaintf_en_val |= BIT(4);
201 if ((mmio_read_32(SOCFPGA_PINUMX_USEFPGA(SDMMC_USEFPGA)) & 0x01) != 0)
202 fpgaintf_en_val |= BIT(8);
203 if ((mmio_read_32(SOCFPGA_PINUMX_USEFPGA(SPIM0_USEFPGA)) & 0x01) != 0)
204 fpgaintf_en_val |= BIT(16);
205 if ((mmio_read_32(SOCFPGA_PINUMX_USEFPGA(SPIM1_USEFPGA)) & 0x01) != 0)
206 fpgaintf_en_val |= BIT(24);
207 mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_2), fpgaintf_en_val);
208
209 /*
210 * System manager FPGA interface enable3 register, disable individual
211 * interfaces between the FPGA and HPS.
212 */
213 fpgaintf_en_val = 0U;
214 if ((mmio_read_32(SOCFPGA_PINUMX_USEFPGA(EMAC0_USEFPGA)) & 0x01) != 0)
215 fpgaintf_en_val |= BIT(0);
216 if ((mmio_read_32(SOCFPGA_PINUMX_USEFPGA(EMAC1_USEFPGA)) & 0x01) != 0)
217 fpgaintf_en_val |= BIT(8);
218 if ((mmio_read_32(SOCFPGA_PINUMX_USEFPGA(EMAC2_USEFPGA)) & 0x01) != 0)
219 fpgaintf_en_val |= BIT(16);
220 mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_3), fpgaintf_en_val);
221 }
222
config_pinmux(handoff * hoff_ptr)223 void config_pinmux(handoff *hoff_ptr)
224 {
225 uint32_t i;
226
227 /* Configure the pin selection */
228 for (i = 0; i < ARRAY_SIZE(hoff_ptr->pinmux_sel_array); i += 2) {
229 mmio_write_32(AGX5_PINMUX_PIN0SEL + hoff_ptr->pinmux_sel_array[i],
230 hoff_ptr->pinmux_sel_array[i+1]);
231 }
232
233 /* Configure the pin control */
234 for (i = 0; i < ARRAY_SIZE(hoff_ptr->pinmux_io_array); i += 2) {
235 mmio_write_32(AGX5_PINMUX_IO0CTRL + hoff_ptr->pinmux_io_array[i],
236 hoff_ptr->pinmux_io_array[i+1]);
237 }
238
239 /*
240 * Configure the FPGA use.
241 * The actual generic handoff contains extra 4 elements, and these 4 elements
242 * are not applicable to the Agilex5 platform. Writing these extra 4 elements
243 * will cause the system to crash, so let's avoid writing them here.
244 */
245 for (i = 0; i < (ARRAY_SIZE(hoff_ptr->pinmux_fpga_array) - 4); i += 2) {
246 mmio_write_32(AGX5_PINMUX_EMAC0_USEFPGA + hoff_ptr->pinmux_fpga_array[i],
247 hoff_ptr->pinmux_fpga_array[i+1]);
248 }
249
250 /* Configure the IO delay */
251 for (i = 0; i < ARRAY_SIZE(hoff_ptr->pinmux_iodelay_array); i += 2) {
252 mmio_write_32(AGX5_PINMUX_IO0_DELAY + hoff_ptr->pinmux_iodelay_array[i],
253 hoff_ptr->pinmux_iodelay_array[i+1]);
254 }
255
256 /* Enable/Disable individual interfaces between the FPGA and HPS */
257 config_fpgaintf_mod();
258 }
259