1 /* 2 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 3 * Copyright (c) 2024, Altera Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SOCFPGA_SYSTEMMANAGER_H 9 #define SOCFPGA_SYSTEMMANAGER_H 10 11 #include "socfpga_plat_def.h" 12 13 /* System Manager Register Map */ 14 15 #define SOCFPGA_SYSMGR_SDMMC 0x28 16 17 /* Field Masking */ 18 #define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0) 19 #define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4) 20 21 #define IDLE_DATA_LWSOC2FPGA BIT(4) 22 #define IDLE_DATA_SOC2FPGA BIT(0) 23 #define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA) 24 25 #define SYSMGR_QSPI_REFCLK_MASK GENMASK(27, 0) 26 27 #define SYSMGR_ECC_OCRAM_MASK BIT(1) 28 #define SYSMGR_ECC_DDR0_MASK BIT(16) 29 #define SYSMGR_ECC_DDR1_MASK BIT(17) 30 31 /* Macros */ 32 33 #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ 34 + (SOCFPGA_SYSMGR_##_reg)) 35 36 /* Function Prototype */ 37 uint32_t intel_hps_get_jtag_id(void); 38 bool is_agilex5_A5F0(void); 39 40 #endif /* SOCFPGA_SYSTEMMANAGER_H */ 41