1 /*
2 * Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2020-2023, NVIDIA Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9 #include <errno.h>
10 #include <inttypes.h>
11 #include <stddef.h>
12 #include <string.h>
13
14 #include <platform_def.h>
15
16 #include <arch.h>
17 #include <arch_helpers.h>
18 #include <bl31/bl31.h>
19 #include <common/bl_common.h>
20 #include <common/debug.h>
21 #include <cortex_a57.h>
22 #include <denver.h>
23 #include <drivers/console.h>
24 #include <lib/mmio.h>
25 #include <lib/utils.h>
26 #include <lib/utils_def.h>
27 #include <plat/common/platform.h>
28
29 #include <memctrl.h>
30 #include <profiler.h>
31 #include <smmu.h>
32 #include <tegra_def.h>
33 #include <tegra_platform.h>
34 #include <tegra_private.h>
35 #ifdef SPD_trusty
36 #include <trusty/plat/boot_args.h>
37 #endif
38
39 /* length of Trusty's input parameters (in bytes) */
40 #define TRUSTY_PARAMS_LEN_BYTES (4096*2)
41
42 /*******************************************************************************
43 * Declarations of linker defined symbols which will help us find the layout
44 * of trusted SRAM
45 ******************************************************************************/
46 IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START);
47
48 extern uint64_t tegra_bl31_phys_base;
49
50 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
51 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
52 .tzdram_size = TZDRAM_SIZE
53 };
54 #ifdef SPD_trusty
55 static aapcs64_params_t bl32_args;
56 #endif
57
58 /*******************************************************************************
59 * This variable holds the non-secure image entry address
60 ******************************************************************************/
61 extern uint64_t ns_image_entrypoint;
62
63 /*******************************************************************************
64 * Return a pointer to the 'entry_point_info' structure of the next image for
65 * security state specified. BL33 corresponds to the non-secure image type
66 * while BL32 corresponds to the secure image type.
67 ******************************************************************************/
bl31_plat_get_next_image_ep_info(uint32_t type)68 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
69 {
70 entry_point_info_t *ep = NULL;
71
72 /* return BL32 entry point info if it is valid */
73 if (type == NON_SECURE) {
74 ep = &bl33_image_ep_info;
75 } else if ((type == SECURE) && (bl32_image_ep_info.pc != 0U)) {
76 ep = &bl32_image_ep_info;
77 }
78
79 return ep;
80 }
81
82 /*******************************************************************************
83 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image
84 * passes this platform specific information.
85 ******************************************************************************/
bl31_get_plat_params(void)86 plat_params_from_bl2_t *bl31_get_plat_params(void)
87 {
88 return &plat_bl31_params_from_bl2;
89 }
90
91 /*******************************************************************************
92 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image
93 * info.
94 ******************************************************************************/
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)95 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
96 u_register_t arg2, u_register_t arg3)
97 {
98 struct tegra_bl31_params *arg_from_bl2 = plat_get_bl31_params();
99 plat_params_from_bl2_t *plat_params = plat_get_bl31_plat_params();
100 int32_t ret;
101
102 /*
103 * Tegra platforms will receive boot parameters through custom
104 * mechanisms. So, we ignore the input parameters.
105 */
106 (void)arg0;
107 (void)arg1;
108
109 /*
110 * Copy BL3-3, BL3-2 entry point information.
111 * They are stored in Secure RAM, in BL2's address space.
112 */
113 assert(arg_from_bl2 != NULL);
114 assert(arg_from_bl2->bl33_ep_info != NULL);
115 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
116
117 if (arg_from_bl2->bl32_ep_info != NULL) {
118 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
119 #ifdef SPD_trusty
120 /* save BL32 boot parameters */
121 memcpy(&bl32_args, &arg_from_bl2->bl32_ep_info->args, sizeof(bl32_args));
122 #endif
123 }
124
125 /*
126 * Parse platform specific parameters
127 */
128 assert(plat_params != NULL);
129 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
130 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
131 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
132 plat_bl31_params_from_bl2.l2_ecc_parity_prot_dis = plat_params->l2_ecc_parity_prot_dis;
133 plat_bl31_params_from_bl2.sc7entry_fw_size = plat_params->sc7entry_fw_size;
134 plat_bl31_params_from_bl2.sc7entry_fw_base = plat_params->sc7entry_fw_base;
135
136 /*
137 * It is very important that we run either from TZDRAM or TZSRAM base.
138 * Add an explicit check here.
139 */
140 if ((plat_bl31_params_from_bl2.tzdram_base != (uint64_t)BL31_BASE) &&
141 (TEGRA_TZRAM_BASE != BL31_BASE)) {
142 panic();
143 }
144
145 /*
146 * Enable console for the platform
147 */
148 plat_enable_console(plat_params->uart_id);
149
150 /*
151 * The previous bootloader passes the base address of the shared memory
152 * location to store the boot profiler logs. Sanity check the
153 * address and initialise the profiler library, if it looks ok.
154 */
155 ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base,
156 PROFILER_SIZE_BYTES);
157 if (ret == (int32_t)0) {
158
159 /* store the membase for the profiler lib */
160 plat_bl31_params_from_bl2.boot_profiler_shmem_base =
161 plat_params->boot_profiler_shmem_base;
162
163 /* initialise the profiler library */
164 boot_profiler_init(plat_params->boot_profiler_shmem_base,
165 TEGRA_TMRUS_BASE);
166 }
167
168 /*
169 * Add timestamp for platform early setup entry.
170 */
171 boot_profiler_add_record("[TF] early setup entry");
172
173 /*
174 * Initialize delay timer
175 */
176 tegra_delay_timer_init();
177
178 /* Early platform setup for Tegra SoCs */
179 plat_early_platform_setup();
180
181 /*
182 * Add timestamp for platform early setup exit.
183 */
184 boot_profiler_add_record("[TF] early setup exit");
185
186 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n",
187 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK)
188 == DENVER_IMPL) ? "Denver" : "ARM", read_mpidr());
189 }
190
191 #ifdef SPD_trusty
plat_trusty_set_boot_args(aapcs64_params_t * args)192 void plat_trusty_set_boot_args(aapcs64_params_t *args)
193 {
194 /*
195 * arg0 = TZDRAM aperture available for BL32
196 * arg1 = BL32 boot params
197 * arg2 = EKS Blob Length
198 * arg3 = Boot Profiler Carveout Base
199 */
200 args->arg0 = bl32_args.arg0;
201 args->arg1 = bl32_args.arg2;
202
203 /* update EKS size */
204 args->arg2 = bl32_args.arg4;
205
206 /* Profiler Carveout Base */
207 args->arg3 = bl32_args.arg5;
208 }
209 #endif
210
211 /*******************************************************************************
212 * Initialize the gic, configure the SCR.
213 ******************************************************************************/
bl31_platform_setup(void)214 void bl31_platform_setup(void)
215 {
216 /*
217 * Add timestamp for platform setup entry.
218 */
219 boot_profiler_add_record("[TF] plat setup entry");
220
221 /* Initialize the gic cpu and distributor interfaces */
222 plat_gic_setup();
223
224 /*
225 * Setup secondary CPU POR infrastructure.
226 */
227 plat_secondary_setup();
228
229 /*
230 * Initial Memory Controller configuration.
231 */
232 tegra_memctrl_setup();
233
234 /*
235 * Late setup handler to allow platforms to performs additional
236 * functionality.
237 * This handler gets called with MMU enabled.
238 */
239 plat_late_platform_setup();
240
241 /*
242 * Add timestamp for platform setup exit.
243 */
244 boot_profiler_add_record("[TF] plat setup exit");
245
246 INFO("BL3-1: Tegra platform setup complete\n");
247 }
248
249 /*******************************************************************************
250 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit
251 ******************************************************************************/
bl31_plat_runtime_setup(void)252 void bl31_plat_runtime_setup(void)
253 {
254 /*
255 * Platform specific runtime setup
256 */
257 plat_runtime_setup();
258
259 /*
260 * Add final timestamp before exiting BL31.
261 */
262 boot_profiler_add_record("[TF] bl31 exit");
263 boot_profiler_deinit();
264 }
265
266 /*******************************************************************************
267 * Perform the very early platform specific architectural setup here. At the
268 * moment this only initializes the mmu in a quick and dirty way.
269 ******************************************************************************/
bl31_plat_arch_setup(void)270 void bl31_plat_arch_setup(void)
271 {
272 uint64_t rw_start = BL31_RW_START;
273 uint64_t rw_size = BL_END - BL31_RW_START;
274 uint64_t rodata_start = BL_RO_DATA_BASE;
275 uint64_t rodata_size = BL_RO_DATA_END - BL_RO_DATA_BASE;
276 uint64_t code_base = BL_CODE_BASE;
277 uint64_t code_size = BL_CODE_END - BL_CODE_BASE;
278 const mmap_region_t *plat_mmio_map = NULL;
279 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
280
281 /*
282 * Add timestamp for arch setup entry.
283 */
284 boot_profiler_add_record("[TF] arch setup entry");
285
286 /* add MMIO space */
287 plat_mmio_map = plat_get_mmio_map();
288 if (plat_mmio_map != NULL) {
289 mmap_add(plat_mmio_map);
290 } else {
291 WARN("MMIO map not available\n");
292 }
293
294 /* add memory regions */
295 mmap_add_region(rw_start, rw_start,
296 rw_size,
297 MT_MEMORY | MT_RW | MT_SECURE);
298 mmap_add_region(rodata_start, rodata_start,
299 rodata_size,
300 MT_RO_DATA | MT_SECURE);
301 mmap_add_region(code_base, code_base,
302 code_size,
303 MT_CODE | MT_SECURE);
304
305 /* map TZDRAM used by BL31 as coherent memory */
306 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
307 mmap_add_region(params_from_bl2->tzdram_base,
308 params_from_bl2->tzdram_base,
309 BL31_SIZE,
310 MT_DEVICE | MT_RW | MT_SECURE);
311 }
312
313 /* set up translation tables */
314 init_xlat_tables();
315
316 /* enable the MMU */
317 enable_mmu_el3(0);
318
319 /*
320 * Add timestamp for arch setup exit.
321 */
322 boot_profiler_add_record("[TF] arch setup exit");
323
324 INFO("BL3-1: Tegra: MMU enabled\n");
325 }
326
327 /*******************************************************************************
328 * Check if the given NS DRAM range is valid
329 ******************************************************************************/
bl31_check_ns_address(uint64_t base,uint64_t size_in_bytes)330 int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
331 {
332 uint64_t end = base + size_in_bytes - U(1);
333
334 /*
335 * Sanity check the input values
336 */
337 if ((base == 0U) || (size_in_bytes == 0U)) {
338 ERROR("NS address 0x%" PRIx64 " (%" PRId64 " bytes) is invalid\n",
339 base, size_in_bytes);
340 return -EINVAL;
341 }
342
343 /*
344 * Check if the NS DRAM address is valid
345 */
346 if ((base < TEGRA_DRAM_BASE) || (base >= TEGRA_DRAM_END) ||
347 (end > TEGRA_DRAM_END)) {
348
349 ERROR("NS address 0x%" PRIx64 " is out-of-bounds!\n", base);
350 return -EFAULT;
351 }
352
353 /*
354 * TZDRAM aperture contains the BL31 and BL32 images, so we need
355 * to check if the NS DRAM range overlaps the TZDRAM aperture.
356 */
357 if ((base < (uint64_t)TZDRAM_END) && (end > tegra_bl31_phys_base)) {
358 ERROR("NS address 0x%" PRIx64 " overlaps TZDRAM!\n", base);
359 return -ENOTSUP;
360 }
361
362 /* valid NS address */
363 return 0;
364 }
365